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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.76 98.25 93.97 97.02 93.02 96.37 99.77 91.89


Total test records in report: 1129
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T1020 /workspace/coverage/cover_reg_top/42.edn_intr_test.2908938140 Jun 11 01:49:41 PM PDT 24 Jun 11 01:49:43 PM PDT 24 53150092 ps
T264 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.649585441 Jun 11 01:49:06 PM PDT 24 Jun 11 01:49:09 PM PDT 24 108710308 ps
T1021 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1532082720 Jun 11 01:49:11 PM PDT 24 Jun 11 01:49:18 PM PDT 24 732185166 ps
T1022 /workspace/coverage/cover_reg_top/9.edn_intr_test.144558427 Jun 11 01:49:12 PM PDT 24 Jun 11 01:49:16 PM PDT 24 25773092 ps
T1023 /workspace/coverage/cover_reg_top/7.edn_tl_errors.87141815 Jun 11 01:49:17 PM PDT 24 Jun 11 01:49:20 PM PDT 24 23445771 ps
T283 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2862926983 Jun 11 01:49:36 PM PDT 24 Jun 11 01:49:38 PM PDT 24 19744672 ps
T1024 /workspace/coverage/cover_reg_top/10.edn_tl_errors.744396001 Jun 11 01:49:15 PM PDT 24 Jun 11 01:49:20 PM PDT 24 107869502 ps
T265 /workspace/coverage/cover_reg_top/11.edn_csr_rw.4083618502 Jun 11 01:49:13 PM PDT 24 Jun 11 01:49:17 PM PDT 24 15474800 ps
T284 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1843670518 Jun 11 01:49:16 PM PDT 24 Jun 11 01:49:19 PM PDT 24 20094572 ps
T1025 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2285314256 Jun 11 01:49:27 PM PDT 24 Jun 11 01:49:34 PM PDT 24 143763590 ps
T1026 /workspace/coverage/cover_reg_top/10.edn_intr_test.3967177405 Jun 11 01:49:08 PM PDT 24 Jun 11 01:49:11 PM PDT 24 38840788 ps
T1027 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4242665248 Jun 11 01:49:06 PM PDT 24 Jun 11 01:49:10 PM PDT 24 65667900 ps
T1028 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.863378726 Jun 11 01:49:06 PM PDT 24 Jun 11 01:49:08 PM PDT 24 17894966 ps
T1029 /workspace/coverage/cover_reg_top/20.edn_intr_test.4227440960 Jun 11 01:49:24 PM PDT 24 Jun 11 01:49:27 PM PDT 24 15306150 ps
T266 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3689473790 Jun 11 01:49:08 PM PDT 24 Jun 11 01:49:11 PM PDT 24 14060737 ps
T1030 /workspace/coverage/cover_reg_top/36.edn_intr_test.2690760994 Jun 11 01:49:37 PM PDT 24 Jun 11 01:49:40 PM PDT 24 114940859 ps
T267 /workspace/coverage/cover_reg_top/15.edn_csr_rw.126186573 Jun 11 01:49:23 PM PDT 24 Jun 11 01:49:26 PM PDT 24 200566167 ps
T1031 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1999197126 Jun 11 01:49:06 PM PDT 24 Jun 11 01:49:09 PM PDT 24 42998785 ps
T1032 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3550003201 Jun 11 01:49:11 PM PDT 24 Jun 11 01:49:17 PM PDT 24 184503091 ps
T1033 /workspace/coverage/cover_reg_top/30.edn_intr_test.1500751213 Jun 11 01:49:26 PM PDT 24 Jun 11 01:49:29 PM PDT 24 45073210 ps
T1034 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1963061101 Jun 11 01:49:21 PM PDT 24 Jun 11 01:49:24 PM PDT 24 56035730 ps
T1035 /workspace/coverage/cover_reg_top/45.edn_intr_test.2437487743 Jun 11 01:49:35 PM PDT 24 Jun 11 01:49:37 PM PDT 24 73729833 ps
T1036 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.991082304 Jun 11 01:49:10 PM PDT 24 Jun 11 01:49:15 PM PDT 24 85280418 ps
T1037 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3194725132 Jun 11 01:49:19 PM PDT 24 Jun 11 01:49:22 PM PDT 24 26916489 ps
T1038 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1394425559 Jun 11 01:49:19 PM PDT 24 Jun 11 01:49:24 PM PDT 24 196148657 ps
T1039 /workspace/coverage/cover_reg_top/48.edn_intr_test.3634570667 Jun 11 01:49:37 PM PDT 24 Jun 11 01:49:39 PM PDT 24 12018797 ps
T268 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.320468747 Jun 11 01:49:13 PM PDT 24 Jun 11 01:49:17 PM PDT 24 27236580 ps
T297 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2661530435 Jun 11 01:49:07 PM PDT 24 Jun 11 01:49:11 PM PDT 24 149752634 ps
T1040 /workspace/coverage/cover_reg_top/0.edn_tl_errors.4196626414 Jun 11 01:49:09 PM PDT 24 Jun 11 01:49:14 PM PDT 24 300442037 ps
T1041 /workspace/coverage/cover_reg_top/5.edn_csr_rw.755072922 Jun 11 01:49:05 PM PDT 24 Jun 11 01:49:07 PM PDT 24 50839194 ps
T299 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1002052316 Jun 11 01:49:42 PM PDT 24 Jun 11 01:49:46 PM PDT 24 286198976 ps
T298 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1721266452 Jun 11 01:49:11 PM PDT 24 Jun 11 01:49:17 PM PDT 24 305292794 ps
T1042 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2477297498 Jun 11 01:49:09 PM PDT 24 Jun 11 01:49:17 PM PDT 24 358142189 ps
T1043 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2162274665 Jun 11 01:49:10 PM PDT 24 Jun 11 01:49:13 PM PDT 24 32325044 ps
T301 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2076632855 Jun 11 01:49:23 PM PDT 24 Jun 11 01:49:26 PM PDT 24 126112379 ps
T1044 /workspace/coverage/cover_reg_top/4.edn_csr_rw.521410761 Jun 11 01:49:12 PM PDT 24 Jun 11 01:49:16 PM PDT 24 14666574 ps
T1045 /workspace/coverage/cover_reg_top/34.edn_intr_test.1063502092 Jun 11 01:49:28 PM PDT 24 Jun 11 01:49:32 PM PDT 24 13459894 ps
T1046 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3765781329 Jun 11 01:49:21 PM PDT 24 Jun 11 01:49:24 PM PDT 24 20759419 ps
T300 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1727967493 Jun 11 01:49:24 PM PDT 24 Jun 11 01:49:28 PM PDT 24 674805648 ps
T1047 /workspace/coverage/cover_reg_top/19.edn_intr_test.1522674526 Jun 11 01:49:22 PM PDT 24 Jun 11 01:49:25 PM PDT 24 85577100 ps
T1048 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2295042228 Jun 11 01:49:07 PM PDT 24 Jun 11 01:49:10 PM PDT 24 34291022 ps
T1049 /workspace/coverage/cover_reg_top/11.edn_intr_test.2109319250 Jun 11 01:49:12 PM PDT 24 Jun 11 01:49:16 PM PDT 24 73059386 ps
T1050 /workspace/coverage/cover_reg_top/26.edn_intr_test.2577491392 Jun 11 01:49:26 PM PDT 24 Jun 11 01:49:29 PM PDT 24 118314986 ps
T1051 /workspace/coverage/cover_reg_top/14.edn_intr_test.2768116113 Jun 11 01:49:22 PM PDT 24 Jun 11 01:49:24 PM PDT 24 14338280 ps
T1052 /workspace/coverage/cover_reg_top/2.edn_intr_test.3792740442 Jun 11 01:49:09 PM PDT 24 Jun 11 01:49:12 PM PDT 24 20011421 ps
T1053 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1087622013 Jun 11 01:49:13 PM PDT 24 Jun 11 01:49:19 PM PDT 24 139132714 ps
T1054 /workspace/coverage/cover_reg_top/17.edn_intr_test.1812153170 Jun 11 01:49:21 PM PDT 24 Jun 11 01:49:23 PM PDT 24 40264909 ps
T1055 /workspace/coverage/cover_reg_top/29.edn_intr_test.2799284941 Jun 11 01:49:23 PM PDT 24 Jun 11 01:49:25 PM PDT 24 11764889 ps
T1056 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2311926164 Jun 11 01:49:26 PM PDT 24 Jun 11 01:49:30 PM PDT 24 110657354 ps
T1057 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1392934356 Jun 11 01:49:22 PM PDT 24 Jun 11 01:49:26 PM PDT 24 223506338 ps
T1058 /workspace/coverage/cover_reg_top/37.edn_intr_test.2881982623 Jun 11 01:49:37 PM PDT 24 Jun 11 01:49:39 PM PDT 24 40713687 ps
T1059 /workspace/coverage/cover_reg_top/27.edn_intr_test.2246465573 Jun 11 01:49:27 PM PDT 24 Jun 11 01:49:30 PM PDT 24 12105947 ps
T1060 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2127869328 Jun 11 01:49:18 PM PDT 24 Jun 11 01:49:26 PM PDT 24 97854979 ps
T1061 /workspace/coverage/cover_reg_top/12.edn_intr_test.2430003882 Jun 11 01:49:18 PM PDT 24 Jun 11 01:49:20 PM PDT 24 44696757 ps
T1062 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1382844251 Jun 11 01:49:23 PM PDT 24 Jun 11 01:49:26 PM PDT 24 45258163 ps
T1063 /workspace/coverage/cover_reg_top/24.edn_intr_test.411832382 Jun 11 01:49:21 PM PDT 24 Jun 11 01:49:23 PM PDT 24 56782668 ps
T269 /workspace/coverage/cover_reg_top/8.edn_csr_rw.748645200 Jun 11 01:49:10 PM PDT 24 Jun 11 01:49:13 PM PDT 24 113010793 ps
T1064 /workspace/coverage/cover_reg_top/39.edn_intr_test.2506584156 Jun 11 01:49:19 PM PDT 24 Jun 11 01:49:21 PM PDT 24 13221604 ps
T1065 /workspace/coverage/cover_reg_top/3.edn_intr_test.1004442548 Jun 11 01:49:09 PM PDT 24 Jun 11 01:49:12 PM PDT 24 91640639 ps
T1066 /workspace/coverage/cover_reg_top/43.edn_intr_test.1472717746 Jun 11 01:49:24 PM PDT 24 Jun 11 01:49:27 PM PDT 24 13428285 ps
T1067 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2284118588 Jun 11 01:49:12 PM PDT 24 Jun 11 01:49:17 PM PDT 24 199662169 ps
T1068 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.231119825 Jun 11 01:49:27 PM PDT 24 Jun 11 01:49:31 PM PDT 24 31071748 ps
T1069 /workspace/coverage/cover_reg_top/7.edn_csr_rw.886447800 Jun 11 01:49:12 PM PDT 24 Jun 11 01:49:16 PM PDT 24 81450456 ps
T1070 /workspace/coverage/cover_reg_top/8.edn_intr_test.3750247933 Jun 11 01:49:12 PM PDT 24 Jun 11 01:49:16 PM PDT 24 25524146 ps
T1071 /workspace/coverage/cover_reg_top/8.edn_tl_errors.4259581460 Jun 11 01:49:09 PM PDT 24 Jun 11 01:49:14 PM PDT 24 272015253 ps
T1072 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1648292488 Jun 11 01:49:33 PM PDT 24 Jun 11 01:49:36 PM PDT 24 267750155 ps
T1073 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3029529807 Jun 11 01:49:15 PM PDT 24 Jun 11 01:49:25 PM PDT 24 439268609 ps
T1074 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3033924250 Jun 11 01:49:06 PM PDT 24 Jun 11 01:49:10 PM PDT 24 184937982 ps
T1075 /workspace/coverage/cover_reg_top/3.edn_tl_errors.709173249 Jun 11 01:49:06 PM PDT 24 Jun 11 01:49:12 PM PDT 24 125486862 ps
T1076 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.794674860 Jun 11 01:49:13 PM PDT 24 Jun 11 01:49:17 PM PDT 24 70715298 ps
T1077 /workspace/coverage/cover_reg_top/40.edn_intr_test.2242897486 Jun 11 01:49:39 PM PDT 24 Jun 11 01:49:41 PM PDT 24 27229465 ps
T1078 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2642822075 Jun 11 01:49:21 PM PDT 24 Jun 11 01:49:24 PM PDT 24 41456256 ps
T1079 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1066789787 Jun 11 01:49:20 PM PDT 24 Jun 11 01:49:22 PM PDT 24 32684810 ps
T1080 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2173395524 Jun 11 01:49:12 PM PDT 24 Jun 11 01:49:16 PM PDT 24 81570023 ps
T1081 /workspace/coverage/cover_reg_top/0.edn_intr_test.3547601106 Jun 11 01:49:07 PM PDT 24 Jun 11 01:49:10 PM PDT 24 12207502 ps
T1082 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1874252273 Jun 11 01:49:08 PM PDT 24 Jun 11 01:49:11 PM PDT 24 35660619 ps
T1083 /workspace/coverage/cover_reg_top/13.edn_csr_rw.663976866 Jun 11 01:49:17 PM PDT 24 Jun 11 01:49:20 PM PDT 24 15380689 ps
T1084 /workspace/coverage/cover_reg_top/25.edn_intr_test.1259630706 Jun 11 01:49:20 PM PDT 24 Jun 11 01:49:22 PM PDT 24 23172218 ps
T1085 /workspace/coverage/cover_reg_top/1.edn_tl_errors.565361084 Jun 11 01:49:08 PM PDT 24 Jun 11 01:49:14 PM PDT 24 206156298 ps
T1086 /workspace/coverage/cover_reg_top/5.edn_intr_test.3850971794 Jun 11 01:49:09 PM PDT 24 Jun 11 01:49:13 PM PDT 24 42226508 ps
T1087 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.474653123 Jun 11 01:49:13 PM PDT 24 Jun 11 01:49:17 PM PDT 24 154439246 ps
T1088 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3091473667 Jun 11 01:49:12 PM PDT 24 Jun 11 01:49:16 PM PDT 24 14171894 ps
T1089 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4131654858 Jun 11 01:49:25 PM PDT 24 Jun 11 01:49:28 PM PDT 24 16834396 ps
T1090 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.269269250 Jun 11 01:49:11 PM PDT 24 Jun 11 01:49:15 PM PDT 24 49090665 ps
T1091 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2459119336 Jun 11 01:49:18 PM PDT 24 Jun 11 01:49:20 PM PDT 24 43187594 ps
T1092 /workspace/coverage/cover_reg_top/15.edn_intr_test.3127789618 Jun 11 01:49:22 PM PDT 24 Jun 11 01:49:24 PM PDT 24 125735047 ps
T1093 /workspace/coverage/cover_reg_top/2.edn_csr_rw.943654131 Jun 11 01:49:08 PM PDT 24 Jun 11 01:49:10 PM PDT 24 14744246 ps
T1094 /workspace/coverage/cover_reg_top/9.edn_csr_rw.126614126 Jun 11 01:49:11 PM PDT 24 Jun 11 01:49:15 PM PDT 24 16995462 ps
T1095 /workspace/coverage/cover_reg_top/1.edn_intr_test.312922819 Jun 11 01:49:07 PM PDT 24 Jun 11 01:49:10 PM PDT 24 22944514 ps
T1096 /workspace/coverage/cover_reg_top/13.edn_intr_test.1080516039 Jun 11 01:49:17 PM PDT 24 Jun 11 01:49:20 PM PDT 24 37614134 ps
T1097 /workspace/coverage/cover_reg_top/6.edn_intr_test.3483986408 Jun 11 01:49:07 PM PDT 24 Jun 11 01:49:10 PM PDT 24 23909096 ps
T1098 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1610311328 Jun 11 01:49:29 PM PDT 24 Jun 11 01:49:33 PM PDT 24 70372679 ps
T1099 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.4226303061 Jun 11 01:49:17 PM PDT 24 Jun 11 01:49:20 PM PDT 24 50336344 ps
T1100 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2786846875 Jun 11 01:49:09 PM PDT 24 Jun 11 01:49:12 PM PDT 24 138609559 ps
T1101 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.313575368 Jun 11 01:49:07 PM PDT 24 Jun 11 01:49:10 PM PDT 24 40201193 ps
T1102 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2243122383 Jun 11 01:49:08 PM PDT 24 Jun 11 01:49:12 PM PDT 24 386316798 ps
T1103 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3337312240 Jun 11 01:49:13 PM PDT 24 Jun 11 01:49:18 PM PDT 24 60752455 ps
T1104 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2423588107 Jun 11 01:49:07 PM PDT 24 Jun 11 01:49:10 PM PDT 24 42593408 ps
T1105 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2579714579 Jun 11 01:49:05 PM PDT 24 Jun 11 01:49:08 PM PDT 24 83912679 ps
T1106 /workspace/coverage/cover_reg_top/32.edn_intr_test.433911190 Jun 11 01:49:40 PM PDT 24 Jun 11 01:49:42 PM PDT 24 17578884 ps
T1107 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3953340753 Jun 11 01:49:24 PM PDT 24 Jun 11 01:49:28 PM PDT 24 95729658 ps
T1108 /workspace/coverage/cover_reg_top/41.edn_intr_test.3887975836 Jun 11 01:49:25 PM PDT 24 Jun 11 01:49:28 PM PDT 24 35785663 ps
T1109 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.994153084 Jun 11 01:49:19 PM PDT 24 Jun 11 01:49:28 PM PDT 24 236131834 ps
T1110 /workspace/coverage/cover_reg_top/0.edn_csr_rw.479183614 Jun 11 01:49:06 PM PDT 24 Jun 11 01:49:09 PM PDT 24 22057169 ps
T1111 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2218533953 Jun 11 01:49:28 PM PDT 24 Jun 11 01:49:34 PM PDT 24 98066888 ps
T270 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3884743780 Jun 11 01:49:07 PM PDT 24 Jun 11 01:49:09 PM PDT 24 24454006 ps
T1112 /workspace/coverage/cover_reg_top/19.edn_tl_errors.728595918 Jun 11 01:49:21 PM PDT 24 Jun 11 01:49:26 PM PDT 24 782514254 ps
T1113 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.658040125 Jun 11 01:49:10 PM PDT 24 Jun 11 01:49:14 PM PDT 24 35808119 ps
T1114 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3792882814 Jun 11 01:49:05 PM PDT 24 Jun 11 01:49:08 PM PDT 24 51929895 ps
T1115 /workspace/coverage/cover_reg_top/16.edn_intr_test.3990152048 Jun 11 01:49:21 PM PDT 24 Jun 11 01:49:23 PM PDT 24 38657173 ps
T1116 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.468591137 Jun 11 01:49:08 PM PDT 24 Jun 11 01:49:11 PM PDT 24 117461625 ps
T271 /workspace/coverage/cover_reg_top/6.edn_csr_rw.47448147 Jun 11 01:49:17 PM PDT 24 Jun 11 01:49:19 PM PDT 24 36855140 ps
T1117 /workspace/coverage/cover_reg_top/23.edn_intr_test.1943319851 Jun 11 01:49:22 PM PDT 24 Jun 11 01:49:24 PM PDT 24 17971559 ps
T272 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3944417323 Jun 11 01:49:09 PM PDT 24 Jun 11 01:49:13 PM PDT 24 124594273 ps
T273 /workspace/coverage/cover_reg_top/16.edn_csr_rw.2627040864 Jun 11 01:49:21 PM PDT 24 Jun 11 01:49:23 PM PDT 24 29108714 ps
T1118 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3161289773 Jun 11 01:49:20 PM PDT 24 Jun 11 01:49:22 PM PDT 24 22847536 ps
T1119 /workspace/coverage/cover_reg_top/31.edn_intr_test.937981999 Jun 11 01:49:42 PM PDT 24 Jun 11 01:49:44 PM PDT 24 34778368 ps
T1120 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.496051102 Jun 11 01:49:11 PM PDT 24 Jun 11 01:49:16 PM PDT 24 46705087 ps
T1121 /workspace/coverage/cover_reg_top/18.edn_intr_test.1890407385 Jun 11 01:49:19 PM PDT 24 Jun 11 01:49:21 PM PDT 24 25232639 ps
T1122 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1371440532 Jun 11 01:49:40 PM PDT 24 Jun 11 01:49:43 PM PDT 24 24014304 ps
T1123 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1034028711 Jun 11 01:49:22 PM PDT 24 Jun 11 01:49:25 PM PDT 24 16137160 ps
T1124 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.561198139 Jun 11 01:49:12 PM PDT 24 Jun 11 01:49:17 PM PDT 24 32151102 ps
T1125 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4160672298 Jun 11 01:49:24 PM PDT 24 Jun 11 01:49:26 PM PDT 24 54187312 ps
T1126 /workspace/coverage/cover_reg_top/35.edn_intr_test.4006501626 Jun 11 01:49:26 PM PDT 24 Jun 11 01:49:29 PM PDT 24 45728937 ps
T274 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2335170278 Jun 11 01:49:12 PM PDT 24 Jun 11 01:49:16 PM PDT 24 59000606 ps
T1127 /workspace/coverage/cover_reg_top/4.edn_tl_errors.4005397571 Jun 11 01:49:13 PM PDT 24 Jun 11 01:49:19 PM PDT 24 93187859 ps
T1128 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.982523614 Jun 11 01:49:36 PM PDT 24 Jun 11 01:49:38 PM PDT 24 459626438 ps
T1129 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1293142203 Jun 11 01:49:05 PM PDT 24 Jun 11 01:49:09 PM PDT 24 96695374 ps
T275 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1737984178 Jun 11 01:49:20 PM PDT 24 Jun 11 01:49:22 PM PDT 24 11496815 ps

Test location /workspace/coverage/default/109.edn_genbits.2926043426
Short name T7
Test name
Test status
Simulation time 37656343 ps
CPU time 1.31 seconds
Started Jun 11 02:21:54 PM PDT 24
Finished Jun 11 02:21:56 PM PDT 24
Peak memory 220288 kb
Host smart-cac64d42-4401-4b93-a497-86280298748d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926043426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2926043426
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2143842557
Short name T38
Test name
Test status
Simulation time 27757992584 ps
CPU time 604.96 seconds
Started Jun 11 02:18:21 PM PDT 24
Finished Jun 11 02:28:27 PM PDT 24
Peak memory 218304 kb
Host smart-a3f28e5c-85c3-499a-b7ba-310c97085d23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143842557 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2143842557
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.edn_alert.2065424177
Short name T81
Test name
Test status
Simulation time 73323916 ps
CPU time 1.17 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:20:59 PM PDT 24
Peak memory 220500 kb
Host smart-05e04a5d-c972-4cae-b1c5-d30aee7ab8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065424177 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.2065424177
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2628370856
Short name T13
Test name
Test status
Simulation time 3387280754 ps
CPU time 8.46 seconds
Started Jun 11 02:18:11 PM PDT 24
Finished Jun 11 02:18:20 PM PDT 24
Peak memory 238092 kb
Host smart-cf03b30e-6db5-45c7-9300-d0c5fbe56b0e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628370856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2628370856
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/22.edn_err.925861070
Short name T5
Test name
Test status
Simulation time 26261040 ps
CPU time 1.33 seconds
Started Jun 11 02:19:36 PM PDT 24
Finished Jun 11 02:19:39 PM PDT 24
Peak memory 229644 kb
Host smart-b76f7491-b388-4e7a-8fd1-4b5ff08e74cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925861070 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.925861070
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/19.edn_disable.3906639292
Short name T84
Test name
Test status
Simulation time 48432237 ps
CPU time 0.87 seconds
Started Jun 11 02:19:27 PM PDT 24
Finished Jun 11 02:19:29 PM PDT 24
Peak memory 216472 kb
Host smart-d52e5599-875c-4431-afa9-fc042e678db3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906639292 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3906639292
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/175.edn_alert.4099773482
Short name T1
Test name
Test status
Simulation time 34475434 ps
CPU time 1.27 seconds
Started Jun 11 02:22:17 PM PDT 24
Finished Jun 11 02:22:19 PM PDT 24
Peak memory 218928 kb
Host smart-fed3a462-5e91-4744-b3d1-b2c4c84e400c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099773482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.4099773482
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/2.edn_regwen.1926534061
Short name T25
Test name
Test status
Simulation time 98481755 ps
CPU time 0.96 seconds
Started Jun 11 02:18:15 PM PDT 24
Finished Jun 11 02:18:17 PM PDT 24
Peak memory 207384 kb
Host smart-59d3eba6-ab2c-4036-af6b-4e52d1f5461e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926534061 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1926534061
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/98.edn_alert.369856472
Short name T162
Test name
Test status
Simulation time 30367878 ps
CPU time 1.35 seconds
Started Jun 11 02:21:44 PM PDT 24
Finished Jun 11 02:21:47 PM PDT 24
Peak memory 215816 kb
Host smart-02d52e1c-ef4d-4abc-b61d-5810c05a0e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369856472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.369856472
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.4030897436
Short name T153
Test name
Test status
Simulation time 35043623 ps
CPU time 1.26 seconds
Started Jun 11 02:20:40 PM PDT 24
Finished Jun 11 02:20:42 PM PDT 24
Peak memory 217020 kb
Host smart-1dc13739-d970-4ae9-b926-ac8694b6d5ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030897436 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.4030897436
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/287.edn_genbits.498391931
Short name T17
Test name
Test status
Simulation time 414415567 ps
CPU time 4.63 seconds
Started Jun 11 02:22:49 PM PDT 24
Finished Jun 11 02:22:55 PM PDT 24
Peak memory 217708 kb
Host smart-1f27cba6-5dde-4f9b-86b0-f3af3f2d2d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498391931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.498391931
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_alert.3991605671
Short name T86
Test name
Test status
Simulation time 35080401 ps
CPU time 1.19 seconds
Started Jun 11 02:20:04 PM PDT 24
Finished Jun 11 02:20:08 PM PDT 24
Peak memory 219720 kb
Host smart-35db3af2-407a-49d5-a19d-a60d511a619c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991605671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3991605671
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1727967493
Short name T300
Test name
Test status
Simulation time 674805648 ps
CPU time 2.3 seconds
Started Jun 11 01:49:24 PM PDT 24
Finished Jun 11 01:49:28 PM PDT 24
Peak memory 206724 kb
Host smart-f3f5b2f1-abf4-4639-ac94-e1f860830e4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727967493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1727967493
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/default/76.edn_alert.1345670387
Short name T223
Test name
Test status
Simulation time 363987954 ps
CPU time 1.41 seconds
Started Jun 11 02:21:16 PM PDT 24
Finished Jun 11 02:21:19 PM PDT 24
Peak memory 220964 kb
Host smart-802eb2b9-1907-4f0f-a9f0-6b23c4e0d8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345670387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.1345670387
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.4083618502
Short name T265
Test name
Test status
Simulation time 15474800 ps
CPU time 0.93 seconds
Started Jun 11 01:49:13 PM PDT 24
Finished Jun 11 01:49:17 PM PDT 24
Peak memory 206604 kb
Host smart-8bdccc46-ac45-41de-bd9f-5fd143bc78d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083618502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.4083618502
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/default/6.edn_disable.3548489445
Short name T217
Test name
Test status
Simulation time 39710723 ps
CPU time 0.92 seconds
Started Jun 11 02:18:45 PM PDT 24
Finished Jun 11 02:18:48 PM PDT 24
Peak memory 216636 kb
Host smart-50ff2300-2cc8-4418-a453-815782d32c77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548489445 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3548489445
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/159.edn_alert.3943581842
Short name T356
Test name
Test status
Simulation time 50268773 ps
CPU time 1.22 seconds
Started Jun 11 02:22:03 PM PDT 24
Finished Jun 11 02:22:05 PM PDT 24
Peak memory 220824 kb
Host smart-3187d2c7-2722-4d7d-9398-bd8116ca04b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943581842 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.3943581842
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.99064575
Short name T205
Test name
Test status
Simulation time 41608136 ps
CPU time 0.9 seconds
Started Jun 11 02:19:07 PM PDT 24
Finished Jun 11 02:19:09 PM PDT 24
Peak memory 215660 kb
Host smart-884c5787-ee62-4174-b9da-23b64773c404
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99064575 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.99064575
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2963297963
Short name T215
Test name
Test status
Simulation time 151583706 ps
CPU time 1.31 seconds
Started Jun 11 02:19:12 PM PDT 24
Finished Jun 11 02:19:14 PM PDT 24
Peak memory 217176 kb
Host smart-a72845fa-ee4f-4ad8-ac44-595d778602c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963297963 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2963297963
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_disable.4242483686
Short name T96
Test name
Test status
Simulation time 63779943 ps
CPU time 0.99 seconds
Started Jun 11 02:19:36 PM PDT 24
Finished Jun 11 02:19:38 PM PDT 24
Peak memory 216644 kb
Host smart-5e34c036-8c49-439b-bf7d-0848dd5656e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242483686 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.4242483686
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable.3223718569
Short name T91
Test name
Test status
Simulation time 14754027 ps
CPU time 0.96 seconds
Started Jun 11 02:19:54 PM PDT 24
Finished Jun 11 02:19:56 PM PDT 24
Peak memory 216800 kb
Host smart-ef6f33c4-60d0-4822-b15f-fd6a94629dd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223718569 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3223718569
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2179437550
Short name T39
Test name
Test status
Simulation time 95923403753 ps
CPU time 2241.65 seconds
Started Jun 11 02:18:14 PM PDT 24
Finished Jun 11 02:55:38 PM PDT 24
Peak memory 228556 kb
Host smart-0c9c19c3-94e2-4599-9428-aa517e85275e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179437550 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2179437550
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.edn_alert.3059338060
Short name T28
Test name
Test status
Simulation time 23558045 ps
CPU time 1.18 seconds
Started Jun 11 02:19:36 PM PDT 24
Finished Jun 11 02:19:37 PM PDT 24
Peak memory 219788 kb
Host smart-a6872a4f-2a02-42da-8dad-28bc6cc36bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059338060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3059338060
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/183.edn_alert.954155449
Short name T256
Test name
Test status
Simulation time 96401775 ps
CPU time 1.24 seconds
Started Jun 11 02:22:18 PM PDT 24
Finished Jun 11 02:22:20 PM PDT 24
Peak memory 218928 kb
Host smart-66283c90-160b-41b7-97af-bcf6075526c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954155449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.954155449
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/34.edn_genbits.653079509
Short name T314
Test name
Test status
Simulation time 67166964 ps
CPU time 1.4 seconds
Started Jun 11 02:20:13 PM PDT 24
Finished Jun 11 02:20:15 PM PDT 24
Peak memory 220280 kb
Host smart-bdbec5f8-8c5d-4894-84ec-7fbf97e1ea6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653079509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.653079509
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_alert.2712295714
Short name T114
Test name
Test status
Simulation time 29442000 ps
CPU time 1.19 seconds
Started Jun 11 02:20:25 PM PDT 24
Finished Jun 11 02:20:27 PM PDT 24
Peak memory 220052 kb
Host smart-f84deb2d-bfe9-4572-b819-c0dd74a5de87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712295714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2712295714
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/81.edn_alert.2416592138
Short name T189
Test name
Test status
Simulation time 56924583 ps
CPU time 1.31 seconds
Started Jun 11 02:21:22 PM PDT 24
Finished Jun 11 02:21:25 PM PDT 24
Peak memory 215924 kb
Host smart-c2c4d931-2084-4bf6-9749-2e8cfb7e9fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416592138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.2416592138
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/117.edn_alert.3929574847
Short name T150
Test name
Test status
Simulation time 117390663 ps
CPU time 1.15 seconds
Started Jun 11 02:21:49 PM PDT 24
Finished Jun 11 02:21:53 PM PDT 24
Peak memory 218832 kb
Host smart-aec6ef24-170c-4ab8-8696-fc27e526b8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929574847 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.3929574847
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/113.edn_alert.2481159229
Short name T628
Test name
Test status
Simulation time 82196158 ps
CPU time 1.18 seconds
Started Jun 11 02:21:46 PM PDT 24
Finished Jun 11 02:21:51 PM PDT 24
Peak memory 220908 kb
Host smart-e1b5a4db-a6c7-48cf-a0ab-c509c4c27fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481159229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2481159229
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/154.edn_alert.1849588530
Short name T131
Test name
Test status
Simulation time 58718614 ps
CPU time 1.19 seconds
Started Jun 11 02:22:05 PM PDT 24
Finished Jun 11 02:22:07 PM PDT 24
Peak memory 219748 kb
Host smart-10c4e15e-3a00-430b-b05b-11706294dfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849588530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.1849588530
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1544937233
Short name T97
Test name
Test status
Simulation time 64617631 ps
CPU time 1.24 seconds
Started Jun 11 02:19:58 PM PDT 24
Finished Jun 11 02:19:59 PM PDT 24
Peak memory 217072 kb
Host smart-f50afeb9-be4e-4d00-bfe7-59498deceb8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544937233 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1544937233
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/88.edn_alert.967581908
Short name T157
Test name
Test status
Simulation time 23396075 ps
CPU time 1.22 seconds
Started Jun 11 02:21:24 PM PDT 24
Finished Jun 11 02:21:27 PM PDT 24
Peak memory 220744 kb
Host smart-57e81467-d5b7-48ff-b035-82e5f92f62bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967581908 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.967581908
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/97.edn_genbits.1109877575
Short name T40
Test name
Test status
Simulation time 63264112 ps
CPU time 1.64 seconds
Started Jun 11 02:21:47 PM PDT 24
Finished Jun 11 02:21:52 PM PDT 24
Peak memory 218816 kb
Host smart-19ac30c1-0f20-404c-9c16-1557c1f2ed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109877575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1109877575
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3413033789
Short name T99
Test name
Test status
Simulation time 34377499 ps
CPU time 0.85 seconds
Started Jun 11 02:18:15 PM PDT 24
Finished Jun 11 02:18:17 PM PDT 24
Peak memory 215772 kb
Host smart-60ef444a-6ed8-4d7c-abb4-802f98f8316e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413033789 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3413033789
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/0.edn_intr.1445656007
Short name T102
Test name
Test status
Simulation time 21513092 ps
CPU time 1.1 seconds
Started Jun 11 02:18:15 PM PDT 24
Finished Jun 11 02:18:17 PM PDT 24
Peak memory 216088 kb
Host smart-db55263b-f20e-460a-9d9d-58126eb3e1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445656007 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1445656007
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/16.edn_alert.537047385
Short name T197
Test name
Test status
Simulation time 81159310 ps
CPU time 1.13 seconds
Started Jun 11 02:19:15 PM PDT 24
Finished Jun 11 02:19:17 PM PDT 24
Peak memory 219280 kb
Host smart-60d7417c-a514-4701-b9e5-1e9ee8f8d759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537047385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.537047385
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/3.edn_disable.2392409129
Short name T168
Test name
Test status
Simulation time 21947167 ps
CPU time 0.89 seconds
Started Jun 11 02:18:28 PM PDT 24
Finished Jun 11 02:18:30 PM PDT 24
Peak memory 215660 kb
Host smart-b39d1041-d936-4f4d-a12a-73cda698cd56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392409129 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2392409129
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1130584102
Short name T813
Test name
Test status
Simulation time 141563358 ps
CPU time 1.06 seconds
Started Jun 11 02:19:07 PM PDT 24
Finished Jun 11 02:19:09 PM PDT 24
Peak memory 219996 kb
Host smart-10bdc4f7-f0ae-4817-8ed1-5e730d3e209b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130584102 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1130584102
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1970021972
Short name T200
Test name
Test status
Simulation time 19944795 ps
CPU time 1.09 seconds
Started Jun 11 02:19:05 PM PDT 24
Finished Jun 11 02:19:07 PM PDT 24
Peak memory 219928 kb
Host smart-a8927b7f-5d0f-4bc8-8061-9941a5402c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970021972 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1970021972
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/15.edn_disable.2175534001
Short name T203
Test name
Test status
Simulation time 34033839 ps
CPU time 0.89 seconds
Started Jun 11 02:19:14 PM PDT 24
Finished Jun 11 02:19:16 PM PDT 24
Peak memory 216500 kb
Host smart-83fc7096-50f4-4fdb-af51-5189ef45646d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175534001 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2175534001
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1347453571
Short name T134
Test name
Test status
Simulation time 92366484 ps
CPU time 1.23 seconds
Started Jun 11 02:19:17 PM PDT 24
Finished Jun 11 02:19:19 PM PDT 24
Peak memory 217320 kb
Host smart-3b22caba-1041-44ba-93db-355472fe2a92
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347453571 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1347453571
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_disable.1368018062
Short name T94
Test name
Test status
Simulation time 46402283 ps
CPU time 0.86 seconds
Started Jun 11 02:19:16 PM PDT 24
Finished Jun 11 02:19:17 PM PDT 24
Peak memory 216500 kb
Host smart-17ba40ed-f35c-4f11-b726-ed5b6065a607
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368018062 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1368018062
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable.1601299154
Short name T211
Test name
Test status
Simulation time 41479705 ps
CPU time 0.92 seconds
Started Jun 11 02:19:51 PM PDT 24
Finished Jun 11 02:19:52 PM PDT 24
Peak memory 216516 kb
Host smart-6d0d4960-570a-4e35-8e48-65d6eb31ac23
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601299154 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1601299154
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.1712854239
Short name T188
Test name
Test status
Simulation time 40528101 ps
CPU time 0.99 seconds
Started Jun 11 02:20:06 PM PDT 24
Finished Jun 11 02:20:09 PM PDT 24
Peak memory 224224 kb
Host smart-c99dd7e3-95ba-419c-8b32-c6d059a5aa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712854239 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1712854239
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/35.edn_disable.1145024179
Short name T194
Test name
Test status
Simulation time 13071153 ps
CPU time 0.94 seconds
Started Jun 11 02:20:13 PM PDT 24
Finished Jun 11 02:20:15 PM PDT 24
Peak memory 216628 kb
Host smart-59129e05-4f5f-4234-912b-73770ac16de3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145024179 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1145024179
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/41.edn_alert.1940614170
Short name T183
Test name
Test status
Simulation time 77148686 ps
CPU time 1.06 seconds
Started Jun 11 02:20:37 PM PDT 24
Finished Jun 11 02:20:39 PM PDT 24
Peak memory 219924 kb
Host smart-56793d98-6823-4c37-9bbf-c193d7d7132b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940614170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1940614170
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/46.edn_disable.604339115
Short name T82
Test name
Test status
Simulation time 56736398 ps
CPU time 0.86 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:20:58 PM PDT 24
Peak memory 216508 kb
Host smart-723c4969-8494-4abd-8a9f-1dfdbab2faad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604339115 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.604339115
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/77.edn_err.407525816
Short name T198
Test name
Test status
Simulation time 24637184 ps
CPU time 0.99 seconds
Started Jun 11 02:21:19 PM PDT 24
Finished Jun 11 02:21:20 PM PDT 24
Peak memory 224036 kb
Host smart-20dd268c-0c78-4cae-9ca8-136f2bb59827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407525816 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.407525816
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/1.edn_alert_test.1441906203
Short name T351
Test name
Test status
Simulation time 51215059 ps
CPU time 1.44 seconds
Started Jun 11 02:18:15 PM PDT 24
Finished Jun 11 02:18:18 PM PDT 24
Peak memory 207036 kb
Host smart-ad1cc97f-702a-438e-b0fa-b9c74bd69d82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441906203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1441906203
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/129.edn_genbits.2887754107
Short name T83
Test name
Test status
Simulation time 62671401 ps
CPU time 2.38 seconds
Started Jun 11 02:22:01 PM PDT 24
Finished Jun 11 02:22:05 PM PDT 24
Peak memory 220352 kb
Host smart-0b64c908-64af-45d5-8cc6-60a3374766da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887754107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2887754107
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/100.edn_genbits.358882795
Short name T321
Test name
Test status
Simulation time 31924537 ps
CPU time 1.45 seconds
Started Jun 11 02:21:48 PM PDT 24
Finished Jun 11 02:21:53 PM PDT 24
Peak memory 218884 kb
Host smart-90b869ae-e85f-4ffb-b0f0-f2cb951ba393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358882795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.358882795
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.3263939130
Short name T625
Test name
Test status
Simulation time 46491698 ps
CPU time 1.17 seconds
Started Jun 11 02:22:05 PM PDT 24
Finished Jun 11 02:22:08 PM PDT 24
Peak memory 219048 kb
Host smart-c991fa4e-0c59-4c20-ba15-5e782a8c964d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263939130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3263939130
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.2465071341
Short name T780
Test name
Test status
Simulation time 58917894 ps
CPU time 1.69 seconds
Started Jun 11 02:22:22 PM PDT 24
Finished Jun 11 02:22:25 PM PDT 24
Peak memory 218612 kb
Host smart-e6e60bd2-7b80-4d9d-99be-80955fa5e02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465071341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2465071341
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1814598970
Short name T100
Test name
Test status
Simulation time 32336369 ps
CPU time 0.88 seconds
Started Jun 11 02:20:54 PM PDT 24
Finished Jun 11 02:20:56 PM PDT 24
Peak memory 215904 kb
Host smart-c79e8be4-de1f-47a4-b874-24b5348b13fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814598970 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1814598970
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/125.edn_genbits.957900429
Short name T319
Test name
Test status
Simulation time 32403095 ps
CPU time 1.31 seconds
Started Jun 11 02:21:47 PM PDT 24
Finished Jun 11 02:21:52 PM PDT 24
Peak memory 217600 kb
Host smart-e95c681a-7b1d-4c7c-9635-044c2ae6e8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957900429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.957900429
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2174913436
Short name T327
Test name
Test status
Simulation time 52818961 ps
CPU time 1.9 seconds
Started Jun 11 02:22:36 PM PDT 24
Finished Jun 11 02:22:40 PM PDT 24
Peak memory 218880 kb
Host smart-96e3837b-f035-4b24-b2f0-b53b9eb87596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174913436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2174913436
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_err.2887217525
Short name T382
Test name
Test status
Simulation time 25822923 ps
CPU time 0.89 seconds
Started Jun 11 02:18:13 PM PDT 24
Finished Jun 11 02:18:15 PM PDT 24
Peak memory 218484 kb
Host smart-b8ca2a31-e321-40a0-92b5-a08e27ffb9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887217525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2887217525
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1293142203
Short name T1129
Test name
Test status
Simulation time 96695374 ps
CPU time 2.64 seconds
Started Jun 11 01:49:05 PM PDT 24
Finished Jun 11 01:49:09 PM PDT 24
Peak memory 214844 kb
Host smart-b5792a9c-9872-4fa1-867f-8a59df381f8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293142203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1293142203
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1258823544
Short name T688
Test name
Test status
Simulation time 103338642 ps
CPU time 1.22 seconds
Started Jun 11 02:18:06 PM PDT 24
Finished Jun 11 02:18:08 PM PDT 24
Peak memory 219696 kb
Host smart-1f480987-f7c9-40a5-801d-649890b08796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258823544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1258823544
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1741648995
Short name T238
Test name
Test status
Simulation time 163787430822 ps
CPU time 1008.33 seconds
Started Jun 11 02:18:04 PM PDT 24
Finished Jun 11 02:34:54 PM PDT 24
Peak memory 221316 kb
Host smart-2ff8b4bb-60bf-4d15-a0c1-4a6988e2f415
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741648995 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1741648995
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_stress_all.1730441498
Short name T675
Test name
Test status
Simulation time 944701725 ps
CPU time 4.99 seconds
Started Jun 11 02:19:06 PM PDT 24
Finished Jun 11 02:19:12 PM PDT 24
Peak memory 215576 kb
Host smart-cdbe51d3-44a1-427b-8ab9-e15be37648fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730441498 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1730441498
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all.1939667609
Short name T908
Test name
Test status
Simulation time 342574124 ps
CPU time 3.88 seconds
Started Jun 11 02:19:08 PM PDT 24
Finished Jun 11 02:19:13 PM PDT 24
Peak memory 215588 kb
Host smart-b8539711-9531-4c56-99e9-fba3afaf2f33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939667609 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1939667609
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/115.edn_genbits.24167363
Short name T251
Test name
Test status
Simulation time 64634625 ps
CPU time 1.56 seconds
Started Jun 11 02:21:55 PM PDT 24
Finished Jun 11 02:21:58 PM PDT 24
Peak memory 219332 kb
Host smart-e9c6bdc1-3add-4355-827c-9bdb0aea95c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24167363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.24167363
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.3371658367
Short name T67
Test name
Test status
Simulation time 89354227 ps
CPU time 2.9 seconds
Started Jun 11 02:22:05 PM PDT 24
Finished Jun 11 02:22:09 PM PDT 24
Peak memory 220116 kb
Host smart-59b87e33-cfe5-41a3-a086-b0252bbe63e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371658367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3371658367
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.4271438775
Short name T311
Test name
Test status
Simulation time 33414672 ps
CPU time 1.49 seconds
Started Jun 11 02:22:10 PM PDT 24
Finished Jun 11 02:22:12 PM PDT 24
Peak memory 217836 kb
Host smart-a7d3e282-b5f8-4808-a059-daa5848dbd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271438775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.4271438775
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_genbits.1276844942
Short name T310
Test name
Test status
Simulation time 72236632 ps
CPU time 1.3 seconds
Started Jun 11 02:19:44 PM PDT 24
Finished Jun 11 02:19:46 PM PDT 24
Peak memory 220124 kb
Host smart-6332b4ae-afe7-4f01-bb1e-a6afe84872ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276844942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1276844942
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/250.edn_genbits.441583674
Short name T324
Test name
Test status
Simulation time 57150049 ps
CPU time 1.29 seconds
Started Jun 11 02:22:38 PM PDT 24
Finished Jun 11 02:22:41 PM PDT 24
Peak memory 220056 kb
Host smart-ccc69b15-4f6d-46fe-b0b4-6d8917c4df4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441583674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.441583674
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2284166416
Short name T32
Test name
Test status
Simulation time 21588946 ps
CPU time 1.09 seconds
Started Jun 11 02:20:16 PM PDT 24
Finished Jun 11 02:20:18 PM PDT 24
Peak memory 216228 kb
Host smart-ca1efaf7-fb77-4523-81ed-418ae4fdcdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284166416 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2284166416
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/14.edn_alert.3004416358
Short name T116
Test name
Test status
Simulation time 72710034 ps
CPU time 1.15 seconds
Started Jun 11 02:19:19 PM PDT 24
Finished Jun 11 02:19:21 PM PDT 24
Peak memory 219016 kb
Host smart-0a0b7b55-5724-4fd8-8365-005fc495e454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004416358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3004416358
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/176.edn_alert.424797118
Short name T113
Test name
Test status
Simulation time 81007640 ps
CPU time 1.21 seconds
Started Jun 11 02:22:13 PM PDT 24
Finished Jun 11 02:22:15 PM PDT 24
Peak memory 218724 kb
Host smart-92eb41a3-f005-45a8-8173-b087b0c23531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424797118 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.424797118
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.3098490610
Short name T697
Test name
Test status
Simulation time 40960451 ps
CPU time 1.48 seconds
Started Jun 11 02:21:48 PM PDT 24
Finished Jun 11 02:21:53 PM PDT 24
Peak memory 220072 kb
Host smart-785472a1-c04d-4419-a6a2-413bd5dcc6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098490610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3098490610
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1860905288
Short name T1013
Test name
Test status
Simulation time 82244133 ps
CPU time 1.64 seconds
Started Jun 11 01:49:08 PM PDT 24
Finished Jun 11 01:49:11 PM PDT 24
Peak memory 206604 kb
Host smart-3dff9467-6de6-4de9-a131-889927b00677
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860905288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1860905288
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3033924250
Short name T1074
Test name
Test status
Simulation time 184937982 ps
CPU time 3 seconds
Started Jun 11 01:49:06 PM PDT 24
Finished Jun 11 01:49:10 PM PDT 24
Peak memory 206644 kb
Host smart-1b5ec8c0-f9d1-4f03-94ab-9b26899a2bec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033924250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3033924250
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3884743780
Short name T270
Test name
Test status
Simulation time 24454006 ps
CPU time 0.91 seconds
Started Jun 11 01:49:07 PM PDT 24
Finished Jun 11 01:49:09 PM PDT 24
Peak memory 206640 kb
Host smart-badd98d7-5316-4a53-bf92-e1e34f901db1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884743780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3884743780
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1874252273
Short name T1082
Test name
Test status
Simulation time 35660619 ps
CPU time 1.59 seconds
Started Jun 11 01:49:08 PM PDT 24
Finished Jun 11 01:49:11 PM PDT 24
Peak memory 218200 kb
Host smart-c239b267-9147-4192-9391-138a81888508
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874252273 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1874252273
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.479183614
Short name T1110
Test name
Test status
Simulation time 22057169 ps
CPU time 0.89 seconds
Started Jun 11 01:49:06 PM PDT 24
Finished Jun 11 01:49:09 PM PDT 24
Peak memory 206540 kb
Host smart-8cc6ea5b-752a-4a77-aeec-143f08bff2af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479183614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.479183614
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3547601106
Short name T1081
Test name
Test status
Simulation time 12207502 ps
CPU time 0.86 seconds
Started Jun 11 01:49:07 PM PDT 24
Finished Jun 11 01:49:10 PM PDT 24
Peak memory 206636 kb
Host smart-884925a7-d608-433a-8f54-887f3a72edde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547601106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3547601106
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.658040125
Short name T1113
Test name
Test status
Simulation time 35808119 ps
CPU time 1.35 seconds
Started Jun 11 01:49:10 PM PDT 24
Finished Jun 11 01:49:14 PM PDT 24
Peak memory 206644 kb
Host smart-8f963739-070a-4e56-8626-ec352f975f93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658040125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.658040125
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.4196626414
Short name T1040
Test name
Test status
Simulation time 300442037 ps
CPU time 2.64 seconds
Started Jun 11 01:49:09 PM PDT 24
Finished Jun 11 01:49:14 PM PDT 24
Peak memory 214892 kb
Host smart-a18ce631-a7c5-4add-a3cf-0587eb7bfd22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196626414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.4196626414
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1366611115
Short name T290
Test name
Test status
Simulation time 56962017 ps
CPU time 1.75 seconds
Started Jun 11 01:49:10 PM PDT 24
Finished Jun 11 01:49:15 PM PDT 24
Peak memory 214780 kb
Host smart-2df1f7fe-dd73-4f3c-bf60-82234846e49c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366611115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1366611115
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3741388894
Short name T261
Test name
Test status
Simulation time 180131422 ps
CPU time 1.11 seconds
Started Jun 11 01:49:06 PM PDT 24
Finished Jun 11 01:49:08 PM PDT 24
Peak memory 206616 kb
Host smart-c01bf61d-be08-45a4-be5b-25d4bd571aa4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741388894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3741388894
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2477297498
Short name T1042
Test name
Test status
Simulation time 358142189 ps
CPU time 5.15 seconds
Started Jun 11 01:49:09 PM PDT 24
Finished Jun 11 01:49:17 PM PDT 24
Peak memory 206504 kb
Host smart-0079f9c6-721a-43f5-9b2b-a7eda073caa6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477297498 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2477297498
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1154879947
Short name T1005
Test name
Test status
Simulation time 14463131 ps
CPU time 0.91 seconds
Started Jun 11 01:49:09 PM PDT 24
Finished Jun 11 01:49:13 PM PDT 24
Peak memory 206496 kb
Host smart-73ab6009-2586-4a4b-a3df-02f481240e3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154879947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1154879947
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3792882814
Short name T1114
Test name
Test status
Simulation time 51929895 ps
CPU time 1.33 seconds
Started Jun 11 01:49:05 PM PDT 24
Finished Jun 11 01:49:08 PM PDT 24
Peak memory 217896 kb
Host smart-c31eeac3-67e4-40e7-bf3f-4448b5879a4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792882814 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3792882814
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3091473667
Short name T1088
Test name
Test status
Simulation time 14171894 ps
CPU time 0.82 seconds
Started Jun 11 01:49:12 PM PDT 24
Finished Jun 11 01:49:16 PM PDT 24
Peak memory 206648 kb
Host smart-3157be63-bbc6-49a8-bdf0-e967e7af0ed8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091473667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3091473667
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.312922819
Short name T1095
Test name
Test status
Simulation time 22944514 ps
CPU time 0.84 seconds
Started Jun 11 01:49:07 PM PDT 24
Finished Jun 11 01:49:10 PM PDT 24
Peak memory 206612 kb
Host smart-aef3a606-0182-471f-aba1-60998d870303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312922819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.312922819
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2423588107
Short name T1104
Test name
Test status
Simulation time 42593408 ps
CPU time 1.06 seconds
Started Jun 11 01:49:07 PM PDT 24
Finished Jun 11 01:49:10 PM PDT 24
Peak memory 206616 kb
Host smart-3983bd40-d207-4490-ae4c-4d4642a4e9c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423588107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2423588107
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.565361084
Short name T1085
Test name
Test status
Simulation time 206156298 ps
CPU time 3.53 seconds
Started Jun 11 01:49:08 PM PDT 24
Finished Jun 11 01:49:14 PM PDT 24
Peak memory 214928 kb
Host smart-a48dafcb-7646-44ef-a507-ea61fac3c7c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565361084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.565361084
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2173395524
Short name T1080
Test name
Test status
Simulation time 81570023 ps
CPU time 1.23 seconds
Started Jun 11 01:49:12 PM PDT 24
Finished Jun 11 01:49:16 PM PDT 24
Peak memory 214936 kb
Host smart-30e2fdb4-da1f-44c5-8543-b5d85ebe7c85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173395524 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2173395524
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2335170278
Short name T274
Test name
Test status
Simulation time 59000606 ps
CPU time 0.97 seconds
Started Jun 11 01:49:12 PM PDT 24
Finished Jun 11 01:49:16 PM PDT 24
Peak memory 206652 kb
Host smart-fcb85ed9-0536-43fa-a1dd-6ce2f365d6e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335170278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2335170278
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3967177405
Short name T1026
Test name
Test status
Simulation time 38840788 ps
CPU time 0.85 seconds
Started Jun 11 01:49:08 PM PDT 24
Finished Jun 11 01:49:11 PM PDT 24
Peak memory 206652 kb
Host smart-8ae1f43c-1e5e-41b8-baf0-2e08ca929e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967177405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3967177405
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.794674860
Short name T1076
Test name
Test status
Simulation time 70715298 ps
CPU time 1.1 seconds
Started Jun 11 01:49:13 PM PDT 24
Finished Jun 11 01:49:17 PM PDT 24
Peak memory 206716 kb
Host smart-0586cc8c-cf4b-4ab5-9615-6e5f6e9583b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794674860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.794674860
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.744396001
Short name T1024
Test name
Test status
Simulation time 107869502 ps
CPU time 2.5 seconds
Started Jun 11 01:49:15 PM PDT 24
Finished Jun 11 01:49:20 PM PDT 24
Peak memory 214904 kb
Host smart-52506a13-bec3-4551-8d47-0acae1be437f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744396001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.744396001
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3029529807
Short name T1073
Test name
Test status
Simulation time 439268609 ps
CPU time 7.35 seconds
Started Jun 11 01:49:15 PM PDT 24
Finished Jun 11 01:49:25 PM PDT 24
Peak memory 206648 kb
Host smart-3f19a672-4585-474f-ba05-b47ed82c9526
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029529807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3029529807
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3765781329
Short name T1046
Test name
Test status
Simulation time 20759419 ps
CPU time 1.19 seconds
Started Jun 11 01:49:21 PM PDT 24
Finished Jun 11 01:49:24 PM PDT 24
Peak memory 214932 kb
Host smart-d5ecd965-c9a4-4302-a434-fecb18d19770
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765781329 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3765781329
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2109319250
Short name T1049
Test name
Test status
Simulation time 73059386 ps
CPU time 0.85 seconds
Started Jun 11 01:49:12 PM PDT 24
Finished Jun 11 01:49:16 PM PDT 24
Peak memory 206484 kb
Host smart-c86f01ba-eee2-4728-ace8-c6728dd1683d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109319250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2109319250
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3100100976
Short name T280
Test name
Test status
Simulation time 25997774 ps
CPU time 1.11 seconds
Started Jun 11 01:49:10 PM PDT 24
Finished Jun 11 01:49:13 PM PDT 24
Peak memory 206644 kb
Host smart-ef008edf-ac62-4442-8669-b7213fe43732
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100100976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3100100976
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2239379896
Short name T1009
Test name
Test status
Simulation time 91605922 ps
CPU time 1.7 seconds
Started Jun 11 01:49:10 PM PDT 24
Finished Jun 11 01:49:15 PM PDT 24
Peak memory 214908 kb
Host smart-8519cb90-17f8-46f3-b034-a4f830728fc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239379896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2239379896
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1721266452
Short name T298
Test name
Test status
Simulation time 305292794 ps
CPU time 2.38 seconds
Started Jun 11 01:49:11 PM PDT 24
Finished Jun 11 01:49:17 PM PDT 24
Peak memory 206652 kb
Host smart-26882237-3096-4b4d-8c11-daf6a1895f8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721266452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1721266452
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1371440532
Short name T1122
Test name
Test status
Simulation time 24014304 ps
CPU time 1.6 seconds
Started Jun 11 01:49:40 PM PDT 24
Finished Jun 11 01:49:43 PM PDT 24
Peak memory 223056 kb
Host smart-394e1649-dd31-4bd6-9f0b-941b2b52850e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371440532 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1371440532
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1737984178
Short name T275
Test name
Test status
Simulation time 11496815 ps
CPU time 0.89 seconds
Started Jun 11 01:49:20 PM PDT 24
Finished Jun 11 01:49:22 PM PDT 24
Peak memory 206648 kb
Host smart-cc8af210-99fc-4f6c-a647-49224c5b7fe5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737984178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1737984178
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2430003882
Short name T1061
Test name
Test status
Simulation time 44696757 ps
CPU time 0.85 seconds
Started Jun 11 01:49:18 PM PDT 24
Finished Jun 11 01:49:20 PM PDT 24
Peak memory 206628 kb
Host smart-84d1f4b3-dc28-4f1f-b905-d966cd6e2ff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430003882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2430003882
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1066789787
Short name T1079
Test name
Test status
Simulation time 32684810 ps
CPU time 0.91 seconds
Started Jun 11 01:49:20 PM PDT 24
Finished Jun 11 01:49:22 PM PDT 24
Peak memory 206700 kb
Host smart-9469cb16-5af8-4cef-a169-42b39e8426f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066789787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1066789787
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3550003201
Short name T1032
Test name
Test status
Simulation time 184503091 ps
CPU time 3.54 seconds
Started Jun 11 01:49:11 PM PDT 24
Finished Jun 11 01:49:17 PM PDT 24
Peak memory 214984 kb
Host smart-0a1ed2ac-7d9c-4ecf-9f40-d9d3466148da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550003201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3550003201
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.994153084
Short name T1109
Test name
Test status
Simulation time 236131834 ps
CPU time 2.04 seconds
Started Jun 11 01:49:19 PM PDT 24
Finished Jun 11 01:49:28 PM PDT 24
Peak memory 206620 kb
Host smart-b77cd633-5801-4bc2-8b6d-cd14e1f5b6e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994153084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.994153084
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1993821889
Short name T998
Test name
Test status
Simulation time 18385502 ps
CPU time 1.23 seconds
Started Jun 11 01:49:40 PM PDT 24
Finished Jun 11 01:49:42 PM PDT 24
Peak memory 214900 kb
Host smart-2a4a7d6a-5d09-46c7-ad81-e6fc4023f722
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993821889 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1993821889
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.663976866
Short name T1083
Test name
Test status
Simulation time 15380689 ps
CPU time 0.99 seconds
Started Jun 11 01:49:17 PM PDT 24
Finished Jun 11 01:49:20 PM PDT 24
Peak memory 206632 kb
Host smart-33e74262-ce63-4cba-afb7-dd8cb549b0ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663976866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.663976866
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1080516039
Short name T1096
Test name
Test status
Simulation time 37614134 ps
CPU time 0.83 seconds
Started Jun 11 01:49:17 PM PDT 24
Finished Jun 11 01:49:20 PM PDT 24
Peak memory 206444 kb
Host smart-1724af81-7b34-4352-8c5b-4b818341a194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080516039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1080516039
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1963061101
Short name T1034
Test name
Test status
Simulation time 56035730 ps
CPU time 1.11 seconds
Started Jun 11 01:49:21 PM PDT 24
Finished Jun 11 01:49:24 PM PDT 24
Peak memory 206652 kb
Host smart-946b9c0f-1d71-41e9-a949-0ea6bc219afa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963061101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.1963061101
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1648292488
Short name T1072
Test name
Test status
Simulation time 267750155 ps
CPU time 2.28 seconds
Started Jun 11 01:49:33 PM PDT 24
Finished Jun 11 01:49:36 PM PDT 24
Peak memory 214912 kb
Host smart-89e58ed8-3e78-4058-b54f-0fec8deaa8aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648292488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1648292488
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1920601489
Short name T289
Test name
Test status
Simulation time 895699239 ps
CPU time 2.32 seconds
Started Jun 11 01:49:40 PM PDT 24
Finished Jun 11 01:49:43 PM PDT 24
Peak memory 214408 kb
Host smart-809e554e-9ed0-427e-8068-8f43b6fba9fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920601489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1920601489
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4131654858
Short name T1089
Test name
Test status
Simulation time 16834396 ps
CPU time 1.01 seconds
Started Jun 11 01:49:25 PM PDT 24
Finished Jun 11 01:49:28 PM PDT 24
Peak memory 206880 kb
Host smart-0ec8265f-57bc-4a12-ba97-a2a22ac8f59f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131654858 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.4131654858
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2612678618
Short name T277
Test name
Test status
Simulation time 29101551 ps
CPU time 0.99 seconds
Started Jun 11 01:49:21 PM PDT 24
Finished Jun 11 01:49:23 PM PDT 24
Peak memory 206596 kb
Host smart-a1955e71-5d1d-4cd2-9ba0-cbc61efb01bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612678618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2612678618
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2768116113
Short name T1051
Test name
Test status
Simulation time 14338280 ps
CPU time 0.96 seconds
Started Jun 11 01:49:22 PM PDT 24
Finished Jun 11 01:49:24 PM PDT 24
Peak memory 206516 kb
Host smart-79b0d42f-194e-4296-a58d-f9dd6c753f65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768116113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2768116113
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3161289773
Short name T1118
Test name
Test status
Simulation time 22847536 ps
CPU time 1.14 seconds
Started Jun 11 01:49:20 PM PDT 24
Finished Jun 11 01:49:22 PM PDT 24
Peak memory 206640 kb
Host smart-7c8067c0-cc59-4c08-9229-d3bd4cab270c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161289773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3161289773
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1394425559
Short name T1038
Test name
Test status
Simulation time 196148657 ps
CPU time 3.99 seconds
Started Jun 11 01:49:19 PM PDT 24
Finished Jun 11 01:49:24 PM PDT 24
Peak memory 214892 kb
Host smart-788275c3-6953-42ef-8be4-b1177164d693
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394425559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1394425559
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1002052316
Short name T299
Test name
Test status
Simulation time 286198976 ps
CPU time 2.36 seconds
Started Jun 11 01:49:42 PM PDT 24
Finished Jun 11 01:49:46 PM PDT 24
Peak memory 206628 kb
Host smart-08b0b9fc-f7ab-4063-9356-669aa9e4619a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002052316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1002052316
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2459119336
Short name T1091
Test name
Test status
Simulation time 43187594 ps
CPU time 0.91 seconds
Started Jun 11 01:49:18 PM PDT 24
Finished Jun 11 01:49:20 PM PDT 24
Peak memory 206700 kb
Host smart-c5f454ed-4dbc-4f70-a279-93fd635888c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459119336 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2459119336
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.126186573
Short name T267
Test name
Test status
Simulation time 200566167 ps
CPU time 0.88 seconds
Started Jun 11 01:49:23 PM PDT 24
Finished Jun 11 01:49:26 PM PDT 24
Peak memory 206636 kb
Host smart-0dc106b1-3641-4771-9aaf-c74b95c93b7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126186573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.126186573
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3127789618
Short name T1092
Test name
Test status
Simulation time 125735047 ps
CPU time 0.79 seconds
Started Jun 11 01:49:22 PM PDT 24
Finished Jun 11 01:49:24 PM PDT 24
Peak memory 206480 kb
Host smart-567155d0-814b-4974-80bb-744bd73a8a4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127789618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3127789618
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3963873738
Short name T278
Test name
Test status
Simulation time 228835978 ps
CPU time 1.36 seconds
Started Jun 11 01:49:25 PM PDT 24
Finished Jun 11 01:49:28 PM PDT 24
Peak memory 206800 kb
Host smart-dba5c5cf-73c2-47da-aad2-3a7bf83f18fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963873738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3963873738
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2285314256
Short name T1025
Test name
Test status
Simulation time 143763590 ps
CPU time 4.61 seconds
Started Jun 11 01:49:27 PM PDT 24
Finished Jun 11 01:49:34 PM PDT 24
Peak memory 214916 kb
Host smart-fad1ce5c-8386-4b77-9a12-6a8844af57bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285314256 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2285314256
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1610311328
Short name T1098
Test name
Test status
Simulation time 70372679 ps
CPU time 2.21 seconds
Started Jun 11 01:49:29 PM PDT 24
Finished Jun 11 01:49:33 PM PDT 24
Peak memory 206788 kb
Host smart-fc61386f-4192-4598-b62c-5cb1b38650ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610311328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1610311328
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3194725132
Short name T1037
Test name
Test status
Simulation time 26916489 ps
CPU time 1.55 seconds
Started Jun 11 01:49:19 PM PDT 24
Finished Jun 11 01:49:22 PM PDT 24
Peak memory 214860 kb
Host smart-e637ee56-13f2-4862-96d4-77668bf2a2bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194725132 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3194725132
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2627040864
Short name T273
Test name
Test status
Simulation time 29108714 ps
CPU time 0.96 seconds
Started Jun 11 01:49:21 PM PDT 24
Finished Jun 11 01:49:23 PM PDT 24
Peak memory 206600 kb
Host smart-9b1d24ac-8b44-4f36-8fcf-2271dd64bfea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627040864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2627040864
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3990152048
Short name T1115
Test name
Test status
Simulation time 38657173 ps
CPU time 0.87 seconds
Started Jun 11 01:49:21 PM PDT 24
Finished Jun 11 01:49:23 PM PDT 24
Peak memory 206644 kb
Host smart-49ab0e05-a153-4537-baa7-241c8bbc7165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990152048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3990152048
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2642822075
Short name T1078
Test name
Test status
Simulation time 41456256 ps
CPU time 1.06 seconds
Started Jun 11 01:49:21 PM PDT 24
Finished Jun 11 01:49:24 PM PDT 24
Peak memory 206652 kb
Host smart-291a0c3a-2302-41e1-8d57-e94a5178bde8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642822075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2642822075
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2127869328
Short name T1060
Test name
Test status
Simulation time 97854979 ps
CPU time 2.24 seconds
Started Jun 11 01:49:18 PM PDT 24
Finished Jun 11 01:49:26 PM PDT 24
Peak memory 214876 kb
Host smart-35abd7b4-940a-4427-9629-a8359ebdae76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127869328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2127869328
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.982523614
Short name T1128
Test name
Test status
Simulation time 459626438 ps
CPU time 1.41 seconds
Started Jun 11 01:49:36 PM PDT 24
Finished Jun 11 01:49:38 PM PDT 24
Peak memory 206704 kb
Host smart-d4cacf96-5795-4b0d-9c0a-d80272ff59dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982523614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.982523614
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3953340753
Short name T1107
Test name
Test status
Simulation time 95729658 ps
CPU time 1.37 seconds
Started Jun 11 01:49:24 PM PDT 24
Finished Jun 11 01:49:28 PM PDT 24
Peak memory 215136 kb
Host smart-8aa5b765-cc89-4a04-aade-db09abe2cf11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953340753 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3953340753
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2862926983
Short name T283
Test name
Test status
Simulation time 19744672 ps
CPU time 0.87 seconds
Started Jun 11 01:49:36 PM PDT 24
Finished Jun 11 01:49:38 PM PDT 24
Peak memory 206444 kb
Host smart-cf68ed9e-66e1-4277-b321-af325897c68f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862926983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2862926983
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1812153170
Short name T1054
Test name
Test status
Simulation time 40264909 ps
CPU time 0.8 seconds
Started Jun 11 01:49:21 PM PDT 24
Finished Jun 11 01:49:23 PM PDT 24
Peak memory 206372 kb
Host smart-c4228ec9-23b1-4512-8c1f-5e7896a355e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812153170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1812153170
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1611345800
Short name T279
Test name
Test status
Simulation time 18428047 ps
CPU time 1.17 seconds
Started Jun 11 01:49:27 PM PDT 24
Finished Jun 11 01:49:30 PM PDT 24
Peak memory 206660 kb
Host smart-a6bc4d5e-52de-4b87-be89-ad93e4593919
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611345800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1611345800
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1392934356
Short name T1057
Test name
Test status
Simulation time 223506338 ps
CPU time 2.31 seconds
Started Jun 11 01:49:22 PM PDT 24
Finished Jun 11 01:49:26 PM PDT 24
Peak memory 214904 kb
Host smart-a387f722-6a11-4a17-b2da-42a11abe3c02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392934356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1392934356
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.4226303061
Short name T1099
Test name
Test status
Simulation time 50336344 ps
CPU time 1.67 seconds
Started Jun 11 01:49:17 PM PDT 24
Finished Jun 11 01:49:20 PM PDT 24
Peak memory 206656 kb
Host smart-79413951-262f-4389-b5a9-3d220430627f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226303061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.4226303061
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3888661384
Short name T1019
Test name
Test status
Simulation time 54376605 ps
CPU time 0.97 seconds
Started Jun 11 01:49:29 PM PDT 24
Finished Jun 11 01:49:32 PM PDT 24
Peak memory 206724 kb
Host smart-e2a8731a-4094-4147-b9fb-f67fa3856725
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888661384 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3888661384
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1382844251
Short name T1062
Test name
Test status
Simulation time 45258163 ps
CPU time 0.9 seconds
Started Jun 11 01:49:23 PM PDT 24
Finished Jun 11 01:49:26 PM PDT 24
Peak memory 206640 kb
Host smart-68acc337-841d-437d-9811-ed03586abf94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382844251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1382844251
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1890407385
Short name T1121
Test name
Test status
Simulation time 25232639 ps
CPU time 0.85 seconds
Started Jun 11 01:49:19 PM PDT 24
Finished Jun 11 01:49:21 PM PDT 24
Peak memory 206496 kb
Host smart-88e9c8be-a93b-4b60-9896-b61e761ff0de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890407385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1890407385
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2311926164
Short name T1056
Test name
Test status
Simulation time 110657354 ps
CPU time 1.32 seconds
Started Jun 11 01:49:26 PM PDT 24
Finished Jun 11 01:49:30 PM PDT 24
Peak memory 206704 kb
Host smart-cf1ed662-dac5-4c74-a98d-cba6492e135b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311926164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2311926164
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2218533953
Short name T1111
Test name
Test status
Simulation time 98066888 ps
CPU time 3.6 seconds
Started Jun 11 01:49:28 PM PDT 24
Finished Jun 11 01:49:34 PM PDT 24
Peak memory 214920 kb
Host smart-b8bc2ef8-6b3c-46c5-8383-ceea31929685
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218533953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2218533953
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2076632855
Short name T301
Test name
Test status
Simulation time 126112379 ps
CPU time 2.02 seconds
Started Jun 11 01:49:23 PM PDT 24
Finished Jun 11 01:49:26 PM PDT 24
Peak memory 215416 kb
Host smart-c1cdf78f-59f4-4ac3-a92b-d3f51a135b8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076632855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2076632855
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.231119825
Short name T1068
Test name
Test status
Simulation time 31071748 ps
CPU time 1.51 seconds
Started Jun 11 01:49:27 PM PDT 24
Finished Jun 11 01:49:31 PM PDT 24
Peak memory 214932 kb
Host smart-4494d43b-01fb-43bb-abab-80e5e6e79196
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231119825 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.231119825
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1783710318
Short name T1012
Test name
Test status
Simulation time 24213910 ps
CPU time 0.87 seconds
Started Jun 11 01:49:22 PM PDT 24
Finished Jun 11 01:49:24 PM PDT 24
Peak memory 206644 kb
Host smart-89853641-da53-4fd4-8cd9-dd5d9335c168
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783710318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1783710318
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1522674526
Short name T1047
Test name
Test status
Simulation time 85577100 ps
CPU time 0.93 seconds
Started Jun 11 01:49:22 PM PDT 24
Finished Jun 11 01:49:25 PM PDT 24
Peak memory 206544 kb
Host smart-0298b010-3650-4a6d-92f2-3d02eaa9f478
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522674526 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1522674526
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4160672298
Short name T1125
Test name
Test status
Simulation time 54187312 ps
CPU time 0.96 seconds
Started Jun 11 01:49:24 PM PDT 24
Finished Jun 11 01:49:26 PM PDT 24
Peak memory 206704 kb
Host smart-e2639211-a061-49ba-9ed3-cef146883690
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160672298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.4160672298
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.728595918
Short name T1112
Test name
Test status
Simulation time 782514254 ps
CPU time 3.8 seconds
Started Jun 11 01:49:21 PM PDT 24
Finished Jun 11 01:49:26 PM PDT 24
Peak memory 214908 kb
Host smart-916c8dcb-7656-4213-9c48-106f09fdd2a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728595918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.728595918
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.649585441
Short name T264
Test name
Test status
Simulation time 108710308 ps
CPU time 1.53 seconds
Started Jun 11 01:49:06 PM PDT 24
Finished Jun 11 01:49:09 PM PDT 24
Peak memory 206636 kb
Host smart-a6636ed4-f93c-489a-abe3-508bd34422a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649585441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.649585441
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3944417323
Short name T272
Test name
Test status
Simulation time 124594273 ps
CPU time 2 seconds
Started Jun 11 01:49:09 PM PDT 24
Finished Jun 11 01:49:13 PM PDT 24
Peak memory 206708 kb
Host smart-d4f6ed5f-af57-46a3-abcc-ef227da884df
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944417323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3944417323
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3689473790
Short name T266
Test name
Test status
Simulation time 14060737 ps
CPU time 0.9 seconds
Started Jun 11 01:49:08 PM PDT 24
Finished Jun 11 01:49:11 PM PDT 24
Peak memory 206488 kb
Host smart-a398849f-099f-4b83-82b4-a13a563f55d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689473790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3689473790
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2183086793
Short name T1014
Test name
Test status
Simulation time 67567950 ps
CPU time 1.24 seconds
Started Jun 11 01:49:10 PM PDT 24
Finished Jun 11 01:49:14 PM PDT 24
Peak memory 214916 kb
Host smart-2e6c5f39-a397-4fa4-9255-bcb518329474
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183086793 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2183086793
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.943654131
Short name T1093
Test name
Test status
Simulation time 14744246 ps
CPU time 0.91 seconds
Started Jun 11 01:49:08 PM PDT 24
Finished Jun 11 01:49:10 PM PDT 24
Peak memory 206640 kb
Host smart-23aac8b0-315e-4d28-8c9f-80563b53c79f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943654131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.943654131
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3792740442
Short name T1052
Test name
Test status
Simulation time 20011421 ps
CPU time 0.83 seconds
Started Jun 11 01:49:09 PM PDT 24
Finished Jun 11 01:49:12 PM PDT 24
Peak memory 206644 kb
Host smart-5b566c64-58f0-4894-b513-d7834f1086f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792740442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3792740442
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.863378726
Short name T1028
Test name
Test status
Simulation time 17894966 ps
CPU time 1.11 seconds
Started Jun 11 01:49:06 PM PDT 24
Finished Jun 11 01:49:08 PM PDT 24
Peak memory 206628 kb
Host smart-746802d5-d4bc-421a-a62d-a7c27bdcc80f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863378726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out
standing.863378726
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2160393330
Short name T1004
Test name
Test status
Simulation time 136019374 ps
CPU time 3.12 seconds
Started Jun 11 01:49:06 PM PDT 24
Finished Jun 11 01:49:10 PM PDT 24
Peak memory 214892 kb
Host smart-a8ff84e3-e71b-48c3-9c9d-62ca879768c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160393330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2160393330
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2579714579
Short name T1105
Test name
Test status
Simulation time 83912679 ps
CPU time 1.73 seconds
Started Jun 11 01:49:05 PM PDT 24
Finished Jun 11 01:49:08 PM PDT 24
Peak memory 206596 kb
Host smart-8545a8c7-e0bc-4fee-99ea-09a00d4888a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579714579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2579714579
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.4227440960
Short name T1029
Test name
Test status
Simulation time 15306150 ps
CPU time 0.99 seconds
Started Jun 11 01:49:24 PM PDT 24
Finished Jun 11 01:49:27 PM PDT 24
Peak memory 206644 kb
Host smart-6ad762b9-9f76-475e-89d8-82c2f7050625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227440960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.4227440960
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.544835602
Short name T1000
Test name
Test status
Simulation time 11539798 ps
CPU time 0.8 seconds
Started Jun 11 01:49:23 PM PDT 24
Finished Jun 11 01:49:25 PM PDT 24
Peak memory 206572 kb
Host smart-5ef7407e-b198-4ee2-8b80-20124ba8b5f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544835602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.544835602
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2660869500
Short name T1016
Test name
Test status
Simulation time 26353813 ps
CPU time 0.9 seconds
Started Jun 11 01:49:17 PM PDT 24
Finished Jun 11 01:49:19 PM PDT 24
Peak memory 206620 kb
Host smart-fd445663-6944-4807-88a2-ebb153cf16b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660869500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2660869500
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1943319851
Short name T1117
Test name
Test status
Simulation time 17971559 ps
CPU time 0.79 seconds
Started Jun 11 01:49:22 PM PDT 24
Finished Jun 11 01:49:24 PM PDT 24
Peak memory 206372 kb
Host smart-4216af4e-d590-4f06-a385-7ebe403067c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943319851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1943319851
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.411832382
Short name T1063
Test name
Test status
Simulation time 56782668 ps
CPU time 0.9 seconds
Started Jun 11 01:49:21 PM PDT 24
Finished Jun 11 01:49:23 PM PDT 24
Peak memory 206540 kb
Host smart-3cefce92-93eb-4d98-a07b-a7c0e7da159a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411832382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.411832382
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1259630706
Short name T1084
Test name
Test status
Simulation time 23172218 ps
CPU time 0.85 seconds
Started Jun 11 01:49:20 PM PDT 24
Finished Jun 11 01:49:22 PM PDT 24
Peak memory 206636 kb
Host smart-3a13a454-5408-4334-87dc-22c0ef146b24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259630706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1259630706
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2577491392
Short name T1050
Test name
Test status
Simulation time 118314986 ps
CPU time 0.85 seconds
Started Jun 11 01:49:26 PM PDT 24
Finished Jun 11 01:49:29 PM PDT 24
Peak memory 206440 kb
Host smart-f517e388-9d20-4ba5-90a3-aa2d261b42b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577491392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2577491392
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2246465573
Short name T1059
Test name
Test status
Simulation time 12105947 ps
CPU time 0.83 seconds
Started Jun 11 01:49:27 PM PDT 24
Finished Jun 11 01:49:30 PM PDT 24
Peak memory 206652 kb
Host smart-ac3381c5-743a-4c23-9b0d-e5521b00c181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246465573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2246465573
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1653239537
Short name T1010
Test name
Test status
Simulation time 25492573 ps
CPU time 0.86 seconds
Started Jun 11 01:49:37 PM PDT 24
Finished Jun 11 01:49:39 PM PDT 24
Peak memory 206648 kb
Host smart-c1fa6b54-e7a2-4e44-b135-27966f11de44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653239537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1653239537
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2799284941
Short name T1055
Test name
Test status
Simulation time 11764889 ps
CPU time 0.84 seconds
Started Jun 11 01:49:23 PM PDT 24
Finished Jun 11 01:49:25 PM PDT 24
Peak memory 206516 kb
Host smart-1dfdd0ac-b02f-4755-bf42-f3360aaaef80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799284941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2799284941
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.313575368
Short name T1101
Test name
Test status
Simulation time 40201193 ps
CPU time 1.13 seconds
Started Jun 11 01:49:07 PM PDT 24
Finished Jun 11 01:49:10 PM PDT 24
Peak memory 206708 kb
Host smart-c8cdd33a-bb5b-4deb-86c3-01d2ab26e5ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313575368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.313575368
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2243122383
Short name T1102
Test name
Test status
Simulation time 386316798 ps
CPU time 2.14 seconds
Started Jun 11 01:49:08 PM PDT 24
Finished Jun 11 01:49:12 PM PDT 24
Peak memory 206700 kb
Host smart-d7567fb4-46f5-42ac-b64a-8196513612cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243122383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2243122383
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.320468747
Short name T268
Test name
Test status
Simulation time 27236580 ps
CPU time 0.86 seconds
Started Jun 11 01:49:13 PM PDT 24
Finished Jun 11 01:49:17 PM PDT 24
Peak memory 206672 kb
Host smart-48648cf0-bb1b-4e6d-9bb9-291d47f02fdb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320468747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.320468747
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.269269250
Short name T1090
Test name
Test status
Simulation time 49090665 ps
CPU time 0.93 seconds
Started Jun 11 01:49:11 PM PDT 24
Finished Jun 11 01:49:15 PM PDT 24
Peak memory 206652 kb
Host smart-3da811bd-74ad-4a1f-97bb-8b81da965bca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269269250 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.269269250
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2162274665
Short name T1043
Test name
Test status
Simulation time 32325044 ps
CPU time 0.88 seconds
Started Jun 11 01:49:10 PM PDT 24
Finished Jun 11 01:49:13 PM PDT 24
Peak memory 206648 kb
Host smart-7a064214-1ba1-47f3-abd4-ebfc1db63ec7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162274665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2162274665
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1004442548
Short name T1065
Test name
Test status
Simulation time 91640639 ps
CPU time 0.85 seconds
Started Jun 11 01:49:09 PM PDT 24
Finished Jun 11 01:49:12 PM PDT 24
Peak memory 206640 kb
Host smart-bcc00920-305a-427f-a7a3-0d712617a197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004442548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1004442548
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.133691352
Short name T282
Test name
Test status
Simulation time 132148515 ps
CPU time 1.25 seconds
Started Jun 11 01:49:08 PM PDT 24
Finished Jun 11 01:49:11 PM PDT 24
Peak memory 206616 kb
Host smart-c3f2f7ff-bb71-40cb-b394-192fe4c37ec2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133691352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.133691352
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.709173249
Short name T1075
Test name
Test status
Simulation time 125486862 ps
CPU time 4.12 seconds
Started Jun 11 01:49:06 PM PDT 24
Finished Jun 11 01:49:12 PM PDT 24
Peak memory 214912 kb
Host smart-8682a003-a91d-44b2-8772-366d35882c18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709173249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.709173249
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.902684204
Short name T296
Test name
Test status
Simulation time 43558605 ps
CPU time 1.51 seconds
Started Jun 11 01:49:11 PM PDT 24
Finished Jun 11 01:49:16 PM PDT 24
Peak memory 206736 kb
Host smart-9925db0f-9b5f-4d80-ba6f-6b9d494d20ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902684204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.902684204
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1500751213
Short name T1033
Test name
Test status
Simulation time 45073210 ps
CPU time 0.87 seconds
Started Jun 11 01:49:26 PM PDT 24
Finished Jun 11 01:49:29 PM PDT 24
Peak memory 206640 kb
Host smart-ba72f70a-0e5a-4d62-a598-baeab107fb10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500751213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1500751213
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.937981999
Short name T1119
Test name
Test status
Simulation time 34778368 ps
CPU time 0.79 seconds
Started Jun 11 01:49:42 PM PDT 24
Finished Jun 11 01:49:44 PM PDT 24
Peak memory 206228 kb
Host smart-90f9230d-f719-449e-a554-584d075d82e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937981999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.937981999
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.433911190
Short name T1106
Test name
Test status
Simulation time 17578884 ps
CPU time 0.8 seconds
Started Jun 11 01:49:40 PM PDT 24
Finished Jun 11 01:49:42 PM PDT 24
Peak memory 206448 kb
Host smart-2415b023-4b0f-45f1-83af-c3dd835cdca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433911190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.433911190
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3959990380
Short name T1002
Test name
Test status
Simulation time 14396293 ps
CPU time 0.91 seconds
Started Jun 11 01:49:40 PM PDT 24
Finished Jun 11 01:49:42 PM PDT 24
Peak memory 206096 kb
Host smart-3249ba9a-dd5b-4ce1-b504-32127d498218
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959990380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3959990380
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1063502092
Short name T1045
Test name
Test status
Simulation time 13459894 ps
CPU time 0.91 seconds
Started Jun 11 01:49:28 PM PDT 24
Finished Jun 11 01:49:32 PM PDT 24
Peak memory 206644 kb
Host smart-9ef5b099-9688-4b3b-842c-751af4ec0074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063502092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1063502092
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.4006501626
Short name T1126
Test name
Test status
Simulation time 45728937 ps
CPU time 0.89 seconds
Started Jun 11 01:49:26 PM PDT 24
Finished Jun 11 01:49:29 PM PDT 24
Peak memory 206596 kb
Host smart-30d29547-4620-4426-a8a0-d7b68dfeeab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006501626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.4006501626
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2690760994
Short name T1030
Test name
Test status
Simulation time 114940859 ps
CPU time 0.86 seconds
Started Jun 11 01:49:37 PM PDT 24
Finished Jun 11 01:49:40 PM PDT 24
Peak memory 206476 kb
Host smart-13b9f1e6-c2ae-4d13-90e3-699dc9f8fb98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690760994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2690760994
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2881982623
Short name T1058
Test name
Test status
Simulation time 40713687 ps
CPU time 0.8 seconds
Started Jun 11 01:49:37 PM PDT 24
Finished Jun 11 01:49:39 PM PDT 24
Peak memory 206448 kb
Host smart-d4b3c0cd-97d3-4e1b-98ca-cdd1ea035a68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881982623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2881982623
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2225870804
Short name T1018
Test name
Test status
Simulation time 23075309 ps
CPU time 0.9 seconds
Started Jun 11 01:49:25 PM PDT 24
Finished Jun 11 01:49:28 PM PDT 24
Peak memory 206808 kb
Host smart-9918cce2-1643-40ac-92f6-ae505efdf263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225870804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2225870804
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2506584156
Short name T1064
Test name
Test status
Simulation time 13221604 ps
CPU time 0.86 seconds
Started Jun 11 01:49:19 PM PDT 24
Finished Jun 11 01:49:21 PM PDT 24
Peak memory 206540 kb
Host smart-b677bd67-f7d7-4f4c-b085-b6428773edeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506584156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2506584156
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.999596530
Short name T262
Test name
Test status
Simulation time 52193618 ps
CPU time 1 seconds
Started Jun 11 01:49:11 PM PDT 24
Finished Jun 11 01:49:15 PM PDT 24
Peak memory 206656 kb
Host smart-5d1c167c-bcaf-47df-b44b-13e6f3d3d22b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999596530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.999596530
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4242665248
Short name T1027
Test name
Test status
Simulation time 65667900 ps
CPU time 2.02 seconds
Started Jun 11 01:49:06 PM PDT 24
Finished Jun 11 01:49:10 PM PDT 24
Peak memory 206576 kb
Host smart-39e23bec-95bb-4733-9419-5e4a35da9aaa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242665248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.4242665248
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1519191960
Short name T263
Test name
Test status
Simulation time 37350385 ps
CPU time 0.83 seconds
Started Jun 11 01:49:09 PM PDT 24
Finished Jun 11 01:49:11 PM PDT 24
Peak memory 206400 kb
Host smart-4bfca5fb-172e-49e2-9705-f7287c30b821
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519191960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1519191960
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1983037856
Short name T1003
Test name
Test status
Simulation time 22149591 ps
CPU time 1.41 seconds
Started Jun 11 01:49:09 PM PDT 24
Finished Jun 11 01:49:12 PM PDT 24
Peak memory 214928 kb
Host smart-1f86852d-43d4-43cb-a7da-a9716cf77b9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983037856 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1983037856
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.521410761
Short name T1044
Test name
Test status
Simulation time 14666574 ps
CPU time 0.92 seconds
Started Jun 11 01:49:12 PM PDT 24
Finished Jun 11 01:49:16 PM PDT 24
Peak memory 206516 kb
Host smart-2b1ae591-4188-4822-a574-d53ec4096202
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521410761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.521410761
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2785679441
Short name T1017
Test name
Test status
Simulation time 62272520 ps
CPU time 0.81 seconds
Started Jun 11 01:49:13 PM PDT 24
Finished Jun 11 01:49:16 PM PDT 24
Peak memory 206644 kb
Host smart-57a32364-3e4a-406b-b673-b5c35ebcd42d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785679441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2785679441
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1999197126
Short name T1031
Test name
Test status
Simulation time 42998785 ps
CPU time 0.93 seconds
Started Jun 11 01:49:06 PM PDT 24
Finished Jun 11 01:49:09 PM PDT 24
Peak memory 206592 kb
Host smart-fec14fd1-0969-48ca-94d0-72d96d844481
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999197126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1999197126
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.4005397571
Short name T1127
Test name
Test status
Simulation time 93187859 ps
CPU time 3.3 seconds
Started Jun 11 01:49:13 PM PDT 24
Finished Jun 11 01:49:19 PM PDT 24
Peak memory 214776 kb
Host smart-5a731924-b1db-4587-a87e-7a56231939ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005397571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.4005397571
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.496051102
Short name T1120
Test name
Test status
Simulation time 46705087 ps
CPU time 1.63 seconds
Started Jun 11 01:49:11 PM PDT 24
Finished Jun 11 01:49:16 PM PDT 24
Peak memory 206768 kb
Host smart-c1a68fb8-822f-49c7-ab32-dfe93f41aec4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496051102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.496051102
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2242897486
Short name T1077
Test name
Test status
Simulation time 27229465 ps
CPU time 0.79 seconds
Started Jun 11 01:49:39 PM PDT 24
Finished Jun 11 01:49:41 PM PDT 24
Peak memory 206476 kb
Host smart-ee9bd4b3-d455-4bd3-9412-dea3af2bba2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242897486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2242897486
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3887975836
Short name T1108
Test name
Test status
Simulation time 35785663 ps
CPU time 0.84 seconds
Started Jun 11 01:49:25 PM PDT 24
Finished Jun 11 01:49:28 PM PDT 24
Peak memory 206808 kb
Host smart-c8229100-b886-4821-92b2-702502f4a440
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887975836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3887975836
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2908938140
Short name T1020
Test name
Test status
Simulation time 53150092 ps
CPU time 0.8 seconds
Started Jun 11 01:49:41 PM PDT 24
Finished Jun 11 01:49:43 PM PDT 24
Peak memory 206384 kb
Host smart-79cf83f9-26e9-403f-a5eb-ac2ab6fb7fc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908938140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2908938140
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1472717746
Short name T1066
Test name
Test status
Simulation time 13428285 ps
CPU time 0.85 seconds
Started Jun 11 01:49:24 PM PDT 24
Finished Jun 11 01:49:27 PM PDT 24
Peak memory 206804 kb
Host smart-483a2c27-3d91-42fe-83f2-520f91ccd58d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472717746 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1472717746
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2231429291
Short name T1006
Test name
Test status
Simulation time 15493081 ps
CPU time 0.75 seconds
Started Jun 11 01:49:29 PM PDT 24
Finished Jun 11 01:49:32 PM PDT 24
Peak memory 206460 kb
Host smart-27dfd917-8fa2-4527-a5a1-11d566fda550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231429291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2231429291
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2437487743
Short name T1035
Test name
Test status
Simulation time 73729833 ps
CPU time 0.76 seconds
Started Jun 11 01:49:35 PM PDT 24
Finished Jun 11 01:49:37 PM PDT 24
Peak memory 206384 kb
Host smart-8a0418a1-312d-48bd-a40d-2f7c9cb767f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437487743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2437487743
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2077888866
Short name T999
Test name
Test status
Simulation time 13754759 ps
CPU time 0.89 seconds
Started Jun 11 01:49:35 PM PDT 24
Finished Jun 11 01:49:37 PM PDT 24
Peak memory 206556 kb
Host smart-2d6a7c6e-8d7c-4894-b62c-2bf1c58f6339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077888866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2077888866
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2829118525
Short name T1011
Test name
Test status
Simulation time 37406867 ps
CPU time 0.78 seconds
Started Jun 11 01:49:26 PM PDT 24
Finished Jun 11 01:49:30 PM PDT 24
Peak memory 206384 kb
Host smart-657fde0f-dcb2-48da-982d-f79dc8ae10b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829118525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2829118525
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3634570667
Short name T1039
Test name
Test status
Simulation time 12018797 ps
CPU time 0.89 seconds
Started Jun 11 01:49:37 PM PDT 24
Finished Jun 11 01:49:39 PM PDT 24
Peak memory 206636 kb
Host smart-2bd71e70-c5cf-4ccf-b987-a907b16635db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634570667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3634570667
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.795282501
Short name T1001
Test name
Test status
Simulation time 12577192 ps
CPU time 0.93 seconds
Started Jun 11 01:49:29 PM PDT 24
Finished Jun 11 01:49:32 PM PDT 24
Peak memory 206632 kb
Host smart-39626919-e1b6-4dd1-bb97-81f533c898fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795282501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.795282501
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1086957119
Short name T1007
Test name
Test status
Simulation time 32653857 ps
CPU time 2.19 seconds
Started Jun 11 01:49:16 PM PDT 24
Finished Jun 11 01:49:20 PM PDT 24
Peak memory 214824 kb
Host smart-83cb7bb8-4508-474d-acba-6ce48b3d07fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086957119 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1086957119
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.755072922
Short name T1041
Test name
Test status
Simulation time 50839194 ps
CPU time 0.86 seconds
Started Jun 11 01:49:05 PM PDT 24
Finished Jun 11 01:49:07 PM PDT 24
Peak memory 206588 kb
Host smart-aeb3c1b1-0867-4a6a-90b7-55270d715715
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755072922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.755072922
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3850971794
Short name T1086
Test name
Test status
Simulation time 42226508 ps
CPU time 0.8 seconds
Started Jun 11 01:49:09 PM PDT 24
Finished Jun 11 01:49:13 PM PDT 24
Peak memory 206708 kb
Host smart-cb1570a4-f864-4515-ac30-20b561d4a264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850971794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3850971794
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2295042228
Short name T1048
Test name
Test status
Simulation time 34291022 ps
CPU time 1.17 seconds
Started Jun 11 01:49:07 PM PDT 24
Finished Jun 11 01:49:10 PM PDT 24
Peak memory 206800 kb
Host smart-5e37ec10-b824-4abf-8690-58d608cc5f07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295042228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2295042228
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1087622013
Short name T1053
Test name
Test status
Simulation time 139132714 ps
CPU time 2.59 seconds
Started Jun 11 01:49:13 PM PDT 24
Finished Jun 11 01:49:19 PM PDT 24
Peak memory 214776 kb
Host smart-cffc15bc-3741-45a8-a422-b5df524ad591
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087622013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1087622013
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2661530435
Short name T297
Test name
Test status
Simulation time 149752634 ps
CPU time 2.32 seconds
Started Jun 11 01:49:07 PM PDT 24
Finished Jun 11 01:49:11 PM PDT 24
Peak memory 206548 kb
Host smart-4814a90e-31cb-46f5-9623-54c4f85ac99e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661530435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2661530435
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.468591137
Short name T1116
Test name
Test status
Simulation time 117461625 ps
CPU time 1.5 seconds
Started Jun 11 01:49:08 PM PDT 24
Finished Jun 11 01:49:11 PM PDT 24
Peak memory 214800 kb
Host smart-8d9ddec1-b4ed-4757-a091-08f80f9075fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468591137 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.468591137
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.47448147
Short name T271
Test name
Test status
Simulation time 36855140 ps
CPU time 0.86 seconds
Started Jun 11 01:49:17 PM PDT 24
Finished Jun 11 01:49:19 PM PDT 24
Peak memory 206448 kb
Host smart-35249757-c0b2-43ab-8c25-9df57fa69559
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47448147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.47448147
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3483986408
Short name T1097
Test name
Test status
Simulation time 23909096 ps
CPU time 0.86 seconds
Started Jun 11 01:49:07 PM PDT 24
Finished Jun 11 01:49:10 PM PDT 24
Peak memory 206608 kb
Host smart-04d7c9b7-3564-4d6a-9a23-3f1c7a57562b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483986408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3483986408
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.855606097
Short name T276
Test name
Test status
Simulation time 71207572 ps
CPU time 1.44 seconds
Started Jun 11 01:49:10 PM PDT 24
Finished Jun 11 01:49:14 PM PDT 24
Peak memory 206640 kb
Host smart-1dac2c7a-d185-47ff-b73f-8f48b6fe310a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855606097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.855606097
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3081226524
Short name T1015
Test name
Test status
Simulation time 81339674 ps
CPU time 2.89 seconds
Started Jun 11 01:49:17 PM PDT 24
Finished Jun 11 01:49:21 PM PDT 24
Peak memory 218904 kb
Host smart-3165339b-3f44-47e1-a36a-6e29444aad3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081226524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3081226524
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.474653123
Short name T1087
Test name
Test status
Simulation time 154439246 ps
CPU time 1.56 seconds
Started Jun 11 01:49:13 PM PDT 24
Finished Jun 11 01:49:17 PM PDT 24
Peak memory 214816 kb
Host smart-9a0f33ab-1b8b-4aec-a438-03cb9094b903
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474653123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.474653123
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.561198139
Short name T1124
Test name
Test status
Simulation time 32151102 ps
CPU time 1.51 seconds
Started Jun 11 01:49:12 PM PDT 24
Finished Jun 11 01:49:17 PM PDT 24
Peak memory 215052 kb
Host smart-51ec022f-a20d-4f7d-962c-f3283494f304
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561198139 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.561198139
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.886447800
Short name T1069
Test name
Test status
Simulation time 81450456 ps
CPU time 0.82 seconds
Started Jun 11 01:49:12 PM PDT 24
Finished Jun 11 01:49:16 PM PDT 24
Peak memory 206416 kb
Host smart-f385352e-8504-42bc-9c85-534527b7f29b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886447800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.886447800
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3994223770
Short name T1008
Test name
Test status
Simulation time 15670387 ps
CPU time 0.94 seconds
Started Jun 11 01:49:16 PM PDT 24
Finished Jun 11 01:49:19 PM PDT 24
Peak memory 206584 kb
Host smart-58fd974a-ea72-4dde-8380-46d8b1c1524d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994223770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3994223770
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1843670518
Short name T284
Test name
Test status
Simulation time 20094572 ps
CPU time 1.25 seconds
Started Jun 11 01:49:16 PM PDT 24
Finished Jun 11 01:49:19 PM PDT 24
Peak memory 206568 kb
Host smart-59b93db3-fcfa-4f58-af1b-dc9c380c93dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843670518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1843670518
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.87141815
Short name T1023
Test name
Test status
Simulation time 23445771 ps
CPU time 1.52 seconds
Started Jun 11 01:49:17 PM PDT 24
Finished Jun 11 01:49:20 PM PDT 24
Peak memory 214800 kb
Host smart-32a09b09-da79-4373-85d3-bb75aabf75e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87141815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.87141815
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2284118588
Short name T1067
Test name
Test status
Simulation time 199662169 ps
CPU time 1.62 seconds
Started Jun 11 01:49:12 PM PDT 24
Finished Jun 11 01:49:17 PM PDT 24
Peak memory 206684 kb
Host smart-c4a96606-b694-4fb9-b414-40be6a9cd940
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284118588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2284118588
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1034028711
Short name T1123
Test name
Test status
Simulation time 16137160 ps
CPU time 1.01 seconds
Started Jun 11 01:49:22 PM PDT 24
Finished Jun 11 01:49:25 PM PDT 24
Peak memory 206720 kb
Host smart-21e55fa4-a47e-4e19-9c24-b4db3d00dece
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034028711 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1034028711
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.748645200
Short name T269
Test name
Test status
Simulation time 113010793 ps
CPU time 0.78 seconds
Started Jun 11 01:49:10 PM PDT 24
Finished Jun 11 01:49:13 PM PDT 24
Peak memory 206472 kb
Host smart-065bd3c7-feee-4300-b0ab-74a847497733
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748645200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.748645200
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3750247933
Short name T1070
Test name
Test status
Simulation time 25524146 ps
CPU time 0.9 seconds
Started Jun 11 01:49:12 PM PDT 24
Finished Jun 11 01:49:16 PM PDT 24
Peak memory 206648 kb
Host smart-8be944cd-300f-48c9-9b21-ef3b6495cbcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750247933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3750247933
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2786846875
Short name T1100
Test name
Test status
Simulation time 138609559 ps
CPU time 1.43 seconds
Started Jun 11 01:49:09 PM PDT 24
Finished Jun 11 01:49:12 PM PDT 24
Peak memory 206640 kb
Host smart-da52495f-5a39-48a5-9f4a-d2ee438e8dcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786846875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2786846875
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.4259581460
Short name T1071
Test name
Test status
Simulation time 272015253 ps
CPU time 2.71 seconds
Started Jun 11 01:49:09 PM PDT 24
Finished Jun 11 01:49:14 PM PDT 24
Peak memory 214892 kb
Host smart-fdd5e865-ff47-456e-aee8-4c84babe3069
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259581460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.4259581460
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2540653691
Short name T291
Test name
Test status
Simulation time 332424315 ps
CPU time 2.27 seconds
Started Jun 11 01:49:08 PM PDT 24
Finished Jun 11 01:49:12 PM PDT 24
Peak memory 206652 kb
Host smart-90e1f3e3-0937-460f-aa12-6c2650c74829
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540653691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2540653691
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.991082304
Short name T1036
Test name
Test status
Simulation time 85280418 ps
CPU time 1.2 seconds
Started Jun 11 01:49:10 PM PDT 24
Finished Jun 11 01:49:15 PM PDT 24
Peak memory 214872 kb
Host smart-fd986a86-5a36-45ba-8dda-3f526a48ae99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991082304 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.991082304
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.126614126
Short name T1094
Test name
Test status
Simulation time 16995462 ps
CPU time 0.89 seconds
Started Jun 11 01:49:11 PM PDT 24
Finished Jun 11 01:49:15 PM PDT 24
Peak memory 206636 kb
Host smart-4764953b-8a83-4e67-b169-d85d06c89680
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126614126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.126614126
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.144558427
Short name T1022
Test name
Test status
Simulation time 25773092 ps
CPU time 0.84 seconds
Started Jun 11 01:49:12 PM PDT 24
Finished Jun 11 01:49:16 PM PDT 24
Peak memory 206632 kb
Host smart-33fbc1a5-373a-412a-bcf3-7bc66c8f69ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144558427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.144558427
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1317524335
Short name T281
Test name
Test status
Simulation time 32233886 ps
CPU time 1.3 seconds
Started Jun 11 01:49:13 PM PDT 24
Finished Jun 11 01:49:17 PM PDT 24
Peak memory 206664 kb
Host smart-085ca535-725c-4d88-8d9b-13788c6053f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317524335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1317524335
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1532082720
Short name T1021
Test name
Test status
Simulation time 732185166 ps
CPU time 3.68 seconds
Started Jun 11 01:49:11 PM PDT 24
Finished Jun 11 01:49:18 PM PDT 24
Peak memory 214896 kb
Host smart-5bb89ee3-bfed-4d2b-906c-3c2e8985e988
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532082720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1532082720
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3337312240
Short name T1103
Test name
Test status
Simulation time 60752455 ps
CPU time 1.76 seconds
Started Jun 11 01:49:13 PM PDT 24
Finished Jun 11 01:49:18 PM PDT 24
Peak memory 206680 kb
Host smart-145ecc34-1725-49ba-8e92-5dbe70cb27e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337312240 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3337312240
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3216385870
Short name T401
Test name
Test status
Simulation time 79977472 ps
CPU time 1.2 seconds
Started Jun 11 02:18:14 PM PDT 24
Finished Jun 11 02:18:17 PM PDT 24
Peak memory 218664 kb
Host smart-0e51084c-b951-47e1-a087-c0964dffe4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216385870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3216385870
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2923665398
Short name T749
Test name
Test status
Simulation time 57259326 ps
CPU time 0.88 seconds
Started Jun 11 02:18:11 PM PDT 24
Finished Jun 11 02:18:13 PM PDT 24
Peak memory 206868 kb
Host smart-5f294efd-39da-4063-ba3f-8ba23f301636
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923665398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2923665398
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.1542039806
Short name T489
Test name
Test status
Simulation time 43122160 ps
CPU time 0.89 seconds
Started Jun 11 02:18:12 PM PDT 24
Finished Jun 11 02:18:13 PM PDT 24
Peak memory 216648 kb
Host smart-82ce22f4-98dc-41fd-a55f-2d0b3c1bf371
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542039806 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1542039806
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2752178188
Short name T127
Test name
Test status
Simulation time 51071520 ps
CPU time 1.45 seconds
Started Jun 11 02:18:14 PM PDT 24
Finished Jun 11 02:18:17 PM PDT 24
Peak memory 216996 kb
Host smart-9a024911-d4fc-4fb1-982c-4d7cffa97fd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752178188 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2752178188
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1352984614
Short name T55
Test name
Test status
Simulation time 18339372 ps
CPU time 1.15 seconds
Started Jun 11 02:18:12 PM PDT 24
Finished Jun 11 02:18:13 PM PDT 24
Peak memory 224152 kb
Host smart-45f36329-f330-419f-b699-7069e819310c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352984614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1352984614
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_regwen.434686657
Short name T329
Test name
Test status
Simulation time 83142612 ps
CPU time 0.96 seconds
Started Jun 11 02:18:06 PM PDT 24
Finished Jun 11 02:18:07 PM PDT 24
Peak memory 206928 kb
Host smart-ddb4f57d-df04-4f2c-abfe-434f89002cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434686657 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.434686657
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3966895051
Short name T60
Test name
Test status
Simulation time 487026077 ps
CPU time 8.32 seconds
Started Jun 11 02:18:14 PM PDT 24
Finished Jun 11 02:18:24 PM PDT 24
Peak memory 243204 kb
Host smart-7a8e00a7-5488-44c2-ad24-b157be70edb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966895051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3966895051
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2931784145
Short name T949
Test name
Test status
Simulation time 29008689 ps
CPU time 0.96 seconds
Started Jun 11 02:18:06 PM PDT 24
Finished Jun 11 02:18:08 PM PDT 24
Peak memory 215568 kb
Host smart-3be13130-826a-41f9-b7c2-0011bafa7691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931784145 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2931784145
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.294283703
Short name T925
Test name
Test status
Simulation time 960238632 ps
CPU time 4.25 seconds
Started Jun 11 02:18:05 PM PDT 24
Finished Jun 11 02:18:10 PM PDT 24
Peak memory 217556 kb
Host smart-9920129f-e3a2-4f52-b325-f1fba56f2fb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294283703 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.294283703
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert.218639958
Short name T592
Test name
Test status
Simulation time 25606066 ps
CPU time 1.22 seconds
Started Jun 11 02:18:13 PM PDT 24
Finished Jun 11 02:18:16 PM PDT 24
Peak memory 218816 kb
Host smart-8bb78e4b-ec79-4f00-bb4a-82e2ce5c7472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218639958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.218639958
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable.1375672315
Short name T940
Test name
Test status
Simulation time 24894343 ps
CPU time 0.9 seconds
Started Jun 11 02:18:14 PM PDT 24
Finished Jun 11 02:18:17 PM PDT 24
Peak memory 216820 kb
Host smart-e8bad3e8-b319-4225-a505-a63b724eca6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375672315 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1375672315
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.327186000
Short name T221
Test name
Test status
Simulation time 30792828 ps
CPU time 1.24 seconds
Started Jun 11 02:18:14 PM PDT 24
Finished Jun 11 02:18:17 PM PDT 24
Peak memory 217172 kb
Host smart-2b6eb145-2419-4e9a-8196-61f791776354
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327186000 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_dis
able_auto_req_mode.327186000
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_genbits.702048059
Short name T585
Test name
Test status
Simulation time 83790396 ps
CPU time 1.01 seconds
Started Jun 11 02:18:12 PM PDT 24
Finished Jun 11 02:18:15 PM PDT 24
Peak memory 217772 kb
Host smart-42158685-3de4-4b76-a235-7d109e3b9e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702048059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.702048059
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.286747701
Short name T331
Test name
Test status
Simulation time 44589303 ps
CPU time 0.9 seconds
Started Jun 11 02:18:14 PM PDT 24
Finished Jun 11 02:18:17 PM PDT 24
Peak memory 207580 kb
Host smart-45fb0666-5f77-46fc-bc09-d0a4ec3a3725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286747701 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.286747701
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.1372485671
Short name T467
Test name
Test status
Simulation time 52165787 ps
CPU time 0.96 seconds
Started Jun 11 02:18:12 PM PDT 24
Finished Jun 11 02:18:15 PM PDT 24
Peak memory 215476 kb
Host smart-f1d9f8ee-254d-4753-93ae-f265dfaa184c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372485671 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1372485671
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3243764445
Short name T106
Test name
Test status
Simulation time 176258235 ps
CPU time 1.58 seconds
Started Jun 11 02:18:12 PM PDT 24
Finished Jun 11 02:18:15 PM PDT 24
Peak memory 215700 kb
Host smart-8d9625d3-dc2c-4ab4-9b41-3360cc6f06e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243764445 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3243764445
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.4148101820
Short name T163
Test name
Test status
Simulation time 93842553 ps
CPU time 1.25 seconds
Started Jun 11 02:19:05 PM PDT 24
Finished Jun 11 02:19:08 PM PDT 24
Peak memory 219300 kb
Host smart-6c7924f5-89aa-4d3a-b147-93556b7d7068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148101820 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.4148101820
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.3106867748
Short name T434
Test name
Test status
Simulation time 24704827 ps
CPU time 1.11 seconds
Started Jun 11 02:19:06 PM PDT 24
Finished Jun 11 02:19:09 PM PDT 24
Peak memory 207172 kb
Host smart-8e8c9f02-f0fd-483c-812f-036aa8870b08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106867748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3106867748
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_err.3874955671
Short name T762
Test name
Test status
Simulation time 18730669 ps
CPU time 1.06 seconds
Started Jun 11 02:19:07 PM PDT 24
Finished Jun 11 02:19:09 PM PDT 24
Peak memory 218708 kb
Host smart-ead1bf03-5237-48fd-8f9b-37d533908bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874955671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3874955671
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.414953599
Short name T743
Test name
Test status
Simulation time 211466350 ps
CPU time 1.08 seconds
Started Jun 11 02:19:07 PM PDT 24
Finished Jun 11 02:19:09 PM PDT 24
Peak memory 217560 kb
Host smart-39855aea-c929-45b2-b1b5-d28735260545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414953599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.414953599
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3689526371
Short name T98
Test name
Test status
Simulation time 32154753 ps
CPU time 0.91 seconds
Started Jun 11 02:19:07 PM PDT 24
Finished Jun 11 02:19:09 PM PDT 24
Peak memory 215932 kb
Host smart-1762d190-83c9-4f3b-9dc0-49449a6f875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689526371 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3689526371
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3728658918
Short name T425
Test name
Test status
Simulation time 40370875 ps
CPU time 0.97 seconds
Started Jun 11 02:19:06 PM PDT 24
Finished Jun 11 02:19:08 PM PDT 24
Peak memory 215604 kb
Host smart-05684adb-5d88-4841-929b-9ab360f5bd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728658918 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3728658918
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1784569403
Short name T232
Test name
Test status
Simulation time 20384407687 ps
CPU time 500.77 seconds
Started Jun 11 02:19:05 PM PDT 24
Finished Jun 11 02:27:27 PM PDT 24
Peak memory 223968 kb
Host smart-81e907ef-43bd-4aae-85cd-14b9ba2feecc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784569403 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1784569403
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.2774799735
Short name T173
Test name
Test status
Simulation time 40557286 ps
CPU time 1.15 seconds
Started Jun 11 02:21:48 PM PDT 24
Finished Jun 11 02:21:52 PM PDT 24
Peak memory 219128 kb
Host smart-50b36aa9-900b-43ad-8ff3-cc56f961d373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774799735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.2774799735
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/101.edn_alert.3244339342
Short name T997
Test name
Test status
Simulation time 36228922 ps
CPU time 1.32 seconds
Started Jun 11 02:21:46 PM PDT 24
Finished Jun 11 02:21:50 PM PDT 24
Peak memory 215916 kb
Host smart-78201047-bac2-41b6-87bd-ef151f60c210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244339342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.3244339342
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.4122774178
Short name T945
Test name
Test status
Simulation time 37449051 ps
CPU time 1.32 seconds
Started Jun 11 02:21:48 PM PDT 24
Finished Jun 11 02:21:52 PM PDT 24
Peak memory 218820 kb
Host smart-3edf75d7-4927-4fd3-9c85-96bacf5ac85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122774178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.4122774178
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.2828079934
Short name T254
Test name
Test status
Simulation time 415969683 ps
CPU time 1.29 seconds
Started Jun 11 02:21:46 PM PDT 24
Finished Jun 11 02:21:50 PM PDT 24
Peak memory 218664 kb
Host smart-77b73f71-63f6-4d95-94bb-3b89320fff1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828079934 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.2828079934
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.2075509391
Short name T687
Test name
Test status
Simulation time 54195408 ps
CPU time 1.21 seconds
Started Jun 11 02:21:46 PM PDT 24
Finished Jun 11 02:21:50 PM PDT 24
Peak memory 217752 kb
Host smart-38550a15-bef2-4b42-989f-648314d21419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075509391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2075509391
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.618239574
Short name T764
Test name
Test status
Simulation time 74212477 ps
CPU time 1.15 seconds
Started Jun 11 02:21:49 PM PDT 24
Finished Jun 11 02:21:53 PM PDT 24
Peak memory 218964 kb
Host smart-6137d0a6-4695-4dd8-8a9f-ce82066d9bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618239574 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.618239574
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.2424681987
Short name T506
Test name
Test status
Simulation time 94729199 ps
CPU time 1.33 seconds
Started Jun 11 02:21:45 PM PDT 24
Finished Jun 11 02:21:47 PM PDT 24
Peak memory 217444 kb
Host smart-cff1b73e-74c9-4359-b2b9-443063082d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424681987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2424681987
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.2371710490
Short name T29
Test name
Test status
Simulation time 47080364 ps
CPU time 1.24 seconds
Started Jun 11 02:21:53 PM PDT 24
Finished Jun 11 02:21:56 PM PDT 24
Peak memory 218928 kb
Host smart-debf82d0-97a2-4cb9-a806-90155aa2f399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371710490 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.2371710490
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.684750625
Short name T48
Test name
Test status
Simulation time 91244840 ps
CPU time 1.97 seconds
Started Jun 11 02:21:48 PM PDT 24
Finished Jun 11 02:21:54 PM PDT 24
Peak memory 220452 kb
Host smart-e911e94e-a628-430e-bcb9-2f5ccd03e000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684750625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.684750625
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.1338188276
Short name T652
Test name
Test status
Simulation time 30074997 ps
CPU time 1.3 seconds
Started Jun 11 02:21:48 PM PDT 24
Finished Jun 11 02:21:52 PM PDT 24
Peak memory 220036 kb
Host smart-5e6c96e0-537e-4c38-b929-6e73ceb9e35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338188276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.1338188276
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.2846828068
Short name T483
Test name
Test status
Simulation time 71542541 ps
CPU time 2.47 seconds
Started Jun 11 02:21:48 PM PDT 24
Finished Jun 11 02:21:53 PM PDT 24
Peak memory 218828 kb
Host smart-55c81391-b65c-4602-b9eb-affc050772a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846828068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2846828068
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.3547219918
Short name T600
Test name
Test status
Simulation time 48676877 ps
CPU time 1.13 seconds
Started Jun 11 02:21:50 PM PDT 24
Finished Jun 11 02:21:54 PM PDT 24
Peak memory 218996 kb
Host smart-93d85eea-3e31-45ea-a896-a27663f872c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547219918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3547219918
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.3729332451
Short name T493
Test name
Test status
Simulation time 44165916 ps
CPU time 1.48 seconds
Started Jun 11 02:21:46 PM PDT 24
Finished Jun 11 02:21:49 PM PDT 24
Peak memory 217616 kb
Host smart-880b614f-e49b-48bb-a808-09ce7dff167e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729332451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3729332451
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.217921184
Short name T421
Test name
Test status
Simulation time 46950489 ps
CPU time 1.27 seconds
Started Jun 11 02:21:45 PM PDT 24
Finished Jun 11 02:21:47 PM PDT 24
Peak memory 219876 kb
Host smart-bdcd0178-10da-49b4-a458-e5b7d0cbbf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217921184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.217921184
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.3359087174
Short name T525
Test name
Test status
Simulation time 30977051 ps
CPU time 1.34 seconds
Started Jun 11 02:21:47 PM PDT 24
Finished Jun 11 02:21:51 PM PDT 24
Peak memory 218940 kb
Host smart-7a540bff-2d4b-4f71-9b4c-e80927832ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359087174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3359087174
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.2570229549
Short name T149
Test name
Test status
Simulation time 33007252 ps
CPU time 1.23 seconds
Started Jun 11 02:21:49 PM PDT 24
Finished Jun 11 02:21:54 PM PDT 24
Peak memory 218740 kb
Host smart-111d237d-0bb3-4a60-8ea4-238ef6aa3657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570229549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.2570229549
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.4223008411
Short name T627
Test name
Test status
Simulation time 93828546 ps
CPU time 1.25 seconds
Started Jun 11 02:21:46 PM PDT 24
Finished Jun 11 02:21:50 PM PDT 24
Peak memory 219376 kb
Host smart-ca842dee-0056-4ef8-abb2-77796ead6907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223008411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.4223008411
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.716899187
Short name T287
Test name
Test status
Simulation time 26030247 ps
CPU time 1.29 seconds
Started Jun 11 02:21:48 PM PDT 24
Finished Jun 11 02:21:52 PM PDT 24
Peak memory 220600 kb
Host smart-8b09bfed-a740-4b8e-9718-43c08f03b3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716899187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.716899187
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert.3899542805
Short name T475
Test name
Test status
Simulation time 24294034 ps
CPU time 1.21 seconds
Started Jun 11 02:19:05 PM PDT 24
Finished Jun 11 02:19:07 PM PDT 24
Peak memory 219692 kb
Host smart-97c825b1-84ba-48ab-8588-0040c3c97a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899542805 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3899542805
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.4055257368
Short name T968
Test name
Test status
Simulation time 34656778 ps
CPU time 0.86 seconds
Started Jun 11 02:19:05 PM PDT 24
Finished Jun 11 02:19:07 PM PDT 24
Peak memory 207060 kb
Host smart-eb04de44-ffc9-484e-8293-2d2518340729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055257368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.4055257368
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3870381401
Short name T562
Test name
Test status
Simulation time 18595757 ps
CPU time 0.86 seconds
Started Jun 11 02:19:07 PM PDT 24
Finished Jun 11 02:19:09 PM PDT 24
Peak memory 216516 kb
Host smart-3daf5d15-e699-40f0-a0ca-e39ef7a35865
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870381401 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3870381401
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_genbits.118085503
Short name T328
Test name
Test status
Simulation time 65386280 ps
CPU time 2.18 seconds
Started Jun 11 02:19:08 PM PDT 24
Finished Jun 11 02:19:11 PM PDT 24
Peak memory 218520 kb
Host smart-ae1d37c4-43e2-43ee-b5de-1d5815fc6ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118085503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.118085503
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1531799209
Short name T31
Test name
Test status
Simulation time 21273764 ps
CPU time 0.98 seconds
Started Jun 11 02:19:08 PM PDT 24
Finished Jun 11 02:19:10 PM PDT 24
Peak memory 216136 kb
Host smart-e56b52eb-5a5e-4f39-b805-bcae3f5603cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531799209 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1531799209
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.682479888
Short name T353
Test name
Test status
Simulation time 41802721 ps
CPU time 0.9 seconds
Started Jun 11 02:19:08 PM PDT 24
Finished Jun 11 02:19:10 PM PDT 24
Peak memory 215600 kb
Host smart-1668e468-262a-4c52-b2ea-f2882605dd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682479888 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.682479888
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3925007413
Short name T626
Test name
Test status
Simulation time 373636402160 ps
CPU time 758.04 seconds
Started Jun 11 02:19:06 PM PDT 24
Finished Jun 11 02:31:46 PM PDT 24
Peak memory 221448 kb
Host smart-cf58e8c3-b386-44d7-a566-a19b6b45ff4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925007413 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3925007413
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.3520116153
Short name T195
Test name
Test status
Simulation time 46758158 ps
CPU time 1.21 seconds
Started Jun 11 02:21:48 PM PDT 24
Finished Jun 11 02:21:53 PM PDT 24
Peak memory 220404 kb
Host smart-03aa8388-cadd-4408-b7e3-4381c57080d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520116153 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.3520116153
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.2675352102
Short name T851
Test name
Test status
Simulation time 49379833 ps
CPU time 1.19 seconds
Started Jun 11 02:21:47 PM PDT 24
Finished Jun 11 02:21:52 PM PDT 24
Peak memory 217624 kb
Host smart-56780b86-6cb9-432a-8901-9b0b5943fba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675352102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2675352102
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.72014776
Short name T845
Test name
Test status
Simulation time 179139250 ps
CPU time 1.33 seconds
Started Jun 11 02:21:45 PM PDT 24
Finished Jun 11 02:21:47 PM PDT 24
Peak memory 219744 kb
Host smart-99c0a655-f3c7-4c92-ad7b-29775922eeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72014776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.72014776
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.1612139210
Short name T422
Test name
Test status
Simulation time 84775685 ps
CPU time 1.25 seconds
Started Jun 11 02:21:46 PM PDT 24
Finished Jun 11 02:21:51 PM PDT 24
Peak memory 215508 kb
Host smart-e3a51b2c-268a-439c-a74f-56c1360dc6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612139210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1612139210
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.2826637011
Short name T169
Test name
Test status
Simulation time 44386097 ps
CPU time 1.14 seconds
Started Jun 11 02:21:47 PM PDT 24
Finished Jun 11 02:21:51 PM PDT 24
Peak memory 219276 kb
Host smart-b4729ef6-4a46-4d77-a091-9d2e41bca167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826637011 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.2826637011
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.352573029
Short name T89
Test name
Test status
Simulation time 47650461 ps
CPU time 1.52 seconds
Started Jun 11 02:21:47 PM PDT 24
Finished Jun 11 02:21:52 PM PDT 24
Peak memory 217452 kb
Host smart-2b9b75e6-9ea8-4cc8-94e6-41112b0d71fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352573029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.352573029
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.1990465258
Short name T42
Test name
Test status
Simulation time 417097334 ps
CPU time 5.36 seconds
Started Jun 11 02:21:45 PM PDT 24
Finished Jun 11 02:21:52 PM PDT 24
Peak memory 218984 kb
Host smart-a6f1da45-3b2f-4152-917d-fd1dbd4c7c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990465258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1990465258
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.2272210321
Short name T983
Test name
Test status
Simulation time 26629575 ps
CPU time 1.26 seconds
Started Jun 11 02:21:46 PM PDT 24
Finished Jun 11 02:21:49 PM PDT 24
Peak memory 218588 kb
Host smart-a8557b51-31ac-4cba-a568-b219d3e0d919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272210321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.2272210321
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.2109064698
Short name T423
Test name
Test status
Simulation time 101386432 ps
CPU time 1.29 seconds
Started Jun 11 02:21:49 PM PDT 24
Finished Jun 11 02:21:53 PM PDT 24
Peak memory 218584 kb
Host smart-3a094c2c-848d-4b7e-b218-afac7a12d2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109064698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2109064698
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.1087204370
Short name T135
Test name
Test status
Simulation time 63587405 ps
CPU time 1.14 seconds
Started Jun 11 02:21:49 PM PDT 24
Finished Jun 11 02:21:53 PM PDT 24
Peak memory 218680 kb
Host smart-dc5e68d2-d2f8-4d01-80ab-bd391ad9315a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087204370 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.1087204370
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/116.edn_alert.3113900425
Short name T850
Test name
Test status
Simulation time 47325444 ps
CPU time 1.24 seconds
Started Jun 11 02:22:02 PM PDT 24
Finished Jun 11 02:22:04 PM PDT 24
Peak memory 220152 kb
Host smart-89bf2f86-d0b4-45ff-8b7b-bc9673390661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113900425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.3113900425
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.4273121023
Short name T445
Test name
Test status
Simulation time 37564712 ps
CPU time 1.5 seconds
Started Jun 11 02:21:54 PM PDT 24
Finished Jun 11 02:21:56 PM PDT 24
Peak memory 217800 kb
Host smart-1a60cd27-afdc-4962-b938-bb5b6ffc19a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273121023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.4273121023
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.4083740724
Short name T375
Test name
Test status
Simulation time 51481400 ps
CPU time 1.24 seconds
Started Jun 11 02:21:45 PM PDT 24
Finished Jun 11 02:21:48 PM PDT 24
Peak memory 218988 kb
Host smart-0b58911c-0a7c-4b48-a695-0e20d2f987c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083740724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.4083740724
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.4181723228
Short name T941
Test name
Test status
Simulation time 54900253 ps
CPU time 1.3 seconds
Started Jun 11 02:21:45 PM PDT 24
Finished Jun 11 02:21:47 PM PDT 24
Peak memory 220772 kb
Host smart-9574c965-35b9-4cc8-bd73-f1772a8d8a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181723228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.4181723228
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.3385285518
Short name T793
Test name
Test status
Simulation time 77206322 ps
CPU time 1.41 seconds
Started Jun 11 02:21:49 PM PDT 24
Finished Jun 11 02:21:53 PM PDT 24
Peak memory 218616 kb
Host smart-8630056c-04eb-446d-b5a6-3bcbc2e0db17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385285518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3385285518
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.2810501651
Short name T809
Test name
Test status
Simulation time 48443018 ps
CPU time 1.34 seconds
Started Jun 11 02:21:55 PM PDT 24
Finished Jun 11 02:21:57 PM PDT 24
Peak memory 220144 kb
Host smart-95e15cb2-0bbd-4296-9a4c-9d62561a5d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810501651 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.2810501651
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.75779562
Short name T776
Test name
Test status
Simulation time 40394727 ps
CPU time 1.69 seconds
Started Jun 11 02:21:45 PM PDT 24
Finished Jun 11 02:21:49 PM PDT 24
Peak memory 218776 kb
Host smart-ec80cd61-73ca-47eb-a34f-3b738ad94950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75779562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.75779562
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.3773963547
Short name T655
Test name
Test status
Simulation time 144677280 ps
CPU time 1.25 seconds
Started Jun 11 02:19:06 PM PDT 24
Finished Jun 11 02:19:08 PM PDT 24
Peak memory 220056 kb
Host smart-a95c4e64-7aae-427d-9f4e-d8127d2884ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773963547 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3773963547
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.1627115619
Short name T72
Test name
Test status
Simulation time 35062902 ps
CPU time 0.84 seconds
Started Jun 11 02:19:01 PM PDT 24
Finished Jun 11 02:19:03 PM PDT 24
Peak memory 206924 kb
Host smart-ee38ceb3-a2c7-418e-9650-8b6d1e9a917c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627115619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1627115619
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.3307759116
Short name T226
Test name
Test status
Simulation time 35999599 ps
CPU time 0.91 seconds
Started Jun 11 02:19:08 PM PDT 24
Finished Jun 11 02:19:10 PM PDT 24
Peak memory 216724 kb
Host smart-64bfba16-5a48-4f3b-903a-c30650f2fbdc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307759116 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3307759116
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3471810886
Short name T513
Test name
Test status
Simulation time 46033882 ps
CPU time 1.33 seconds
Started Jun 11 02:19:07 PM PDT 24
Finished Jun 11 02:19:09 PM PDT 24
Peak memory 217236 kb
Host smart-739534b1-cc77-4a87-ad52-8f72c5acd97c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471810886 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3471810886
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.1481608405
Short name T180
Test name
Test status
Simulation time 29926163 ps
CPU time 1.02 seconds
Started Jun 11 02:19:07 PM PDT 24
Finished Jun 11 02:19:09 PM PDT 24
Peak memory 224040 kb
Host smart-7f84c7c0-988b-43c1-a1f1-b29c3cdd8841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481608405 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1481608405
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1158665849
Short name T595
Test name
Test status
Simulation time 472170063 ps
CPU time 5.32 seconds
Started Jun 11 02:19:05 PM PDT 24
Finished Jun 11 02:19:11 PM PDT 24
Peak memory 217656 kb
Host smart-eef7de66-a292-4b4a-8b57-24392e33791d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158665849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1158665849
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.771002983
Short name T35
Test name
Test status
Simulation time 37860668 ps
CPU time 0.94 seconds
Started Jun 11 02:19:04 PM PDT 24
Finished Jun 11 02:19:05 PM PDT 24
Peak memory 216148 kb
Host smart-8b5d9212-ba68-4c13-a276-5e2826ced3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771002983 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.771002983
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2549779861
Short name T875
Test name
Test status
Simulation time 39878799 ps
CPU time 0.91 seconds
Started Jun 11 02:19:08 PM PDT 24
Finished Jun 11 02:19:10 PM PDT 24
Peak memory 215560 kb
Host smart-b3c919fa-b315-454a-be98-e628d5827856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549779861 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2549779861
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1768685417
Short name T548
Test name
Test status
Simulation time 378369687 ps
CPU time 7.7 seconds
Started Jun 11 02:19:06 PM PDT 24
Finished Jun 11 02:19:15 PM PDT 24
Peak memory 217476 kb
Host smart-c6c9967f-9e3d-444e-80be-c313ca8c7b10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768685417 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1768685417
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.142874303
Short name T646
Test name
Test status
Simulation time 221865378428 ps
CPU time 570.86 seconds
Started Jun 11 02:19:06 PM PDT 24
Finished Jun 11 02:28:37 PM PDT 24
Peak memory 220224 kb
Host smart-2eb532dd-db86-4924-a6a4-524c58bae88d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142874303 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.142874303
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.361489910
Short name T286
Test name
Test status
Simulation time 64043059 ps
CPU time 1.29 seconds
Started Jun 11 02:21:45 PM PDT 24
Finished Jun 11 02:21:47 PM PDT 24
Peak memory 220044 kb
Host smart-3824ad14-868f-43fd-be98-cdc187597a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361489910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.361489910
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.2762865078
Short name T462
Test name
Test status
Simulation time 64473631 ps
CPU time 1.63 seconds
Started Jun 11 02:21:45 PM PDT 24
Finished Jun 11 02:21:48 PM PDT 24
Peak memory 218904 kb
Host smart-14466506-a868-4021-9d89-667255efb05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762865078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2762865078
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.3148453857
Short name T80
Test name
Test status
Simulation time 200134258 ps
CPU time 1.14 seconds
Started Jun 11 02:21:49 PM PDT 24
Finished Jun 11 02:21:53 PM PDT 24
Peak memory 219748 kb
Host smart-897c1990-6890-4e8a-8000-935396ca74b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148453857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3148453857
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.226704520
Short name T495
Test name
Test status
Simulation time 33148243 ps
CPU time 1.38 seconds
Started Jun 11 02:21:49 PM PDT 24
Finished Jun 11 02:21:54 PM PDT 24
Peak memory 218616 kb
Host smart-1b8c7807-7a52-4038-a066-7a67841d0893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226704520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.226704520
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.3379873705
Short name T784
Test name
Test status
Simulation time 83288025 ps
CPU time 1.15 seconds
Started Jun 11 02:21:50 PM PDT 24
Finished Jun 11 02:21:54 PM PDT 24
Peak memory 219964 kb
Host smart-f46bc33d-2fad-4c41-bd12-1d19e7c2654f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379873705 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.3379873705
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.543459318
Short name T979
Test name
Test status
Simulation time 44136480 ps
CPU time 1.53 seconds
Started Jun 11 02:21:47 PM PDT 24
Finished Jun 11 02:21:52 PM PDT 24
Peak memory 218916 kb
Host smart-32e34c82-b8c0-45e5-9193-dc84de041481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543459318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.543459318
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.3538584633
Short name T50
Test name
Test status
Simulation time 162663747 ps
CPU time 1.2 seconds
Started Jun 11 02:21:47 PM PDT 24
Finished Jun 11 02:21:51 PM PDT 24
Peak memory 219844 kb
Host smart-7a04321f-5d0e-4c24-8670-9bbdcac687e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538584633 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.3538584633
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/124.edn_alert.4255490516
Short name T49
Test name
Test status
Simulation time 63651134 ps
CPU time 1.05 seconds
Started Jun 11 02:21:53 PM PDT 24
Finished Jun 11 02:21:56 PM PDT 24
Peak memory 220084 kb
Host smart-3738db20-8db2-4df5-85bb-abb6b535c8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255490516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.4255490516
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.414010518
Short name T792
Test name
Test status
Simulation time 37367633 ps
CPU time 1.52 seconds
Started Jun 11 02:21:47 PM PDT 24
Finished Jun 11 02:21:52 PM PDT 24
Peak memory 219504 kb
Host smart-a5c2a9ab-e421-4a8f-b7c0-6ff7bb09045e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414010518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.414010518
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.1578680981
Short name T530
Test name
Test status
Simulation time 29242360 ps
CPU time 1.32 seconds
Started Jun 11 02:21:46 PM PDT 24
Finished Jun 11 02:21:51 PM PDT 24
Peak memory 219940 kb
Host smart-4d160a1d-2e12-48ef-89d2-fe471f5b3c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578680981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.1578680981
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/126.edn_alert.998756668
Short name T304
Test name
Test status
Simulation time 21509272 ps
CPU time 1.13 seconds
Started Jun 11 02:21:48 PM PDT 24
Finished Jun 11 02:21:53 PM PDT 24
Peak memory 219752 kb
Host smart-e78db244-b5e9-4e43-a57e-286ea734995a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998756668 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.998756668
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.919587639
Short name T499
Test name
Test status
Simulation time 95305336 ps
CPU time 1.04 seconds
Started Jun 11 02:21:49 PM PDT 24
Finished Jun 11 02:21:53 PM PDT 24
Peak memory 217676 kb
Host smart-13f0c0e4-894d-417c-a84d-d831f968e45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919587639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.919587639
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.1619125008
Short name T877
Test name
Test status
Simulation time 39847220 ps
CPU time 1.11 seconds
Started Jun 11 02:21:55 PM PDT 24
Finished Jun 11 02:21:56 PM PDT 24
Peak memory 218584 kb
Host smart-7298d732-daf7-42b0-821d-6705fa20fe2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619125008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.1619125008
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.2661605711
Short name T954
Test name
Test status
Simulation time 37992507 ps
CPU time 1.32 seconds
Started Jun 11 02:21:45 PM PDT 24
Finished Jun 11 02:21:49 PM PDT 24
Peak memory 217492 kb
Host smart-5c310cdc-0205-43e3-a108-594d9c20d78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661605711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2661605711
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.3900529254
Short name T681
Test name
Test status
Simulation time 155135844 ps
CPU time 1.27 seconds
Started Jun 11 02:22:01 PM PDT 24
Finished Jun 11 02:22:03 PM PDT 24
Peak memory 220580 kb
Host smart-e1180afd-7ffb-4c85-9bdf-e824b1480478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900529254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.3900529254
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.522643416
Short name T510
Test name
Test status
Simulation time 49498606 ps
CPU time 1.44 seconds
Started Jun 11 02:21:50 PM PDT 24
Finished Jun 11 02:21:54 PM PDT 24
Peak memory 220212 kb
Host smart-05fb4889-e985-4c03-a380-6f3fbfd6149b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522643416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.522643416
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.2187134452
Short name T886
Test name
Test status
Simulation time 39590607 ps
CPU time 1.11 seconds
Started Jun 11 02:22:04 PM PDT 24
Finished Jun 11 02:22:06 PM PDT 24
Peak memory 219792 kb
Host smart-910963e8-987c-4245-a729-e8696100519e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187134452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.2187134452
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert.3146754229
Short name T796
Test name
Test status
Simulation time 97462494 ps
CPU time 1.3 seconds
Started Jun 11 02:19:14 PM PDT 24
Finished Jun 11 02:19:17 PM PDT 24
Peak memory 219980 kb
Host smart-58b68630-4143-41a9-b63b-f0dce815d495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146754229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3146754229
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.1460051787
Short name T344
Test name
Test status
Simulation time 40802477 ps
CPU time 0.86 seconds
Started Jun 11 02:19:18 PM PDT 24
Finished Jun 11 02:19:20 PM PDT 24
Peak memory 206872 kb
Host smart-c902100d-917e-4c88-9178-8c3e52c6ea4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460051787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1460051787
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.165153045
Short name T980
Test name
Test status
Simulation time 22269767 ps
CPU time 0.87 seconds
Started Jun 11 02:19:15 PM PDT 24
Finished Jun 11 02:19:16 PM PDT 24
Peak memory 216276 kb
Host smart-e60f0fc8-422a-414e-85fb-426fcce9a463
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165153045 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.165153045
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3519686005
Short name T155
Test name
Test status
Simulation time 35413993 ps
CPU time 1.31 seconds
Started Jun 11 02:19:20 PM PDT 24
Finished Jun 11 02:19:22 PM PDT 24
Peak memory 217080 kb
Host smart-5fe0b00b-71c6-4724-8c96-26308af6912b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519686005 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3519686005
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3901197494
Short name T756
Test name
Test status
Simulation time 37297407 ps
CPU time 0.96 seconds
Started Jun 11 02:19:18 PM PDT 24
Finished Jun 11 02:19:20 PM PDT 24
Peak memory 220144 kb
Host smart-81f38d05-210c-4ba9-82a5-0633c47a3736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901197494 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3901197494
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.4134398027
Short name T430
Test name
Test status
Simulation time 54592267 ps
CPU time 1.4 seconds
Started Jun 11 02:19:18 PM PDT 24
Finished Jun 11 02:19:21 PM PDT 24
Peak memory 218912 kb
Host smart-3f53f51b-2b6d-4a5e-a6ad-5818049fc06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134398027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.4134398027
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3587220256
Short name T365
Test name
Test status
Simulation time 21410206 ps
CPU time 1.16 seconds
Started Jun 11 02:19:17 PM PDT 24
Finished Jun 11 02:19:20 PM PDT 24
Peak memory 215940 kb
Host smart-a7e1d93b-427f-4f62-8883-3ae2fdb27b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587220256 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3587220256
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.628153837
Short name T539
Test name
Test status
Simulation time 20008686 ps
CPU time 1.11 seconds
Started Jun 11 02:19:15 PM PDT 24
Finished Jun 11 02:19:17 PM PDT 24
Peak memory 215592 kb
Host smart-c1cae48d-b2bf-451a-af8f-63221e44ac75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628153837 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.628153837
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.271798647
Short name T396
Test name
Test status
Simulation time 1767170016 ps
CPU time 4.57 seconds
Started Jun 11 02:19:15 PM PDT 24
Finished Jun 11 02:19:20 PM PDT 24
Peak memory 215596 kb
Host smart-1dea8f08-2f5b-4c49-aeda-67224de8998f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271798647 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.271798647
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2996766681
Short name T6
Test name
Test status
Simulation time 82180380981 ps
CPU time 980.75 seconds
Started Jun 11 02:19:24 PM PDT 24
Finished Jun 11 02:35:46 PM PDT 24
Peak memory 221396 kb
Host smart-5ba64bab-574d-49a2-9f93-66549128f825
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996766681 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2996766681
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.2387572186
Short name T755
Test name
Test status
Simulation time 46852066 ps
CPU time 1.17 seconds
Started Jun 11 02:22:00 PM PDT 24
Finished Jun 11 02:22:03 PM PDT 24
Peak memory 219452 kb
Host smart-53043e50-d78a-4c85-aad8-aa4d22b79831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387572186 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2387572186
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.1736580013
Short name T20
Test name
Test status
Simulation time 41302632 ps
CPU time 1.8 seconds
Started Jun 11 02:22:04 PM PDT 24
Finished Jun 11 02:22:07 PM PDT 24
Peak memory 218900 kb
Host smart-ad190209-ff51-4254-a4f8-c6b28eb80338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736580013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1736580013
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.471074381
Short name T671
Test name
Test status
Simulation time 32154673 ps
CPU time 1.3 seconds
Started Jun 11 02:22:02 PM PDT 24
Finished Jun 11 02:22:04 PM PDT 24
Peak memory 219928 kb
Host smart-4a968f08-7f50-4793-8b64-5b2b8fc3c7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471074381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.471074381
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.1302253296
Short name T912
Test name
Test status
Simulation time 77974843 ps
CPU time 1.16 seconds
Started Jun 11 02:22:05 PM PDT 24
Finished Jun 11 02:22:08 PM PDT 24
Peak memory 217584 kb
Host smart-67623704-62bc-4630-89de-efcdd74dff34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302253296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1302253296
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.3611710447
Short name T170
Test name
Test status
Simulation time 231153269 ps
CPU time 1.31 seconds
Started Jun 11 02:22:04 PM PDT 24
Finished Jun 11 02:22:06 PM PDT 24
Peak memory 215900 kb
Host smart-b0fcab12-8fb7-4060-ba2d-c68a0b354dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611710447 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.3611710447
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.2333284841
Short name T632
Test name
Test status
Simulation time 80975906 ps
CPU time 1.2 seconds
Started Jun 11 02:22:00 PM PDT 24
Finished Jun 11 02:22:02 PM PDT 24
Peak memory 219092 kb
Host smart-32cd4098-7f07-4939-802c-4be7bca35a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333284841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2333284841
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.1428097275
Short name T599
Test name
Test status
Simulation time 326027082 ps
CPU time 1.31 seconds
Started Jun 11 02:22:06 PM PDT 24
Finished Jun 11 02:22:08 PM PDT 24
Peak memory 219496 kb
Host smart-4e1fc14c-9970-4266-b9a5-7534e07679c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428097275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.1428097275
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.2240741031
Short name T712
Test name
Test status
Simulation time 210674094 ps
CPU time 3.11 seconds
Started Jun 11 02:22:06 PM PDT 24
Finished Jun 11 02:22:11 PM PDT 24
Peak memory 217980 kb
Host smart-a233170e-41c2-4aa5-909a-1f14f8e142d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240741031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2240741031
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.3139067070
Short name T707
Test name
Test status
Simulation time 24343650 ps
CPU time 1.18 seconds
Started Jun 11 02:22:03 PM PDT 24
Finished Jun 11 02:22:05 PM PDT 24
Peak memory 218840 kb
Host smart-01a22b0c-ca30-47f6-8e07-a8e69cb8dc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139067070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.3139067070
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.2680171415
Short name T689
Test name
Test status
Simulation time 31310639 ps
CPU time 1.31 seconds
Started Jun 11 02:22:03 PM PDT 24
Finished Jun 11 02:22:05 PM PDT 24
Peak memory 220360 kb
Host smart-247944f6-d10e-4f69-8dfc-4babb4e5ccdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680171415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2680171415
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.2435374836
Short name T700
Test name
Test status
Simulation time 27644823 ps
CPU time 1.24 seconds
Started Jun 11 02:22:02 PM PDT 24
Finished Jun 11 02:22:04 PM PDT 24
Peak memory 221016 kb
Host smart-8a8340e1-bc83-4679-a85d-418126dbd48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435374836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.2435374836
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.1408911393
Short name T9
Test name
Test status
Simulation time 63876610 ps
CPU time 1.31 seconds
Started Jun 11 02:22:02 PM PDT 24
Finished Jun 11 02:22:04 PM PDT 24
Peak memory 220080 kb
Host smart-a256ab72-d3ae-43fb-b025-5c341ecc9688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408911393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1408911393
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.4281935680
Short name T584
Test name
Test status
Simulation time 29737355 ps
CPU time 1.34 seconds
Started Jun 11 02:22:05 PM PDT 24
Finished Jun 11 02:22:07 PM PDT 24
Peak memory 221004 kb
Host smart-ac819c82-b56f-4e25-ba59-78478449d445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281935680 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.4281935680
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.266354868
Short name T589
Test name
Test status
Simulation time 111057777 ps
CPU time 1.83 seconds
Started Jun 11 02:22:06 PM PDT 24
Finished Jun 11 02:22:10 PM PDT 24
Peak memory 219380 kb
Host smart-ffac101c-5024-40f3-918a-0a427dad9866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266354868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.266354868
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.3269617865
Short name T225
Test name
Test status
Simulation time 46130175 ps
CPU time 1.29 seconds
Started Jun 11 02:22:07 PM PDT 24
Finished Jun 11 02:22:10 PM PDT 24
Peak memory 220684 kb
Host smart-7675a970-eac0-4d1d-9d98-97723f5fcbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269617865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.3269617865
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.3946917943
Short name T823
Test name
Test status
Simulation time 45734776 ps
CPU time 1.53 seconds
Started Jun 11 02:22:06 PM PDT 24
Finished Jun 11 02:22:09 PM PDT 24
Peak memory 217828 kb
Host smart-ba11db36-98b1-4174-89ce-85d4b9015424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946917943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3946917943
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.3170997991
Short name T178
Test name
Test status
Simulation time 30291482 ps
CPU time 1.32 seconds
Started Jun 11 02:22:06 PM PDT 24
Finished Jun 11 02:22:09 PM PDT 24
Peak memory 220904 kb
Host smart-2db1626c-ff2b-4f33-8ce6-557b370bf239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170997991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3170997991
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.1535932555
Short name T442
Test name
Test status
Simulation time 61160485 ps
CPU time 1.54 seconds
Started Jun 11 02:21:59 PM PDT 24
Finished Jun 11 02:22:01 PM PDT 24
Peak memory 220088 kb
Host smart-5c194325-711f-4b64-9e58-f5686586a90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535932555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1535932555
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.2915524447
Short name T711
Test name
Test status
Simulation time 21033736 ps
CPU time 1.21 seconds
Started Jun 11 02:22:01 PM PDT 24
Finished Jun 11 02:22:03 PM PDT 24
Peak memory 219772 kb
Host smart-69ac8864-b2a1-4817-b836-1b956b7dbc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915524447 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.2915524447
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.3177213614
Short name T2
Test name
Test status
Simulation time 82590454 ps
CPU time 1.21 seconds
Started Jun 11 02:22:05 PM PDT 24
Finished Jun 11 02:22:08 PM PDT 24
Peak memory 219604 kb
Host smart-15d322a0-5b89-49ea-b81b-b6983cd09427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177213614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3177213614
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert_test.3900973491
Short name T798
Test name
Test status
Simulation time 41883935 ps
CPU time 0.84 seconds
Started Jun 11 02:19:15 PM PDT 24
Finished Jun 11 02:19:17 PM PDT 24
Peak memory 207220 kb
Host smart-1e413c5a-0a66-4a47-92f2-d9b4ff916fdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900973491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3900973491
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.3065159907
Short name T216
Test name
Test status
Simulation time 12164580 ps
CPU time 0.91 seconds
Started Jun 11 02:19:16 PM PDT 24
Finished Jun 11 02:19:18 PM PDT 24
Peak memory 216480 kb
Host smart-59a1f5f2-0b24-44be-97db-b514142418c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065159907 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3065159907
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1120944767
Short name T608
Test name
Test status
Simulation time 83397033 ps
CPU time 1.23 seconds
Started Jun 11 02:19:19 PM PDT 24
Finished Jun 11 02:19:21 PM PDT 24
Peak memory 217128 kb
Host smart-51d1f2eb-4da9-4bdd-8cf9-7e17ab56daf9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120944767 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1120944767
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2282633764
Short name T120
Test name
Test status
Simulation time 35065028 ps
CPU time 1.06 seconds
Started Jun 11 02:19:15 PM PDT 24
Finished Jun 11 02:19:17 PM PDT 24
Peak memory 230004 kb
Host smart-a64e4095-15d3-4b50-801a-69c5773cb9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282633764 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2282633764
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3972768346
Short name T573
Test name
Test status
Simulation time 61727376 ps
CPU time 1.27 seconds
Started Jun 11 02:19:17 PM PDT 24
Finished Jun 11 02:19:19 PM PDT 24
Peak memory 219100 kb
Host smart-890b8e96-bef1-4e9b-8912-2f42d1632498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972768346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3972768346
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3614554529
Short name T583
Test name
Test status
Simulation time 45215322 ps
CPU time 0.88 seconds
Started Jun 11 02:19:20 PM PDT 24
Finished Jun 11 02:19:21 PM PDT 24
Peak memory 215584 kb
Host smart-0d5b87d5-133a-4197-a1ca-396852c2066f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614554529 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3614554529
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2103711309
Short name T959
Test name
Test status
Simulation time 15098514 ps
CPU time 0.99 seconds
Started Jun 11 02:19:23 PM PDT 24
Finished Jun 11 02:19:25 PM PDT 24
Peak memory 215596 kb
Host smart-d561f1c4-7e0c-4821-85c1-b47a5adda931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103711309 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2103711309
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2540062657
Short name T643
Test name
Test status
Simulation time 324848717 ps
CPU time 3.92 seconds
Started Jun 11 02:19:16 PM PDT 24
Finished Jun 11 02:19:21 PM PDT 24
Peak memory 215532 kb
Host smart-8730ba28-dc82-454a-b02f-8c459dd0634d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540062657 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2540062657
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.217708225
Short name T452
Test name
Test status
Simulation time 33219271054 ps
CPU time 416.58 seconds
Started Jun 11 02:19:17 PM PDT 24
Finished Jun 11 02:26:15 PM PDT 24
Peak memory 218084 kb
Host smart-6aced995-5079-41c6-b181-a8975c5e5bee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217708225 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.217708225
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.1736110535
Short name T550
Test name
Test status
Simulation time 25749047 ps
CPU time 1.22 seconds
Started Jun 11 02:22:06 PM PDT 24
Finished Jun 11 02:22:09 PM PDT 24
Peak memory 220372 kb
Host smart-ea79df6f-2c7d-463d-8451-5b23e95d5545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736110535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.1736110535
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.805993200
Short name T75
Test name
Test status
Simulation time 97135594 ps
CPU time 1.23 seconds
Started Jun 11 02:22:04 PM PDT 24
Finished Jun 11 02:22:06 PM PDT 24
Peak memory 217472 kb
Host smart-79c6854d-d9dd-40f1-b875-3a37d0815aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805993200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.805993200
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.1272427612
Short name T986
Test name
Test status
Simulation time 39853780 ps
CPU time 1.23 seconds
Started Jun 11 02:22:00 PM PDT 24
Finished Jun 11 02:22:02 PM PDT 24
Peak memory 219180 kb
Host smart-29ccbd1a-87dc-4135-8b9c-a3a08fd9e3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272427612 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.1272427612
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.2955815137
Short name T994
Test name
Test status
Simulation time 44024600 ps
CPU time 1.16 seconds
Started Jun 11 02:22:05 PM PDT 24
Finished Jun 11 02:22:08 PM PDT 24
Peak memory 220312 kb
Host smart-2729f9a0-7073-47e2-8464-7c833293f325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955815137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2955815137
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.1502439308
Short name T392
Test name
Test status
Simulation time 77544786 ps
CPU time 1.29 seconds
Started Jun 11 02:22:06 PM PDT 24
Finished Jun 11 02:22:09 PM PDT 24
Peak memory 219112 kb
Host smart-51e76a39-05a2-44e2-9baa-8f2254648c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502439308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1502439308
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.1557059075
Short name T684
Test name
Test status
Simulation time 40824013 ps
CPU time 1.17 seconds
Started Jun 11 02:22:05 PM PDT 24
Finished Jun 11 02:22:07 PM PDT 24
Peak memory 220136 kb
Host smart-bbabb59e-d9b3-482d-81b9-96c1fb1883e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557059075 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1557059075
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.235665164
Short name T364
Test name
Test status
Simulation time 42615790 ps
CPU time 1.54 seconds
Started Jun 11 02:22:06 PM PDT 24
Finished Jun 11 02:22:09 PM PDT 24
Peak memory 218612 kb
Host smart-2f38fd20-ed08-4ecc-9e68-1b26a091444e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235665164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.235665164
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.1089561854
Short name T228
Test name
Test status
Simulation time 49472387 ps
CPU time 1.23 seconds
Started Jun 11 02:22:01 PM PDT 24
Finished Jun 11 02:22:03 PM PDT 24
Peak memory 221048 kb
Host smart-6b05539f-a080-4372-bcd2-80b18cbfb0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089561854 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.1089561854
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.1828328569
Short name T484
Test name
Test status
Simulation time 45744860 ps
CPU time 1.63 seconds
Started Jun 11 02:22:00 PM PDT 24
Finished Jun 11 02:22:02 PM PDT 24
Peak memory 220140 kb
Host smart-c01b761a-7fa5-44fc-914d-26d97fa3fc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828328569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1828328569
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.1944839770
Short name T545
Test name
Test status
Simulation time 45860450 ps
CPU time 1.22 seconds
Started Jun 11 02:22:02 PM PDT 24
Finished Jun 11 02:22:05 PM PDT 24
Peak memory 219768 kb
Host smart-a26b4532-2561-40ed-8a8b-50e118998cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944839770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.1944839770
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.2053803477
Short name T750
Test name
Test status
Simulation time 83530667 ps
CPU time 1.49 seconds
Started Jun 11 02:21:59 PM PDT 24
Finished Jun 11 02:22:02 PM PDT 24
Peak memory 218520 kb
Host smart-fe38d4d4-616e-4081-869f-3169187447eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053803477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2053803477
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.645576236
Short name T848
Test name
Test status
Simulation time 42745620 ps
CPU time 1.14 seconds
Started Jun 11 02:22:05 PM PDT 24
Finished Jun 11 02:22:08 PM PDT 24
Peak memory 219868 kb
Host smart-068249a7-e4ee-49c5-8fa5-174cdeeae5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645576236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.645576236
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.3350216937
Short name T11
Test name
Test status
Simulation time 61963082 ps
CPU time 1.36 seconds
Started Jun 11 02:22:05 PM PDT 24
Finished Jun 11 02:22:08 PM PDT 24
Peak memory 220292 kb
Host smart-eb71bb7e-fb0a-4d83-ba36-71f0fb74fa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350216937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3350216937
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.43957133
Short name T754
Test name
Test status
Simulation time 37128559 ps
CPU time 1.06 seconds
Started Jun 11 02:22:03 PM PDT 24
Finished Jun 11 02:22:05 PM PDT 24
Peak memory 220012 kb
Host smart-e5ef9fe0-a364-4f1e-ba12-b854f037918c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43957133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.43957133
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3561180890
Short name T390
Test name
Test status
Simulation time 126676487 ps
CPU time 2.77 seconds
Started Jun 11 02:22:03 PM PDT 24
Finished Jun 11 02:22:07 PM PDT 24
Peak memory 220588 kb
Host smart-ce4e0987-a93e-4147-99d0-92285c3290ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561180890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3561180890
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.1469338374
Short name T935
Test name
Test status
Simulation time 45898152 ps
CPU time 1.27 seconds
Started Jun 11 02:22:01 PM PDT 24
Finished Jun 11 02:22:03 PM PDT 24
Peak memory 218708 kb
Host smart-a6e73851-88ed-402b-8ab0-5c0c8a166703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469338374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.1469338374
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.1044143958
Short name T685
Test name
Test status
Simulation time 29139114 ps
CPU time 1.32 seconds
Started Jun 11 02:22:05 PM PDT 24
Finished Jun 11 02:22:08 PM PDT 24
Peak memory 218944 kb
Host smart-394df1e9-a7fe-4eb2-9324-edaac6d5541d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044143958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1044143958
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.2303593872
Short name T260
Test name
Test status
Simulation time 49943791 ps
CPU time 1.19 seconds
Started Jun 11 02:22:04 PM PDT 24
Finished Jun 11 02:22:06 PM PDT 24
Peak memory 218768 kb
Host smart-4145c5c7-6af9-442f-b132-c7be300fb0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303593872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.2303593872
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.744632968
Short name T650
Test name
Test status
Simulation time 42550160 ps
CPU time 1.04 seconds
Started Jun 11 02:22:05 PM PDT 24
Finished Jun 11 02:22:08 PM PDT 24
Peak memory 217612 kb
Host smart-287b98e4-5036-4da0-8094-c2dedbabeec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744632968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.744632968
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.32344277
Short name T140
Test name
Test status
Simulation time 70917533 ps
CPU time 1.21 seconds
Started Jun 11 02:19:19 PM PDT 24
Finished Jun 11 02:19:21 PM PDT 24
Peak memory 218916 kb
Host smart-dba7ebc3-ea46-489c-9802-2380a10d2c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32344277 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.32344277
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.657246896
Short name T387
Test name
Test status
Simulation time 54624786 ps
CPU time 0.92 seconds
Started Jun 11 02:19:16 PM PDT 24
Finished Jun 11 02:19:18 PM PDT 24
Peak memory 207148 kb
Host smart-311170c6-6aa9-441a-9a21-c82a6646a031
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657246896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.657246896
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_err.1889879341
Short name T637
Test name
Test status
Simulation time 19454853 ps
CPU time 1.11 seconds
Started Jun 11 02:19:15 PM PDT 24
Finished Jun 11 02:19:17 PM PDT 24
Peak memory 218764 kb
Host smart-b9f042e5-241d-424d-9bc6-cb869bcfc400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889879341 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1889879341
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.884240695
Short name T563
Test name
Test status
Simulation time 42939306 ps
CPU time 1.5 seconds
Started Jun 11 02:19:15 PM PDT 24
Finished Jun 11 02:19:18 PM PDT 24
Peak memory 219324 kb
Host smart-58e7a409-2641-44f8-affb-7eba6d48b116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884240695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.884240695
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2813138020
Short name T554
Test name
Test status
Simulation time 24122714 ps
CPU time 1.02 seconds
Started Jun 11 02:19:24 PM PDT 24
Finished Jun 11 02:19:26 PM PDT 24
Peak memory 215852 kb
Host smart-aa58d3f4-4ade-4ccd-a4fd-eb0dfd024707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813138020 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2813138020
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.4122869996
Short name T352
Test name
Test status
Simulation time 31090863 ps
CPU time 1 seconds
Started Jun 11 02:19:17 PM PDT 24
Finished Jun 11 02:19:19 PM PDT 24
Peak memory 215580 kb
Host smart-360af3ef-9900-4921-a050-68ae9c99d7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122869996 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.4122869996
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2197208844
Short name T73
Test name
Test status
Simulation time 347369867 ps
CPU time 3.67 seconds
Started Jun 11 02:19:16 PM PDT 24
Finished Jun 11 02:19:21 PM PDT 24
Peak memory 215604 kb
Host smart-3eb6890e-1763-4994-8c4a-e3ec570b5697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197208844 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2197208844
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.343063760
Short name T109
Test name
Test status
Simulation time 12693848932 ps
CPU time 154.87 seconds
Started Jun 11 02:19:17 PM PDT 24
Finished Jun 11 02:21:53 PM PDT 24
Peak memory 223568 kb
Host smart-52fa3331-ff4f-467b-9a45-e2244230552e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343063760 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.343063760
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.2254416581
Short name T288
Test name
Test status
Simulation time 79153340 ps
CPU time 1.12 seconds
Started Jun 11 02:22:05 PM PDT 24
Finished Jun 11 02:22:08 PM PDT 24
Peak memory 220064 kb
Host smart-8e93ddf2-afd4-4df8-a99d-07ccb6f476b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254416581 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2254416581
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.2684734745
Short name T535
Test name
Test status
Simulation time 52769403 ps
CPU time 1.64 seconds
Started Jun 11 02:22:06 PM PDT 24
Finished Jun 11 02:22:09 PM PDT 24
Peak memory 218756 kb
Host smart-aead4c23-c808-4529-bbd3-367e2d6fa186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684734745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2684734745
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.4012033736
Short name T88
Test name
Test status
Simulation time 40288234 ps
CPU time 1.23 seconds
Started Jun 11 02:22:07 PM PDT 24
Finished Jun 11 02:22:10 PM PDT 24
Peak memory 219208 kb
Host smart-007d7f53-5bc5-4898-938b-77c9cd56965f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012033736 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.4012033736
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.1715428278
Short name T699
Test name
Test status
Simulation time 97032567 ps
CPU time 1.6 seconds
Started Jun 11 02:22:02 PM PDT 24
Finished Jun 11 02:22:05 PM PDT 24
Peak memory 219064 kb
Host smart-3c544d03-b7e0-415f-8722-972e37bd498a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715428278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1715428278
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.478501666
Short name T576
Test name
Test status
Simulation time 86328617 ps
CPU time 1.1 seconds
Started Jun 11 02:22:04 PM PDT 24
Finished Jun 11 02:22:06 PM PDT 24
Peak memory 220452 kb
Host smart-03d71bf4-7a37-453c-b0a3-a2b7f315cb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478501666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.478501666
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.1135307576
Short name T656
Test name
Test status
Simulation time 54904782 ps
CPU time 1.44 seconds
Started Jun 11 02:22:01 PM PDT 24
Finished Jun 11 02:22:04 PM PDT 24
Peak memory 218848 kb
Host smart-c59e97b5-3ba6-4a86-8318-0951fd75767f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135307576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1135307576
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.1173300919
Short name T253
Test name
Test status
Simulation time 32137720 ps
CPU time 1.33 seconds
Started Jun 11 02:22:04 PM PDT 24
Finished Jun 11 02:22:06 PM PDT 24
Peak memory 220460 kb
Host smart-baff5666-f13b-4ee0-9e88-cc5da5b5a23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173300919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1173300919
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.1316274604
Short name T494
Test name
Test status
Simulation time 84945678 ps
CPU time 1.18 seconds
Started Jun 11 02:22:05 PM PDT 24
Finished Jun 11 02:22:08 PM PDT 24
Peak memory 220100 kb
Host smart-424fbabc-17e2-4912-b772-ff7e10c0a4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316274604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1316274604
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.3057836415
Short name T835
Test name
Test status
Simulation time 56936447 ps
CPU time 1.49 seconds
Started Jun 11 02:22:05 PM PDT 24
Finished Jun 11 02:22:08 PM PDT 24
Peak memory 217800 kb
Host smart-226bc91d-e66e-41d4-967f-b7429f82c096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057836415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3057836415
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.1025672059
Short name T199
Test name
Test status
Simulation time 334637285 ps
CPU time 1.35 seconds
Started Jun 11 02:22:00 PM PDT 24
Finished Jun 11 02:22:03 PM PDT 24
Peak memory 220848 kb
Host smart-3608f3e3-47cc-47da-86f9-07d993bd2f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025672059 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.1025672059
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1976207655
Short name T464
Test name
Test status
Simulation time 32209252 ps
CPU time 1.37 seconds
Started Jun 11 02:22:01 PM PDT 24
Finished Jun 11 02:22:03 PM PDT 24
Peak memory 218740 kb
Host smart-8edb105f-4d28-471c-a8a2-4797b3665696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976207655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1976207655
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.643054136
Short name T970
Test name
Test status
Simulation time 355864410 ps
CPU time 1.26 seconds
Started Jun 11 02:22:06 PM PDT 24
Finished Jun 11 02:22:08 PM PDT 24
Peak memory 221508 kb
Host smart-5ec5dcaf-2a45-4395-8202-3e6951e31698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643054136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.643054136
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.4057929130
Short name T480
Test name
Test status
Simulation time 40779418 ps
CPU time 1.12 seconds
Started Jun 11 02:22:07 PM PDT 24
Finished Jun 11 02:22:10 PM PDT 24
Peak memory 217580 kb
Host smart-18a52d9a-311a-4366-a291-0a79a100272b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057929130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.4057929130
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.3595166150
Short name T645
Test name
Test status
Simulation time 21791683 ps
CPU time 1.12 seconds
Started Jun 11 02:22:06 PM PDT 24
Finished Jun 11 02:22:09 PM PDT 24
Peak memory 220012 kb
Host smart-b3f5d82e-7930-4884-bd98-c381390e3716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595166150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.3595166150
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.1459166124
Short name T447
Test name
Test status
Simulation time 65290651 ps
CPU time 1.12 seconds
Started Jun 11 02:22:07 PM PDT 24
Finished Jun 11 02:22:09 PM PDT 24
Peak memory 217512 kb
Host smart-3371baa8-a061-4908-ac49-8d6713542429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459166124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1459166124
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.1947880796
Short name T885
Test name
Test status
Simulation time 76150321 ps
CPU time 1.19 seconds
Started Jun 11 02:22:05 PM PDT 24
Finished Jun 11 02:22:07 PM PDT 24
Peak memory 219008 kb
Host smart-c81e2d00-5f47-4b16-9087-af1a3d0fd0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947880796 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.1947880796
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.3737395809
Short name T673
Test name
Test status
Simulation time 46554588 ps
CPU time 1.57 seconds
Started Jun 11 02:22:05 PM PDT 24
Finished Jun 11 02:22:07 PM PDT 24
Peak memory 218832 kb
Host smart-301e1f8e-ddee-45c8-9f41-6cf2231e75e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737395809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3737395809
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert_test.1281169009
Short name T250
Test name
Test status
Simulation time 49887259 ps
CPU time 0.91 seconds
Started Jun 11 02:19:17 PM PDT 24
Finished Jun 11 02:19:19 PM PDT 24
Peak memory 206952 kb
Host smart-95e3a291-b481-4cb3-9800-ad7f4beb1ee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281169009 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1281169009
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.897296948
Short name T218
Test name
Test status
Simulation time 42153797 ps
CPU time 1.42 seconds
Started Jun 11 02:19:24 PM PDT 24
Finished Jun 11 02:19:26 PM PDT 24
Peak memory 217100 kb
Host smart-9991230f-0461-4564-b346-ce961164af90
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897296948 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.897296948
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3740990233
Short name T590
Test name
Test status
Simulation time 37536289 ps
CPU time 1.13 seconds
Started Jun 11 02:19:17 PM PDT 24
Finished Jun 11 02:19:19 PM PDT 24
Peak memory 219952 kb
Host smart-64fd476c-2411-40d4-80d6-d8e200351dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740990233 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3740990233
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.1199302208
Short name T482
Test name
Test status
Simulation time 115419959 ps
CPU time 1.7 seconds
Started Jun 11 02:19:17 PM PDT 24
Finished Jun 11 02:19:20 PM PDT 24
Peak memory 219256 kb
Host smart-5396aa44-cfc5-417c-9428-b7d6f72e1c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199302208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1199302208
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3336733558
Short name T881
Test name
Test status
Simulation time 42685617 ps
CPU time 1.11 seconds
Started Jun 11 02:19:17 PM PDT 24
Finished Jun 11 02:19:20 PM PDT 24
Peak memory 224248 kb
Host smart-03ad12e4-83f1-422e-9856-d47ef2a39bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336733558 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3336733558
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.733027929
Short name T715
Test name
Test status
Simulation time 26345752 ps
CPU time 0.94 seconds
Started Jun 11 02:19:17 PM PDT 24
Finished Jun 11 02:19:19 PM PDT 24
Peak memory 215580 kb
Host smart-e5d61ded-b2ae-4eff-9202-1445113b63f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733027929 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.733027929
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2312558472
Short name T615
Test name
Test status
Simulation time 291923918 ps
CPU time 5.47 seconds
Started Jun 11 02:19:24 PM PDT 24
Finished Jun 11 02:19:31 PM PDT 24
Peak memory 217500 kb
Host smart-d35d0cb5-2a0e-44df-8889-9af0ca9137eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312558472 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2312558472
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1090385839
Short name T702
Test name
Test status
Simulation time 58141660651 ps
CPU time 692.45 seconds
Started Jun 11 02:19:17 PM PDT 24
Finished Jun 11 02:30:51 PM PDT 24
Peak memory 221772 kb
Host smart-e14952fb-8e2b-431b-ba6f-67cdd293fbe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090385839 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1090385839
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.4113789719
Short name T248
Test name
Test status
Simulation time 44946667 ps
CPU time 1.19 seconds
Started Jun 11 02:22:02 PM PDT 24
Finished Jun 11 02:22:05 PM PDT 24
Peak memory 221340 kb
Host smart-3389055f-d12d-4392-b223-4276ced53249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113789719 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.4113789719
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.3727071051
Short name T602
Test name
Test status
Simulation time 2851455285 ps
CPU time 82.84 seconds
Started Jun 11 02:22:02 PM PDT 24
Finished Jun 11 02:23:26 PM PDT 24
Peak memory 219204 kb
Host smart-f2958639-7e0c-445a-9af5-77ea2a28803c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727071051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3727071051
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.4128330200
Short name T629
Test name
Test status
Simulation time 26658808 ps
CPU time 1.19 seconds
Started Jun 11 02:22:03 PM PDT 24
Finished Jun 11 02:22:05 PM PDT 24
Peak memory 220044 kb
Host smart-5e48706d-be00-476d-9b8f-2375709d2ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128330200 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.4128330200
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.686568174
Short name T919
Test name
Test status
Simulation time 65867344 ps
CPU time 1.12 seconds
Started Jun 11 02:22:03 PM PDT 24
Finished Jun 11 02:22:06 PM PDT 24
Peak memory 219068 kb
Host smart-9ff71e5e-37df-4eeb-b42d-acd5ea61b1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686568174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.686568174
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.4143336538
Short name T224
Test name
Test status
Simulation time 46035979 ps
CPU time 1.25 seconds
Started Jun 11 02:22:13 PM PDT 24
Finished Jun 11 02:22:15 PM PDT 24
Peak memory 218728 kb
Host smart-17d63cc6-f57c-47f1-8559-1d53130da90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143336538 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.4143336538
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.25140859
Short name T391
Test name
Test status
Simulation time 79194636 ps
CPU time 1.43 seconds
Started Jun 11 02:22:02 PM PDT 24
Finished Jun 11 02:22:05 PM PDT 24
Peak memory 217688 kb
Host smart-a7f18a09-f9b4-45f7-964a-09cd1ca672db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25140859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.25140859
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.4193443294
Short name T450
Test name
Test status
Simulation time 131100340 ps
CPU time 1.13 seconds
Started Jun 11 02:22:14 PM PDT 24
Finished Jun 11 02:22:16 PM PDT 24
Peak memory 219032 kb
Host smart-ad0f4f39-ec88-4e97-9700-53c8c03bc0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193443294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.4193443294
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.1930262355
Short name T531
Test name
Test status
Simulation time 74272008 ps
CPU time 1.51 seconds
Started Jun 11 02:22:22 PM PDT 24
Finished Jun 11 02:22:25 PM PDT 24
Peak memory 219004 kb
Host smart-5c3e3fe5-4a10-4dcf-8c41-e411dc5067f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930262355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1930262355
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.1248835452
Short name T619
Test name
Test status
Simulation time 68213734 ps
CPU time 1.19 seconds
Started Jun 11 02:22:11 PM PDT 24
Finished Jun 11 02:22:13 PM PDT 24
Peak memory 219584 kb
Host smart-7114a6b1-e2b1-41ee-b892-7c45cf056aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248835452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.1248835452
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.3399681299
Short name T501
Test name
Test status
Simulation time 113047497 ps
CPU time 1.43 seconds
Started Jun 11 02:22:14 PM PDT 24
Finished Jun 11 02:22:16 PM PDT 24
Peak memory 219148 kb
Host smart-5df3637b-19e4-49cd-8742-037ddebd5b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399681299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3399681299
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.3560760025
Short name T176
Test name
Test status
Simulation time 32104848 ps
CPU time 1.06 seconds
Started Jun 11 02:22:14 PM PDT 24
Finished Jun 11 02:22:16 PM PDT 24
Peak memory 218636 kb
Host smart-b8a9457a-4a8b-4a44-81f2-8eadd684e8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560760025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.3560760025
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1597791442
Short name T313
Test name
Test status
Simulation time 228993350 ps
CPU time 3.72 seconds
Started Jun 11 02:22:15 PM PDT 24
Finished Jun 11 02:22:20 PM PDT 24
Peak memory 220476 kb
Host smart-831ed79a-b3d3-48cd-a50f-e13969dbaa86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597791442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1597791442
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.1314479898
Short name T807
Test name
Test status
Simulation time 122323793 ps
CPU time 1.05 seconds
Started Jun 11 02:22:13 PM PDT 24
Finished Jun 11 02:22:15 PM PDT 24
Peak memory 220876 kb
Host smart-b2f3c241-9e68-4bb9-93df-8600eba2cf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314479898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.1314479898
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.3902873812
Short name T929
Test name
Test status
Simulation time 40210223 ps
CPU time 1.08 seconds
Started Jun 11 02:22:15 PM PDT 24
Finished Jun 11 02:22:17 PM PDT 24
Peak memory 217536 kb
Host smart-61447779-b5ed-4744-9738-1323d6e594f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902873812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3902873812
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.2085893759
Short name T540
Test name
Test status
Simulation time 78916936 ps
CPU time 1.23 seconds
Started Jun 11 02:22:16 PM PDT 24
Finished Jun 11 02:22:18 PM PDT 24
Peak memory 219756 kb
Host smart-76cfb71d-9586-443e-92e9-bfb53e685db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085893759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.2085893759
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.4215755862
Short name T693
Test name
Test status
Simulation time 42673298 ps
CPU time 1.12 seconds
Started Jun 11 02:22:12 PM PDT 24
Finished Jun 11 02:22:13 PM PDT 24
Peak memory 217604 kb
Host smart-0b3c68a7-8016-40ec-aab0-7fd70bcc9fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215755862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.4215755862
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.3727579427
Short name T943
Test name
Test status
Simulation time 59917196 ps
CPU time 1.15 seconds
Started Jun 11 02:22:16 PM PDT 24
Finished Jun 11 02:22:18 PM PDT 24
Peak memory 219880 kb
Host smart-f0c9a8e1-af58-4122-8b6b-59a49bb4de9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727579427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.3727579427
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.3104346425
Short name T725
Test name
Test status
Simulation time 77776900 ps
CPU time 1.1 seconds
Started Jun 11 02:22:13 PM PDT 24
Finished Jun 11 02:22:15 PM PDT 24
Peak memory 217436 kb
Host smart-76e16688-46c6-41de-95ec-4c98e99fd333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104346425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3104346425
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.3351427691
Short name T767
Test name
Test status
Simulation time 87281820 ps
CPU time 1.23 seconds
Started Jun 11 02:22:22 PM PDT 24
Finished Jun 11 02:22:25 PM PDT 24
Peak memory 220892 kb
Host smart-def50b40-d189-45dc-936d-873aff5ef217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351427691 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.3351427691
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.405220866
Short name T488
Test name
Test status
Simulation time 73192719 ps
CPU time 1.39 seconds
Started Jun 11 02:22:15 PM PDT 24
Finished Jun 11 02:22:17 PM PDT 24
Peak memory 219048 kb
Host smart-e3aa7585-2107-4a02-ae5e-b64ebee968cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405220866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.405220866
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.506974963
Short name T988
Test name
Test status
Simulation time 42344785 ps
CPU time 1.17 seconds
Started Jun 11 02:19:26 PM PDT 24
Finished Jun 11 02:19:28 PM PDT 24
Peak memory 219928 kb
Host smart-6882993f-fe16-45f5-8004-bbf18934f067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506974963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.506974963
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.356037539
Short name T371
Test name
Test status
Simulation time 14100612 ps
CPU time 0.91 seconds
Started Jun 11 02:19:26 PM PDT 24
Finished Jun 11 02:19:28 PM PDT 24
Peak memory 207140 kb
Host smart-0494b81b-54de-4b28-a1fd-ba6d0b6936bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356037539 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.356037539
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3120690152
Short name T591
Test name
Test status
Simulation time 16546099 ps
CPU time 0.84 seconds
Started Jun 11 02:19:28 PM PDT 24
Finished Jun 11 02:19:30 PM PDT 24
Peak memory 216516 kb
Host smart-f60eee16-61e4-4a81-b87e-1e498046c636
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120690152 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3120690152
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.483382272
Short name T580
Test name
Test status
Simulation time 34250475 ps
CPU time 1.16 seconds
Started Jun 11 02:19:25 PM PDT 24
Finished Jun 11 02:19:27 PM PDT 24
Peak memory 217220 kb
Host smart-f4f726d3-bd8c-4c77-b44c-6c5fc9d3629f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483382272 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.483382272
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1467780147
Short name T622
Test name
Test status
Simulation time 39665858 ps
CPU time 0.95 seconds
Started Jun 11 02:19:26 PM PDT 24
Finished Jun 11 02:19:28 PM PDT 24
Peak memory 220056 kb
Host smart-0021d0a9-e623-411c-96c0-efcbe6ae43a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467780147 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1467780147
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.4153590423
Short name T996
Test name
Test status
Simulation time 50868982 ps
CPU time 1.52 seconds
Started Jun 11 02:19:19 PM PDT 24
Finished Jun 11 02:19:22 PM PDT 24
Peak memory 218980 kb
Host smart-eb820d65-6a69-41bf-8b6e-42eedb20c4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153590423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.4153590423
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.4125009318
Short name T854
Test name
Test status
Simulation time 23140332 ps
CPU time 1.22 seconds
Started Jun 11 02:19:26 PM PDT 24
Finished Jun 11 02:19:29 PM PDT 24
Peak memory 224332 kb
Host smart-9048ea7c-bfed-497c-8cb6-ce96bef9a6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125009318 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.4125009318
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3735794840
Short name T558
Test name
Test status
Simulation time 46027675 ps
CPU time 1 seconds
Started Jun 11 02:19:17 PM PDT 24
Finished Jun 11 02:19:19 PM PDT 24
Peak memory 215488 kb
Host smart-bc3e7d9e-f3e3-406b-80d8-a3d97a90b7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735794840 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3735794840
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3264745338
Short name T444
Test name
Test status
Simulation time 223282578 ps
CPU time 4.29 seconds
Started Jun 11 02:19:26 PM PDT 24
Finished Jun 11 02:19:32 PM PDT 24
Peak memory 218908 kb
Host smart-bc193332-31bb-4a2d-bf14-4054fe4baf49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264745338 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3264745338
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.323806679
Short name T235
Test name
Test status
Simulation time 190070827657 ps
CPU time 1049.56 seconds
Started Jun 11 02:19:25 PM PDT 24
Finished Jun 11 02:36:56 PM PDT 24
Peak memory 223912 kb
Host smart-77812b66-1a5d-454f-995d-168de6b7cb2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323806679 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.323806679
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.1281602642
Short name T156
Test name
Test status
Simulation time 30250999 ps
CPU time 1.17 seconds
Started Jun 11 02:22:24 PM PDT 24
Finished Jun 11 02:22:27 PM PDT 24
Peak memory 218856 kb
Host smart-c8096ff0-fcd7-4ca1-b7a2-fc1769b658b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281602642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.1281602642
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.92656397
Short name T454
Test name
Test status
Simulation time 52457427 ps
CPU time 1.31 seconds
Started Jun 11 02:22:15 PM PDT 24
Finished Jun 11 02:22:17 PM PDT 24
Peak memory 218812 kb
Host smart-e5460408-206c-47f6-a97f-5777a6576083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92656397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.92656397
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.3863457647
Short name T330
Test name
Test status
Simulation time 158850771 ps
CPU time 1.11 seconds
Started Jun 11 02:22:12 PM PDT 24
Finished Jun 11 02:22:14 PM PDT 24
Peak memory 219780 kb
Host smart-671e4de0-d754-426e-bb5a-d7892b716845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863457647 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.3863457647
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.2914324278
Short name T486
Test name
Test status
Simulation time 29391169 ps
CPU time 1.53 seconds
Started Jun 11 02:22:14 PM PDT 24
Finished Jun 11 02:22:16 PM PDT 24
Peak memory 217496 kb
Host smart-9df523c8-7ace-477d-b820-320486b08c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914324278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2914324278
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.3344813374
Short name T115
Test name
Test status
Simulation time 67389996 ps
CPU time 1.1 seconds
Started Jun 11 02:22:22 PM PDT 24
Finished Jun 11 02:22:24 PM PDT 24
Peak memory 219376 kb
Host smart-e56f3cbc-8d88-45e7-846f-6d0928394c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344813374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.3344813374
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.4281906576
Short name T359
Test name
Test status
Simulation time 51384324 ps
CPU time 1.17 seconds
Started Jun 11 02:22:16 PM PDT 24
Finished Jun 11 02:22:18 PM PDT 24
Peak memory 218880 kb
Host smart-c9a606cf-22d9-4d1f-85d9-904f44c155c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281906576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.4281906576
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.3661032131
Short name T148
Test name
Test status
Simulation time 74846458 ps
CPU time 1.14 seconds
Started Jun 11 02:22:22 PM PDT 24
Finished Jun 11 02:22:25 PM PDT 24
Peak memory 218672 kb
Host smart-11993353-1bf5-4f80-993f-1b0d436db3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661032131 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3661032131
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.3526566282
Short name T24
Test name
Test status
Simulation time 144271135 ps
CPU time 1.45 seconds
Started Jun 11 02:22:12 PM PDT 24
Finished Jun 11 02:22:15 PM PDT 24
Peak memory 219136 kb
Host smart-f39883eb-4f35-460b-bb7f-a3f5ac43c3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526566282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3526566282
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.1425929724
Short name T947
Test name
Test status
Simulation time 29945385 ps
CPU time 1.18 seconds
Started Jun 11 02:22:17 PM PDT 24
Finished Jun 11 02:22:19 PM PDT 24
Peak memory 218632 kb
Host smart-be948022-b2f7-4a4d-9710-8a4cee2f8f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425929724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.1425929724
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.1751026111
Short name T934
Test name
Test status
Simulation time 30604916 ps
CPU time 1.29 seconds
Started Jun 11 02:22:12 PM PDT 24
Finished Jun 11 02:22:14 PM PDT 24
Peak memory 218688 kb
Host smart-b001cb92-dd23-42a7-a130-7f0c5a38bcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751026111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1751026111
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.172875214
Short name T957
Test name
Test status
Simulation time 46321600 ps
CPU time 1.2 seconds
Started Jun 11 02:22:12 PM PDT 24
Finished Jun 11 02:22:14 PM PDT 24
Peak memory 217656 kb
Host smart-e1dc83bf-8b69-49ae-855d-0eda94887f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172875214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.172875214
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2023700459
Short name T631
Test name
Test status
Simulation time 35620511 ps
CPU time 1.48 seconds
Started Jun 11 02:22:18 PM PDT 24
Finished Jun 11 02:22:20 PM PDT 24
Peak memory 218924 kb
Host smart-82f510b2-b0e8-471e-ae85-7c7af242927f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023700459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2023700459
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.2797749561
Short name T818
Test name
Test status
Simulation time 39837210 ps
CPU time 1.13 seconds
Started Jun 11 02:22:16 PM PDT 24
Finished Jun 11 02:22:18 PM PDT 24
Peak memory 219068 kb
Host smart-488d2a4a-30af-474e-8964-d8695f88ef70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797749561 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.2797749561
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.2574097054
Short name T346
Test name
Test status
Simulation time 30738604 ps
CPU time 1.24 seconds
Started Jun 11 02:22:20 PM PDT 24
Finished Jun 11 02:22:22 PM PDT 24
Peak memory 215636 kb
Host smart-ce202031-2789-4dc8-a07c-088083cf47f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574097054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2574097054
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.408333194
Short name T860
Test name
Test status
Simulation time 72812034 ps
CPU time 1.12 seconds
Started Jun 11 02:22:14 PM PDT 24
Finished Jun 11 02:22:16 PM PDT 24
Peak memory 219920 kb
Host smart-5d4469d9-8d35-487c-8fd2-a93e1a2baae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408333194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.408333194
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.491796198
Short name T339
Test name
Test status
Simulation time 365760194 ps
CPU time 3.93 seconds
Started Jun 11 02:22:14 PM PDT 24
Finished Jun 11 02:22:19 PM PDT 24
Peak memory 220640 kb
Host smart-98723479-ebb6-41e9-9b5a-52ec6664039c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491796198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.491796198
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.3074905007
Short name T992
Test name
Test status
Simulation time 90085512 ps
CPU time 1.21 seconds
Started Jun 11 02:22:12 PM PDT 24
Finished Jun 11 02:22:14 PM PDT 24
Peak memory 218680 kb
Host smart-3ce1d74b-94f6-4e8e-a64e-a793fa996816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074905007 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3074905007
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.116681848
Short name T93
Test name
Test status
Simulation time 120836977 ps
CPU time 2.65 seconds
Started Jun 11 02:22:24 PM PDT 24
Finished Jun 11 02:22:28 PM PDT 24
Peak memory 218828 kb
Host smart-ca87831c-d8d8-4464-ab39-6f0c192ee8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116681848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.116681848
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.2990825444
Short name T727
Test name
Test status
Simulation time 37907383 ps
CPU time 1.15 seconds
Started Jun 11 02:19:26 PM PDT 24
Finished Jun 11 02:19:29 PM PDT 24
Peak memory 218876 kb
Host smart-f23bda00-2988-4baf-90c8-95bc67bb5708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990825444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2990825444
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2982497457
Short name T415
Test name
Test status
Simulation time 37469426 ps
CPU time 0.87 seconds
Started Jun 11 02:19:28 PM PDT 24
Finished Jun 11 02:19:30 PM PDT 24
Peak memory 206824 kb
Host smart-3fe84284-17f5-4fcf-b4c4-94254814cfeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982497457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2982497457
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2315011567
Short name T528
Test name
Test status
Simulation time 19218282 ps
CPU time 0.9 seconds
Started Jun 11 02:19:25 PM PDT 24
Finished Jun 11 02:19:27 PM PDT 24
Peak memory 216508 kb
Host smart-d41aecbb-6974-4310-85de-dc429e4c0a0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315011567 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2315011567
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.4010146828
Short name T243
Test name
Test status
Simulation time 142444056 ps
CPU time 1.21 seconds
Started Jun 11 02:19:26 PM PDT 24
Finished Jun 11 02:19:29 PM PDT 24
Peak memory 217152 kb
Host smart-c605eea2-394c-44f7-831a-4b99abb8e6f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010146828 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.4010146828
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1960623061
Short name T138
Test name
Test status
Simulation time 26109158 ps
CPU time 1 seconds
Started Jun 11 02:19:27 PM PDT 24
Finished Jun 11 02:19:29 PM PDT 24
Peak memory 219756 kb
Host smart-bdfc923f-8b1e-42bf-a292-ba5ffe08f372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960623061 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1960623061
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1506865010
Short name T757
Test name
Test status
Simulation time 34167239 ps
CPU time 1.33 seconds
Started Jun 11 02:19:25 PM PDT 24
Finished Jun 11 02:19:27 PM PDT 24
Peak memory 219800 kb
Host smart-a6dcb0ba-afd6-4e18-a459-c174737c54a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506865010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1506865010
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.4024412209
Short name T596
Test name
Test status
Simulation time 31100815 ps
CPU time 0.88 seconds
Started Jun 11 02:19:26 PM PDT 24
Finished Jun 11 02:19:29 PM PDT 24
Peak memory 215804 kb
Host smart-ff102f47-08bf-41a1-8d06-92a48b351dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024412209 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.4024412209
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1471623434
Short name T542
Test name
Test status
Simulation time 15175274 ps
CPU time 0.99 seconds
Started Jun 11 02:19:25 PM PDT 24
Finished Jun 11 02:19:27 PM PDT 24
Peak memory 215600 kb
Host smart-ed74d69c-ab5a-49ee-a58d-37d222f9a598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471623434 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1471623434
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3176786340
Short name T424
Test name
Test status
Simulation time 362736731 ps
CPU time 4.11 seconds
Started Jun 11 02:19:26 PM PDT 24
Finished Jun 11 02:19:32 PM PDT 24
Peak memory 217772 kb
Host smart-34354ab5-2cfb-4eb2-93cb-0fc86143aa8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176786340 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3176786340
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2570954110
Short name T237
Test name
Test status
Simulation time 35322423154 ps
CPU time 841.33 seconds
Started Jun 11 02:19:26 PM PDT 24
Finished Jun 11 02:33:29 PM PDT 24
Peak memory 218684 kb
Host smart-5c7e7c07-2534-463b-a07f-df580bdf04aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570954110 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2570954110
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.1152044614
Short name T779
Test name
Test status
Simulation time 84950641 ps
CPU time 1.31 seconds
Started Jun 11 02:22:24 PM PDT 24
Finished Jun 11 02:22:27 PM PDT 24
Peak memory 219768 kb
Host smart-8747a473-a77e-427f-88d8-8fa15d3febcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152044614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.1152044614
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.2485330424
Short name T640
Test name
Test status
Simulation time 42367296 ps
CPU time 1.47 seconds
Started Jun 11 02:22:17 PM PDT 24
Finished Jun 11 02:22:19 PM PDT 24
Peak memory 218760 kb
Host smart-65e30ffb-86fa-44c8-883d-78958a0124b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485330424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2485330424
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.1496314726
Short name T831
Test name
Test status
Simulation time 144924026 ps
CPU time 1.22 seconds
Started Jun 11 02:22:22 PM PDT 24
Finished Jun 11 02:22:25 PM PDT 24
Peak memory 218780 kb
Host smart-fdcf6c80-c8af-461c-91d3-2a9b4d6c37d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496314726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.1496314726
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3424258649
Short name T726
Test name
Test status
Simulation time 75262094 ps
CPU time 1.21 seconds
Started Jun 11 02:22:16 PM PDT 24
Finished Jun 11 02:22:18 PM PDT 24
Peak memory 220200 kb
Host smart-073e5b0f-37c0-41a0-b72c-a62aea5a01c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424258649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3424258649
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.2094323539
Short name T257
Test name
Test status
Simulation time 50063971 ps
CPU time 1.25 seconds
Started Jun 11 02:22:12 PM PDT 24
Finished Jun 11 02:22:14 PM PDT 24
Peak memory 219920 kb
Host smart-3fd51dbe-c082-4ef6-b44c-4342091bf8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094323539 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2094323539
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.947347443
Short name T814
Test name
Test status
Simulation time 54085146 ps
CPU time 1.81 seconds
Started Jun 11 02:22:20 PM PDT 24
Finished Jun 11 02:22:23 PM PDT 24
Peak memory 218816 kb
Host smart-05440216-c681-4d4d-b44f-f7f94309ed14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947347443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.947347443
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.3625513568
Short name T944
Test name
Test status
Simulation time 53005581 ps
CPU time 1.26 seconds
Started Jun 11 02:22:24 PM PDT 24
Finished Jun 11 02:22:27 PM PDT 24
Peak memory 217640 kb
Host smart-de5bb4ca-a6ba-4c0c-bbb3-07ddac73a3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625513568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3625513568
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.2006710792
Short name T801
Test name
Test status
Simulation time 40176988 ps
CPU time 1.12 seconds
Started Jun 11 02:22:15 PM PDT 24
Finished Jun 11 02:22:18 PM PDT 24
Peak memory 218948 kb
Host smart-a1f17876-1158-47e0-9226-ba8921ec15f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006710792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.2006710792
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/185.edn_alert.2667270837
Short name T568
Test name
Test status
Simulation time 24079075 ps
CPU time 1.17 seconds
Started Jun 11 02:22:24 PM PDT 24
Finished Jun 11 02:22:27 PM PDT 24
Peak memory 218936 kb
Host smart-0d75184b-4444-4a9a-8fd5-8eb4e9a26152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667270837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.2667270837
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.3894885305
Short name T518
Test name
Test status
Simulation time 66592158 ps
CPU time 1.19 seconds
Started Jun 11 02:22:24 PM PDT 24
Finished Jun 11 02:22:27 PM PDT 24
Peak memory 219400 kb
Host smart-0c297abf-efe0-4a4a-a79b-1003de53e5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894885305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3894885305
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.187743070
Short name T841
Test name
Test status
Simulation time 36581253 ps
CPU time 1.14 seconds
Started Jun 11 02:22:24 PM PDT 24
Finished Jun 11 02:22:27 PM PDT 24
Peak memory 220124 kb
Host smart-f80551c5-7b0b-45cf-aab6-acc620fbb702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187743070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.187743070
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.3903555538
Short name T435
Test name
Test status
Simulation time 58819375 ps
CPU time 1.76 seconds
Started Jun 11 02:22:22 PM PDT 24
Finished Jun 11 02:22:25 PM PDT 24
Peak memory 220152 kb
Host smart-ab1605b5-5489-4d46-97f1-7ec89a832d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903555538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3903555538
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.422703270
Short name T789
Test name
Test status
Simulation time 50753132 ps
CPU time 1.19 seconds
Started Jun 11 02:22:12 PM PDT 24
Finished Jun 11 02:22:14 PM PDT 24
Peak memory 219916 kb
Host smart-9cceec87-57a9-4a0b-a329-b369e381b448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422703270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.422703270
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/188.edn_alert.402184623
Short name T255
Test name
Test status
Simulation time 30704645 ps
CPU time 1.32 seconds
Started Jun 11 02:22:14 PM PDT 24
Finished Jun 11 02:22:17 PM PDT 24
Peak memory 220660 kb
Host smart-ad7ca53a-db38-484d-9fc3-594919cee180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402184623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.402184623
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.1767386493
Short name T985
Test name
Test status
Simulation time 109563429 ps
CPU time 1.57 seconds
Started Jun 11 02:22:13 PM PDT 24
Finished Jun 11 02:22:16 PM PDT 24
Peak memory 220128 kb
Host smart-ccb66264-8b9e-4014-9366-d2bf5582ed65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767386493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1767386493
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.2800445837
Short name T332
Test name
Test status
Simulation time 69184674 ps
CPU time 1.06 seconds
Started Jun 11 02:22:15 PM PDT 24
Finished Jun 11 02:22:17 PM PDT 24
Peak memory 220020 kb
Host smart-fa3727b2-a604-40b0-b73c-cfcb6936d418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800445837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2800445837
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2108053935
Short name T952
Test name
Test status
Simulation time 48185286 ps
CPU time 1.82 seconds
Started Jun 11 02:22:16 PM PDT 24
Finished Jun 11 02:22:19 PM PDT 24
Peak memory 218812 kb
Host smart-daea7399-45b1-4684-ac1c-377e1a84b015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108053935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2108053935
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.975915838
Short name T112
Test name
Test status
Simulation time 56175511 ps
CPU time 1.36 seconds
Started Jun 11 02:19:27 PM PDT 24
Finished Jun 11 02:19:30 PM PDT 24
Peak memory 215944 kb
Host smart-b80004a4-b865-4ff8-a8a7-acbd4d97d338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975915838 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.975915838
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2312718731
Short name T21
Test name
Test status
Simulation time 30391250 ps
CPU time 0.85 seconds
Started Jun 11 02:19:26 PM PDT 24
Finished Jun 11 02:19:28 PM PDT 24
Peak memory 206760 kb
Host smart-8a9a6ac6-b3fb-49dd-8fd2-c1761d274e31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312718731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2312718731
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3973110617
Short name T718
Test name
Test status
Simulation time 49031499 ps
CPU time 1.5 seconds
Started Jun 11 02:19:25 PM PDT 24
Finished Jun 11 02:19:27 PM PDT 24
Peak memory 217024 kb
Host smart-a243d006-5878-4085-8e84-0a0afab32416
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973110617 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3973110617
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3908877651
Short name T634
Test name
Test status
Simulation time 19672774 ps
CPU time 1.09 seconds
Started Jun 11 02:19:26 PM PDT 24
Finished Jun 11 02:19:28 PM PDT 24
Peak memory 218728 kb
Host smart-bd4f4c6f-b750-44d0-a72d-aa4738bc5438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908877651 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3908877651
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.4129023143
Short name T651
Test name
Test status
Simulation time 43333350 ps
CPU time 1.47 seconds
Started Jun 11 02:19:28 PM PDT 24
Finished Jun 11 02:19:30 PM PDT 24
Peak memory 218920 kb
Host smart-1c71f5b3-af81-47b4-a626-91594e715cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129023143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.4129023143
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2263222444
Short name T417
Test name
Test status
Simulation time 21588312 ps
CPU time 1.1 seconds
Started Jun 11 02:19:26 PM PDT 24
Finished Jun 11 02:19:29 PM PDT 24
Peak memory 215716 kb
Host smart-38029e17-2ffd-447a-863f-c954016addb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263222444 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2263222444
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.626732777
Short name T604
Test name
Test status
Simulation time 36549792 ps
CPU time 0.84 seconds
Started Jun 11 02:19:26 PM PDT 24
Finished Jun 11 02:19:28 PM PDT 24
Peak memory 215576 kb
Host smart-e6d20f46-33fc-41e9-be37-9bf6459ff038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626732777 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.626732777
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3749521728
Short name T241
Test name
Test status
Simulation time 287554098 ps
CPU time 5.6 seconds
Started Jun 11 02:19:26 PM PDT 24
Finished Jun 11 02:19:33 PM PDT 24
Peak memory 220752 kb
Host smart-4ed8fc0f-d0b9-456e-930c-0c3eb05ab3dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749521728 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3749521728
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1428694355
Short name T931
Test name
Test status
Simulation time 16954730101 ps
CPU time 222.42 seconds
Started Jun 11 02:19:29 PM PDT 24
Finished Jun 11 02:23:13 PM PDT 24
Peak memory 219092 kb
Host smart-e8ee9d55-ccf8-4089-9c84-bcff424d2916
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428694355 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1428694355
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.2625790816
Short name T853
Test name
Test status
Simulation time 25530403 ps
CPU time 1.16 seconds
Started Jun 11 02:22:14 PM PDT 24
Finished Jun 11 02:22:17 PM PDT 24
Peak memory 218968 kb
Host smart-e3394b5b-7df3-49a1-b9ee-1d6b9c88251b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625790816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.2625790816
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.814709449
Short name T747
Test name
Test status
Simulation time 73640563 ps
CPU time 1.1 seconds
Started Jun 11 02:22:20 PM PDT 24
Finished Jun 11 02:22:22 PM PDT 24
Peak memory 217432 kb
Host smart-d9589fd3-2d0c-4966-a854-8c15c9723eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814709449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.814709449
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.2860504780
Short name T826
Test name
Test status
Simulation time 68211921 ps
CPU time 1.13 seconds
Started Jun 11 02:22:28 PM PDT 24
Finished Jun 11 02:22:29 PM PDT 24
Peak memory 218796 kb
Host smart-ebaf5024-674b-4f29-94f4-91d8ade1fdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860504780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.2860504780
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.1427197359
Short name T307
Test name
Test status
Simulation time 148617142 ps
CPU time 1.07 seconds
Started Jun 11 02:22:22 PM PDT 24
Finished Jun 11 02:22:24 PM PDT 24
Peak memory 215556 kb
Host smart-801b41a8-e0ae-41dd-a33a-029689a7229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427197359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1427197359
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.4274517504
Short name T811
Test name
Test status
Simulation time 88832426 ps
CPU time 1.21 seconds
Started Jun 11 02:22:25 PM PDT 24
Finished Jun 11 02:22:27 PM PDT 24
Peak memory 219848 kb
Host smart-61f199a8-046f-468d-a805-6cfa7d473209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274517504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.4274517504
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.1018281005
Short name T682
Test name
Test status
Simulation time 122715969 ps
CPU time 1.03 seconds
Started Jun 11 02:22:27 PM PDT 24
Finished Jun 11 02:22:29 PM PDT 24
Peak memory 217604 kb
Host smart-45c3598f-afc5-4a7c-94e1-4437fc622676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018281005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1018281005
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.1900984429
Short name T664
Test name
Test status
Simulation time 62500750 ps
CPU time 1.25 seconds
Started Jun 11 02:22:24 PM PDT 24
Finished Jun 11 02:22:26 PM PDT 24
Peak memory 220084 kb
Host smart-2d02ddf0-6069-4e41-b381-af69354820c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900984429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.1900984429
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.1965218966
Short name T973
Test name
Test status
Simulation time 96725342 ps
CPU time 1.27 seconds
Started Jun 11 02:22:29 PM PDT 24
Finished Jun 11 02:22:30 PM PDT 24
Peak memory 219560 kb
Host smart-89ec06ec-27f6-44a1-adf0-00a8d3f52341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965218966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1965218966
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.3986221065
Short name T695
Test name
Test status
Simulation time 82811556 ps
CPU time 1.13 seconds
Started Jun 11 02:22:23 PM PDT 24
Finished Jun 11 02:22:25 PM PDT 24
Peak memory 219856 kb
Host smart-1e7ddc4f-3b12-4f23-bf83-0dbca58965c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986221065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.3986221065
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.2177630362
Short name T472
Test name
Test status
Simulation time 111316532 ps
CPU time 1.3 seconds
Started Jun 11 02:22:25 PM PDT 24
Finished Jun 11 02:22:27 PM PDT 24
Peak memory 218788 kb
Host smart-09321841-7fba-47fc-8686-682875403f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177630362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2177630362
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.2781341797
Short name T449
Test name
Test status
Simulation time 58422487 ps
CPU time 1.28 seconds
Started Jun 11 02:22:24 PM PDT 24
Finished Jun 11 02:22:27 PM PDT 24
Peak memory 220444 kb
Host smart-33df2376-13c5-4d27-ae2e-00e8629556a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781341797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2781341797
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.926178742
Short name T16
Test name
Test status
Simulation time 333554114 ps
CPU time 4.47 seconds
Started Jun 11 02:22:25 PM PDT 24
Finished Jun 11 02:22:30 PM PDT 24
Peak memory 220524 kb
Host smart-962cf4f1-f690-4ecc-a493-e8869762b036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926178742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.926178742
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.68919887
Short name T742
Test name
Test status
Simulation time 28492507 ps
CPU time 1.27 seconds
Started Jun 11 02:22:24 PM PDT 24
Finished Jun 11 02:22:26 PM PDT 24
Peak memory 215940 kb
Host smart-6075b1db-b8a8-4df3-978a-e1ac9f8cca87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68919887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.68919887
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.2412180296
Short name T411
Test name
Test status
Simulation time 66258932 ps
CPU time 1.05 seconds
Started Jun 11 02:22:23 PM PDT 24
Finished Jun 11 02:22:25 PM PDT 24
Peak memory 220224 kb
Host smart-98b10320-868c-42bb-9497-46d04a27dac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412180296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2412180296
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.1264096087
Short name T405
Test name
Test status
Simulation time 25100476 ps
CPU time 1.31 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:37 PM PDT 24
Peak memory 220360 kb
Host smart-d068e895-c5c1-41ba-a0ff-8a646d150e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264096087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.1264096087
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.924356841
Short name T901
Test name
Test status
Simulation time 45767230 ps
CPU time 1.15 seconds
Started Jun 11 02:22:23 PM PDT 24
Finished Jun 11 02:22:25 PM PDT 24
Peak memory 217604 kb
Host smart-8c5ffae6-0c1e-4ec1-8fd8-d82d38e226cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924356841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.924356841
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.2429208019
Short name T508
Test name
Test status
Simulation time 57206686 ps
CPU time 1.26 seconds
Started Jun 11 02:22:32 PM PDT 24
Finished Jun 11 02:22:34 PM PDT 24
Peak memory 219280 kb
Host smart-ef8d8de1-a4fc-403c-a1de-3acdbeae5d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429208019 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.2429208019
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.2584587545
Short name T633
Test name
Test status
Simulation time 46395586 ps
CPU time 1.44 seconds
Started Jun 11 02:22:41 PM PDT 24
Finished Jun 11 02:22:43 PM PDT 24
Peak memory 218768 kb
Host smart-73a56c72-ee10-401a-a89e-e495bb029cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584587545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2584587545
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.2307673165
Short name T579
Test name
Test status
Simulation time 71225790 ps
CPU time 1.12 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:36 PM PDT 24
Peak memory 220084 kb
Host smart-7f0a8140-e709-4214-a0dd-52cc624f82d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307673165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.2307673165
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.3641880703
Short name T22
Test name
Test status
Simulation time 56173516 ps
CPU time 1.05 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:37 PM PDT 24
Peak memory 217500 kb
Host smart-938a4194-28cc-4c35-9b4c-e83fce674138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641880703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3641880703
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3384775564
Short name T87
Test name
Test status
Simulation time 25525420 ps
CPU time 1.25 seconds
Started Jun 11 02:18:20 PM PDT 24
Finished Jun 11 02:18:22 PM PDT 24
Peak memory 219948 kb
Host smart-ed1f2c85-c328-4df3-bf3f-8c035ccef4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384775564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3384775564
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2269100818
Short name T610
Test name
Test status
Simulation time 23867464 ps
CPU time 1.07 seconds
Started Jun 11 02:18:22 PM PDT 24
Finished Jun 11 02:18:24 PM PDT 24
Peak memory 207036 kb
Host smart-73884a79-7ff3-42cb-a1f4-66d254efbe00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269100818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2269100818
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2823051480
Short name T734
Test name
Test status
Simulation time 20594016 ps
CPU time 0.87 seconds
Started Jun 11 02:18:28 PM PDT 24
Finished Jun 11 02:18:30 PM PDT 24
Peak memory 215696 kb
Host smart-766d9a95-3da8-4250-8aa6-b2d87b2fcd06
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823051480 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2823051480
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.4270078389
Short name T913
Test name
Test status
Simulation time 34900397 ps
CPU time 1.25 seconds
Started Jun 11 02:18:22 PM PDT 24
Finished Jun 11 02:18:24 PM PDT 24
Peak memory 219456 kb
Host smart-5ea4f987-2310-4b5f-bcd1-3a3daeb6a338
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270078389 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.4270078389
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.4018205671
Short name T922
Test name
Test status
Simulation time 18193806 ps
CPU time 1.21 seconds
Started Jun 11 02:18:24 PM PDT 24
Finished Jun 11 02:18:25 PM PDT 24
Peak memory 224188 kb
Host smart-59c78b81-3fef-4e61-ac42-21897af803f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018205671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.4018205671
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3936112582
Short name T803
Test name
Test status
Simulation time 75765016 ps
CPU time 1.49 seconds
Started Jun 11 02:18:12 PM PDT 24
Finished Jun 11 02:18:15 PM PDT 24
Peak memory 219096 kb
Host smart-1ab1059d-461c-46ce-a182-94c882783b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936112582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3936112582
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2472331919
Short name T565
Test name
Test status
Simulation time 19460803 ps
CPU time 1.1 seconds
Started Jun 11 02:18:22 PM PDT 24
Finished Jun 11 02:18:25 PM PDT 24
Peak memory 216072 kb
Host smart-b7dcefe7-cca3-4d80-91dc-7006c6e20e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472331919 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2472331919
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3985953420
Short name T15
Test name
Test status
Simulation time 425288132 ps
CPU time 7.04 seconds
Started Jun 11 02:18:27 PM PDT 24
Finished Jun 11 02:18:35 PM PDT 24
Peak memory 236368 kb
Host smart-d16e3557-4a89-4a19-a363-2e170b484d86
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985953420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3985953420
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3636334454
Short name T618
Test name
Test status
Simulation time 18303207 ps
CPU time 1.12 seconds
Started Jun 11 02:18:14 PM PDT 24
Finished Jun 11 02:18:17 PM PDT 24
Peak memory 215568 kb
Host smart-e4f4b71b-8b8c-4f34-abb8-9fa8a354af40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636334454 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3636334454
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.390012169
Short name T828
Test name
Test status
Simulation time 261859144 ps
CPU time 5.19 seconds
Started Jun 11 02:18:22 PM PDT 24
Finished Jun 11 02:18:29 PM PDT 24
Peak memory 217504 kb
Host smart-68541cf3-8350-4168-87eb-0b2d0cbc60b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390012169 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.390012169
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.284549086
Short name T765
Test name
Test status
Simulation time 194120250702 ps
CPU time 1394.77 seconds
Started Jun 11 02:18:21 PM PDT 24
Finished Jun 11 02:41:37 PM PDT 24
Peak memory 225636 kb
Host smart-4525e002-0910-439e-ab68-0b1344bf66bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284549086 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.284549086
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1383192512
Short name T783
Test name
Test status
Simulation time 46456239 ps
CPU time 1.19 seconds
Started Jun 11 02:19:37 PM PDT 24
Finished Jun 11 02:19:40 PM PDT 24
Peak memory 218808 kb
Host smart-390b6d0d-7e93-4eb5-acae-4970a8cc65ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383192512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1383192512
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.4113797331
Short name T566
Test name
Test status
Simulation time 30952456 ps
CPU time 1.2 seconds
Started Jun 11 02:19:37 PM PDT 24
Finished Jun 11 02:19:40 PM PDT 24
Peak memory 207208 kb
Host smart-0ee0f94b-5692-42f5-843d-4b48acc9c80e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113797331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.4113797331
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1550714067
Short name T738
Test name
Test status
Simulation time 11547542 ps
CPU time 0.86 seconds
Started Jun 11 02:19:37 PM PDT 24
Finished Jun 11 02:19:39 PM PDT 24
Peak memory 215648 kb
Host smart-c14ebdba-4d94-447f-91fd-8babb3912dad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550714067 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1550714067
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.281960417
Short name T154
Test name
Test status
Simulation time 52948313 ps
CPU time 1.44 seconds
Started Jun 11 02:19:37 PM PDT 24
Finished Jun 11 02:19:39 PM PDT 24
Peak memory 217264 kb
Host smart-55c8a7d5-f95e-4b3b-8bf4-3ec07a0dc381
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281960417 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.281960417
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1589559798
Short name T136
Test name
Test status
Simulation time 28861834 ps
CPU time 1.31 seconds
Started Jun 11 02:19:37 PM PDT 24
Finished Jun 11 02:19:40 PM PDT 24
Peak memory 229928 kb
Host smart-404cdd0e-8ab6-4a16-89d0-9cb16a634c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589559798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1589559798
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.901498406
Short name T294
Test name
Test status
Simulation time 49484751 ps
CPU time 1.03 seconds
Started Jun 11 02:19:26 PM PDT 24
Finished Jun 11 02:19:29 PM PDT 24
Peak memory 217536 kb
Host smart-b2ca0e66-23bd-4ea8-acc8-5d04c19588f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901498406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.901498406
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.4180438528
Short name T469
Test name
Test status
Simulation time 23810724 ps
CPU time 1.08 seconds
Started Jun 11 02:19:37 PM PDT 24
Finished Jun 11 02:19:39 PM PDT 24
Peak memory 215780 kb
Host smart-93b6d2e1-01ac-4499-ac37-37b71a0bac45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180438528 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.4180438528
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1031895722
Short name T460
Test name
Test status
Simulation time 45431334 ps
CPU time 0.92 seconds
Started Jun 11 02:19:26 PM PDT 24
Finished Jun 11 02:19:29 PM PDT 24
Peak memory 215564 kb
Host smart-7b07fe74-3e82-44b9-bb0a-f71421a13368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031895722 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1031895722
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.199354956
Short name T440
Test name
Test status
Simulation time 370722769 ps
CPU time 3.92 seconds
Started Jun 11 02:19:37 PM PDT 24
Finished Jun 11 02:19:42 PM PDT 24
Peak memory 218920 kb
Host smart-fa568396-1174-4533-bf9a-297e0f5c3ce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199354956 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.199354956
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.526182300
Short name T388
Test name
Test status
Simulation time 277577727944 ps
CPU time 1676.02 seconds
Started Jun 11 02:19:39 PM PDT 24
Finished Jun 11 02:47:37 PM PDT 24
Peak memory 225272 kb
Host smart-db0239d8-3522-4ce4-8bc4-3f5715e256e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526182300 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.526182300
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.372086915
Short name T746
Test name
Test status
Simulation time 34684012 ps
CPU time 1.37 seconds
Started Jun 11 02:22:37 PM PDT 24
Finished Jun 11 02:22:40 PM PDT 24
Peak memory 218964 kb
Host smart-f650c3eb-85d7-4e78-9338-1f411f7e7e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372086915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.372086915
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.4124395248
Short name T404
Test name
Test status
Simulation time 42461957 ps
CPU time 1.54 seconds
Started Jun 11 02:22:33 PM PDT 24
Finished Jun 11 02:22:36 PM PDT 24
Peak memory 217452 kb
Host smart-7fa48e3c-3ec2-4469-9dc3-10bc21a8331b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124395248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.4124395248
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1194191236
Short name T989
Test name
Test status
Simulation time 251018545 ps
CPU time 1.54 seconds
Started Jun 11 02:22:35 PM PDT 24
Finished Jun 11 02:22:38 PM PDT 24
Peak memory 219084 kb
Host smart-3aefa3ee-b676-4575-bf2b-77f58bd98399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194191236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1194191236
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.572045710
Short name T861
Test name
Test status
Simulation time 37931047 ps
CPU time 1.34 seconds
Started Jun 11 02:22:38 PM PDT 24
Finished Jun 11 02:22:41 PM PDT 24
Peak memory 217796 kb
Host smart-b37bac49-819a-4d49-84f8-ab9ac656003f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572045710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.572045710
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3948868962
Short name T520
Test name
Test status
Simulation time 59602090 ps
CPU time 1.34 seconds
Started Jun 11 02:22:35 PM PDT 24
Finished Jun 11 02:22:38 PM PDT 24
Peak memory 218724 kb
Host smart-20efee85-46d5-46d3-af58-f132d5ab0c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948868962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3948868962
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3361959056
Short name T485
Test name
Test status
Simulation time 53732337 ps
CPU time 1.31 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:37 PM PDT 24
Peak memory 217548 kb
Host smart-bac2b1ef-911a-4ab4-8efd-8fc979e5d466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361959056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3361959056
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1424303825
Short name T825
Test name
Test status
Simulation time 45258054 ps
CPU time 1.79 seconds
Started Jun 11 02:22:36 PM PDT 24
Finished Jun 11 02:22:39 PM PDT 24
Peak memory 218944 kb
Host smart-128cdbd0-2ab7-4683-b5b3-e71c833fe36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424303825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1424303825
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.437797462
Short name T665
Test name
Test status
Simulation time 50812658 ps
CPU time 2.01 seconds
Started Jun 11 02:22:35 PM PDT 24
Finished Jun 11 02:22:39 PM PDT 24
Peak memory 218996 kb
Host smart-ae225982-343f-47a7-b7f6-964eadcd4e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437797462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.437797462
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.141866796
Short name T620
Test name
Test status
Simulation time 79122358 ps
CPU time 1.6 seconds
Started Jun 11 02:22:35 PM PDT 24
Finished Jun 11 02:22:39 PM PDT 24
Peak memory 220480 kb
Host smart-27294eea-6919-4a1f-a508-89589cb53df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141866796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.141866796
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.27616876
Short name T836
Test name
Test status
Simulation time 66843492 ps
CPU time 1.23 seconds
Started Jun 11 02:22:33 PM PDT 24
Finished Jun 11 02:22:35 PM PDT 24
Peak memory 217932 kb
Host smart-f3683427-78df-43f1-be35-052c3d8fd4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27616876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.27616876
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3959206162
Short name T110
Test name
Test status
Simulation time 28211135 ps
CPU time 1.32 seconds
Started Jun 11 02:19:35 PM PDT 24
Finished Jun 11 02:19:37 PM PDT 24
Peak memory 220748 kb
Host smart-2471fb10-24a1-46bc-996e-f49292ba2b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959206162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3959206162
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2343855684
Short name T956
Test name
Test status
Simulation time 70314997 ps
CPU time 0.9 seconds
Started Jun 11 02:19:39 PM PDT 24
Finished Jun 11 02:19:41 PM PDT 24
Peak memory 206992 kb
Host smart-9f1402cd-c24e-479d-87d4-0f250847503c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343855684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2343855684
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2668595079
Short name T953
Test name
Test status
Simulation time 11894438 ps
CPU time 0.84 seconds
Started Jun 11 02:19:40 PM PDT 24
Finished Jun 11 02:19:41 PM PDT 24
Peak memory 216360 kb
Host smart-10f8b101-d708-43a1-9cbf-ee5818ec8375
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668595079 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2668595079
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.4283653230
Short name T556
Test name
Test status
Simulation time 157143604 ps
CPU time 1.06 seconds
Started Jun 11 02:19:39 PM PDT 24
Finished Jun 11 02:19:41 PM PDT 24
Peak memory 219836 kb
Host smart-61731b5b-1c83-4ca2-8d34-9dee4cf70c84
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283653230 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.4283653230
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.1728590129
Short name T105
Test name
Test status
Simulation time 21907444 ps
CPU time 1.12 seconds
Started Jun 11 02:19:38 PM PDT 24
Finished Jun 11 02:19:40 PM PDT 24
Peak memory 218840 kb
Host smart-ab9d95f2-112d-4c79-aaf2-aaf514be3b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728590129 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1728590129
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3915385479
Short name T879
Test name
Test status
Simulation time 132979181 ps
CPU time 2.03 seconds
Started Jun 11 02:19:36 PM PDT 24
Finished Jun 11 02:19:39 PM PDT 24
Peak memory 220276 kb
Host smart-7def8c59-8bed-4aee-93ca-83ac2460089d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915385479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3915385479
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3327659440
Short name T889
Test name
Test status
Simulation time 29382046 ps
CPU time 0.95 seconds
Started Jun 11 02:19:37 PM PDT 24
Finished Jun 11 02:19:40 PM PDT 24
Peak memory 216168 kb
Host smart-be089e2e-b13f-4432-b5b6-a3bb156c05e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327659440 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3327659440
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2963733139
Short name T519
Test name
Test status
Simulation time 27425473 ps
CPU time 1.02 seconds
Started Jun 11 02:19:37 PM PDT 24
Finished Jun 11 02:19:39 PM PDT 24
Peak memory 215460 kb
Host smart-50da4c8c-1fca-4565-985e-bbb0c9cb55dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963733139 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2963733139
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1277099208
Short name T696
Test name
Test status
Simulation time 324471131 ps
CPU time 6.71 seconds
Started Jun 11 02:19:36 PM PDT 24
Finished Jun 11 02:19:44 PM PDT 24
Peak memory 218968 kb
Host smart-5accfa22-5191-4d47-8050-66edca52bcfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277099208 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1277099208
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1023923673
Short name T470
Test name
Test status
Simulation time 11637240974 ps
CPU time 148.88 seconds
Started Jun 11 02:19:40 PM PDT 24
Finished Jun 11 02:22:10 PM PDT 24
Peak memory 222392 kb
Host smart-6eb4363c-8df9-470e-86ea-0f30c5c0ddf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023923673 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1023923673
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2308484395
Short name T374
Test name
Test status
Simulation time 52640091 ps
CPU time 1.84 seconds
Started Jun 11 02:22:35 PM PDT 24
Finished Jun 11 02:22:39 PM PDT 24
Peak memory 218596 kb
Host smart-a43a4f2d-56e5-4a4b-a765-5e083d1b5e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308484395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2308484395
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3196412143
Short name T582
Test name
Test status
Simulation time 445739086 ps
CPU time 4.73 seconds
Started Jun 11 02:22:36 PM PDT 24
Finished Jun 11 02:22:43 PM PDT 24
Peak memory 220312 kb
Host smart-4b371684-f150-4b98-a9ae-c585b7e8dad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196412143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3196412143
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1651050855
Short name T252
Test name
Test status
Simulation time 111368069 ps
CPU time 1.16 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:36 PM PDT 24
Peak memory 217508 kb
Host smart-c51a92df-0e08-4e8e-aee2-df1f48547d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651050855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1651050855
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.680180326
Short name T378
Test name
Test status
Simulation time 118045755 ps
CPU time 1.48 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:37 PM PDT 24
Peak memory 219304 kb
Host smart-1fbac811-c368-4428-b2d2-b24d01befd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680180326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.680180326
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.394776264
Short name T815
Test name
Test status
Simulation time 54649706 ps
CPU time 1.38 seconds
Started Jun 11 02:22:33 PM PDT 24
Finished Jun 11 02:22:35 PM PDT 24
Peak memory 217992 kb
Host smart-25bf7abd-e3e0-429b-82b3-dab0572c4f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394776264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.394776264
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2015076129
Short name T790
Test name
Test status
Simulation time 39419366 ps
CPU time 1.42 seconds
Started Jun 11 02:22:38 PM PDT 24
Finished Jun 11 02:22:41 PM PDT 24
Peak memory 217668 kb
Host smart-15761215-fc9c-450a-b4a8-00684fffda39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015076129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2015076129
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1147621206
Short name T759
Test name
Test status
Simulation time 84136842 ps
CPU time 1.05 seconds
Started Jun 11 02:22:38 PM PDT 24
Finished Jun 11 02:22:40 PM PDT 24
Peak memory 217744 kb
Host smart-da3e77c9-43d7-422d-801c-15f55de2de5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147621206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1147621206
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.82419797
Short name T507
Test name
Test status
Simulation time 26384940 ps
CPU time 1.19 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:37 PM PDT 24
Peak memory 220232 kb
Host smart-1b15fa90-b7d9-4d05-8220-849cc9fe87e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82419797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.82419797
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.117831940
Short name T802
Test name
Test status
Simulation time 33286667 ps
CPU time 1.45 seconds
Started Jun 11 02:22:41 PM PDT 24
Finished Jun 11 02:22:43 PM PDT 24
Peak memory 218756 kb
Host smart-32e117af-0803-4fcf-9e20-f0a7fb56cee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117831940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.117831940
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3856054278
Short name T950
Test name
Test status
Simulation time 22279474 ps
CPU time 1.14 seconds
Started Jun 11 02:19:38 PM PDT 24
Finished Jun 11 02:19:40 PM PDT 24
Peak memory 219960 kb
Host smart-3e4c33c4-4920-4a49-8ac4-5ba22cb53e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856054278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3856054278
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1451610180
Short name T348
Test name
Test status
Simulation time 18671277 ps
CPU time 1.05 seconds
Started Jun 11 02:19:36 PM PDT 24
Finished Jun 11 02:19:38 PM PDT 24
Peak memory 215572 kb
Host smart-0acc984f-c99a-47d7-9030-ed394e563382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451610180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1451610180
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.4227896629
Short name T936
Test name
Test status
Simulation time 89488399 ps
CPU time 1.07 seconds
Started Jun 11 02:19:36 PM PDT 24
Finished Jun 11 02:19:38 PM PDT 24
Peak memory 219956 kb
Host smart-fe238201-e93b-4ee4-9a4f-818fdc77646b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227896629 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.4227896629
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_genbits.1026331992
Short name T978
Test name
Test status
Simulation time 147998252 ps
CPU time 1.29 seconds
Started Jun 11 02:19:35 PM PDT 24
Finished Jun 11 02:19:37 PM PDT 24
Peak memory 218740 kb
Host smart-40c1810e-9006-49b3-92d1-491875067a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026331992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1026331992
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3654257629
Short name T723
Test name
Test status
Simulation time 29129165 ps
CPU time 1.07 seconds
Started Jun 11 02:19:36 PM PDT 24
Finished Jun 11 02:19:38 PM PDT 24
Peak memory 224304 kb
Host smart-736c06f0-e019-4989-8582-135a8956a679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654257629 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3654257629
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1234585696
Short name T410
Test name
Test status
Simulation time 32453052 ps
CPU time 0.99 seconds
Started Jun 11 02:19:38 PM PDT 24
Finished Jun 11 02:19:40 PM PDT 24
Peak memory 215624 kb
Host smart-f742d32a-950a-424b-9082-489a79d196e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234585696 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1234585696
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3554299064
Short name T355
Test name
Test status
Simulation time 345252369 ps
CPU time 2.25 seconds
Started Jun 11 02:19:36 PM PDT 24
Finished Jun 11 02:19:40 PM PDT 24
Peak memory 217600 kb
Host smart-4d61fddc-3f6a-4938-9272-4475f1f9eec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554299064 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3554299064
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2750579239
Short name T955
Test name
Test status
Simulation time 58637235407 ps
CPU time 813.81 seconds
Started Jun 11 02:19:36 PM PDT 24
Finished Jun 11 02:33:11 PM PDT 24
Peak memory 219260 kb
Host smart-de287fb2-e7b9-4a40-b6e7-518a07c50727
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750579239 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2750579239
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2618005650
Short name T623
Test name
Test status
Simulation time 23996535 ps
CPU time 1.12 seconds
Started Jun 11 02:22:35 PM PDT 24
Finished Jun 11 02:22:38 PM PDT 24
Peak memory 217668 kb
Host smart-415b4ed5-e331-4538-8b4e-eb93effa39ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618005650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2618005650
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1090618157
Short name T658
Test name
Test status
Simulation time 295699678 ps
CPU time 3.46 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:39 PM PDT 24
Peak memory 220572 kb
Host smart-02ee19d9-9806-4508-910a-c622a7d08313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090618157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1090618157
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2077342632
Short name T586
Test name
Test status
Simulation time 60762689 ps
CPU time 1.09 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:37 PM PDT 24
Peak memory 217560 kb
Host smart-4d23d57f-8625-4b56-bef3-043c545c7b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077342632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2077342632
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3950131580
Short name T745
Test name
Test status
Simulation time 124314952 ps
CPU time 1.57 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:37 PM PDT 24
Peak memory 217720 kb
Host smart-27a45391-480d-4167-a5d4-ddc1d3ad6ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950131580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3950131580
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2789702793
Short name T824
Test name
Test status
Simulation time 43177450 ps
CPU time 1.15 seconds
Started Jun 11 02:22:35 PM PDT 24
Finished Jun 11 02:22:38 PM PDT 24
Peak memory 217604 kb
Host smart-1aaf0ef1-c6e3-42d5-895f-183e94da2264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789702793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2789702793
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1210570387
Short name T775
Test name
Test status
Simulation time 34991142 ps
CPU time 1.52 seconds
Started Jun 11 02:22:36 PM PDT 24
Finished Jun 11 02:22:40 PM PDT 24
Peak memory 215664 kb
Host smart-51181184-86d3-486a-afcd-e55984a39219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210570387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1210570387
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.340591446
Short name T642
Test name
Test status
Simulation time 66789612 ps
CPU time 1.26 seconds
Started Jun 11 02:22:35 PM PDT 24
Finished Jun 11 02:22:38 PM PDT 24
Peak memory 217700 kb
Host smart-f34a6980-7635-4e8a-bc30-92c76ceed478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340591446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.340591446
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.527878265
Short name T928
Test name
Test status
Simulation time 56507621 ps
CPU time 1.2 seconds
Started Jun 11 02:22:40 PM PDT 24
Finished Jun 11 02:22:42 PM PDT 24
Peak memory 218864 kb
Host smart-76145f4f-cecf-45e8-81ab-154e04529f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527878265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.527878265
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1164733564
Short name T312
Test name
Test status
Simulation time 48298810 ps
CPU time 2.04 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:38 PM PDT 24
Peak memory 218700 kb
Host smart-1a3dfd66-e2a5-4aee-b4fd-f14bb6076e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164733564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1164733564
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1878555659
Short name T242
Test name
Test status
Simulation time 134258176 ps
CPU time 1.03 seconds
Started Jun 11 02:22:36 PM PDT 24
Finished Jun 11 02:22:39 PM PDT 24
Peak memory 215612 kb
Host smart-541198e0-be8f-4d36-9d41-7f4b694496fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878555659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1878555659
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert_test.4176628588
Short name T719
Test name
Test status
Simulation time 116183010 ps
CPU time 0.86 seconds
Started Jun 11 02:19:51 PM PDT 24
Finished Jun 11 02:19:53 PM PDT 24
Peak memory 207076 kb
Host smart-31b387e5-f2af-4104-a707-45d00b871ff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176628588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.4176628588
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_err.1509032467
Short name T575
Test name
Test status
Simulation time 19015453 ps
CPU time 1.1 seconds
Started Jun 11 02:19:37 PM PDT 24
Finished Jun 11 02:19:39 PM PDT 24
Peak memory 218692 kb
Host smart-b70d1705-2851-46a2-8953-a8557d61ff94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509032467 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1509032467
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2821849227
Short name T915
Test name
Test status
Simulation time 87298517 ps
CPU time 2.83 seconds
Started Jun 11 02:19:39 PM PDT 24
Finished Jun 11 02:19:43 PM PDT 24
Peak memory 220156 kb
Host smart-080da348-55b5-4d33-90dc-5314b2ac349c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821849227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2821849227
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.90369117
Short name T880
Test name
Test status
Simulation time 23217862 ps
CPU time 1.31 seconds
Started Jun 11 02:19:39 PM PDT 24
Finished Jun 11 02:19:41 PM PDT 24
Peak memory 224352 kb
Host smart-c89eb19a-88b0-47d1-8b0f-0cbaae1c6231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90369117 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.90369117
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2031263870
Short name T349
Test name
Test status
Simulation time 23647448 ps
CPU time 0.95 seconds
Started Jun 11 02:19:36 PM PDT 24
Finished Jun 11 02:19:38 PM PDT 24
Peak memory 215564 kb
Host smart-b52a6713-5c1a-4044-a637-5d5f74b13236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031263870 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2031263870
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2086592304
Short name T902
Test name
Test status
Simulation time 374848215 ps
CPU time 4.02 seconds
Started Jun 11 02:19:36 PM PDT 24
Finished Jun 11 02:19:41 PM PDT 24
Peak memory 217324 kb
Host smart-d56e7664-51de-40d5-85e1-610d46a28d9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086592304 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2086592304
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3794983192
Short name T309
Test name
Test status
Simulation time 37105400870 ps
CPU time 780.77 seconds
Started Jun 11 02:19:39 PM PDT 24
Finished Jun 11 02:32:41 PM PDT 24
Peak memory 218340 kb
Host smart-21e2bd40-41f6-4485-9945-3e79e4613051
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794983192 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3794983192
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.238309734
Short name T524
Test name
Test status
Simulation time 192473212 ps
CPU time 1.24 seconds
Started Jun 11 02:22:35 PM PDT 24
Finished Jun 11 02:22:38 PM PDT 24
Peak memory 219892 kb
Host smart-906d328d-4945-4e76-b148-5f8388593d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238309734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.238309734
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2176430202
Short name T361
Test name
Test status
Simulation time 60551259 ps
CPU time 1.05 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:36 PM PDT 24
Peak memory 217724 kb
Host smart-08a9cbb8-ca8b-414a-bc7d-0a3cf3c3b692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176430202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2176430202
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2947924687
Short name T721
Test name
Test status
Simulation time 40287012 ps
CPU time 1.62 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:37 PM PDT 24
Peak memory 218872 kb
Host smart-afe589af-7348-4483-be4d-88f38cad702c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947924687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2947924687
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1815559592
Short name T465
Test name
Test status
Simulation time 42146120 ps
CPU time 1.56 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:37 PM PDT 24
Peak memory 217484 kb
Host smart-a043ed99-8ba6-4f7a-853f-60e5a28a663d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815559592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1815559592
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.64337341
Short name T862
Test name
Test status
Simulation time 107168890 ps
CPU time 1.55 seconds
Started Jun 11 02:22:32 PM PDT 24
Finished Jun 11 02:22:34 PM PDT 24
Peak memory 218864 kb
Host smart-dcbab9dd-aad1-4926-88a6-7ba227769865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64337341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.64337341
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.4145374260
Short name T476
Test name
Test status
Simulation time 54700843 ps
CPU time 1.41 seconds
Started Jun 11 02:22:36 PM PDT 24
Finished Jun 11 02:22:40 PM PDT 24
Peak memory 220448 kb
Host smart-fb3036dc-79ad-4d3b-9ae7-5ba770cbdd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145374260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.4145374260
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2515931523
Short name T92
Test name
Test status
Simulation time 81727271 ps
CPU time 1.3 seconds
Started Jun 11 02:22:37 PM PDT 24
Finished Jun 11 02:22:40 PM PDT 24
Peak memory 217644 kb
Host smart-b99ff741-b20e-4365-9c54-b00a41ee8413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515931523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2515931523
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.4161970648
Short name T68
Test name
Test status
Simulation time 191418091 ps
CPU time 1.09 seconds
Started Jun 11 02:22:35 PM PDT 24
Finished Jun 11 02:22:37 PM PDT 24
Peak memory 215592 kb
Host smart-df037847-5c6c-4964-8ec5-c07822c7ea2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161970648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.4161970648
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.935331098
Short name T463
Test name
Test status
Simulation time 32108454 ps
CPU time 1.41 seconds
Started Jun 11 02:22:36 PM PDT 24
Finished Jun 11 02:22:39 PM PDT 24
Peak memory 217676 kb
Host smart-2f2e8620-ec3e-4447-a48c-488b715816f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935331098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.935331098
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.287782838
Short name T694
Test name
Test status
Simulation time 161863382 ps
CPU time 3.27 seconds
Started Jun 11 02:22:40 PM PDT 24
Finished Jun 11 02:22:44 PM PDT 24
Peak memory 220396 kb
Host smart-30160ac8-9595-47bd-85f4-db4a005f45a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287782838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.287782838
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1461414476
Short name T636
Test name
Test status
Simulation time 213130294 ps
CPU time 1.24 seconds
Started Jun 11 02:19:50 PM PDT 24
Finished Jun 11 02:19:52 PM PDT 24
Peak memory 220848 kb
Host smart-1fd0ceae-2cb9-40a6-96fa-e8bd83b16c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461414476 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1461414476
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.540271368
Short name T744
Test name
Test status
Simulation time 25266145 ps
CPU time 0.92 seconds
Started Jun 11 02:20:01 PM PDT 24
Finished Jun 11 02:20:04 PM PDT 24
Peak memory 207096 kb
Host smart-b9c85b70-faf0-4257-a561-049781965be8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540271368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.540271368
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.950792707
Short name T512
Test name
Test status
Simulation time 28742747 ps
CPU time 0.87 seconds
Started Jun 11 02:19:50 PM PDT 24
Finished Jun 11 02:19:52 PM PDT 24
Peak memory 216264 kb
Host smart-c7447715-dc7c-4a42-84ba-66e320b735ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950792707 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.950792707
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.93115891
Short name T4
Test name
Test status
Simulation time 21147494 ps
CPU time 1.15 seconds
Started Jun 11 02:19:50 PM PDT 24
Finished Jun 11 02:19:52 PM PDT 24
Peak memory 220096 kb
Host smart-7ce0de23-9737-4688-ba2c-d4aa83159018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93115891 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.93115891
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_intr.243548715
Short name T601
Test name
Test status
Simulation time 20688594 ps
CPU time 1.1 seconds
Started Jun 11 02:19:53 PM PDT 24
Finished Jun 11 02:19:54 PM PDT 24
Peak memory 215840 kb
Host smart-c641ac45-af10-4277-bcde-62e00d22530b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243548715 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.243548715
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2884279665
Short name T709
Test name
Test status
Simulation time 24000752 ps
CPU time 0.99 seconds
Started Jun 11 02:19:51 PM PDT 24
Finished Jun 11 02:19:53 PM PDT 24
Peak memory 215460 kb
Host smart-e2819ae6-75d3-441c-bb92-c2a2bcf11890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884279665 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2884279665
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1847575329
Short name T839
Test name
Test status
Simulation time 230375685 ps
CPU time 5.12 seconds
Started Jun 11 02:19:50 PM PDT 24
Finished Jun 11 02:19:56 PM PDT 24
Peak memory 220296 kb
Host smart-85e0e5e7-fe9f-4c9f-8592-3edf352602af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847575329 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1847575329
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.82162905
Short name T372
Test name
Test status
Simulation time 84625384217 ps
CPU time 474.53 seconds
Started Jun 11 02:19:51 PM PDT 24
Finished Jun 11 02:27:46 PM PDT 24
Peak memory 219692 kb
Host smart-83f073a6-68ae-4ed7-a63f-0f7e21f0824d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82162905 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.82162905
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1425630527
Short name T572
Test name
Test status
Simulation time 61475149 ps
CPU time 1.31 seconds
Started Jun 11 02:22:40 PM PDT 24
Finished Jun 11 02:22:43 PM PDT 24
Peak memory 217600 kb
Host smart-9c923150-b547-4ebf-81d1-cdfc4e85b87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425630527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1425630527
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1648347163
Short name T663
Test name
Test status
Simulation time 64726146 ps
CPU time 1.24 seconds
Started Jun 11 02:22:38 PM PDT 24
Finished Jun 11 02:22:41 PM PDT 24
Peak memory 219956 kb
Host smart-3b9bf9da-9579-4dd0-95be-0bcd081b2add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648347163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1648347163
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.935446666
Short name T564
Test name
Test status
Simulation time 121293399 ps
CPU time 3 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:39 PM PDT 24
Peak memory 219168 kb
Host smart-b6b78d00-b12d-43c2-a1d5-6c87124a56e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935446666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.935446666
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2774833755
Short name T471
Test name
Test status
Simulation time 118975888 ps
CPU time 2.7 seconds
Started Jun 11 02:22:36 PM PDT 24
Finished Jun 11 02:22:40 PM PDT 24
Peak memory 220360 kb
Host smart-fe6d7625-d4b9-4f65-a660-5f73b64c2f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774833755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2774833755
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3618089818
Short name T670
Test name
Test status
Simulation time 54924595 ps
CPU time 1.16 seconds
Started Jun 11 02:22:41 PM PDT 24
Finished Jun 11 02:22:43 PM PDT 24
Peak memory 218772 kb
Host smart-ad2def69-e6af-4c1a-9322-b05f7a2252de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618089818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3618089818
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2509334730
Short name T43
Test name
Test status
Simulation time 39582389 ps
CPU time 1.38 seconds
Started Jun 11 02:22:35 PM PDT 24
Finished Jun 11 02:22:38 PM PDT 24
Peak memory 218808 kb
Host smart-4bf4e6b1-b37c-4c0e-955d-cc2c6477b57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509334730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2509334730
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3964248708
Short name T896
Test name
Test status
Simulation time 83238513 ps
CPU time 1.3 seconds
Started Jun 11 02:22:35 PM PDT 24
Finished Jun 11 02:22:37 PM PDT 24
Peak memory 219328 kb
Host smart-4f45bdd6-c37d-4511-ad6a-9e17ccc94a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964248708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3964248708
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.853816316
Short name T322
Test name
Test status
Simulation time 46388437 ps
CPU time 1.84 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:37 PM PDT 24
Peak memory 218920 kb
Host smart-2b53b26e-3a61-4760-8e45-c328e3ec2645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853816316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.853816316
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.262698371
Short name T418
Test name
Test status
Simulation time 31216970 ps
CPU time 1.25 seconds
Started Jun 11 02:22:35 PM PDT 24
Finished Jun 11 02:22:39 PM PDT 24
Peak memory 217656 kb
Host smart-fc8dc202-cfb6-46cd-a9e8-b649805e0d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262698371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.262698371
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.950007862
Short name T810
Test name
Test status
Simulation time 108170117 ps
CPU time 1.61 seconds
Started Jun 11 02:22:35 PM PDT 24
Finished Jun 11 02:22:38 PM PDT 24
Peak memory 218900 kb
Host smart-a74e4373-f706-45b2-b957-afdfcfd8170b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950007862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.950007862
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1072452862
Short name T537
Test name
Test status
Simulation time 27328453 ps
CPU time 1.17 seconds
Started Jun 11 02:19:52 PM PDT 24
Finished Jun 11 02:19:54 PM PDT 24
Peak memory 218884 kb
Host smart-1803ba03-a079-4f29-ba63-9ef254bbbfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072452862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1072452862
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2135945098
Short name T917
Test name
Test status
Simulation time 20346730 ps
CPU time 0.96 seconds
Started Jun 11 02:20:01 PM PDT 24
Finished Jun 11 02:20:04 PM PDT 24
Peak memory 207080 kb
Host smart-4e93bc60-0830-452d-ab5e-5e03a197f67e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135945098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2135945098
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2871432635
Short name T866
Test name
Test status
Simulation time 74560978 ps
CPU time 1.06 seconds
Started Jun 11 02:19:54 PM PDT 24
Finished Jun 11 02:19:56 PM PDT 24
Peak memory 219520 kb
Host smart-832b2e3b-203b-46f4-a354-c619c179d278
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871432635 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2871432635
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.709260941
Short name T144
Test name
Test status
Simulation time 132870524 ps
CPU time 1.14 seconds
Started Jun 11 02:19:58 PM PDT 24
Finished Jun 11 02:20:00 PM PDT 24
Peak memory 229896 kb
Host smart-f0805c2c-4c63-4ed7-a7d4-d6c48862ccbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709260941 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.709260941
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.732413369
Short name T724
Test name
Test status
Simulation time 44026613 ps
CPU time 1.09 seconds
Started Jun 11 02:19:59 PM PDT 24
Finished Jun 11 02:20:01 PM PDT 24
Peak memory 217432 kb
Host smart-6a7ce713-067b-4052-9144-b8f81ade5e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732413369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.732413369
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2555309116
Short name T981
Test name
Test status
Simulation time 25155492 ps
CPU time 1.19 seconds
Started Jun 11 02:19:58 PM PDT 24
Finished Jun 11 02:20:00 PM PDT 24
Peak memory 224364 kb
Host smart-a65eae94-ca77-4684-b222-ea7f3d50c7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555309116 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2555309116
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2173836646
Short name T717
Test name
Test status
Simulation time 39971362 ps
CPU time 0.92 seconds
Started Jun 11 02:19:53 PM PDT 24
Finished Jun 11 02:19:54 PM PDT 24
Peak memory 215600 kb
Host smart-c97a6f81-0d88-4785-9ee8-3feb56d1664a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173836646 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2173836646
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1459469771
Short name T847
Test name
Test status
Simulation time 446473167 ps
CPU time 4.67 seconds
Started Jun 11 02:19:59 PM PDT 24
Finished Jun 11 02:20:04 PM PDT 24
Peak memory 215716 kb
Host smart-458b6b0b-93f7-43ab-9dfc-85c06f315cbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459469771 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1459469771
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3236388507
Short name T662
Test name
Test status
Simulation time 13525336650 ps
CPU time 357.71 seconds
Started Jun 11 02:19:51 PM PDT 24
Finished Jun 11 02:25:50 PM PDT 24
Peak memory 223132 kb
Host smart-6e74ac98-a3f2-48c7-b7eb-bac5756930ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236388507 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3236388507
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/251.edn_genbits.3475740611
Short name T23
Test name
Test status
Simulation time 49249547 ps
CPU time 1.18 seconds
Started Jun 11 02:22:35 PM PDT 24
Finished Jun 11 02:22:38 PM PDT 24
Peak memory 217608 kb
Host smart-0a967359-bf39-4393-9b1c-54f4bd08918a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475740611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3475740611
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3870554148
Short name T492
Test name
Test status
Simulation time 34251381 ps
CPU time 1.39 seconds
Started Jun 11 02:22:35 PM PDT 24
Finished Jun 11 02:22:38 PM PDT 24
Peak memory 220392 kb
Host smart-1f1b3e1e-e649-4de3-accd-1d49061988c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870554148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3870554148
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1818652582
Short name T479
Test name
Test status
Simulation time 80419407 ps
CPU time 1.36 seconds
Started Jun 11 02:22:36 PM PDT 24
Finished Jun 11 02:22:39 PM PDT 24
Peak memory 220236 kb
Host smart-524d2821-c565-413e-958a-c3f117d8a6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818652582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1818652582
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2618410513
Short name T971
Test name
Test status
Simulation time 37029270 ps
CPU time 1.31 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:36 PM PDT 24
Peak memory 217620 kb
Host smart-e70ef236-1a2a-48f3-b3a6-1c8f28a01184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618410513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2618410513
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2997118120
Short name T342
Test name
Test status
Simulation time 61286765 ps
CPU time 1.08 seconds
Started Jun 11 02:22:35 PM PDT 24
Finished Jun 11 02:22:38 PM PDT 24
Peak memory 217720 kb
Host smart-ccf58b88-8af9-41b5-b24a-24f97676d0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997118120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2997118120
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1851291261
Short name T326
Test name
Test status
Simulation time 66063475 ps
CPU time 1.43 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:38 PM PDT 24
Peak memory 217664 kb
Host smart-e0e9c6dd-8bc4-497c-bb71-cb9666ba24e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851291261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1851291261
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1454548824
Short name T62
Test name
Test status
Simulation time 37774762 ps
CPU time 1.49 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:37 PM PDT 24
Peak memory 217700 kb
Host smart-c0c57583-14f0-4152-9b7f-b285190d857f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454548824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1454548824
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3711911985
Short name T318
Test name
Test status
Simulation time 60606057 ps
CPU time 1.73 seconds
Started Jun 11 02:22:34 PM PDT 24
Finished Jun 11 02:22:38 PM PDT 24
Peak memory 219276 kb
Host smart-61fee9c0-85d0-454a-ac90-480b76efeb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711911985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3711911985
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3351013771
Short name T543
Test name
Test status
Simulation time 60883720 ps
CPU time 1.4 seconds
Started Jun 11 02:22:36 PM PDT 24
Finished Jun 11 02:22:39 PM PDT 24
Peak memory 215588 kb
Host smart-b517d916-69bb-4519-8f29-61950e4fda5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351013771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3351013771
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.4077113123
Short name T964
Test name
Test status
Simulation time 74041966 ps
CPU time 1.12 seconds
Started Jun 11 02:20:02 PM PDT 24
Finished Jun 11 02:20:05 PM PDT 24
Peak memory 219812 kb
Host smart-38673d1a-fedf-4ad7-a4cc-cc18f47ed339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077113123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.4077113123
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.4149387986
Short name T907
Test name
Test status
Simulation time 23100895 ps
CPU time 1.15 seconds
Started Jun 11 02:20:01 PM PDT 24
Finished Jun 11 02:20:04 PM PDT 24
Peak memory 207140 kb
Host smart-f088230b-aa00-4cb0-a484-e8455e26fd20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149387986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.4149387986
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3656518419
Short name T181
Test name
Test status
Simulation time 14809523 ps
CPU time 0.96 seconds
Started Jun 11 02:20:01 PM PDT 24
Finished Jun 11 02:20:04 PM PDT 24
Peak memory 216672 kb
Host smart-8f3bbb54-1b9f-49bc-b00d-2aaeeb79bab3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656518419 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3656518419
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.933147464
Short name T384
Test name
Test status
Simulation time 21648082 ps
CPU time 1 seconds
Started Jun 11 02:20:02 PM PDT 24
Finished Jun 11 02:20:06 PM PDT 24
Peak memory 217136 kb
Host smart-5b6ef2d8-1a77-41e1-aa0e-42e80a319ba6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933147464 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_di
sable_auto_req_mode.933147464
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.199257486
Short name T840
Test name
Test status
Simulation time 20120305 ps
CPU time 1.18 seconds
Started Jun 11 02:20:01 PM PDT 24
Finished Jun 11 02:20:04 PM PDT 24
Peak memory 219836 kb
Host smart-18ffeb12-7ec8-4fa3-b90d-dc3a72b2623c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199257486 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.199257486
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1674944215
Short name T737
Test name
Test status
Simulation time 44767090 ps
CPU time 1.37 seconds
Started Jun 11 02:20:00 PM PDT 24
Finished Jun 11 02:20:02 PM PDT 24
Peak memory 220276 kb
Host smart-13e2a4d8-b1df-4173-aab4-8b4f07bfe4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674944215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1674944215
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.304661699
Short name T914
Test name
Test status
Simulation time 21277764 ps
CPU time 1.11 seconds
Started Jun 11 02:20:02 PM PDT 24
Finished Jun 11 02:20:06 PM PDT 24
Peak memory 215856 kb
Host smart-64fc25c2-e2d4-4ee7-a9b7-12d69b12302d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304661699 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.304661699
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.75031227
Short name T385
Test name
Test status
Simulation time 16053241 ps
CPU time 1 seconds
Started Jun 11 02:20:02 PM PDT 24
Finished Jun 11 02:20:05 PM PDT 24
Peak memory 215584 kb
Host smart-745336ea-fd4e-4320-9204-c0ba29892197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75031227 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.75031227
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2287511140
Short name T704
Test name
Test status
Simulation time 362846167 ps
CPU time 6.84 seconds
Started Jun 11 02:20:04 PM PDT 24
Finished Jun 11 02:20:14 PM PDT 24
Peak memory 215460 kb
Host smart-e451b904-fffd-432a-84a1-49452f522b5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287511140 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2287511140
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2744022023
Short name T942
Test name
Test status
Simulation time 63160266055 ps
CPU time 251.89 seconds
Started Jun 11 02:20:03 PM PDT 24
Finished Jun 11 02:24:17 PM PDT 24
Peak memory 224028 kb
Host smart-7ec0355c-876c-4eb4-b86b-0a1745032602
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744022023 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2744022023
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.2021452676
Short name T674
Test name
Test status
Simulation time 31725988 ps
CPU time 1.35 seconds
Started Jun 11 02:22:37 PM PDT 24
Finished Jun 11 02:22:40 PM PDT 24
Peak memory 217584 kb
Host smart-ee4919ec-8363-43d9-b7c4-205033a2fc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021452676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2021452676
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1597007173
Short name T514
Test name
Test status
Simulation time 119446318 ps
CPU time 1.26 seconds
Started Jun 11 02:22:44 PM PDT 24
Finished Jun 11 02:22:45 PM PDT 24
Peak memory 217728 kb
Host smart-d2cf2c61-22f2-4c05-82cb-722c1eb71519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597007173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1597007173
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.6892294
Short name T549
Test name
Test status
Simulation time 192834196 ps
CPU time 1.58 seconds
Started Jun 11 02:22:44 PM PDT 24
Finished Jun 11 02:22:46 PM PDT 24
Peak memory 218828 kb
Host smart-f5456787-82a2-4992-9291-025736319c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6892294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.6892294
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1905638499
Short name T46
Test name
Test status
Simulation time 44449776 ps
CPU time 1.67 seconds
Started Jun 11 02:22:45 PM PDT 24
Finished Jun 11 02:22:47 PM PDT 24
Peak memory 218752 kb
Host smart-135c2b1d-0571-4d09-a42f-41c411483ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905638499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1905638499
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.4077757920
Short name T315
Test name
Test status
Simulation time 74555422 ps
CPU time 1.22 seconds
Started Jun 11 02:22:45 PM PDT 24
Finished Jun 11 02:22:47 PM PDT 24
Peak memory 218948 kb
Host smart-a16e6058-d7ef-4a58-bd2b-df94e7cc07b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077757920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.4077757920
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2010365841
Short name T538
Test name
Test status
Simulation time 46175023 ps
CPU time 1.49 seconds
Started Jun 11 02:22:46 PM PDT 24
Finished Jun 11 02:22:48 PM PDT 24
Peak memory 218876 kb
Host smart-0f88f144-02d3-4387-94ff-5fa08b789817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010365841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2010365841
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2202648264
Short name T560
Test name
Test status
Simulation time 317722250 ps
CPU time 1.4 seconds
Started Jun 11 02:22:46 PM PDT 24
Finished Jun 11 02:22:49 PM PDT 24
Peak memory 217740 kb
Host smart-472f097b-ac23-43e6-82bf-b2b79557b4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202648264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2202648264
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3149978822
Short name T316
Test name
Test status
Simulation time 37946264 ps
CPU time 1.55 seconds
Started Jun 11 02:22:45 PM PDT 24
Finished Jun 11 02:22:48 PM PDT 24
Peak memory 218788 kb
Host smart-f69b7717-0ea3-49e3-b8db-4414c31b68fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149978822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3149978822
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.3860497718
Short name T938
Test name
Test status
Simulation time 56887857 ps
CPU time 0.99 seconds
Started Jun 11 02:22:48 PM PDT 24
Finished Jun 11 02:22:50 PM PDT 24
Peak memory 217636 kb
Host smart-a15021ce-e7e0-414d-bdea-61f931718dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860497718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.3860497718
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3241784121
Short name T966
Test name
Test status
Simulation time 77629612 ps
CPU time 1.37 seconds
Started Jun 11 02:22:46 PM PDT 24
Finished Jun 11 02:22:49 PM PDT 24
Peak memory 218812 kb
Host smart-df0072ed-6f1f-427d-adc8-64d8a5d462f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241784121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3241784121
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3825326499
Short name T869
Test name
Test status
Simulation time 70979534 ps
CPU time 1.09 seconds
Started Jun 11 02:20:02 PM PDT 24
Finished Jun 11 02:20:06 PM PDT 24
Peak memory 218588 kb
Host smart-12a32b48-d173-43a2-bf2e-dcd7ec81f2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825326499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3825326499
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1451817922
Short name T478
Test name
Test status
Simulation time 69651579 ps
CPU time 1.05 seconds
Started Jun 11 02:20:01 PM PDT 24
Finished Jun 11 02:20:04 PM PDT 24
Peak memory 207236 kb
Host smart-c448004e-7a8a-470d-a675-26a320caf9d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451817922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1451817922
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.2209240246
Short name T186
Test name
Test status
Simulation time 32816749 ps
CPU time 0.86 seconds
Started Jun 11 02:20:02 PM PDT 24
Finished Jun 11 02:20:05 PM PDT 24
Peak memory 216608 kb
Host smart-4af33f01-268b-4c9f-a57a-f7ee5f94583f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209240246 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2209240246
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2573001887
Short name T683
Test name
Test status
Simulation time 38071461 ps
CPU time 1.14 seconds
Started Jun 11 02:20:02 PM PDT 24
Finished Jun 11 02:20:05 PM PDT 24
Peak memory 217136 kb
Host smart-59474eb5-43f6-4381-996d-2a93ce833eec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573001887 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2573001887
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3461660062
Short name T151
Test name
Test status
Simulation time 25382613 ps
CPU time 1.19 seconds
Started Jun 11 02:20:02 PM PDT 24
Finished Jun 11 02:20:05 PM PDT 24
Peak memory 220148 kb
Host smart-d0a05cdb-5037-4d1d-b334-394082907652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461660062 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3461660062
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1488690841
Short name T821
Test name
Test status
Simulation time 27256822 ps
CPU time 1.27 seconds
Started Jun 11 02:20:02 PM PDT 24
Finished Jun 11 02:20:06 PM PDT 24
Peak memory 217584 kb
Host smart-c2ba6056-d157-42d9-a40d-0b6976d99ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488690841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1488690841
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1764297387
Short name T794
Test name
Test status
Simulation time 23624341 ps
CPU time 1.07 seconds
Started Jun 11 02:20:04 PM PDT 24
Finished Jun 11 02:20:08 PM PDT 24
Peak memory 215828 kb
Host smart-3779d235-b540-45eb-b7c7-5b0ef3f55540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764297387 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1764297387
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1975794162
Short name T939
Test name
Test status
Simulation time 19245148 ps
CPU time 0.96 seconds
Started Jun 11 02:20:03 PM PDT 24
Finished Jun 11 02:20:07 PM PDT 24
Peak memory 215556 kb
Host smart-b5c486db-2db1-45a1-864c-bcea95786ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975794162 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1975794162
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3398903573
Short name T785
Test name
Test status
Simulation time 361318012 ps
CPU time 1.41 seconds
Started Jun 11 02:20:02 PM PDT 24
Finished Jun 11 02:20:06 PM PDT 24
Peak memory 217612 kb
Host smart-4a33bfc7-5a51-4a6b-afa2-424ee3146b4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398903573 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3398903573
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2581324769
Short name T66
Test name
Test status
Simulation time 377733477937 ps
CPU time 1742.57 seconds
Started Jun 11 02:20:02 PM PDT 24
Finished Jun 11 02:49:07 PM PDT 24
Peak memory 226836 kb
Host smart-c6768869-c077-464a-b78d-c47dfdec8aff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581324769 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2581324769
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1880237708
Short name T820
Test name
Test status
Simulation time 65097084 ps
CPU time 2.45 seconds
Started Jun 11 02:22:48 PM PDT 24
Finished Jun 11 02:22:51 PM PDT 24
Peak memory 219152 kb
Host smart-8e5f5273-40a1-46f6-a181-818ddc558261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880237708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1880237708
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.4116945847
Short name T395
Test name
Test status
Simulation time 33532844 ps
CPU time 1.28 seconds
Started Jun 11 02:22:46 PM PDT 24
Finished Jun 11 02:22:48 PM PDT 24
Peak memory 217632 kb
Host smart-db6573cd-e6c5-4520-8a65-0ac6a5aaa2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116945847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.4116945847
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3607695295
Short name T680
Test name
Test status
Simulation time 258268939 ps
CPU time 1.48 seconds
Started Jun 11 02:22:47 PM PDT 24
Finished Jun 11 02:22:49 PM PDT 24
Peak memory 217688 kb
Host smart-5850087a-55b9-4bbf-adb2-77e294276562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607695295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3607695295
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2315156122
Short name T577
Test name
Test status
Simulation time 127936769 ps
CPU time 2.56 seconds
Started Jun 11 02:22:46 PM PDT 24
Finished Jun 11 02:22:49 PM PDT 24
Peak memory 220048 kb
Host smart-5b38c904-ca62-421f-a16a-326d4256128a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315156122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2315156122
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3541602922
Short name T446
Test name
Test status
Simulation time 62660595 ps
CPU time 1.51 seconds
Started Jun 11 02:22:46 PM PDT 24
Finished Jun 11 02:22:49 PM PDT 24
Peak memory 215572 kb
Host smart-b74dd533-d86d-457a-8e98-73dba08a4d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541602922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3541602922
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.56298112
Short name T876
Test name
Test status
Simulation time 35745292 ps
CPU time 1.4 seconds
Started Jun 11 02:22:48 PM PDT 24
Finished Jun 11 02:22:51 PM PDT 24
Peak memory 218824 kb
Host smart-e9cffffa-9d85-4a53-b69b-e3c4fa65b31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56298112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.56298112
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3490856451
Short name T308
Test name
Test status
Simulation time 81629775 ps
CPU time 1.07 seconds
Started Jun 11 02:22:44 PM PDT 24
Finished Jun 11 02:22:45 PM PDT 24
Peak memory 217520 kb
Host smart-1d853660-8b47-40ba-a9c8-41f3301b5b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490856451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3490856451
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1628639560
Short name T536
Test name
Test status
Simulation time 56664777 ps
CPU time 1.01 seconds
Started Jun 11 02:22:45 PM PDT 24
Finished Jun 11 02:22:47 PM PDT 24
Peak memory 217560 kb
Host smart-83ca3411-5cfc-47e0-ae5a-5367e1477aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628639560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1628639560
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2761902971
Short name T838
Test name
Test status
Simulation time 85752819 ps
CPU time 2.51 seconds
Started Jun 11 02:22:46 PM PDT 24
Finished Jun 11 02:22:49 PM PDT 24
Peak memory 219180 kb
Host smart-48697e7d-f845-4ffe-ae74-3e303012bef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761902971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2761902971
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.671613729
Short name T521
Test name
Test status
Simulation time 89999202 ps
CPU time 1.16 seconds
Started Jun 11 02:22:47 PM PDT 24
Finished Jun 11 02:22:49 PM PDT 24
Peak memory 217300 kb
Host smart-fc5703cc-8dff-45f5-a803-d3cec3640bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671613729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.671613729
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2046434998
Short name T245
Test name
Test status
Simulation time 34237528 ps
CPU time 1.39 seconds
Started Jun 11 02:20:00 PM PDT 24
Finished Jun 11 02:20:03 PM PDT 24
Peak memory 215900 kb
Host smart-bdb43b17-b188-4aca-92f5-2def73d22e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046434998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2046434998
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1920089461
Short name T763
Test name
Test status
Simulation time 19634574 ps
CPU time 1.06 seconds
Started Jun 11 02:20:02 PM PDT 24
Finished Jun 11 02:20:06 PM PDT 24
Peak memory 207180 kb
Host smart-cb2ae454-bc6a-4c0d-a2ba-bca2a3ab6eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920089461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1920089461
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2667447887
Short name T701
Test name
Test status
Simulation time 12621828 ps
CPU time 0.93 seconds
Started Jun 11 02:20:01 PM PDT 24
Finished Jun 11 02:20:03 PM PDT 24
Peak memory 215844 kb
Host smart-48c97239-96a8-46c6-96ea-ad5438bbdb89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667447887 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2667447887
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3553921785
Short name T126
Test name
Test status
Simulation time 44467009 ps
CPU time 1.28 seconds
Started Jun 11 02:20:03 PM PDT 24
Finished Jun 11 02:20:07 PM PDT 24
Peak memory 217132 kb
Host smart-954171f7-3058-4023-a3ff-5cce0571b544
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553921785 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3553921785
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2368698716
Short name T805
Test name
Test status
Simulation time 34343453 ps
CPU time 1.16 seconds
Started Jun 11 02:20:00 PM PDT 24
Finished Jun 11 02:20:03 PM PDT 24
Peak memory 220960 kb
Host smart-291bb037-753a-418d-aec1-adbc30ef8e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368698716 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2368698716
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3714638220
Short name T868
Test name
Test status
Simulation time 321351619 ps
CPU time 1.33 seconds
Started Jun 11 02:20:05 PM PDT 24
Finished Jun 11 02:20:09 PM PDT 24
Peak memory 217592 kb
Host smart-e67cf35a-63c0-4753-b74c-08b8dc24f1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714638220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3714638220
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2653241040
Short name T728
Test name
Test status
Simulation time 21168980 ps
CPU time 1.19 seconds
Started Jun 11 02:20:06 PM PDT 24
Finished Jun 11 02:20:10 PM PDT 24
Peak memory 224340 kb
Host smart-ffff9300-f934-4270-baed-875116a142d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653241040 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2653241040
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.991109615
Short name T967
Test name
Test status
Simulation time 16702710 ps
CPU time 1.03 seconds
Started Jun 11 02:20:04 PM PDT 24
Finished Jun 11 02:20:08 PM PDT 24
Peak memory 215616 kb
Host smart-2a5d90b4-569b-4b80-a95b-794a336d3f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991109615 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.991109615
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2993904274
Short name T667
Test name
Test status
Simulation time 112147575 ps
CPU time 2.69 seconds
Started Jun 11 02:20:03 PM PDT 24
Finished Jun 11 02:20:08 PM PDT 24
Peak memory 217500 kb
Host smart-5a6f356e-1833-4a9f-b511-b107c44557b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993904274 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2993904274
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.741224011
Short name T544
Test name
Test status
Simulation time 25860257607 ps
CPU time 597.98 seconds
Started Jun 11 02:20:03 PM PDT 24
Finished Jun 11 02:30:03 PM PDT 24
Peak memory 218088 kb
Host smart-9c065e5e-df50-4865-87f1-13a06fbde5cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741224011 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.741224011
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.114137449
Short name T733
Test name
Test status
Simulation time 49332101 ps
CPU time 1.73 seconds
Started Jun 11 02:22:48 PM PDT 24
Finished Jun 11 02:22:51 PM PDT 24
Peak memory 217864 kb
Host smart-c3a11340-82e6-4a73-8005-f5625573f467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114137449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.114137449
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.67474133
Short name T555
Test name
Test status
Simulation time 35228342 ps
CPU time 1.21 seconds
Started Jun 11 02:22:47 PM PDT 24
Finished Jun 11 02:22:49 PM PDT 24
Peak memory 219984 kb
Host smart-853382dc-83dc-4e36-a217-ef8d8a4e9abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67474133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.67474133
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1224575644
Short name T325
Test name
Test status
Simulation time 198997393 ps
CPU time 3.72 seconds
Started Jun 11 02:22:47 PM PDT 24
Finished Jun 11 02:22:51 PM PDT 24
Peak memory 220540 kb
Host smart-565c4ead-d492-41cf-b729-b9d1bba28325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224575644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1224575644
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3878970995
Short name T468
Test name
Test status
Simulation time 93057497 ps
CPU time 1.24 seconds
Started Jun 11 02:22:47 PM PDT 24
Finished Jun 11 02:22:49 PM PDT 24
Peak memory 220064 kb
Host smart-dcccc4cc-a6ab-48b1-82a1-6753e2a252cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878970995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3878970995
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.282962176
Short name T923
Test name
Test status
Simulation time 159107130 ps
CPU time 2.58 seconds
Started Jun 11 02:22:46 PM PDT 24
Finished Jun 11 02:22:49 PM PDT 24
Peak memory 220584 kb
Host smart-6478df90-8fa1-4161-84a3-86ce7bd135bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282962176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.282962176
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2689073561
Short name T991
Test name
Test status
Simulation time 32357600 ps
CPU time 1.32 seconds
Started Jun 11 02:22:48 PM PDT 24
Finished Jun 11 02:22:50 PM PDT 24
Peak memory 220140 kb
Host smart-e3b4ba84-9175-4f8a-ae74-a33e61964442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689073561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2689073561
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1889398075
Short name T459
Test name
Test status
Simulation time 100235986 ps
CPU time 2.08 seconds
Started Jun 11 02:22:48 PM PDT 24
Finished Jun 11 02:22:51 PM PDT 24
Peak memory 220124 kb
Host smart-a6d042db-8873-4ff5-b966-de3043ce3f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889398075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1889398075
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2494821709
Short name T362
Test name
Test status
Simulation time 36436540 ps
CPU time 1.5 seconds
Started Jun 11 02:22:48 PM PDT 24
Finished Jun 11 02:22:50 PM PDT 24
Peak memory 217764 kb
Host smart-b412cb69-ee6e-4d98-ab54-aaa6d11cf768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494821709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2494821709
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1549444353
Short name T498
Test name
Test status
Simulation time 247892020 ps
CPU time 1.14 seconds
Started Jun 11 02:22:45 PM PDT 24
Finished Jun 11 02:22:47 PM PDT 24
Peak memory 215564 kb
Host smart-1adb9462-016d-4f1f-a29f-3493a18de534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549444353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1549444353
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.3060403636
Short name T292
Test name
Test status
Simulation time 33366963 ps
CPU time 1.36 seconds
Started Jun 11 02:20:03 PM PDT 24
Finished Jun 11 02:20:07 PM PDT 24
Peak memory 215928 kb
Host smart-db1a2fe9-3e4d-4467-80df-9473fc72c553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060403636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3060403636
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2608737429
Short name T428
Test name
Test status
Simulation time 19416177 ps
CPU time 1.08 seconds
Started Jun 11 02:20:00 PM PDT 24
Finished Jun 11 02:20:03 PM PDT 24
Peak memory 207144 kb
Host smart-8ed75e7b-d4db-4cba-a423-6da7cec3f35f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608737429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2608737429
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2985254962
Short name T166
Test name
Test status
Simulation time 12843095 ps
CPU time 0.93 seconds
Started Jun 11 02:20:01 PM PDT 24
Finished Jun 11 02:20:03 PM PDT 24
Peak memory 215660 kb
Host smart-9a26d944-5c9c-4680-985a-9d81e8f4c20f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985254962 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2985254962
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.604049392
Short name T128
Test name
Test status
Simulation time 106625186 ps
CPU time 1.13 seconds
Started Jun 11 02:20:03 PM PDT 24
Finished Jun 11 02:20:07 PM PDT 24
Peak memory 217080 kb
Host smart-46880184-8d27-43c2-80e8-5a639d03d8f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604049392 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.604049392
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1794912443
Short name T921
Test name
Test status
Simulation time 20993480 ps
CPU time 1.17 seconds
Started Jun 11 02:20:03 PM PDT 24
Finished Jun 11 02:20:07 PM PDT 24
Peak memory 220112 kb
Host smart-5cdcd499-ce52-4a9a-adc5-fa38f05a8288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794912443 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1794912443
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1697496000
Short name T933
Test name
Test status
Simulation time 51750804 ps
CPU time 1.02 seconds
Started Jun 11 02:20:02 PM PDT 24
Finished Jun 11 02:20:06 PM PDT 24
Peak memory 217636 kb
Host smart-627744af-db32-4c52-9114-a2601ee84fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697496000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1697496000
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.626704524
Short name T654
Test name
Test status
Simulation time 41070465 ps
CPU time 0.95 seconds
Started Jun 11 02:20:04 PM PDT 24
Finished Jun 11 02:20:08 PM PDT 24
Peak memory 215856 kb
Host smart-98a2abb8-e918-48d6-9591-b8a298af7274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626704524 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.626704524
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2858303262
Short name T368
Test name
Test status
Simulation time 94404043 ps
CPU time 0.95 seconds
Started Jun 11 02:20:01 PM PDT 24
Finished Jun 11 02:20:03 PM PDT 24
Peak memory 215412 kb
Host smart-c1242afa-6b14-4bff-8b41-5452c14f6baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858303262 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2858303262
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2199762947
Short name T714
Test name
Test status
Simulation time 357832327 ps
CPU time 4 seconds
Started Jun 11 02:20:03 PM PDT 24
Finished Jun 11 02:20:10 PM PDT 24
Peak memory 218764 kb
Host smart-3ed34a61-7402-4cc1-b5d3-2d9699993b48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199762947 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2199762947
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1288697239
Short name T517
Test name
Test status
Simulation time 78034356110 ps
CPU time 1750.39 seconds
Started Jun 11 02:20:03 PM PDT 24
Finished Jun 11 02:49:16 PM PDT 24
Peak memory 227368 kb
Host smart-aa6bbde2-0bde-4b14-bd59-9ba1933a2752
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288697239 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1288697239
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1175313712
Short name T509
Test name
Test status
Simulation time 55216434 ps
CPU time 1.25 seconds
Started Jun 11 02:22:45 PM PDT 24
Finished Jun 11 02:22:47 PM PDT 24
Peak memory 217452 kb
Host smart-2311008d-ff9b-47c1-94ae-ad5d8201b671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175313712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1175313712
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1530715700
Short name T295
Test name
Test status
Simulation time 47996562 ps
CPU time 1.86 seconds
Started Jun 11 02:22:47 PM PDT 24
Finished Jun 11 02:22:50 PM PDT 24
Peak memory 218672 kb
Host smart-f0d4aab3-d39c-484e-9f56-cb7cc9458f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530715700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1530715700
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1337356778
Short name T306
Test name
Test status
Simulation time 44806403 ps
CPU time 1.13 seconds
Started Jun 11 02:23:00 PM PDT 24
Finished Jun 11 02:23:02 PM PDT 24
Peak memory 217588 kb
Host smart-074e55be-588e-4480-afe2-e36212b48b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337356778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1337356778
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2048062233
Short name T79
Test name
Test status
Simulation time 103263835 ps
CPU time 1.08 seconds
Started Jun 11 02:22:56 PM PDT 24
Finished Jun 11 02:22:58 PM PDT 24
Peak memory 217420 kb
Host smart-fdae3475-ba11-41e2-b54d-c19aeb525885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048062233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2048062233
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3323073640
Short name T10
Test name
Test status
Simulation time 251545976 ps
CPU time 1.39 seconds
Started Jun 11 02:22:58 PM PDT 24
Finished Jun 11 02:23:01 PM PDT 24
Peak memory 219176 kb
Host smart-6988bd69-61d8-4348-87fe-9b30378cba74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323073640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3323073640
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.4174272267
Short name T249
Test name
Test status
Simulation time 82128191 ps
CPU time 1.22 seconds
Started Jun 11 02:23:03 PM PDT 24
Finished Jun 11 02:23:06 PM PDT 24
Peak memory 220164 kb
Host smart-2336a628-8718-471f-93a7-2c93cb72b577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174272267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.4174272267
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2458052220
Short name T357
Test name
Test status
Simulation time 28103361 ps
CPU time 1.29 seconds
Started Jun 11 02:23:02 PM PDT 24
Finished Jun 11 02:23:04 PM PDT 24
Peak memory 218780 kb
Host smart-7efac724-1fe4-4c6a-bdf4-b01222902f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458052220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2458052220
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.95610648
Short name T107
Test name
Test status
Simulation time 864298771 ps
CPU time 7.04 seconds
Started Jun 11 02:22:59 PM PDT 24
Finished Jun 11 02:23:07 PM PDT 24
Peak memory 217940 kb
Host smart-cb50ec05-e12b-4339-9a9d-f8167d4b93cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95610648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.95610648
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2348585875
Short name T526
Test name
Test status
Simulation time 103190773 ps
CPU time 1.16 seconds
Started Jun 11 02:22:58 PM PDT 24
Finished Jun 11 02:23:00 PM PDT 24
Peak memory 217568 kb
Host smart-dccf7eb4-c543-4eac-9496-991b86fc1737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348585875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2348585875
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2095310012
Short name T320
Test name
Test status
Simulation time 42203468 ps
CPU time 1.18 seconds
Started Jun 11 02:22:59 PM PDT 24
Finished Jun 11 02:23:01 PM PDT 24
Peak memory 219396 kb
Host smart-6f01161f-e12f-4a39-9557-7c3df54d19dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095310012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2095310012
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1753715493
Short name T594
Test name
Test status
Simulation time 100637494 ps
CPU time 1.25 seconds
Started Jun 11 02:18:28 PM PDT 24
Finished Jun 11 02:18:30 PM PDT 24
Peak memory 215880 kb
Host smart-7538de1e-61fd-4385-8ec0-e17397b0f780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753715493 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1753715493
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.4137216837
Short name T343
Test name
Test status
Simulation time 28988414 ps
CPU time 0.85 seconds
Started Jun 11 02:18:34 PM PDT 24
Finished Jun 11 02:18:36 PM PDT 24
Peak memory 215252 kb
Host smart-e1f1f7b4-e838-421c-a98e-ce01fb1d9403
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137216837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.4137216837
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1254759174
Short name T146
Test name
Test status
Simulation time 105929334 ps
CPU time 1.05 seconds
Started Jun 11 02:18:26 PM PDT 24
Finished Jun 11 02:18:28 PM PDT 24
Peak memory 216968 kb
Host smart-0eb088a7-fac8-4ec3-a5fe-c83ff2473e5c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254759174 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1254759174
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2580653177
Short name T56
Test name
Test status
Simulation time 65833029 ps
CPU time 1.29 seconds
Started Jun 11 02:18:27 PM PDT 24
Finished Jun 11 02:18:29 PM PDT 24
Peak memory 232388 kb
Host smart-ed6c5815-1942-4bff-aa5a-d2f80a2bf3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580653177 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2580653177
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.827214131
Short name T593
Test name
Test status
Simulation time 205687542 ps
CPU time 2.81 seconds
Started Jun 11 02:18:29 PM PDT 24
Finished Jun 11 02:18:32 PM PDT 24
Peak memory 219876 kb
Host smart-d50c78c7-eaf8-4b90-9449-99799f910daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827214131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.827214131
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.946636756
Short name T34
Test name
Test status
Simulation time 22135957 ps
CPU time 1.05 seconds
Started Jun 11 02:18:28 PM PDT 24
Finished Jun 11 02:18:30 PM PDT 24
Peak memory 216120 kb
Host smart-6befb37f-7c3a-4f09-8fd6-f38faea419b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946636756 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.946636756
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.117065988
Short name T782
Test name
Test status
Simulation time 34481246 ps
CPU time 0.93 seconds
Started Jun 11 02:18:27 PM PDT 24
Finished Jun 11 02:18:30 PM PDT 24
Peak memory 207336 kb
Host smart-e447bd7d-e78c-4e69-b1e0-e1c13ab20dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117065988 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.117065988
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.879476142
Short name T14
Test name
Test status
Simulation time 770120723 ps
CPU time 11.11 seconds
Started Jun 11 02:18:33 PM PDT 24
Finished Jun 11 02:18:46 PM PDT 24
Peak memory 236732 kb
Host smart-0c105748-952b-4cf9-829f-12df498929ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879476142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.879476142
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2925517691
Short name T761
Test name
Test status
Simulation time 25159156 ps
CPU time 0.97 seconds
Started Jun 11 02:18:21 PM PDT 24
Finished Jun 11 02:18:23 PM PDT 24
Peak memory 215612 kb
Host smart-e6aab4ac-dc0c-4329-b6f7-6cdb4ab1ef2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925517691 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2925517691
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2476537605
Short name T729
Test name
Test status
Simulation time 77341562 ps
CPU time 1.15 seconds
Started Jun 11 02:18:27 PM PDT 24
Finished Jun 11 02:18:29 PM PDT 24
Peak memory 215440 kb
Host smart-0a32c4b3-ac25-433d-8b8c-19633d4b1bfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476537605 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2476537605
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_alert.361214756
Short name T487
Test name
Test status
Simulation time 54625545 ps
CPU time 1.28 seconds
Started Jun 11 02:20:03 PM PDT 24
Finished Jun 11 02:20:06 PM PDT 24
Peak memory 219976 kb
Host smart-d8fa9533-41b7-4e2b-b7c6-cca2c5ef9898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361214756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.361214756
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3497050098
Short name T974
Test name
Test status
Simulation time 45398156 ps
CPU time 0.9 seconds
Started Jun 11 02:20:04 PM PDT 24
Finished Jun 11 02:20:08 PM PDT 24
Peak memory 215564 kb
Host smart-63e1c3e9-25e0-4119-9d46-f1f4a7b4464e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497050098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3497050098
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1446003001
Short name T219
Test name
Test status
Simulation time 12678513 ps
CPU time 0.91 seconds
Started Jun 11 02:20:01 PM PDT 24
Finished Jun 11 02:20:04 PM PDT 24
Peak memory 216680 kb
Host smart-c388017a-a35a-4f53-a0de-b2c768cc1c27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446003001 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1446003001
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2495830392
Short name T161
Test name
Test status
Simulation time 149729561 ps
CPU time 1.38 seconds
Started Jun 11 02:20:04 PM PDT 24
Finished Jun 11 02:20:08 PM PDT 24
Peak memory 217080 kb
Host smart-340bc88f-6f7d-4d01-83fb-8137130e8587
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495830392 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2495830392
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1423715006
Short name T152
Test name
Test status
Simulation time 52740643 ps
CPU time 1.16 seconds
Started Jun 11 02:20:05 PM PDT 24
Finished Jun 11 02:20:09 PM PDT 24
Peak memory 230120 kb
Host smart-478bf814-9561-4e54-80be-46bec3d5c4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423715006 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1423715006
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3593472006
Short name T882
Test name
Test status
Simulation time 57832970 ps
CPU time 1.22 seconds
Started Jun 11 02:20:02 PM PDT 24
Finished Jun 11 02:20:05 PM PDT 24
Peak memory 217440 kb
Host smart-6c6b9e24-77d6-46ac-b3b7-e5560ac9c267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593472006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3593472006
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2136900411
Short name T12
Test name
Test status
Simulation time 26877984 ps
CPU time 1.24 seconds
Started Jun 11 02:20:05 PM PDT 24
Finished Jun 11 02:20:09 PM PDT 24
Peak memory 224368 kb
Host smart-33b3ea38-da30-43d5-b0d1-d74be3c4ca4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136900411 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2136900411
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1907105376
Short name T874
Test name
Test status
Simulation time 17188618 ps
CPU time 0.98 seconds
Started Jun 11 02:20:02 PM PDT 24
Finished Jun 11 02:20:06 PM PDT 24
Peak memory 215624 kb
Host smart-d6082468-7ef3-421f-a377-50283cde731d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907105376 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1907105376
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3315000778
Short name T305
Test name
Test status
Simulation time 180277796 ps
CPU time 2.3 seconds
Started Jun 11 02:20:02 PM PDT 24
Finished Jun 11 02:20:06 PM PDT 24
Peak memory 215628 kb
Host smart-bfdcc1a0-ce5e-4f24-91d9-2e738c3c4db6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315000778 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3315000778
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.927106567
Short name T398
Test name
Test status
Simulation time 145551691404 ps
CPU time 1699.85 seconds
Started Jun 11 02:20:03 PM PDT 24
Finished Jun 11 02:48:25 PM PDT 24
Peak memory 225816 kb
Host smart-9551800c-535a-411a-94a1-0def92ca4812
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927106567 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.927106567
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2338411579
Short name T511
Test name
Test status
Simulation time 67156400 ps
CPU time 1.09 seconds
Started Jun 11 02:20:03 PM PDT 24
Finished Jun 11 02:20:07 PM PDT 24
Peak memory 220932 kb
Host smart-eaa51809-8101-4a2d-9cf1-a4810bfac66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338411579 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2338411579
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.4088417394
Short name T703
Test name
Test status
Simulation time 25718675 ps
CPU time 0.98 seconds
Started Jun 11 02:20:06 PM PDT 24
Finished Jun 11 02:20:10 PM PDT 24
Peak memory 207068 kb
Host smart-b4792226-5e53-4ef9-8bb1-a539010981d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088417394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.4088417394
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2939276694
Short name T716
Test name
Test status
Simulation time 12552712 ps
CPU time 0.87 seconds
Started Jun 11 02:20:06 PM PDT 24
Finished Jun 11 02:20:10 PM PDT 24
Peak memory 215588 kb
Host smart-5dd0d134-a6f7-41ce-8f66-7d5ce9994877
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939276694 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2939276694
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1383236822
Short name T547
Test name
Test status
Simulation time 24054587 ps
CPU time 1.06 seconds
Started Jun 11 02:20:06 PM PDT 24
Finished Jun 11 02:20:10 PM PDT 24
Peak memory 217024 kb
Host smart-9b156968-1a2a-4b02-89ac-c3e806510bc9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383236822 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1383236822
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_genbits.2646760278
Short name T377
Test name
Test status
Simulation time 172749314 ps
CPU time 2.06 seconds
Started Jun 11 02:20:03 PM PDT 24
Finished Jun 11 02:20:08 PM PDT 24
Peak memory 217828 kb
Host smart-83144cbb-3c19-477e-937e-a26274b53566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646760278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2646760278
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.44512014
Short name T57
Test name
Test status
Simulation time 34109945 ps
CPU time 1.08 seconds
Started Jun 11 02:20:04 PM PDT 24
Finished Jun 11 02:20:07 PM PDT 24
Peak memory 224404 kb
Host smart-a5bfbbe4-b232-4b32-851a-27e7e7e5d522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44512014 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.44512014
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1133966512
Short name T354
Test name
Test status
Simulation time 26914634 ps
CPU time 0.98 seconds
Started Jun 11 02:20:04 PM PDT 24
Finished Jun 11 02:20:08 PM PDT 24
Peak memory 215580 kb
Host smart-9aa25dee-939b-415c-aa7f-3d70b76c3b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133966512 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1133966512
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.557581129
Short name T414
Test name
Test status
Simulation time 1087610527 ps
CPU time 5.65 seconds
Started Jun 11 02:20:03 PM PDT 24
Finished Jun 11 02:20:12 PM PDT 24
Peak memory 217488 kb
Host smart-48fe7f22-ee87-44f8-9a2b-e63b4ed5056e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557581129 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.557581129
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.897119303
Short name T366
Test name
Test status
Simulation time 141645881412 ps
CPU time 1169.29 seconds
Started Jun 11 02:20:05 PM PDT 24
Finished Jun 11 02:39:37 PM PDT 24
Peak memory 225144 kb
Host smart-4fca523a-8855-4215-82fe-81a0a3f73d39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897119303 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.897119303
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert_test.3380306803
Short name T878
Test name
Test status
Simulation time 63658804 ps
CPU time 0.92 seconds
Started Jun 11 02:20:06 PM PDT 24
Finished Jun 11 02:20:10 PM PDT 24
Peak memory 215564 kb
Host smart-866c9aae-740b-4c09-992c-43236362de64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380306803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3380306803
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2496851494
Short name T206
Test name
Test status
Simulation time 34027887 ps
CPU time 0.86 seconds
Started Jun 11 02:20:04 PM PDT 24
Finished Jun 11 02:20:08 PM PDT 24
Peak memory 216648 kb
Host smart-adcdb8d8-a0fa-459f-9f1c-7dfb0f452217
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496851494 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2496851494
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.4293485445
Short name T781
Test name
Test status
Simulation time 141960205 ps
CPU time 1.16 seconds
Started Jun 11 02:20:05 PM PDT 24
Finished Jun 11 02:20:09 PM PDT 24
Peak memory 217140 kb
Host smart-fd32159b-18da-49c9-ad0d-0cc2c334d3bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293485445 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.4293485445
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3472359153
Short name T192
Test name
Test status
Simulation time 32453963 ps
CPU time 0.89 seconds
Started Jun 11 02:20:07 PM PDT 24
Finished Jun 11 02:20:10 PM PDT 24
Peak memory 218432 kb
Host smart-6ea8961f-6538-473f-9b4b-1f84d91fb180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472359153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3472359153
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3038713356
Short name T987
Test name
Test status
Simulation time 35714498 ps
CPU time 1.6 seconds
Started Jun 11 02:20:07 PM PDT 24
Finished Jun 11 02:20:11 PM PDT 24
Peak memory 220396 kb
Host smart-d4ebdadb-b9fc-4ae7-b9c6-c15d7cbac039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038713356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3038713356
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2700038042
Short name T33
Test name
Test status
Simulation time 51233849 ps
CPU time 0.86 seconds
Started Jun 11 02:20:05 PM PDT 24
Finished Jun 11 02:20:09 PM PDT 24
Peak memory 215972 kb
Host smart-52e143b5-8b11-4629-8141-a7eb952eb729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700038042 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2700038042
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2726961636
Short name T904
Test name
Test status
Simulation time 35281001 ps
CPU time 0.86 seconds
Started Jun 11 02:20:04 PM PDT 24
Finished Jun 11 02:20:07 PM PDT 24
Peak memory 215400 kb
Host smart-2366b0e1-7913-4c46-8e05-06f23a2196f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726961636 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2726961636
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.78683763
Short name T347
Test name
Test status
Simulation time 111238428 ps
CPU time 1.2 seconds
Started Jun 11 02:20:05 PM PDT 24
Finished Jun 11 02:20:08 PM PDT 24
Peak memory 215520 kb
Host smart-129a66f6-b01a-44d1-8e1d-8bc95719dca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78683763 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.78683763
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.165668838
Short name T383
Test name
Test status
Simulation time 65148598871 ps
CPU time 323.07 seconds
Started Jun 11 02:20:08 PM PDT 24
Finished Jun 11 02:25:33 PM PDT 24
Peak memory 217980 kb
Host smart-65a1d255-9642-4a9b-8d38-a08afc6155d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165668838 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.165668838
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2610994179
Short name T63
Test name
Test status
Simulation time 72980154 ps
CPU time 1.18 seconds
Started Jun 11 02:20:12 PM PDT 24
Finished Jun 11 02:20:14 PM PDT 24
Peak memory 218780 kb
Host smart-dbda2c24-d0a7-4f26-8c08-110d666e9f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610994179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2610994179
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3586008565
Short name T951
Test name
Test status
Simulation time 17088997 ps
CPU time 0.91 seconds
Started Jun 11 02:20:15 PM PDT 24
Finished Jun 11 02:20:17 PM PDT 24
Peak memory 207136 kb
Host smart-99c13d7a-cb30-4e19-9702-9d4101799b7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586008565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3586008565
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.744869207
Short name T581
Test name
Test status
Simulation time 13399006 ps
CPU time 0.94 seconds
Started Jun 11 02:20:15 PM PDT 24
Finished Jun 11 02:20:17 PM PDT 24
Peak memory 216428 kb
Host smart-4add83b9-cc03-4b6e-a87f-94164ff37f03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744869207 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.744869207
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3158000480
Short name T409
Test name
Test status
Simulation time 78901837 ps
CPU time 1.13 seconds
Started Jun 11 02:20:16 PM PDT 24
Finished Jun 11 02:20:19 PM PDT 24
Peak memory 217024 kb
Host smart-49a7934e-2eb8-4d82-97f1-9d460d664bad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158000480 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3158000480
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.4122238158
Short name T698
Test name
Test status
Simulation time 20165861 ps
CPU time 1.08 seconds
Started Jun 11 02:20:14 PM PDT 24
Finished Jun 11 02:20:16 PM PDT 24
Peak memory 218824 kb
Host smart-81392f94-f51b-439b-b0b9-402e4b444470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122238158 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.4122238158
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.4147126454
Short name T341
Test name
Test status
Simulation time 26815362 ps
CPU time 1.21 seconds
Started Jun 11 02:20:06 PM PDT 24
Finished Jun 11 02:20:10 PM PDT 24
Peak memory 220288 kb
Host smart-3541c3b9-9a81-436e-ad28-b6b0894ad9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147126454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.4147126454
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.269536826
Short name T504
Test name
Test status
Simulation time 25820990 ps
CPU time 0.98 seconds
Started Jun 11 02:20:15 PM PDT 24
Finished Jun 11 02:20:18 PM PDT 24
Peak memory 215696 kb
Host smart-e52b741e-6c9e-4108-9bd0-2f0e4e8a93eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269536826 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.269536826
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.762393620
Short name T380
Test name
Test status
Simulation time 24244739 ps
CPU time 0.95 seconds
Started Jun 11 02:20:06 PM PDT 24
Finished Jun 11 02:20:10 PM PDT 24
Peak memory 215588 kb
Host smart-4179d1d5-fcc9-401d-9dbf-7252db839dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762393620 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.762393620
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2351967143
Short name T108
Test name
Test status
Simulation time 891486441 ps
CPU time 4.94 seconds
Started Jun 11 02:20:05 PM PDT 24
Finished Jun 11 02:20:13 PM PDT 24
Peak memory 217424 kb
Host smart-91efa822-6c0e-4932-9ac1-86b46145dc11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351967143 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2351967143
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1757192700
Short name T234
Test name
Test status
Simulation time 60362352983 ps
CPU time 385.06 seconds
Started Jun 11 02:20:06 PM PDT 24
Finished Jun 11 02:26:34 PM PDT 24
Peak memory 220368 kb
Host smart-6efa4bda-172c-432b-8055-a2a2dad6d70f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757192700 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1757192700
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1623974706
Short name T416
Test name
Test status
Simulation time 27917500 ps
CPU time 1.24 seconds
Started Jun 11 02:20:13 PM PDT 24
Finished Jun 11 02:20:16 PM PDT 24
Peak memory 219792 kb
Host smart-28e1558b-957a-472b-abd5-995106ff66f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623974706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1623974706
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2883510879
Short name T969
Test name
Test status
Simulation time 195686425 ps
CPU time 0.87 seconds
Started Jun 11 02:20:14 PM PDT 24
Finished Jun 11 02:20:16 PM PDT 24
Peak memory 207036 kb
Host smart-a063ee0c-e607-4403-97ab-e1b3def55b78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883510879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2883510879
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.4161970903
Short name T741
Test name
Test status
Simulation time 14153121 ps
CPU time 0.94 seconds
Started Jun 11 02:20:15 PM PDT 24
Finished Jun 11 02:20:17 PM PDT 24
Peak memory 216636 kb
Host smart-67dd3633-658a-4628-9e3a-6502f4c791d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161970903 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.4161970903
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2705276924
Short name T121
Test name
Test status
Simulation time 82742532 ps
CPU time 1.4 seconds
Started Jun 11 02:20:13 PM PDT 24
Finished Jun 11 02:20:15 PM PDT 24
Peak memory 219484 kb
Host smart-4503f557-e65f-45f5-a233-7d77d3baffa9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705276924 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2705276924
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.684190661
Short name T222
Test name
Test status
Simulation time 28990310 ps
CPU time 1.19 seconds
Started Jun 11 02:20:14 PM PDT 24
Finished Jun 11 02:20:16 PM PDT 24
Peak memory 219648 kb
Host smart-0461a3fc-8671-4eb6-869d-cda8e414ee74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684190661 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.684190661
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_intr.913844498
Short name T993
Test name
Test status
Simulation time 19742865 ps
CPU time 1.13 seconds
Started Jun 11 02:20:13 PM PDT 24
Finished Jun 11 02:20:15 PM PDT 24
Peak memory 216132 kb
Host smart-52cf17e8-5af1-47cf-9d1a-c90734a47af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913844498 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.913844498
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2830047060
Short name T534
Test name
Test status
Simulation time 27212055 ps
CPU time 0.96 seconds
Started Jun 11 02:20:14 PM PDT 24
Finished Jun 11 02:20:17 PM PDT 24
Peak memory 215600 kb
Host smart-0105afaf-fbaa-44b9-a9ee-bd590e4674a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830047060 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2830047060
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2913743013
Short name T686
Test name
Test status
Simulation time 136071253 ps
CPU time 3.02 seconds
Started Jun 11 02:20:12 PM PDT 24
Finished Jun 11 02:20:16 PM PDT 24
Peak memory 215596 kb
Host smart-812e61a7-faa8-4aad-a551-6de90a13b4cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913743013 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2913743013
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2753465426
Short name T239
Test name
Test status
Simulation time 103191187360 ps
CPU time 1162.17 seconds
Started Jun 11 02:20:15 PM PDT 24
Finished Jun 11 02:39:38 PM PDT 24
Peak memory 223380 kb
Host smart-e38c8f6d-1fc7-4923-baf5-28bd05b08325
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753465426 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2753465426
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3832554263
Short name T911
Test name
Test status
Simulation time 29402614 ps
CPU time 1.31 seconds
Started Jun 11 02:20:13 PM PDT 24
Finished Jun 11 02:20:16 PM PDT 24
Peak memory 219876 kb
Host smart-df70929d-3cbb-4249-b56a-b104c2aa898a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832554263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3832554263
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2082662002
Short name T448
Test name
Test status
Simulation time 14758414 ps
CPU time 0.91 seconds
Started Jun 11 02:20:15 PM PDT 24
Finished Jun 11 02:20:18 PM PDT 24
Peak memory 207060 kb
Host smart-c218c8e3-4551-4851-ac51-f2f5d116bfc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082662002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2082662002
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.685595647
Short name T691
Test name
Test status
Simulation time 23299988 ps
CPU time 1.07 seconds
Started Jun 11 02:20:13 PM PDT 24
Finished Jun 11 02:20:15 PM PDT 24
Peak memory 217000 kb
Host smart-379016d0-633c-4a7e-9023-062f1ae366b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685595647 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.685595647
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2516936383
Short name T53
Test name
Test status
Simulation time 20679157 ps
CPU time 1.17 seconds
Started Jun 11 02:20:14 PM PDT 24
Finished Jun 11 02:20:17 PM PDT 24
Peak memory 224196 kb
Host smart-b4f2cff9-0532-4305-ab94-dc23a4b846b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516936383 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2516936383
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3890743202
Short name T490
Test name
Test status
Simulation time 42278872 ps
CPU time 1.63 seconds
Started Jun 11 02:20:17 PM PDT 24
Finished Jun 11 02:20:20 PM PDT 24
Peak memory 218752 kb
Host smart-621a3155-f1e3-4a03-8a23-1b74fa9aa5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890743202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3890743202
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.4064130300
Short name T408
Test name
Test status
Simulation time 27756768 ps
CPU time 1.13 seconds
Started Jun 11 02:20:13 PM PDT 24
Finished Jun 11 02:20:15 PM PDT 24
Peak memory 224360 kb
Host smart-c8305840-2417-440f-ba06-329d8c49a3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064130300 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.4064130300
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.483545808
Short name T616
Test name
Test status
Simulation time 15293674 ps
CPU time 0.98 seconds
Started Jun 11 02:20:12 PM PDT 24
Finished Jun 11 02:20:13 PM PDT 24
Peak memory 215464 kb
Host smart-019bd113-e366-4642-af80-db43f0cf6edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483545808 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.483545808
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2724913931
Short name T611
Test name
Test status
Simulation time 62633267 ps
CPU time 0.95 seconds
Started Jun 11 02:20:13 PM PDT 24
Finished Jun 11 02:20:15 PM PDT 24
Peak memory 207052 kb
Host smart-a043d97c-6dec-4674-bade-953300de8e55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724913931 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2724913931
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.777229900
Short name T557
Test name
Test status
Simulation time 43477578240 ps
CPU time 884.88 seconds
Started Jun 11 02:20:14 PM PDT 24
Finished Jun 11 02:35:01 PM PDT 24
Peak memory 223964 kb
Host smart-067197a5-d7ec-4970-8c3d-b5eaa61f2093
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777229900 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.777229900
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2142659689
Short name T808
Test name
Test status
Simulation time 57908483 ps
CPU time 1.35 seconds
Started Jun 11 02:20:14 PM PDT 24
Finished Jun 11 02:20:17 PM PDT 24
Peak memory 215864 kb
Host smart-f631d777-7d47-4e70-a077-4b1ae2020647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142659689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2142659689
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.435112634
Short name T639
Test name
Test status
Simulation time 14924985 ps
CPU time 0.95 seconds
Started Jun 11 02:20:16 PM PDT 24
Finished Jun 11 02:20:18 PM PDT 24
Peak memory 215552 kb
Host smart-78971bbd-40c3-4a0c-8e64-193d156a828a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435112634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.435112634
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2377129620
Short name T167
Test name
Test status
Simulation time 35993194 ps
CPU time 0.89 seconds
Started Jun 11 02:20:12 PM PDT 24
Finished Jun 11 02:20:14 PM PDT 24
Peak memory 215668 kb
Host smart-3e703192-f739-4a06-937d-37271454e33b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377129620 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2377129620
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.4200633077
Short name T924
Test name
Test status
Simulation time 64640972 ps
CPU time 1.35 seconds
Started Jun 11 02:20:16 PM PDT 24
Finished Jun 11 02:20:19 PM PDT 24
Peak memory 218588 kb
Host smart-dde2aaa9-a6ef-4616-aece-a0e5022a0c88
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200633077 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.4200633077
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3223234010
Short name T158
Test name
Test status
Simulation time 48645397 ps
CPU time 0.98 seconds
Started Jun 11 02:20:15 PM PDT 24
Finished Jun 11 02:20:17 PM PDT 24
Peak memory 219900 kb
Host smart-5834a605-fdbf-4e20-a179-ff24f83eba3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223234010 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3223234010
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.764540736
Short name T41
Test name
Test status
Simulation time 73191819 ps
CPU time 1.21 seconds
Started Jun 11 02:20:16 PM PDT 24
Finished Jun 11 02:20:19 PM PDT 24
Peak memory 217708 kb
Host smart-def303a0-6ea6-4f63-a5da-104b59d0cf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764540736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.764540736
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1733302000
Short name T523
Test name
Test status
Simulation time 102240676 ps
CPU time 1.02 seconds
Started Jun 11 02:20:14 PM PDT 24
Finished Jun 11 02:20:17 PM PDT 24
Peak memory 224168 kb
Host smart-a8d4bc04-aa12-4578-bd74-e38705d316e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733302000 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1733302000
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.589042415
Short name T706
Test name
Test status
Simulation time 61890940 ps
CPU time 0.94 seconds
Started Jun 11 02:20:15 PM PDT 24
Finished Jun 11 02:20:17 PM PDT 24
Peak memory 215584 kb
Host smart-ac19238d-3faf-40e8-82cb-5ea490816448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589042415 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.589042415
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3287157039
Short name T412
Test name
Test status
Simulation time 358163893 ps
CPU time 4.63 seconds
Started Jun 11 02:20:13 PM PDT 24
Finished Jun 11 02:20:18 PM PDT 24
Peak memory 217536 kb
Host smart-a672eff4-e195-4fc9-9618-79b63d0fa569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287157039 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3287157039
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.358315316
Short name T736
Test name
Test status
Simulation time 548690602003 ps
CPU time 1245.98 seconds
Started Jun 11 02:20:15 PM PDT 24
Finished Jun 11 02:41:03 PM PDT 24
Peak memory 224620 kb
Host smart-a4ce72e2-8ae8-43c0-9352-a8c4bb4370f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358315316 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.358315316
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2884659130
Short name T657
Test name
Test status
Simulation time 23052256 ps
CPU time 1.16 seconds
Started Jun 11 02:20:14 PM PDT 24
Finished Jun 11 02:20:16 PM PDT 24
Peak memory 218668 kb
Host smart-1e35a1e2-a0af-4576-ac0d-b617c3b3a2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884659130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2884659130
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1292831474
Short name T816
Test name
Test status
Simulation time 120167993 ps
CPU time 0.98 seconds
Started Jun 11 02:20:26 PM PDT 24
Finished Jun 11 02:20:27 PM PDT 24
Peak memory 207160 kb
Host smart-60151d54-9d6a-4e40-a986-bd4e21743042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292831474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1292831474
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2467293720
Short name T187
Test name
Test status
Simulation time 17159220 ps
CPU time 0.89 seconds
Started Jun 11 02:20:22 PM PDT 24
Finished Jun 11 02:20:25 PM PDT 24
Peak memory 216484 kb
Host smart-ba8699da-4775-4ed2-9ba3-8f050b978622
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467293720 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2467293720
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2465976952
Short name T147
Test name
Test status
Simulation time 44187377 ps
CPU time 1.32 seconds
Started Jun 11 02:20:22 PM PDT 24
Finished Jun 11 02:20:25 PM PDT 24
Peak memory 218552 kb
Host smart-7202b0ac-ab22-41a5-bf5b-14704a404911
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465976952 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2465976952
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3170891764
Short name T806
Test name
Test status
Simulation time 32334884 ps
CPU time 0.95 seconds
Started Jun 11 02:20:28 PM PDT 24
Finished Jun 11 02:20:30 PM PDT 24
Peak memory 218772 kb
Host smart-ac91e852-0d7d-4a81-b6c6-73ba0225cd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170891764 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3170891764
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3406493363
Short name T393
Test name
Test status
Simulation time 42762851 ps
CPU time 1.72 seconds
Started Jun 11 02:20:17 PM PDT 24
Finished Jun 11 02:20:20 PM PDT 24
Peak memory 219036 kb
Host smart-e00bfd4b-75b9-4b87-8d8c-6d97e8420804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406493363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3406493363
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_smoke.1533871199
Short name T641
Test name
Test status
Simulation time 39266165 ps
CPU time 0.9 seconds
Started Jun 11 02:20:16 PM PDT 24
Finished Jun 11 02:20:19 PM PDT 24
Peak memory 215572 kb
Host smart-ea41deb4-a50e-457a-87bd-444ff0c26914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533871199 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1533871199
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1539770984
Short name T571
Test name
Test status
Simulation time 24924425 ps
CPU time 1.08 seconds
Started Jun 11 02:20:13 PM PDT 24
Finished Jun 11 02:20:15 PM PDT 24
Peak memory 206748 kb
Host smart-26d12181-90c6-40ca-b94a-9f44cf7142a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539770984 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1539770984
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1798932466
Short name T453
Test name
Test status
Simulation time 158021572846 ps
CPU time 3611.77 seconds
Started Jun 11 02:20:14 PM PDT 24
Finished Jun 11 03:20:28 PM PDT 24
Peak memory 234460 kb
Host smart-6cb302b0-7552-429d-9b14-c05bb8906b58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798932466 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1798932466
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert_test.3374807070
Short name T497
Test name
Test status
Simulation time 13673330 ps
CPU time 0.92 seconds
Started Jun 11 02:20:22 PM PDT 24
Finished Jun 11 02:20:24 PM PDT 24
Peak memory 207328 kb
Host smart-101121a1-44b8-4d0a-b410-4d2a224cb4a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374807070 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3374807070
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1352613860
Short name T45
Test name
Test status
Simulation time 11456580 ps
CPU time 0.88 seconds
Started Jun 11 02:20:24 PM PDT 24
Finished Jun 11 02:20:26 PM PDT 24
Peak memory 216604 kb
Host smart-dd064586-292d-4969-b958-4b21dd0a22b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352613860 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1352613860
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1339950447
Short name T213
Test name
Test status
Simulation time 71094193 ps
CPU time 1.03 seconds
Started Jun 11 02:20:24 PM PDT 24
Finished Jun 11 02:20:26 PM PDT 24
Peak memory 217100 kb
Host smart-b82b1170-fc91-450a-9ce1-5eb8fcb2284e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339950447 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1339950447
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1306884812
Short name T182
Test name
Test status
Simulation time 34403123 ps
CPU time 1 seconds
Started Jun 11 02:20:21 PM PDT 24
Finished Jun 11 02:20:23 PM PDT 24
Peak memory 224024 kb
Host smart-7e355879-0e96-44eb-8c51-c7830d1cd1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306884812 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1306884812
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1619016234
Short name T635
Test name
Test status
Simulation time 303810602 ps
CPU time 1.86 seconds
Started Jun 11 02:20:23 PM PDT 24
Finished Jun 11 02:20:26 PM PDT 24
Peak memory 219388 kb
Host smart-d5ab63c0-e08f-4d37-889d-216627b0f07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619016234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1619016234
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.4053991253
Short name T660
Test name
Test status
Simulation time 23108625 ps
CPU time 1.1 seconds
Started Jun 11 02:20:21 PM PDT 24
Finished Jun 11 02:20:23 PM PDT 24
Peak memory 215724 kb
Host smart-f38648b8-b43f-4b40-9994-ae9d7b400dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053991253 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.4053991253
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3671887100
Short name T730
Test name
Test status
Simulation time 24353242 ps
CPU time 0.97 seconds
Started Jun 11 02:20:21 PM PDT 24
Finished Jun 11 02:20:22 PM PDT 24
Peak memory 215600 kb
Host smart-08b9638a-a378-4ca9-8889-7c9b7e71af49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671887100 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3671887100
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.203349472
Short name T753
Test name
Test status
Simulation time 425380571 ps
CPU time 4.54 seconds
Started Jun 11 02:20:22 PM PDT 24
Finished Jun 11 02:20:28 PM PDT 24
Peak memory 217440 kb
Host smart-abe2748b-032f-4099-8a2a-5e16cadb0eff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203349472 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.203349472
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.378842559
Short name T965
Test name
Test status
Simulation time 13571044884 ps
CPU time 366 seconds
Started Jun 11 02:20:23 PM PDT 24
Finished Jun 11 02:26:30 PM PDT 24
Peak memory 218872 kb
Host smart-9acb0597-1b0d-4dfc-8c38-1ba2a2327b22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378842559 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.378842559
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.542189233
Short name T888
Test name
Test status
Simulation time 156909046 ps
CPU time 1.2 seconds
Started Jun 11 02:20:20 PM PDT 24
Finished Jun 11 02:20:22 PM PDT 24
Peak memory 218956 kb
Host smart-ca36dbee-f778-4de8-acac-f96319911a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542189233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.542189233
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.4125144937
Short name T3
Test name
Test status
Simulation time 47306372 ps
CPU time 0.9 seconds
Started Jun 11 02:20:21 PM PDT 24
Finished Jun 11 02:20:22 PM PDT 24
Peak memory 207112 kb
Host smart-1b7cd654-88b4-46d6-9706-5336e57c6077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125144937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.4125144937
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1427280471
Short name T946
Test name
Test status
Simulation time 42965122 ps
CPU time 0.82 seconds
Started Jun 11 02:20:22 PM PDT 24
Finished Jun 11 02:20:24 PM PDT 24
Peak memory 216388 kb
Host smart-afcccac3-89eb-4a29-b27b-8db5ffcd0274
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427280471 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1427280471
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2300051085
Short name T207
Test name
Test status
Simulation time 31023810 ps
CPU time 1.11 seconds
Started Jun 11 02:20:27 PM PDT 24
Finished Jun 11 02:20:29 PM PDT 24
Peak memory 217072 kb
Host smart-bdde1212-4eb8-43d1-8824-bf13a83dc9af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300051085 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2300051085
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.144245423
Short name T679
Test name
Test status
Simulation time 19314326 ps
CPU time 1.19 seconds
Started Jun 11 02:20:24 PM PDT 24
Finished Jun 11 02:20:27 PM PDT 24
Peak memory 224212 kb
Host smart-b8d2eb29-b181-4bf8-b202-abd847f74d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144245423 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.144245423
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2301903279
Short name T830
Test name
Test status
Simulation time 23777547 ps
CPU time 1.15 seconds
Started Jun 11 02:20:22 PM PDT 24
Finished Jun 11 02:20:25 PM PDT 24
Peak memory 217624 kb
Host smart-ce7a7e03-2b13-49d6-8a71-0dfe880bb515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301903279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2301903279
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.4257191329
Short name T857
Test name
Test status
Simulation time 36586679 ps
CPU time 0.89 seconds
Started Jun 11 02:20:28 PM PDT 24
Finished Jun 11 02:20:30 PM PDT 24
Peak memory 215808 kb
Host smart-9ea94803-7d95-4ed5-9ae9-3eec9b0fc04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257191329 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.4257191329
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.801407836
Short name T451
Test name
Test status
Simulation time 21683627 ps
CPU time 0.91 seconds
Started Jun 11 02:20:23 PM PDT 24
Finished Jun 11 02:20:25 PM PDT 24
Peak memory 215580 kb
Host smart-caaa1143-c35b-429e-be3a-0e2c800e6fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801407836 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.801407836
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.200935438
Short name T413
Test name
Test status
Simulation time 525052205 ps
CPU time 5.25 seconds
Started Jun 11 02:20:22 PM PDT 24
Finished Jun 11 02:20:29 PM PDT 24
Peak memory 217484 kb
Host smart-8e17c095-1df5-4d87-a22e-af144cbd7a70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200935438 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.200935438
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.91741204
Short name T231
Test name
Test status
Simulation time 1151378247789 ps
CPU time 1619.59 seconds
Started Jun 11 02:20:25 PM PDT 24
Finished Jun 11 02:47:25 PM PDT 24
Peak memory 223840 kb
Host smart-42b0c54d-dc84-413a-8e85-38b51f56038b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91741204 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.91741204
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.807884736
Short name T196
Test name
Test status
Simulation time 38995966 ps
CPU time 1.15 seconds
Started Jun 11 02:18:33 PM PDT 24
Finished Jun 11 02:18:35 PM PDT 24
Peak memory 220340 kb
Host smart-ac462ec2-d075-41f3-98b7-2d20aa0f2a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807884736 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.807884736
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3448433879
Short name T546
Test name
Test status
Simulation time 15073107 ps
CPU time 0.92 seconds
Started Jun 11 02:18:36 PM PDT 24
Finished Jun 11 02:18:38 PM PDT 24
Peak memory 207092 kb
Host smart-afc79f0a-29eb-45ca-9711-78aa0b97b826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448433879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3448433879
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3066470038
Short name T772
Test name
Test status
Simulation time 34308063 ps
CPU time 0.83 seconds
Started Jun 11 02:18:35 PM PDT 24
Finished Jun 11 02:18:37 PM PDT 24
Peak memory 216504 kb
Host smart-b3d8e172-7bdc-4433-bd09-f161af7bf81a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066470038 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3066470038
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2042083766
Short name T843
Test name
Test status
Simulation time 30423670 ps
CPU time 1.17 seconds
Started Jun 11 02:18:33 PM PDT 24
Finished Jun 11 02:18:36 PM PDT 24
Peak memory 217176 kb
Host smart-8093698f-a989-4fe9-b95c-292b51549085
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042083766 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2042083766
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2227108004
Short name T209
Test name
Test status
Simulation time 266925527 ps
CPU time 1.16 seconds
Started Jun 11 02:18:35 PM PDT 24
Finished Jun 11 02:18:37 PM PDT 24
Peak memory 219764 kb
Host smart-046dcd3a-fb19-4b8f-b6cf-8008addc64b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227108004 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2227108004
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1810257115
Short name T672
Test name
Test status
Simulation time 65575613 ps
CPU time 1.13 seconds
Started Jun 11 02:18:34 PM PDT 24
Finished Jun 11 02:18:36 PM PDT 24
Peak memory 218844 kb
Host smart-6c9f5d39-d857-4abd-9252-cb4786aae97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810257115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1810257115
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3701252761
Short name T609
Test name
Test status
Simulation time 21240016 ps
CPU time 1.13 seconds
Started Jun 11 02:18:33 PM PDT 24
Finished Jun 11 02:18:36 PM PDT 24
Peak memory 215820 kb
Host smart-1bce15ab-d60f-456f-ac88-546ae1fd365d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701252761 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3701252761
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.782418113
Short name T777
Test name
Test status
Simulation time 44626097 ps
CPU time 0.89 seconds
Started Jun 11 02:18:35 PM PDT 24
Finished Jun 11 02:18:37 PM PDT 24
Peak memory 207360 kb
Host smart-cf9ea6ca-1b21-48ab-bcdc-ad752c52232d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782418113 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.782418113
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3410626253
Short name T61
Test name
Test status
Simulation time 3882440674 ps
CPU time 8.76 seconds
Started Jun 11 02:18:33 PM PDT 24
Finished Jun 11 02:18:43 PM PDT 24
Peak memory 237936 kb
Host smart-88479c98-30cd-43ca-8c8f-33c43cca0900
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410626253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3410626253
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2308184265
Short name T439
Test name
Test status
Simulation time 41252658 ps
CPU time 0.95 seconds
Started Jun 11 02:18:33 PM PDT 24
Finished Jun 11 02:18:35 PM PDT 24
Peak memory 215612 kb
Host smart-a3df02af-436c-4159-998e-855789f2daf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308184265 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2308184265
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1884546167
Short name T791
Test name
Test status
Simulation time 371565097 ps
CPU time 4.16 seconds
Started Jun 11 02:18:34 PM PDT 24
Finished Jun 11 02:18:39 PM PDT 24
Peak memory 215456 kb
Host smart-babe1aca-0029-4d78-9f60-8623a88bc38e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884546167 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1884546167
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.364014066
Short name T456
Test name
Test status
Simulation time 45659734570 ps
CPU time 529.12 seconds
Started Jun 11 02:18:32 PM PDT 24
Finished Jun 11 02:27:23 PM PDT 24
Peak memory 224076 kb
Host smart-b0cf9488-b4f3-4d8e-b1bf-4fe2d31e46eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364014066 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.364014066
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1714109232
Short name T191
Test name
Test status
Simulation time 67696949 ps
CPU time 1.11 seconds
Started Jun 11 02:20:28 PM PDT 24
Finished Jun 11 02:20:30 PM PDT 24
Peak memory 219120 kb
Host smart-50fe3337-586c-4f5a-b249-88c719b47b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714109232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1714109232
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.202509188
Short name T567
Test name
Test status
Simulation time 20110096 ps
CPU time 0.89 seconds
Started Jun 11 02:20:23 PM PDT 24
Finished Jun 11 02:20:25 PM PDT 24
Peak memory 215288 kb
Host smart-b7b5e389-4496-4a2e-8bc0-ef397d9fb1d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202509188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.202509188
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.4245857058
Short name T561
Test name
Test status
Simulation time 30657266 ps
CPU time 0.87 seconds
Started Jun 11 02:20:25 PM PDT 24
Finished Jun 11 02:20:27 PM PDT 24
Peak memory 216516 kb
Host smart-6a54411b-fbdc-4036-ac3a-c52d1f8397b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245857058 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.4245857058
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2544458066
Short name T588
Test name
Test status
Simulation time 110950092 ps
CPU time 1.11 seconds
Started Jun 11 02:20:24 PM PDT 24
Finished Jun 11 02:20:26 PM PDT 24
Peak memory 218564 kb
Host smart-e8af87fd-0946-4bc1-bac5-9c0a496ea218
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544458066 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2544458066
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.479113141
Short name T210
Test name
Test status
Simulation time 46593283 ps
CPU time 1.2 seconds
Started Jun 11 02:20:22 PM PDT 24
Finished Jun 11 02:20:24 PM PDT 24
Peak memory 225840 kb
Host smart-a68a2643-b732-4672-8d46-966f2cb6ab9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479113141 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.479113141
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.4217730945
Short name T833
Test name
Test status
Simulation time 51915031 ps
CPU time 1.61 seconds
Started Jun 11 02:20:25 PM PDT 24
Finished Jun 11 02:20:27 PM PDT 24
Peak memory 218936 kb
Host smart-e83be066-6fd2-43c9-9ef6-6bfa0b3fe2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217730945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.4217730945
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3729235447
Short name T30
Test name
Test status
Simulation time 22775869 ps
CPU time 0.98 seconds
Started Jun 11 02:20:22 PM PDT 24
Finished Jun 11 02:20:24 PM PDT 24
Peak memory 216204 kb
Host smart-6730db1d-7add-46d7-9c52-0b3b5387f82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729235447 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3729235447
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.82402160
Short name T614
Test name
Test status
Simulation time 19200333 ps
CPU time 1.04 seconds
Started Jun 11 02:20:22 PM PDT 24
Finished Jun 11 02:20:25 PM PDT 24
Peak memory 215492 kb
Host smart-71c42f44-15ad-4951-a0a6-316cd48ba8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82402160 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.82402160
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1185534638
Short name T420
Test name
Test status
Simulation time 449220637 ps
CPU time 5.01 seconds
Started Jun 11 02:20:22 PM PDT 24
Finished Jun 11 02:20:29 PM PDT 24
Peak memory 220216 kb
Host smart-06d1e9cd-7394-4b09-8b62-a8467ddd184c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185534638 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1185534638
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.49429549
Short name T369
Test name
Test status
Simulation time 39899193597 ps
CPU time 943.74 seconds
Started Jun 11 02:20:23 PM PDT 24
Finished Jun 11 02:36:08 PM PDT 24
Peak memory 219264 kb
Host smart-d9450bc1-88f7-4a5a-ba3d-945e32068958
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49429549 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.49429549
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert_test.1849487012
Short name T496
Test name
Test status
Simulation time 20585626 ps
CPU time 1.05 seconds
Started Jun 11 02:20:30 PM PDT 24
Finished Jun 11 02:20:31 PM PDT 24
Peak memory 207148 kb
Host smart-c0f6ee91-0a23-4272-8283-e7d5b69ac459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849487012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1849487012
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2914829890
Short name T920
Test name
Test status
Simulation time 55777414 ps
CPU time 0.79 seconds
Started Jun 11 02:20:37 PM PDT 24
Finished Jun 11 02:20:38 PM PDT 24
Peak memory 216120 kb
Host smart-89c3e80d-b1da-4f0d-ba46-501e7a3f4bba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914829890 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2914829890
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2485121029
Short name T613
Test name
Test status
Simulation time 46251317 ps
CPU time 1.43 seconds
Started Jun 11 02:20:37 PM PDT 24
Finished Jun 11 02:20:38 PM PDT 24
Peak memory 217060 kb
Host smart-6a43c072-8002-4e68-a57c-c08d9c27cb3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485121029 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2485121029
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3089945154
Short name T78
Test name
Test status
Simulation time 40754238 ps
CPU time 1.2 seconds
Started Jun 11 02:20:33 PM PDT 24
Finished Jun 11 02:20:35 PM PDT 24
Peak memory 215728 kb
Host smart-475d0ccf-c788-441b-a596-5c4dc9bd218c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089945154 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3089945154
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.884320621
Short name T386
Test name
Test status
Simulation time 71150519 ps
CPU time 1.23 seconds
Started Jun 11 02:20:37 PM PDT 24
Finished Jun 11 02:20:39 PM PDT 24
Peak memory 217440 kb
Host smart-5299ac2b-031a-477f-95c4-47dc322cbe85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884320621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.884320621
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1370912332
Short name T37
Test name
Test status
Simulation time 27328047 ps
CPU time 0.88 seconds
Started Jun 11 02:20:37 PM PDT 24
Finished Jun 11 02:20:38 PM PDT 24
Peak memory 215916 kb
Host smart-e4e7d19a-7443-40ec-9ea6-db96341d43c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370912332 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1370912332
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.139261922
Short name T774
Test name
Test status
Simulation time 17554421 ps
CPU time 1.04 seconds
Started Jun 11 02:20:24 PM PDT 24
Finished Jun 11 02:20:26 PM PDT 24
Peak memory 215444 kb
Host smart-225429f1-13c5-4d21-8449-535421bbe44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139261922 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.139261922
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1384612545
Short name T899
Test name
Test status
Simulation time 426481459 ps
CPU time 4.92 seconds
Started Jun 11 02:20:30 PM PDT 24
Finished Jun 11 02:20:35 PM PDT 24
Peak memory 215536 kb
Host smart-58fbdc34-4629-4ca9-a169-3b6b8063a963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384612545 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1384612545
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1531201026
Short name T559
Test name
Test status
Simulation time 109099063665 ps
CPU time 778.96 seconds
Started Jun 11 02:20:30 PM PDT 24
Finished Jun 11 02:33:30 PM PDT 24
Peak memory 222492 kb
Host smart-9758702d-a0b0-4daa-8c0f-0e8849c2baac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531201026 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1531201026
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3159249393
Short name T607
Test name
Test status
Simulation time 23864232 ps
CPU time 1.24 seconds
Started Jun 11 02:20:41 PM PDT 24
Finished Jun 11 02:20:42 PM PDT 24
Peak memory 219676 kb
Host smart-06fa3e8b-d8d0-4ac5-ad89-b0d9a49322b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159249393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3159249393
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3389323555
Short name T360
Test name
Test status
Simulation time 109301694 ps
CPU time 0.84 seconds
Started Jun 11 02:20:43 PM PDT 24
Finished Jun 11 02:20:45 PM PDT 24
Peak memory 207160 kb
Host smart-02fadc5e-fb68-4dda-9506-2f8e7307eab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389323555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3389323555
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.4033323167
Short name T705
Test name
Test status
Simulation time 86961990 ps
CPU time 0.9 seconds
Started Jun 11 02:20:42 PM PDT 24
Finished Jun 11 02:20:43 PM PDT 24
Peak memory 216696 kb
Host smart-874c4d81-36a7-4fe6-96fe-99e7941f0ad6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033323167 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.4033323167
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1449371088
Short name T598
Test name
Test status
Simulation time 57017621 ps
CPU time 1.14 seconds
Started Jun 11 02:20:43 PM PDT 24
Finished Jun 11 02:20:45 PM PDT 24
Peak memory 217100 kb
Host smart-48bba2b3-94a6-467b-bed5-ad6914ada88d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449371088 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1449371088
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1740379046
Short name T8
Test name
Test status
Simulation time 23137988 ps
CPU time 1.13 seconds
Started Jun 11 02:20:41 PM PDT 24
Finished Jun 11 02:20:43 PM PDT 24
Peak memory 224140 kb
Host smart-76b5e1a5-c297-4516-b93e-3c3b3351bdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740379046 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1740379046
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2826334003
Short name T909
Test name
Test status
Simulation time 113675769 ps
CPU time 1.26 seconds
Started Jun 11 02:20:32 PM PDT 24
Finished Jun 11 02:20:34 PM PDT 24
Peak memory 219436 kb
Host smart-50ea055e-567c-4a8f-9436-0e65619dfdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826334003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2826334003
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3074067422
Short name T569
Test name
Test status
Simulation time 33452562 ps
CPU time 0.83 seconds
Started Jun 11 02:20:29 PM PDT 24
Finished Jun 11 02:20:31 PM PDT 24
Peak memory 215900 kb
Host smart-6f2dc564-0f5b-4e0c-9c92-3f30672d8411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074067422 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3074067422
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.4039459629
Short name T612
Test name
Test status
Simulation time 64546242 ps
CPU time 0.97 seconds
Started Jun 11 02:20:29 PM PDT 24
Finished Jun 11 02:20:31 PM PDT 24
Peak memory 215576 kb
Host smart-62466901-90c7-44ba-8836-eac619ad8525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039459629 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.4039459629
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.4088414499
Short name T19
Test name
Test status
Simulation time 33355518 ps
CPU time 1.36 seconds
Started Jun 11 02:20:30 PM PDT 24
Finished Jun 11 02:20:32 PM PDT 24
Peak memory 215556 kb
Host smart-fc5414ff-3aa6-4c6f-a6fe-5c4bbcaefab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088414499 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.4088414499
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2382707288
Short name T773
Test name
Test status
Simulation time 281802391294 ps
CPU time 1558.79 seconds
Started Jun 11 02:20:37 PM PDT 24
Finished Jun 11 02:46:37 PM PDT 24
Peak memory 227660 kb
Host smart-00a99ba0-eed8-4280-9f90-1efcdffb886f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382707288 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2382707288
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.3793647447
Short name T895
Test name
Test status
Simulation time 39467753 ps
CPU time 1.11 seconds
Started Jun 11 02:20:42 PM PDT 24
Finished Jun 11 02:20:44 PM PDT 24
Peak memory 219020 kb
Host smart-42f657af-6255-4c65-88a8-b597f9a9d124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793647447 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3793647447
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2149236278
Short name T59
Test name
Test status
Simulation time 28932997 ps
CPU time 0.93 seconds
Started Jun 11 02:20:42 PM PDT 24
Finished Jun 11 02:20:44 PM PDT 24
Peak memory 215240 kb
Host smart-327585d5-a87e-4320-b017-4213a9e7d8cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149236278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2149236278
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.769464878
Short name T407
Test name
Test status
Simulation time 18290658 ps
CPU time 0.85 seconds
Started Jun 11 02:20:41 PM PDT 24
Finished Jun 11 02:20:43 PM PDT 24
Peak memory 216652 kb
Host smart-cdf8f513-69f6-4702-accc-de5b692ac13b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769464878 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.769464878
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1937044871
Short name T844
Test name
Test status
Simulation time 21890710 ps
CPU time 1.04 seconds
Started Jun 11 02:20:42 PM PDT 24
Finished Jun 11 02:20:43 PM PDT 24
Peak memory 217084 kb
Host smart-a578f223-cfbf-4ce7-b53f-befe205d336a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937044871 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1937044871
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1277551424
Short name T570
Test name
Test status
Simulation time 38804031 ps
CPU time 1.15 seconds
Started Jun 11 02:20:41 PM PDT 24
Finished Jun 11 02:20:42 PM PDT 24
Peak memory 218660 kb
Host smart-c840f0c3-cbe5-46ae-86e3-2fadc8ed3307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277551424 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1277551424
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3936002393
Short name T441
Test name
Test status
Simulation time 104396576 ps
CPU time 1.41 seconds
Started Jun 11 02:20:42 PM PDT 24
Finished Jun 11 02:20:45 PM PDT 24
Peak memory 217692 kb
Host smart-31a14ed2-b820-434f-8165-56f4f6ee5203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936002393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3936002393
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2360762952
Short name T603
Test name
Test status
Simulation time 22581341 ps
CPU time 1.11 seconds
Started Jun 11 02:20:43 PM PDT 24
Finished Jun 11 02:20:45 PM PDT 24
Peak memory 215728 kb
Host smart-74cbf0eb-6e3c-475a-806e-dfb45a7d7822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360762952 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2360762952
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.4172182421
Short name T379
Test name
Test status
Simulation time 43282020 ps
CPU time 0.94 seconds
Started Jun 11 02:20:42 PM PDT 24
Finished Jun 11 02:20:45 PM PDT 24
Peak memory 215560 kb
Host smart-5f03fe2c-4887-4b41-a9ae-0081a8556237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172182421 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.4172182421
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1794200024
Short name T872
Test name
Test status
Simulation time 738023978 ps
CPU time 4.19 seconds
Started Jun 11 02:20:43 PM PDT 24
Finished Jun 11 02:20:48 PM PDT 24
Peak memory 217788 kb
Host smart-a2d6aab3-be55-4814-9fea-3a8f97e77c34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794200024 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1794200024
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3617632343
Short name T240
Test name
Test status
Simulation time 83423866789 ps
CPU time 926.07 seconds
Started Jun 11 02:20:43 PM PDT 24
Finished Jun 11 02:36:10 PM PDT 24
Peak memory 222172 kb
Host smart-774bde98-fe94-4081-9a32-4ce1b125c216
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617632343 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3617632343
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.275721111
Short name T735
Test name
Test status
Simulation time 43642023 ps
CPU time 1.2 seconds
Started Jun 11 02:20:54 PM PDT 24
Finished Jun 11 02:20:56 PM PDT 24
Peak memory 218804 kb
Host smart-04026e1c-9e24-48bd-a417-01a2350bd446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275721111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.275721111
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1858310750
Short name T363
Test name
Test status
Simulation time 43265005 ps
CPU time 1.02 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:21:00 PM PDT 24
Peak memory 215572 kb
Host smart-b2205faf-54b0-4476-bcff-a65b968eb4df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858310750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1858310750
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.942014790
Short name T551
Test name
Test status
Simulation time 34744551 ps
CPU time 0.85 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:20:58 PM PDT 24
Peak memory 216512 kb
Host smart-0a7c42c7-b4b2-45b7-bcd4-ddd095f7e6b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942014790 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.942014790
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3653086000
Short name T984
Test name
Test status
Simulation time 26817556 ps
CPU time 1.1 seconds
Started Jun 11 02:20:54 PM PDT 24
Finished Jun 11 02:20:56 PM PDT 24
Peak memory 218504 kb
Host smart-3bf215ef-760d-43e2-91ea-f5ca93b1de4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653086000 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3653086000
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3647893335
Short name T51
Test name
Test status
Simulation time 75435763 ps
CPU time 1.19 seconds
Started Jun 11 02:20:57 PM PDT 24
Finished Jun 11 02:21:00 PM PDT 24
Peak memory 225996 kb
Host smart-e1137f8d-32a8-4c4a-883c-155c8ead0ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647893335 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3647893335
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2409373240
Short name T477
Test name
Test status
Simulation time 39350107 ps
CPU time 1.53 seconds
Started Jun 11 02:20:42 PM PDT 24
Finished Jun 11 02:20:45 PM PDT 24
Peak memory 219812 kb
Host smart-75833140-c280-4070-86fa-4d5f0b3e7fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409373240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2409373240
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2443210242
Short name T621
Test name
Test status
Simulation time 28087204 ps
CPU time 1.09 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:20:57 PM PDT 24
Peak memory 224324 kb
Host smart-15a907f1-3906-451d-8793-76129de1d82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443210242 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2443210242
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2598083896
Short name T69
Test name
Test status
Simulation time 37147406 ps
CPU time 0.9 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:20:57 PM PDT 24
Peak memory 215596 kb
Host smart-da0f468c-2dd4-4495-9350-939f9844a343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598083896 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2598083896
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1271551384
Short name T864
Test name
Test status
Simulation time 184920460 ps
CPU time 2.36 seconds
Started Jun 11 02:20:41 PM PDT 24
Finished Jun 11 02:20:44 PM PDT 24
Peak memory 217480 kb
Host smart-d094102b-ae29-4b30-94ce-b414cb09fa5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271551384 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1271551384
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2952741509
Short name T71
Test name
Test status
Simulation time 13787382324 ps
CPU time 322.74 seconds
Started Jun 11 02:20:43 PM PDT 24
Finished Jun 11 02:26:07 PM PDT 24
Peak memory 218724 kb
Host smart-5047a5a4-b8fa-43e2-ad7d-78708e110341
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952741509 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2952741509
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2600159297
Short name T258
Test name
Test status
Simulation time 32507357 ps
CPU time 1.36 seconds
Started Jun 11 02:20:58 PM PDT 24
Finished Jun 11 02:21:01 PM PDT 24
Peak memory 220216 kb
Host smart-dec074a5-f0ea-40a5-9a72-a73fc33536ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600159297 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2600159297
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2548914025
Short name T74
Test name
Test status
Simulation time 81180243 ps
CPU time 0.9 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:20:59 PM PDT 24
Peak memory 207084 kb
Host smart-d64ca437-96bb-4766-8579-fe369b2b06f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548914025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2548914025
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3054739974
Short name T770
Test name
Test status
Simulation time 17288863 ps
CPU time 0.86 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:20:58 PM PDT 24
Peak memory 216292 kb
Host smart-85de610d-a127-4c17-b926-afaf2b5a0f06
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054739974 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3054739974
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1979804949
Short name T491
Test name
Test status
Simulation time 51743082 ps
CPU time 1.1 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:20:57 PM PDT 24
Peak memory 218628 kb
Host smart-b69fd87c-4791-4a07-91e4-090721eb86ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979804949 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1979804949
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1905361593
Short name T208
Test name
Test status
Simulation time 18839628 ps
CPU time 1.26 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:21:00 PM PDT 24
Peak memory 224384 kb
Host smart-b3ca60db-f258-4073-b6c3-f798b64cf8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905361593 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1905361593
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3589994341
Short name T863
Test name
Test status
Simulation time 55959212 ps
CPU time 1.27 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:20:59 PM PDT 24
Peak memory 217540 kb
Host smart-cb1e474c-4d8d-4ddb-b00e-b89144bb723f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589994341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3589994341
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.99453743
Short name T36
Test name
Test status
Simulation time 21410046 ps
CPU time 0.96 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:20:57 PM PDT 24
Peak memory 216036 kb
Host smart-870ea724-3dc4-40e4-ac11-e31cce9225f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99453743 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.99453743
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2758383983
Short name T466
Test name
Test status
Simulation time 28750020 ps
CPU time 0.99 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:20:59 PM PDT 24
Peak memory 215584 kb
Host smart-852ce66f-010a-4802-830b-566aba104e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758383983 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2758383983
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2600332729
Short name T958
Test name
Test status
Simulation time 102575446 ps
CPU time 2.4 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:20:59 PM PDT 24
Peak memory 215476 kb
Host smart-3afdba3d-40e9-4a5f-bab6-a9d8bc552a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600332729 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2600332729
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1550398844
Short name T233
Test name
Test status
Simulation time 44104774321 ps
CPU time 1010.64 seconds
Started Jun 11 02:20:54 PM PDT 24
Finished Jun 11 02:37:46 PM PDT 24
Peak memory 221356 kb
Host smart-ccbbff0b-0a31-472c-959b-2ec31b61015d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550398844 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1550398844
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1408602610
Short name T740
Test name
Test status
Simulation time 30351477 ps
CPU time 1.33 seconds
Started Jun 11 02:20:54 PM PDT 24
Finished Jun 11 02:20:56 PM PDT 24
Peak memory 219120 kb
Host smart-604b3dcf-4be4-42e0-8580-495ea350c186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408602610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1408602610
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3312183809
Short name T473
Test name
Test status
Simulation time 253848460 ps
CPU time 1 seconds
Started Jun 11 02:20:57 PM PDT 24
Finished Jun 11 02:21:01 PM PDT 24
Peak memory 207068 kb
Host smart-157b250f-2109-4e22-8e3d-91baaf36e9d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312183809 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3312183809
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.10807043
Short name T133
Test name
Test status
Simulation time 54954043 ps
CPU time 1 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:21:00 PM PDT 24
Peak memory 216996 kb
Host smart-f5b6b745-4e86-44a4-a6a3-ba137a9a0670
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10807043 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_dis
able_auto_req_mode.10807043
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2808781736
Short name T119
Test name
Test status
Simulation time 20395545 ps
CPU time 1.18 seconds
Started Jun 11 02:20:59 PM PDT 24
Finished Jun 11 02:21:02 PM PDT 24
Peak memory 219944 kb
Host smart-1282c8e4-dd56-4795-aa65-89a55ec54dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808781736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2808781736
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2650825707
Short name T358
Test name
Test status
Simulation time 84071971 ps
CPU time 1.31 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:20:57 PM PDT 24
Peak memory 219156 kb
Host smart-5f28ec0d-687d-42a8-aa87-e1c4b2b57803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650825707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2650825707
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3800701273
Short name T574
Test name
Test status
Simulation time 23858310 ps
CPU time 1 seconds
Started Jun 11 02:20:54 PM PDT 24
Finished Jun 11 02:20:57 PM PDT 24
Peak memory 215816 kb
Host smart-17133312-6f41-4dc4-8a43-64eb40c482a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800701273 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3800701273
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1267426627
Short name T552
Test name
Test status
Simulation time 19113346 ps
CPU time 0.93 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:20:58 PM PDT 24
Peak memory 207416 kb
Host smart-b809b26f-305f-44ce-9420-caa871fc6e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267426627 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1267426627
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2640336200
Short name T553
Test name
Test status
Simulation time 508141402 ps
CPU time 5.47 seconds
Started Jun 11 02:20:54 PM PDT 24
Finished Jun 11 02:21:01 PM PDT 24
Peak memory 217740 kb
Host smart-717d73b3-71f9-46bd-9298-d7d03d526cd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640336200 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2640336200
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3790093467
Short name T963
Test name
Test status
Simulation time 80929334346 ps
CPU time 897.03 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:35:54 PM PDT 24
Peak memory 222076 kb
Host smart-3e81a26c-35bb-4c1d-94fc-2ec21854072b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790093467 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3790093467
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.818423809
Short name T171
Test name
Test status
Simulation time 94016965 ps
CPU time 1.19 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:20:59 PM PDT 24
Peak memory 220044 kb
Host smart-9bfdf865-1667-48a0-96b9-acf1dafe6456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818423809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.818423809
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1351678620
Short name T429
Test name
Test status
Simulation time 22836970 ps
CPU time 0.89 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:20:58 PM PDT 24
Peak memory 215264 kb
Host smart-19e5c549-56c2-409c-bc98-9d9b85d4c443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351678620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1351678620
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1888982631
Short name T160
Test name
Test status
Simulation time 319124152 ps
CPU time 1.14 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:21:00 PM PDT 24
Peak memory 217144 kb
Host smart-b1fad4f9-7ffd-4165-8f18-82a1a727cfbd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888982631 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1888982631
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.865933117
Short name T883
Test name
Test status
Simulation time 39039810 ps
CPU time 0.85 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:20:58 PM PDT 24
Peak memory 218300 kb
Host smart-c46698c4-9a43-47e0-b66a-381adf99e20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865933117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.865933117
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1862539599
Short name T433
Test name
Test status
Simulation time 69320532 ps
CPU time 2.43 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:20:59 PM PDT 24
Peak memory 220156 kb
Host smart-4a36bc6a-71a2-4337-ae34-140532954d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862539599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1862539599
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_smoke.964699484
Short name T350
Test name
Test status
Simulation time 27261948 ps
CPU time 1.02 seconds
Started Jun 11 02:20:54 PM PDT 24
Finished Jun 11 02:20:56 PM PDT 24
Peak memory 215576 kb
Host smart-6307ee5c-ae39-489b-aab3-72e1f7859676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964699484 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.964699484
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.922355862
Short name T605
Test name
Test status
Simulation time 535571477 ps
CPU time 3.35 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:21:01 PM PDT 24
Peak memory 217584 kb
Host smart-367c1fe6-acda-4bfd-a0df-d389e3662627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922355862 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.922355862
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2503561199
Short name T787
Test name
Test status
Simulation time 47468827284 ps
CPU time 266.79 seconds
Started Jun 11 02:20:54 PM PDT 24
Finished Jun 11 02:25:22 PM PDT 24
Peak memory 216124 kb
Host smart-c13cb807-9ba8-408c-8c49-1a22a66ce7c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503561199 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2503561199
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.4100940754
Short name T431
Test name
Test status
Simulation time 28060456 ps
CPU time 1.3 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:20:58 PM PDT 24
Peak memory 219996 kb
Host smart-6ca15dd8-a584-472d-8f0c-bc1fc7c0b8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100940754 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.4100940754
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1909734661
Short name T436
Test name
Test status
Simulation time 54332578 ps
CPU time 0.92 seconds
Started Jun 11 02:20:54 PM PDT 24
Finished Jun 11 02:20:56 PM PDT 24
Peak memory 214704 kb
Host smart-8ecac98a-4230-4310-a17e-f87e9f190604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909734661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1909734661
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3483540825
Short name T829
Test name
Test status
Simulation time 11769540 ps
CPU time 0.9 seconds
Started Jun 11 02:20:59 PM PDT 24
Finished Jun 11 02:21:01 PM PDT 24
Peak memory 215652 kb
Host smart-6f22b7c7-6972-48ec-8297-4a430c3ba90e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483540825 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3483540825
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.151183404
Short name T145
Test name
Test status
Simulation time 30068183 ps
CPU time 1.08 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:20:59 PM PDT 24
Peak memory 219428 kb
Host smart-8a019e5d-fc59-4c7d-b51c-94cf600519f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151183404 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.151183404
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2312423198
Short name T760
Test name
Test status
Simulation time 25646598 ps
CPU time 1.3 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:20:58 PM PDT 24
Peak memory 229808 kb
Host smart-643f86d3-3582-4497-8cee-d4fdeef43c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312423198 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2312423198
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3466248520
Short name T340
Test name
Test status
Simulation time 58408397 ps
CPU time 1.36 seconds
Started Jun 11 02:20:54 PM PDT 24
Finished Jun 11 02:20:55 PM PDT 24
Peak memory 220148 kb
Host smart-60f272a6-3a9a-4382-9685-d267f6682748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466248520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3466248520
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3332813
Short name T505
Test name
Test status
Simulation time 20943829 ps
CPU time 1.08 seconds
Started Jun 11 02:20:53 PM PDT 24
Finished Jun 11 02:20:54 PM PDT 24
Peak memory 215808 kb
Host smart-10d7f3bb-a1fa-4382-a704-0bc889d439dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332813 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3332813
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2320506140
Short name T865
Test name
Test status
Simulation time 15916931 ps
CPU time 0.97 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:20:57 PM PDT 24
Peak memory 215524 kb
Host smart-3c360253-5e48-4371-acc9-59314c436dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320506140 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2320506140
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.856361909
Short name T910
Test name
Test status
Simulation time 717906301 ps
CPU time 4.1 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:21:00 PM PDT 24
Peak memory 215572 kb
Host smart-0f2aaeb7-fcd6-46cd-973c-5693c9344a2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856361909 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.856361909
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1881641701
Short name T70
Test name
Test status
Simulation time 831342630104 ps
CPU time 2233.85 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:58:12 PM PDT 24
Peak memory 228296 kb
Host smart-52540570-35e0-4b0e-949b-8662ce994796
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881641701 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1881641701
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1628056033
Short name T333
Test name
Test status
Simulation time 34577275 ps
CPU time 1.12 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:20:59 PM PDT 24
Peak memory 218460 kb
Host smart-0606d218-b7eb-4d4a-93c8-29074c16874f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628056033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1628056033
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.4005355539
Short name T975
Test name
Test status
Simulation time 44829616 ps
CPU time 0.86 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:20:59 PM PDT 24
Peak memory 215124 kb
Host smart-08885505-9089-4df4-b9ca-56a3be16f604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005355539 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.4005355539
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.53643941
Short name T516
Test name
Test status
Simulation time 19177575 ps
CPU time 0.89 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:20:59 PM PDT 24
Peak memory 216404 kb
Host smart-558a966b-4e37-4852-a522-43a5073e38d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53643941 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.53643941
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2163018386
Short name T812
Test name
Test status
Simulation time 36785401 ps
CPU time 1.27 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:20:59 PM PDT 24
Peak memory 217004 kb
Host smart-1ac7e01c-fe62-44ec-9ed8-bf32a5d3ec44
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163018386 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2163018386
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.195997324
Short name T982
Test name
Test status
Simulation time 33361415 ps
CPU time 1.18 seconds
Started Jun 11 02:20:54 PM PDT 24
Finished Jun 11 02:20:57 PM PDT 24
Peak memory 219912 kb
Host smart-76269560-6b3f-4508-ae20-696e0a68bc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195997324 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.195997324
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3340183338
Short name T678
Test name
Test status
Simulation time 135649431 ps
CPU time 1.34 seconds
Started Jun 11 02:20:57 PM PDT 24
Finished Jun 11 02:21:00 PM PDT 24
Peak memory 218932 kb
Host smart-16b7c3d9-c194-4fc7-9342-52107f89fbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340183338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3340183338
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3148404413
Short name T819
Test name
Test status
Simulation time 27448940 ps
CPU time 0.96 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:20:59 PM PDT 24
Peak memory 215724 kb
Host smart-17964bcf-fe1b-4e8d-b806-a675b80cae6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148404413 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3148404413
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1847357983
Short name T397
Test name
Test status
Simulation time 22723814 ps
CPU time 1.01 seconds
Started Jun 11 02:20:58 PM PDT 24
Finished Jun 11 02:21:01 PM PDT 24
Peak memory 215548 kb
Host smart-12f264c6-bb5e-4c9d-9eae-363094802390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847357983 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1847357983
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1921518068
Short name T244
Test name
Test status
Simulation time 307410658 ps
CPU time 4.61 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:21:03 PM PDT 24
Peak memory 219716 kb
Host smart-f6087e23-0daa-4a18-a8ea-137567660185
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921518068 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1921518068
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3096884549
Short name T834
Test name
Test status
Simulation time 8120875630 ps
CPU time 174.18 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:23:53 PM PDT 24
Peak memory 221616 kb
Host smart-4aacc868-2be3-432b-981a-65e444299b3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096884549 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3096884549
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.594141790
Short name T906
Test name
Test status
Simulation time 24847050 ps
CPU time 1.11 seconds
Started Jun 11 02:18:43 PM PDT 24
Finished Jun 11 02:18:45 PM PDT 24
Peak memory 218788 kb
Host smart-8966667d-1f71-48e2-9beb-161ffe31e8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594141790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.594141790
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.951492970
Short name T527
Test name
Test status
Simulation time 12579888 ps
CPU time 0.91 seconds
Started Jun 11 02:18:43 PM PDT 24
Finished Jun 11 02:18:45 PM PDT 24
Peak memory 215504 kb
Host smart-9f4bc9d3-9e0d-4324-932b-4d3d40e1a250
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951492970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.951492970
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.785379110
Short name T822
Test name
Test status
Simulation time 21548701 ps
CPU time 0.84 seconds
Started Jun 11 02:18:43 PM PDT 24
Finished Jun 11 02:18:45 PM PDT 24
Peak memory 216384 kb
Host smart-3d10a243-8fcf-422c-b1e0-63a63d0c02dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785379110 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.785379110
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2921111612
Short name T692
Test name
Test status
Simulation time 33197050 ps
CPU time 1.11 seconds
Started Jun 11 02:18:43 PM PDT 24
Finished Jun 11 02:18:45 PM PDT 24
Peak memory 219808 kb
Host smart-ae91049e-028b-4cf2-952f-478eafd92ed3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921111612 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2921111612
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.4123741451
Short name T731
Test name
Test status
Simulation time 22528708 ps
CPU time 0.93 seconds
Started Jun 11 02:18:43 PM PDT 24
Finished Jun 11 02:18:45 PM PDT 24
Peak memory 218904 kb
Host smart-6ff032a2-47bd-4652-b83e-3ce7e57828cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123741451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.4123741451
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1087932544
Short name T437
Test name
Test status
Simulation time 87354920 ps
CPU time 1.19 seconds
Started Jun 11 02:18:32 PM PDT 24
Finished Jun 11 02:18:35 PM PDT 24
Peak memory 220296 kb
Host smart-cc2c8353-53ec-4b5c-998c-01e4d57e3fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087932544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1087932544
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.670614464
Short name T898
Test name
Test status
Simulation time 32939955 ps
CPU time 0.93 seconds
Started Jun 11 02:18:33 PM PDT 24
Finished Jun 11 02:18:35 PM PDT 24
Peak memory 215812 kb
Host smart-f8224df3-e0d2-4165-8f4e-b3305aa36e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670614464 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.670614464
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1163034385
Short name T335
Test name
Test status
Simulation time 20334021 ps
CPU time 1.02 seconds
Started Jun 11 02:18:33 PM PDT 24
Finished Jun 11 02:18:35 PM PDT 24
Peak memory 207404 kb
Host smart-7fa99bdd-bd9e-4b99-a3cc-ab0f594b8e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163034385 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1163034385
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3393823719
Short name T461
Test name
Test status
Simulation time 19608499 ps
CPU time 1.02 seconds
Started Jun 11 02:18:33 PM PDT 24
Finished Jun 11 02:18:36 PM PDT 24
Peak memory 215568 kb
Host smart-31880555-1ca8-40a9-9fd4-de217b5d4a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393823719 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3393823719
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2446280354
Short name T669
Test name
Test status
Simulation time 389396919 ps
CPU time 4.01 seconds
Started Jun 11 02:18:34 PM PDT 24
Finished Jun 11 02:18:40 PM PDT 24
Peak memory 217392 kb
Host smart-d1974ac7-6ebc-4ebd-a13d-f2d726ebb3b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446280354 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2446280354
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2997850930
Short name T873
Test name
Test status
Simulation time 398843518993 ps
CPU time 1690.32 seconds
Started Jun 11 02:18:33 PM PDT 24
Finished Jun 11 02:46:45 PM PDT 24
Peak memory 227288 kb
Host smart-eb089634-417a-462a-85b7-b06480d2aa0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997850930 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2997850930
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.2031371287
Short name T817
Test name
Test status
Simulation time 37996100 ps
CPU time 1.14 seconds
Started Jun 11 02:20:53 PM PDT 24
Finished Jun 11 02:20:55 PM PDT 24
Peak memory 218940 kb
Host smart-b2a1dfc7-7a8a-4acf-b096-cc191a34983d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031371287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2031371287
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.1943458653
Short name T175
Test name
Test status
Simulation time 63898461 ps
CPU time 0.86 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:20:59 PM PDT 24
Peak memory 218500 kb
Host smart-85642779-dfc8-42e3-af95-6c8bebe3f6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943458653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1943458653
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.889727904
Short name T90
Test name
Test status
Simulation time 28518857 ps
CPU time 1.17 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:20:58 PM PDT 24
Peak memory 217676 kb
Host smart-2f617266-0e0e-47f3-b841-1fdb0d65d579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889727904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.889727904
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.1928420091
Short name T800
Test name
Test status
Simulation time 31472856 ps
CPU time 1.29 seconds
Started Jun 11 02:20:54 PM PDT 24
Finished Jun 11 02:20:56 PM PDT 24
Peak memory 215944 kb
Host smart-5c63ae28-4253-44ef-95f6-4fd5bd6c5723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928420091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.1928420091
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.1961215858
Short name T859
Test name
Test status
Simulation time 29937037 ps
CPU time 1.07 seconds
Started Jun 11 02:20:58 PM PDT 24
Finished Jun 11 02:21:01 PM PDT 24
Peak memory 229784 kb
Host smart-63b55a18-f164-48f8-89b1-eef795b2f478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961215858 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1961215858
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.4139204429
Short name T323
Test name
Test status
Simulation time 305899500 ps
CPU time 4.19 seconds
Started Jun 11 02:20:55 PM PDT 24
Finished Jun 11 02:21:01 PM PDT 24
Peak memory 220484 kb
Host smart-8be10942-fc65-4876-8457-7e02a3443f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139204429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.4139204429
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.1781243989
Short name T190
Test name
Test status
Simulation time 168926923 ps
CPU time 1.37 seconds
Started Jun 11 02:20:58 PM PDT 24
Finished Jun 11 02:21:02 PM PDT 24
Peak memory 215908 kb
Host smart-a9edee7c-aebc-4740-be07-040e7d712d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781243989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.1781243989
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.256177137
Short name T648
Test name
Test status
Simulation time 73185311 ps
CPU time 1.28 seconds
Started Jun 11 02:20:57 PM PDT 24
Finished Jun 11 02:21:01 PM PDT 24
Peak memory 225128 kb
Host smart-a07e1b11-2c52-4180-8f74-5c585b0186f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256177137 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.256177137
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.412702534
Short name T649
Test name
Test status
Simulation time 38038031 ps
CPU time 1.41 seconds
Started Jun 11 02:20:57 PM PDT 24
Finished Jun 11 02:21:01 PM PDT 24
Peak memory 218780 kb
Host smart-a9a753c2-42bb-4dd4-8225-c72e76da90d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412702534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.412702534
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.3000736711
Short name T302
Test name
Test status
Simulation time 41078506 ps
CPU time 1.22 seconds
Started Jun 11 02:20:58 PM PDT 24
Finished Jun 11 02:21:01 PM PDT 24
Peak memory 218684 kb
Host smart-027f4039-81c2-42ec-99a1-fb1ee62e900e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000736711 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.3000736711
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.2210673628
Short name T165
Test name
Test status
Simulation time 34520259 ps
CPU time 0.9 seconds
Started Jun 11 02:20:58 PM PDT 24
Finished Jun 11 02:21:01 PM PDT 24
Peak memory 218456 kb
Host smart-109b09fe-7553-4316-b3f3-f6cbb62e99bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210673628 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2210673628
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3881716201
Short name T432
Test name
Test status
Simulation time 41476067 ps
CPU time 1.44 seconds
Started Jun 11 02:20:58 PM PDT 24
Finished Jun 11 02:21:02 PM PDT 24
Peak memory 217520 kb
Host smart-8dbb45dd-4fb0-4807-a367-cccd6ecfd387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881716201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3881716201
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.4223775214
Short name T303
Test name
Test status
Simulation time 25656027 ps
CPU time 1.23 seconds
Started Jun 11 02:20:58 PM PDT 24
Finished Jun 11 02:21:01 PM PDT 24
Peak memory 221036 kb
Host smart-76732a43-b118-431b-9756-58de1206c27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223775214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.4223775214
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.3007167220
Short name T541
Test name
Test status
Simulation time 31370398 ps
CPU time 0.89 seconds
Started Jun 11 02:20:57 PM PDT 24
Finished Jun 11 02:21:00 PM PDT 24
Peak memory 218780 kb
Host smart-aadc59ec-9ecd-416d-8cd2-30149d7e9c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007167220 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3007167220
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1100801687
Short name T617
Test name
Test status
Simulation time 33824573 ps
CPU time 1.3 seconds
Started Jun 11 02:20:58 PM PDT 24
Finished Jun 11 02:21:01 PM PDT 24
Peak memory 220344 kb
Host smart-49b7329a-cc4d-47e0-b447-06af42c1256a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100801687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1100801687
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.2994694579
Short name T677
Test name
Test status
Simulation time 37798435 ps
CPU time 1.09 seconds
Started Jun 11 02:21:09 PM PDT 24
Finished Jun 11 02:21:11 PM PDT 24
Peak memory 220788 kb
Host smart-44e5bf78-6a92-403d-afeb-0fbd0f98677f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994694579 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2994694579
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1218303449
Short name T961
Test name
Test status
Simulation time 41092833 ps
CPU time 1.13 seconds
Started Jun 11 02:20:56 PM PDT 24
Finished Jun 11 02:21:00 PM PDT 24
Peak memory 215560 kb
Host smart-1b82a13d-8cee-45bb-bc9e-b844d2e1a3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218303449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1218303449
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.2641339897
Short name T653
Test name
Test status
Simulation time 63768879 ps
CPU time 1.08 seconds
Started Jun 11 02:21:13 PM PDT 24
Finished Jun 11 02:21:15 PM PDT 24
Peak memory 219956 kb
Host smart-a87daa84-5d09-4310-9644-9ef7a68f3621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641339897 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.2641339897
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.3390993246
Short name T212
Test name
Test status
Simulation time 53246903 ps
CPU time 1.14 seconds
Started Jun 11 02:21:07 PM PDT 24
Finished Jun 11 02:21:10 PM PDT 24
Peak memory 219960 kb
Host smart-0db5c5db-e065-46c7-864f-9d1cded70c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390993246 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3390993246
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1394249600
Short name T426
Test name
Test status
Simulation time 60664633 ps
CPU time 1.84 seconds
Started Jun 11 02:21:08 PM PDT 24
Finished Jun 11 02:21:11 PM PDT 24
Peak memory 219372 kb
Host smart-48549588-4226-4f2b-a2ef-50ad92b09acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394249600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1394249600
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.931310569
Short name T788
Test name
Test status
Simulation time 78323608 ps
CPU time 1.14 seconds
Started Jun 11 02:21:12 PM PDT 24
Finished Jun 11 02:21:14 PM PDT 24
Peak memory 218592 kb
Host smart-4975b87a-57fa-4612-852c-c05650b07ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931310569 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.931310569
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.3682744467
Short name T64
Test name
Test status
Simulation time 20077170 ps
CPU time 1.02 seconds
Started Jun 11 02:21:10 PM PDT 24
Finished Jun 11 02:21:13 PM PDT 24
Peak memory 218688 kb
Host smart-37f42030-a4e6-4905-a2b8-f66eab5cac77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682744467 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3682744467
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2987269208
Short name T713
Test name
Test status
Simulation time 71862707 ps
CPU time 1.27 seconds
Started Jun 11 02:21:10 PM PDT 24
Finished Jun 11 02:21:12 PM PDT 24
Peak memory 217520 kb
Host smart-7497510d-fe4d-442b-8632-ef7902a4ea8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987269208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2987269208
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.261522497
Short name T752
Test name
Test status
Simulation time 66465296 ps
CPU time 1.27 seconds
Started Jun 11 02:21:07 PM PDT 24
Finished Jun 11 02:21:09 PM PDT 24
Peak memory 215896 kb
Host smart-c03085de-6a6c-46d0-bfc6-b6e164d5a8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261522497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.261522497
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.3217789615
Short name T174
Test name
Test status
Simulation time 77575273 ps
CPU time 1.2 seconds
Started Jun 11 02:21:11 PM PDT 24
Finished Jun 11 02:21:14 PM PDT 24
Peak memory 225988 kb
Host smart-617eb734-4930-4874-a21e-d86804ef71cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217789615 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3217789615
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.147551680
Short name T972
Test name
Test status
Simulation time 210589837 ps
CPU time 2.97 seconds
Started Jun 11 02:21:11 PM PDT 24
Finished Jun 11 02:21:16 PM PDT 24
Peak memory 220704 kb
Host smart-fd216ed1-3b6d-4953-9389-d95a7280b28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147551680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.147551680
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.2244105393
Short name T285
Test name
Test status
Simulation time 30403361 ps
CPU time 1.27 seconds
Started Jun 11 02:21:10 PM PDT 24
Finished Jun 11 02:21:12 PM PDT 24
Peak memory 218820 kb
Host smart-8a200484-f173-42d4-9fb2-d1392a005e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244105393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.2244105393
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.2506990689
Short name T522
Test name
Test status
Simulation time 34350122 ps
CPU time 0.93 seconds
Started Jun 11 02:21:10 PM PDT 24
Finished Jun 11 02:21:12 PM PDT 24
Peak memory 218684 kb
Host smart-6e2636fa-eae0-4159-84dd-5a305aa3769d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506990689 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2506990689
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2433654612
Short name T856
Test name
Test status
Simulation time 29212945 ps
CPU time 1.16 seconds
Started Jun 11 02:21:08 PM PDT 24
Finished Jun 11 02:21:11 PM PDT 24
Peak memory 217656 kb
Host smart-417840dc-8fc4-4432-a086-6bf9f663777f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433654612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2433654612
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.1491196661
Short name T900
Test name
Test status
Simulation time 81447754 ps
CPU time 1.22 seconds
Started Jun 11 02:18:44 PM PDT 24
Finished Jun 11 02:18:46 PM PDT 24
Peak memory 218680 kb
Host smart-abe97054-bda0-43e4-8020-8d6448d42632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491196661 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1491196661
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.4172703104
Short name T976
Test name
Test status
Simulation time 19998342 ps
CPU time 0.99 seconds
Started Jun 11 02:18:45 PM PDT 24
Finished Jun 11 02:18:47 PM PDT 24
Peak memory 207148 kb
Host smart-a55d5451-c82e-4ee4-9d3a-fdde44d888da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172703104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.4172703104
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3372371681
Short name T202
Test name
Test status
Simulation time 163365619 ps
CPU time 1.1 seconds
Started Jun 11 02:18:43 PM PDT 24
Finished Jun 11 02:18:46 PM PDT 24
Peak memory 217032 kb
Host smart-322bcd09-dda4-4d2d-a6a0-cdbb6e6ff875
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372371681 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3372371681
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2982361645
Short name T52
Test name
Test status
Simulation time 33018870 ps
CPU time 1.04 seconds
Started Jun 11 02:18:45 PM PDT 24
Finished Jun 11 02:18:47 PM PDT 24
Peak memory 224016 kb
Host smart-5f84f5d8-acf8-43c4-b6e4-d92b2fc220bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982361645 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2982361645
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3529639395
Short name T47
Test name
Test status
Simulation time 74824810 ps
CPU time 1.53 seconds
Started Jun 11 02:18:43 PM PDT 24
Finished Jun 11 02:18:46 PM PDT 24
Peak memory 218604 kb
Host smart-5756f815-eca6-4178-9668-95aefbb44adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529639395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3529639395
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.262439783
Short name T708
Test name
Test status
Simulation time 29581377 ps
CPU time 0.97 seconds
Started Jun 11 02:18:44 PM PDT 24
Finished Jun 11 02:18:47 PM PDT 24
Peak memory 215708 kb
Host smart-4bba352b-c25e-47b6-a797-f7d3690a9155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262439783 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.262439783
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1982550474
Short name T529
Test name
Test status
Simulation time 32501468 ps
CPU time 0.9 seconds
Started Jun 11 02:18:42 PM PDT 24
Finished Jun 11 02:18:43 PM PDT 24
Peak memory 207312 kb
Host smart-9fb86f05-50e5-4240-84bd-631ef8f37a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982550474 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1982550474
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.767513234
Short name T367
Test name
Test status
Simulation time 24159290 ps
CPU time 0.94 seconds
Started Jun 11 02:18:43 PM PDT 24
Finished Jun 11 02:18:45 PM PDT 24
Peak memory 207380 kb
Host smart-e9a342f2-d871-4fd4-81c0-603a9483e440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767513234 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.767513234
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2773208139
Short name T443
Test name
Test status
Simulation time 898782030 ps
CPU time 4.99 seconds
Started Jun 11 02:18:44 PM PDT 24
Finished Jun 11 02:18:51 PM PDT 24
Peak memory 217472 kb
Host smart-86e66e5c-a9bd-49bd-bda8-6574b5f7bb77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773208139 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2773208139
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2748647406
Short name T630
Test name
Test status
Simulation time 957519411950 ps
CPU time 1412.25 seconds
Started Jun 11 02:18:44 PM PDT 24
Finished Jun 11 02:42:17 PM PDT 24
Peak memory 225792 kb
Host smart-ef594c77-8f81-4532-b672-460c9543e528
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748647406 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2748647406
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.2605202741
Short name T668
Test name
Test status
Simulation time 157415487 ps
CPU time 1.24 seconds
Started Jun 11 02:21:05 PM PDT 24
Finished Jun 11 02:21:07 PM PDT 24
Peak memory 221828 kb
Host smart-d535484d-04ce-47a0-977d-466eddff4b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605202741 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.2605202741
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1114375731
Short name T455
Test name
Test status
Simulation time 49163119 ps
CPU time 0.81 seconds
Started Jun 11 02:21:08 PM PDT 24
Finished Jun 11 02:21:10 PM PDT 24
Peak memory 218132 kb
Host smart-3a25d67f-6050-40db-a839-caba23ed8c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114375731 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1114375731
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3131478487
Short name T732
Test name
Test status
Simulation time 43359379 ps
CPU time 1.01 seconds
Started Jun 11 02:21:10 PM PDT 24
Finished Jun 11 02:21:13 PM PDT 24
Peak memory 217660 kb
Host smart-7a5364c6-1768-4387-b826-411a1823d6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131478487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3131478487
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.396426878
Short name T76
Test name
Test status
Simulation time 229639018 ps
CPU time 1.33 seconds
Started Jun 11 02:21:08 PM PDT 24
Finished Jun 11 02:21:11 PM PDT 24
Peak memory 219912 kb
Host smart-431bf0ef-9c73-4249-b2c2-581e70d6fc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396426878 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.396426878
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1542361241
Short name T897
Test name
Test status
Simulation time 33185660 ps
CPU time 1.32 seconds
Started Jun 11 02:21:08 PM PDT 24
Finished Jun 11 02:21:11 PM PDT 24
Peak memory 219900 kb
Host smart-56535b70-7ba3-46dc-a003-201d3abf09e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542361241 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1542361241
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1092707734
Short name T402
Test name
Test status
Simulation time 128918500 ps
CPU time 1.47 seconds
Started Jun 11 02:21:06 PM PDT 24
Finished Jun 11 02:21:09 PM PDT 24
Peak memory 218952 kb
Host smart-4fdcd7c4-7e39-40d0-a313-e6ed7ae6ba6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092707734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1092707734
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.3842119740
Short name T587
Test name
Test status
Simulation time 54586145 ps
CPU time 1.29 seconds
Started Jun 11 02:21:10 PM PDT 24
Finished Jun 11 02:21:13 PM PDT 24
Peak memory 218828 kb
Host smart-a4fa0ed6-32ee-4197-b41f-c52f00d3abc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842119740 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.3842119740
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.3045018668
Short name T104
Test name
Test status
Simulation time 25230596 ps
CPU time 1.15 seconds
Started Jun 11 02:21:08 PM PDT 24
Finished Jun 11 02:21:11 PM PDT 24
Peak memory 218392 kb
Host smart-25588cbf-d4be-49f9-9d64-53bef2fd562d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045018668 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3045018668
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.396780983
Short name T768
Test name
Test status
Simulation time 190372880 ps
CPU time 2.6 seconds
Started Jun 11 02:21:07 PM PDT 24
Finished Jun 11 02:21:11 PM PDT 24
Peak memory 220468 kb
Host smart-1839dca7-9fe8-4a14-9583-4ea19f6d7076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396780983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.396780983
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.869589937
Short name T95
Test name
Test status
Simulation time 35411948 ps
CPU time 1.24 seconds
Started Jun 11 02:21:06 PM PDT 24
Finished Jun 11 02:21:09 PM PDT 24
Peak memory 218836 kb
Host smart-9b6fd3f0-1f69-42f4-85f5-3fa1c9378c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869589937 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.869589937
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.3231907239
Short name T247
Test name
Test status
Simulation time 25760242 ps
CPU time 1.26 seconds
Started Jun 11 02:21:12 PM PDT 24
Finished Jun 11 02:21:15 PM PDT 24
Peak memory 220952 kb
Host smart-a57e57f9-4c1e-408f-a351-3fce54c4e419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231907239 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3231907239
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3184541984
Short name T502
Test name
Test status
Simulation time 37681374 ps
CPU time 1.05 seconds
Started Jun 11 02:21:06 PM PDT 24
Finished Jun 11 02:21:08 PM PDT 24
Peak memory 217768 kb
Host smart-9a2a5997-7bb1-4249-a3b6-204045a3241d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184541984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3184541984
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.2233289318
Short name T334
Test name
Test status
Simulation time 30983049 ps
CPU time 1.2 seconds
Started Jun 11 02:21:12 PM PDT 24
Finished Jun 11 02:21:14 PM PDT 24
Peak memory 220308 kb
Host smart-3a630a80-3bc6-49c1-ae58-378dada01386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233289318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.2233289318
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.2283738349
Short name T103
Test name
Test status
Simulation time 35274771 ps
CPU time 0.93 seconds
Started Jun 11 02:21:10 PM PDT 24
Finished Jun 11 02:21:13 PM PDT 24
Peak memory 219388 kb
Host smart-a88163b9-5f5f-4bb5-bc16-1ee6cc42bf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283738349 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2283738349
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3286925189
Short name T474
Test name
Test status
Simulation time 25869017 ps
CPU time 1.13 seconds
Started Jun 11 02:21:07 PM PDT 24
Finished Jun 11 02:21:10 PM PDT 24
Peak memory 217388 kb
Host smart-175c32cf-5298-4315-b29a-cfbd39fe3f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286925189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3286925189
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.3739469602
Short name T858
Test name
Test status
Simulation time 379646698 ps
CPU time 1.46 seconds
Started Jun 11 02:21:05 PM PDT 24
Finished Jun 11 02:21:08 PM PDT 24
Peak memory 218716 kb
Host smart-329c711a-0df3-42cd-8b0c-8a54bf714937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739469602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.3739469602
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.618747154
Short name T179
Test name
Test status
Simulation time 20390936 ps
CPU time 1.07 seconds
Started Jun 11 02:21:12 PM PDT 24
Finished Jun 11 02:21:14 PM PDT 24
Peak memory 218848 kb
Host smart-a5813da2-4eb6-4eea-b5f8-b86ba159779e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618747154 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.618747154
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.758702537
Short name T893
Test name
Test status
Simulation time 42950265 ps
CPU time 1.73 seconds
Started Jun 11 02:21:11 PM PDT 24
Finished Jun 11 02:21:14 PM PDT 24
Peak memory 219072 kb
Host smart-947a53bc-a6ed-41e6-a203-708c55bee21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758702537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.758702537
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.4220745123
Short name T85
Test name
Test status
Simulation time 76292861 ps
CPU time 1.1 seconds
Started Jun 11 02:21:07 PM PDT 24
Finished Jun 11 02:21:09 PM PDT 24
Peak memory 218796 kb
Host smart-042358da-ff30-4641-99a5-9f776b849a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220745123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.4220745123
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.3669385117
Short name T142
Test name
Test status
Simulation time 24432696 ps
CPU time 0.94 seconds
Started Jun 11 02:21:11 PM PDT 24
Finished Jun 11 02:21:14 PM PDT 24
Peak memory 219920 kb
Host smart-959ed91b-2627-4695-a052-1b3c67b60b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669385117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3669385117
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.963263247
Short name T345
Test name
Test status
Simulation time 61544137 ps
CPU time 1.05 seconds
Started Jun 11 02:21:08 PM PDT 24
Finished Jun 11 02:21:10 PM PDT 24
Peak memory 217672 kb
Host smart-6fcbf9ff-4676-4c48-8a40-7853008b7341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963263247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.963263247
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.1841122409
Short name T259
Test name
Test status
Simulation time 50420159 ps
CPU time 1.29 seconds
Started Jun 11 02:21:07 PM PDT 24
Finished Jun 11 02:21:09 PM PDT 24
Peak memory 218952 kb
Host smart-091e3abb-05be-4b20-8181-72368521fcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841122409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.1841122409
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.586913500
Short name T125
Test name
Test status
Simulation time 27458455 ps
CPU time 1.32 seconds
Started Jun 11 02:21:09 PM PDT 24
Finished Jun 11 02:21:11 PM PDT 24
Peak memory 229888 kb
Host smart-a97535fb-66ef-4622-a207-0fd14c1a01bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586913500 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.586913500
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3638546542
Short name T624
Test name
Test status
Simulation time 39233545 ps
CPU time 1.45 seconds
Started Jun 11 02:21:10 PM PDT 24
Finished Jun 11 02:21:13 PM PDT 24
Peak memory 218000 kb
Host smart-e1b2bf41-96ff-4e4e-82bf-6df0ed27bb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638546542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3638546542
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.3364954669
Short name T177
Test name
Test status
Simulation time 73610370 ps
CPU time 1.12 seconds
Started Jun 11 02:21:06 PM PDT 24
Finished Jun 11 02:21:09 PM PDT 24
Peak memory 220012 kb
Host smart-8cc7e5bc-bad7-4e8e-b220-e7f803bcc71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364954669 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.3364954669
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.1300585992
Short name T533
Test name
Test status
Simulation time 23574907 ps
CPU time 1.11 seconds
Started Jun 11 02:21:08 PM PDT 24
Finished Jun 11 02:21:11 PM PDT 24
Peak memory 224268 kb
Host smart-1c0bd08d-a7dc-43ef-a4f8-c1906f27bd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300585992 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1300585992
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1978493604
Short name T884
Test name
Test status
Simulation time 92353953 ps
CPU time 2.89 seconds
Started Jun 11 02:21:12 PM PDT 24
Finished Jun 11 02:21:16 PM PDT 24
Peak memory 220136 kb
Host smart-ce97f76d-66a7-45ae-9a1e-5463862702b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978493604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1978493604
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.53889390
Short name T797
Test name
Test status
Simulation time 26617906 ps
CPU time 1.29 seconds
Started Jun 11 02:21:08 PM PDT 24
Finished Jun 11 02:21:11 PM PDT 24
Peak memory 219888 kb
Host smart-4e8cbab1-a281-4c19-8ae2-57a840576795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53889390 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.53889390
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2694475383
Short name T214
Test name
Test status
Simulation time 66775979 ps
CPU time 1.13 seconds
Started Jun 11 02:21:12 PM PDT 24
Finished Jun 11 02:21:15 PM PDT 24
Peak memory 219652 kb
Host smart-427c2714-f822-451a-b41f-7b7380bd835e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694475383 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2694475383
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2390769067
Short name T846
Test name
Test status
Simulation time 130838134 ps
CPU time 1.21 seconds
Started Jun 11 02:21:11 PM PDT 24
Finished Jun 11 02:21:14 PM PDT 24
Peak memory 220372 kb
Host smart-48d12671-f705-44f1-8890-e60df46bfcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390769067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2390769067
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2275264452
Short name T293
Test name
Test status
Simulation time 39837478 ps
CPU time 1.31 seconds
Started Jun 11 02:18:45 PM PDT 24
Finished Jun 11 02:18:47 PM PDT 24
Peak memory 218948 kb
Host smart-36ebace7-0b19-4f67-951c-02767da06ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275264452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2275264452
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1981711304
Short name T403
Test name
Test status
Simulation time 15964627 ps
CPU time 0.94 seconds
Started Jun 11 02:18:52 PM PDT 24
Finished Jun 11 02:18:54 PM PDT 24
Peak memory 207048 kb
Host smart-7201b627-ec64-4bed-8323-1ee64f7c7dab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981711304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1981711304
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.559924630
Short name T204
Test name
Test status
Simulation time 34431174 ps
CPU time 0.87 seconds
Started Jun 11 02:18:52 PM PDT 24
Finished Jun 11 02:18:54 PM PDT 24
Peak memory 215636 kb
Host smart-62e0278d-ec37-47ab-b2c8-8cdea68b08b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559924630 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.559924630
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3245479157
Short name T122
Test name
Test status
Simulation time 97578346 ps
CPU time 1.25 seconds
Started Jun 11 02:18:54 PM PDT 24
Finished Jun 11 02:18:57 PM PDT 24
Peak memory 217068 kb
Host smart-fb195481-564d-4999-9f96-7de763760c7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245479157 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3245479157
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1253934239
Short name T185
Test name
Test status
Simulation time 26781640 ps
CPU time 1.02 seconds
Started Jun 11 02:18:45 PM PDT 24
Finished Jun 11 02:18:48 PM PDT 24
Peak memory 223996 kb
Host smart-2bde8eb4-099d-4981-a7b1-c37c66fde6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253934239 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1253934239
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3570722347
Short name T937
Test name
Test status
Simulation time 35968188 ps
CPU time 1.37 seconds
Started Jun 11 02:18:46 PM PDT 24
Finished Jun 11 02:18:48 PM PDT 24
Peak memory 218772 kb
Host smart-18d95a54-cf0e-45d8-a326-cd84a2aecedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570722347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3570722347
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.612577176
Short name T676
Test name
Test status
Simulation time 20996590 ps
CPU time 1.07 seconds
Started Jun 11 02:18:48 PM PDT 24
Finished Jun 11 02:18:50 PM PDT 24
Peak memory 215716 kb
Host smart-c7f8c3c7-b45f-4aa2-96db-3196a64f6ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612577176 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.612577176
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.361415480
Short name T336
Test name
Test status
Simulation time 37767796 ps
CPU time 0.88 seconds
Started Jun 11 02:18:44 PM PDT 24
Finished Jun 11 02:18:47 PM PDT 24
Peak memory 207380 kb
Host smart-ca55b8d1-6d41-42c8-bdfa-b70c64c2a783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361415480 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.361415480
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3999537451
Short name T373
Test name
Test status
Simulation time 18216211 ps
CPU time 0.97 seconds
Started Jun 11 02:18:46 PM PDT 24
Finished Jun 11 02:18:49 PM PDT 24
Peak memory 215424 kb
Host smart-b62c1ba3-4c10-4dd5-b089-b99a5a8e6df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999537451 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3999537451
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1645928917
Short name T891
Test name
Test status
Simulation time 1761273778 ps
CPU time 2.68 seconds
Started Jun 11 02:18:44 PM PDT 24
Finished Jun 11 02:18:48 PM PDT 24
Peak memory 217488 kb
Host smart-9b0a423b-1346-4bd5-9bb7-f1399c117589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645928917 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1645928917
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1908783087
Short name T230
Test name
Test status
Simulation time 21262927400 ps
CPU time 525.92 seconds
Started Jun 11 02:18:50 PM PDT 24
Finished Jun 11 02:27:36 PM PDT 24
Peak memory 218676 kb
Host smart-08330649-ab43-468f-8391-74a667d53c2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908783087 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1908783087
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.357110127
Short name T644
Test name
Test status
Simulation time 51552346 ps
CPU time 1.25 seconds
Started Jun 11 02:21:11 PM PDT 24
Finished Jun 11 02:21:14 PM PDT 24
Peak memory 218668 kb
Host smart-e4bd93b9-d944-4120-b956-c3f4469ce617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357110127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.357110127
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.3174465265
Short name T111
Test name
Test status
Simulation time 26750143 ps
CPU time 1.29 seconds
Started Jun 11 02:21:07 PM PDT 24
Finished Jun 11 02:21:09 PM PDT 24
Peak memory 220908 kb
Host smart-9401ca90-367c-4a03-ad30-a96e03fb5143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174465265 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3174465265
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2599231625
Short name T887
Test name
Test status
Simulation time 210841743 ps
CPU time 3.48 seconds
Started Jun 11 02:21:09 PM PDT 24
Finished Jun 11 02:21:13 PM PDT 24
Peak memory 218876 kb
Host smart-e9971cce-928d-4def-a7c1-d7b87e13e47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599231625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2599231625
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.3258789834
Short name T849
Test name
Test status
Simulation time 68056376 ps
CPU time 1.14 seconds
Started Jun 11 02:21:12 PM PDT 24
Finished Jun 11 02:21:15 PM PDT 24
Peak memory 220568 kb
Host smart-df7c40a8-827f-46db-9937-3dd906818cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258789834 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.3258789834
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.2027685487
Short name T795
Test name
Test status
Simulation time 41215620 ps
CPU time 0.86 seconds
Started Jun 11 02:21:10 PM PDT 24
Finished Jun 11 02:21:13 PM PDT 24
Peak memory 218652 kb
Host smart-381b2842-ddaa-4b0a-bbf4-6586cd088572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027685487 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2027685487
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1594979113
Short name T394
Test name
Test status
Simulation time 25874788 ps
CPU time 1.18 seconds
Started Jun 11 02:21:08 PM PDT 24
Finished Jun 11 02:21:10 PM PDT 24
Peak memory 217508 kb
Host smart-cf63a02b-109a-4443-bd03-0ea345fd190f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594979113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1594979113
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.1288822943
Short name T338
Test name
Test status
Simulation time 35373198 ps
CPU time 1.11 seconds
Started Jun 11 02:21:10 PM PDT 24
Finished Jun 11 02:21:12 PM PDT 24
Peak memory 220980 kb
Host smart-f2437a22-056c-44ba-beb8-d583426a3d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288822943 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.1288822943
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3491610206
Short name T804
Test name
Test status
Simulation time 50390173 ps
CPU time 1.06 seconds
Started Jun 11 02:21:12 PM PDT 24
Finished Jun 11 02:21:14 PM PDT 24
Peak memory 229856 kb
Host smart-c3cdb197-f3e8-4617-8f20-284024ddeda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491610206 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3491610206
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.4145647987
Short name T870
Test name
Test status
Simulation time 42329862 ps
CPU time 1.35 seconds
Started Jun 11 02:21:13 PM PDT 24
Finished Jun 11 02:21:15 PM PDT 24
Peak memory 218960 kb
Host smart-4d8d6ae4-c31d-41b0-9316-45f7d56fe222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145647987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.4145647987
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.3645486162
Short name T578
Test name
Test status
Simulation time 53794410 ps
CPU time 1.27 seconds
Started Jun 11 02:21:12 PM PDT 24
Finished Jun 11 02:21:14 PM PDT 24
Peak memory 215912 kb
Host smart-01844aee-b230-4441-9484-ae451d0db006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645486162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.3645486162
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.2690723783
Short name T799
Test name
Test status
Simulation time 31645627 ps
CPU time 1.4 seconds
Started Jun 11 02:21:13 PM PDT 24
Finished Jun 11 02:21:16 PM PDT 24
Peak memory 219812 kb
Host smart-3b4dd8ea-912f-436f-89b5-47f9c9160ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690723783 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2690723783
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.751674822
Short name T894
Test name
Test status
Simulation time 96885729 ps
CPU time 1.12 seconds
Started Jun 11 02:21:13 PM PDT 24
Finished Jun 11 02:21:16 PM PDT 24
Peak memory 217372 kb
Host smart-ee64fad8-bc6a-4f5d-a055-cc89f73e5922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751674822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.751674822
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.2722191034
Short name T827
Test name
Test status
Simulation time 33505617 ps
CPU time 1.31 seconds
Started Jun 11 02:21:12 PM PDT 24
Finished Jun 11 02:21:15 PM PDT 24
Peak memory 218800 kb
Host smart-8b1d173e-bfe5-4026-831b-dc3f83611195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722191034 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.2722191034
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.1358660071
Short name T159
Test name
Test status
Simulation time 40622757 ps
CPU time 1 seconds
Started Jun 11 02:21:13 PM PDT 24
Finished Jun 11 02:21:16 PM PDT 24
Peak memory 219880 kb
Host smart-5d450219-43bf-4bba-9ce3-026c49cdf52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358660071 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1358660071
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2691459451
Short name T58
Test name
Test status
Simulation time 63704175 ps
CPU time 1.27 seconds
Started Jun 11 02:21:12 PM PDT 24
Finished Jun 11 02:21:14 PM PDT 24
Peak memory 217656 kb
Host smart-21b8de44-7984-417c-9e1c-d55f12c07e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691459451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2691459451
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.1432899719
Short name T141
Test name
Test status
Simulation time 26265212 ps
CPU time 1.15 seconds
Started Jun 11 02:21:10 PM PDT 24
Finished Jun 11 02:21:12 PM PDT 24
Peak memory 218820 kb
Host smart-4b68a9d9-8d58-483e-a180-2e28de0c1a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432899719 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.1432899719
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.2531397532
Short name T193
Test name
Test status
Simulation time 78131659 ps
CPU time 0.83 seconds
Started Jun 11 02:21:10 PM PDT 24
Finished Jun 11 02:21:12 PM PDT 24
Peak memory 218668 kb
Host smart-d19d323d-479d-409e-a744-ea7c25270d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531397532 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2531397532
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1704542923
Short name T399
Test name
Test status
Simulation time 28996442 ps
CPU time 1.24 seconds
Started Jun 11 02:21:12 PM PDT 24
Finished Jun 11 02:21:15 PM PDT 24
Peak memory 218796 kb
Host smart-48dc6bd5-9fcd-4e93-867e-fbcc888d63b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704542923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1704542923
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.2237728338
Short name T201
Test name
Test status
Simulation time 41401545 ps
CPU time 0.87 seconds
Started Jun 11 02:21:20 PM PDT 24
Finished Jun 11 02:21:21 PM PDT 24
Peak memory 219504 kb
Host smart-9fc09786-dcf6-4b18-aca3-3cb46445cbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237728338 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2237728338
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.4231539024
Short name T101
Test name
Test status
Simulation time 44665268 ps
CPU time 1.66 seconds
Started Jun 11 02:21:20 PM PDT 24
Finished Jun 11 02:21:22 PM PDT 24
Peak memory 220264 kb
Host smart-ebdfcc18-25c5-45e0-bbec-917d0d7cfd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231539024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.4231539024
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.589998144
Short name T532
Test name
Test status
Simulation time 42704436 ps
CPU time 1.17 seconds
Started Jun 11 02:21:21 PM PDT 24
Finished Jun 11 02:21:23 PM PDT 24
Peak memory 219000 kb
Host smart-2a5e73c7-b8e9-406e-ac1d-3bb176403fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589998144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.589998144
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_genbits.1226675356
Short name T65
Test name
Test status
Simulation time 91948427 ps
CPU time 2.8 seconds
Started Jun 11 02:21:20 PM PDT 24
Finished Jun 11 02:21:23 PM PDT 24
Peak memory 220576 kb
Host smart-ea89c6d3-5848-4577-9678-bda2514379a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226675356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1226675356
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.2578729225
Short name T184
Test name
Test status
Simulation time 30023794 ps
CPU time 1.3 seconds
Started Jun 11 02:21:19 PM PDT 24
Finished Jun 11 02:21:21 PM PDT 24
Peak memory 215932 kb
Host smart-b62fff5a-ffd2-463c-950f-fc421ccf53c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578729225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.2578729225
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.104885724
Short name T54
Test name
Test status
Simulation time 50546584 ps
CPU time 1.31 seconds
Started Jun 11 02:21:16 PM PDT 24
Finished Jun 11 02:21:18 PM PDT 24
Peak memory 225680 kb
Host smart-d1b5c421-8035-4c21-b6db-0c22a8e2389e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104885724 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.104885724
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.204395174
Short name T400
Test name
Test status
Simulation time 52393128 ps
CPU time 1.28 seconds
Started Jun 11 02:21:19 PM PDT 24
Finished Jun 11 02:21:22 PM PDT 24
Peak memory 217464 kb
Host smart-b9af0506-7104-4962-bc64-3d820822a5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204395174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.204395174
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.88201615
Short name T139
Test name
Test status
Simulation time 50803271 ps
CPU time 1.22 seconds
Started Jun 11 02:21:21 PM PDT 24
Finished Jun 11 02:21:24 PM PDT 24
Peak memory 220768 kb
Host smart-4f645c71-7271-4884-98a7-7e2614b916f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88201615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.88201615
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.1068711193
Short name T500
Test name
Test status
Simulation time 23433258 ps
CPU time 0.99 seconds
Started Jun 11 02:21:21 PM PDT 24
Finished Jun 11 02:21:24 PM PDT 24
Peak memory 224028 kb
Host smart-bde34599-159f-4fd6-be36-4665e4b07882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068711193 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1068711193
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2662381068
Short name T376
Test name
Test status
Simulation time 43756797 ps
CPU time 1.17 seconds
Started Jun 11 02:21:16 PM PDT 24
Finished Jun 11 02:21:18 PM PDT 24
Peak memory 218704 kb
Host smart-bf432b45-9cb0-42ac-be55-546a2bc538bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662381068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2662381068
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1600561151
Short name T229
Test name
Test status
Simulation time 67803542 ps
CPU time 1.23 seconds
Started Jun 11 02:18:52 PM PDT 24
Finished Jun 11 02:18:54 PM PDT 24
Peak memory 219464 kb
Host smart-22538d58-500c-4a8d-9040-d1719ee2cf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600561151 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1600561151
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3282360166
Short name T606
Test name
Test status
Simulation time 166061091 ps
CPU time 1.04 seconds
Started Jun 11 02:18:53 PM PDT 24
Finished Jun 11 02:18:55 PM PDT 24
Peak memory 207140 kb
Host smart-eb7f4399-589b-43df-9825-9c0f312462a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282360166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3282360166
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3730281614
Short name T930
Test name
Test status
Simulation time 10602101 ps
CPU time 0.88 seconds
Started Jun 11 02:18:53 PM PDT 24
Finished Jun 11 02:18:56 PM PDT 24
Peak memory 216532 kb
Host smart-713f9be2-e3a1-49b4-a47d-5324cf5c4486
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730281614 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3730281614
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3014359990
Short name T926
Test name
Test status
Simulation time 96388419 ps
CPU time 1.13 seconds
Started Jun 11 02:18:53 PM PDT 24
Finished Jun 11 02:18:55 PM PDT 24
Peak memory 217128 kb
Host smart-1511d5f8-e13c-415a-96c7-953df782db84
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014359990 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3014359990
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1342863036
Short name T419
Test name
Test status
Simulation time 26941252 ps
CPU time 0.94 seconds
Started Jun 11 02:18:52 PM PDT 24
Finished Jun 11 02:18:53 PM PDT 24
Peak memory 218772 kb
Host smart-855c8f88-9536-4a4f-84ab-4b84f6728a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342863036 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1342863036
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3747398979
Short name T597
Test name
Test status
Simulation time 21833755 ps
CPU time 1.22 seconds
Started Jun 11 02:18:53 PM PDT 24
Finished Jun 11 02:18:56 PM PDT 24
Peak memory 220084 kb
Host smart-b0fe3cfa-8158-4665-8830-3f324e73e0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747398979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3747398979
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.764147087
Short name T832
Test name
Test status
Simulation time 39964928 ps
CPU time 1.03 seconds
Started Jun 11 02:18:52 PM PDT 24
Finished Jun 11 02:18:53 PM PDT 24
Peak memory 224320 kb
Host smart-7c1bbda1-177b-49e2-a9bc-325e0598ae67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764147087 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.764147087
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.541638812
Short name T27
Test name
Test status
Simulation time 16412938 ps
CPU time 1.01 seconds
Started Jun 11 02:18:53 PM PDT 24
Finished Jun 11 02:18:55 PM PDT 24
Peak memory 207408 kb
Host smart-21553e30-6eb4-4112-91f8-a464966cb313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541638812 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.541638812
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.997936163
Short name T855
Test name
Test status
Simulation time 33342172 ps
CPU time 0.9 seconds
Started Jun 11 02:18:55 PM PDT 24
Finished Jun 11 02:18:57 PM PDT 24
Peak memory 215460 kb
Host smart-61eca493-6cad-4205-b566-614aac5ca3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997936163 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.997936163
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2068395203
Short name T638
Test name
Test status
Simulation time 318744339 ps
CPU time 6.29 seconds
Started Jun 11 02:18:54 PM PDT 24
Finished Jun 11 02:19:01 PM PDT 24
Peak memory 217860 kb
Host smart-c21155be-52bc-4a4c-8db0-04411662c760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068395203 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2068395203
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3487067732
Short name T236
Test name
Test status
Simulation time 407722817255 ps
CPU time 1442.14 seconds
Started Jun 11 02:18:53 PM PDT 24
Finished Jun 11 02:42:56 PM PDT 24
Peak memory 224148 kb
Host smart-6d8e854d-8977-4b6d-bd9e-fa761665a53f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487067732 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3487067732
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.2417376742
Short name T932
Test name
Test status
Simulation time 33998150 ps
CPU time 1.35 seconds
Started Jun 11 02:21:13 PM PDT 24
Finished Jun 11 02:21:16 PM PDT 24
Peak memory 215864 kb
Host smart-c2124756-d3a6-4c60-91f1-12beb08a5a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417376742 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2417376742
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.4010336457
Short name T661
Test name
Test status
Simulation time 23026592 ps
CPU time 0.98 seconds
Started Jun 11 02:21:20 PM PDT 24
Finished Jun 11 02:21:22 PM PDT 24
Peak memory 219808 kb
Host smart-f4954df0-d1bd-4940-b2e2-532c21380b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010336457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.4010336457
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2845080890
Short name T18
Test name
Test status
Simulation time 58029099 ps
CPU time 1.29 seconds
Started Jun 11 02:21:22 PM PDT 24
Finished Jun 11 02:21:25 PM PDT 24
Peak memory 219820 kb
Host smart-e160af51-f811-44d7-a980-8365ed743509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845080890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2845080890
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.1902109222
Short name T132
Test name
Test status
Simulation time 105161641 ps
CPU time 1.15 seconds
Started Jun 11 02:21:15 PM PDT 24
Finished Jun 11 02:21:17 PM PDT 24
Peak memory 229980 kb
Host smart-1128cbc4-0bc7-47a6-b368-789d9961f314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902109222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1902109222
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.30104619
Short name T44
Test name
Test status
Simulation time 89065481 ps
CPU time 1.28 seconds
Started Jun 11 02:21:16 PM PDT 24
Finished Jun 11 02:21:18 PM PDT 24
Peak memory 217756 kb
Host smart-ea1b8c17-0489-4ce0-8b12-2b58a89f5d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30104619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.30104619
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.2101498535
Short name T990
Test name
Test status
Simulation time 25106275 ps
CPU time 1.17 seconds
Started Jun 11 02:21:20 PM PDT 24
Finished Jun 11 02:21:22 PM PDT 24
Peak memory 221092 kb
Host smart-90f32e63-e981-49d4-ab3f-fa01cfb25d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101498535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.2101498535
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.4205136284
Short name T406
Test name
Test status
Simulation time 67011740 ps
CPU time 1.03 seconds
Started Jun 11 02:21:15 PM PDT 24
Finished Jun 11 02:21:17 PM PDT 24
Peak memory 218788 kb
Host smart-91135e21-a94b-485f-8cdb-d24e4bb597c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205136284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.4205136284
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.437733144
Short name T769
Test name
Test status
Simulation time 66878670 ps
CPU time 1.04 seconds
Started Jun 11 02:21:21 PM PDT 24
Finished Jun 11 02:21:23 PM PDT 24
Peak memory 217476 kb
Host smart-4dd85865-6572-4fc6-a0a0-3d27363d337c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437733144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.437733144
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.1473249881
Short name T995
Test name
Test status
Simulation time 74837174 ps
CPU time 1.2 seconds
Started Jun 11 02:21:17 PM PDT 24
Finished Jun 11 02:21:19 PM PDT 24
Peak memory 220776 kb
Host smart-5f9bde74-a154-44a5-8f84-fbff08a73fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473249881 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.1473249881
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.399673588
Short name T960
Test name
Test status
Simulation time 30880907 ps
CPU time 0.99 seconds
Started Jun 11 02:21:21 PM PDT 24
Finished Jun 11 02:21:24 PM PDT 24
Peak memory 224008 kb
Host smart-90ca089a-19d8-44e3-993f-27a89bd0e2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399673588 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.399673588
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1885763323
Short name T317
Test name
Test status
Simulation time 172067421 ps
CPU time 1.71 seconds
Started Jun 11 02:21:20 PM PDT 24
Finished Jun 11 02:21:22 PM PDT 24
Peak memory 218984 kb
Host smart-f9fee67b-5b90-4fb9-97ed-f62ed3d3cbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885763323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1885763323
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.204437232
Short name T246
Test name
Test status
Simulation time 29954225 ps
CPU time 1.25 seconds
Started Jun 11 02:21:28 PM PDT 24
Finished Jun 11 02:21:30 PM PDT 24
Peak memory 219496 kb
Host smart-f0346515-2587-4010-9441-ee78b8e08884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204437232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.204437232
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.3554260470
Short name T837
Test name
Test status
Simulation time 71244424 ps
CPU time 1.12 seconds
Started Jun 11 02:21:23 PM PDT 24
Finished Jun 11 02:21:25 PM PDT 24
Peak memory 219944 kb
Host smart-e7c86d4a-ff28-4be9-9b27-4267ecfe7c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554260470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3554260470
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3384578505
Short name T916
Test name
Test status
Simulation time 590920854 ps
CPU time 4.91 seconds
Started Jun 11 02:21:20 PM PDT 24
Finished Jun 11 02:21:26 PM PDT 24
Peak memory 217712 kb
Host smart-b9dec8de-d970-4fea-9198-14d0f53e542f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384578505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3384578505
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.844177489
Short name T751
Test name
Test status
Simulation time 26401336 ps
CPU time 1.25 seconds
Started Jun 11 02:21:25 PM PDT 24
Finished Jun 11 02:21:27 PM PDT 24
Peak memory 218908 kb
Host smart-a5896eae-9b70-492b-8ceb-da90373e7ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844177489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.844177489
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.3987368934
Short name T690
Test name
Test status
Simulation time 26143417 ps
CPU time 0.92 seconds
Started Jun 11 02:21:25 PM PDT 24
Finished Jun 11 02:21:26 PM PDT 24
Peak memory 218672 kb
Host smart-ab9550c4-eda8-41fb-b4ae-1633bc8b3336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987368934 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3987368934
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1275522734
Short name T890
Test name
Test status
Simulation time 72926129 ps
CPU time 1.9 seconds
Started Jun 11 02:21:25 PM PDT 24
Finished Jun 11 02:21:28 PM PDT 24
Peak memory 220620 kb
Host smart-245e42b8-8e31-4e46-8564-2bb10f1d02e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275522734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1275522734
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.2562998567
Short name T164
Test name
Test status
Simulation time 27505841 ps
CPU time 1.36 seconds
Started Jun 11 02:21:28 PM PDT 24
Finished Jun 11 02:21:30 PM PDT 24
Peak memory 219308 kb
Host smart-7f3bd545-dc8a-4492-a618-6c9a5a0cc7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562998567 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.2562998567
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2849578478
Short name T143
Test name
Test status
Simulation time 38027152 ps
CPU time 1.18 seconds
Started Jun 11 02:21:25 PM PDT 24
Finished Jun 11 02:21:28 PM PDT 24
Peak memory 229928 kb
Host smart-f656b78b-fc92-4d5d-a162-df43a1ccfaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849578478 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2849578478
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.328220223
Short name T748
Test name
Test status
Simulation time 36717203 ps
CPU time 1.41 seconds
Started Jun 11 02:21:26 PM PDT 24
Finished Jun 11 02:21:28 PM PDT 24
Peak memory 219024 kb
Host smart-6a5132c2-d997-42b1-84f2-09cda437ff82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328220223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.328220223
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.2930042938
Short name T927
Test name
Test status
Simulation time 92140693 ps
CPU time 1.19 seconds
Started Jun 11 02:21:31 PM PDT 24
Finished Jun 11 02:21:33 PM PDT 24
Peak memory 218740 kb
Host smart-26484bad-ce4f-4a7a-828c-a90d133f9dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930042938 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.2930042938
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.2137788938
Short name T867
Test name
Test status
Simulation time 40349990 ps
CPU time 1.15 seconds
Started Jun 11 02:21:23 PM PDT 24
Finished Jun 11 02:21:25 PM PDT 24
Peak memory 220668 kb
Host smart-ae7e2f12-269c-40f3-b357-fcacca429936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137788938 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2137788938
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.989306729
Short name T842
Test name
Test status
Simulation time 61006043 ps
CPU time 1.38 seconds
Started Jun 11 02:21:24 PM PDT 24
Finished Jun 11 02:21:26 PM PDT 24
Peak memory 218796 kb
Host smart-8463e674-a9b9-4ddc-bd1c-59a6c7501679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989306729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.989306729
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.2511198723
Short name T77
Test name
Test status
Simulation time 19830898 ps
CPU time 1.11 seconds
Started Jun 11 02:21:31 PM PDT 24
Finished Jun 11 02:21:33 PM PDT 24
Peak memory 218268 kb
Host smart-2ce5c952-9fa8-45cb-9b52-292edcdbc027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511198723 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2511198723
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.316134212
Short name T905
Test name
Test status
Simulation time 97178789 ps
CPU time 1.29 seconds
Started Jun 11 02:21:26 PM PDT 24
Finished Jun 11 02:21:28 PM PDT 24
Peak memory 220184 kb
Host smart-e59b0432-60c2-4ef7-a6ae-13f38fedbd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316134212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.316134212
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.594880121
Short name T771
Test name
Test status
Simulation time 26158443 ps
CPU time 1.2 seconds
Started Jun 11 02:21:26 PM PDT 24
Finished Jun 11 02:21:28 PM PDT 24
Peak memory 220064 kb
Host smart-cd906fef-0e17-4bb7-937f-33459cbe21fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594880121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.594880121
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.3446242132
Short name T739
Test name
Test status
Simulation time 19479718 ps
CPU time 1.07 seconds
Started Jun 11 02:21:25 PM PDT 24
Finished Jun 11 02:21:27 PM PDT 24
Peak memory 218548 kb
Host smart-d28aa9f9-f33b-4e6e-b4b0-84f1503e9e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446242132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3446242132
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1090404902
Short name T722
Test name
Test status
Simulation time 172617955 ps
CPU time 1.2 seconds
Started Jun 11 02:21:26 PM PDT 24
Finished Jun 11 02:21:28 PM PDT 24
Peak memory 217476 kb
Host smart-68dff78e-4785-4457-a313-126ca7b92aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090404902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1090404902
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.2350929833
Short name T337
Test name
Test status
Simulation time 36563361 ps
CPU time 1.28 seconds
Started Jun 11 02:18:53 PM PDT 24
Finished Jun 11 02:18:55 PM PDT 24
Peak memory 219928 kb
Host smart-b7ca9565-7e67-49a2-8e67-d8ac4a9ba092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350929833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2350929833
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.690608394
Short name T370
Test name
Test status
Simulation time 12442603 ps
CPU time 0.87 seconds
Started Jun 11 02:19:06 PM PDT 24
Finished Jun 11 02:19:08 PM PDT 24
Peak memory 206960 kb
Host smart-0daa6136-99f7-4dcc-b504-cce604a5502a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690608394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.690608394
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.684263288
Short name T227
Test name
Test status
Simulation time 14396408 ps
CPU time 0.95 seconds
Started Jun 11 02:19:07 PM PDT 24
Finished Jun 11 02:19:10 PM PDT 24
Peak memory 216812 kb
Host smart-15b8e588-d066-472c-a4d3-8368275d1f8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684263288 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.684263288
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3778934973
Short name T871
Test name
Test status
Simulation time 101280407 ps
CPU time 0.95 seconds
Started Jun 11 02:19:07 PM PDT 24
Finished Jun 11 02:19:09 PM PDT 24
Peak memory 218360 kb
Host smart-8edff94f-f571-4cd5-bc47-c03d2094a5f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778934973 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3778934973
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.174288707
Short name T381
Test name
Test status
Simulation time 35273322 ps
CPU time 0.85 seconds
Started Jun 11 02:19:09 PM PDT 24
Finished Jun 11 02:19:11 PM PDT 24
Peak memory 218512 kb
Host smart-fa5dba05-6f9d-4ec0-b83f-5f131529f700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174288707 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.174288707
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.591915862
Short name T962
Test name
Test status
Simulation time 35979861 ps
CPU time 1.39 seconds
Started Jun 11 02:18:53 PM PDT 24
Finished Jun 11 02:18:56 PM PDT 24
Peak memory 218604 kb
Host smart-7957384e-2b0d-4f49-9b21-83819bb84022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591915862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.591915862
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3779939250
Short name T852
Test name
Test status
Simulation time 38332849 ps
CPU time 1.02 seconds
Started Jun 11 02:18:54 PM PDT 24
Finished Jun 11 02:18:57 PM PDT 24
Peak memory 224312 kb
Host smart-02a80806-f639-4600-8b86-e5f0f25a73dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779939250 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3779939250
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2607182067
Short name T26
Test name
Test status
Simulation time 47814875 ps
CPU time 0.91 seconds
Started Jun 11 02:18:54 PM PDT 24
Finished Jun 11 02:18:56 PM PDT 24
Peak memory 207380 kb
Host smart-0ef378ec-1b36-4bb3-8b74-f57562edda02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607182067 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2607182067
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1451582079
Short name T903
Test name
Test status
Simulation time 26488186 ps
CPU time 0.94 seconds
Started Jun 11 02:18:53 PM PDT 24
Finished Jun 11 02:18:55 PM PDT 24
Peak memory 215552 kb
Host smart-378b7630-0b56-4d92-ac3e-b50b42e11a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451582079 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1451582079
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3552787546
Short name T778
Test name
Test status
Simulation time 291687605 ps
CPU time 2.2 seconds
Started Jun 11 02:18:54 PM PDT 24
Finished Jun 11 02:18:57 PM PDT 24
Peak memory 220256 kb
Host smart-800e252b-4806-4aee-8d41-93fa49c58454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552787546 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3552787546
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.150673688
Short name T786
Test name
Test status
Simulation time 16838465971 ps
CPU time 211.88 seconds
Started Jun 11 02:18:54 PM PDT 24
Finished Jun 11 02:22:28 PM PDT 24
Peak memory 218852 kb
Host smart-8767bef3-38c4-4fb3-ac77-ea35d20f5144
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150673688 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.150673688
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.669992177
Short name T457
Test name
Test status
Simulation time 22212452 ps
CPU time 1.2 seconds
Started Jun 11 02:21:25 PM PDT 24
Finished Jun 11 02:21:27 PM PDT 24
Peak memory 218984 kb
Host smart-be6e8cef-a069-4c30-bece-439a386f6396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669992177 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.669992177
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.2901521546
Short name T123
Test name
Test status
Simulation time 20493967 ps
CPU time 1.1 seconds
Started Jun 11 02:21:26 PM PDT 24
Finished Jun 11 02:21:28 PM PDT 24
Peak memory 219896 kb
Host smart-93e145ec-c5a0-4362-8abd-12d53d7d141d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901521546 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2901521546
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3731071077
Short name T427
Test name
Test status
Simulation time 24602354 ps
CPU time 1.15 seconds
Started Jun 11 02:21:26 PM PDT 24
Finished Jun 11 02:21:28 PM PDT 24
Peak memory 220276 kb
Host smart-11ecebb7-b462-4356-b150-ad0da28db8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731071077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3731071077
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.138243821
Short name T515
Test name
Test status
Simulation time 63546225 ps
CPU time 1.11 seconds
Started Jun 11 02:21:27 PM PDT 24
Finished Jun 11 02:21:29 PM PDT 24
Peak memory 219144 kb
Host smart-124b34ac-6fb0-488d-b977-1dada11bd5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138243821 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.138243821
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.3432639031
Short name T481
Test name
Test status
Simulation time 135449502 ps
CPU time 1.22 seconds
Started Jun 11 02:21:24 PM PDT 24
Finished Jun 11 02:21:27 PM PDT 24
Peak memory 225864 kb
Host smart-86380cba-2db0-4c5f-81e7-24caf12d5e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432639031 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3432639031
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3109360950
Short name T766
Test name
Test status
Simulation time 72023589 ps
CPU time 1.19 seconds
Started Jun 11 02:21:31 PM PDT 24
Finished Jun 11 02:21:33 PM PDT 24
Peak memory 217712 kb
Host smart-b36328f6-c8e1-4491-9d8f-f9250ff9aac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109360950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3109360950
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.110305208
Short name T647
Test name
Test status
Simulation time 28451449 ps
CPU time 1.23 seconds
Started Jun 11 02:21:27 PM PDT 24
Finished Jun 11 02:21:29 PM PDT 24
Peak memory 215936 kb
Host smart-c55c3fb6-8e16-4ec8-8c90-55983653f184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110305208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.110305208
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.129415450
Short name T220
Test name
Test status
Simulation time 77214230 ps
CPU time 1.18 seconds
Started Jun 11 02:21:26 PM PDT 24
Finished Jun 11 02:21:28 PM PDT 24
Peak memory 225872 kb
Host smart-4d80232a-13e3-49b7-b27b-92826a4269bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129415450 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.129415450
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3136226251
Short name T720
Test name
Test status
Simulation time 52894452 ps
CPU time 1.61 seconds
Started Jun 11 02:21:25 PM PDT 24
Finished Jun 11 02:21:27 PM PDT 24
Peak memory 218656 kb
Host smart-e22768a0-77ed-46ae-b083-77834df51e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136226251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3136226251
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.1095716341
Short name T129
Test name
Test status
Simulation time 22563316 ps
CPU time 1.17 seconds
Started Jun 11 02:21:35 PM PDT 24
Finished Jun 11 02:21:37 PM PDT 24
Peak memory 221172 kb
Host smart-b054c818-04c0-41ea-8065-332333528a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095716341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.1095716341
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.2699083727
Short name T977
Test name
Test status
Simulation time 47315002 ps
CPU time 0.84 seconds
Started Jun 11 02:21:35 PM PDT 24
Finished Jun 11 02:21:36 PM PDT 24
Peak memory 219420 kb
Host smart-2f8bbd7a-41c9-4a97-90f3-214f86deb828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699083727 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2699083727
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2121161006
Short name T948
Test name
Test status
Simulation time 42112594 ps
CPU time 1.54 seconds
Started Jun 11 02:21:25 PM PDT 24
Finished Jun 11 02:21:28 PM PDT 24
Peak memory 218896 kb
Host smart-73dda9c1-21cd-41aa-9eba-336757c71129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121161006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2121161006
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.2298184733
Short name T130
Test name
Test status
Simulation time 24046489 ps
CPU time 1.18 seconds
Started Jun 11 02:21:34 PM PDT 24
Finished Jun 11 02:21:36 PM PDT 24
Peak memory 218808 kb
Host smart-8bf3ec5e-88c0-4efb-8790-905f56539326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298184733 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.2298184733
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1675180890
Short name T710
Test name
Test status
Simulation time 30351275 ps
CPU time 0.91 seconds
Started Jun 11 02:21:33 PM PDT 24
Finished Jun 11 02:21:35 PM PDT 24
Peak memory 218420 kb
Host smart-388f3a22-aff8-4ddb-b267-de9a8ec424c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675180890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1675180890
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1986066549
Short name T438
Test name
Test status
Simulation time 34614144 ps
CPU time 1.4 seconds
Started Jun 11 02:21:33 PM PDT 24
Finished Jun 11 02:21:35 PM PDT 24
Peak memory 217476 kb
Host smart-64d46e14-e015-48f4-8432-1f3370d8ea94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986066549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1986066549
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.397736708
Short name T458
Test name
Test status
Simulation time 60005899 ps
CPU time 1.11 seconds
Started Jun 11 02:21:34 PM PDT 24
Finished Jun 11 02:21:36 PM PDT 24
Peak memory 215928 kb
Host smart-05e2d545-0f96-4a33-8af1-e524eeb79a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397736708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.397736708
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1463020222
Short name T918
Test name
Test status
Simulation time 48124411 ps
CPU time 1.03 seconds
Started Jun 11 02:21:34 PM PDT 24
Finished Jun 11 02:21:36 PM PDT 24
Peak memory 219716 kb
Host smart-ca7e9ffb-2008-4ab3-9efe-e32342e9b667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463020222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1463020222
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2390811600
Short name T503
Test name
Test status
Simulation time 124663685 ps
CPU time 1.15 seconds
Started Jun 11 02:21:34 PM PDT 24
Finished Jun 11 02:21:36 PM PDT 24
Peak memory 217604 kb
Host smart-0d3bd8fb-9b1c-42af-8107-95735a074333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390811600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2390811600
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.990569633
Short name T389
Test name
Test status
Simulation time 21185139 ps
CPU time 1.11 seconds
Started Jun 11 02:21:52 PM PDT 24
Finished Jun 11 02:21:55 PM PDT 24
Peak memory 218640 kb
Host smart-0977f464-671f-4d5b-ad37-d7e0e9e52343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990569633 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.990569633
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.1449631239
Short name T124
Test name
Test status
Simulation time 49860867 ps
CPU time 1 seconds
Started Jun 11 02:21:44 PM PDT 24
Finished Jun 11 02:21:46 PM PDT 24
Peak memory 219832 kb
Host smart-e226aa63-5217-477e-bcc5-509c2f636784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449631239 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1449631239
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.783419372
Short name T659
Test name
Test status
Simulation time 44015646 ps
CPU time 1.23 seconds
Started Jun 11 02:21:45 PM PDT 24
Finished Jun 11 02:21:47 PM PDT 24
Peak memory 217604 kb
Host smart-4587771e-8aed-4c01-98c9-7b818ddd530c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783419372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.783419372
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.3177675577
Short name T172
Test name
Test status
Simulation time 79169899 ps
CPU time 1.17 seconds
Started Jun 11 02:21:48 PM PDT 24
Finished Jun 11 02:21:53 PM PDT 24
Peak memory 219052 kb
Host smart-46ef72f8-37ac-45c1-a397-1b29401f5ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177675577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.3177675577
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.1291144408
Short name T118
Test name
Test status
Simulation time 33533519 ps
CPU time 1.06 seconds
Started Jun 11 02:21:49 PM PDT 24
Finished Jun 11 02:21:53 PM PDT 24
Peak memory 229944 kb
Host smart-51d6ee05-0ebe-41fa-bd7f-e6da03ed1f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291144408 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1291144408
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/98.edn_err.2202623190
Short name T137
Test name
Test status
Simulation time 39262345 ps
CPU time 0.94 seconds
Started Jun 11 02:21:46 PM PDT 24
Finished Jun 11 02:21:50 PM PDT 24
Peak memory 219740 kb
Host smart-bc522b07-9af7-4057-b475-db748a8b5692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202623190 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2202623190
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1726478647
Short name T758
Test name
Test status
Simulation time 63389461 ps
CPU time 1.62 seconds
Started Jun 11 02:21:45 PM PDT 24
Finished Jun 11 02:21:48 PM PDT 24
Peak memory 218624 kb
Host smart-19f706c4-a0ef-4556-83a5-3a1d6f2159a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726478647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1726478647
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.204349182
Short name T117
Test name
Test status
Simulation time 66882031 ps
CPU time 1.21 seconds
Started Jun 11 02:21:46 PM PDT 24
Finished Jun 11 02:21:51 PM PDT 24
Peak memory 219432 kb
Host smart-f6a31066-9506-40fa-a5e8-55883067c876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204349182 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.204349182
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.3215524661
Short name T892
Test name
Test status
Simulation time 36730578 ps
CPU time 1.37 seconds
Started Jun 11 02:21:49 PM PDT 24
Finished Jun 11 02:21:53 PM PDT 24
Peak memory 219916 kb
Host smart-68ae3b91-adaa-4913-907e-a128d727c0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215524661 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3215524661
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3641680645
Short name T666
Test name
Test status
Simulation time 487652710 ps
CPU time 4.33 seconds
Started Jun 11 02:21:46 PM PDT 24
Finished Jun 11 02:21:54 PM PDT 24
Peak memory 219408 kb
Host smart-f641b8cb-ecd0-4e51-b467-8365b785f8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641680645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3641680645
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%