Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.78 98.25 93.91 97.02 93.02 96.37 99.77 92.08


Total test records in report: 1130
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T1020 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4291756542 Jun 13 02:40:32 PM PDT 24 Jun 13 02:40:40 PM PDT 24 224922742 ps
T251 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.4033841783 Jun 13 02:40:45 PM PDT 24 Jun 13 02:40:50 PM PDT 24 377994844 ps
T1021 /workspace/coverage/cover_reg_top/35.edn_intr_test.2893112478 Jun 13 02:40:50 PM PDT 24 Jun 13 02:40:56 PM PDT 24 11690448 ps
T1022 /workspace/coverage/cover_reg_top/42.edn_intr_test.4156185839 Jun 13 02:40:51 PM PDT 24 Jun 13 02:40:58 PM PDT 24 19215538 ps
T1023 /workspace/coverage/cover_reg_top/3.edn_intr_test.4033883034 Jun 13 02:40:33 PM PDT 24 Jun 13 02:40:40 PM PDT 24 24241316 ps
T1024 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.558776227 Jun 13 02:40:35 PM PDT 24 Jun 13 02:40:41 PM PDT 24 67436422 ps
T1025 /workspace/coverage/cover_reg_top/49.edn_intr_test.4177534151 Jun 13 02:40:53 PM PDT 24 Jun 13 02:41:01 PM PDT 24 40601227 ps
T286 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1646657991 Jun 13 02:40:49 PM PDT 24 Jun 13 02:40:58 PM PDT 24 117986003 ps
T1026 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4132049350 Jun 13 02:40:33 PM PDT 24 Jun 13 02:40:42 PM PDT 24 1265993109 ps
T1027 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2524134584 Jun 13 02:40:33 PM PDT 24 Jun 13 02:40:41 PM PDT 24 32976512 ps
T1028 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3283840498 Jun 13 02:40:33 PM PDT 24 Jun 13 02:40:39 PM PDT 24 24644189 ps
T252 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1061540939 Jun 13 02:40:45 PM PDT 24 Jun 13 02:40:50 PM PDT 24 26442940 ps
T1029 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3866437626 Jun 13 02:40:45 PM PDT 24 Jun 13 02:40:52 PM PDT 24 57585616 ps
T1030 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1001074831 Jun 13 02:40:49 PM PDT 24 Jun 13 02:40:57 PM PDT 24 227781906 ps
T1031 /workspace/coverage/cover_reg_top/6.edn_tl_errors.929718444 Jun 13 02:40:30 PM PDT 24 Jun 13 02:40:38 PM PDT 24 158561937 ps
T1032 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4086507995 Jun 13 02:40:46 PM PDT 24 Jun 13 02:40:54 PM PDT 24 89972207 ps
T262 /workspace/coverage/cover_reg_top/16.edn_csr_rw.4017881585 Jun 13 02:40:46 PM PDT 24 Jun 13 02:40:52 PM PDT 24 43786815 ps
T263 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2340382313 Jun 13 02:40:38 PM PDT 24 Jun 13 02:40:44 PM PDT 24 45265158 ps
T1033 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.248326649 Jun 13 02:40:39 PM PDT 24 Jun 13 02:40:46 PM PDT 24 114937636 ps
T1034 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3153865591 Jun 13 02:40:45 PM PDT 24 Jun 13 02:40:51 PM PDT 24 90101066 ps
T264 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.4144428674 Jun 13 02:40:35 PM PDT 24 Jun 13 02:40:42 PM PDT 24 60471799 ps
T1035 /workspace/coverage/cover_reg_top/34.edn_intr_test.1226474800 Jun 13 02:40:57 PM PDT 24 Jun 13 02:41:03 PM PDT 24 138710343 ps
T1036 /workspace/coverage/cover_reg_top/33.edn_intr_test.2899881202 Jun 13 02:40:53 PM PDT 24 Jun 13 02:41:00 PM PDT 24 34179558 ps
T1037 /workspace/coverage/cover_reg_top/1.edn_tl_errors.913017811 Jun 13 02:40:30 PM PDT 24 Jun 13 02:40:38 PM PDT 24 946964510 ps
T1038 /workspace/coverage/cover_reg_top/47.edn_intr_test.2444239002 Jun 13 02:40:58 PM PDT 24 Jun 13 02:41:04 PM PDT 24 12898904 ps
T265 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3616846854 Jun 13 02:40:45 PM PDT 24 Jun 13 02:40:50 PM PDT 24 17326384 ps
T1039 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3513975591 Jun 13 02:40:39 PM PDT 24 Jun 13 02:40:47 PM PDT 24 78411920 ps
T266 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3622331318 Jun 13 02:40:37 PM PDT 24 Jun 13 02:40:44 PM PDT 24 11391616 ps
T1040 /workspace/coverage/cover_reg_top/17.edn_intr_test.1943435083 Jun 13 02:40:46 PM PDT 24 Jun 13 02:40:52 PM PDT 24 24893489 ps
T1041 /workspace/coverage/cover_reg_top/40.edn_intr_test.469591249 Jun 13 02:40:51 PM PDT 24 Jun 13 02:40:59 PM PDT 24 11850854 ps
T267 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1782450418 Jun 13 02:40:45 PM PDT 24 Jun 13 02:40:50 PM PDT 24 43222130 ps
T253 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.349935807 Jun 13 02:40:35 PM PDT 24 Jun 13 02:40:41 PM PDT 24 50004507 ps
T1042 /workspace/coverage/cover_reg_top/0.edn_intr_test.567940753 Jun 13 02:40:27 PM PDT 24 Jun 13 02:40:32 PM PDT 24 60020316 ps
T1043 /workspace/coverage/cover_reg_top/28.edn_intr_test.377899961 Jun 13 02:40:53 PM PDT 24 Jun 13 02:41:00 PM PDT 24 18373600 ps
T1044 /workspace/coverage/cover_reg_top/43.edn_intr_test.808966606 Jun 13 02:40:51 PM PDT 24 Jun 13 02:40:59 PM PDT 24 29692365 ps
T1045 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.173934999 Jun 13 02:40:35 PM PDT 24 Jun 13 02:40:42 PM PDT 24 254126702 ps
T1046 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3349426638 Jun 13 02:40:48 PM PDT 24 Jun 13 02:40:54 PM PDT 24 19392362 ps
T1047 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1169958455 Jun 13 02:40:35 PM PDT 24 Jun 13 02:40:41 PM PDT 24 18484075 ps
T259 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.532097675 Jun 13 02:40:33 PM PDT 24 Jun 13 02:40:42 PM PDT 24 58947597 ps
T1048 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1713240862 Jun 13 02:40:33 PM PDT 24 Jun 13 02:40:40 PM PDT 24 88715350 ps
T1049 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2842917688 Jun 13 02:40:26 PM PDT 24 Jun 13 02:40:31 PM PDT 24 77974003 ps
T1050 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.592934303 Jun 13 02:40:42 PM PDT 24 Jun 13 02:40:48 PM PDT 24 62175793 ps
T1051 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3793609042 Jun 13 02:40:41 PM PDT 24 Jun 13 02:40:49 PM PDT 24 183469208 ps
T1052 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.663877610 Jun 13 02:40:46 PM PDT 24 Jun 13 02:40:53 PM PDT 24 97465877 ps
T1053 /workspace/coverage/cover_reg_top/22.edn_intr_test.2675064111 Jun 13 02:40:49 PM PDT 24 Jun 13 02:40:56 PM PDT 24 65720559 ps
T1054 /workspace/coverage/cover_reg_top/11.edn_intr_test.500557203 Jun 13 02:40:48 PM PDT 24 Jun 13 02:40:54 PM PDT 24 11824262 ps
T1055 /workspace/coverage/cover_reg_top/6.edn_intr_test.2312998988 Jun 13 02:40:35 PM PDT 24 Jun 13 02:40:41 PM PDT 24 34745295 ps
T1056 /workspace/coverage/cover_reg_top/20.edn_intr_test.605320907 Jun 13 02:40:43 PM PDT 24 Jun 13 02:40:49 PM PDT 24 13231782 ps
T1057 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.786302698 Jun 13 02:40:49 PM PDT 24 Jun 13 02:40:57 PM PDT 24 113608647 ps
T1058 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2534816783 Jun 13 02:40:39 PM PDT 24 Jun 13 02:40:47 PM PDT 24 73050928 ps
T1059 /workspace/coverage/cover_reg_top/9.edn_intr_test.1607257171 Jun 13 02:41:43 PM PDT 24 Jun 13 02:41:48 PM PDT 24 13807983 ps
T1060 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.311854397 Jun 13 02:40:36 PM PDT 24 Jun 13 02:40:42 PM PDT 24 25782969 ps
T1061 /workspace/coverage/cover_reg_top/5.edn_intr_test.2692427190 Jun 13 02:40:33 PM PDT 24 Jun 13 02:40:40 PM PDT 24 18730714 ps
T1062 /workspace/coverage/cover_reg_top/15.edn_csr_rw.3901930709 Jun 13 02:40:38 PM PDT 24 Jun 13 02:40:44 PM PDT 24 63275432 ps
T1063 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4036372421 Jun 13 02:40:49 PM PDT 24 Jun 13 02:40:56 PM PDT 24 42407861 ps
T260 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2329722758 Jun 13 02:40:26 PM PDT 24 Jun 13 02:40:33 PM PDT 24 113272023 ps
T1064 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2595403694 Jun 13 02:40:43 PM PDT 24 Jun 13 02:40:48 PM PDT 24 38049307 ps
T1065 /workspace/coverage/cover_reg_top/2.edn_intr_test.1450446572 Jun 13 02:40:35 PM PDT 24 Jun 13 02:40:41 PM PDT 24 39454781 ps
T1066 /workspace/coverage/cover_reg_top/23.edn_intr_test.3891322755 Jun 13 02:40:49 PM PDT 24 Jun 13 02:40:56 PM PDT 24 88202252 ps
T1067 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2060754583 Jun 13 02:40:38 PM PDT 24 Jun 13 02:40:45 PM PDT 24 40900113 ps
T1068 /workspace/coverage/cover_reg_top/1.edn_intr_test.352887459 Jun 13 02:40:25 PM PDT 24 Jun 13 02:40:30 PM PDT 24 56389588 ps
T1069 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1656179754 Jun 13 02:40:48 PM PDT 24 Jun 13 02:40:54 PM PDT 24 73329979 ps
T287 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1312878414 Jun 13 02:40:35 PM PDT 24 Jun 13 02:40:42 PM PDT 24 280515816 ps
T1070 /workspace/coverage/cover_reg_top/19.edn_tl_errors.939518673 Jun 13 02:40:44 PM PDT 24 Jun 13 02:40:50 PM PDT 24 124760996 ps
T1071 /workspace/coverage/cover_reg_top/29.edn_intr_test.100590933 Jun 13 02:40:50 PM PDT 24 Jun 13 02:40:58 PM PDT 24 13219746 ps
T1072 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.562470235 Jun 13 02:40:31 PM PDT 24 Jun 13 02:40:41 PM PDT 24 347193581 ps
T1073 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1704992853 Jun 13 02:40:49 PM PDT 24 Jun 13 02:40:56 PM PDT 24 24233877 ps
T1074 /workspace/coverage/cover_reg_top/10.edn_intr_test.3142282092 Jun 13 02:40:46 PM PDT 24 Jun 13 02:40:52 PM PDT 24 64426127 ps
T1075 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3433304000 Jun 13 02:40:49 PM PDT 24 Jun 13 02:40:56 PM PDT 24 24272992 ps
T1076 /workspace/coverage/cover_reg_top/18.edn_intr_test.4105511438 Jun 13 02:40:49 PM PDT 24 Jun 13 02:40:57 PM PDT 24 16009807 ps
T1077 /workspace/coverage/cover_reg_top/24.edn_intr_test.3234754401 Jun 13 02:40:48 PM PDT 24 Jun 13 02:40:55 PM PDT 24 144417848 ps
T1078 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1831111191 Jun 13 02:40:30 PM PDT 24 Jun 13 02:40:37 PM PDT 24 225847622 ps
T254 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.960591443 Jun 13 02:40:36 PM PDT 24 Jun 13 02:40:43 PM PDT 24 51102781 ps
T1079 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3092098195 Jun 13 02:40:49 PM PDT 24 Jun 13 02:40:57 PM PDT 24 46726054 ps
T1080 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3388528386 Jun 13 02:40:49 PM PDT 24 Jun 13 02:40:57 PM PDT 24 116179211 ps
T1081 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3827222127 Jun 13 02:40:32 PM PDT 24 Jun 13 02:40:38 PM PDT 24 46472363 ps
T1082 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1937222436 Jun 13 02:40:36 PM PDT 24 Jun 13 02:40:42 PM PDT 24 196038804 ps
T1083 /workspace/coverage/cover_reg_top/0.edn_tl_errors.159985682 Jun 13 02:40:24 PM PDT 24 Jun 13 02:40:30 PM PDT 24 74811925 ps
T1084 /workspace/coverage/cover_reg_top/27.edn_intr_test.1308036599 Jun 13 02:40:50 PM PDT 24 Jun 13 02:40:57 PM PDT 24 47915729 ps
T1085 /workspace/coverage/cover_reg_top/46.edn_intr_test.491946119 Jun 13 02:40:58 PM PDT 24 Jun 13 02:41:04 PM PDT 24 34249322 ps
T1086 /workspace/coverage/cover_reg_top/13.edn_intr_test.3577227639 Jun 13 02:40:40 PM PDT 24 Jun 13 02:40:46 PM PDT 24 32750184 ps
T1087 /workspace/coverage/cover_reg_top/5.edn_csr_rw.371599441 Jun 13 02:40:33 PM PDT 24 Jun 13 02:40:39 PM PDT 24 94275119 ps
T1088 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3863140450 Jun 13 02:40:45 PM PDT 24 Jun 13 02:40:50 PM PDT 24 27381418 ps
T288 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.992380636 Jun 13 02:40:38 PM PDT 24 Jun 13 02:40:45 PM PDT 24 134268078 ps
T1089 /workspace/coverage/cover_reg_top/38.edn_intr_test.3442118831 Jun 13 02:40:50 PM PDT 24 Jun 13 02:40:57 PM PDT 24 88328194 ps
T1090 /workspace/coverage/cover_reg_top/0.edn_csr_rw.3070028697 Jun 13 02:40:25 PM PDT 24 Jun 13 02:40:30 PM PDT 24 32453858 ps
T255 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1668473560 Jun 13 02:40:37 PM PDT 24 Jun 13 02:40:43 PM PDT 24 16853833 ps
T1091 /workspace/coverage/cover_reg_top/19.edn_intr_test.2647660405 Jun 13 02:40:48 PM PDT 24 Jun 13 02:40:54 PM PDT 24 149041218 ps
T1092 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1037066294 Jun 13 02:40:37 PM PDT 24 Jun 13 02:40:44 PM PDT 24 24986153 ps
T1093 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.4289172579 Jun 13 02:40:33 PM PDT 24 Jun 13 02:40:39 PM PDT 24 63422060 ps
T1094 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.952761497 Jun 13 02:40:33 PM PDT 24 Jun 13 02:40:41 PM PDT 24 128895900 ps
T1095 /workspace/coverage/cover_reg_top/25.edn_intr_test.3694359915 Jun 13 02:40:43 PM PDT 24 Jun 13 02:40:49 PM PDT 24 12994111 ps
T1096 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3001370968 Jun 13 02:40:40 PM PDT 24 Jun 13 02:40:46 PM PDT 24 74045897 ps
T1097 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2813011757 Jun 13 02:40:35 PM PDT 24 Jun 13 02:40:41 PM PDT 24 19607550 ps
T1098 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2743520987 Jun 13 02:40:32 PM PDT 24 Jun 13 02:40:38 PM PDT 24 20583880 ps
T256 /workspace/coverage/cover_reg_top/8.edn_csr_rw.68559450 Jun 13 02:40:45 PM PDT 24 Jun 13 02:40:50 PM PDT 24 40754641 ps
T257 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2897403428 Jun 13 02:40:34 PM PDT 24 Jun 13 02:40:40 PM PDT 24 68882772 ps
T1099 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4287782581 Jun 13 02:40:33 PM PDT 24 Jun 13 02:40:40 PM PDT 24 86219061 ps
T1100 /workspace/coverage/cover_reg_top/45.edn_intr_test.3899704169 Jun 13 02:40:49 PM PDT 24 Jun 13 02:40:56 PM PDT 24 16636252 ps
T1101 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1353554802 Jun 13 02:40:31 PM PDT 24 Jun 13 02:40:37 PM PDT 24 18490601 ps
T1102 /workspace/coverage/cover_reg_top/21.edn_intr_test.3558775419 Jun 13 02:40:42 PM PDT 24 Jun 13 02:40:48 PM PDT 24 13341869 ps
T1103 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1846045938 Jun 13 02:40:27 PM PDT 24 Jun 13 02:40:33 PM PDT 24 293888006 ps
T1104 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1327260108 Jun 13 02:40:41 PM PDT 24 Jun 13 02:40:48 PM PDT 24 74399861 ps
T1105 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1447118135 Jun 13 02:40:39 PM PDT 24 Jun 13 02:40:46 PM PDT 24 96534230 ps
T1106 /workspace/coverage/cover_reg_top/18.edn_csr_rw.2732235597 Jun 13 02:40:42 PM PDT 24 Jun 13 02:40:48 PM PDT 24 23355197 ps
T1107 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.418058559 Jun 13 02:40:46 PM PDT 24 Jun 13 02:40:51 PM PDT 24 36779635 ps
T1108 /workspace/coverage/cover_reg_top/19.edn_csr_rw.58490272 Jun 13 02:40:43 PM PDT 24 Jun 13 02:40:48 PM PDT 24 40833511 ps
T1109 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3645190153 Jun 13 02:40:36 PM PDT 24 Jun 13 02:40:42 PM PDT 24 33281461 ps
T1110 /workspace/coverage/cover_reg_top/4.edn_intr_test.4076769772 Jun 13 02:40:35 PM PDT 24 Jun 13 02:40:41 PM PDT 24 13741693 ps
T1111 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1869532380 Jun 13 02:40:45 PM PDT 24 Jun 13 02:40:52 PM PDT 24 192565468 ps
T1112 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3646416505 Jun 13 02:40:41 PM PDT 24 Jun 13 02:40:47 PM PDT 24 43100395 ps
T1113 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2023225247 Jun 13 02:40:48 PM PDT 24 Jun 13 02:40:54 PM PDT 24 45538441 ps
T1114 /workspace/coverage/cover_reg_top/14.edn_intr_test.792797285 Jun 13 02:40:47 PM PDT 24 Jun 13 02:40:54 PM PDT 24 21061708 ps
T1115 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2940112450 Jun 13 02:40:31 PM PDT 24 Jun 13 02:40:39 PM PDT 24 478261742 ps
T1116 /workspace/coverage/cover_reg_top/44.edn_intr_test.4222999520 Jun 13 02:40:52 PM PDT 24 Jun 13 02:40:59 PM PDT 24 14610861 ps
T1117 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1654074687 Jun 13 02:40:51 PM PDT 24 Jun 13 02:40:58 PM PDT 24 60316806 ps
T1118 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3600182369 Jun 13 02:40:42 PM PDT 24 Jun 13 02:40:48 PM PDT 24 34442465 ps
T1119 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2880634371 Jun 13 02:40:33 PM PDT 24 Jun 13 02:40:40 PM PDT 24 62911741 ps
T1120 /workspace/coverage/cover_reg_top/16.edn_intr_test.3000349898 Jun 13 02:40:48 PM PDT 24 Jun 13 02:40:54 PM PDT 24 30397425 ps
T1121 /workspace/coverage/cover_reg_top/14.edn_tl_errors.503181656 Jun 13 02:40:43 PM PDT 24 Jun 13 02:40:49 PM PDT 24 63724333 ps
T1122 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2980305301 Jun 13 02:40:49 PM PDT 24 Jun 13 02:40:56 PM PDT 24 59676792 ps
T1123 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3159431169 Jun 13 02:40:48 PM PDT 24 Jun 13 02:40:56 PM PDT 24 166665898 ps
T1124 /workspace/coverage/cover_reg_top/39.edn_intr_test.3549515822 Jun 13 02:40:50 PM PDT 24 Jun 13 02:40:58 PM PDT 24 21824391 ps
T1125 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1474112176 Jun 13 02:40:36 PM PDT 24 Jun 13 02:40:43 PM PDT 24 29520525 ps
T1126 /workspace/coverage/cover_reg_top/36.edn_intr_test.807117032 Jun 13 02:40:51 PM PDT 24 Jun 13 02:40:59 PM PDT 24 16608208 ps
T258 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.4056319911 Jun 13 02:40:33 PM PDT 24 Jun 13 02:40:39 PM PDT 24 15846830 ps
T1127 /workspace/coverage/cover_reg_top/26.edn_intr_test.481086670 Jun 13 02:40:51 PM PDT 24 Jun 13 02:40:58 PM PDT 24 27276195 ps
T1128 /workspace/coverage/cover_reg_top/13.edn_tl_errors.104935657 Jun 13 02:40:48 PM PDT 24 Jun 13 02:40:55 PM PDT 24 136657970 ps
T1129 /workspace/coverage/cover_reg_top/32.edn_intr_test.1994290022 Jun 13 02:40:51 PM PDT 24 Jun 13 02:40:59 PM PDT 24 17623172 ps
T1130 /workspace/coverage/cover_reg_top/4.edn_csr_rw.580756618 Jun 13 02:40:42 PM PDT 24 Jun 13 02:40:47 PM PDT 24 39526987 ps

Test location /workspace/coverage/default/182.edn_genbits.1882711583
Short name T10
Test name
Test status
Simulation time 117158404 ps
CPU time 2.75 seconds
Started Jun 13 01:51:47 PM PDT 24
Finished Jun 13 01:51:52 PM PDT 24
Peak memory 217924 kb
Host smart-e8c7e323-0fef-440a-a15d-583b2a829b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882711583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1882711583
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2493333318
Short name T4
Test name
Test status
Simulation time 1134876136384 ps
CPU time 3697.1 seconds
Started Jun 13 01:50:15 PM PDT 24
Finished Jun 13 02:51:55 PM PDT 24
Peak memory 236228 kb
Host smart-9d795fc4-be47-488d-b8aa-4864952536ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493333318 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2493333318
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.edn_alert.3680153725
Short name T11
Test name
Test status
Simulation time 50386647 ps
CPU time 1.3 seconds
Started Jun 13 01:50:40 PM PDT 24
Finished Jun 13 01:50:44 PM PDT 24
Peak memory 217924 kb
Host smart-3194a37c-fc2b-4ebc-91d7-850e699679a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680153725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.3680153725
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3623358053
Short name T18
Test name
Test status
Simulation time 3620191565 ps
CPU time 8.88 seconds
Started Jun 13 01:48:53 PM PDT 24
Finished Jun 13 01:49:04 PM PDT 24
Peak memory 237444 kb
Host smart-edce982b-ab3e-42de-a253-280d450671e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623358053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3623358053
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/80.edn_err.1888365741
Short name T50
Test name
Test status
Simulation time 29373241 ps
CPU time 0.95 seconds
Started Jun 13 01:50:57 PM PDT 24
Finished Jun 13 01:51:00 PM PDT 24
Peak memory 223188 kb
Host smart-b4f22dde-566c-41a6-b623-f91761c72a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888365741 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1888365741
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/23.edn_disable.2134590146
Short name T178
Test name
Test status
Simulation time 23042462 ps
CPU time 0.9 seconds
Started Jun 13 01:49:46 PM PDT 24
Finished Jun 13 01:49:47 PM PDT 24
Peak memory 215684 kb
Host smart-6758d2d3-e471-4d20-9d1b-e0096efb633f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134590146 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2134590146
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/109.edn_alert.2174094427
Short name T80
Test name
Test status
Simulation time 228475734 ps
CPU time 1.42 seconds
Started Jun 13 01:51:19 PM PDT 24
Finished Jun 13 01:51:22 PM PDT 24
Peak memory 219956 kb
Host smart-2a2cc681-6859-4d76-95b2-0b2395939611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174094427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.2174094427
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2972202837
Short name T109
Test name
Test status
Simulation time 113513464 ps
CPU time 1.25 seconds
Started Jun 13 01:49:43 PM PDT 24
Finished Jun 13 01:49:46 PM PDT 24
Peak memory 216296 kb
Host smart-bdab9cff-8586-4d4f-8e46-5d54ddba1593
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972202837 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2972202837
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.4255237465
Short name T71
Test name
Test status
Simulation time 51096597493 ps
CPU time 1179.54 seconds
Started Jun 13 01:50:08 PM PDT 24
Finished Jun 13 02:09:50 PM PDT 24
Peak memory 220208 kb
Host smart-21d10964-9eb1-4b7c-b981-85502bef91cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255237465 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.4255237465
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/186.edn_genbits.3083339837
Short name T43
Test name
Test status
Simulation time 84788044 ps
CPU time 1.9 seconds
Started Jun 13 01:51:47 PM PDT 24
Finished Jun 13 01:51:52 PM PDT 24
Peak memory 218212 kb
Host smart-594ed196-08d3-4aaf-959b-76dc90412dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083339837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3083339837
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_regwen.2837398668
Short name T30
Test name
Test status
Simulation time 74092842 ps
CPU time 0.89 seconds
Started Jun 13 01:49:04 PM PDT 24
Finished Jun 13 01:49:05 PM PDT 24
Peak memory 206280 kb
Host smart-e3c6138b-f1f5-487c-a14b-cf470daf5360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837398668 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2837398668
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/98.edn_alert.3180200154
Short name T122
Test name
Test status
Simulation time 101984339 ps
CPU time 1.23 seconds
Started Jun 13 01:51:04 PM PDT 24
Finished Jun 13 01:51:07 PM PDT 24
Peak memory 217936 kb
Host smart-731f6a97-f93a-4d95-88fa-c661e83990c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180200154 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.3180200154
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1646657991
Short name T286
Test name
Test status
Simulation time 117986003 ps
CPU time 2.94 seconds
Started Jun 13 02:40:49 PM PDT 24
Finished Jun 13 02:40:58 PM PDT 24
Peak memory 206792 kb
Host smart-d869f888-f0ff-45b5-b3d7-4674232ab674
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646657991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1646657991
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/65.edn_alert.927750414
Short name T102
Test name
Test status
Simulation time 73697088 ps
CPU time 1.26 seconds
Started Jun 13 01:50:51 PM PDT 24
Finished Jun 13 01:50:54 PM PDT 24
Peak memory 215052 kb
Host smart-8d01c846-19ee-4dda-9876-8df748788876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927750414 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.927750414
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2848700979
Short name T143
Test name
Test status
Simulation time 114076857 ps
CPU time 1.29 seconds
Started Jun 13 01:48:53 PM PDT 24
Finished Jun 13 01:48:55 PM PDT 24
Peak memory 216312 kb
Host smart-40056315-b510-4e19-96f4-7d581da4a8c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848700979 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2848700979
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_disable.2823505908
Short name T33
Test name
Test status
Simulation time 94408152 ps
CPU time 0.91 seconds
Started Jun 13 01:49:42 PM PDT 24
Finished Jun 13 01:49:43 PM PDT 24
Peak memory 215676 kb
Host smart-30b8680a-fabd-4950-a378-688c0c0bbc01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823505908 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2823505908
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/184.edn_alert.2937983051
Short name T110
Test name
Test status
Simulation time 22629102 ps
CPU time 1.37 seconds
Started Jun 13 01:51:45 PM PDT 24
Finished Jun 13 01:51:49 PM PDT 24
Peak memory 218968 kb
Host smart-8b1a4d19-ba27-469d-8f8c-f0bf8bfc0cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937983051 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.2937983051
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/30.edn_err.3406826488
Short name T160
Test name
Test status
Simulation time 48786886 ps
CPU time 0.92 seconds
Started Jun 13 01:50:02 PM PDT 24
Finished Jun 13 01:50:05 PM PDT 24
Peak memory 217956 kb
Host smart-4ede7d06-df66-446e-86cb-a40f6d515c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406826488 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3406826488
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/0.edn_disable.924469330
Short name T198
Test name
Test status
Simulation time 38497529 ps
CPU time 0.87 seconds
Started Jun 13 01:48:49 PM PDT 24
Finished Jun 13 01:48:51 PM PDT 24
Peak memory 215652 kb
Host smart-017d8c35-df71-44b7-a3b5-9a6a21c5674b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924469330 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.924469330
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable.201767362
Short name T211
Test name
Test status
Simulation time 40505857 ps
CPU time 0.89 seconds
Started Jun 13 01:49:27 PM PDT 24
Finished Jun 13 01:49:29 PM PDT 24
Peak memory 215664 kb
Host smart-3b5824d9-d659-438e-81b3-49974facf7ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201767362 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.201767362
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.960591443
Short name T254
Test name
Test status
Simulation time 51102781 ps
CPU time 1.19 seconds
Started Jun 13 02:40:36 PM PDT 24
Finished Jun 13 02:40:43 PM PDT 24
Peak memory 206372 kb
Host smart-eae0efdd-42b9-4d3b-9518-ff3bc57da972
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960591443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.960591443
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/default/134.edn_alert.4126170372
Short name T290
Test name
Test status
Simulation time 100049062 ps
CPU time 1.24 seconds
Started Jun 13 01:51:24 PM PDT 24
Finished Jun 13 01:51:27 PM PDT 24
Peak memory 218704 kb
Host smart-3684a90b-c16b-4488-8da8-29f50bbc4c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126170372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.4126170372
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/151.edn_alert.1581077433
Short name T273
Test name
Test status
Simulation time 100811553 ps
CPU time 1.13 seconds
Started Jun 13 01:51:35 PM PDT 24
Finished Jun 13 01:51:37 PM PDT 24
Peak memory 219976 kb
Host smart-845dacf7-07b1-46b3-9210-87174161a878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581077433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1581077433
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/100.edn_alert.103666865
Short name T25
Test name
Test status
Simulation time 39277354 ps
CPU time 1.24 seconds
Started Jun 13 01:51:03 PM PDT 24
Finished Jun 13 01:51:06 PM PDT 24
Peak memory 218216 kb
Host smart-297f9f2a-3c51-49df-a787-c4806f55da8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103666865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.103666865
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.2045637790
Short name T306
Test name
Test status
Simulation time 220235090 ps
CPU time 1.41 seconds
Started Jun 13 01:51:18 PM PDT 24
Finished Jun 13 01:51:20 PM PDT 24
Peak memory 218164 kb
Host smart-12c85128-6179-48b8-9e09-fcefbab73651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045637790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2045637790
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2250180580
Short name T100
Test name
Test status
Simulation time 50403552 ps
CPU time 1.23 seconds
Started Jun 13 01:49:22 PM PDT 24
Finished Jun 13 01:49:24 PM PDT 24
Peak memory 218096 kb
Host smart-395a5d62-2830-492b-8bfe-25a69afd6be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250180580 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2250180580
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/118.edn_alert.1657975632
Short name T237
Test name
Test status
Simulation time 31446353 ps
CPU time 1.36 seconds
Started Jun 13 01:51:24 PM PDT 24
Finished Jun 13 01:51:27 PM PDT 24
Peak memory 219876 kb
Host smart-205ad5d1-6aad-4aab-8905-8fffaa34895b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657975632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1657975632
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1053931861
Short name T1
Test name
Test status
Simulation time 242095688 ps
CPU time 1.15 seconds
Started Jun 13 01:49:20 PM PDT 24
Finished Jun 13 01:49:23 PM PDT 24
Peak memory 219200 kb
Host smart-8b5de4e9-2f07-468f-9889-54d9aa8bcb87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053931861 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1053931861
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/121.edn_alert.3677905392
Short name T711
Test name
Test status
Simulation time 29152561 ps
CPU time 1.32 seconds
Started Jun 13 01:51:22 PM PDT 24
Finished Jun 13 01:51:24 PM PDT 24
Peak memory 218904 kb
Host smart-fe3fb7e5-9f1b-4fcd-a862-7080c9b44901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677905392 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3677905392
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/131.edn_alert.2538890282
Short name T191
Test name
Test status
Simulation time 30990443 ps
CPU time 1.42 seconds
Started Jun 13 01:51:25 PM PDT 24
Finished Jun 13 01:51:28 PM PDT 24
Peak memory 215064 kb
Host smart-33b4920b-cb3e-4f4c-ba1e-482c25e1a065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538890282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.2538890282
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/196.edn_alert.1109237052
Short name T172
Test name
Test status
Simulation time 48532962 ps
CPU time 1.24 seconds
Started Jun 13 01:51:56 PM PDT 24
Finished Jun 13 01:51:58 PM PDT 24
Peak memory 219160 kb
Host smart-919f38da-b868-45ed-b44e-389fa8ce79b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109237052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.1109237052
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/28.edn_intr.3399635999
Short name T91
Test name
Test status
Simulation time 21161824 ps
CPU time 1.12 seconds
Started Jun 13 01:49:55 PM PDT 24
Finished Jun 13 01:49:58 PM PDT 24
Peak memory 215084 kb
Host smart-aed75796-d9e5-4821-afc8-4ba0973457e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399635999 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3399635999
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/236.edn_genbits.3435671466
Short name T313
Test name
Test status
Simulation time 54311155 ps
CPU time 1.33 seconds
Started Jun 13 01:52:03 PM PDT 24
Finished Jun 13 01:52:05 PM PDT 24
Peak memory 219308 kb
Host smart-4203db09-1cf3-4b93-8534-d09bf955dc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435671466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3435671466
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.2190956393
Short name T513
Test name
Test status
Simulation time 21518815 ps
CPU time 1.14 seconds
Started Jun 13 01:51:45 PM PDT 24
Finished Jun 13 01:51:49 PM PDT 24
Peak memory 218276 kb
Host smart-0c660ae3-06fd-45c1-9794-3333d6dcfc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190956393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.2190956393
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/3.edn_intr.3648744748
Short name T38
Test name
Test status
Simulation time 43467524 ps
CPU time 0.86 seconds
Started Jun 13 01:48:55 PM PDT 24
Finished Jun 13 01:48:58 PM PDT 24
Peak memory 214772 kb
Host smart-2dc017f0-beb6-44b4-90d7-a94da012415e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648744748 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3648744748
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/1.edn_alert.1992691355
Short name T758
Test name
Test status
Simulation time 25798781 ps
CPU time 1.14 seconds
Started Jun 13 01:48:50 PM PDT 24
Finished Jun 13 01:48:52 PM PDT 24
Peak memory 217744 kb
Host smart-caf11a11-922b-409e-b718-de6331cd4f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992691355 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1992691355
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.882366024
Short name T462
Test name
Test status
Simulation time 37803005 ps
CPU time 1.05 seconds
Started Jun 13 01:48:51 PM PDT 24
Finished Jun 13 01:48:53 PM PDT 24
Peak memory 217676 kb
Host smart-3d2bb975-df69-4211-b45f-9840b495b03d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882366024 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_dis
able_auto_req_mode.882366024
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_disable.175765392
Short name T207
Test name
Test status
Simulation time 35113077 ps
CPU time 0.85 seconds
Started Jun 13 01:49:12 PM PDT 24
Finished Jun 13 01:49:14 PM PDT 24
Peak memory 215760 kb
Host smart-0ae21dfb-01b0-44bc-91a6-1c34ca5d8ebc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175765392 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.175765392
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/125.edn_alert.3951502709
Short name T128
Test name
Test status
Simulation time 86668582 ps
CPU time 1.22 seconds
Started Jun 13 01:51:23 PM PDT 24
Finished Jun 13 01:51:25 PM PDT 24
Peak memory 219044 kb
Host smart-eb78df69-b26c-41ff-b3ac-559048779bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951502709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.3951502709
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1716421824
Short name T142
Test name
Test status
Simulation time 38096094 ps
CPU time 1.31 seconds
Started Jun 13 01:49:27 PM PDT 24
Finished Jun 13 01:49:29 PM PDT 24
Peak memory 216156 kb
Host smart-b2939655-e777-468f-903e-08f09e08c246
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716421824 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1716421824
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3822311044
Short name T77
Test name
Test status
Simulation time 20022179 ps
CPU time 1.1 seconds
Started Jun 13 01:49:26 PM PDT 24
Finished Jun 13 01:49:27 PM PDT 24
Peak memory 217852 kb
Host smart-3b82c487-99b8-4ff0-a98d-b040edd9281f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822311044 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3822311044
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2089462837
Short name T23
Test name
Test status
Simulation time 29221938 ps
CPU time 1.16 seconds
Started Jun 13 01:49:40 PM PDT 24
Finished Jun 13 01:49:42 PM PDT 24
Peak memory 216268 kb
Host smart-91739fcf-7133-49af-abc9-a893ed4f2bb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089462837 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2089462837
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_disable.4130848266
Short name T641
Test name
Test status
Simulation time 40611187 ps
CPU time 0.84 seconds
Started Jun 13 01:49:43 PM PDT 24
Finished Jun 13 01:49:45 PM PDT 24
Peak memory 214776 kb
Host smart-32bd108f-4f56-491e-9659-606a2f2863ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130848266 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.4130848266
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable.4237712778
Short name T212
Test name
Test status
Simulation time 34012793 ps
CPU time 0.88 seconds
Started Jun 13 01:50:00 PM PDT 24
Finished Jun 13 01:50:04 PM PDT 24
Peak memory 215668 kb
Host smart-a707b8fd-82f8-4800-b3e0-95cfd59f7c7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237712778 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.4237712778
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3450750151
Short name T202
Test name
Test status
Simulation time 73668217 ps
CPU time 1.04 seconds
Started Jun 13 01:50:04 PM PDT 24
Finished Jun 13 01:50:07 PM PDT 24
Peak memory 216260 kb
Host smart-10f590db-e2ee-48c0-ad65-4d9ebf22fd6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450750151 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3450750151
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1513881666
Short name T874
Test name
Test status
Simulation time 22700600 ps
CPU time 0.95 seconds
Started Jun 13 01:50:12 PM PDT 24
Finished Jun 13 01:50:16 PM PDT 24
Peak memory 218984 kb
Host smart-f07fbea2-cf12-45d2-9a69-8f9ffc4e2fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513881666 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1513881666
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/6.edn_disable.2551322708
Short name T188
Test name
Test status
Simulation time 11293840 ps
CPU time 0.9 seconds
Started Jun 13 01:49:06 PM PDT 24
Finished Jun 13 01:49:08 PM PDT 24
Peak memory 215616 kb
Host smart-424e3146-f9f7-4c1d-9b37-e8a8bbe03278
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551322708 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2551322708
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/10.edn_alert_test.2219943280
Short name T68
Test name
Test status
Simulation time 54518910 ps
CPU time 0.83 seconds
Started Jun 13 01:49:10 PM PDT 24
Finished Jun 13 01:49:12 PM PDT 24
Peak memory 214552 kb
Host smart-1b2dffff-85e6-409f-828d-765dd0b08cc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219943280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2219943280
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_genbits.2089973279
Short name T28
Test name
Test status
Simulation time 39523980 ps
CPU time 1.42 seconds
Started Jun 13 01:49:57 PM PDT 24
Finished Jun 13 01:50:00 PM PDT 24
Peak memory 217952 kb
Host smart-29d24dee-951c-41d6-8d40-27419e4806e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089973279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2089973279
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.1072527195
Short name T311
Test name
Test status
Simulation time 41286306 ps
CPU time 1.28 seconds
Started Jun 13 01:51:20 PM PDT 24
Finished Jun 13 01:51:22 PM PDT 24
Peak memory 217904 kb
Host smart-71b6f34f-f5be-4049-9a48-3647e8e08ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072527195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1072527195
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.1942103914
Short name T327
Test name
Test status
Simulation time 66484763 ps
CPU time 1.37 seconds
Started Jun 13 01:51:43 PM PDT 24
Finished Jun 13 01:51:47 PM PDT 24
Peak memory 219372 kb
Host smart-0a46c89b-5b8e-4490-bb33-7016d04c4162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942103914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1942103914
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.2162408504
Short name T76
Test name
Test status
Simulation time 40382172 ps
CPU time 1.64 seconds
Started Jun 13 01:51:56 PM PDT 24
Finished Jun 13 01:51:58 PM PDT 24
Peak memory 217768 kb
Host smart-72641295-5626-4a6d-8037-9752318a8382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162408504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2162408504
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_genbits.2838219178
Short name T323
Test name
Test status
Simulation time 64234599 ps
CPU time 2.37 seconds
Started Jun 13 01:49:44 PM PDT 24
Finished Jun 13 01:49:47 PM PDT 24
Peak memory 219472 kb
Host smart-349ca709-117c-4a02-9962-6a27e68ac16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838219178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2838219178
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2714567809
Short name T92
Test name
Test status
Simulation time 44107194 ps
CPU time 0.9 seconds
Started Jun 13 01:49:34 PM PDT 24
Finished Jun 13 01:49:36 PM PDT 24
Peak memory 214988 kb
Host smart-d912b604-942b-4fca-a203-6d2a92429b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714567809 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2714567809
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/153.edn_alert.1068272350
Short name T403
Test name
Test status
Simulation time 176548499 ps
CPU time 1.17 seconds
Started Jun 13 01:51:40 PM PDT 24
Finished Jun 13 01:51:43 PM PDT 24
Peak memory 219820 kb
Host smart-5dab7b01-b1e7-48f8-9fba-8da501bcb48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068272350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1068272350
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/11.edn_genbits.734391848
Short name T14
Test name
Test status
Simulation time 28286934 ps
CPU time 1.3 seconds
Started Jun 13 01:49:18 PM PDT 24
Finished Jun 13 01:49:21 PM PDT 24
Peak memory 219464 kb
Host smart-6e6ee748-d3d7-44ff-aa58-78391e52f87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734391848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.734391848
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2398926521
Short name T261
Test name
Test status
Simulation time 22406611 ps
CPU time 0.91 seconds
Started Jun 13 02:40:32 PM PDT 24
Finished Jun 13 02:40:38 PM PDT 24
Peak memory 206344 kb
Host smart-5d18f943-7def-42ee-90d3-bd35c9b58a89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398926521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2398926521
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/default/113.edn_genbits.3797141936
Short name T44
Test name
Test status
Simulation time 92942375 ps
CPU time 1.22 seconds
Started Jun 13 01:51:20 PM PDT 24
Finished Jun 13 01:51:22 PM PDT 24
Peak memory 216784 kb
Host smart-73715808-5097-40cd-ab98-7ce10aae1b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797141936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3797141936
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.309558758
Short name T326
Test name
Test status
Simulation time 42311891 ps
CPU time 1.78 seconds
Started Jun 13 01:51:17 PM PDT 24
Finished Jun 13 01:51:20 PM PDT 24
Peak memory 217816 kb
Host smart-fa15637b-d152-445e-811c-42dd1dbb3b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309558758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.309558758
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.2951567445
Short name T890
Test name
Test status
Simulation time 97908886 ps
CPU time 1.21 seconds
Started Jun 13 01:51:29 PM PDT 24
Finished Jun 13 01:51:31 PM PDT 24
Peak memory 216680 kb
Host smart-fb3dbada-0b3c-4cb4-8964-a3f3b5978e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951567445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2951567445
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_stress_all.2322706343
Short name T303
Test name
Test status
Simulation time 307035479 ps
CPU time 6.08 seconds
Started Jun 13 01:49:19 PM PDT 24
Finished Jun 13 01:49:27 PM PDT 24
Peak memory 217956 kb
Host smart-87d60368-f8da-418f-b35f-230875f74ec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322706343 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2322706343
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/150.edn_genbits.2282948189
Short name T319
Test name
Test status
Simulation time 50282518 ps
CPU time 1.1 seconds
Started Jun 13 01:51:35 PM PDT 24
Finished Jun 13 01:51:38 PM PDT 24
Peak memory 217912 kb
Host smart-87fc1a0c-f45e-4720-b70d-76ec2fd59700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282948189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2282948189
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.1711662713
Short name T312
Test name
Test status
Simulation time 169101880 ps
CPU time 1.15 seconds
Started Jun 13 01:51:52 PM PDT 24
Finished Jun 13 01:51:54 PM PDT 24
Peak memory 219520 kb
Host smart-fb08d772-f631-4a27-ab0d-63a39eaaab79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711662713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1711662713
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2286958108
Short name T12
Test name
Test status
Simulation time 86076495 ps
CPU time 1.23 seconds
Started Jun 13 01:51:50 PM PDT 24
Finished Jun 13 01:51:53 PM PDT 24
Peak memory 214592 kb
Host smart-13cab551-801f-43fa-aaa1-151da1708dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286958108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2286958108
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2240951378
Short name T35
Test name
Test status
Simulation time 22826833 ps
CPU time 1.03 seconds
Started Jun 13 01:50:28 PM PDT 24
Finished Jun 13 01:50:30 PM PDT 24
Peak memory 214996 kb
Host smart-672c99da-3d5a-4286-8b75-1d12781469b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240951378 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2240951378
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/105.edn_genbits.373427077
Short name T336
Test name
Test status
Simulation time 54090729 ps
CPU time 1.5 seconds
Started Jun 13 01:51:10 PM PDT 24
Finished Jun 13 01:51:13 PM PDT 24
Peak memory 218044 kb
Host smart-b11efa7c-c7b0-4ef9-9a7c-059f9ad54032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373427077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.373427077
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3947887092
Short name T359
Test name
Test status
Simulation time 47518776 ps
CPU time 1.71 seconds
Started Jun 13 01:51:23 PM PDT 24
Finished Jun 13 01:51:26 PM PDT 24
Peak memory 219328 kb
Host smart-ab54558c-e428-48e1-89b9-a6ac5a1c4085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947887092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3947887092
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_err.2489004660
Short name T135
Test name
Test status
Simulation time 31962329 ps
CPU time 0.94 seconds
Started Jun 13 01:49:22 PM PDT 24
Finished Jun 13 01:49:24 PM PDT 24
Peak memory 217824 kb
Host smart-e88fc971-6a87-4f2f-8d54-08752d637e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489004660 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2489004660
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3827222127
Short name T1081
Test name
Test status
Simulation time 46472363 ps
CPU time 1.2 seconds
Started Jun 13 02:40:32 PM PDT 24
Finished Jun 13 02:40:38 PM PDT 24
Peak memory 206336 kb
Host smart-61dc3e9a-5147-4807-bb2d-4110fa6c3b06
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827222127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3827222127
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2329722758
Short name T260
Test name
Test status
Simulation time 113272023 ps
CPU time 3.26 seconds
Started Jun 13 02:40:26 PM PDT 24
Finished Jun 13 02:40:33 PM PDT 24
Peak memory 206332 kb
Host smart-73ea1c39-82e4-4f0d-9ad1-b76107b3b6c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329722758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2329722758
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2842917688
Short name T1049
Test name
Test status
Simulation time 77974003 ps
CPU time 0.91 seconds
Started Jun 13 02:40:26 PM PDT 24
Finished Jun 13 02:40:31 PM PDT 24
Peak memory 206332 kb
Host smart-d9ff3c90-0248-4240-8f42-91a1c325f25b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842917688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2842917688
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1846045938
Short name T1103
Test name
Test status
Simulation time 293888006 ps
CPU time 1.37 seconds
Started Jun 13 02:40:27 PM PDT 24
Finished Jun 13 02:40:33 PM PDT 24
Peak memory 214664 kb
Host smart-a6ee7585-574c-477c-9034-da76d1c0ad81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846045938 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1846045938
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3070028697
Short name T1090
Test name
Test status
Simulation time 32453858 ps
CPU time 0.8 seconds
Started Jun 13 02:40:25 PM PDT 24
Finished Jun 13 02:40:30 PM PDT 24
Peak memory 206220 kb
Host smart-b92ca0f1-f65f-4065-bc78-5197256de2c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070028697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3070028697
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.567940753
Short name T1042
Test name
Test status
Simulation time 60020316 ps
CPU time 0.94 seconds
Started Jun 13 02:40:27 PM PDT 24
Finished Jun 13 02:40:32 PM PDT 24
Peak memory 206348 kb
Host smart-3e3a8525-8522-4246-9165-84662ee5c139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567940753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.567940753
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2743520987
Short name T1098
Test name
Test status
Simulation time 20583880 ps
CPU time 1.21 seconds
Started Jun 13 02:40:32 PM PDT 24
Finished Jun 13 02:40:38 PM PDT 24
Peak memory 206400 kb
Host smart-cb6c5ca1-36fd-40ca-86fc-048361404192
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743520987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2743520987
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.159985682
Short name T1083
Test name
Test status
Simulation time 74811925 ps
CPU time 2.67 seconds
Started Jun 13 02:40:24 PM PDT 24
Finished Jun 13 02:40:30 PM PDT 24
Peak memory 214824 kb
Host smart-0a038073-0482-4d04-99fb-a17a56d040c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159985682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.159985682
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1643356354
Short name T277
Test name
Test status
Simulation time 157710623 ps
CPU time 1.42 seconds
Started Jun 13 02:40:26 PM PDT 24
Finished Jun 13 02:40:31 PM PDT 24
Peak memory 206652 kb
Host smart-e82aafb4-76cd-4fe8-aa84-3331ca14747c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643356354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1643356354
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2940112450
Short name T1115
Test name
Test status
Simulation time 478261742 ps
CPU time 3.37 seconds
Started Jun 13 02:40:31 PM PDT 24
Finished Jun 13 02:40:39 PM PDT 24
Peak memory 206356 kb
Host smart-a37f69f3-a54d-4afd-9295-91591bda859f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940112450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2940112450
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3163862455
Short name T1015
Test name
Test status
Simulation time 20539911 ps
CPU time 1.06 seconds
Started Jun 13 02:40:25 PM PDT 24
Finished Jun 13 02:40:29 PM PDT 24
Peak memory 206340 kb
Host smart-e18bd328-c257-43a2-9896-5fe49ed8bbd8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163862455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3163862455
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1353554802
Short name T1101
Test name
Test status
Simulation time 18490601 ps
CPU time 1.05 seconds
Started Jun 13 02:40:31 PM PDT 24
Finished Jun 13 02:40:37 PM PDT 24
Peak memory 214660 kb
Host smart-90ba0627-1b44-4242-b6ad-18db07ff9b18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353554802 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1353554802
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.352887459
Short name T1068
Test name
Test status
Simulation time 56389588 ps
CPU time 0.92 seconds
Started Jun 13 02:40:25 PM PDT 24
Finished Jun 13 02:40:30 PM PDT 24
Peak memory 206324 kb
Host smart-19dabb53-b768-4523-a629-e91b9e49fa19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352887459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.352887459
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.4144428674
Short name T264
Test name
Test status
Simulation time 60471799 ps
CPU time 0.96 seconds
Started Jun 13 02:40:35 PM PDT 24
Finished Jun 13 02:40:42 PM PDT 24
Peak memory 206404 kb
Host smart-320a692a-94d4-4223-9c58-a8fb85195c43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144428674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.4144428674
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.913017811
Short name T1037
Test name
Test status
Simulation time 946964510 ps
CPU time 3.4 seconds
Started Jun 13 02:40:30 PM PDT 24
Finished Jun 13 02:40:38 PM PDT 24
Peak memory 214836 kb
Host smart-1b2fd808-aab7-4794-9c6d-966ee930d3d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913017811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.913017811
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.943904542
Short name T279
Test name
Test status
Simulation time 102014597 ps
CPU time 2.29 seconds
Started Jun 13 02:40:28 PM PDT 24
Finished Jun 13 02:40:34 PM PDT 24
Peak memory 214644 kb
Host smart-39a10c5a-4cd6-49ca-b541-2fd7497fa7db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943904542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.943904542
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3001370968
Short name T1096
Test name
Test status
Simulation time 74045897 ps
CPU time 1.17 seconds
Started Jun 13 02:40:40 PM PDT 24
Finished Jun 13 02:40:46 PM PDT 24
Peak memory 214632 kb
Host smart-c65b8106-07ee-4e35-86ad-5e25ee00470d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001370968 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3001370968
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1061540939
Short name T252
Test name
Test status
Simulation time 26442940 ps
CPU time 0.9 seconds
Started Jun 13 02:40:45 PM PDT 24
Finished Jun 13 02:40:50 PM PDT 24
Peak memory 206332 kb
Host smart-13ea8112-9fb5-4156-8926-9210c4781422
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061540939 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1061540939
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3142282092
Short name T1074
Test name
Test status
Simulation time 64426127 ps
CPU time 0.75 seconds
Started Jun 13 02:40:46 PM PDT 24
Finished Jun 13 02:40:52 PM PDT 24
Peak memory 206188 kb
Host smart-84593228-2eb4-4d2c-9b12-dc10d477d786
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142282092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3142282092
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1656179754
Short name T1069
Test name
Test status
Simulation time 73329979 ps
CPU time 1.14 seconds
Started Jun 13 02:40:48 PM PDT 24
Finished Jun 13 02:40:54 PM PDT 24
Peak memory 206360 kb
Host smart-0aae871e-57cd-470d-9d50-a4405572fd8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656179754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1656179754
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3793609042
Short name T1051
Test name
Test status
Simulation time 183469208 ps
CPU time 3.6 seconds
Started Jun 13 02:40:41 PM PDT 24
Finished Jun 13 02:40:49 PM PDT 24
Peak memory 214700 kb
Host smart-b2fdc3ee-3862-45b5-8ca1-f403b99cadf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793609042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3793609042
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.992380636
Short name T288
Test name
Test status
Simulation time 134268078 ps
CPU time 1.53 seconds
Started Jun 13 02:40:38 PM PDT 24
Finished Jun 13 02:40:45 PM PDT 24
Peak memory 206408 kb
Host smart-737fdef1-5096-4b7b-9f29-72c4f705b9a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992380636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.992380636
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2980305301
Short name T1122
Test name
Test status
Simulation time 59676792 ps
CPU time 1.05 seconds
Started Jun 13 02:40:49 PM PDT 24
Finished Jun 13 02:40:56 PM PDT 24
Peak memory 216012 kb
Host smart-503bb67a-a8b1-4e4b-96ce-c784574a5708
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980305301 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2980305301
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1668473560
Short name T255
Test name
Test status
Simulation time 16853833 ps
CPU time 0.98 seconds
Started Jun 13 02:40:37 PM PDT 24
Finished Jun 13 02:40:43 PM PDT 24
Peak memory 206336 kb
Host smart-e8635273-be5e-4b3d-98bf-25e8cfe6db6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668473560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1668473560
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.500557203
Short name T1054
Test name
Test status
Simulation time 11824262 ps
CPU time 0.85 seconds
Started Jun 13 02:40:48 PM PDT 24
Finished Jun 13 02:40:54 PM PDT 24
Peak memory 206304 kb
Host smart-9e72ec74-77aa-4dad-994c-12316c5cacfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500557203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.500557203
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1037066294
Short name T1092
Test name
Test status
Simulation time 24986153 ps
CPU time 1.17 seconds
Started Jun 13 02:40:37 PM PDT 24
Finished Jun 13 02:40:44 PM PDT 24
Peak memory 206492 kb
Host smart-8074dd0a-e5ab-476d-8861-24c39f9a32d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037066294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1037066294
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.498328965
Short name T1001
Test name
Test status
Simulation time 223582343 ps
CPU time 3.57 seconds
Started Jun 13 02:40:40 PM PDT 24
Finished Jun 13 02:40:49 PM PDT 24
Peak memory 214948 kb
Host smart-51e33197-0e2c-4c8e-bd04-6bd096dd9f29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498328965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.498328965
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1958686045
Short name T284
Test name
Test status
Simulation time 148965300 ps
CPU time 1.57 seconds
Started Jun 13 02:40:38 PM PDT 24
Finished Jun 13 02:40:45 PM PDT 24
Peak memory 206404 kb
Host smart-f3bef25c-1285-4d96-8432-bf09661ccc44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958686045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1958686045
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3600182369
Short name T1118
Test name
Test status
Simulation time 34442465 ps
CPU time 1.52 seconds
Started Jun 13 02:40:42 PM PDT 24
Finished Jun 13 02:40:48 PM PDT 24
Peak memory 214616 kb
Host smart-a3b11bde-aeb3-4607-bb56-020ba62a4b62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600182369 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3600182369
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2023225247
Short name T1113
Test name
Test status
Simulation time 45538441 ps
CPU time 0.87 seconds
Started Jun 13 02:40:48 PM PDT 24
Finished Jun 13 02:40:54 PM PDT 24
Peak memory 206248 kb
Host smart-7e95e74a-5c20-45f0-8fce-fa3330f5f788
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023225247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2023225247
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2015828075
Short name T1008
Test name
Test status
Simulation time 13102002 ps
CPU time 0.86 seconds
Started Jun 13 02:40:43 PM PDT 24
Finished Jun 13 02:40:48 PM PDT 24
Peak memory 206348 kb
Host smart-a60a15e8-aa9a-4699-9610-fd7328dee99d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015828075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2015828075
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1782450418
Short name T267
Test name
Test status
Simulation time 43222130 ps
CPU time 1.13 seconds
Started Jun 13 02:40:45 PM PDT 24
Finished Jun 13 02:40:50 PM PDT 24
Peak memory 206336 kb
Host smart-dcbdc1c0-15df-419f-9191-07cf885e9361
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782450418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1782450418
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3010475491
Short name T1014
Test name
Test status
Simulation time 239524847 ps
CPU time 2.92 seconds
Started Jun 13 02:40:37 PM PDT 24
Finished Jun 13 02:40:45 PM PDT 24
Peak memory 214700 kb
Host smart-9df99ce2-8ae6-4a42-9df7-eb6cff7c4140
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010475491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3010475491
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3513975591
Short name T1039
Test name
Test status
Simulation time 78411920 ps
CPU time 2.01 seconds
Started Jun 13 02:40:39 PM PDT 24
Finished Jun 13 02:40:47 PM PDT 24
Peak memory 206508 kb
Host smart-c5cd8ae0-2ea4-468b-82a9-dd006090db51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513975591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3513975591
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1255890482
Short name T1013
Test name
Test status
Simulation time 31589596 ps
CPU time 0.94 seconds
Started Jun 13 02:40:49 PM PDT 24
Finished Jun 13 02:40:56 PM PDT 24
Peak memory 206464 kb
Host smart-04880c66-71cd-4b5d-bdae-4b5dbbd3ebd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255890482 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1255890482
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3622331318
Short name T266
Test name
Test status
Simulation time 11391616 ps
CPU time 0.87 seconds
Started Jun 13 02:40:37 PM PDT 24
Finished Jun 13 02:40:44 PM PDT 24
Peak memory 206332 kb
Host smart-6181e4dd-1720-43c1-aea4-251453fd5d49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622331318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3622331318
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3577227639
Short name T1086
Test name
Test status
Simulation time 32750184 ps
CPU time 0.86 seconds
Started Jun 13 02:40:40 PM PDT 24
Finished Jun 13 02:40:46 PM PDT 24
Peak memory 206332 kb
Host smart-e691b2ff-b7aa-431f-b68f-c7bba3f4dab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577227639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3577227639
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2340382313
Short name T263
Test name
Test status
Simulation time 45265158 ps
CPU time 1.12 seconds
Started Jun 13 02:40:38 PM PDT 24
Finished Jun 13 02:40:44 PM PDT 24
Peak memory 206432 kb
Host smart-37c1fd93-320f-4354-bcfc-6eef09a279c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340382313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2340382313
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.104935657
Short name T1128
Test name
Test status
Simulation time 136657970 ps
CPU time 1.87 seconds
Started Jun 13 02:40:48 PM PDT 24
Finished Jun 13 02:40:55 PM PDT 24
Peak memory 214136 kb
Host smart-7f31d083-d3a1-4b1f-8258-6e173c6fce27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104935657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.104935657
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3159431169
Short name T1123
Test name
Test status
Simulation time 166665898 ps
CPU time 2.41 seconds
Started Jun 13 02:40:48 PM PDT 24
Finished Jun 13 02:40:56 PM PDT 24
Peak memory 214692 kb
Host smart-168f9202-1d6b-453c-85b3-b0971e47122f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159431169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3159431169
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1654074687
Short name T1117
Test name
Test status
Simulation time 60316806 ps
CPU time 1.01 seconds
Started Jun 13 02:40:51 PM PDT 24
Finished Jun 13 02:40:58 PM PDT 24
Peak memory 206468 kb
Host smart-4dcf7789-8285-4ec5-a4a8-d90fa225b0f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654074687 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1654074687
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.4101887336
Short name T1018
Test name
Test status
Simulation time 71482635 ps
CPU time 0.85 seconds
Started Jun 13 02:40:47 PM PDT 24
Finished Jun 13 02:40:53 PM PDT 24
Peak memory 206296 kb
Host smart-5483a825-f221-424a-b9d1-208742af2154
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101887336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.4101887336
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.792797285
Short name T1114
Test name
Test status
Simulation time 21061708 ps
CPU time 0.81 seconds
Started Jun 13 02:40:47 PM PDT 24
Finished Jun 13 02:40:54 PM PDT 24
Peak memory 206212 kb
Host smart-03f39a35-3b5b-4c73-aad9-16372bc44316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792797285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.792797285
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.418058559
Short name T1107
Test name
Test status
Simulation time 36779635 ps
CPU time 0.86 seconds
Started Jun 13 02:40:46 PM PDT 24
Finished Jun 13 02:40:51 PM PDT 24
Peak memory 206364 kb
Host smart-796ab302-165b-481a-9e21-c9539ce15b9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418058559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.418058559
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.503181656
Short name T1121
Test name
Test status
Simulation time 63724333 ps
CPU time 1.73 seconds
Started Jun 13 02:40:43 PM PDT 24
Finished Jun 13 02:40:49 PM PDT 24
Peak memory 214668 kb
Host smart-033fa81f-c458-4abe-985a-ee214c205b28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503181656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.503181656
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1327260108
Short name T1104
Test name
Test status
Simulation time 74399861 ps
CPU time 2.12 seconds
Started Jun 13 02:40:41 PM PDT 24
Finished Jun 13 02:40:48 PM PDT 24
Peak memory 214688 kb
Host smart-a0bb40bf-aae6-41f8-87cb-bd65ab0a14db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327260108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1327260108
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3349426638
Short name T1046
Test name
Test status
Simulation time 19392362 ps
CPU time 1.08 seconds
Started Jun 13 02:40:48 PM PDT 24
Finished Jun 13 02:40:54 PM PDT 24
Peak memory 214656 kb
Host smart-ea5fe6af-a037-4fcf-b6a7-cd08e148d57b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349426638 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3349426638
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3901930709
Short name T1062
Test name
Test status
Simulation time 63275432 ps
CPU time 0.82 seconds
Started Jun 13 02:40:38 PM PDT 24
Finished Jun 13 02:40:44 PM PDT 24
Peak memory 206232 kb
Host smart-b963e533-ecea-41ae-bbb6-4ac7f41b6293
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901930709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3901930709
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2192158504
Short name T1017
Test name
Test status
Simulation time 18956950 ps
CPU time 0.82 seconds
Started Jun 13 02:40:38 PM PDT 24
Finished Jun 13 02:40:44 PM PDT 24
Peak memory 206252 kb
Host smart-5b4be358-9ed3-4caf-ae8d-c6438cf58903
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192158504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2192158504
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.592934303
Short name T1050
Test name
Test status
Simulation time 62175793 ps
CPU time 1.08 seconds
Started Jun 13 02:40:42 PM PDT 24
Finished Jun 13 02:40:48 PM PDT 24
Peak memory 206328 kb
Host smart-0ac6b59f-cc55-4292-b995-a876464748e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592934303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.592934303
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3056295181
Short name T998
Test name
Test status
Simulation time 116461646 ps
CPU time 2.98 seconds
Started Jun 13 02:40:43 PM PDT 24
Finished Jun 13 02:40:50 PM PDT 24
Peak memory 214676 kb
Host smart-c8bb90ac-2721-4992-a585-bad2613273d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056295181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3056295181
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1447118135
Short name T1105
Test name
Test status
Simulation time 96534230 ps
CPU time 1.61 seconds
Started Jun 13 02:40:39 PM PDT 24
Finished Jun 13 02:40:46 PM PDT 24
Peak memory 214596 kb
Host smart-bd60a99f-b2c8-4929-bc93-ab9c8a229c52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447118135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1447118135
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2429958725
Short name T1011
Test name
Test status
Simulation time 25643185 ps
CPU time 1.28 seconds
Started Jun 13 02:40:39 PM PDT 24
Finished Jun 13 02:40:46 PM PDT 24
Peak memory 214680 kb
Host smart-1665752c-8db5-45fa-b305-4dc86f69fd38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429958725 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2429958725
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.4017881585
Short name T262
Test name
Test status
Simulation time 43786815 ps
CPU time 1.32 seconds
Started Jun 13 02:40:46 PM PDT 24
Finished Jun 13 02:40:52 PM PDT 24
Peak memory 205252 kb
Host smart-884c6bab-e797-42f1-b782-7e9c9da70124
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017881585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.4017881585
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3000349898
Short name T1120
Test name
Test status
Simulation time 30397425 ps
CPU time 0.81 seconds
Started Jun 13 02:40:48 PM PDT 24
Finished Jun 13 02:40:54 PM PDT 24
Peak memory 206256 kb
Host smart-ffba9086-60bb-4d95-90d9-5530e9cd78fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000349898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3000349898
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3092098195
Short name T1079
Test name
Test status
Simulation time 46726054 ps
CPU time 1.1 seconds
Started Jun 13 02:40:49 PM PDT 24
Finished Jun 13 02:40:57 PM PDT 24
Peak memory 206364 kb
Host smart-abd5fb46-3126-4509-b051-cdb5473a0dce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092098195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3092098195
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2534816783
Short name T1058
Test name
Test status
Simulation time 73050928 ps
CPU time 2.82 seconds
Started Jun 13 02:40:39 PM PDT 24
Finished Jun 13 02:40:47 PM PDT 24
Peak memory 214676 kb
Host smart-5096d91b-a241-4b54-96e0-d2c6b31de50c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534816783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2534816783
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4086507995
Short name T1032
Test name
Test status
Simulation time 89972207 ps
CPU time 2.52 seconds
Started Jun 13 02:40:46 PM PDT 24
Finished Jun 13 02:40:54 PM PDT 24
Peak memory 206408 kb
Host smart-c53e6999-1d6d-43c8-b7f0-9603c296db9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086507995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.4086507995
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3863140450
Short name T1088
Test name
Test status
Simulation time 27381418 ps
CPU time 1.35 seconds
Started Jun 13 02:40:45 PM PDT 24
Finished Jun 13 02:40:50 PM PDT 24
Peak memory 214860 kb
Host smart-ee076dcd-55a6-4ca8-b224-d827e26a1d62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863140450 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3863140450
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3645190153
Short name T1109
Test name
Test status
Simulation time 33281461 ps
CPU time 0.87 seconds
Started Jun 13 02:40:36 PM PDT 24
Finished Jun 13 02:40:42 PM PDT 24
Peak memory 206220 kb
Host smart-2fc7e65a-bff0-4012-8972-0fc37f7113bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645190153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3645190153
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1943435083
Short name T1040
Test name
Test status
Simulation time 24893489 ps
CPU time 0.86 seconds
Started Jun 13 02:40:46 PM PDT 24
Finished Jun 13 02:40:52 PM PDT 24
Peak memory 205464 kb
Host smart-4925d5fb-55d2-4602-add7-6d80e7d0351a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943435083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1943435083
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3063034217
Short name T247
Test name
Test status
Simulation time 79645071 ps
CPU time 1.19 seconds
Started Jun 13 02:40:42 PM PDT 24
Finished Jun 13 02:40:48 PM PDT 24
Peak memory 206400 kb
Host smart-8774d8aa-aec3-4ed1-83e5-62c7828bb247
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063034217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3063034217
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1869532380
Short name T1111
Test name
Test status
Simulation time 192565468 ps
CPU time 2.67 seconds
Started Jun 13 02:40:45 PM PDT 24
Finished Jun 13 02:40:52 PM PDT 24
Peak memory 214656 kb
Host smart-1d1b4f12-8e53-40ec-b043-e08f2e7e5fb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869532380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1869532380
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.372756834
Short name T285
Test name
Test status
Simulation time 99714248 ps
CPU time 2.63 seconds
Started Jun 13 02:40:48 PM PDT 24
Finished Jun 13 02:40:56 PM PDT 24
Peak memory 214512 kb
Host smart-f63259fc-c949-4deb-8def-3736a002ed37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372756834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.372756834
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.786302698
Short name T1057
Test name
Test status
Simulation time 113608647 ps
CPU time 2.05 seconds
Started Jun 13 02:40:49 PM PDT 24
Finished Jun 13 02:40:57 PM PDT 24
Peak memory 214576 kb
Host smart-f504f89a-d21e-4b6f-9b69-c81b59ffc258
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786302698 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.786302698
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2732235597
Short name T1106
Test name
Test status
Simulation time 23355197 ps
CPU time 0.91 seconds
Started Jun 13 02:40:42 PM PDT 24
Finished Jun 13 02:40:48 PM PDT 24
Peak memory 206320 kb
Host smart-6344e096-777d-4eed-9fd5-27506fe48e95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732235597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2732235597
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.4105511438
Short name T1076
Test name
Test status
Simulation time 16009807 ps
CPU time 0.92 seconds
Started Jun 13 02:40:49 PM PDT 24
Finished Jun 13 02:40:57 PM PDT 24
Peak memory 206340 kb
Host smart-1c132b9b-61d0-4aa7-bb19-e3f8432dacbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105511438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.4105511438
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3388528386
Short name T1080
Test name
Test status
Simulation time 116179211 ps
CPU time 1.46 seconds
Started Jun 13 02:40:49 PM PDT 24
Finished Jun 13 02:40:57 PM PDT 24
Peak memory 206400 kb
Host smart-fe6d1de0-d754-45d7-84b7-2f25c1effa1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388528386 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3388528386
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3866437626
Short name T1029
Test name
Test status
Simulation time 57585616 ps
CPU time 2.19 seconds
Started Jun 13 02:40:45 PM PDT 24
Finished Jun 13 02:40:52 PM PDT 24
Peak memory 214640 kb
Host smart-160e2a4a-27ae-4603-b155-90e882a4a0d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866437626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3866437626
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1001074831
Short name T1030
Test name
Test status
Simulation time 227781906 ps
CPU time 1.78 seconds
Started Jun 13 02:40:49 PM PDT 24
Finished Jun 13 02:40:57 PM PDT 24
Peak memory 206720 kb
Host smart-c521a6a5-01b6-40ec-933c-05474e671d04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001074831 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1001074831
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3433304000
Short name T1075
Test name
Test status
Simulation time 24272992 ps
CPU time 0.92 seconds
Started Jun 13 02:40:49 PM PDT 24
Finished Jun 13 02:40:56 PM PDT 24
Peak memory 206460 kb
Host smart-6dda7b50-6987-4c55-b9af-f75a4e6aed1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433304000 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3433304000
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.58490272
Short name T1108
Test name
Test status
Simulation time 40833511 ps
CPU time 0.9 seconds
Started Jun 13 02:40:43 PM PDT 24
Finished Jun 13 02:40:48 PM PDT 24
Peak memory 206348 kb
Host smart-fd4bc4d4-dd9e-46b7-b43b-bb768c857bde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58490272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.58490272
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2647660405
Short name T1091
Test name
Test status
Simulation time 149041218 ps
CPU time 0.87 seconds
Started Jun 13 02:40:48 PM PDT 24
Finished Jun 13 02:40:54 PM PDT 24
Peak memory 205824 kb
Host smart-4494db81-fb38-473a-b775-94ace3b2ec26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647660405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2647660405
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4036372421
Short name T1063
Test name
Test status
Simulation time 42407861 ps
CPU time 1.13 seconds
Started Jun 13 02:40:49 PM PDT 24
Finished Jun 13 02:40:56 PM PDT 24
Peak memory 206352 kb
Host smart-60d3bc52-6c25-45d1-9efd-c0859a5ba0b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036372421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.4036372421
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.939518673
Short name T1070
Test name
Test status
Simulation time 124760996 ps
CPU time 2.28 seconds
Started Jun 13 02:40:44 PM PDT 24
Finished Jun 13 02:40:50 PM PDT 24
Peak memory 214796 kb
Host smart-4e4b5666-dc66-4892-8a71-bec48e76b1d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939518673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.939518673
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.663877610
Short name T1052
Test name
Test status
Simulation time 97465877 ps
CPU time 1.68 seconds
Started Jun 13 02:40:46 PM PDT 24
Finished Jun 13 02:40:53 PM PDT 24
Peak memory 215036 kb
Host smart-82e31bf0-a58e-45fd-917c-b86de63e989a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663877610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.663877610
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1624727580
Short name T249
Test name
Test status
Simulation time 276546193 ps
CPU time 1.52 seconds
Started Jun 13 02:40:36 PM PDT 24
Finished Jun 13 02:40:42 PM PDT 24
Peak memory 206352 kb
Host smart-287d14c7-91c0-4adc-877c-27c5a2cb0344
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624727580 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1624727580
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4132049350
Short name T1026
Test name
Test status
Simulation time 1265993109 ps
CPU time 3.13 seconds
Started Jun 13 02:40:33 PM PDT 24
Finished Jun 13 02:40:42 PM PDT 24
Peak memory 206332 kb
Host smart-c5bc07b7-7efe-454c-9225-910c47d2e299
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132049350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.4132049350
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1876817650
Short name T246
Test name
Test status
Simulation time 187878958 ps
CPU time 0.85 seconds
Started Jun 13 02:40:31 PM PDT 24
Finished Jun 13 02:40:37 PM PDT 24
Peak memory 206236 kb
Host smart-32279b10-224d-4d84-b7d7-e66a61433902
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876817650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1876817650
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3849264568
Short name T1003
Test name
Test status
Simulation time 44267082 ps
CPU time 1.21 seconds
Started Jun 13 02:40:33 PM PDT 24
Finished Jun 13 02:40:40 PM PDT 24
Peak memory 214656 kb
Host smart-67b4e836-d965-479f-b822-577758ddf320
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849264568 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3849264568
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3283840498
Short name T1028
Test name
Test status
Simulation time 24644189 ps
CPU time 0.88 seconds
Started Jun 13 02:40:33 PM PDT 24
Finished Jun 13 02:40:39 PM PDT 24
Peak memory 206344 kb
Host smart-d8f9ea05-3755-4798-98c2-fab5684e58c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283840498 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3283840498
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1450446572
Short name T1065
Test name
Test status
Simulation time 39454781 ps
CPU time 0.81 seconds
Started Jun 13 02:40:35 PM PDT 24
Finished Jun 13 02:40:41 PM PDT 24
Peak memory 206160 kb
Host smart-edda2623-7713-48fc-947f-f84a8b7a3764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450446572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1450446572
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1713240862
Short name T1048
Test name
Test status
Simulation time 88715350 ps
CPU time 1.05 seconds
Started Jun 13 02:40:33 PM PDT 24
Finished Jun 13 02:40:40 PM PDT 24
Peak memory 206468 kb
Host smart-dd7b1a1c-cdf5-445f-b82e-087eb7b0ebc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713240862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1713240862
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.765527953
Short name T1002
Test name
Test status
Simulation time 315632187 ps
CPU time 3.06 seconds
Started Jun 13 02:40:34 PM PDT 24
Finished Jun 13 02:40:42 PM PDT 24
Peak memory 214700 kb
Host smart-00db71b9-fd01-43a0-ad7a-655f6ef6d945
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765527953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.765527953
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4291756542
Short name T1020
Test name
Test status
Simulation time 224922742 ps
CPU time 3.32 seconds
Started Jun 13 02:40:32 PM PDT 24
Finished Jun 13 02:40:40 PM PDT 24
Peak memory 206544 kb
Host smart-e518e9c8-5557-434c-af9f-2b80b5e9c5a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291756542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.4291756542
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.605320907
Short name T1056
Test name
Test status
Simulation time 13231782 ps
CPU time 0.88 seconds
Started Jun 13 02:40:43 PM PDT 24
Finished Jun 13 02:40:49 PM PDT 24
Peak memory 206388 kb
Host smart-82c7ef49-6a9f-4e70-9822-ddd2713980a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605320907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.605320907
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3558775419
Short name T1102
Test name
Test status
Simulation time 13341869 ps
CPU time 0.87 seconds
Started Jun 13 02:40:42 PM PDT 24
Finished Jun 13 02:40:48 PM PDT 24
Peak memory 206316 kb
Host smart-00b203e4-4851-47b4-80b9-a5e7d455b56a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558775419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3558775419
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2675064111
Short name T1053
Test name
Test status
Simulation time 65720559 ps
CPU time 0.92 seconds
Started Jun 13 02:40:49 PM PDT 24
Finished Jun 13 02:40:56 PM PDT 24
Peak memory 206360 kb
Host smart-a2ae0e55-bfb2-41fa-af57-e8cf16e5bab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675064111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2675064111
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3891322755
Short name T1066
Test name
Test status
Simulation time 88202252 ps
CPU time 0.83 seconds
Started Jun 13 02:40:49 PM PDT 24
Finished Jun 13 02:40:56 PM PDT 24
Peak memory 206248 kb
Host smart-af4231dd-21a0-408a-a5f2-04b6746d2436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891322755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3891322755
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3234754401
Short name T1077
Test name
Test status
Simulation time 144417848 ps
CPU time 0.9 seconds
Started Jun 13 02:40:48 PM PDT 24
Finished Jun 13 02:40:55 PM PDT 24
Peak memory 206268 kb
Host smart-36bc8870-adcf-434f-8728-b78150d87018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234754401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3234754401
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3694359915
Short name T1095
Test name
Test status
Simulation time 12994111 ps
CPU time 0.91 seconds
Started Jun 13 02:40:43 PM PDT 24
Finished Jun 13 02:40:49 PM PDT 24
Peak memory 206312 kb
Host smart-b3fa39c2-acac-4d2c-8392-72ca6ae2254b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694359915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3694359915
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.481086670
Short name T1127
Test name
Test status
Simulation time 27276195 ps
CPU time 0.89 seconds
Started Jun 13 02:40:51 PM PDT 24
Finished Jun 13 02:40:58 PM PDT 24
Peak memory 206336 kb
Host smart-3fff3151-e583-4b06-8ad5-481572db381c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481086670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.481086670
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1308036599
Short name T1084
Test name
Test status
Simulation time 47915729 ps
CPU time 0.83 seconds
Started Jun 13 02:40:50 PM PDT 24
Finished Jun 13 02:40:57 PM PDT 24
Peak memory 206276 kb
Host smart-0a0acd2d-59e3-4cb4-a3aa-4122ae373f1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308036599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1308036599
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.377899961
Short name T1043
Test name
Test status
Simulation time 18373600 ps
CPU time 0.81 seconds
Started Jun 13 02:40:53 PM PDT 24
Finished Jun 13 02:41:00 PM PDT 24
Peak memory 206220 kb
Host smart-fcc6740e-3be4-4b74-9fa8-c0b794c4ebeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377899961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.377899961
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.100590933
Short name T1071
Test name
Test status
Simulation time 13219746 ps
CPU time 0.91 seconds
Started Jun 13 02:40:50 PM PDT 24
Finished Jun 13 02:40:58 PM PDT 24
Peak memory 206364 kb
Host smart-6af96655-fcc4-4526-b507-d6c1c3b9f54f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100590933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.100590933
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2320764535
Short name T250
Test name
Test status
Simulation time 36552606 ps
CPU time 1.27 seconds
Started Jun 13 02:40:31 PM PDT 24
Finished Jun 13 02:40:37 PM PDT 24
Peak memory 206332 kb
Host smart-f71a5f74-bc40-4859-ad3d-dfcec193f970
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320764535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2320764535
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.532097675
Short name T259
Test name
Test status
Simulation time 58947597 ps
CPU time 3.3 seconds
Started Jun 13 02:40:33 PM PDT 24
Finished Jun 13 02:40:42 PM PDT 24
Peak memory 206312 kb
Host smart-07c1ad10-6eb8-41a4-ad73-6d6056a681de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532097675 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.532097675
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.349935807
Short name T253
Test name
Test status
Simulation time 50004507 ps
CPU time 0.91 seconds
Started Jun 13 02:40:35 PM PDT 24
Finished Jun 13 02:40:41 PM PDT 24
Peak memory 206196 kb
Host smart-7d1a9dde-e8f3-43bf-bd18-374766dfc8eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349935807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.349935807
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3744966466
Short name T1007
Test name
Test status
Simulation time 61349636 ps
CPU time 1.13 seconds
Started Jun 13 02:40:36 PM PDT 24
Finished Jun 13 02:40:42 PM PDT 24
Peak memory 214752 kb
Host smart-a0b0ce11-6207-48d1-a53b-b2c9add92f73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744966466 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3744966466
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3644764754
Short name T1000
Test name
Test status
Simulation time 18208162 ps
CPU time 0.82 seconds
Started Jun 13 02:40:30 PM PDT 24
Finished Jun 13 02:40:36 PM PDT 24
Peak memory 206248 kb
Host smart-f5b036e3-d84a-4c3e-9fce-cb86c66f2cb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644764754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3644764754
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.4033883034
Short name T1023
Test name
Test status
Simulation time 24241316 ps
CPU time 0.87 seconds
Started Jun 13 02:40:33 PM PDT 24
Finished Jun 13 02:40:40 PM PDT 24
Peak memory 206344 kb
Host smart-cad886ce-bf81-4cd9-a0ce-9a877f3590ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033883034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.4033883034
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.311854397
Short name T1060
Test name
Test status
Simulation time 25782969 ps
CPU time 1.19 seconds
Started Jun 13 02:40:36 PM PDT 24
Finished Jun 13 02:40:42 PM PDT 24
Peak memory 206488 kb
Host smart-9eea4fed-ef9b-41f2-ba46-7d539e2c7d5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311854397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.311854397
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2880634371
Short name T1119
Test name
Test status
Simulation time 62911741 ps
CPU time 2.31 seconds
Started Jun 13 02:40:33 PM PDT 24
Finished Jun 13 02:40:40 PM PDT 24
Peak memory 214564 kb
Host smart-a17cc846-8d3e-4209-9bf5-32ace3bc04e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880634371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2880634371
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.952761497
Short name T1094
Test name
Test status
Simulation time 128895900 ps
CPU time 1.92 seconds
Started Jun 13 02:40:33 PM PDT 24
Finished Jun 13 02:40:41 PM PDT 24
Peak memory 206652 kb
Host smart-adce2b77-1890-4ab2-b194-244f466466ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952761497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.952761497
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.740173512
Short name T999
Test name
Test status
Simulation time 23339559 ps
CPU time 0.82 seconds
Started Jun 13 02:40:52 PM PDT 24
Finished Jun 13 02:40:59 PM PDT 24
Peak memory 206328 kb
Host smart-2e6dd33f-8b81-402f-bb3d-dff250a01c81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740173512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.740173512
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3812828611
Short name T1004
Test name
Test status
Simulation time 23685903 ps
CPU time 0.82 seconds
Started Jun 13 02:40:49 PM PDT 24
Finished Jun 13 02:40:56 PM PDT 24
Peak memory 206360 kb
Host smart-73edf15e-1071-4793-bedf-ca55d0ffe89f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812828611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3812828611
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1994290022
Short name T1129
Test name
Test status
Simulation time 17623172 ps
CPU time 0.83 seconds
Started Jun 13 02:40:51 PM PDT 24
Finished Jun 13 02:40:59 PM PDT 24
Peak memory 206344 kb
Host smart-34105e48-1a21-4926-b84f-5bc6c76ab3f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994290022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1994290022
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2899881202
Short name T1036
Test name
Test status
Simulation time 34179558 ps
CPU time 0.8 seconds
Started Jun 13 02:40:53 PM PDT 24
Finished Jun 13 02:41:00 PM PDT 24
Peak memory 206272 kb
Host smart-d028814e-8fcd-497e-adc5-3268ca54a17e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899881202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2899881202
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1226474800
Short name T1035
Test name
Test status
Simulation time 138710343 ps
CPU time 0.85 seconds
Started Jun 13 02:40:57 PM PDT 24
Finished Jun 13 02:41:03 PM PDT 24
Peak memory 206452 kb
Host smart-46f80b20-4489-407d-aa11-e439ffa717ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226474800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1226474800
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2893112478
Short name T1021
Test name
Test status
Simulation time 11690448 ps
CPU time 0.83 seconds
Started Jun 13 02:40:50 PM PDT 24
Finished Jun 13 02:40:56 PM PDT 24
Peak memory 206368 kb
Host smart-36b11be3-4600-4518-91bc-99db12083aa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893112478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2893112478
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.807117032
Short name T1126
Test name
Test status
Simulation time 16608208 ps
CPU time 0.78 seconds
Started Jun 13 02:40:51 PM PDT 24
Finished Jun 13 02:40:59 PM PDT 24
Peak memory 206252 kb
Host smart-bd25581e-202e-4e41-9cc3-830df579f302
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807117032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.807117032
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2537122286
Short name T1009
Test name
Test status
Simulation time 17971127 ps
CPU time 0.98 seconds
Started Jun 13 02:40:51 PM PDT 24
Finished Jun 13 02:40:59 PM PDT 24
Peak memory 206352 kb
Host smart-1f5a965e-af4f-419e-858b-2203e8ebc7b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537122286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2537122286
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3442118831
Short name T1089
Test name
Test status
Simulation time 88328194 ps
CPU time 0.88 seconds
Started Jun 13 02:40:50 PM PDT 24
Finished Jun 13 02:40:57 PM PDT 24
Peak memory 206360 kb
Host smart-f9c2de8b-45c4-4449-a197-f9ca7eb2de3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442118831 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3442118831
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3549515822
Short name T1124
Test name
Test status
Simulation time 21824391 ps
CPU time 0.93 seconds
Started Jun 13 02:40:50 PM PDT 24
Finished Jun 13 02:40:58 PM PDT 24
Peak memory 206348 kb
Host smart-d3c5e193-2def-4ddf-b507-3ccc6b44a935
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549515822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3549515822
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1169958455
Short name T1047
Test name
Test status
Simulation time 18484075 ps
CPU time 1.07 seconds
Started Jun 13 02:40:35 PM PDT 24
Finished Jun 13 02:40:41 PM PDT 24
Peak memory 206336 kb
Host smart-14a12b18-8ebf-436b-ab61-1cfcc0a11fa7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169958455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1169958455
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.562470235
Short name T1072
Test name
Test status
Simulation time 347193581 ps
CPU time 5.14 seconds
Started Jun 13 02:40:31 PM PDT 24
Finished Jun 13 02:40:41 PM PDT 24
Peak memory 206412 kb
Host smart-ddee46cc-7c68-48bc-8ade-2cdf83c1c722
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562470235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.562470235
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.4056319911
Short name T258
Test name
Test status
Simulation time 15846830 ps
CPU time 0.92 seconds
Started Jun 13 02:40:33 PM PDT 24
Finished Jun 13 02:40:39 PM PDT 24
Peak memory 206340 kb
Host smart-224c896a-9279-4840-9d27-dff262fd14e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056319911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.4056319911
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.558776227
Short name T1024
Test name
Test status
Simulation time 67436422 ps
CPU time 1.08 seconds
Started Jun 13 02:40:35 PM PDT 24
Finished Jun 13 02:40:41 PM PDT 24
Peak memory 215832 kb
Host smart-84048d37-6b5a-4628-b23d-d87d743ef528
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558776227 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.558776227
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.580756618
Short name T1130
Test name
Test status
Simulation time 39526987 ps
CPU time 0.85 seconds
Started Jun 13 02:40:42 PM PDT 24
Finished Jun 13 02:40:47 PM PDT 24
Peak memory 206340 kb
Host smart-6de97241-b091-46c6-8ac6-17e928cfa542
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580756618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.580756618
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.4076769772
Short name T1110
Test name
Test status
Simulation time 13741693 ps
CPU time 0.85 seconds
Started Jun 13 02:40:35 PM PDT 24
Finished Jun 13 02:40:41 PM PDT 24
Peak memory 206360 kb
Host smart-9fe453e3-1dc1-4e3b-8d51-4b05427abac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076769772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.4076769772
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4287782581
Short name T1099
Test name
Test status
Simulation time 86219061 ps
CPU time 1.26 seconds
Started Jun 13 02:40:33 PM PDT 24
Finished Jun 13 02:40:40 PM PDT 24
Peak memory 206624 kb
Host smart-d7f815a4-97a6-4237-9f96-b4ff300e9552
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287782581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.4287782581
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.679787214
Short name T1010
Test name
Test status
Simulation time 157421785 ps
CPU time 3.87 seconds
Started Jun 13 02:40:32 PM PDT 24
Finished Jun 13 02:40:41 PM PDT 24
Peak memory 214696 kb
Host smart-6978d250-f911-45c0-8186-45d190398f1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679787214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.679787214
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1831111191
Short name T1078
Test name
Test status
Simulation time 225847622 ps
CPU time 1.79 seconds
Started Jun 13 02:40:30 PM PDT 24
Finished Jun 13 02:40:37 PM PDT 24
Peak memory 206560 kb
Host smart-1a49f61c-da2e-47a1-a476-c6667c5ad9d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831111191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1831111191
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.469591249
Short name T1041
Test name
Test status
Simulation time 11850854 ps
CPU time 0.84 seconds
Started Jun 13 02:40:51 PM PDT 24
Finished Jun 13 02:40:59 PM PDT 24
Peak memory 206336 kb
Host smart-8579cb32-602f-4b81-ab2e-e21bef9db333
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469591249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.469591249
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2996016721
Short name T1005
Test name
Test status
Simulation time 65879108 ps
CPU time 0.91 seconds
Started Jun 13 02:40:50 PM PDT 24
Finished Jun 13 02:40:58 PM PDT 24
Peak memory 206336 kb
Host smart-37215444-89be-4f23-b4de-53d444095368
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996016721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2996016721
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.4156185839
Short name T1022
Test name
Test status
Simulation time 19215538 ps
CPU time 0.95 seconds
Started Jun 13 02:40:51 PM PDT 24
Finished Jun 13 02:40:58 PM PDT 24
Peak memory 206344 kb
Host smart-62d05b7b-904f-400d-8b18-3c56f92e5054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156185839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.4156185839
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.808966606
Short name T1044
Test name
Test status
Simulation time 29692365 ps
CPU time 0.78 seconds
Started Jun 13 02:40:51 PM PDT 24
Finished Jun 13 02:40:59 PM PDT 24
Peak memory 206224 kb
Host smart-d9ff51b7-9181-4d24-b06c-640dd9d405dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808966606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.808966606
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.4222999520
Short name T1116
Test name
Test status
Simulation time 14610861 ps
CPU time 0.98 seconds
Started Jun 13 02:40:52 PM PDT 24
Finished Jun 13 02:40:59 PM PDT 24
Peak memory 206316 kb
Host smart-eb3fb718-2968-4daf-b70d-6e9d3c53e1ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222999520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.4222999520
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3899704169
Short name T1100
Test name
Test status
Simulation time 16636252 ps
CPU time 0.94 seconds
Started Jun 13 02:40:49 PM PDT 24
Finished Jun 13 02:40:56 PM PDT 24
Peak memory 206360 kb
Host smart-4824c14b-281c-4cb5-a06e-88b38a7cf4b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899704169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3899704169
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.491946119
Short name T1085
Test name
Test status
Simulation time 34249322 ps
CPU time 0.8 seconds
Started Jun 13 02:40:58 PM PDT 24
Finished Jun 13 02:41:04 PM PDT 24
Peak memory 206416 kb
Host smart-2293707f-449e-4f7d-9124-bae4755e5f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491946119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.491946119
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2444239002
Short name T1038
Test name
Test status
Simulation time 12898904 ps
CPU time 0.85 seconds
Started Jun 13 02:40:58 PM PDT 24
Finished Jun 13 02:41:04 PM PDT 24
Peak memory 206508 kb
Host smart-9a9be588-5f20-43c4-a6b8-f26015cb494e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444239002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2444239002
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.583158624
Short name T1012
Test name
Test status
Simulation time 12221699 ps
CPU time 0.86 seconds
Started Jun 13 02:40:48 PM PDT 24
Finished Jun 13 02:40:55 PM PDT 24
Peak memory 206372 kb
Host smart-f610b05c-6e11-4a9e-9ce3-34c70c2c6027
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583158624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.583158624
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.4177534151
Short name T1025
Test name
Test status
Simulation time 40601227 ps
CPU time 0.89 seconds
Started Jun 13 02:40:53 PM PDT 24
Finished Jun 13 02:41:01 PM PDT 24
Peak memory 206324 kb
Host smart-67aa3ae2-520e-430d-93d6-6d3969335d50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177534151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.4177534151
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.4289172579
Short name T1093
Test name
Test status
Simulation time 63422060 ps
CPU time 1.05 seconds
Started Jun 13 02:40:33 PM PDT 24
Finished Jun 13 02:40:39 PM PDT 24
Peak memory 216360 kb
Host smart-b9a4fd09-780d-4f5a-ada3-9e0172dbbe6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289172579 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.4289172579
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.371599441
Short name T1087
Test name
Test status
Simulation time 94275119 ps
CPU time 0.83 seconds
Started Jun 13 02:40:33 PM PDT 24
Finished Jun 13 02:40:39 PM PDT 24
Peak memory 206240 kb
Host smart-7ae207aa-f695-4c64-af18-cb074b1fcc91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371599441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.371599441
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2692427190
Short name T1061
Test name
Test status
Simulation time 18730714 ps
CPU time 0.9 seconds
Started Jun 13 02:40:33 PM PDT 24
Finished Jun 13 02:40:40 PM PDT 24
Peak memory 206372 kb
Host smart-be26903b-ab9d-4b76-9d6a-b8105751e831
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692427190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2692427190
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2060754583
Short name T1067
Test name
Test status
Simulation time 40900113 ps
CPU time 0.94 seconds
Started Jun 13 02:40:38 PM PDT 24
Finished Jun 13 02:40:45 PM PDT 24
Peak memory 206372 kb
Host smart-1a46a22b-1759-4f78-8b27-b44fad8615b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060754583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2060754583
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2343297894
Short name T1019
Test name
Test status
Simulation time 138919745 ps
CPU time 2.44 seconds
Started Jun 13 02:40:35 PM PDT 24
Finished Jun 13 02:40:42 PM PDT 24
Peak memory 214716 kb
Host smart-04a0bdd0-19fa-40f9-9715-e5862090837c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343297894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2343297894
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1312878414
Short name T287
Test name
Test status
Simulation time 280515816 ps
CPU time 2.26 seconds
Started Jun 13 02:40:35 PM PDT 24
Finished Jun 13 02:40:42 PM PDT 24
Peak memory 205788 kb
Host smart-d57399e4-cbe4-4f1d-b009-18223e257567
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312878414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1312878414
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2524134584
Short name T1027
Test name
Test status
Simulation time 32976512 ps
CPU time 1.47 seconds
Started Jun 13 02:40:33 PM PDT 24
Finished Jun 13 02:40:41 PM PDT 24
Peak memory 222840 kb
Host smart-604e3c60-086a-4569-b65c-cc1bd22d3ffd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524134584 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2524134584
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1937222436
Short name T1082
Test name
Test status
Simulation time 196038804 ps
CPU time 0.84 seconds
Started Jun 13 02:40:36 PM PDT 24
Finished Jun 13 02:40:42 PM PDT 24
Peak memory 206280 kb
Host smart-e2b83e35-92e7-4a8e-b45a-39ab16942cf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937222436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1937222436
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2312998988
Short name T1055
Test name
Test status
Simulation time 34745295 ps
CPU time 0.81 seconds
Started Jun 13 02:40:35 PM PDT 24
Finished Jun 13 02:40:41 PM PDT 24
Peak memory 206320 kb
Host smart-91fea64f-7ad5-48c1-a69e-943b90bc3b9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312998988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2312998988
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1328452089
Short name T248
Test name
Test status
Simulation time 100375372 ps
CPU time 1.1 seconds
Started Jun 13 02:40:32 PM PDT 24
Finished Jun 13 02:40:38 PM PDT 24
Peak memory 206404 kb
Host smart-61fec693-9f26-4259-b300-d4148e293329
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328452089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1328452089
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.929718444
Short name T1031
Test name
Test status
Simulation time 158561937 ps
CPU time 2.62 seconds
Started Jun 13 02:40:30 PM PDT 24
Finished Jun 13 02:40:38 PM PDT 24
Peak memory 214648 kb
Host smart-536ea78d-550b-426a-9e0c-736c18af7538
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929718444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.929718444
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1712034581
Short name T283
Test name
Test status
Simulation time 89491651 ps
CPU time 1.67 seconds
Started Jun 13 02:40:33 PM PDT 24
Finished Jun 13 02:40:41 PM PDT 24
Peak memory 206492 kb
Host smart-ca23f139-1c8e-4ce7-a114-96d302454a60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712034581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1712034581
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2595403694
Short name T1064
Test name
Test status
Simulation time 38049307 ps
CPU time 1.07 seconds
Started Jun 13 02:40:43 PM PDT 24
Finished Jun 13 02:40:48 PM PDT 24
Peak memory 216868 kb
Host smart-d23046d8-2d09-4a62-a734-a19a112feb6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595403694 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2595403694
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2897403428
Short name T257
Test name
Test status
Simulation time 68882772 ps
CPU time 0.95 seconds
Started Jun 13 02:40:34 PM PDT 24
Finished Jun 13 02:40:40 PM PDT 24
Peak memory 206340 kb
Host smart-7fc0c3a3-b1a2-41f4-be5c-46bea315d60a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897403428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2897403428
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3805920886
Short name T1006
Test name
Test status
Simulation time 41667956 ps
CPU time 0.89 seconds
Started Jun 13 02:40:34 PM PDT 24
Finished Jun 13 02:40:41 PM PDT 24
Peak memory 206244 kb
Host smart-e4fd7cc7-a615-4fff-a3c3-a63ebbe58fff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805920886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3805920886
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2813011757
Short name T1097
Test name
Test status
Simulation time 19607550 ps
CPU time 1.1 seconds
Started Jun 13 02:40:35 PM PDT 24
Finished Jun 13 02:40:41 PM PDT 24
Peak memory 206336 kb
Host smart-661c4f6f-a975-4549-bf8e-9a2f599628ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813011757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2813011757
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1474112176
Short name T1125
Test name
Test status
Simulation time 29520525 ps
CPU time 1.92 seconds
Started Jun 13 02:40:36 PM PDT 24
Finished Jun 13 02:40:43 PM PDT 24
Peak memory 214708 kb
Host smart-6e5e393b-58bc-4582-815d-7acf129690eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474112176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1474112176
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.173934999
Short name T1045
Test name
Test status
Simulation time 254126702 ps
CPU time 2.11 seconds
Started Jun 13 02:40:35 PM PDT 24
Finished Jun 13 02:40:42 PM PDT 24
Peak memory 206460 kb
Host smart-9a55029f-29b8-49a8-bcbe-366d6687a3f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173934999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.173934999
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.623599748
Short name T1016
Test name
Test status
Simulation time 34432302 ps
CPU time 1.34 seconds
Started Jun 13 02:40:46 PM PDT 24
Finished Jun 13 02:40:52 PM PDT 24
Peak memory 214604 kb
Host smart-1b9a6707-a417-44e8-975a-2f8223fba8b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623599748 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.623599748
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.68559450
Short name T256
Test name
Test status
Simulation time 40754641 ps
CPU time 0.89 seconds
Started Jun 13 02:40:45 PM PDT 24
Finished Jun 13 02:40:50 PM PDT 24
Peak memory 206332 kb
Host smart-668a588c-feb5-4459-973b-b5295323877b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68559450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.68559450
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.857111693
Short name T997
Test name
Test status
Simulation time 20874201 ps
CPU time 0.84 seconds
Started Jun 13 02:40:46 PM PDT 24
Finished Jun 13 02:40:52 PM PDT 24
Peak memory 206348 kb
Host smart-fb6ab270-bbb7-4014-ac78-1c190544fc9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857111693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.857111693
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.4033841783
Short name T251
Test name
Test status
Simulation time 377994844 ps
CPU time 1.3 seconds
Started Jun 13 02:40:45 PM PDT 24
Finished Jun 13 02:40:50 PM PDT 24
Peak memory 206368 kb
Host smart-37de4efc-aa5d-433a-b265-2d98479de972
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033841783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.4033841783
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3646416505
Short name T1112
Test name
Test status
Simulation time 43100395 ps
CPU time 1.71 seconds
Started Jun 13 02:40:41 PM PDT 24
Finished Jun 13 02:40:47 PM PDT 24
Peak memory 214796 kb
Host smart-ff51e4c5-212e-46c5-b85c-ec46a1da1d31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646416505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3646416505
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2963489582
Short name T278
Test name
Test status
Simulation time 264161996 ps
CPU time 2.03 seconds
Started Jun 13 02:40:37 PM PDT 24
Finished Jun 13 02:40:45 PM PDT 24
Peak memory 214536 kb
Host smart-ca283a08-d0a2-4501-a3bc-6367326fc0ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963489582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2963489582
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.248326649
Short name T1033
Test name
Test status
Simulation time 114937636 ps
CPU time 1.18 seconds
Started Jun 13 02:40:39 PM PDT 24
Finished Jun 13 02:40:46 PM PDT 24
Peak memory 222892 kb
Host smart-84924268-42b7-4681-b9fe-1c8496cc2819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248326649 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.248326649
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1704992853
Short name T1073
Test name
Test status
Simulation time 24233877 ps
CPU time 0.87 seconds
Started Jun 13 02:40:49 PM PDT 24
Finished Jun 13 02:40:56 PM PDT 24
Peak memory 206344 kb
Host smart-fb1539a9-09ba-461e-8143-0a132dd97e23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704992853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1704992853
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1607257171
Short name T1059
Test name
Test status
Simulation time 13807983 ps
CPU time 0.84 seconds
Started Jun 13 02:41:43 PM PDT 24
Finished Jun 13 02:41:48 PM PDT 24
Peak memory 206284 kb
Host smart-5ae8d7c5-aa85-429f-abcb-ccd09ad92f84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607257171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1607257171
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3616846854
Short name T265
Test name
Test status
Simulation time 17326384 ps
CPU time 1.13 seconds
Started Jun 13 02:40:45 PM PDT 24
Finished Jun 13 02:40:50 PM PDT 24
Peak memory 206512 kb
Host smart-6e4a4f02-312f-4988-9449-5620aca6e95e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616846854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3616846854
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3153865591
Short name T1034
Test name
Test status
Simulation time 90101066 ps
CPU time 1.86 seconds
Started Jun 13 02:40:45 PM PDT 24
Finished Jun 13 02:40:51 PM PDT 24
Peak memory 214684 kb
Host smart-48ebfd8c-988e-4fe1-905c-ae7909353ae6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153865591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3153865591
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/default/0.edn_alert.2408316733
Short name T220
Test name
Test status
Simulation time 24400869 ps
CPU time 1.21 seconds
Started Jun 13 01:48:48 PM PDT 24
Finished Jun 13 01:48:50 PM PDT 24
Peak memory 218240 kb
Host smart-2ad7eaa5-c936-4289-889e-14c5e31fc7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408316733 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2408316733
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.3680419105
Short name T677
Test name
Test status
Simulation time 97669340 ps
CPU time 1.05 seconds
Started Jun 13 01:48:49 PM PDT 24
Finished Jun 13 01:48:51 PM PDT 24
Peak memory 206136 kb
Host smart-0a9a3120-5750-4178-b2d1-f61398467bb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680419105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3680419105
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1851446446
Short name T996
Test name
Test status
Simulation time 51654793 ps
CPU time 1.14 seconds
Started Jun 13 01:48:47 PM PDT 24
Finished Jun 13 01:48:49 PM PDT 24
Peak memory 217732 kb
Host smart-26c20e5c-461e-460d-87b8-51c13eb4046d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851446446 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1851446446
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.316166359
Short name T831
Test name
Test status
Simulation time 35341332 ps
CPU time 1.17 seconds
Started Jun 13 01:48:50 PM PDT 24
Finished Jun 13 01:48:52 PM PDT 24
Peak memory 223348 kb
Host smart-de10e659-957e-425d-8366-e4e5bb52bc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316166359 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.316166359
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2200847441
Short name T420
Test name
Test status
Simulation time 34659820 ps
CPU time 1.41 seconds
Started Jun 13 01:48:53 PM PDT 24
Finished Jun 13 01:48:56 PM PDT 24
Peak memory 216628 kb
Host smart-1bc88faa-ee66-494e-9630-2da1e08e9d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200847441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2200847441
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.454433935
Short name T851
Test name
Test status
Simulation time 30185897 ps
CPU time 1.29 seconds
Started Jun 13 01:48:49 PM PDT 24
Finished Jun 13 01:48:51 PM PDT 24
Peak memory 220092 kb
Host smart-c6cc2c13-65c5-49f3-870f-0367c476422c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454433935 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.454433935
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.1220032780
Short name T826
Test name
Test status
Simulation time 129089379 ps
CPU time 0.94 seconds
Started Jun 13 01:48:49 PM PDT 24
Finished Jun 13 01:48:51 PM PDT 24
Peak memory 206440 kb
Host smart-142f7581-dc69-4f3b-8167-c47635a61552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220032780 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1220032780
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2804481620
Short name T59
Test name
Test status
Simulation time 256641486 ps
CPU time 4.44 seconds
Started Jun 13 01:48:53 PM PDT 24
Finished Jun 13 01:48:59 PM PDT 24
Peak memory 235568 kb
Host smart-76a484b2-e328-4484-8576-4930b1367fb2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804481620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2804481620
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.4052869120
Short name T538
Test name
Test status
Simulation time 20459500 ps
CPU time 1 seconds
Started Jun 13 01:48:46 PM PDT 24
Finished Jun 13 01:48:48 PM PDT 24
Peak memory 214640 kb
Host smart-33fa680a-c54a-40a5-9d1d-bd1e8d7bb87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052869120 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.4052869120
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2981278777
Short name T469
Test name
Test status
Simulation time 95277777 ps
CPU time 2.45 seconds
Started Jun 13 01:48:51 PM PDT 24
Finished Jun 13 01:48:54 PM PDT 24
Peak memory 216592 kb
Host smart-8081f162-7814-4f7d-9759-22632abe4d2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981278777 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2981278777
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2691268830
Short name T822
Test name
Test status
Simulation time 184370525260 ps
CPU time 1118.44 seconds
Started Jun 13 01:48:45 PM PDT 24
Finished Jun 13 02:07:24 PM PDT 24
Peak memory 223412 kb
Host smart-dd29104a-89c4-4b04-9ab6-780842cde753
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691268830 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2691268830
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.794976332
Short name T484
Test name
Test status
Simulation time 26095942 ps
CPU time 0.9 seconds
Started Jun 13 01:48:46 PM PDT 24
Finished Jun 13 01:48:48 PM PDT 24
Peak memory 214328 kb
Host smart-9fffcfc9-956b-4fad-93db-8986e5832e3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794976332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.794976332
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.1288197019
Short name T171
Test name
Test status
Simulation time 20512843 ps
CPU time 0.86 seconds
Started Jun 13 01:48:47 PM PDT 24
Finished Jun 13 01:48:49 PM PDT 24
Peak memory 215692 kb
Host smart-6c06d7eb-18fa-46b1-a290-6adf99743141
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288197019 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1288197019
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.2490649016
Short name T901
Test name
Test status
Simulation time 25709908 ps
CPU time 1.24 seconds
Started Jun 13 01:48:47 PM PDT 24
Finished Jun 13 01:48:50 PM PDT 24
Peak memory 217764 kb
Host smart-706511b6-6740-46e0-b774-1f5dfd872e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490649016 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2490649016
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3338980799
Short name T399
Test name
Test status
Simulation time 37178158 ps
CPU time 1.4 seconds
Started Jun 13 01:48:48 PM PDT 24
Finished Jun 13 01:48:50 PM PDT 24
Peak memory 217812 kb
Host smart-ef737131-6afe-47d3-9514-5c089aaa2db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338980799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3338980799
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.620963980
Short name T377
Test name
Test status
Simulation time 46185753 ps
CPU time 0.94 seconds
Started Jun 13 01:48:51 PM PDT 24
Finished Jun 13 01:48:53 PM PDT 24
Peak memory 214744 kb
Host smart-524d19ce-e9dc-4f98-af1d-d5bd81013eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620963980 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.620963980
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.2448789979
Short name T506
Test name
Test status
Simulation time 38664115 ps
CPU time 0.93 seconds
Started Jun 13 01:48:47 PM PDT 24
Finished Jun 13 01:48:49 PM PDT 24
Peak memory 206428 kb
Host smart-1f6cd22a-07b0-4f2a-b222-d1b21b21d84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448789979 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2448789979
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.1294747208
Short name T335
Test name
Test status
Simulation time 17545189 ps
CPU time 0.98 seconds
Started Jun 13 01:48:47 PM PDT 24
Finished Jun 13 01:48:48 PM PDT 24
Peak memory 214608 kb
Host smart-b9c4c06b-a90b-4cea-ae16-5ce4f394eac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294747208 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1294747208
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1866207116
Short name T234
Test name
Test status
Simulation time 20327500 ps
CPU time 1.03 seconds
Started Jun 13 01:48:53 PM PDT 24
Finished Jun 13 01:48:56 PM PDT 24
Peak memory 205840 kb
Host smart-dd392ef7-f2f0-4ab2-96f9-c87a9aca6a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866207116 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1866207116
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2096707478
Short name T869
Test name
Test status
Simulation time 46400721908 ps
CPU time 1125.97 seconds
Started Jun 13 01:48:47 PM PDT 24
Finished Jun 13 02:07:34 PM PDT 24
Peak memory 222912 kb
Host smart-80bf2d48-dcf4-40a3-8cc4-b53aa52d3213
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096707478 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2096707478
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1234274726
Short name T963
Test name
Test status
Simulation time 24255056 ps
CPU time 1.21 seconds
Started Jun 13 01:49:11 PM PDT 24
Finished Jun 13 01:49:13 PM PDT 24
Peak memory 220028 kb
Host smart-d09b0ce6-53fc-4a7b-9aa4-bbcbe83eac22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234274726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1234274726
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3324129716
Short name T872
Test name
Test status
Simulation time 161002007 ps
CPU time 1.23 seconds
Started Jun 13 01:49:11 PM PDT 24
Finished Jun 13 01:49:13 PM PDT 24
Peak memory 216236 kb
Host smart-00165980-a75f-4a01-a007-4b3dd6a01322
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324129716 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3324129716
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.3410642569
Short name T780
Test name
Test status
Simulation time 53445979 ps
CPU time 0.99 seconds
Started Jun 13 01:49:12 PM PDT 24
Finished Jun 13 01:49:15 PM PDT 24
Peak memory 218096 kb
Host smart-0020de9f-7fdc-45fc-a16f-533107a0dfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410642569 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3410642569
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3363239337
Short name T402
Test name
Test status
Simulation time 103139515 ps
CPU time 1.17 seconds
Started Jun 13 01:49:12 PM PDT 24
Finished Jun 13 01:49:14 PM PDT 24
Peak memory 216576 kb
Host smart-ee25c20a-73cf-4153-a124-da75d032332e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363239337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3363239337
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3303193986
Short name T777
Test name
Test status
Simulation time 24543997 ps
CPU time 1.11 seconds
Started Jun 13 01:49:12 PM PDT 24
Finished Jun 13 01:49:15 PM PDT 24
Peak memory 214752 kb
Host smart-af715f41-cbe7-4a39-bc5d-fd9bc025a997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303193986 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3303193986
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1707794962
Short name T604
Test name
Test status
Simulation time 26024261 ps
CPU time 0.96 seconds
Started Jun 13 01:49:13 PM PDT 24
Finished Jun 13 01:49:16 PM PDT 24
Peak memory 214616 kb
Host smart-76cc87bf-db41-4e27-80e5-27c8cd1a8402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707794962 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1707794962
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.549726177
Short name T638
Test name
Test status
Simulation time 428524413 ps
CPU time 4.98 seconds
Started Jun 13 01:49:14 PM PDT 24
Finished Jun 13 01:49:20 PM PDT 24
Peak memory 218000 kb
Host smart-a7d32a7d-d853-4a38-a5af-654129ffe1ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549726177 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.549726177
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1534493818
Short name T41
Test name
Test status
Simulation time 34403455925 ps
CPU time 396.58 seconds
Started Jun 13 01:49:11 PM PDT 24
Finished Jun 13 01:55:49 PM PDT 24
Peak memory 218380 kb
Host smart-9ad70bca-614a-45c5-8c18-3530843af898
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534493818 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1534493818
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.1670925051
Short name T598
Test name
Test status
Simulation time 88865560 ps
CPU time 1.12 seconds
Started Jun 13 01:51:05 PM PDT 24
Finished Jun 13 01:51:08 PM PDT 24
Peak memory 216728 kb
Host smart-72f8049b-53fe-4797-b94a-7e97f300b092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670925051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1670925051
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.503684020
Short name T737
Test name
Test status
Simulation time 224806599 ps
CPU time 1.4 seconds
Started Jun 13 01:51:06 PM PDT 24
Finished Jun 13 01:51:10 PM PDT 24
Peak memory 217864 kb
Host smart-50b7eba3-f0bb-480e-a346-a1a4cc31e8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503684020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.503684020
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.599348238
Short name T348
Test name
Test status
Simulation time 51303935 ps
CPU time 1.27 seconds
Started Jun 13 01:51:06 PM PDT 24
Finished Jun 13 01:51:09 PM PDT 24
Peak memory 217988 kb
Host smart-e51315cc-59b5-4725-9c4a-6d73e68aeaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599348238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.599348238
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.3906403902
Short name T295
Test name
Test status
Simulation time 42203268 ps
CPU time 1.2 seconds
Started Jun 13 01:51:11 PM PDT 24
Finished Jun 13 01:51:13 PM PDT 24
Peak memory 219256 kb
Host smart-13c96221-6c9c-4345-b4da-6d889fe601dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906403902 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.3906403902
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.3570069841
Short name T487
Test name
Test status
Simulation time 53888347 ps
CPU time 1.61 seconds
Started Jun 13 01:51:11 PM PDT 24
Finished Jun 13 01:51:13 PM PDT 24
Peak memory 217788 kb
Host smart-dfba1394-e7a3-414b-aae3-07811b97107b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570069841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3570069841
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.592062396
Short name T152
Test name
Test status
Simulation time 263820352 ps
CPU time 1.36 seconds
Started Jun 13 01:51:12 PM PDT 24
Finished Jun 13 01:51:15 PM PDT 24
Peak memory 215072 kb
Host smart-3beccbdc-0c75-4ea7-94d4-bd3b5bdfc379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592062396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.592062396
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.3001945242
Short name T696
Test name
Test status
Simulation time 230422592 ps
CPU time 1.78 seconds
Started Jun 13 01:51:10 PM PDT 24
Finished Jun 13 01:51:12 PM PDT 24
Peak memory 218008 kb
Host smart-a1d9b403-f935-46e0-80a3-8147621dcce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001945242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3001945242
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.2623786744
Short name T384
Test name
Test status
Simulation time 49042303 ps
CPU time 1.12 seconds
Started Jun 13 01:51:12 PM PDT 24
Finished Jun 13 01:51:14 PM PDT 24
Peak memory 218676 kb
Host smart-6b55ae50-7405-475a-909d-7961694ac998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623786744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.2623786744
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.122055048
Short name T429
Test name
Test status
Simulation time 86994333 ps
CPU time 1.48 seconds
Started Jun 13 01:51:12 PM PDT 24
Finished Jun 13 01:51:14 PM PDT 24
Peak memory 216812 kb
Host smart-9bde2af1-2392-42de-bd5d-cb64c4c8ec78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122055048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.122055048
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.3953879041
Short name T471
Test name
Test status
Simulation time 95514004 ps
CPU time 1.22 seconds
Started Jun 13 01:51:11 PM PDT 24
Finished Jun 13 01:51:13 PM PDT 24
Peak memory 214972 kb
Host smart-a25a6012-23af-4512-884a-991237a2594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953879041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.3953879041
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/106.edn_alert.3601201757
Short name T663
Test name
Test status
Simulation time 60597976 ps
CPU time 1.29 seconds
Started Jun 13 01:51:12 PM PDT 24
Finished Jun 13 01:51:14 PM PDT 24
Peak memory 218736 kb
Host smart-19b018f5-b4c1-4dd1-8fcc-69567e0b9809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601201757 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3601201757
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.1468027568
Short name T950
Test name
Test status
Simulation time 49031990 ps
CPU time 1.28 seconds
Started Jun 13 01:51:10 PM PDT 24
Finished Jun 13 01:51:13 PM PDT 24
Peak memory 218712 kb
Host smart-b432072a-9113-4a2c-b6ea-b1ae229ee0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468027568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1468027568
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.3051020101
Short name T624
Test name
Test status
Simulation time 25249574 ps
CPU time 1.17 seconds
Started Jun 13 01:51:11 PM PDT 24
Finished Jun 13 01:51:13 PM PDT 24
Peak memory 219132 kb
Host smart-211775e8-25ac-467e-9a85-a1d7961cff44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051020101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.3051020101
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.2057001478
Short name T764
Test name
Test status
Simulation time 74518416 ps
CPU time 1.23 seconds
Started Jun 13 01:51:14 PM PDT 24
Finished Jun 13 01:51:16 PM PDT 24
Peak memory 216688 kb
Host smart-bcb2a319-ac16-497c-a91c-4ef427c83d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057001478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2057001478
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.3973705128
Short name T784
Test name
Test status
Simulation time 70840542 ps
CPU time 1.14 seconds
Started Jun 13 01:51:11 PM PDT 24
Finished Jun 13 01:51:13 PM PDT 24
Peak memory 218120 kb
Host smart-9087c494-9b7b-40d5-a174-8397c085c04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973705128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.3973705128
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.3930976820
Short name T532
Test name
Test status
Simulation time 33730354 ps
CPU time 1.14 seconds
Started Jun 13 01:51:10 PM PDT 24
Finished Jun 13 01:51:12 PM PDT 24
Peak memory 216488 kb
Host smart-f1033880-847e-422d-b945-b2e0a555dc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930976820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3930976820
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.673887272
Short name T568
Test name
Test status
Simulation time 137403140 ps
CPU time 1.43 seconds
Started Jun 13 01:51:19 PM PDT 24
Finished Jun 13 01:51:21 PM PDT 24
Peak memory 218096 kb
Host smart-a79603f0-d743-43a2-a3cb-0f93e8459a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673887272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.673887272
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.2394842585
Short name T679
Test name
Test status
Simulation time 139394319 ps
CPU time 0.92 seconds
Started Jun 13 01:49:19 PM PDT 24
Finished Jun 13 01:49:21 PM PDT 24
Peak memory 214160 kb
Host smart-d6500c53-3d0b-4bcd-9210-2c149ce9c4ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394842585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2394842585
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.1004096831
Short name T702
Test name
Test status
Simulation time 10574597 ps
CPU time 0.85 seconds
Started Jun 13 01:49:18 PM PDT 24
Finished Jun 13 01:49:20 PM PDT 24
Peak memory 215444 kb
Host smart-ab71033c-5142-45aa-865f-e6db4bd27b30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004096831 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1004096831
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.2956118804
Short name T108
Test name
Test status
Simulation time 92703927 ps
CPU time 0.95 seconds
Started Jun 13 01:49:19 PM PDT 24
Finished Jun 13 01:49:21 PM PDT 24
Peak memory 218860 kb
Host smart-f53b49dd-1a4a-45d7-a02d-a73da8057f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956118804 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2956118804
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.2454283922
Short name T97
Test name
Test status
Simulation time 22281395 ps
CPU time 0.92 seconds
Started Jun 13 01:49:19 PM PDT 24
Finished Jun 13 01:49:21 PM PDT 24
Peak memory 215084 kb
Host smart-984b800b-5eb4-43f0-9222-71c55fa5725a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454283922 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2454283922
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1630057683
Short name T738
Test name
Test status
Simulation time 18137158 ps
CPU time 1.07 seconds
Started Jun 13 01:49:15 PM PDT 24
Finished Jun 13 01:49:17 PM PDT 24
Peak memory 214600 kb
Host smart-867d1a66-da40-4d00-881d-02a4c8f11589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630057683 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1630057683
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1509494049
Short name T887
Test name
Test status
Simulation time 523162227 ps
CPU time 3.45 seconds
Started Jun 13 01:49:25 PM PDT 24
Finished Jun 13 01:49:29 PM PDT 24
Peak memory 216612 kb
Host smart-9bcdcd19-4482-4c30-9965-e5e944ef7a16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509494049 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1509494049
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.362115047
Short name T391
Test name
Test status
Simulation time 229281188168 ps
CPU time 1282.05 seconds
Started Jun 13 01:49:21 PM PDT 24
Finished Jun 13 02:10:45 PM PDT 24
Peak memory 223132 kb
Host smart-b5d74da6-10af-45bb-8c3f-bc4319327d2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362115047 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.362115047
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.2587931835
Short name T626
Test name
Test status
Simulation time 27984992 ps
CPU time 1.21 seconds
Started Jun 13 01:51:20 PM PDT 24
Finished Jun 13 01:51:22 PM PDT 24
Peak memory 217792 kb
Host smart-ba18c89c-f015-4170-a025-5478e21c6473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587931835 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.2587931835
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.1472332298
Short name T355
Test name
Test status
Simulation time 47702448 ps
CPU time 1.42 seconds
Started Jun 13 01:51:19 PM PDT 24
Finished Jun 13 01:51:22 PM PDT 24
Peak memory 218044 kb
Host smart-a01ac79a-fd6e-43f7-97fe-816b35ae8c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472332298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1472332298
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.514869535
Short name T786
Test name
Test status
Simulation time 63464423 ps
CPU time 1.1 seconds
Started Jun 13 01:51:20 PM PDT 24
Finished Jun 13 01:51:22 PM PDT 24
Peak memory 217960 kb
Host smart-eb485e73-a24a-4cc2-890c-56b5663f28e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514869535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.514869535
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.2868392062
Short name T479
Test name
Test status
Simulation time 35504681 ps
CPU time 1.55 seconds
Started Jun 13 01:51:17 PM PDT 24
Finished Jun 13 01:51:19 PM PDT 24
Peak memory 217812 kb
Host smart-2e1b1025-05a9-4ed7-8d59-68c708323c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868392062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2868392062
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.152909020
Short name T870
Test name
Test status
Simulation time 43250244 ps
CPU time 1.19 seconds
Started Jun 13 01:51:17 PM PDT 24
Finished Jun 13 01:51:19 PM PDT 24
Peak memory 220164 kb
Host smart-d5b8475d-8c02-455e-a7ee-cd584db19231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152909020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.152909020
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/113.edn_alert.1592585493
Short name T162
Test name
Test status
Simulation time 43521737 ps
CPU time 1.19 seconds
Started Jun 13 01:51:18 PM PDT 24
Finished Jun 13 01:51:21 PM PDT 24
Peak memory 217944 kb
Host smart-660f93ec-741f-46a8-98d8-2ac1aa6860ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592585493 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.1592585493
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/114.edn_alert.3637758541
Short name T523
Test name
Test status
Simulation time 27336230 ps
CPU time 1.23 seconds
Started Jun 13 01:51:18 PM PDT 24
Finished Jun 13 01:51:20 PM PDT 24
Peak memory 219056 kb
Host smart-482b2986-8dc0-4768-8ad7-005d4cb00199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637758541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3637758541
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.2576687196
Short name T22
Test name
Test status
Simulation time 496883452 ps
CPU time 4.08 seconds
Started Jun 13 01:51:23 PM PDT 24
Finished Jun 13 01:51:28 PM PDT 24
Peak memory 219672 kb
Host smart-9329510b-06e6-4f18-9dee-99ee47e109dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576687196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2576687196
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.660268661
Short name T86
Test name
Test status
Simulation time 45740954 ps
CPU time 1.15 seconds
Started Jun 13 01:51:17 PM PDT 24
Finished Jun 13 01:51:19 PM PDT 24
Peak memory 218176 kb
Host smart-8bad3d27-a6d7-45db-9e64-ce7bdfe9712a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660268661 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.660268661
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.1609883225
Short name T915
Test name
Test status
Simulation time 44772852 ps
CPU time 1.51 seconds
Started Jun 13 01:51:19 PM PDT 24
Finished Jun 13 01:51:22 PM PDT 24
Peak memory 217840 kb
Host smart-8574b33c-5b2b-4e77-946f-b571befa103a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609883225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1609883225
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.1971481458
Short name T294
Test name
Test status
Simulation time 52458977 ps
CPU time 1.13 seconds
Started Jun 13 01:51:22 PM PDT 24
Finished Jun 13 01:51:24 PM PDT 24
Peak memory 219064 kb
Host smart-254b3e4f-462d-47e4-8243-fe5dec879110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971481458 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.1971481458
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/117.edn_alert.1012954730
Short name T957
Test name
Test status
Simulation time 92919019 ps
CPU time 1.27 seconds
Started Jun 13 01:51:24 PM PDT 24
Finished Jun 13 01:51:27 PM PDT 24
Peak memory 217708 kb
Host smart-c8cf4626-5d69-441d-b295-546b68caa9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012954730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1012954730
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.3393854027
Short name T934
Test name
Test status
Simulation time 58550782 ps
CPU time 1.23 seconds
Started Jun 13 01:51:22 PM PDT 24
Finished Jun 13 01:51:24 PM PDT 24
Peak memory 216684 kb
Host smart-6c00556c-5b77-4156-95bb-ca4c10556624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393854027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3393854027
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.2364985615
Short name T139
Test name
Test status
Simulation time 26937013 ps
CPU time 1.21 seconds
Started Jun 13 01:51:24 PM PDT 24
Finished Jun 13 01:51:27 PM PDT 24
Peak memory 217808 kb
Host smart-663c5510-3730-4f6a-98ad-ec4294aa217e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364985615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.2364985615
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert.2989970554
Short name T931
Test name
Test status
Simulation time 32211995 ps
CPU time 1.17 seconds
Started Jun 13 01:49:19 PM PDT 24
Finished Jun 13 01:49:22 PM PDT 24
Peak memory 219032 kb
Host smart-f9e172ed-d209-491f-b977-97a0d9801a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989970554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2989970554
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.4206353682
Short name T884
Test name
Test status
Simulation time 28883990 ps
CPU time 0.94 seconds
Started Jun 13 01:49:20 PM PDT 24
Finished Jun 13 01:49:22 PM PDT 24
Peak memory 214268 kb
Host smart-7cd8992e-3680-42ea-b443-956a2719440c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206353682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.4206353682
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.3391024628
Short name T206
Test name
Test status
Simulation time 18338611 ps
CPU time 0.86 seconds
Started Jun 13 01:49:21 PM PDT 24
Finished Jun 13 01:49:23 PM PDT 24
Peak memory 215680 kb
Host smart-d150da20-2149-4084-bc60-4dc1b9d1748c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391024628 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3391024628
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3920000244
Short name T114
Test name
Test status
Simulation time 100095089 ps
CPU time 1.08 seconds
Started Jun 13 01:49:19 PM PDT 24
Finished Jun 13 01:49:21 PM PDT 24
Peak memory 216288 kb
Host smart-36581e84-5c4e-4e75-af78-4fdac658e930
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920000244 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3920000244
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.2023614155
Short name T592
Test name
Test status
Simulation time 25092328 ps
CPU time 1.2 seconds
Started Jun 13 01:49:20 PM PDT 24
Finished Jun 13 01:49:23 PM PDT 24
Peak memory 216960 kb
Host smart-2b507d88-8178-4648-9275-526677fc5efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023614155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2023614155
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1683173518
Short name T589
Test name
Test status
Simulation time 100395527 ps
CPU time 1.39 seconds
Started Jun 13 01:49:19 PM PDT 24
Finished Jun 13 01:49:21 PM PDT 24
Peak memory 216712 kb
Host smart-d571ee99-65e8-46ad-96c2-01a80b2481da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683173518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1683173518
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1825344831
Short name T925
Test name
Test status
Simulation time 110370875 ps
CPU time 0.88 seconds
Started Jun 13 01:49:19 PM PDT 24
Finished Jun 13 01:49:21 PM PDT 24
Peak memory 214808 kb
Host smart-32ca42a0-b14c-4404-9539-9ffc7629716d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825344831 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1825344831
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.3632194857
Short name T705
Test name
Test status
Simulation time 16681120 ps
CPU time 0.98 seconds
Started Jun 13 01:49:18 PM PDT 24
Finished Jun 13 01:49:20 PM PDT 24
Peak memory 214636 kb
Host smart-576adc52-6f1b-403a-939f-bef28c033d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632194857 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3632194857
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3285327364
Short name T736
Test name
Test status
Simulation time 89432753 ps
CPU time 1.17 seconds
Started Jun 13 01:49:22 PM PDT 24
Finished Jun 13 01:49:24 PM PDT 24
Peak memory 214724 kb
Host smart-ec047dc9-69da-42cf-9fae-424cf5224d84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285327364 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3285327364
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.974637138
Short name T530
Test name
Test status
Simulation time 131339974004 ps
CPU time 2977.58 seconds
Started Jun 13 01:49:18 PM PDT 24
Finished Jun 13 02:38:56 PM PDT 24
Peak memory 230944 kb
Host smart-7acf21c0-59e0-4ebb-b254-6109d2975aa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974637138 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.974637138
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.3394275206
Short name T685
Test name
Test status
Simulation time 67988312 ps
CPU time 1.15 seconds
Started Jun 13 01:51:27 PM PDT 24
Finished Jun 13 01:51:30 PM PDT 24
Peak memory 218192 kb
Host smart-ba78b033-dafa-4cc0-a9f0-37614fbd21c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394275206 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.3394275206
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.4210821144
Short name T880
Test name
Test status
Simulation time 71433693 ps
CPU time 1.05 seconds
Started Jun 13 01:51:26 PM PDT 24
Finished Jun 13 01:51:28 PM PDT 24
Peak memory 216612 kb
Host smart-b4b566f2-e3ae-44c7-bdeb-547d310087b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210821144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.4210821144
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.649902682
Short name T316
Test name
Test status
Simulation time 40710489 ps
CPU time 1.16 seconds
Started Jun 13 01:51:23 PM PDT 24
Finished Jun 13 01:51:25 PM PDT 24
Peak memory 216560 kb
Host smart-77b85036-c33e-4ace-8f9d-277147613288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649902682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.649902682
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.2451720650
Short name T757
Test name
Test status
Simulation time 271835849 ps
CPU time 1.11 seconds
Started Jun 13 01:51:25 PM PDT 24
Finished Jun 13 01:51:28 PM PDT 24
Peak memory 219508 kb
Host smart-55d33a1b-3835-4d4e-bba6-3befcd6eb86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451720650 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.2451720650
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.3083017067
Short name T551
Test name
Test status
Simulation time 51836869 ps
CPU time 1.42 seconds
Started Jun 13 01:51:23 PM PDT 24
Finished Jun 13 01:51:25 PM PDT 24
Peak memory 218080 kb
Host smart-3ce43ebe-dd83-4f96-af50-02af570122e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083017067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3083017067
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.1590584301
Short name T617
Test name
Test status
Simulation time 71135975 ps
CPU time 1.15 seconds
Started Jun 13 01:51:23 PM PDT 24
Finished Jun 13 01:51:25 PM PDT 24
Peak memory 218848 kb
Host smart-c2430039-6295-4934-bd6a-166b76a67909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590584301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.1590584301
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.499594403
Short name T63
Test name
Test status
Simulation time 65501282 ps
CPU time 1.42 seconds
Started Jun 13 01:51:24 PM PDT 24
Finished Jun 13 01:51:26 PM PDT 24
Peak memory 217728 kb
Host smart-de2990bd-f060-4acc-8e81-a241c6f673bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499594403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.499594403
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.3319412952
Short name T138
Test name
Test status
Simulation time 49613575 ps
CPU time 1.16 seconds
Started Jun 13 01:51:23 PM PDT 24
Finished Jun 13 01:51:25 PM PDT 24
Peak memory 220108 kb
Host smart-bec35e66-22f8-4957-aa6c-6f77ab72fab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319412952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.3319412952
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.677120556
Short name T850
Test name
Test status
Simulation time 40265016 ps
CPU time 1.59 seconds
Started Jun 13 01:51:23 PM PDT 24
Finished Jun 13 01:51:25 PM PDT 24
Peak memory 217704 kb
Host smart-acd60949-cd99-4623-8056-1e37818017f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677120556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.677120556
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.4194955911
Short name T88
Test name
Test status
Simulation time 60646145 ps
CPU time 1.17 seconds
Started Jun 13 01:51:23 PM PDT 24
Finished Jun 13 01:51:25 PM PDT 24
Peak memory 216600 kb
Host smart-949fde59-3701-4bf7-b028-5c3ebef03157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194955911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.4194955911
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.1924053371
Short name T824
Test name
Test status
Simulation time 161829902 ps
CPU time 1.25 seconds
Started Jun 13 01:51:24 PM PDT 24
Finished Jun 13 01:51:27 PM PDT 24
Peak memory 218980 kb
Host smart-1ff75299-b18c-4f9c-94da-b9205c38df71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924053371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.1924053371
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/127.edn_alert.1900272634
Short name T769
Test name
Test status
Simulation time 105462265 ps
CPU time 1.19 seconds
Started Jun 13 01:51:25 PM PDT 24
Finished Jun 13 01:51:28 PM PDT 24
Peak memory 218012 kb
Host smart-85b261c4-57ae-4003-8dfd-f53e5bd2e709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900272634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.1900272634
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.2863689770
Short name T972
Test name
Test status
Simulation time 328874923 ps
CPU time 1.78 seconds
Started Jun 13 01:51:25 PM PDT 24
Finished Jun 13 01:51:28 PM PDT 24
Peak memory 218168 kb
Host smart-97193c88-40ec-4aa3-bca1-ca32033cab23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863689770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2863689770
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.132982200
Short name T57
Test name
Test status
Simulation time 267078277 ps
CPU time 1.38 seconds
Started Jun 13 01:51:27 PM PDT 24
Finished Jun 13 01:51:30 PM PDT 24
Peak memory 217824 kb
Host smart-ed6038e1-fdd1-4a42-9a00-93110fca001a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132982200 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.132982200
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.353204071
Short name T13
Test name
Test status
Simulation time 63834091 ps
CPU time 1.2 seconds
Started Jun 13 01:51:24 PM PDT 24
Finished Jun 13 01:51:26 PM PDT 24
Peak memory 216816 kb
Host smart-26f50611-0e0b-47d4-8585-495d557c8121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353204071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.353204071
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.3950005874
Short name T511
Test name
Test status
Simulation time 23422602 ps
CPU time 1.24 seconds
Started Jun 13 01:51:24 PM PDT 24
Finished Jun 13 01:51:26 PM PDT 24
Peak memory 219144 kb
Host smart-33e80761-ea15-42a4-969d-2b1c0866d79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950005874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.3950005874
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.3157913360
Short name T978
Test name
Test status
Simulation time 44698564 ps
CPU time 1.53 seconds
Started Jun 13 01:51:22 PM PDT 24
Finished Jun 13 01:51:24 PM PDT 24
Peak memory 217908 kb
Host smart-aa56331c-4926-4306-99be-ced9fc0a991a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157913360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3157913360
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1100232144
Short name T947
Test name
Test status
Simulation time 23829654 ps
CPU time 1.14 seconds
Started Jun 13 01:49:18 PM PDT 24
Finished Jun 13 01:49:20 PM PDT 24
Peak memory 218940 kb
Host smart-38e2213b-af30-41cc-8a62-cd8e95bc1b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100232144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1100232144
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3574308555
Short name T828
Test name
Test status
Simulation time 25177780 ps
CPU time 0.93 seconds
Started Jun 13 01:49:19 PM PDT 24
Finished Jun 13 01:49:21 PM PDT 24
Peak memory 206040 kb
Host smart-43d1eb4e-0d09-4325-bdb8-0dc1d0ab4062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574308555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3574308555
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3192372008
Short name T213
Test name
Test status
Simulation time 12731838 ps
CPU time 0.92 seconds
Started Jun 13 01:49:20 PM PDT 24
Finished Jun 13 01:49:22 PM PDT 24
Peak memory 215960 kb
Host smart-c7a10965-88fd-41f5-812e-be9613e679d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192372008 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3192372008
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3113607574
Short name T144
Test name
Test status
Simulation time 53507707 ps
CPU time 1.18 seconds
Started Jun 13 01:49:17 PM PDT 24
Finished Jun 13 01:49:19 PM PDT 24
Peak memory 216152 kb
Host smart-a6a61ab6-62ba-485e-bf9c-016e91ce487f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113607574 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3113607574
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_genbits.3783646970
Short name T690
Test name
Test status
Simulation time 85784499 ps
CPU time 2.89 seconds
Started Jun 13 01:49:21 PM PDT 24
Finished Jun 13 01:49:25 PM PDT 24
Peak memory 219456 kb
Host smart-d9a5baba-6c6e-4bd7-9a7b-178bfc7e0333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783646970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3783646970
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.638905121
Short name T107
Test name
Test status
Simulation time 19620200 ps
CPU time 1.07 seconds
Started Jun 13 01:49:17 PM PDT 24
Finished Jun 13 01:49:19 PM PDT 24
Peak memory 215036 kb
Host smart-9e368673-16dd-475d-aeb4-68a1c6532dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638905121 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.638905121
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1690564274
Short name T472
Test name
Test status
Simulation time 17826307 ps
CPU time 1.01 seconds
Started Jun 13 01:49:20 PM PDT 24
Finished Jun 13 01:49:22 PM PDT 24
Peak memory 214648 kb
Host smart-25e4f853-ff3f-4c97-9f96-e01a3baf9c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690564274 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1690564274
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3609875947
Short name T854
Test name
Test status
Simulation time 41089521665 ps
CPU time 646.88 seconds
Started Jun 13 01:49:20 PM PDT 24
Finished Jun 13 02:00:08 PM PDT 24
Peak memory 216688 kb
Host smart-f71c5d73-cd45-4906-8d81-036efff6c467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609875947 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3609875947
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.103020264
Short name T788
Test name
Test status
Simulation time 51246085 ps
CPU time 1.08 seconds
Started Jun 13 01:51:25 PM PDT 24
Finished Jun 13 01:51:27 PM PDT 24
Peak memory 218996 kb
Host smart-d61ddd8e-b152-4da9-ae07-23b8c8db9a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103020264 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.103020264
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.2150574789
Short name T27
Test name
Test status
Simulation time 149611804 ps
CPU time 1.08 seconds
Started Jun 13 01:51:24 PM PDT 24
Finished Jun 13 01:51:27 PM PDT 24
Peak memory 216612 kb
Host smart-a244c15b-6c84-4b16-85bf-928403aff671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150574789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2150574789
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.3902237171
Short name T875
Test name
Test status
Simulation time 99952068 ps
CPU time 1.7 seconds
Started Jun 13 01:51:24 PM PDT 24
Finished Jun 13 01:51:28 PM PDT 24
Peak memory 217996 kb
Host smart-8e698eaa-073a-4b94-b496-fab59bdfb587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902237171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3902237171
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.3053047188
Short name T776
Test name
Test status
Simulation time 107992432 ps
CPU time 1.21 seconds
Started Jun 13 01:51:25 PM PDT 24
Finished Jun 13 01:51:27 PM PDT 24
Peak memory 218124 kb
Host smart-2051c0be-e73e-442a-8f29-e4a2c85aab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053047188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.3053047188
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.3247002625
Short name T516
Test name
Test status
Simulation time 86607565 ps
CPU time 1.43 seconds
Started Jun 13 01:51:26 PM PDT 24
Finished Jun 13 01:51:29 PM PDT 24
Peak memory 218312 kb
Host smart-086556b2-bd94-425e-bd84-78966a44f550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247002625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3247002625
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.2998029783
Short name T145
Test name
Test status
Simulation time 81079965 ps
CPU time 1.16 seconds
Started Jun 13 01:51:25 PM PDT 24
Finished Jun 13 01:51:28 PM PDT 24
Peak memory 217920 kb
Host smart-25b0a6f2-bd96-4153-a92c-4de466700dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998029783 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.2998029783
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.3816547490
Short name T362
Test name
Test status
Simulation time 60511728 ps
CPU time 1.24 seconds
Started Jun 13 01:51:25 PM PDT 24
Finished Jun 13 01:51:28 PM PDT 24
Peak memory 216760 kb
Host smart-bf01cf1c-44ef-42e9-9543-96e389c7ecae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816547490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3816547490
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3600066017
Short name T455
Test name
Test status
Simulation time 55374254 ps
CPU time 1.66 seconds
Started Jun 13 01:51:23 PM PDT 24
Finished Jun 13 01:51:26 PM PDT 24
Peak memory 217812 kb
Host smart-2cf3e988-b0b0-4bb3-8f6e-f70b963af584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600066017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3600066017
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.1925037751
Short name T691
Test name
Test status
Simulation time 96916743 ps
CPU time 1.17 seconds
Started Jun 13 01:51:27 PM PDT 24
Finished Jun 13 01:51:30 PM PDT 24
Peak memory 218488 kb
Host smart-290434aa-fa44-480a-bb7d-6c96fe43529a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925037751 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.1925037751
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.456388843
Short name T730
Test name
Test status
Simulation time 83282850 ps
CPU time 3.08 seconds
Started Jun 13 01:51:22 PM PDT 24
Finished Jun 13 01:51:26 PM PDT 24
Peak memory 216976 kb
Host smart-4ee4d354-2f98-4a6e-a4a9-0166d749fca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456388843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.456388843
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.1325828907
Short name T939
Test name
Test status
Simulation time 70591587 ps
CPU time 1.17 seconds
Started Jun 13 01:51:27 PM PDT 24
Finished Jun 13 01:51:29 PM PDT 24
Peak memory 217988 kb
Host smart-9b1e66b4-e257-4c47-85d5-814fb29ebe51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325828907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1325828907
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.214256872
Short name T961
Test name
Test status
Simulation time 40098051 ps
CPU time 1.51 seconds
Started Jun 13 01:51:28 PM PDT 24
Finished Jun 13 01:51:30 PM PDT 24
Peak memory 217808 kb
Host smart-5e763675-d053-487e-9ce2-dba872502ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214256872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.214256872
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.2266978268
Short name T976
Test name
Test status
Simulation time 72919516 ps
CPU time 1.12 seconds
Started Jun 13 01:51:27 PM PDT 24
Finished Jun 13 01:51:29 PM PDT 24
Peak memory 217976 kb
Host smart-9bc3f335-1f1a-4952-99c2-8577073f09bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266978268 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.2266978268
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.2141939776
Short name T773
Test name
Test status
Simulation time 106778889 ps
CPU time 1.24 seconds
Started Jun 13 01:51:28 PM PDT 24
Finished Jun 13 01:51:30 PM PDT 24
Peak memory 219308 kb
Host smart-9401810e-d280-4563-bed6-2d3931ddb395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141939776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2141939776
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.1554981279
Short name T161
Test name
Test status
Simulation time 73870395 ps
CPU time 1.2 seconds
Started Jun 13 01:51:28 PM PDT 24
Finished Jun 13 01:51:30 PM PDT 24
Peak memory 219432 kb
Host smart-bd82d951-efe5-4061-acd0-dce0604da28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554981279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.1554981279
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.2054301782
Short name T594
Test name
Test status
Simulation time 89464714 ps
CPU time 1.16 seconds
Started Jun 13 01:51:27 PM PDT 24
Finished Jun 13 01:51:29 PM PDT 24
Peak memory 216576 kb
Host smart-c9b5f78b-c864-4f27-924f-f8399a25b555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054301782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2054301782
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.2157988632
Short name T789
Test name
Test status
Simulation time 87880023 ps
CPU time 1.12 seconds
Started Jun 13 01:51:35 PM PDT 24
Finished Jun 13 01:51:37 PM PDT 24
Peak memory 218080 kb
Host smart-28600904-a410-4b38-b304-770d1b6ef6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157988632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.2157988632
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.1062567494
Short name T498
Test name
Test status
Simulation time 85925924 ps
CPU time 1.21 seconds
Started Jun 13 01:51:26 PM PDT 24
Finished Jun 13 01:51:29 PM PDT 24
Peak memory 216776 kb
Host smart-74edf581-5188-4d19-86bf-5a4c14e6ef86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062567494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1062567494
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1537278993
Short name T127
Test name
Test status
Simulation time 24337920 ps
CPU time 1.25 seconds
Started Jun 13 01:49:22 PM PDT 24
Finished Jun 13 01:49:24 PM PDT 24
Peak memory 219112 kb
Host smart-7d1f6558-33b9-45a2-9558-118c95922cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537278993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1537278993
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3381570120
Short name T346
Test name
Test status
Simulation time 18256254 ps
CPU time 0.89 seconds
Started Jun 13 01:49:24 PM PDT 24
Finished Jun 13 01:49:25 PM PDT 24
Peak memory 206076 kb
Host smart-b4afe312-9be5-4529-b182-a98269d4cc64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381570120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3381570120
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.235278053
Short name T442
Test name
Test status
Simulation time 29159988 ps
CPU time 0.82 seconds
Started Jun 13 01:49:19 PM PDT 24
Finished Jun 13 01:49:22 PM PDT 24
Peak memory 215624 kb
Host smart-38ad34b8-e06d-4958-9222-39422f8330ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235278053 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.235278053
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.232901479
Short name T151
Test name
Test status
Simulation time 42186544 ps
CPU time 1.13 seconds
Started Jun 13 01:49:20 PM PDT 24
Finished Jun 13 01:49:22 PM PDT 24
Peak memory 216328 kb
Host smart-45de6cb7-bd28-4e26-94f3-4963396bf3b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232901479 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.232901479
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.262685178
Short name T177
Test name
Test status
Simulation time 31579419 ps
CPU time 0.87 seconds
Started Jun 13 01:49:20 PM PDT 24
Finished Jun 13 01:49:23 PM PDT 24
Peak memory 217572 kb
Host smart-7f737cdb-2507-483c-abb7-4b6107f5dbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262685178 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.262685178
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2049300229
Short name T729
Test name
Test status
Simulation time 103991408 ps
CPU time 1.24 seconds
Started Jun 13 01:49:22 PM PDT 24
Finished Jun 13 01:49:24 PM PDT 24
Peak memory 217992 kb
Host smart-17d1b664-748b-46bd-88e0-36e704134813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049300229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2049300229
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.393487634
Short name T578
Test name
Test status
Simulation time 31876844 ps
CPU time 0.96 seconds
Started Jun 13 01:49:19 PM PDT 24
Finished Jun 13 01:49:21 PM PDT 24
Peak memory 214988 kb
Host smart-8dfefb0d-2e3e-492b-9ec8-590d27d8993c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393487634 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.393487634
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.1900737492
Short name T882
Test name
Test status
Simulation time 25834926 ps
CPU time 0.94 seconds
Started Jun 13 01:49:20 PM PDT 24
Finished Jun 13 01:49:23 PM PDT 24
Peak memory 214604 kb
Host smart-b5714ec3-e7ac-4cb7-8015-2efe99257d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900737492 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1900737492
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3498825833
Short name T519
Test name
Test status
Simulation time 400577119 ps
CPU time 4.62 seconds
Started Jun 13 01:49:20 PM PDT 24
Finished Jun 13 01:49:26 PM PDT 24
Peak memory 216480 kb
Host smart-4e163489-eb44-48cb-a89f-546f70244fe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498825833 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3498825833
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3145137026
Short name T232
Test name
Test status
Simulation time 51053159738 ps
CPU time 570.14 seconds
Started Jun 13 01:49:22 PM PDT 24
Finished Jun 13 01:58:53 PM PDT 24
Peak memory 216488 kb
Host smart-95480c1b-2da5-4211-b8f3-fd9c9ba38b32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145137026 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3145137026
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.2912152500
Short name T276
Test name
Test status
Simulation time 58148544 ps
CPU time 1.27 seconds
Started Jun 13 01:51:28 PM PDT 24
Finished Jun 13 01:51:30 PM PDT 24
Peak memory 215028 kb
Host smart-78c8410b-7e01-480d-94eb-3d501682b883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912152500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.2912152500
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.3644456286
Short name T723
Test name
Test status
Simulation time 53574175 ps
CPU time 1.63 seconds
Started Jun 13 01:51:30 PM PDT 24
Finished Jun 13 01:51:33 PM PDT 24
Peak memory 217656 kb
Host smart-f82cec1d-3aec-4327-aede-abb5137a3afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644456286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3644456286
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.3994369517
Short name T146
Test name
Test status
Simulation time 210787886 ps
CPU time 1.08 seconds
Started Jun 13 01:51:34 PM PDT 24
Finished Jun 13 01:51:36 PM PDT 24
Peak memory 218164 kb
Host smart-2b7f7f05-8823-4663-9cec-f36e748a762f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994369517 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.3994369517
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.41410614
Short name T613
Test name
Test status
Simulation time 34929560 ps
CPU time 1.05 seconds
Started Jun 13 01:51:34 PM PDT 24
Finished Jun 13 01:51:36 PM PDT 24
Peak memory 217832 kb
Host smart-4d626b98-d291-49f6-9a2c-ad5e722263f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41410614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.41410614
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.841059802
Short name T496
Test name
Test status
Simulation time 41422932 ps
CPU time 1.21 seconds
Started Jun 13 01:51:31 PM PDT 24
Finished Jun 13 01:51:33 PM PDT 24
Peak memory 218664 kb
Host smart-70c454a6-d57c-4585-95b7-9ac90420a936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841059802 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.841059802
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.941443307
Short name T993
Test name
Test status
Simulation time 226210280 ps
CPU time 1.12 seconds
Started Jun 13 01:51:35 PM PDT 24
Finished Jun 13 01:51:37 PM PDT 24
Peak memory 216812 kb
Host smart-e1a430e0-6b70-4d8f-aa1f-79e7683be984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941443307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.941443307
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.248027717
Short name T954
Test name
Test status
Simulation time 78711828 ps
CPU time 1.18 seconds
Started Jun 13 01:51:33 PM PDT 24
Finished Jun 13 01:51:34 PM PDT 24
Peak memory 219040 kb
Host smart-1d1f10b2-3003-4c56-8080-6c2b3ba9c06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248027717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.248027717
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.243062510
Short name T805
Test name
Test status
Simulation time 56465083 ps
CPU time 1.92 seconds
Started Jun 13 01:51:30 PM PDT 24
Finished Jun 13 01:51:32 PM PDT 24
Peak memory 217864 kb
Host smart-d0362aa5-46d7-409a-9724-89332b548df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243062510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.243062510
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.2074976367
Short name T280
Test name
Test status
Simulation time 272979495 ps
CPU time 1.21 seconds
Started Jun 13 01:51:33 PM PDT 24
Finished Jun 13 01:51:34 PM PDT 24
Peak memory 215064 kb
Host smart-9001f50d-f373-47a4-a040-725a412afc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074976367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.2074976367
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.2742197
Short name T564
Test name
Test status
Simulation time 78955110 ps
CPU time 1.05 seconds
Started Jun 13 01:51:34 PM PDT 24
Finished Jun 13 01:51:36 PM PDT 24
Peak memory 216868 kb
Host smart-d2593626-c9af-4af5-9c73-34784f932410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2742197
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.3755817994
Short name T765
Test name
Test status
Simulation time 34150431 ps
CPU time 1.17 seconds
Started Jun 13 01:51:29 PM PDT 24
Finished Jun 13 01:51:31 PM PDT 24
Peak memory 218136 kb
Host smart-b3d947df-a2f8-4d41-9c78-c01bd2e79f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755817994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.3755817994
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.2840631306
Short name T514
Test name
Test status
Simulation time 47208853 ps
CPU time 1.31 seconds
Started Jun 13 01:51:29 PM PDT 24
Finished Jun 13 01:51:31 PM PDT 24
Peak memory 219168 kb
Host smart-70966dbe-b49c-490d-bd97-8d3a952b28b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840631306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2840631306
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.1532383176
Short name T173
Test name
Test status
Simulation time 27271653 ps
CPU time 1.24 seconds
Started Jun 13 01:51:29 PM PDT 24
Finished Jun 13 01:51:31 PM PDT 24
Peak memory 217800 kb
Host smart-1576d64e-70dd-401d-b2e7-b7427b15f226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532383176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.1532383176
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.1393306925
Short name T808
Test name
Test status
Simulation time 73897265 ps
CPU time 1.35 seconds
Started Jun 13 01:51:32 PM PDT 24
Finished Jun 13 01:51:34 PM PDT 24
Peak memory 218112 kb
Host smart-deb5f15d-080e-4cba-b7ad-194710d178a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393306925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1393306925
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.459913750
Short name T438
Test name
Test status
Simulation time 39014843 ps
CPU time 1.16 seconds
Started Jun 13 01:51:39 PM PDT 24
Finished Jun 13 01:51:42 PM PDT 24
Peak memory 218968 kb
Host smart-53490405-51ac-4d47-a6e7-eeff9b9da6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459913750 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.459913750
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.1765169871
Short name T350
Test name
Test status
Simulation time 45599287 ps
CPU time 1.53 seconds
Started Jun 13 01:51:35 PM PDT 24
Finished Jun 13 01:51:37 PM PDT 24
Peak memory 216748 kb
Host smart-f96545e0-d692-417f-b26e-ff0ae4ea8c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765169871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1765169871
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.894047204
Short name T528
Test name
Test status
Simulation time 28970876 ps
CPU time 1.24 seconds
Started Jun 13 01:51:37 PM PDT 24
Finished Jun 13 01:51:40 PM PDT 24
Peak memory 220104 kb
Host smart-355601d9-f28d-4d4b-b02c-c67a21c32734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894047204 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.894047204
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.3115189463
Short name T370
Test name
Test status
Simulation time 124231715 ps
CPU time 1.14 seconds
Started Jun 13 01:51:36 PM PDT 24
Finished Jun 13 01:51:39 PM PDT 24
Peak memory 216656 kb
Host smart-353d671f-e90a-4e93-8714-3d20e095ee5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115189463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3115189463
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.106656991
Short name T300
Test name
Test status
Simulation time 45519776 ps
CPU time 1.12 seconds
Started Jun 13 01:51:33 PM PDT 24
Finished Jun 13 01:51:35 PM PDT 24
Peak memory 219080 kb
Host smart-15988a61-7778-4171-9ae7-2467025a9140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106656991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.106656991
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.1857973518
Short name T985
Test name
Test status
Simulation time 41430787 ps
CPU time 1.12 seconds
Started Jun 13 01:51:35 PM PDT 24
Finished Jun 13 01:51:38 PM PDT 24
Peak memory 216696 kb
Host smart-1008797d-fea4-4c78-ba9f-8a7d6e23b223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857973518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1857973518
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1143374560
Short name T174
Test name
Test status
Simulation time 32161207 ps
CPU time 1.09 seconds
Started Jun 13 01:49:30 PM PDT 24
Finished Jun 13 01:49:32 PM PDT 24
Peak memory 219256 kb
Host smart-5e6b55d7-2b10-4432-a4af-3e1b6e789f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143374560 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1143374560
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1078293190
Short name T806
Test name
Test status
Simulation time 20539165 ps
CPU time 0.88 seconds
Started Jun 13 01:49:24 PM PDT 24
Finished Jun 13 01:49:26 PM PDT 24
Peak memory 206260 kb
Host smart-b3768643-0ca4-4c66-9cf5-ff57f1d006a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078293190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1078293190
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.254697208
Short name T89
Test name
Test status
Simulation time 13684520 ps
CPU time 0.91 seconds
Started Jun 13 01:49:23 PM PDT 24
Finished Jun 13 01:49:24 PM PDT 24
Peak memory 215464 kb
Host smart-a0838896-3f70-4fb2-8d7c-d2632a469cd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254697208 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.254697208
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.2474694302
Short name T165
Test name
Test status
Simulation time 73789322 ps
CPU time 1.12 seconds
Started Jun 13 01:49:31 PM PDT 24
Finished Jun 13 01:49:34 PM PDT 24
Peak memory 219024 kb
Host smart-bb793153-2d93-4158-99e1-3ab095a853ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474694302 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2474694302
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3790631534
Short name T706
Test name
Test status
Simulation time 61993222 ps
CPU time 1.39 seconds
Started Jun 13 01:49:27 PM PDT 24
Finished Jun 13 01:49:30 PM PDT 24
Peak memory 219352 kb
Host smart-0b2f5025-5f4b-4afd-a213-f1157d455f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790631534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3790631534
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.3115466311
Short name T433
Test name
Test status
Simulation time 39285749 ps
CPU time 0.94 seconds
Started Jun 13 01:49:26 PM PDT 24
Finished Jun 13 01:49:28 PM PDT 24
Peak memory 214780 kb
Host smart-7bebe684-96a7-4b06-bbc2-dadb45d9e2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115466311 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3115466311
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1406338227
Short name T65
Test name
Test status
Simulation time 17067899 ps
CPU time 0.98 seconds
Started Jun 13 01:49:27 PM PDT 24
Finished Jun 13 01:49:29 PM PDT 24
Peak memory 214600 kb
Host smart-ee3cf318-5e04-42d2-ab3b-3bcaf2f05afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406338227 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1406338227
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3900230707
Short name T664
Test name
Test status
Simulation time 258572791 ps
CPU time 4.12 seconds
Started Jun 13 01:49:31 PM PDT 24
Finished Jun 13 01:49:36 PM PDT 24
Peak memory 216440 kb
Host smart-9a077ea0-85a9-457e-99fa-7dd9bdb9a1f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900230707 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3900230707
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3377341493
Short name T407
Test name
Test status
Simulation time 280793125875 ps
CPU time 3236.79 seconds
Started Jun 13 01:49:24 PM PDT 24
Finished Jun 13 02:43:22 PM PDT 24
Peak memory 230524 kb
Host smart-bcdcb923-c366-42b6-9933-22a15fdd025a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377341493 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3377341493
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.706426501
Short name T185
Test name
Test status
Simulation time 78904403 ps
CPU time 1.25 seconds
Started Jun 13 01:51:38 PM PDT 24
Finished Jun 13 01:51:41 PM PDT 24
Peak memory 215068 kb
Host smart-3a08258c-a07a-4bee-8520-d8356dd9fac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706426501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.706426501
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.3929906191
Short name T718
Test name
Test status
Simulation time 71286707 ps
CPU time 0.98 seconds
Started Jun 13 01:51:36 PM PDT 24
Finished Jun 13 01:51:38 PM PDT 24
Peak memory 216600 kb
Host smart-f2f905a2-bcfb-43d0-a98f-dd363ae13af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929906191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3929906191
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.3477311968
Short name T606
Test name
Test status
Simulation time 32371046 ps
CPU time 1.35 seconds
Started Jun 13 01:51:35 PM PDT 24
Finished Jun 13 01:51:37 PM PDT 24
Peak memory 215056 kb
Host smart-64a5afe9-9c1d-4421-b5b8-b9037f6276aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477311968 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3477311968
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.4147782007
Short name T236
Test name
Test status
Simulation time 71032092 ps
CPU time 1.18 seconds
Started Jun 13 01:51:37 PM PDT 24
Finished Jun 13 01:51:40 PM PDT 24
Peak memory 218328 kb
Host smart-c203b6ba-79dd-440f-8d66-70b05bb7e07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147782007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.4147782007
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.648503263
Short name T650
Test name
Test status
Simulation time 40403851 ps
CPU time 1.63 seconds
Started Jun 13 01:51:38 PM PDT 24
Finished Jun 13 01:51:42 PM PDT 24
Peak memory 218032 kb
Host smart-46fafc59-03b2-43c5-b164-bcc0ab0e5d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648503263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.648503263
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.599546604
Short name T422
Test name
Test status
Simulation time 155697069 ps
CPU time 1.14 seconds
Started Jun 13 01:51:36 PM PDT 24
Finished Jun 13 01:51:39 PM PDT 24
Peak memory 218108 kb
Host smart-0f2ed9da-c23b-4801-95db-8f88583554a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599546604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.599546604
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1263955222
Short name T395
Test name
Test status
Simulation time 155567237 ps
CPU time 1.11 seconds
Started Jun 13 01:51:36 PM PDT 24
Finished Jun 13 01:51:39 PM PDT 24
Peak memory 216600 kb
Host smart-37779d71-80e1-4f1a-8fed-755b3560864e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263955222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1263955222
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.2801408282
Short name T379
Test name
Test status
Simulation time 47033435 ps
CPU time 1.21 seconds
Started Jun 13 01:51:36 PM PDT 24
Finished Jun 13 01:51:39 PM PDT 24
Peak memory 220176 kb
Host smart-df6b652c-e782-4cd9-b297-0df46e362e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801408282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.2801408282
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.2662274015
Short name T762
Test name
Test status
Simulation time 54595649 ps
CPU time 1.89 seconds
Started Jun 13 01:51:37 PM PDT 24
Finished Jun 13 01:51:41 PM PDT 24
Peak memory 217948 kb
Host smart-775d9b0e-7f64-4136-85ce-0d40157a54bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662274015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2662274015
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.3525261692
Short name T180
Test name
Test status
Simulation time 93939021 ps
CPU time 1.13 seconds
Started Jun 13 01:51:37 PM PDT 24
Finished Jun 13 01:51:41 PM PDT 24
Peak memory 218000 kb
Host smart-25ce1353-8ec5-42cb-b289-9d8e8859e973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525261692 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.3525261692
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.1795811232
Short name T658
Test name
Test status
Simulation time 74365664 ps
CPU time 1.52 seconds
Started Jun 13 01:51:34 PM PDT 24
Finished Jun 13 01:51:36 PM PDT 24
Peak memory 219520 kb
Host smart-2b84287a-eb6f-42d8-b482-1bf582373863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795811232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1795811232
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.1526679316
Short name T596
Test name
Test status
Simulation time 36776395 ps
CPU time 1.08 seconds
Started Jun 13 01:51:37 PM PDT 24
Finished Jun 13 01:51:40 PM PDT 24
Peak memory 219172 kb
Host smart-65e853af-9537-486a-bb18-6f4a2b3dcce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526679316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.1526679316
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.450532374
Short name T670
Test name
Test status
Simulation time 37336859 ps
CPU time 1.52 seconds
Started Jun 13 01:51:38 PM PDT 24
Finished Jun 13 01:51:42 PM PDT 24
Peak memory 217868 kb
Host smart-d725858c-8cf2-42bf-960d-9890187d80d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450532374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.450532374
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.2193394428
Short name T275
Test name
Test status
Simulation time 27945992 ps
CPU time 1.29 seconds
Started Jun 13 01:51:35 PM PDT 24
Finished Jun 13 01:51:38 PM PDT 24
Peak memory 218812 kb
Host smart-85de9d54-f3fa-41fe-b032-478ef9643b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193394428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.2193394428
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.833062722
Short name T580
Test name
Test status
Simulation time 52729421 ps
CPU time 1.32 seconds
Started Jun 13 01:51:36 PM PDT 24
Finished Jun 13 01:51:39 PM PDT 24
Peak memory 217724 kb
Host smart-5c9adb07-0009-491a-a0f5-6b3a63cff3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833062722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.833062722
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.2283614655
Short name T126
Test name
Test status
Simulation time 25614378 ps
CPU time 1.19 seconds
Started Jun 13 01:51:36 PM PDT 24
Finished Jun 13 01:51:39 PM PDT 24
Peak memory 220008 kb
Host smart-6faa4326-19e5-4736-975f-39d912613b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283614655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.2283614655
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.196605429
Short name T328
Test name
Test status
Simulation time 42996075 ps
CPU time 1.21 seconds
Started Jun 13 01:51:37 PM PDT 24
Finished Jun 13 01:51:40 PM PDT 24
Peak memory 219296 kb
Host smart-a74ae5d6-6ccf-4165-966b-87c94f2d2e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196605429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.196605429
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.26598967
Short name T846
Test name
Test status
Simulation time 45551809 ps
CPU time 1.22 seconds
Started Jun 13 01:49:24 PM PDT 24
Finished Jun 13 01:49:26 PM PDT 24
Peak memory 217900 kb
Host smart-138d9e0e-edeb-40cb-ada8-b0d9c51df199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26598967 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.26598967
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2164096026
Short name T766
Test name
Test status
Simulation time 88429255 ps
CPU time 0.76 seconds
Started Jun 13 01:49:26 PM PDT 24
Finished Jun 13 01:49:28 PM PDT 24
Peak memory 205768 kb
Host smart-c03f122b-73db-4dfe-a848-c164c0db5a7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164096026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2164096026
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1485425700
Short name T410
Test name
Test status
Simulation time 122367023 ps
CPU time 1.24 seconds
Started Jun 13 01:49:25 PM PDT 24
Finished Jun 13 01:49:27 PM PDT 24
Peak memory 218812 kb
Host smart-44f3ee5e-895e-4e74-b884-cb41f0440a47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485425700 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1485425700
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_genbits.1906397174
Short name T330
Test name
Test status
Simulation time 72285241 ps
CPU time 1.12 seconds
Started Jun 13 01:49:30 PM PDT 24
Finished Jun 13 01:49:32 PM PDT 24
Peak memory 218876 kb
Host smart-24fb5acc-18eb-4cb6-a49c-e83959b55eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906397174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1906397174
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.471207442
Short name T15
Test name
Test status
Simulation time 32519731 ps
CPU time 1.05 seconds
Started Jun 13 01:49:25 PM PDT 24
Finished Jun 13 01:49:27 PM PDT 24
Peak memory 223364 kb
Host smart-e636eaad-021f-4ba5-8b5d-d81cb049e005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471207442 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.471207442
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1803288440
Short name T308
Test name
Test status
Simulation time 65887100 ps
CPU time 0.94 seconds
Started Jun 13 01:49:25 PM PDT 24
Finished Jun 13 01:49:27 PM PDT 24
Peak memory 214648 kb
Host smart-3deb5e0f-a280-48fb-b55a-01b4c61e1b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803288440 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1803288440
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3657479697
Short name T463
Test name
Test status
Simulation time 144658543 ps
CPU time 1.48 seconds
Started Jun 13 01:49:30 PM PDT 24
Finished Jun 13 01:49:33 PM PDT 24
Peak memory 216484 kb
Host smart-2e0fc4f7-3232-4765-a267-e3cd595a4fd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657479697 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3657479697
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2073773582
Short name T542
Test name
Test status
Simulation time 66289841969 ps
CPU time 1481.02 seconds
Started Jun 13 01:49:26 PM PDT 24
Finished Jun 13 02:14:09 PM PDT 24
Peak memory 222656 kb
Host smart-8223c61e-9690-464c-9723-ffb0759746a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073773582 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2073773582
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.2908642155
Short name T883
Test name
Test status
Simulation time 25501065 ps
CPU time 1.21 seconds
Started Jun 13 01:51:35 PM PDT 24
Finished Jun 13 01:51:37 PM PDT 24
Peak memory 219208 kb
Host smart-768ed43b-739a-4c83-b146-a6a159948ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908642155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.2908642155
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.379941075
Short name T67
Test name
Test status
Simulation time 61999786 ps
CPU time 1.31 seconds
Started Jun 13 01:51:36 PM PDT 24
Finished Jun 13 01:51:39 PM PDT 24
Peak memory 219144 kb
Host smart-2d104932-f474-4fa7-b6eb-cb12a4edda5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379941075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.379941075
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.1263249274
Short name T583
Test name
Test status
Simulation time 38705077 ps
CPU time 1.07 seconds
Started Jun 13 01:51:43 PM PDT 24
Finished Jun 13 01:51:46 PM PDT 24
Peak memory 220368 kb
Host smart-b4e607c7-8db0-4888-bdaa-f0a1b0fa2f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263249274 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.1263249274
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.3581536703
Short name T859
Test name
Test status
Simulation time 94240210 ps
CPU time 1.33 seconds
Started Jun 13 01:51:39 PM PDT 24
Finished Jun 13 01:51:42 PM PDT 24
Peak memory 218244 kb
Host smart-5077b7cc-34c2-4864-942e-dd52eb467729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581536703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3581536703
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.727411304
Short name T84
Test name
Test status
Simulation time 24311198 ps
CPU time 1.15 seconds
Started Jun 13 01:51:37 PM PDT 24
Finished Jun 13 01:51:40 PM PDT 24
Peak memory 219308 kb
Host smart-1dbb8734-5282-42e7-bb45-536d8c461682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727411304 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.727411304
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.3727182666
Short name T85
Test name
Test status
Simulation time 30529205 ps
CPU time 1.39 seconds
Started Jun 13 01:51:38 PM PDT 24
Finished Jun 13 01:51:42 PM PDT 24
Peak memory 216764 kb
Host smart-d2e3bc82-e550-4d78-8d1b-136a54e127ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727182666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3727182666
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.4034412063
Short name T223
Test name
Test status
Simulation time 197662626 ps
CPU time 1.24 seconds
Started Jun 13 01:51:36 PM PDT 24
Finished Jun 13 01:51:39 PM PDT 24
Peak memory 218948 kb
Host smart-4583cc59-b099-4938-bbb8-e041efb18c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034412063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.4034412063
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.598838582
Short name T363
Test name
Test status
Simulation time 58318263 ps
CPU time 2.06 seconds
Started Jun 13 01:51:39 PM PDT 24
Finished Jun 13 01:51:43 PM PDT 24
Peak memory 219300 kb
Host smart-944445cd-c7b2-485f-ad7d-72779beca548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598838582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.598838582
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.228820292
Short name T746
Test name
Test status
Simulation time 63566695 ps
CPU time 1.07 seconds
Started Jun 13 01:51:38 PM PDT 24
Finished Jun 13 01:51:42 PM PDT 24
Peak memory 217800 kb
Host smart-7003cf15-30ea-4f42-a82b-965a17ca3ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228820292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.228820292
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.2618524722
Short name T360
Test name
Test status
Simulation time 38125829 ps
CPU time 1.53 seconds
Started Jun 13 01:51:39 PM PDT 24
Finished Jun 13 01:51:43 PM PDT 24
Peak memory 217640 kb
Host smart-0d8218db-0dff-4a8f-b5aa-e2e4dd6a8667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618524722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2618524722
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.758186062
Short name T892
Test name
Test status
Simulation time 104363544 ps
CPU time 1.28 seconds
Started Jun 13 01:51:37 PM PDT 24
Finished Jun 13 01:51:40 PM PDT 24
Peak memory 219260 kb
Host smart-9d27bfa4-4074-498b-9290-ecd6f6e67ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758186062 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.758186062
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.2548994594
Short name T512
Test name
Test status
Simulation time 41770345 ps
CPU time 1.31 seconds
Started Jun 13 01:51:36 PM PDT 24
Finished Jun 13 01:51:39 PM PDT 24
Peak memory 216632 kb
Host smart-f523f1ea-791c-4ccc-b60f-98b325aff43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548994594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2548994594
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.375808420
Short name T493
Test name
Test status
Simulation time 25624672 ps
CPU time 1.3 seconds
Started Jun 13 01:51:34 PM PDT 24
Finished Jun 13 01:51:36 PM PDT 24
Peak memory 218888 kb
Host smart-29b6bd04-f13d-4de9-b840-1dec7cb69816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375808420 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.375808420
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.3601214764
Short name T571
Test name
Test status
Simulation time 51036610 ps
CPU time 1.75 seconds
Started Jun 13 01:51:37 PM PDT 24
Finished Jun 13 01:51:41 PM PDT 24
Peak memory 218928 kb
Host smart-d7d6394a-7d3b-47cf-8e99-91c4e61084b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601214764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3601214764
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1081519263
Short name T428
Test name
Test status
Simulation time 49163781 ps
CPU time 1.12 seconds
Started Jun 13 01:51:36 PM PDT 24
Finished Jun 13 01:51:39 PM PDT 24
Peak memory 218036 kb
Host smart-2e6fb039-23cd-4a9b-ba73-6a630398d7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081519263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1081519263
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.2475039185
Short name T515
Test name
Test status
Simulation time 43734788 ps
CPU time 1.72 seconds
Started Jun 13 01:51:36 PM PDT 24
Finished Jun 13 01:51:39 PM PDT 24
Peak memory 219552 kb
Host smart-e6f71358-1e06-4942-9086-63267fc5a38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475039185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2475039185
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.1019994068
Short name T616
Test name
Test status
Simulation time 49521013 ps
CPU time 1.22 seconds
Started Jun 13 01:51:41 PM PDT 24
Finished Jun 13 01:51:44 PM PDT 24
Peak memory 217928 kb
Host smart-78910deb-b4d6-49a5-bcde-f7858e8cf9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019994068 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.1019994068
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.2023150817
Short name T810
Test name
Test status
Simulation time 154578831 ps
CPU time 1.16 seconds
Started Jun 13 01:51:38 PM PDT 24
Finished Jun 13 01:51:41 PM PDT 24
Peak memory 216704 kb
Host smart-d77ea8b1-0e22-4e70-9bf3-6e633a3e34ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023150817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2023150817
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.2310891804
Short name T194
Test name
Test status
Simulation time 26693440 ps
CPU time 1.22 seconds
Started Jun 13 01:51:36 PM PDT 24
Finished Jun 13 01:51:39 PM PDT 24
Peak memory 215072 kb
Host smart-8c0bf4c9-4f8c-42fe-b1ff-78d11dbe2873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310891804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2310891804
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.3664901436
Short name T862
Test name
Test status
Simulation time 42796467 ps
CPU time 1.16 seconds
Started Jun 13 01:51:37 PM PDT 24
Finished Jun 13 01:51:40 PM PDT 24
Peak memory 217996 kb
Host smart-0193e6db-235e-4cfa-b7f0-c4959227b960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664901436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3664901436
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1447869062
Short name T541
Test name
Test status
Simulation time 25742091 ps
CPU time 1.27 seconds
Started Jun 13 01:49:26 PM PDT 24
Finished Jun 13 01:49:29 PM PDT 24
Peak memory 218988 kb
Host smart-0723e31a-4cf2-4d63-a645-de244b7cf5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447869062 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1447869062
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3382776564
Short name T818
Test name
Test status
Simulation time 12351698 ps
CPU time 0.89 seconds
Started Jun 13 01:49:27 PM PDT 24
Finished Jun 13 01:49:29 PM PDT 24
Peak memory 206092 kb
Host smart-6db179ec-025b-4aa4-8caf-687a372cbc71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382776564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3382776564
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3108874435
Short name T423
Test name
Test status
Simulation time 21267912 ps
CPU time 0.81 seconds
Started Jun 13 01:49:24 PM PDT 24
Finished Jun 13 01:49:25 PM PDT 24
Peak memory 215636 kb
Host smart-6b909c8e-ae69-470a-a190-d9f4f0482d16
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108874435 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3108874435
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2085625325
Short name T906
Test name
Test status
Simulation time 35468845 ps
CPU time 0.99 seconds
Started Jun 13 01:49:30 PM PDT 24
Finished Jun 13 01:49:32 PM PDT 24
Peak memory 217800 kb
Host smart-aa003254-4989-478b-82ce-b9868d1688de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085625325 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2085625325
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.183110115
Short name T811
Test name
Test status
Simulation time 46895566 ps
CPU time 0.93 seconds
Started Jun 13 01:49:25 PM PDT 24
Finished Jun 13 01:49:27 PM PDT 24
Peak memory 217944 kb
Host smart-b9b6b0b2-d811-4b64-b9c6-59d0ac37208b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183110115 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.183110115
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3518627345
Short name T751
Test name
Test status
Simulation time 51982853 ps
CPU time 1.48 seconds
Started Jun 13 01:49:25 PM PDT 24
Finished Jun 13 01:49:27 PM PDT 24
Peak memory 218028 kb
Host smart-7b8b529f-281e-46bf-b142-59e21084fa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518627345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3518627345
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.4133413790
Short name T450
Test name
Test status
Simulation time 21834068 ps
CPU time 1.15 seconds
Started Jun 13 01:49:25 PM PDT 24
Finished Jun 13 01:49:27 PM PDT 24
Peak memory 214688 kb
Host smart-6e178b4e-151d-4721-8ddd-e6ae352f8c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133413790 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.4133413790
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3694940527
Short name T552
Test name
Test status
Simulation time 38166401 ps
CPU time 0.9 seconds
Started Jun 13 01:49:25 PM PDT 24
Finished Jun 13 01:49:27 PM PDT 24
Peak memory 214592 kb
Host smart-5fe996e5-6ddd-4b04-8567-d0716343c45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694940527 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3694940527
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1347303362
Short name T728
Test name
Test status
Simulation time 340317667 ps
CPU time 5.21 seconds
Started Jun 13 01:49:28 PM PDT 24
Finished Jun 13 01:49:34 PM PDT 24
Peak memory 217820 kb
Host smart-4903ef79-54f4-4aa8-b72f-82db6b2ceb14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347303362 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1347303362
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2414260662
Short name T903
Test name
Test status
Simulation time 61216283531 ps
CPU time 1362.65 seconds
Started Jun 13 01:49:27 PM PDT 24
Finished Jun 13 02:12:11 PM PDT 24
Peak memory 221592 kb
Host smart-7ac466de-496f-45c2-a63c-2b3132ba4ad6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414260662 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2414260662
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.973562196
Short name T292
Test name
Test status
Simulation time 160567056 ps
CPU time 1.36 seconds
Started Jun 13 01:51:40 PM PDT 24
Finished Jun 13 01:51:44 PM PDT 24
Peak memory 219764 kb
Host smart-6960666a-2b08-47e4-b84e-1419b849aac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973562196 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.973562196
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.3849994430
Short name T333
Test name
Test status
Simulation time 85568957 ps
CPU time 1.47 seconds
Started Jun 13 01:51:42 PM PDT 24
Finished Jun 13 01:51:46 PM PDT 24
Peak memory 218196 kb
Host smart-9cfecc3a-2ed2-4cba-b57e-0091499ef2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849994430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3849994430
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.2960806468
Short name T503
Test name
Test status
Simulation time 24610933 ps
CPU time 1.27 seconds
Started Jun 13 01:51:40 PM PDT 24
Finished Jun 13 01:51:44 PM PDT 24
Peak memory 218172 kb
Host smart-7374bdba-fc06-46b6-a4e5-fdee11807ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960806468 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.2960806468
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.3921799451
Short name T856
Test name
Test status
Simulation time 122589472 ps
CPU time 1.35 seconds
Started Jun 13 01:51:42 PM PDT 24
Finished Jun 13 01:51:45 PM PDT 24
Peak memory 216712 kb
Host smart-a7e4d34d-41d8-43af-a181-635fd42913d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921799451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3921799451
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.548198021
Short name T329
Test name
Test status
Simulation time 66330807 ps
CPU time 2.38 seconds
Started Jun 13 01:51:46 PM PDT 24
Finished Jun 13 01:51:51 PM PDT 24
Peak memory 214524 kb
Host smart-46c1c712-698e-4162-b493-d30c5f31cdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548198021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.548198021
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.958574423
Short name T982
Test name
Test status
Simulation time 53007848 ps
CPU time 1.24 seconds
Started Jun 13 01:51:43 PM PDT 24
Finished Jun 13 01:51:46 PM PDT 24
Peak memory 218932 kb
Host smart-98aa2e12-0bed-4218-bc16-16b527e11db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958574423 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.958574423
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/174.edn_alert.3177655816
Short name T289
Test name
Test status
Simulation time 345862086 ps
CPU time 1.76 seconds
Started Jun 13 01:51:41 PM PDT 24
Finished Jun 13 01:51:45 PM PDT 24
Peak memory 219120 kb
Host smart-ff5d6696-5289-4c64-ae31-2832681a975a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177655816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.3177655816
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.3537451499
Short name T499
Test name
Test status
Simulation time 202889898 ps
CPU time 3.11 seconds
Started Jun 13 01:51:40 PM PDT 24
Finished Jun 13 01:51:45 PM PDT 24
Peak memory 219636 kb
Host smart-54a86c13-995c-4f36-a6d2-69d21518d87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537451499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3537451499
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3984808143
Short name T137
Test name
Test status
Simulation time 48240875 ps
CPU time 1.15 seconds
Started Jun 13 01:51:44 PM PDT 24
Finished Jun 13 01:51:48 PM PDT 24
Peak memory 220024 kb
Host smart-b448bdf5-a2cf-4f8a-b3ca-24d2089ade77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984808143 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3984808143
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/176.edn_alert.2256975746
Short name T694
Test name
Test status
Simulation time 32408528 ps
CPU time 1.17 seconds
Started Jun 13 01:51:48 PM PDT 24
Finished Jun 13 01:51:52 PM PDT 24
Peak memory 219148 kb
Host smart-d65dc07e-c01a-4746-8630-531c81b470f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256975746 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2256975746
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.4022547408
Short name T839
Test name
Test status
Simulation time 55076302 ps
CPU time 1.35 seconds
Started Jun 13 01:51:42 PM PDT 24
Finished Jun 13 01:51:46 PM PDT 24
Peak memory 217632 kb
Host smart-ab53610b-b069-404e-88e6-9a20d3f54379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022547408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.4022547408
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.403517009
Short name T768
Test name
Test status
Simulation time 73263627 ps
CPU time 1.22 seconds
Started Jun 13 01:51:43 PM PDT 24
Finished Jun 13 01:51:47 PM PDT 24
Peak memory 219240 kb
Host smart-90f9a9d6-171f-4209-b741-3aeef1124b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403517009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.403517009
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.77913278
Short name T896
Test name
Test status
Simulation time 33084460 ps
CPU time 1.32 seconds
Started Jun 13 01:51:45 PM PDT 24
Finished Jun 13 01:51:49 PM PDT 24
Peak memory 219256 kb
Host smart-27f21a80-b715-4257-ac2b-9294627e8634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77913278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.77913278
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.1994486506
Short name T272
Test name
Test status
Simulation time 50331310 ps
CPU time 1.3 seconds
Started Jun 13 01:51:43 PM PDT 24
Finished Jun 13 01:51:47 PM PDT 24
Peak memory 219248 kb
Host smart-82ec30ef-d7e5-4d2b-9afd-c92ecd579644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994486506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.1994486506
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3693533304
Short name T509
Test name
Test status
Simulation time 85844695 ps
CPU time 1.77 seconds
Started Jun 13 01:51:52 PM PDT 24
Finished Jun 13 01:51:55 PM PDT 24
Peak memory 217812 kb
Host smart-98a33aa8-fab3-4017-932f-18e36b2041b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693533304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3693533304
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.1498986656
Short name T803
Test name
Test status
Simulation time 60130056 ps
CPU time 1.33 seconds
Started Jun 13 01:51:42 PM PDT 24
Finished Jun 13 01:51:46 PM PDT 24
Peak memory 219388 kb
Host smart-8327ab72-274c-494b-a5ac-5bc45f3500ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498986656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.1498986656
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.4255239304
Short name T529
Test name
Test status
Simulation time 44818653 ps
CPU time 1.49 seconds
Started Jun 13 01:51:44 PM PDT 24
Finished Jun 13 01:51:48 PM PDT 24
Peak memory 217632 kb
Host smart-91ff2093-8c5a-4b27-9a33-487abb1e7dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255239304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.4255239304
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.958973413
Short name T657
Test name
Test status
Simulation time 57693299 ps
CPU time 1.22 seconds
Started Jun 13 01:49:26 PM PDT 24
Finished Jun 13 01:49:28 PM PDT 24
Peak memory 218032 kb
Host smart-114ddf32-cdbc-4b59-94ff-d01776fe7696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958973413 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.958973413
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2203723132
Short name T910
Test name
Test status
Simulation time 148582371 ps
CPU time 1 seconds
Started Jun 13 01:49:28 PM PDT 24
Finished Jun 13 01:49:30 PM PDT 24
Peak memory 206128 kb
Host smart-7d958386-0318-422a-8b14-8b7911f0ddc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203723132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2203723132
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2475894480
Short name T166
Test name
Test status
Simulation time 18104102 ps
CPU time 0.95 seconds
Started Jun 13 01:49:30 PM PDT 24
Finished Jun 13 01:49:32 PM PDT 24
Peak memory 215820 kb
Host smart-8b98b28e-334e-41ab-9cc6-cdaffa9efef0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475894480 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2475894480
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1552868084
Short name T131
Test name
Test status
Simulation time 31046814 ps
CPU time 1.13 seconds
Started Jun 13 01:49:26 PM PDT 24
Finished Jun 13 01:49:28 PM PDT 24
Peak memory 217832 kb
Host smart-f7fe748e-5e57-4f6f-9c75-e81867b5e810
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552868084 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1552868084
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1257345115
Short name T175
Test name
Test status
Simulation time 18399176 ps
CPU time 1.05 seconds
Started Jun 13 01:49:27 PM PDT 24
Finished Jun 13 01:49:29 PM PDT 24
Peak memory 217864 kb
Host smart-c8e4fe37-4107-429a-8990-67fd93e228be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257345115 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1257345115
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1920239574
Short name T590
Test name
Test status
Simulation time 57183182 ps
CPU time 1.59 seconds
Started Jun 13 01:49:26 PM PDT 24
Finished Jun 13 01:49:28 PM PDT 24
Peak memory 216832 kb
Host smart-1f2622ad-c9bd-41e2-b2d2-2388e75f33e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920239574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1920239574
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1704683880
Short name T943
Test name
Test status
Simulation time 25968829 ps
CPU time 1.29 seconds
Started Jun 13 01:49:27 PM PDT 24
Finished Jun 13 01:49:29 PM PDT 24
Peak memory 224276 kb
Host smart-a4046b71-7944-4916-b1d6-481c3d95ff52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704683880 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1704683880
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1375748899
Short name T557
Test name
Test status
Simulation time 30709321 ps
CPU time 0.99 seconds
Started Jun 13 01:49:29 PM PDT 24
Finished Jun 13 01:49:30 PM PDT 24
Peak memory 214632 kb
Host smart-1ce31d42-ff0e-4e7a-9edc-33602ae9dcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375748899 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1375748899
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3231401902
Short name T944
Test name
Test status
Simulation time 418737830 ps
CPU time 3.53 seconds
Started Jun 13 01:49:30 PM PDT 24
Finished Jun 13 01:49:35 PM PDT 24
Peak memory 216524 kb
Host smart-0cf34bd4-8a2d-474b-a108-753910935472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231401902 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3231401902
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2870444372
Short name T697
Test name
Test status
Simulation time 65225660328 ps
CPU time 726.84 seconds
Started Jun 13 01:49:25 PM PDT 24
Finished Jun 13 02:01:33 PM PDT 24
Peak memory 222880 kb
Host smart-5eb6ce8d-33c9-4626-9fee-1a7b1f95297a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870444372 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2870444372
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.2566289100
Short name T654
Test name
Test status
Simulation time 104537083 ps
CPU time 1.28 seconds
Started Jun 13 01:51:46 PM PDT 24
Finished Jun 13 01:51:50 PM PDT 24
Peak memory 215008 kb
Host smart-279b214e-c39d-45ef-92ca-25009bd6435b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566289100 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.2566289100
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.1283188434
Short name T975
Test name
Test status
Simulation time 187596428 ps
CPU time 1.34 seconds
Started Jun 13 01:51:41 PM PDT 24
Finished Jun 13 01:51:45 PM PDT 24
Peak memory 216516 kb
Host smart-a4771cb0-cc81-4611-92a6-7b1431e9324b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283188434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1283188434
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.1120177964
Short name T615
Test name
Test status
Simulation time 24868994 ps
CPU time 1.22 seconds
Started Jun 13 01:51:42 PM PDT 24
Finished Jun 13 01:51:45 PM PDT 24
Peak memory 219128 kb
Host smart-e1b990fe-e591-4912-ab4e-d69b2212b7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120177964 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.1120177964
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.1369833755
Short name T83
Test name
Test status
Simulation time 90727432 ps
CPU time 1.2 seconds
Started Jun 13 01:51:43 PM PDT 24
Finished Jun 13 01:51:46 PM PDT 24
Peak memory 216776 kb
Host smart-251ced9d-4ffa-4a8a-8e42-ec5a9663600f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369833755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1369833755
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.2986105026
Short name T116
Test name
Test status
Simulation time 24464185 ps
CPU time 1.24 seconds
Started Jun 13 01:51:41 PM PDT 24
Finished Jun 13 01:51:45 PM PDT 24
Peak memory 217908 kb
Host smart-9d0628ba-c2a9-417b-8e9f-93618e638968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986105026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2986105026
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/183.edn_alert.1003426630
Short name T371
Test name
Test status
Simulation time 39654231 ps
CPU time 1.11 seconds
Started Jun 13 01:51:48 PM PDT 24
Finished Jun 13 01:51:52 PM PDT 24
Peak memory 219296 kb
Host smart-fbc6c656-bfa9-436b-94e0-0ca790c61ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003426630 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1003426630
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.2170781528
Short name T454
Test name
Test status
Simulation time 33948196 ps
CPU time 1.41 seconds
Started Jun 13 01:51:42 PM PDT 24
Finished Jun 13 01:51:46 PM PDT 24
Peak memory 216608 kb
Host smart-234943b0-48a4-4f87-a39b-6ea206856840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170781528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2170781528
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.4242039269
Short name T494
Test name
Test status
Simulation time 68354117 ps
CPU time 1.32 seconds
Started Jun 13 01:51:40 PM PDT 24
Finished Jun 13 01:51:43 PM PDT 24
Peak memory 218204 kb
Host smart-9da5aac4-07dd-4dd3-af8b-ea3dfaec491d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242039269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.4242039269
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.1464038310
Short name T123
Test name
Test status
Simulation time 80197409 ps
CPU time 1.23 seconds
Started Jun 13 01:51:44 PM PDT 24
Finished Jun 13 01:51:48 PM PDT 24
Peak memory 217948 kb
Host smart-ae1484d2-b34c-45e9-bdf1-2d8ede0a2fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464038310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.1464038310
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.1427938230
Short name T983
Test name
Test status
Simulation time 38208404 ps
CPU time 1.52 seconds
Started Jun 13 01:51:51 PM PDT 24
Finished Jun 13 01:51:54 PM PDT 24
Peak memory 216816 kb
Host smart-31016482-1873-48f9-bb79-5544f5b8f619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427938230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1427938230
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.2638831501
Short name T87
Test name
Test status
Simulation time 55383198 ps
CPU time 1.34 seconds
Started Jun 13 01:51:44 PM PDT 24
Finished Jun 13 01:51:48 PM PDT 24
Peak memory 215056 kb
Host smart-cd4461ae-7849-49ed-baec-e07017d06440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638831501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2638831501
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/187.edn_alert.1738975473
Short name T42
Test name
Test status
Simulation time 69633238 ps
CPU time 1.16 seconds
Started Jun 13 01:51:40 PM PDT 24
Finished Jun 13 01:51:44 PM PDT 24
Peak memory 219228 kb
Host smart-651850f4-351c-45fe-9641-ca0804763978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738975473 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1738975473
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.2088793902
Short name T620
Test name
Test status
Simulation time 37351045 ps
CPU time 1.51 seconds
Started Jun 13 01:51:45 PM PDT 24
Finished Jun 13 01:51:49 PM PDT 24
Peak memory 217692 kb
Host smart-91366970-0c56-45dd-bb8e-e427298a9bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088793902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2088793902
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.3194867627
Short name T271
Test name
Test status
Simulation time 47065957 ps
CPU time 1.27 seconds
Started Jun 13 01:51:45 PM PDT 24
Finished Jun 13 01:51:49 PM PDT 24
Peak memory 219572 kb
Host smart-3d9f9259-11e0-4303-8ad2-d45fcad6501a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194867627 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.3194867627
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.1969639954
Short name T524
Test name
Test status
Simulation time 52612918 ps
CPU time 2.03 seconds
Started Jun 13 01:51:43 PM PDT 24
Finished Jun 13 01:51:47 PM PDT 24
Peak memory 217972 kb
Host smart-90ccaeec-6d8d-4771-8fd8-46682f30682c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969639954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1969639954
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.930632143
Short name T517
Test name
Test status
Simulation time 24507985 ps
CPU time 1.22 seconds
Started Jun 13 01:51:41 PM PDT 24
Finished Jun 13 01:51:45 PM PDT 24
Peak memory 219748 kb
Host smart-cc85e684-6e37-4c15-aa9d-1bd9b6fd518d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930632143 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.930632143
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.989601361
Short name T540
Test name
Test status
Simulation time 19732736 ps
CPU time 1.09 seconds
Started Jun 13 01:51:43 PM PDT 24
Finished Jun 13 01:51:46 PM PDT 24
Peak memory 216704 kb
Host smart-0c571ae1-e9d5-4e0b-9bd3-adcc1fd5ffec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989601361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.989601361
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2657328585
Short name T809
Test name
Test status
Simulation time 73111022 ps
CPU time 1.12 seconds
Started Jun 13 01:49:31 PM PDT 24
Finished Jun 13 01:49:33 PM PDT 24
Peak memory 219552 kb
Host smart-61fddd8f-86c7-40c4-b75e-9d3d03a386f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657328585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2657328585
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3335643566
Short name T501
Test name
Test status
Simulation time 23380396 ps
CPU time 1.09 seconds
Started Jun 13 01:49:34 PM PDT 24
Finished Jun 13 01:49:36 PM PDT 24
Peak memory 214600 kb
Host smart-211049fd-eed6-4626-b944-b657968a0c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335643566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3335643566
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.3205719549
Short name T935
Test name
Test status
Simulation time 13898352 ps
CPU time 0.98 seconds
Started Jun 13 01:49:34 PM PDT 24
Finished Jun 13 01:49:36 PM PDT 24
Peak memory 215432 kb
Host smart-35587eec-44ba-4b29-a349-e49965b515e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205719549 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3205719549
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.960977832
Short name T785
Test name
Test status
Simulation time 134512282 ps
CPU time 1.2 seconds
Started Jun 13 01:49:34 PM PDT 24
Finished Jun 13 01:49:36 PM PDT 24
Peak memory 216176 kb
Host smart-f761f628-24d6-4966-b78a-a30549742e9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960977832 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.960977832
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3984985802
Short name T9
Test name
Test status
Simulation time 35356609 ps
CPU time 1.03 seconds
Started Jun 13 01:49:32 PM PDT 24
Finished Jun 13 01:49:34 PM PDT 24
Peak memory 229020 kb
Host smart-037efa6f-a51b-4b38-a087-c18ef5ba2273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984985802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3984985802
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.4189797740
Short name T443
Test name
Test status
Simulation time 66440859 ps
CPU time 1.3 seconds
Started Jun 13 01:49:30 PM PDT 24
Finished Jun 13 01:49:32 PM PDT 24
Peak memory 216608 kb
Host smart-edf86564-35e7-4422-b762-3abd68511c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189797740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.4189797740
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1791014401
Short name T390
Test name
Test status
Simulation time 38409835 ps
CPU time 1.08 seconds
Started Jun 13 01:49:30 PM PDT 24
Finished Jun 13 01:49:32 PM PDT 24
Peak memory 223352 kb
Host smart-87df94ca-bba3-4648-80a0-c967c90d1340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791014401 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1791014401
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.443401916
Short name T343
Test name
Test status
Simulation time 27085512 ps
CPU time 0.94 seconds
Started Jun 13 01:49:28 PM PDT 24
Finished Jun 13 01:49:30 PM PDT 24
Peak memory 214628 kb
Host smart-fcd7fafd-b800-49b1-89eb-a296541dc98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443401916 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.443401916
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2232540105
Short name T783
Test name
Test status
Simulation time 90700862 ps
CPU time 2.25 seconds
Started Jun 13 01:49:31 PM PDT 24
Finished Jun 13 01:49:34 PM PDT 24
Peak memory 216608 kb
Host smart-3c58ebff-c636-40c3-acb3-36c3aa888a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232540105 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2232540105
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3366899801
Short name T61
Test name
Test status
Simulation time 36534120424 ps
CPU time 793.42 seconds
Started Jun 13 01:49:32 PM PDT 24
Finished Jun 13 02:02:47 PM PDT 24
Peak memory 217476 kb
Host smart-512e70a4-db7b-4d41-9b93-017bad3aafe3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366899801 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3366899801
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.2526868583
Short name T239
Test name
Test status
Simulation time 30263785 ps
CPU time 1.39 seconds
Started Jun 13 01:51:44 PM PDT 24
Finished Jun 13 01:51:49 PM PDT 24
Peak memory 219928 kb
Host smart-c9b88085-949b-40e7-b9bc-8f6aadb84344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526868583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.2526868583
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.1995580826
Short name T307
Test name
Test status
Simulation time 59301573 ps
CPU time 1.71 seconds
Started Jun 13 01:51:52 PM PDT 24
Finished Jun 13 01:51:55 PM PDT 24
Peak memory 217788 kb
Host smart-70793b73-143e-4ffd-a8dd-ed76c07e1526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995580826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1995580826
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.590949227
Short name T973
Test name
Test status
Simulation time 120568954 ps
CPU time 1.36 seconds
Started Jun 13 01:51:46 PM PDT 24
Finished Jun 13 01:51:50 PM PDT 24
Peak memory 217712 kb
Host smart-7c58d357-30aa-4b20-84cd-a2d637d12cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590949227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.590949227
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.4127862766
Short name T781
Test name
Test status
Simulation time 79183003 ps
CPU time 1.23 seconds
Started Jun 13 01:51:42 PM PDT 24
Finished Jun 13 01:51:46 PM PDT 24
Peak memory 216736 kb
Host smart-b693caa5-33dd-4181-8723-7cba68932b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127862766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.4127862766
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.4099733140
Short name T938
Test name
Test status
Simulation time 58257736 ps
CPU time 1.16 seconds
Started Jun 13 01:51:43 PM PDT 24
Finished Jun 13 01:51:47 PM PDT 24
Peak memory 218400 kb
Host smart-1adf8212-d991-45a6-ae14-82b5a21df34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099733140 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.4099733140
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.226317262
Short name T897
Test name
Test status
Simulation time 134101010 ps
CPU time 3.25 seconds
Started Jun 13 01:51:42 PM PDT 24
Finished Jun 13 01:51:47 PM PDT 24
Peak memory 218532 kb
Host smart-694386fc-0417-4dd7-a941-aa800bb73bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226317262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.226317262
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.658128758
Short name T848
Test name
Test status
Simulation time 48116415 ps
CPU time 1.21 seconds
Started Jun 13 01:51:48 PM PDT 24
Finished Jun 13 01:51:52 PM PDT 24
Peak memory 215068 kb
Host smart-5d228716-6ebe-4fe5-9008-86824d8c2fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658128758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.658128758
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.979966438
Short name T796
Test name
Test status
Simulation time 84500006 ps
CPU time 1.66 seconds
Started Jun 13 01:51:42 PM PDT 24
Finished Jun 13 01:51:47 PM PDT 24
Peak memory 217884 kb
Host smart-477eccba-6883-4792-8693-779e3d28fbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979966438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.979966438
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.1492405615
Short name T608
Test name
Test status
Simulation time 161544853 ps
CPU time 1.11 seconds
Started Jun 13 01:51:52 PM PDT 24
Finished Jun 13 01:51:54 PM PDT 24
Peak memory 219168 kb
Host smart-dd7ed74d-3a93-429a-96de-4c1a6a8aade6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492405615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.1492405615
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/195.edn_alert.2431957626
Short name T916
Test name
Test status
Simulation time 63173202 ps
CPU time 1.14 seconds
Started Jun 13 01:51:48 PM PDT 24
Finished Jun 13 01:51:52 PM PDT 24
Peak memory 220288 kb
Host smart-1cd1c7d6-01f8-4bb3-aaed-ec0e439eec5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431957626 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2431957626
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.2639966398
Short name T547
Test name
Test status
Simulation time 203377665 ps
CPU time 1.56 seconds
Started Jun 13 01:51:47 PM PDT 24
Finished Jun 13 01:51:51 PM PDT 24
Peak memory 218288 kb
Host smart-f2547dad-f4cb-4ea3-8ca0-7bd9ed85c5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639966398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2639966398
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.88123601
Short name T804
Test name
Test status
Simulation time 205475060 ps
CPU time 2.82 seconds
Started Jun 13 01:51:56 PM PDT 24
Finished Jun 13 01:52:00 PM PDT 24
Peak memory 218692 kb
Host smart-667b3e88-428a-4425-80bd-8e83ddd3556e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88123601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.88123601
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.3134786126
Short name T942
Test name
Test status
Simulation time 37472353 ps
CPU time 1.25 seconds
Started Jun 13 01:51:49 PM PDT 24
Finished Jun 13 01:51:52 PM PDT 24
Peak memory 219216 kb
Host smart-fb51b2b3-b782-466b-bea2-16169c63d0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134786126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3134786126
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.3807636880
Short name T304
Test name
Test status
Simulation time 46771219 ps
CPU time 1.69 seconds
Started Jun 13 01:51:47 PM PDT 24
Finished Jun 13 01:51:51 PM PDT 24
Peak memory 217976 kb
Host smart-fd454e5c-d035-401b-8215-8301f9abc165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807636880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3807636880
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.2011895042
Short name T618
Test name
Test status
Simulation time 26129191 ps
CPU time 1.26 seconds
Started Jun 13 01:51:47 PM PDT 24
Finished Jun 13 01:51:51 PM PDT 24
Peak memory 219788 kb
Host smart-c184290d-3009-48be-99af-5ce1ef949825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011895042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.2011895042
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3759968852
Short name T974
Test name
Test status
Simulation time 51731645 ps
CPU time 1.27 seconds
Started Jun 13 01:51:51 PM PDT 24
Finished Jun 13 01:51:54 PM PDT 24
Peak memory 216652 kb
Host smart-534bb5af-80a3-49ec-9129-23a8ed48dd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759968852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3759968852
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.739133827
Short name T986
Test name
Test status
Simulation time 36079711 ps
CPU time 1.12 seconds
Started Jun 13 01:51:48 PM PDT 24
Finished Jun 13 01:51:52 PM PDT 24
Peak memory 218200 kb
Host smart-c26e9a08-53fd-4c0d-bfeb-4074e89b550f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739133827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.739133827
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.3874978447
Short name T324
Test name
Test status
Simulation time 53843991 ps
CPU time 1.35 seconds
Started Jun 13 01:51:48 PM PDT 24
Finished Jun 13 01:51:52 PM PDT 24
Peak memory 219092 kb
Host smart-62d2d423-fff3-467b-93f9-c4b5e177df63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874978447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3874978447
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1916539566
Short name T124
Test name
Test status
Simulation time 28226471 ps
CPU time 1.27 seconds
Started Jun 13 01:48:56 PM PDT 24
Finished Jun 13 01:48:59 PM PDT 24
Peak memory 217956 kb
Host smart-c3bffc12-d966-4431-93be-3512a2e22aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916539566 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1916539566
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.533730775
Short name T936
Test name
Test status
Simulation time 22090621 ps
CPU time 0.92 seconds
Started Jun 13 01:48:54 PM PDT 24
Finished Jun 13 01:48:57 PM PDT 24
Peak memory 206132 kb
Host smart-a838980e-6ab9-42e3-8880-2bf53c0e1450
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533730775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.533730775
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3460541186
Short name T189
Test name
Test status
Simulation time 12136592 ps
CPU time 0.96 seconds
Started Jun 13 01:48:56 PM PDT 24
Finished Jun 13 01:49:00 PM PDT 24
Peak memory 215772 kb
Host smart-066dfd6d-e97c-46ef-8612-84c524902801
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460541186 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3460541186
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.3047576766
Short name T817
Test name
Test status
Simulation time 25378741 ps
CPU time 0.97 seconds
Started Jun 13 01:48:55 PM PDT 24
Finished Jun 13 01:48:58 PM PDT 24
Peak memory 217992 kb
Host smart-d8b5dfaa-8fcc-4686-a85d-f25ffd2a5fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047576766 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3047576766
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3189409833
Short name T940
Test name
Test status
Simulation time 49441704 ps
CPU time 1.59 seconds
Started Jun 13 01:48:48 PM PDT 24
Finished Jun 13 01:48:50 PM PDT 24
Peak memory 216772 kb
Host smart-29200ec6-9327-4de2-af21-42185d220ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189409833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3189409833
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.345250405
Short name T699
Test name
Test status
Simulation time 39614996 ps
CPU time 1.02 seconds
Started Jun 13 01:48:54 PM PDT 24
Finished Jun 13 01:48:57 PM PDT 24
Peak memory 223336 kb
Host smart-96dc3ad7-6774-4793-ab6a-33a5d3bd4bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345250405 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.345250405
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3528726917
Short name T611
Test name
Test status
Simulation time 15142670 ps
CPU time 1 seconds
Started Jun 13 01:48:48 PM PDT 24
Finished Jun 13 01:48:50 PM PDT 24
Peak memory 206404 kb
Host smart-7cc26570-535b-492e-88c4-78d73dcb092d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528726917 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3528726917
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3657448302
Short name T17
Test name
Test status
Simulation time 2378736929 ps
CPU time 4.99 seconds
Started Jun 13 01:48:54 PM PDT 24
Finished Jun 13 01:49:01 PM PDT 24
Peak memory 241692 kb
Host smart-28d7d342-2775-45a7-8227-309834259ba7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657448302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3657448302
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.4271919833
Short name T383
Test name
Test status
Simulation time 131061328 ps
CPU time 1.02 seconds
Started Jun 13 01:48:49 PM PDT 24
Finished Jun 13 01:48:51 PM PDT 24
Peak memory 214616 kb
Host smart-7cd54dcc-970a-423e-ad6e-dd1e576136d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271919833 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.4271919833
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.677322184
Short name T545
Test name
Test status
Simulation time 39726640 ps
CPU time 1.44 seconds
Started Jun 13 01:48:54 PM PDT 24
Finished Jun 13 01:48:58 PM PDT 24
Peak memory 216588 kb
Host smart-80149a66-20b6-461b-a4ca-e1573ccd8a2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677322184 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.677322184
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.455127020
Short name T787
Test name
Test status
Simulation time 144196386359 ps
CPU time 1879.63 seconds
Started Jun 13 01:48:54 PM PDT 24
Finished Jun 13 02:20:15 PM PDT 24
Peak memory 236268 kb
Host smart-8a402721-40d1-47a3-9865-080179d73945
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455127020 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.455127020
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2363162866
Short name T631
Test name
Test status
Simulation time 28788459 ps
CPU time 1.25 seconds
Started Jun 13 01:49:32 PM PDT 24
Finished Jun 13 01:49:34 PM PDT 24
Peak memory 217760 kb
Host smart-43579894-a84d-434a-930e-e2d801eddd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363162866 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2363162866
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.417256894
Short name T444
Test name
Test status
Simulation time 15890037 ps
CPU time 0.94 seconds
Started Jun 13 01:49:32 PM PDT 24
Finished Jun 13 01:49:34 PM PDT 24
Peak memory 206096 kb
Host smart-4e50dea8-8e34-4685-bccb-eabc31020dfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417256894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.417256894
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3865642897
Short name T898
Test name
Test status
Simulation time 100355066 ps
CPU time 0.83 seconds
Started Jun 13 01:49:30 PM PDT 24
Finished Jun 13 01:49:32 PM PDT 24
Peak memory 215620 kb
Host smart-52aac844-ca24-4988-8cc1-387d46bea170
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865642897 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3865642897
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2549123800
Short name T133
Test name
Test status
Simulation time 33923272 ps
CPU time 1.18 seconds
Started Jun 13 01:49:31 PM PDT 24
Finished Jun 13 01:49:33 PM PDT 24
Peak memory 218576 kb
Host smart-223a1782-bbb5-4892-9428-f159d14e8657
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549123800 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2549123800
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.381042821
Short name T118
Test name
Test status
Simulation time 20691888 ps
CPU time 1.08 seconds
Started Jun 13 01:49:32 PM PDT 24
Finished Jun 13 01:49:35 PM PDT 24
Peak memory 219068 kb
Host smart-b08eb9d9-8645-47c4-a300-6fab77e35eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381042821 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.381042821
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.4220923498
Short name T560
Test name
Test status
Simulation time 41116706 ps
CPU time 1.34 seconds
Started Jun 13 01:49:32 PM PDT 24
Finished Jun 13 01:49:34 PM PDT 24
Peak memory 217788 kb
Host smart-973dbdf2-bb4b-416f-ad98-6bdae29952c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220923498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.4220923498
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1793225306
Short name T774
Test name
Test status
Simulation time 47696992 ps
CPU time 0.96 seconds
Started Jun 13 01:49:29 PM PDT 24
Finished Jun 13 01:49:31 PM PDT 24
Peak memory 214812 kb
Host smart-2e8b4448-9e73-411b-88c4-f011c27e9c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793225306 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1793225306
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3768633759
Short name T342
Test name
Test status
Simulation time 22919040 ps
CPU time 0.98 seconds
Started Jun 13 01:49:35 PM PDT 24
Finished Jun 13 01:49:37 PM PDT 24
Peak memory 214612 kb
Host smart-d018f919-6edf-48d7-8c71-fdde67105821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768633759 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3768633759
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1743381438
Short name T563
Test name
Test status
Simulation time 152832837 ps
CPU time 1.39 seconds
Started Jun 13 01:49:29 PM PDT 24
Finished Jun 13 01:49:32 PM PDT 24
Peak memory 206208 kb
Host smart-79e26989-9cc1-4abf-81d8-1d6b060efaa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743381438 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1743381438
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2747530711
Short name T543
Test name
Test status
Simulation time 70331208940 ps
CPU time 1471.51 seconds
Started Jun 13 01:49:34 PM PDT 24
Finished Jun 13 02:14:06 PM PDT 24
Peak memory 222936 kb
Host smart-dee81e71-86ed-458e-9cda-2ddddb247c76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747530711 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2747530711
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.106595607
Short name T233
Test name
Test status
Simulation time 37693444 ps
CPU time 1.35 seconds
Started Jun 13 01:51:49 PM PDT 24
Finished Jun 13 01:51:53 PM PDT 24
Peak memory 217688 kb
Host smart-183d12a0-fc67-4d78-aebf-9cddcee09225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106595607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.106595607
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1267651255
Short name T393
Test name
Test status
Simulation time 128571818 ps
CPU time 1.14 seconds
Started Jun 13 01:51:49 PM PDT 24
Finished Jun 13 01:51:52 PM PDT 24
Peak memory 216444 kb
Host smart-921b55ae-acd0-4f53-b8d4-164c4feeb2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267651255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1267651255
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.53479499
Short name T994
Test name
Test status
Simulation time 135152867 ps
CPU time 2.47 seconds
Started Jun 13 01:51:48 PM PDT 24
Finished Jun 13 01:51:54 PM PDT 24
Peak memory 219612 kb
Host smart-adc4af9d-4208-45e5-b262-b8dce11360c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53479499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.53479499
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1066231683
Short name T832
Test name
Test status
Simulation time 79902540 ps
CPU time 1.5 seconds
Started Jun 13 01:51:47 PM PDT 24
Finished Jun 13 01:51:51 PM PDT 24
Peak memory 218112 kb
Host smart-8741af2d-1f27-47ee-84cc-6cba70034a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066231683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1066231683
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2031276880
Short name T331
Test name
Test status
Simulation time 70380924 ps
CPU time 2.8 seconds
Started Jun 13 01:51:46 PM PDT 24
Finished Jun 13 01:51:52 PM PDT 24
Peak memory 219544 kb
Host smart-094fbcd2-84f4-4179-be24-62b6882df11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031276880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2031276880
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1787636421
Short name T627
Test name
Test status
Simulation time 41773752 ps
CPU time 1.69 seconds
Started Jun 13 01:51:48 PM PDT 24
Finished Jun 13 01:51:52 PM PDT 24
Peak memory 219612 kb
Host smart-3deace13-aa05-4fcb-894f-4af6a023adba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787636421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1787636421
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.385994955
Short name T477
Test name
Test status
Simulation time 75274714 ps
CPU time 1.45 seconds
Started Jun 13 01:51:56 PM PDT 24
Finished Jun 13 01:51:58 PM PDT 24
Peak memory 219316 kb
Host smart-98548be7-0c2c-4d92-a78f-8734d2a73b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385994955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.385994955
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3756772578
Short name T386
Test name
Test status
Simulation time 96309770 ps
CPU time 1.67 seconds
Started Jun 13 01:51:51 PM PDT 24
Finished Jun 13 01:51:54 PM PDT 24
Peak memory 218160 kb
Host smart-f31e3ec3-e5da-4799-93ad-f32dc19a14bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756772578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3756772578
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1811800011
Short name T21
Test name
Test status
Simulation time 65441058 ps
CPU time 2.5 seconds
Started Jun 13 01:51:52 PM PDT 24
Finished Jun 13 01:51:55 PM PDT 24
Peak memory 219508 kb
Host smart-15c64e6d-e796-4a91-b07b-40d7b7a300bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811800011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1811800011
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1256792689
Short name T621
Test name
Test status
Simulation time 65837982 ps
CPU time 1.32 seconds
Started Jun 13 01:51:49 PM PDT 24
Finished Jun 13 01:51:53 PM PDT 24
Peak memory 217800 kb
Host smart-44049fee-a8ce-4ed3-b961-a538bba42adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256792689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1256792689
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.598236220
Short name T192
Test name
Test status
Simulation time 31456314 ps
CPU time 1.2 seconds
Started Jun 13 01:49:33 PM PDT 24
Finished Jun 13 01:49:36 PM PDT 24
Peak memory 219152 kb
Host smart-85ac06a2-8348-42cb-a749-7a723bd65e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598236220 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.598236220
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1339617268
Short name T458
Test name
Test status
Simulation time 13526272 ps
CPU time 0.88 seconds
Started Jun 13 01:49:45 PM PDT 24
Finished Jun 13 01:49:47 PM PDT 24
Peak memory 206048 kb
Host smart-4580f277-8244-43d6-9806-2ec2eba05fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339617268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1339617268
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1056505170
Short name T713
Test name
Test status
Simulation time 12371517 ps
CPU time 0.93 seconds
Started Jun 13 01:49:33 PM PDT 24
Finished Jun 13 01:49:35 PM PDT 24
Peak memory 215588 kb
Host smart-38a87d48-5807-45e9-b254-8a1a53a6654d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056505170 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1056505170
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3166239091
Short name T150
Test name
Test status
Simulation time 76164390 ps
CPU time 1.15 seconds
Started Jun 13 01:49:37 PM PDT 24
Finished Jun 13 01:49:40 PM PDT 24
Peak memory 216204 kb
Host smart-18baeb87-399b-4a6b-81ce-1fbb75851f4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166239091 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3166239091
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3319746669
Short name T801
Test name
Test status
Simulation time 36826285 ps
CPU time 0.85 seconds
Started Jun 13 01:49:33 PM PDT 24
Finished Jun 13 01:49:35 PM PDT 24
Peak memory 217812 kb
Host smart-cb804fe5-67f1-4c46-bd41-2054cb795d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319746669 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3319746669
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2597615691
Short name T778
Test name
Test status
Simulation time 75851550 ps
CPU time 1.34 seconds
Started Jun 13 01:49:33 PM PDT 24
Finished Jun 13 01:49:36 PM PDT 24
Peak memory 217984 kb
Host smart-d4e723d2-1709-48cc-bfd6-be42fc98a8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597615691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2597615691
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_smoke.3699560088
Short name T489
Test name
Test status
Simulation time 115891882 ps
CPU time 0.89 seconds
Started Jun 13 01:49:34 PM PDT 24
Finished Jun 13 01:49:36 PM PDT 24
Peak memory 214600 kb
Host smart-13175e3c-57df-46d6-917b-dc5123206d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699560088 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3699560088
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.296309506
Short name T510
Test name
Test status
Simulation time 871334083 ps
CPU time 3.75 seconds
Started Jun 13 01:49:34 PM PDT 24
Finished Jun 13 01:49:39 PM PDT 24
Peak memory 216344 kb
Host smart-51226d63-f2d5-47fb-9a0a-f63fc07e6da7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296309506 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.296309506
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2878225210
Short name T724
Test name
Test status
Simulation time 76350162738 ps
CPU time 402.33 seconds
Started Jun 13 01:49:31 PM PDT 24
Finished Jun 13 01:56:15 PM PDT 24
Peak memory 217624 kb
Host smart-6eba6526-3aa4-4dee-8c37-c7d649ffc728
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878225210 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2878225210
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.155257264
Short name T823
Test name
Test status
Simulation time 71825205 ps
CPU time 1.22 seconds
Started Jun 13 01:51:51 PM PDT 24
Finished Jun 13 01:51:54 PM PDT 24
Peak memory 217776 kb
Host smart-2f8ed109-16e3-45c4-87dd-8c05ce7f5852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155257264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.155257264
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.808246498
Short name T310
Test name
Test status
Simulation time 79707546 ps
CPU time 1.49 seconds
Started Jun 13 01:51:56 PM PDT 24
Finished Jun 13 01:51:58 PM PDT 24
Peak memory 217928 kb
Host smart-5940c26e-b60e-4120-b627-0158377c32a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808246498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.808246498
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2355608127
Short name T322
Test name
Test status
Simulation time 292370769 ps
CPU time 1.69 seconds
Started Jun 13 01:51:52 PM PDT 24
Finished Jun 13 01:51:55 PM PDT 24
Peak memory 218000 kb
Host smart-d8ace91c-13d8-4889-a476-bb7a9b68b59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355608127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2355608127
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.801022354
Short name T90
Test name
Test status
Simulation time 56864204 ps
CPU time 1.59 seconds
Started Jun 13 01:51:50 PM PDT 24
Finished Jun 13 01:51:54 PM PDT 24
Peak memory 218016 kb
Host smart-57a7dbf0-5d0c-43c1-976a-039712fb1b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801022354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.801022354
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.4159180021
Short name T522
Test name
Test status
Simulation time 111692743 ps
CPU time 1.33 seconds
Started Jun 13 01:51:51 PM PDT 24
Finished Jun 13 01:51:54 PM PDT 24
Peak memory 217884 kb
Host smart-4cdb5743-a490-49da-9d71-a3a32f0d72f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159180021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.4159180021
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1215364064
Short name T894
Test name
Test status
Simulation time 96588463 ps
CPU time 1.61 seconds
Started Jun 13 01:51:55 PM PDT 24
Finished Jun 13 01:51:58 PM PDT 24
Peak memory 218112 kb
Host smart-0c70e03a-5d02-436f-81ed-14ae5cdf92f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215364064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1215364064
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3698262947
Short name T602
Test name
Test status
Simulation time 155142262 ps
CPU time 1.15 seconds
Started Jun 13 01:51:54 PM PDT 24
Finished Jun 13 01:51:56 PM PDT 24
Peak memory 217820 kb
Host smart-aebab021-9bbd-4d97-b0b5-fcf1eb1250d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698262947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3698262947
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.786572516
Short name T770
Test name
Test status
Simulation time 43491173 ps
CPU time 1.78 seconds
Started Jun 13 01:51:53 PM PDT 24
Finished Jun 13 01:51:55 PM PDT 24
Peak memory 217724 kb
Host smart-8955222d-12e4-4f01-9331-75a3e06b39d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786572516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.786572516
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2542348188
Short name T375
Test name
Test status
Simulation time 25668541 ps
CPU time 1.24 seconds
Started Jun 13 01:51:58 PM PDT 24
Finished Jun 13 01:52:00 PM PDT 24
Peak memory 216888 kb
Host smart-1c5192cb-5dc0-4bce-acba-a919928e2631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542348188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2542348188
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2958619916
Short name T680
Test name
Test status
Simulation time 88669646 ps
CPU time 1.27 seconds
Started Jun 13 01:49:36 PM PDT 24
Finished Jun 13 01:49:39 PM PDT 24
Peak memory 217824 kb
Host smart-50e2c060-2e5e-4717-88ff-4cea91da7eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958619916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2958619916
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2714117574
Short name T795
Test name
Test status
Simulation time 52140479 ps
CPU time 0.92 seconds
Started Jun 13 01:49:38 PM PDT 24
Finished Jun 13 01:49:41 PM PDT 24
Peak memory 214288 kb
Host smart-3e07824d-99ff-4742-b226-7f210436116e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714117574 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2714117574
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2534492268
Short name T490
Test name
Test status
Simulation time 16462468 ps
CPU time 0.98 seconds
Started Jun 13 01:49:37 PM PDT 24
Finished Jun 13 01:49:40 PM PDT 24
Peak memory 215816 kb
Host smart-10f1972b-40c6-4b0a-8fc1-3c08559d7b1e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534492268 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2534492268
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_err.4030949245
Short name T94
Test name
Test status
Simulation time 29715606 ps
CPU time 0.95 seconds
Started Jun 13 01:49:38 PM PDT 24
Finished Jun 13 01:49:40 PM PDT 24
Peak memory 217952 kb
Host smart-66b16c07-52f9-49d8-a624-90e4c640c227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030949245 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.4030949245
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2988535569
Short name T434
Test name
Test status
Simulation time 65967777 ps
CPU time 1.65 seconds
Started Jun 13 01:49:38 PM PDT 24
Finished Jun 13 01:49:41 PM PDT 24
Peak memory 218128 kb
Host smart-21fc9c03-e564-49cf-b864-b36426e9a26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988535569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2988535569
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1588487879
Short name T78
Test name
Test status
Simulation time 29149334 ps
CPU time 0.88 seconds
Started Jun 13 01:49:39 PM PDT 24
Finished Jun 13 01:49:42 PM PDT 24
Peak memory 214852 kb
Host smart-4877feb8-c3d5-4956-9bc8-0f3c15aa7db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588487879 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1588487879
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.654157926
Short name T990
Test name
Test status
Simulation time 67461343 ps
CPU time 0.95 seconds
Started Jun 13 01:49:36 PM PDT 24
Finished Jun 13 01:49:38 PM PDT 24
Peak memory 214628 kb
Host smart-4dc40a69-6dab-4dd5-87b7-e784342f2596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654157926 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.654157926
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3844697822
Short name T98
Test name
Test status
Simulation time 603027193 ps
CPU time 3.88 seconds
Started Jun 13 01:49:41 PM PDT 24
Finished Jun 13 01:49:46 PM PDT 24
Peak memory 214608 kb
Host smart-d4850deb-27a5-4088-b7b3-0a5e1ea6bf0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844697822 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3844697822
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.992433427
Short name T228
Test name
Test status
Simulation time 66455908672 ps
CPU time 1522.93 seconds
Started Jun 13 01:49:39 PM PDT 24
Finished Jun 13 02:15:04 PM PDT 24
Peak memory 222940 kb
Host smart-7bb03066-0657-4310-9f49-9629f9e2748b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992433427 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.992433427
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2272254701
Short name T413
Test name
Test status
Simulation time 75393373 ps
CPU time 1.02 seconds
Started Jun 13 01:51:52 PM PDT 24
Finished Jun 13 01:51:54 PM PDT 24
Peak memory 216688 kb
Host smart-5412db26-8cff-4cd0-a92b-b33fb42a8a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272254701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2272254701
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2829448049
Short name T756
Test name
Test status
Simulation time 169462307 ps
CPU time 1.01 seconds
Started Jun 13 01:51:53 PM PDT 24
Finished Jun 13 01:51:55 PM PDT 24
Peak memory 216684 kb
Host smart-2fc3dfad-80db-4b23-9674-f00f3af39d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829448049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2829448049
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3773324651
Short name T414
Test name
Test status
Simulation time 317333574 ps
CPU time 2.09 seconds
Started Jun 13 01:51:54 PM PDT 24
Finished Jun 13 01:51:57 PM PDT 24
Peak memory 218104 kb
Host smart-0d55ab09-c7a1-4b7c-b7cc-afd151bfee28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773324651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3773324651
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3624001740
Short name T577
Test name
Test status
Simulation time 45092414 ps
CPU time 1.71 seconds
Started Jun 13 01:51:56 PM PDT 24
Finished Jun 13 01:51:59 PM PDT 24
Peak memory 217992 kb
Host smart-4c30b6e5-18ee-4063-95bd-38e831165710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624001740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3624001740
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2916787840
Short name T661
Test name
Test status
Simulation time 60003016 ps
CPU time 1.27 seconds
Started Jun 13 01:51:54 PM PDT 24
Finished Jun 13 01:51:57 PM PDT 24
Peak memory 216628 kb
Host smart-cf08b1c2-2b9a-4be6-8090-93c4b9f6ca39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916787840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2916787840
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2850016861
Short name T573
Test name
Test status
Simulation time 31897519 ps
CPU time 1.36 seconds
Started Jun 13 01:51:54 PM PDT 24
Finished Jun 13 01:51:56 PM PDT 24
Peak memory 217888 kb
Host smart-fad0a102-1ead-4270-b50b-f4969dfe45c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850016861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2850016861
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2072276795
Short name T452
Test name
Test status
Simulation time 59780847 ps
CPU time 1.28 seconds
Started Jun 13 01:51:53 PM PDT 24
Finished Jun 13 01:51:55 PM PDT 24
Peak memory 219260 kb
Host smart-b6f0aae6-e546-4907-8019-8cdff2f95b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072276795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2072276795
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2050531387
Short name T570
Test name
Test status
Simulation time 32987544 ps
CPU time 1.4 seconds
Started Jun 13 01:51:58 PM PDT 24
Finished Jun 13 01:52:00 PM PDT 24
Peak memory 219268 kb
Host smart-635a2685-3c2a-4212-9c5d-ef40626ba117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050531387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2050531387
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1194252313
Short name T842
Test name
Test status
Simulation time 91287415 ps
CPU time 1.42 seconds
Started Jun 13 01:51:55 PM PDT 24
Finished Jun 13 01:51:58 PM PDT 24
Peak memory 216700 kb
Host smart-5aee600c-77aa-4d23-9181-e662cf4630b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194252313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1194252313
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.493240588
Short name T927
Test name
Test status
Simulation time 79471512 ps
CPU time 2.74 seconds
Started Jun 13 01:51:59 PM PDT 24
Finished Jun 13 01:52:02 PM PDT 24
Peak memory 217836 kb
Host smart-c046d5dc-08fc-4815-b887-dfcab2b86703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493240588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.493240588
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.496348702
Short name T184
Test name
Test status
Simulation time 47052966 ps
CPU time 1.11 seconds
Started Jun 13 01:49:37 PM PDT 24
Finished Jun 13 01:49:39 PM PDT 24
Peak memory 219920 kb
Host smart-d2b1158d-a89f-4d11-be1d-2e14ad3f93ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496348702 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.496348702
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.235074090
Short name T73
Test name
Test status
Simulation time 64785616 ps
CPU time 0.92 seconds
Started Jun 13 01:49:38 PM PDT 24
Finished Jun 13 01:49:40 PM PDT 24
Peak memory 206112 kb
Host smart-51678365-625d-4d69-9fd7-2d8babf4d212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235074090 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.235074090
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.914983897
Short name T841
Test name
Test status
Simulation time 154361156 ps
CPU time 1.17 seconds
Started Jun 13 01:49:38 PM PDT 24
Finished Jun 13 01:49:41 PM PDT 24
Peak memory 217912 kb
Host smart-66447902-7be4-4360-86a3-fb1bb6ae2766
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914983897 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.914983897
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3888318509
Short name T965
Test name
Test status
Simulation time 19346059 ps
CPU time 1.08 seconds
Started Jun 13 01:49:40 PM PDT 24
Finished Jun 13 01:49:42 PM PDT 24
Peak memory 218024 kb
Host smart-a30d0c2c-8c14-4ce4-b477-5f3eedba1bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888318509 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3888318509
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1902284929
Short name T46
Test name
Test status
Simulation time 179761342 ps
CPU time 1.38 seconds
Started Jun 13 01:49:46 PM PDT 24
Finished Jun 13 01:49:48 PM PDT 24
Peak memory 216540 kb
Host smart-6363307d-a9b0-4c78-9734-4b9699773ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902284929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1902284929
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3661294203
Short name T376
Test name
Test status
Simulation time 55622779 ps
CPU time 0.96 seconds
Started Jun 13 01:49:39 PM PDT 24
Finished Jun 13 01:49:41 PM PDT 24
Peak memory 223220 kb
Host smart-16e34873-b19a-4666-bee0-126d078e100c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661294203 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3661294203
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1078259138
Short name T268
Test name
Test status
Simulation time 15697922 ps
CPU time 1.03 seconds
Started Jun 13 01:49:39 PM PDT 24
Finished Jun 13 01:49:41 PM PDT 24
Peak memory 214600 kb
Host smart-a00f7a75-dac0-4c16-89c0-ef5b0eb2860c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078259138 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1078259138
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3907063253
Short name T354
Test name
Test status
Simulation time 220982746 ps
CPU time 4.48 seconds
Started Jun 13 01:49:36 PM PDT 24
Finished Jun 13 01:49:42 PM PDT 24
Peak memory 219036 kb
Host smart-e0ece72c-7729-4b6f-ba0e-14481b723a4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907063253 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3907063253
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2917961193
Short name T527
Test name
Test status
Simulation time 73668019077 ps
CPU time 882.74 seconds
Started Jun 13 01:49:36 PM PDT 24
Finished Jun 13 02:04:20 PM PDT 24
Peak memory 219300 kb
Host smart-d887b9c0-2389-41a6-94b0-6896ff9ae28c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917961193 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2917961193
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2782572012
Short name T734
Test name
Test status
Simulation time 86416297 ps
CPU time 1.31 seconds
Started Jun 13 01:51:59 PM PDT 24
Finished Jun 13 01:52:01 PM PDT 24
Peak memory 216824 kb
Host smart-b315c169-6cba-4912-a5f7-d93a6ad23271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782572012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2782572012
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2849567339
Short name T921
Test name
Test status
Simulation time 34646885 ps
CPU time 1.29 seconds
Started Jun 13 01:52:00 PM PDT 24
Finished Jun 13 01:52:02 PM PDT 24
Peak memory 216620 kb
Host smart-aec99618-e2a9-49d8-96e6-ff221b2bb76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849567339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2849567339
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1105599940
Short name T555
Test name
Test status
Simulation time 44174525 ps
CPU time 1.3 seconds
Started Jun 13 01:52:02 PM PDT 24
Finished Jun 13 01:52:05 PM PDT 24
Peak memory 216628 kb
Host smart-b99af3d3-f8d4-4320-84fe-a9a12edbbde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105599940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1105599940
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3549963853
Short name T970
Test name
Test status
Simulation time 51990032 ps
CPU time 1.27 seconds
Started Jun 13 01:52:02 PM PDT 24
Finished Jun 13 01:52:04 PM PDT 24
Peak memory 216712 kb
Host smart-15619bef-eef5-4350-9f62-fd2c87071133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549963853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3549963853
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1882324920
Short name T739
Test name
Test status
Simulation time 56925620 ps
CPU time 2.16 seconds
Started Jun 13 01:52:01 PM PDT 24
Finished Jun 13 01:52:05 PM PDT 24
Peak memory 219516 kb
Host smart-7283a6ec-f791-4d85-b884-e218ac97b93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882324920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1882324920
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.273881126
Short name T64
Test name
Test status
Simulation time 124942111 ps
CPU time 1.18 seconds
Started Jun 13 01:51:59 PM PDT 24
Finished Jun 13 01:52:01 PM PDT 24
Peak memory 216704 kb
Host smart-d84d97b4-f6e7-45f9-a2d7-6e6487be3c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273881126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.273881126
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.49006094
Short name T556
Test name
Test status
Simulation time 90070437 ps
CPU time 1.54 seconds
Started Jun 13 01:51:59 PM PDT 24
Finished Jun 13 01:52:02 PM PDT 24
Peak memory 218160 kb
Host smart-8a0e5807-3b01-4f57-8962-c2b45e54d6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49006094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.49006094
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.60013851
Short name T923
Test name
Test status
Simulation time 52869145 ps
CPU time 1.7 seconds
Started Jun 13 01:52:03 PM PDT 24
Finished Jun 13 01:52:05 PM PDT 24
Peak memory 219432 kb
Host smart-ba166435-f0d6-4de0-80dc-75ada8b03bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60013851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.60013851
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.889055541
Short name T816
Test name
Test status
Simulation time 59577184 ps
CPU time 1.58 seconds
Started Jun 13 01:52:01 PM PDT 24
Finished Jun 13 01:52:03 PM PDT 24
Peak memory 218144 kb
Host smart-ddb3c336-26d7-41f5-89a5-e3801571b04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889055541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.889055541
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1586609867
Short name T653
Test name
Test status
Simulation time 27122303 ps
CPU time 1.22 seconds
Started Jun 13 01:49:38 PM PDT 24
Finished Jun 13 01:49:40 PM PDT 24
Peak memory 220140 kb
Host smart-04be816c-30ef-4e30-ac58-e70a17510a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586609867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1586609867
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1607742783
Short name T344
Test name
Test status
Simulation time 50478813 ps
CPU time 0.92 seconds
Started Jun 13 01:49:45 PM PDT 24
Finished Jun 13 01:49:46 PM PDT 24
Peak memory 214584 kb
Host smart-1599bea6-bd84-4376-9d4d-989599b9dbd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607742783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1607742783
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1566396223
Short name T908
Test name
Test status
Simulation time 83957273 ps
CPU time 0.87 seconds
Started Jun 13 01:49:38 PM PDT 24
Finished Jun 13 01:49:41 PM PDT 24
Peak memory 215668 kb
Host smart-d87ea828-0467-4b92-a04e-6ae4a5dd4fda
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566396223 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1566396223
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2636531738
Short name T132
Test name
Test status
Simulation time 26778336 ps
CPU time 1 seconds
Started Jun 13 01:49:46 PM PDT 24
Finished Jun 13 01:49:47 PM PDT 24
Peak memory 219192 kb
Host smart-890540cf-8f8c-431f-8192-c9e5688b2418
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636531738 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2636531738
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1956276798
Short name T779
Test name
Test status
Simulation time 35408573 ps
CPU time 0.89 seconds
Started Jun 13 01:49:38 PM PDT 24
Finished Jun 13 01:49:41 PM PDT 24
Peak memory 217812 kb
Host smart-b8df1ca9-e5ca-4f3e-9a35-170d2088cb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956276798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1956276798
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3085779168
Short name T561
Test name
Test status
Simulation time 91043534 ps
CPU time 1.09 seconds
Started Jun 13 01:49:40 PM PDT 24
Finished Jun 13 01:49:43 PM PDT 24
Peak memory 216532 kb
Host smart-54f9fcf5-ecbd-4b9f-9195-6a0cc12fb59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085779168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3085779168
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2281401774
Short name T584
Test name
Test status
Simulation time 23196998 ps
CPU time 1.15 seconds
Started Jun 13 01:49:39 PM PDT 24
Finished Jun 13 01:49:42 PM PDT 24
Peak memory 214748 kb
Host smart-84205bad-99fd-4a6b-9c43-5b7ed39e5c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281401774 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2281401774
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.857484561
Short name T637
Test name
Test status
Simulation time 27753213 ps
CPU time 0.95 seconds
Started Jun 13 01:49:37 PM PDT 24
Finished Jun 13 01:49:40 PM PDT 24
Peak memory 214628 kb
Host smart-79accfaa-4b69-41c0-aaa2-975f543d3d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857484561 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.857484561
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3918975764
Short name T767
Test name
Test status
Simulation time 177665138 ps
CPU time 1.5 seconds
Started Jun 13 01:49:37 PM PDT 24
Finished Jun 13 01:49:40 PM PDT 24
Peak memory 216636 kb
Host smart-3a367008-b12e-4033-96b8-bcd6b6d8e399
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918975764 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3918975764
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2662642679
Short name T647
Test name
Test status
Simulation time 229479694610 ps
CPU time 466.55 seconds
Started Jun 13 01:49:46 PM PDT 24
Finished Jun 13 01:57:33 PM PDT 24
Peak memory 218252 kb
Host smart-ac09d596-7673-407d-8604-e765fa2638d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662642679 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2662642679
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2670032487
Short name T987
Test name
Test status
Simulation time 49277008 ps
CPU time 1.93 seconds
Started Jun 13 01:52:01 PM PDT 24
Finished Jun 13 01:52:03 PM PDT 24
Peak memory 217884 kb
Host smart-51b3fe23-e40e-437e-848a-c3bae6ef99ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670032487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2670032487
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1511832531
Short name T922
Test name
Test status
Simulation time 64344490 ps
CPU time 1.11 seconds
Started Jun 13 01:52:00 PM PDT 24
Finished Jun 13 01:52:02 PM PDT 24
Peak memory 216772 kb
Host smart-e1f7ac6c-76ab-4f52-b810-63db230681aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511832531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1511832531
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.460405213
Short name T364
Test name
Test status
Simulation time 37324774 ps
CPU time 1.49 seconds
Started Jun 13 01:52:00 PM PDT 24
Finished Jun 13 01:52:02 PM PDT 24
Peak memory 217832 kb
Host smart-359534e9-2eb5-4cd9-b2ef-57cc8c519334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460405213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.460405213
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2760040789
Short name T681
Test name
Test status
Simulation time 36639358 ps
CPU time 1.66 seconds
Started Jun 13 01:52:03 PM PDT 24
Finished Jun 13 01:52:06 PM PDT 24
Peak memory 217888 kb
Host smart-c47358f1-742d-4d6b-af65-dd571e8b59d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760040789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2760040789
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.449857684
Short name T849
Test name
Test status
Simulation time 101822266 ps
CPU time 1.3 seconds
Started Jun 13 01:52:03 PM PDT 24
Finished Jun 13 01:52:05 PM PDT 24
Peak memory 218136 kb
Host smart-bc87b760-f585-4a5c-9163-d2f37df2ffb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449857684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.449857684
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3335391998
Short name T45
Test name
Test status
Simulation time 49960932 ps
CPU time 1.93 seconds
Started Jun 13 01:52:03 PM PDT 24
Finished Jun 13 01:52:06 PM PDT 24
Peak memory 216792 kb
Host smart-e27a8d7e-4a2d-40ca-9c3a-080d681e377d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335391998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3335391998
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.559219479
Short name T761
Test name
Test status
Simulation time 42023531 ps
CPU time 1.45 seconds
Started Jun 13 01:52:00 PM PDT 24
Finished Jun 13 01:52:02 PM PDT 24
Peak memory 217828 kb
Host smart-a71f8d35-2258-4757-880b-4bb286513fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559219479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.559219479
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3354574099
Short name T26
Test name
Test status
Simulation time 46576353 ps
CPU time 1.58 seconds
Started Jun 13 01:52:02 PM PDT 24
Finished Jun 13 01:52:04 PM PDT 24
Peak memory 217748 kb
Host smart-1788d07f-3ae8-4810-8f3b-e7b3b92e38c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354574099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3354574099
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.980756521
Short name T282
Test name
Test status
Simulation time 66130942 ps
CPU time 1.33 seconds
Started Jun 13 01:52:02 PM PDT 24
Finished Jun 13 01:52:05 PM PDT 24
Peak memory 219316 kb
Host smart-3f008180-0887-4eff-9830-9cbf12d2070e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980756521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.980756521
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.747985304
Short name T347
Test name
Test status
Simulation time 92424626 ps
CPU time 1.15 seconds
Started Jun 13 01:52:05 PM PDT 24
Finished Jun 13 01:52:07 PM PDT 24
Peak memory 217808 kb
Host smart-a29deec5-0ef4-4443-8d0b-8b66ae4aea34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747985304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.747985304
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2181455901
Short name T868
Test name
Test status
Simulation time 47080286 ps
CPU time 1.24 seconds
Started Jun 13 01:49:46 PM PDT 24
Finished Jun 13 01:49:48 PM PDT 24
Peak memory 218964 kb
Host smart-61b2e46a-0671-413a-9202-d50e56bc54b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181455901 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2181455901
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3425266172
Short name T441
Test name
Test status
Simulation time 13495504 ps
CPU time 0.88 seconds
Started Jun 13 01:49:43 PM PDT 24
Finished Jun 13 01:49:45 PM PDT 24
Peak memory 214568 kb
Host smart-b57705e0-2a74-44cc-94b6-788d3cede649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425266172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3425266172
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_err.3525032847
Short name T427
Test name
Test status
Simulation time 49874916 ps
CPU time 0.87 seconds
Started Jun 13 01:49:48 PM PDT 24
Finished Jun 13 01:49:50 PM PDT 24
Peak memory 217872 kb
Host smart-25432743-1e62-4bd5-941b-e9d929a63105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525032847 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3525032847
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_intr.796310733
Short name T36
Test name
Test status
Simulation time 24555668 ps
CPU time 0.91 seconds
Started Jun 13 01:49:48 PM PDT 24
Finished Jun 13 01:49:50 PM PDT 24
Peak memory 215120 kb
Host smart-5c2f5401-82ca-4a07-9418-bd13458f698b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796310733 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.796310733
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3081215973
Short name T387
Test name
Test status
Simulation time 24375337 ps
CPU time 0.94 seconds
Started Jun 13 01:49:44 PM PDT 24
Finished Jun 13 01:49:46 PM PDT 24
Peak memory 214624 kb
Host smart-59fca65e-bd6b-4d5b-b34b-d0f5adf2b925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081215973 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3081215973
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2945112324
Short name T759
Test name
Test status
Simulation time 258818538 ps
CPU time 5.15 seconds
Started Jun 13 01:49:42 PM PDT 24
Finished Jun 13 01:49:48 PM PDT 24
Peak memory 216596 kb
Host smart-f4c914f4-10f9-4f76-a5b8-fcc770b0a9be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945112324 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2945112324
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.4050651917
Short name T409
Test name
Test status
Simulation time 142359432099 ps
CPU time 699.65 seconds
Started Jun 13 01:49:43 PM PDT 24
Finished Jun 13 02:01:24 PM PDT 24
Peak memory 222928 kb
Host smart-a1aef9ce-544a-4b7b-b258-82676bb01284
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050651917 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.4050651917
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3743152108
Short name T380
Test name
Test status
Simulation time 60747980 ps
CPU time 1.38 seconds
Started Jun 13 01:52:09 PM PDT 24
Finished Jun 13 01:52:12 PM PDT 24
Peak memory 219180 kb
Host smart-09f335b7-ef2a-4b12-afd8-a0edeaa1c89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743152108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3743152108
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2834800432
Short name T432
Test name
Test status
Simulation time 48239472 ps
CPU time 1.61 seconds
Started Jun 13 01:52:12 PM PDT 24
Finished Jun 13 01:52:15 PM PDT 24
Peak memory 217828 kb
Host smart-9210558b-959d-4934-8615-c1bdeb2ba227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834800432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2834800432
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3307387113
Short name T480
Test name
Test status
Simulation time 140445986 ps
CPU time 2.98 seconds
Started Jun 13 01:52:07 PM PDT 24
Finished Jun 13 01:52:12 PM PDT 24
Peak memory 217916 kb
Host smart-8e25fb43-73d0-4c86-8069-7b85ae2e6237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307387113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3307387113
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.4029667281
Short name T601
Test name
Test status
Simulation time 49461281 ps
CPU time 1.2 seconds
Started Jun 13 01:52:10 PM PDT 24
Finished Jun 13 01:52:13 PM PDT 24
Peak memory 216580 kb
Host smart-54eaca2d-c9ce-4cfa-95df-05452736fb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029667281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.4029667281
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2892066366
Short name T505
Test name
Test status
Simulation time 56115421 ps
CPU time 1.44 seconds
Started Jun 13 01:52:06 PM PDT 24
Finished Jun 13 01:52:07 PM PDT 24
Peak memory 217576 kb
Host smart-4e2fcb37-a0c1-4d8a-856a-2c9ce8e80da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892066366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2892066366
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2508158256
Short name T709
Test name
Test status
Simulation time 56638244 ps
CPU time 1.23 seconds
Started Jun 13 01:52:13 PM PDT 24
Finished Jun 13 01:52:16 PM PDT 24
Peak memory 216820 kb
Host smart-08b60c25-3da1-4976-bc6c-badf67a1893d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508158256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2508158256
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.4169220246
Short name T719
Test name
Test status
Simulation time 78233630 ps
CPU time 1.41 seconds
Started Jun 13 01:52:07 PM PDT 24
Finished Jun 13 01:52:10 PM PDT 24
Peak memory 219480 kb
Host smart-695382aa-f027-4f36-aac7-590d75a5f553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169220246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.4169220246
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1371513806
Short name T634
Test name
Test status
Simulation time 53152478 ps
CPU time 1.4 seconds
Started Jun 13 01:52:11 PM PDT 24
Finished Jun 13 01:52:14 PM PDT 24
Peak memory 218024 kb
Host smart-6fc98466-f874-4ce5-bac9-1f6454d16a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371513806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1371513806
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3794572660
Short name T486
Test name
Test status
Simulation time 35326235 ps
CPU time 1.42 seconds
Started Jun 13 01:52:09 PM PDT 24
Finished Jun 13 01:52:12 PM PDT 24
Peak memory 217904 kb
Host smart-480f90b7-34be-4c74-9cfd-741e36bde614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794572660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3794572660
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3781828830
Short name T905
Test name
Test status
Simulation time 32081546 ps
CPU time 1.22 seconds
Started Jun 13 01:52:07 PM PDT 24
Finished Jun 13 01:52:10 PM PDT 24
Peak memory 219220 kb
Host smart-9007fe94-f605-48c5-9807-5deeae4dfec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781828830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3781828830
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.490039735
Short name T948
Test name
Test status
Simulation time 142550346 ps
CPU time 1.29 seconds
Started Jun 13 01:49:43 PM PDT 24
Finished Jun 13 01:49:45 PM PDT 24
Peak memory 218032 kb
Host smart-81b6009c-16b9-4f98-b0cf-c85430e18e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490039735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.490039735
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1994049422
Short name T340
Test name
Test status
Simulation time 75909081 ps
CPU time 0.92 seconds
Started Jun 13 01:49:43 PM PDT 24
Finished Jun 13 01:49:44 PM PDT 24
Peak memory 214288 kb
Host smart-36ddad19-0b18-4adc-8416-afa559ef2327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994049422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1994049422
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.656177485
Short name T726
Test name
Test status
Simulation time 41072629 ps
CPU time 1.4 seconds
Started Jun 13 01:49:45 PM PDT 24
Finished Jun 13 01:49:47 PM PDT 24
Peak memory 216308 kb
Host smart-cec477c9-666d-4d9d-b8be-0c86842aefe3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656177485 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_di
sable_auto_req_mode.656177485
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.906204137
Short name T111
Test name
Test status
Simulation time 21964094 ps
CPU time 1.15 seconds
Started Jun 13 01:49:46 PM PDT 24
Finished Jun 13 01:49:48 PM PDT 24
Peak memory 228880 kb
Host smart-c9602588-f98a-4dfd-9399-a259c4f9836e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906204137 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.906204137
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.725187599
Short name T526
Test name
Test status
Simulation time 91385797 ps
CPU time 1.26 seconds
Started Jun 13 01:49:44 PM PDT 24
Finished Jun 13 01:49:46 PM PDT 24
Peak memory 218992 kb
Host smart-2ca2943f-e8ec-4422-80fb-62b25852d355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725187599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.725187599
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.733916754
Short name T819
Test name
Test status
Simulation time 23072878 ps
CPU time 1.1 seconds
Started Jun 13 01:49:44 PM PDT 24
Finished Jun 13 01:49:46 PM PDT 24
Peak memory 214748 kb
Host smart-300f5516-9342-4413-abc8-10ea443cd657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733916754 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.733916754
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2231562480
Short name T731
Test name
Test status
Simulation time 40488767 ps
CPU time 0.92 seconds
Started Jun 13 01:49:52 PM PDT 24
Finished Jun 13 01:49:55 PM PDT 24
Peak memory 214636 kb
Host smart-87826e5e-8497-433b-8253-e05472eb8cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231562480 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2231562480
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1559178324
Short name T836
Test name
Test status
Simulation time 317900166 ps
CPU time 6.53 seconds
Started Jun 13 01:49:42 PM PDT 24
Finished Jun 13 01:49:49 PM PDT 24
Peak memory 214716 kb
Host smart-539f6467-b283-4e72-a806-267d43742a40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559178324 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1559178324
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3084832351
Short name T674
Test name
Test status
Simulation time 217517587649 ps
CPU time 1519.79 seconds
Started Jun 13 01:49:44 PM PDT 24
Finished Jun 13 02:15:05 PM PDT 24
Peak memory 224996 kb
Host smart-05ea9d2a-2379-4c80-94c7-6f51b4366183
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084832351 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3084832351
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.261195642
Short name T321
Test name
Test status
Simulation time 68984842 ps
CPU time 2.65 seconds
Started Jun 13 01:52:07 PM PDT 24
Finished Jun 13 01:52:11 PM PDT 24
Peak memory 217900 kb
Host smart-85057071-fe36-45b2-9dae-e77e354f4b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261195642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.261195642
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.359362882
Short name T325
Test name
Test status
Simulation time 57589197 ps
CPU time 1.45 seconds
Started Jun 13 01:52:08 PM PDT 24
Finished Jun 13 01:52:11 PM PDT 24
Peak memory 219304 kb
Host smart-818b572f-c80d-42b9-827d-3f79216ec896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359362882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.359362882
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2557297165
Short name T722
Test name
Test status
Simulation time 51058100 ps
CPU time 1.28 seconds
Started Jun 13 01:52:08 PM PDT 24
Finished Jun 13 01:52:11 PM PDT 24
Peak memory 218080 kb
Host smart-0812142c-9e8b-4727-9081-944015cdaa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557297165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2557297165
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2310710762
Short name T873
Test name
Test status
Simulation time 63222633 ps
CPU time 1.33 seconds
Started Jun 13 01:52:13 PM PDT 24
Finished Jun 13 01:52:16 PM PDT 24
Peak memory 216616 kb
Host smart-db674e78-b537-4ee0-b5ca-b0252c763702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310710762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2310710762
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.765335083
Short name T504
Test name
Test status
Simulation time 63364051 ps
CPU time 1 seconds
Started Jun 13 01:52:07 PM PDT 24
Finished Jun 13 01:52:09 PM PDT 24
Peak memory 216580 kb
Host smart-610c78fd-63ee-4846-a934-fe520f59efd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765335083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.765335083
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3413644132
Short name T871
Test name
Test status
Simulation time 54428094 ps
CPU time 1.34 seconds
Started Jun 13 01:52:08 PM PDT 24
Finished Jun 13 01:52:11 PM PDT 24
Peak memory 217680 kb
Host smart-18533c7a-8d92-41ed-9e4e-da533ae8095d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413644132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3413644132
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2483373565
Short name T320
Test name
Test status
Simulation time 91757577 ps
CPU time 1.33 seconds
Started Jun 13 01:52:06 PM PDT 24
Finished Jun 13 01:52:08 PM PDT 24
Peak memory 216976 kb
Host smart-8d28dbcc-3a01-45e9-8a36-ad08397f9f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483373565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2483373565
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2438149180
Short name T717
Test name
Test status
Simulation time 37474431 ps
CPU time 1.45 seconds
Started Jun 13 01:52:08 PM PDT 24
Finished Jun 13 01:52:11 PM PDT 24
Peak memory 217876 kb
Host smart-5edda4ac-d28c-4ffa-8ecf-33517a1efe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438149180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2438149180
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1219477534
Short name T332
Test name
Test status
Simulation time 101907389 ps
CPU time 1.3 seconds
Started Jun 13 01:52:09 PM PDT 24
Finished Jun 13 01:52:12 PM PDT 24
Peak memory 219328 kb
Host smart-92fdb53a-b2f7-482e-bc02-29cc093f8f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219477534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1219477534
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2897304702
Short name T405
Test name
Test status
Simulation time 108216727 ps
CPU time 1.31 seconds
Started Jun 13 01:52:08 PM PDT 24
Finished Jun 13 01:52:11 PM PDT 24
Peak memory 218148 kb
Host smart-6ecd377b-82f7-45ee-9512-a36f17f9935e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897304702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2897304702
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1201828
Short name T103
Test name
Test status
Simulation time 171995458 ps
CPU time 1.1 seconds
Started Jun 13 01:49:54 PM PDT 24
Finished Jun 13 01:49:56 PM PDT 24
Peak memory 218064 kb
Host smart-fc4cc1be-57ae-464a-92e4-0f8d109314b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1201828
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2196629352
Short name T712
Test name
Test status
Simulation time 45641267 ps
CPU time 0.98 seconds
Started Jun 13 01:49:54 PM PDT 24
Finished Jun 13 01:49:57 PM PDT 24
Peak memory 214292 kb
Host smart-e0522bd3-37c1-4acb-ba73-c76c4ba0eac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196629352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2196629352
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3239966549
Short name T179
Test name
Test status
Simulation time 12943718 ps
CPU time 0.93 seconds
Started Jun 13 01:49:54 PM PDT 24
Finished Jun 13 01:49:56 PM PDT 24
Peak memory 215972 kb
Host smart-0fa16e2d-0553-4091-8b1f-049ee37b3194
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239966549 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3239966549
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1579683012
Short name T367
Test name
Test status
Simulation time 51293129 ps
CPU time 1.5 seconds
Started Jun 13 01:49:55 PM PDT 24
Finished Jun 13 01:49:59 PM PDT 24
Peak memory 216200 kb
Host smart-d40a518c-66df-4489-8d62-e6dd049a2f91
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579683012 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1579683012
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2789724071
Short name T834
Test name
Test status
Simulation time 23509853 ps
CPU time 0.92 seconds
Started Jun 13 01:49:52 PM PDT 24
Finished Jun 13 01:49:54 PM PDT 24
Peak memory 218160 kb
Host smart-94ae0bf0-ddf1-493c-95a7-04f5b8200493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789724071 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2789724071
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3377857295
Short name T744
Test name
Test status
Simulation time 104368160 ps
CPU time 2.39 seconds
Started Jun 13 01:49:43 PM PDT 24
Finished Jun 13 01:49:46 PM PDT 24
Peak memory 219324 kb
Host smart-2f3f8637-8bb1-4483-ab41-5197a35b43a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377857295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3377857295
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.4075012743
Short name T775
Test name
Test status
Simulation time 28869205 ps
CPU time 1.12 seconds
Started Jun 13 01:49:52 PM PDT 24
Finished Jun 13 01:49:54 PM PDT 24
Peak memory 223376 kb
Host smart-8b87788b-ca03-416a-9e14-5793990d88f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075012743 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.4075012743
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2672450876
Short name T675
Test name
Test status
Simulation time 77069932 ps
CPU time 0.93 seconds
Started Jun 13 01:49:44 PM PDT 24
Finished Jun 13 01:49:46 PM PDT 24
Peak memory 214600 kb
Host smart-e6c80937-f6f2-46a9-862e-27c69e5695fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672450876 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2672450876
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2994719978
Short name T361
Test name
Test status
Simulation time 255270281 ps
CPU time 4.91 seconds
Started Jun 13 01:49:43 PM PDT 24
Finished Jun 13 01:49:48 PM PDT 24
Peak memory 219380 kb
Host smart-4603e12b-ea17-4256-b5e5-a60b8b43aa6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994719978 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2994719978
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2462676648
Short name T575
Test name
Test status
Simulation time 23747971722 ps
CPU time 563.29 seconds
Started Jun 13 01:49:53 PM PDT 24
Finished Jun 13 01:59:18 PM PDT 24
Peak memory 222684 kb
Host smart-c8559c24-7566-40ea-a34e-129d44f15dfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462676648 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2462676648
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2103618738
Short name T314
Test name
Test status
Simulation time 72039404 ps
CPU time 1.39 seconds
Started Jun 13 01:52:07 PM PDT 24
Finished Jun 13 01:52:10 PM PDT 24
Peak memory 219280 kb
Host smart-6e90a3a9-498b-42e4-9abc-86f611a25c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103618738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2103618738
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2883534671
Short name T962
Test name
Test status
Simulation time 61747938 ps
CPU time 1.42 seconds
Started Jun 13 01:52:08 PM PDT 24
Finished Jun 13 01:52:11 PM PDT 24
Peak memory 217964 kb
Host smart-afea33a1-4304-4738-a60b-f8a4cbd1db9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883534671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2883534671
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2444387356
Short name T979
Test name
Test status
Simulation time 34362910 ps
CPU time 1.43 seconds
Started Jun 13 01:52:09 PM PDT 24
Finished Jun 13 01:52:12 PM PDT 24
Peak memory 216900 kb
Host smart-05678e47-1e0b-4d6e-b159-94cf8562b945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444387356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2444387356
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2762429442
Short name T406
Test name
Test status
Simulation time 39469526 ps
CPU time 1.65 seconds
Started Jun 13 01:52:13 PM PDT 24
Finished Jun 13 01:52:16 PM PDT 24
Peak memory 217788 kb
Host smart-6f300c78-7e1d-4690-a8ed-ef0382c8206c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762429442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2762429442
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1924594635
Short name T932
Test name
Test status
Simulation time 129020229 ps
CPU time 1.3 seconds
Started Jun 13 01:52:06 PM PDT 24
Finished Jun 13 01:52:08 PM PDT 24
Peak memory 216468 kb
Host smart-72f97a59-b6ed-40f6-82ca-9000e50214c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924594635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1924594635
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2880242045
Short name T365
Test name
Test status
Simulation time 28444643 ps
CPU time 1.28 seconds
Started Jun 13 01:52:10 PM PDT 24
Finished Jun 13 01:52:13 PM PDT 24
Peak memory 217860 kb
Host smart-e7b83fde-6301-4218-ae48-8081725e33cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880242045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2880242045
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1952929383
Short name T74
Test name
Test status
Simulation time 115441277 ps
CPU time 1.76 seconds
Started Jun 13 01:52:14 PM PDT 24
Finished Jun 13 01:52:18 PM PDT 24
Peak memory 218320 kb
Host smart-dc370b81-5d79-4b93-8dbb-52cdb289b43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952929383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1952929383
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2548650720
Short name T629
Test name
Test status
Simulation time 41652998 ps
CPU time 1.64 seconds
Started Jun 13 01:52:13 PM PDT 24
Finished Jun 13 01:52:16 PM PDT 24
Peak memory 216676 kb
Host smart-e03ee4e8-f41e-4870-8b86-850428a91a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548650720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2548650720
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2437838902
Short name T716
Test name
Test status
Simulation time 129556111 ps
CPU time 2.95 seconds
Started Jun 13 01:52:07 PM PDT 24
Finished Jun 13 01:52:12 PM PDT 24
Peak memory 217876 kb
Host smart-34b1edac-1f86-484c-85ef-16d3a0c50b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437838902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2437838902
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2689963575
Short name T814
Test name
Test status
Simulation time 236146377 ps
CPU time 3.19 seconds
Started Jun 13 01:52:12 PM PDT 24
Finished Jun 13 01:52:17 PM PDT 24
Peak memory 219416 kb
Host smart-62a14a4d-847a-4c31-a7a2-1665797e3e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689963575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2689963575
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.74498803
Short name T917
Test name
Test status
Simulation time 24266340 ps
CPU time 1.14 seconds
Started Jun 13 01:49:53 PM PDT 24
Finished Jun 13 01:49:56 PM PDT 24
Peak memory 217896 kb
Host smart-89c296c0-aa94-4caf-b361-d7710f70c24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74498803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.74498803
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1060682463
Short name T366
Test name
Test status
Simulation time 13364925 ps
CPU time 0.88 seconds
Started Jun 13 01:49:54 PM PDT 24
Finished Jun 13 01:49:57 PM PDT 24
Peak memory 206044 kb
Host smart-3d9cb54a-5018-4670-abfa-3bd077b8937f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060682463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1060682463
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.654053763
Short name T157
Test name
Test status
Simulation time 18672126 ps
CPU time 0.93 seconds
Started Jun 13 01:49:53 PM PDT 24
Finished Jun 13 01:49:56 PM PDT 24
Peak memory 214828 kb
Host smart-5669cbb8-791f-4fbb-b83d-01519c4ce598
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654053763 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.654053763
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3692634862
Short name T649
Test name
Test status
Simulation time 75683817 ps
CPU time 1.1 seconds
Started Jun 13 01:49:57 PM PDT 24
Finished Jun 13 01:50:00 PM PDT 24
Peak memory 216288 kb
Host smart-0d47b22c-805a-440f-bb40-d46c23d46016
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692634862 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3692634862
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1394964440
Short name T96
Test name
Test status
Simulation time 41372850 ps
CPU time 1.16 seconds
Started Jun 13 01:49:53 PM PDT 24
Finished Jun 13 01:49:56 PM PDT 24
Peak memory 219192 kb
Host smart-f0c64fc6-ad3f-439f-823e-838a09819810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394964440 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1394964440
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2986221107
Short name T385
Test name
Test status
Simulation time 106672625 ps
CPU time 1.32 seconds
Started Jun 13 01:49:53 PM PDT 24
Finished Jun 13 01:49:56 PM PDT 24
Peak memory 217888 kb
Host smart-4e7d488f-caa4-4c4b-b4fb-875618c60717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986221107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2986221107
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_smoke.1082454160
Short name T644
Test name
Test status
Simulation time 35727835 ps
CPU time 0.88 seconds
Started Jun 13 01:49:51 PM PDT 24
Finished Jun 13 01:49:53 PM PDT 24
Peak memory 214612 kb
Host smart-e61ad74a-5f86-41b7-90f8-8741220b5ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082454160 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1082454160
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2201935002
Short name T396
Test name
Test status
Simulation time 115023040 ps
CPU time 1.79 seconds
Started Jun 13 01:49:54 PM PDT 24
Finished Jun 13 01:49:57 PM PDT 24
Peak memory 216708 kb
Host smart-c0b9ebaf-d64d-4d86-912e-84c0f4feeed1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201935002 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2201935002
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.330441750
Short name T224
Test name
Test status
Simulation time 39826661284 ps
CPU time 850.13 seconds
Started Jun 13 01:49:55 PM PDT 24
Finished Jun 13 02:04:07 PM PDT 24
Peak memory 220292 kb
Host smart-93935c13-075c-4e90-92c1-9d713740ff99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330441750 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.330441750
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3114169378
Short name T485
Test name
Test status
Simulation time 123602709 ps
CPU time 1.23 seconds
Started Jun 13 01:52:07 PM PDT 24
Finished Jun 13 01:52:10 PM PDT 24
Peak memory 216648 kb
Host smart-06a36969-4a39-453e-8289-0c5d82d11310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114169378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3114169378
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3617514572
Short name T902
Test name
Test status
Simulation time 83502425 ps
CPU time 1.25 seconds
Started Jun 13 01:52:10 PM PDT 24
Finished Jun 13 01:52:13 PM PDT 24
Peak memory 216736 kb
Host smart-6c74b3b5-810b-4116-ab36-c6dd53eb0d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617514572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3617514572
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3947248543
Short name T317
Test name
Test status
Simulation time 70654633 ps
CPU time 1.08 seconds
Started Jun 13 01:52:20 PM PDT 24
Finished Jun 13 01:52:23 PM PDT 24
Peak memory 216600 kb
Host smart-1cb83f21-bd43-4cfb-8b0b-dbe3e8b22809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947248543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3947248543
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.4086795402
Short name T534
Test name
Test status
Simulation time 120981852 ps
CPU time 1.12 seconds
Started Jun 13 01:52:12 PM PDT 24
Finished Jun 13 01:52:15 PM PDT 24
Peak memory 218556 kb
Host smart-580885db-7d8e-4829-bb68-a8efa25ddcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086795402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.4086795402
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3506683656
Short name T576
Test name
Test status
Simulation time 447303728 ps
CPU time 1.26 seconds
Started Jun 13 01:52:14 PM PDT 24
Finished Jun 13 01:52:17 PM PDT 24
Peak memory 216700 kb
Host smart-745d9c3c-e497-4f3e-8e6c-99de622d139f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506683656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3506683656
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3540661288
Short name T964
Test name
Test status
Simulation time 216328258 ps
CPU time 1.19 seconds
Started Jun 13 01:52:09 PM PDT 24
Finished Jun 13 01:52:12 PM PDT 24
Peak memory 216708 kb
Host smart-5e87933e-7edd-4d19-a707-d7892310f456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540661288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3540661288
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3188688379
Short name T318
Test name
Test status
Simulation time 59367146 ps
CPU time 1.5 seconds
Started Jun 13 01:52:19 PM PDT 24
Finished Jun 13 01:52:22 PM PDT 24
Peak memory 217992 kb
Host smart-fadbe83c-0ad5-41e5-bd78-5822d8b83774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188688379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3188688379
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.94458755
Short name T852
Test name
Test status
Simulation time 45456577 ps
CPU time 1.37 seconds
Started Jun 13 01:52:08 PM PDT 24
Finished Jun 13 01:52:11 PM PDT 24
Peak memory 216696 kb
Host smart-a15aa28e-40cb-479f-9d68-fe42be32818d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94458755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.94458755
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2529666282
Short name T686
Test name
Test status
Simulation time 33850552 ps
CPU time 1.42 seconds
Started Jun 13 01:52:13 PM PDT 24
Finished Jun 13 01:52:17 PM PDT 24
Peak memory 219124 kb
Host smart-0da8f846-3db4-4307-86cd-eaeceecb17f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529666282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2529666282
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2649309089
Short name T539
Test name
Test status
Simulation time 247555492 ps
CPU time 3.21 seconds
Started Jun 13 01:52:09 PM PDT 24
Finished Jun 13 01:52:14 PM PDT 24
Peak memory 216772 kb
Host smart-7b8c088b-6a63-46a8-866c-c1b9e760f792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649309089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2649309089
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.205982172
Short name T296
Test name
Test status
Simulation time 53692977 ps
CPU time 1.29 seconds
Started Jun 13 01:49:53 PM PDT 24
Finished Jun 13 01:49:55 PM PDT 24
Peak memory 215068 kb
Host smart-3e54dda6-2130-48c9-8613-e6d08441bfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205982172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.205982172
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.966746466
Short name T382
Test name
Test status
Simulation time 26228252 ps
CPU time 0.85 seconds
Started Jun 13 01:49:53 PM PDT 24
Finished Jun 13 01:49:56 PM PDT 24
Peak memory 205964 kb
Host smart-01070901-939e-49b5-9b7c-4c1d5f3d67da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966746466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.966746466
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2922638157
Short name T216
Test name
Test status
Simulation time 17977640 ps
CPU time 0.87 seconds
Started Jun 13 01:49:51 PM PDT 24
Finished Jun 13 01:49:52 PM PDT 24
Peak memory 215676 kb
Host smart-0e8177e2-bcef-4b84-9015-00321094d771
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922638157 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2922638157
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3921376215
Short name T201
Test name
Test status
Simulation time 268998628 ps
CPU time 1.05 seconds
Started Jun 13 01:49:53 PM PDT 24
Finished Jun 13 01:49:55 PM PDT 24
Peak memory 217308 kb
Host smart-a549537a-9c75-4baa-ba28-a0b4ee3ece5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921376215 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3921376215
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.536601279
Short name T155
Test name
Test status
Simulation time 41208141 ps
CPU time 1.37 seconds
Started Jun 13 01:49:53 PM PDT 24
Finished Jun 13 01:49:56 PM PDT 24
Peak memory 225176 kb
Host smart-ac014554-9685-42d5-8be6-35d81713b05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536601279 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.536601279
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_intr.3431637081
Short name T508
Test name
Test status
Simulation time 29250640 ps
CPU time 1.01 seconds
Started Jun 13 01:49:55 PM PDT 24
Finished Jun 13 01:49:57 PM PDT 24
Peak memory 214848 kb
Host smart-bbbeba9d-26e8-4a4b-a545-15e679b576df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431637081 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3431637081
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1047683125
Short name T792
Test name
Test status
Simulation time 19037074 ps
CPU time 1.08 seconds
Started Jun 13 01:49:55 PM PDT 24
Finished Jun 13 01:49:57 PM PDT 24
Peak memory 214612 kb
Host smart-f144e1b1-45d1-4914-80ef-ce92e4810492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047683125 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1047683125
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1808741304
Short name T495
Test name
Test status
Simulation time 455889429 ps
CPU time 5 seconds
Started Jun 13 01:49:53 PM PDT 24
Finished Jun 13 01:49:59 PM PDT 24
Peak memory 216528 kb
Host smart-17db5c3f-1d69-4fbe-bd71-9a5a21113e5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808741304 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1808741304
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.355447508
Short name T733
Test name
Test status
Simulation time 31234893961 ps
CPU time 698.96 seconds
Started Jun 13 01:49:54 PM PDT 24
Finished Jun 13 02:01:35 PM PDT 24
Peak memory 220452 kb
Host smart-9fc16e5c-c2df-42fb-b2a3-a1b2aaeaa34a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355447508 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.355447508
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.3085304504
Short name T855
Test name
Test status
Simulation time 40775684 ps
CPU time 1.44 seconds
Started Jun 13 01:52:10 PM PDT 24
Finished Jun 13 01:52:13 PM PDT 24
Peak memory 217828 kb
Host smart-7c77d8f8-f674-4290-81a4-e58217dcf85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085304504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3085304504
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2050919152
Short name T358
Test name
Test status
Simulation time 64970884 ps
CPU time 1.62 seconds
Started Jun 13 01:52:13 PM PDT 24
Finished Jun 13 01:52:17 PM PDT 24
Peak memory 218196 kb
Host smart-0fd9f3ac-6c9e-4d8d-a469-e713d50c1ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050919152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2050919152
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3507992318
Short name T473
Test name
Test status
Simulation time 47336387 ps
CPU time 1.22 seconds
Started Jun 13 01:52:10 PM PDT 24
Finished Jun 13 01:52:13 PM PDT 24
Peak memory 219356 kb
Host smart-de4523c4-ad63-473b-a1ad-dcf461f5de4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507992318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3507992318
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1563372421
Short name T865
Test name
Test status
Simulation time 48904450 ps
CPU time 1.51 seconds
Started Jun 13 01:52:10 PM PDT 24
Finished Jun 13 01:52:13 PM PDT 24
Peak memory 216736 kb
Host smart-5bdda905-2321-4cdf-9dd8-5414f98e7023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563372421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1563372421
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1822034501
Short name T941
Test name
Test status
Simulation time 70562953 ps
CPU time 1.24 seconds
Started Jun 13 01:52:13 PM PDT 24
Finished Jun 13 01:52:16 PM PDT 24
Peak memory 218404 kb
Host smart-cc0c0f4a-ee09-4a73-9a5a-b5bc87a97283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822034501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1822034501
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2571301825
Short name T693
Test name
Test status
Simulation time 96277202 ps
CPU time 1.57 seconds
Started Jun 13 01:52:14 PM PDT 24
Finished Jun 13 01:52:17 PM PDT 24
Peak memory 217904 kb
Host smart-6b4b093c-0f5b-4722-a246-504400214602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571301825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2571301825
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1717404923
Short name T760
Test name
Test status
Simulation time 34996160 ps
CPU time 1.41 seconds
Started Jun 13 01:52:16 PM PDT 24
Finished Jun 13 01:52:18 PM PDT 24
Peak memory 217920 kb
Host smart-1742e88d-cac6-4cf2-8f86-b228ba8e20f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717404923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1717404923
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.584971356
Short name T953
Test name
Test status
Simulation time 33280724 ps
CPU time 1.4 seconds
Started Jun 13 01:52:14 PM PDT 24
Finished Jun 13 01:52:17 PM PDT 24
Peak memory 217764 kb
Host smart-2494fa1e-ad1c-4b60-9974-002439fbeb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584971356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.584971356
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.340512497
Short name T356
Test name
Test status
Simulation time 262293783 ps
CPU time 1.14 seconds
Started Jun 13 01:52:12 PM PDT 24
Finished Jun 13 01:52:15 PM PDT 24
Peak memory 216672 kb
Host smart-7f9572a0-3a7e-4086-8f42-70b35fd3e36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340512497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.340512497
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.874824394
Short name T614
Test name
Test status
Simulation time 97880206 ps
CPU time 1.55 seconds
Started Jun 13 01:52:18 PM PDT 24
Finished Jun 13 01:52:21 PM PDT 24
Peak memory 216532 kb
Host smart-3aeedef1-6066-4a2b-8268-69b6a0a73142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874824394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.874824394
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.4169869311
Short name T99
Test name
Test status
Simulation time 91602093 ps
CPU time 1.3 seconds
Started Jun 13 01:48:56 PM PDT 24
Finished Jun 13 01:49:00 PM PDT 24
Peak memory 215072 kb
Host smart-d003f6bb-89ee-47f4-a306-d2f5a1bd635a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169869311 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.4169869311
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.317559228
Short name T605
Test name
Test status
Simulation time 14393226 ps
CPU time 0.95 seconds
Started Jun 13 01:48:56 PM PDT 24
Finished Jun 13 01:48:59 PM PDT 24
Peak memory 206096 kb
Host smart-fb8847a8-03f2-4a4f-a7f3-68d60568de15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317559228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.317559228
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2573863482
Short name T159
Test name
Test status
Simulation time 20265915 ps
CPU time 0.88 seconds
Started Jun 13 01:48:52 PM PDT 24
Finished Jun 13 01:48:53 PM PDT 24
Peak memory 214796 kb
Host smart-725c7cbf-b1a6-41a3-9d0f-e235cbd5b690
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573863482 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2573863482
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.4068907275
Short name T208
Test name
Test status
Simulation time 79652844 ps
CPU time 1.04 seconds
Started Jun 13 01:48:55 PM PDT 24
Finished Jun 13 01:48:58 PM PDT 24
Peak memory 216252 kb
Host smart-48c74086-3797-43fb-ba9d-431b4b3cc933
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068907275 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.4068907275
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1985220397
Short name T7
Test name
Test status
Simulation time 26856165 ps
CPU time 1.01 seconds
Started Jun 13 01:48:53 PM PDT 24
Finished Jun 13 01:48:56 PM PDT 24
Peak memory 219076 kb
Host smart-07dd9080-16da-4f59-9b98-f13b70c284fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985220397 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1985220397
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1561134269
Short name T481
Test name
Test status
Simulation time 46930786 ps
CPU time 1.38 seconds
Started Jun 13 01:48:56 PM PDT 24
Finished Jun 13 01:49:01 PM PDT 24
Peak memory 218048 kb
Host smart-4db2e2ae-6ae4-4b17-a348-7198a90ecd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561134269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1561134269
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_regwen.2000997436
Short name T840
Test name
Test status
Simulation time 56112982 ps
CPU time 0.95 seconds
Started Jun 13 01:48:55 PM PDT 24
Finished Jun 13 01:48:58 PM PDT 24
Peak memory 206400 kb
Host smart-4e6317d5-fb16-4ef3-81d7-a3deb1739256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000997436 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2000997436
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.115276590
Short name T19
Test name
Test status
Simulation time 478900742 ps
CPU time 4.1 seconds
Started Jun 13 01:48:53 PM PDT 24
Finished Jun 13 01:48:59 PM PDT 24
Peak memory 238528 kb
Host smart-813850bc-5500-4ac3-a01a-c227d5108685
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115276590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.115276590
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.1668705808
Short name T554
Test name
Test status
Simulation time 16606077 ps
CPU time 1.01 seconds
Started Jun 13 01:48:54 PM PDT 24
Finished Jun 13 01:48:56 PM PDT 24
Peak memory 214628 kb
Host smart-2b7f9d07-1435-4c6b-bea4-87bbc4201ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668705808 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1668705808
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.658098850
Short name T200
Test name
Test status
Simulation time 75655824 ps
CPU time 1.37 seconds
Started Jun 13 01:48:55 PM PDT 24
Finished Jun 13 01:48:58 PM PDT 24
Peak memory 216360 kb
Host smart-20999769-0cb8-42a0-a0ad-211365c5512e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658098850 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.658098850
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3630491730
Short name T566
Test name
Test status
Simulation time 142129326997 ps
CPU time 929.28 seconds
Started Jun 13 01:48:56 PM PDT 24
Finished Jun 13 02:04:29 PM PDT 24
Peak memory 222452 kb
Host smart-f58508b8-0546-4cc5-b071-4ca56d7a410c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630491730 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3630491730
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3600507935
Short name T195
Test name
Test status
Simulation time 63951517 ps
CPU time 1.16 seconds
Started Jun 13 01:49:56 PM PDT 24
Finished Jun 13 01:50:00 PM PDT 24
Peak memory 219200 kb
Host smart-5785886f-1e41-4ae8-8f54-1bfb1c182c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600507935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3600507935
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3074208421
Short name T755
Test name
Test status
Simulation time 23242365 ps
CPU time 0.9 seconds
Started Jun 13 01:49:56 PM PDT 24
Finished Jun 13 01:49:59 PM PDT 24
Peak memory 206080 kb
Host smart-47b8390b-c1ea-4b8d-b98c-8da6c7d10b68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074208421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3074208421
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3365731951
Short name T625
Test name
Test status
Simulation time 112689011 ps
CPU time 0.83 seconds
Started Jun 13 01:50:02 PM PDT 24
Finished Jun 13 01:50:04 PM PDT 24
Peak memory 215320 kb
Host smart-c36787df-31cd-41d2-afbb-244167b92cdf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365731951 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3365731951
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2515047498
Short name T888
Test name
Test status
Simulation time 127674625 ps
CPU time 1.14 seconds
Started Jun 13 01:49:58 PM PDT 24
Finished Jun 13 01:50:01 PM PDT 24
Peak memory 219116 kb
Host smart-3017d533-126b-4d71-97ed-75103f0dd8ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515047498 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2515047498
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_genbits.1990719223
Short name T315
Test name
Test status
Simulation time 139641304 ps
CPU time 1.57 seconds
Started Jun 13 01:49:54 PM PDT 24
Finished Jun 13 01:49:57 PM PDT 24
Peak memory 219532 kb
Host smart-3d167be5-8e7c-45ef-a986-b2a523f49854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990719223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1990719223
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.399535802
Short name T446
Test name
Test status
Simulation time 44496853 ps
CPU time 0.98 seconds
Started Jun 13 01:49:54 PM PDT 24
Finished Jun 13 01:49:56 PM PDT 24
Peak memory 214736 kb
Host smart-5e8ea89f-0cee-4124-bf7b-4ab7c7a79db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399535802 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.399535802
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2960526441
Short name T593
Test name
Test status
Simulation time 123774007 ps
CPU time 0.9 seconds
Started Jun 13 01:49:52 PM PDT 24
Finished Jun 13 01:49:54 PM PDT 24
Peak memory 214536 kb
Host smart-18370b3a-5673-4ea3-8663-32c49b747515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960526441 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2960526441
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2378117477
Short name T692
Test name
Test status
Simulation time 230099449 ps
CPU time 4.87 seconds
Started Jun 13 01:49:54 PM PDT 24
Finished Jun 13 01:50:01 PM PDT 24
Peak memory 214620 kb
Host smart-a6d902ee-c2ff-460f-bf04-b429f00bbac4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378117477 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2378117477
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2959182727
Short name T899
Test name
Test status
Simulation time 90459368883 ps
CPU time 1015.59 seconds
Started Jun 13 01:49:54 PM PDT 24
Finished Jun 13 02:06:52 PM PDT 24
Peak memory 220388 kb
Host smart-5c63434c-ad6b-4682-b827-4a3ae262f8f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959182727 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2959182727
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.353354938
Short name T945
Test name
Test status
Simulation time 92158072 ps
CPU time 1.16 seconds
Started Jun 13 01:49:56 PM PDT 24
Finished Jun 13 01:49:59 PM PDT 24
Peak memory 215072 kb
Host smart-02bec272-440f-46d7-95c4-85305f57fa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353354938 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.353354938
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.63177460
Short name T478
Test name
Test status
Simulation time 15060077 ps
CPU time 0.92 seconds
Started Jun 13 01:49:59 PM PDT 24
Finished Jun 13 01:50:01 PM PDT 24
Peak memory 214308 kb
Host smart-66fb7836-a22f-4a7b-b1fb-e57363cf5c80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63177460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.63177460
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.52167616
Short name T695
Test name
Test status
Simulation time 237410445 ps
CPU time 1.13 seconds
Started Jun 13 01:49:58 PM PDT 24
Finished Jun 13 01:50:00 PM PDT 24
Peak memory 216248 kb
Host smart-e8b335d1-33f2-4de0-afd9-97932496d558
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52167616 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_dis
able_auto_req_mode.52167616
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.4161632109
Short name T562
Test name
Test status
Simulation time 18479528 ps
CPU time 1.13 seconds
Started Jun 13 01:49:58 PM PDT 24
Finished Jun 13 01:50:01 PM PDT 24
Peak memory 232084 kb
Host smart-b8cebc7f-0cf3-4e71-9012-71fe0ee5a51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161632109 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.4161632109
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.13450823
Short name T794
Test name
Test status
Simulation time 53417599 ps
CPU time 1.21 seconds
Started Jun 13 01:49:59 PM PDT 24
Finished Jun 13 01:50:02 PM PDT 24
Peak memory 217964 kb
Host smart-5f1873d6-70a5-46a0-9cd7-b41beb9aa54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13450823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.13450823
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2033076131
Short name T105
Test name
Test status
Simulation time 34380140 ps
CPU time 0.87 seconds
Started Jun 13 01:49:58 PM PDT 24
Finished Jun 13 01:50:01 PM PDT 24
Peak memory 214976 kb
Host smart-ffe610ef-b863-44e2-8d4e-567961a4e8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033076131 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2033076131
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1169553563
Short name T727
Test name
Test status
Simulation time 24845651 ps
CPU time 0.91 seconds
Started Jun 13 01:49:59 PM PDT 24
Finished Jun 13 01:50:01 PM PDT 24
Peak memory 214632 kb
Host smart-55746db3-20fd-4016-8729-35af0f728e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169553563 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1169553563
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.4288218754
Short name T6
Test name
Test status
Simulation time 473369366 ps
CPU time 5 seconds
Started Jun 13 01:50:03 PM PDT 24
Finished Jun 13 01:50:11 PM PDT 24
Peak memory 214616 kb
Host smart-4ddff53d-4140-472f-97bb-9a0bf4aa1a59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288218754 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.4288218754
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2687755769
Short name T227
Test name
Test status
Simulation time 42793929650 ps
CPU time 801.66 seconds
Started Jun 13 01:49:57 PM PDT 24
Finished Jun 13 02:03:20 PM PDT 24
Peak memory 218188 kb
Host smart-0e14ebf9-43a8-4233-822a-9ff457e1f08e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687755769 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2687755769
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1902228643
Short name T676
Test name
Test status
Simulation time 145224116 ps
CPU time 1.29 seconds
Started Jun 13 01:49:57 PM PDT 24
Finished Jun 13 01:50:00 PM PDT 24
Peak memory 219076 kb
Host smart-6fd2cafb-747d-488b-a97d-8652dd9a9fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902228643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1902228643
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1331492394
Short name T337
Test name
Test status
Simulation time 14201592 ps
CPU time 0.91 seconds
Started Jun 13 01:49:59 PM PDT 24
Finished Jun 13 01:50:01 PM PDT 24
Peak memory 206080 kb
Host smart-e3c9a3b4-4e28-45b7-b504-b92d624b8619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331492394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1331492394
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2945505619
Short name T771
Test name
Test status
Simulation time 20693059 ps
CPU time 0.89 seconds
Started Jun 13 01:50:00 PM PDT 24
Finished Jun 13 01:50:04 PM PDT 24
Peak memory 214828 kb
Host smart-2e583707-6c80-4810-a045-23bd75c46f5b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945505619 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2945505619
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3987619894
Short name T636
Test name
Test status
Simulation time 69483672 ps
CPU time 1.21 seconds
Started Jun 13 01:49:57 PM PDT 24
Finished Jun 13 01:50:00 PM PDT 24
Peak memory 218684 kb
Host smart-87110696-6be2-4186-9819-bf9b4b593f68
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987619894 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3987619894
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2630912136
Short name T140
Test name
Test status
Simulation time 45553445 ps
CPU time 1.1 seconds
Started Jun 13 01:49:54 PM PDT 24
Finished Jun 13 01:49:57 PM PDT 24
Peak memory 229044 kb
Host smart-cc1106d1-0812-4966-be01-ff3610d2e560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630912136 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2630912136
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1794548212
Short name T825
Test name
Test status
Simulation time 44021555 ps
CPU time 1.46 seconds
Started Jun 13 01:49:55 PM PDT 24
Finished Jun 13 01:49:59 PM PDT 24
Peak memory 217888 kb
Host smart-52f964a0-c79c-4250-a1d8-eef4be4af853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794548212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1794548212
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2145469947
Short name T960
Test name
Test status
Simulation time 40666081 ps
CPU time 0.9 seconds
Started Jun 13 01:49:56 PM PDT 24
Finished Jun 13 01:49:59 PM PDT 24
Peak memory 214820 kb
Host smart-b42b5294-2f35-45ae-9879-ce63ab611392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145469947 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2145469947
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1214534082
Short name T430
Test name
Test status
Simulation time 14162867 ps
CPU time 0.95 seconds
Started Jun 13 01:49:58 PM PDT 24
Finished Jun 13 01:50:01 PM PDT 24
Peak memory 214560 kb
Host smart-7f6984ac-815c-4395-8996-a22a944b6665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214534082 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1214534082
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3764302927
Short name T497
Test name
Test status
Simulation time 356755945 ps
CPU time 4.37 seconds
Started Jun 13 01:49:57 PM PDT 24
Finished Jun 13 01:50:04 PM PDT 24
Peak memory 216384 kb
Host smart-d5f1d18f-474a-4ded-94d0-a2a3764e65c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764302927 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3764302927
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3724981916
Short name T639
Test name
Test status
Simulation time 57893795317 ps
CPU time 1436.01 seconds
Started Jun 13 01:49:56 PM PDT 24
Finished Jun 13 02:13:55 PM PDT 24
Peak memory 223728 kb
Host smart-4a60fb8c-ae23-4996-bf63-544def2d311c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724981916 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3724981916
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.719712504
Short name T640
Test name
Test status
Simulation time 44780058 ps
CPU time 1.13 seconds
Started Jun 13 01:50:07 PM PDT 24
Finished Jun 13 01:50:10 PM PDT 24
Peak memory 215068 kb
Host smart-b68050d1-5fa9-4d34-b6f0-c2ebee601174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719712504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.719712504
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.109350017
Short name T582
Test name
Test status
Simulation time 14945421 ps
CPU time 0.9 seconds
Started Jun 13 01:50:04 PM PDT 24
Finished Jun 13 01:50:07 PM PDT 24
Peak memory 206092 kb
Host smart-c6e8f199-4750-4efd-a1a3-1af9f3c8a65b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109350017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.109350017
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2026761579
Short name T190
Test name
Test status
Simulation time 32020343 ps
CPU time 0.87 seconds
Started Jun 13 01:50:08 PM PDT 24
Finished Jun 13 01:50:12 PM PDT 24
Peak memory 215676 kb
Host smart-1f6e1d72-7dfa-4c45-be9e-b959e99f974f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026761579 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2026761579
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3070295891
Short name T456
Test name
Test status
Simulation time 62457945 ps
CPU time 1.15 seconds
Started Jun 13 01:50:04 PM PDT 24
Finished Jun 13 01:50:07 PM PDT 24
Peak memory 216288 kb
Host smart-b532a00e-9c63-4af3-96e2-5ee8358a4ba2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070295891 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3070295891
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3155724647
Short name T857
Test name
Test status
Simulation time 22049690 ps
CPU time 1.2 seconds
Started Jun 13 01:50:03 PM PDT 24
Finished Jun 13 01:50:07 PM PDT 24
Peak memory 219200 kb
Host smart-a3ed0f44-13cb-4300-a39e-ed6b820a55c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155724647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3155724647
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1212547248
Short name T701
Test name
Test status
Simulation time 48475831 ps
CPU time 1.19 seconds
Started Jun 13 01:50:07 PM PDT 24
Finished Jun 13 01:50:11 PM PDT 24
Peak memory 218000 kb
Host smart-032066f5-74fb-4b29-a273-bf547e2e82e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212547248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1212547248
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.333728045
Short name T55
Test name
Test status
Simulation time 48469483 ps
CPU time 0.96 seconds
Started Jun 13 01:50:08 PM PDT 24
Finished Jun 13 01:50:12 PM PDT 24
Peak memory 223200 kb
Host smart-4b53b445-9270-49f0-ab5b-17bd4cbb3bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333728045 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.333728045
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2279925606
Short name T426
Test name
Test status
Simulation time 24329076 ps
CPU time 0.95 seconds
Started Jun 13 01:50:01 PM PDT 24
Finished Jun 13 01:50:05 PM PDT 24
Peak memory 214572 kb
Host smart-9555c52f-504a-416d-a7ff-7d412ab7edf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279925606 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2279925606
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1519105404
Short name T378
Test name
Test status
Simulation time 101686328 ps
CPU time 1.16 seconds
Started Jun 13 01:50:04 PM PDT 24
Finished Jun 13 01:50:07 PM PDT 24
Peak memory 206224 kb
Host smart-28b96262-5e5f-4b7c-b807-6d467f763da9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519105404 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1519105404
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_alert.3602566668
Short name T297
Test name
Test status
Simulation time 31087347 ps
CPU time 1.28 seconds
Started Jun 13 01:50:05 PM PDT 24
Finished Jun 13 01:50:09 PM PDT 24
Peak memory 219300 kb
Host smart-75400a5d-7df2-4134-8b88-e00b43d4b3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602566668 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3602566668
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2704592162
Short name T404
Test name
Test status
Simulation time 22250517 ps
CPU time 1.08 seconds
Started Jun 13 01:50:01 PM PDT 24
Finished Jun 13 01:50:04 PM PDT 24
Peak memory 214364 kb
Host smart-f93a23e7-f720-44f7-bf4f-583bbf57df38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704592162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2704592162
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.431512067
Short name T169
Test name
Test status
Simulation time 36065863 ps
CPU time 0.93 seconds
Started Jun 13 01:50:02 PM PDT 24
Finished Jun 13 01:50:06 PM PDT 24
Peak memory 215688 kb
Host smart-1d001d38-9df1-46c0-8571-9c3c11bc695a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431512067 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.431512067
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2940977341
Short name T622
Test name
Test status
Simulation time 52235051 ps
CPU time 1.21 seconds
Started Jun 13 01:50:03 PM PDT 24
Finished Jun 13 01:50:07 PM PDT 24
Peak memory 216412 kb
Host smart-afeda3f3-2850-430f-b051-baa710f2149f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940977341 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2940977341
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2985858877
Short name T117
Test name
Test status
Simulation time 59613925 ps
CPU time 1.21 seconds
Started Jun 13 01:50:02 PM PDT 24
Finished Jun 13 01:50:05 PM PDT 24
Peak memory 229020 kb
Host smart-78ac144a-fee2-46ee-96c5-50218e512362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985858877 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2985858877
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.302813391
Short name T959
Test name
Test status
Simulation time 132028085 ps
CPU time 1.81 seconds
Started Jun 13 01:50:02 PM PDT 24
Finished Jun 13 01:50:06 PM PDT 24
Peak memory 218064 kb
Host smart-04a5d156-1880-4236-9bad-3bba42075e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302813391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.302813391
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2181705732
Short name T37
Test name
Test status
Simulation time 20204913 ps
CPU time 1.07 seconds
Started Jun 13 01:50:04 PM PDT 24
Finished Jun 13 01:50:08 PM PDT 24
Peak memory 215180 kb
Host smart-f95f83bf-6692-4c85-be97-9b0a69480086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181705732 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2181705732
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1697220949
Short name T461
Test name
Test status
Simulation time 51853353 ps
CPU time 1.02 seconds
Started Jun 13 01:50:07 PM PDT 24
Finished Jun 13 01:50:10 PM PDT 24
Peak memory 214632 kb
Host smart-aa969d51-ac22-4998-a472-265e1aee7f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697220949 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1697220949
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3847367615
Short name T302
Test name
Test status
Simulation time 382376579 ps
CPU time 7.46 seconds
Started Jun 13 01:50:02 PM PDT 24
Finished Jun 13 01:50:11 PM PDT 24
Peak memory 219648 kb
Host smart-64a2e8de-2f70-4b5f-a982-95777b082699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847367615 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3847367615
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2975822967
Short name T70
Test name
Test status
Simulation time 184487424472 ps
CPU time 1080.95 seconds
Started Jun 13 01:50:04 PM PDT 24
Finished Jun 13 02:08:08 PM PDT 24
Peak memory 223480 kb
Host smart-38ec2323-58b4-4b15-9ce8-0c8ec98f8e38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975822967 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2975822967
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.332695444
Short name T243
Test name
Test status
Simulation time 104349357 ps
CPU time 1.3 seconds
Started Jun 13 01:50:05 PM PDT 24
Finished Jun 13 01:50:09 PM PDT 24
Peak memory 215064 kb
Host smart-8353eef6-5fa1-4902-9562-4b9f3366af22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332695444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.332695444
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3844955396
Short name T752
Test name
Test status
Simulation time 12917764 ps
CPU time 0.89 seconds
Started Jun 13 01:50:10 PM PDT 24
Finished Jun 13 01:50:14 PM PDT 24
Peak memory 214300 kb
Host smart-85ba824d-9b12-4c0e-a93a-0ab42aba2944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844955396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3844955396
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2144491296
Short name T886
Test name
Test status
Simulation time 57109290 ps
CPU time 0.84 seconds
Started Jun 13 01:50:01 PM PDT 24
Finished Jun 13 01:50:04 PM PDT 24
Peak memory 215808 kb
Host smart-4e6efab8-4213-424a-979d-43a0c158145d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144491296 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2144491296
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_err.1342975812
Short name T630
Test name
Test status
Simulation time 18565346 ps
CPU time 1.08 seconds
Started Jun 13 01:50:04 PM PDT 24
Finished Jun 13 01:50:08 PM PDT 24
Peak memory 218132 kb
Host smart-19386f63-be86-41f6-a6f4-5437d8675267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342975812 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1342975812
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3538253599
Short name T665
Test name
Test status
Simulation time 332416154 ps
CPU time 1.85 seconds
Started Jun 13 01:50:03 PM PDT 24
Finished Jun 13 01:50:07 PM PDT 24
Peak memory 218472 kb
Host smart-f3d91d23-98dc-4c70-8644-db095348d587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538253599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3538253599
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1082171999
Short name T53
Test name
Test status
Simulation time 34642143 ps
CPU time 1.02 seconds
Started Jun 13 01:50:00 PM PDT 24
Finished Jun 13 01:50:03 PM PDT 24
Peak memory 223388 kb
Host smart-369718b4-1b8c-46d5-b41c-d034f7c80ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082171999 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1082171999
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.590814241
Short name T269
Test name
Test status
Simulation time 31557083 ps
CPU time 0.91 seconds
Started Jun 13 01:49:59 PM PDT 24
Finished Jun 13 01:50:01 PM PDT 24
Peak memory 214612 kb
Host smart-12794147-1ef4-4cb9-b311-e7acc75d2bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590814241 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.590814241
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.992703002
Short name T946
Test name
Test status
Simulation time 846227704 ps
CPU time 4.69 seconds
Started Jun 13 01:50:05 PM PDT 24
Finished Jun 13 01:50:13 PM PDT 24
Peak memory 216664 kb
Host smart-627849ba-8195-4853-aaec-281fef92f864
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992703002 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.992703002
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.914013599
Short name T40
Test name
Test status
Simulation time 16434317381 ps
CPU time 197.7 seconds
Started Jun 13 01:50:02 PM PDT 24
Finished Jun 13 01:53:22 PM PDT 24
Peak memory 221840 kb
Host smart-6e020aba-8b40-48a7-9ece-be3ac2ab8906
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914013599 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.914013599
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3951609911
Short name T182
Test name
Test status
Simulation time 22253338 ps
CPU time 1.1 seconds
Started Jun 13 01:50:10 PM PDT 24
Finished Jun 13 01:50:15 PM PDT 24
Peak memory 217812 kb
Host smart-3591e5cd-c752-4fd8-b618-8903a8776774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951609911 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3951609911
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3034284199
Short name T858
Test name
Test status
Simulation time 44010782 ps
CPU time 0.98 seconds
Started Jun 13 01:50:09 PM PDT 24
Finished Jun 13 01:50:13 PM PDT 24
Peak memory 206084 kb
Host smart-d78b442e-f955-48b3-aca8-9439fa622646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034284199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3034284199
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1049439018
Short name T170
Test name
Test status
Simulation time 14303257 ps
CPU time 0.93 seconds
Started Jun 13 01:50:12 PM PDT 24
Finished Jun 13 01:50:16 PM PDT 24
Peak memory 215816 kb
Host smart-aacaa638-391b-4596-9ff7-f33d38d381eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049439018 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1049439018
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.797239154
Short name T215
Test name
Test status
Simulation time 191885204 ps
CPU time 1.24 seconds
Started Jun 13 01:50:10 PM PDT 24
Finished Jun 13 01:50:14 PM PDT 24
Peak memory 216308 kb
Host smart-88ae5cfa-e15b-4788-92e0-61d5cc3a1eb4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797239154 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.797239154
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_genbits.182623043
Short name T341
Test name
Test status
Simulation time 41391292 ps
CPU time 1.65 seconds
Started Jun 13 01:50:10 PM PDT 24
Finished Jun 13 01:50:15 PM PDT 24
Peak memory 217796 kb
Host smart-8b07fd56-8d3d-46e7-9a64-dd54efca4181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182623043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.182623043
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3208504478
Short name T919
Test name
Test status
Simulation time 22341720 ps
CPU time 1 seconds
Started Jun 13 01:50:12 PM PDT 24
Finished Jun 13 01:50:16 PM PDT 24
Peak memory 215112 kb
Host smart-160e0ea4-bf49-4b16-972c-035b0f450ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208504478 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3208504478
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3657648483
Short name T609
Test name
Test status
Simulation time 25976628 ps
CPU time 0.92 seconds
Started Jun 13 01:50:09 PM PDT 24
Finished Jun 13 01:50:13 PM PDT 24
Peak memory 214604 kb
Host smart-3a5ddd6f-2b85-46b0-b37e-f10a1ed135a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657648483 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3657648483
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.294485336
Short name T411
Test name
Test status
Simulation time 1199617666 ps
CPU time 3.46 seconds
Started Jun 13 01:50:09 PM PDT 24
Finished Jun 13 01:50:16 PM PDT 24
Peak memory 216508 kb
Host smart-329ee46f-eb97-47f5-a76b-e4cef7244677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294485336 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.294485336
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.4044421575
Short name T69
Test name
Test status
Simulation time 37296670794 ps
CPU time 477.31 seconds
Started Jun 13 01:50:10 PM PDT 24
Finished Jun 13 01:58:11 PM PDT 24
Peak memory 222868 kb
Host smart-e3acd4ce-c4f5-4dd1-b5d4-41b88edb82fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044421575 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.4044421575
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1285621897
Short name T48
Test name
Test status
Simulation time 70105169 ps
CPU time 1.09 seconds
Started Jun 13 01:50:12 PM PDT 24
Finished Jun 13 01:50:16 PM PDT 24
Peak memory 217988 kb
Host smart-fd054ec0-447a-477a-b49c-d1af85df7f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285621897 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1285621897
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.39589954
Short name T242
Test name
Test status
Simulation time 127176504 ps
CPU time 0.96 seconds
Started Jun 13 01:50:12 PM PDT 24
Finished Jun 13 01:50:16 PM PDT 24
Peak memory 205764 kb
Host smart-8ec9208b-ece1-4e70-b37c-727ea08079bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39589954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.39589954
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3343610871
Short name T210
Test name
Test status
Simulation time 38948319 ps
CPU time 0.9 seconds
Started Jun 13 01:50:12 PM PDT 24
Finished Jun 13 01:50:16 PM PDT 24
Peak memory 215284 kb
Host smart-07ef1f4f-2281-47b2-b1c3-8699f6abe56e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343610871 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3343610871
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3081165203
Short name T642
Test name
Test status
Simulation time 85782358 ps
CPU time 1.16 seconds
Started Jun 13 01:50:10 PM PDT 24
Finished Jun 13 01:50:14 PM PDT 24
Peak memory 216396 kb
Host smart-c0031bad-3127-424b-a69e-9a8e4e993043
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081165203 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3081165203
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2537359566
Short name T8
Test name
Test status
Simulation time 34032478 ps
CPU time 0.99 seconds
Started Jun 13 01:50:10 PM PDT 24
Finished Jun 13 01:50:14 PM PDT 24
Peak memory 217780 kb
Host smart-5efa938f-acee-4a72-9a62-5a5f5dc58d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537359566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2537359566
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.670006495
Short name T416
Test name
Test status
Simulation time 77361265 ps
CPU time 1.17 seconds
Started Jun 13 01:50:10 PM PDT 24
Finished Jun 13 01:50:15 PM PDT 24
Peak memory 216872 kb
Host smart-b737df8e-f06a-4064-8c6a-cb9e5ca3bfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670006495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.670006495
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.314998587
Short name T782
Test name
Test status
Simulation time 51225707 ps
CPU time 0.97 seconds
Started Jun 13 01:50:09 PM PDT 24
Finished Jun 13 01:50:13 PM PDT 24
Peak memory 223200 kb
Host smart-064ba57a-8b67-498a-8318-c8b71de6c53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314998587 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.314998587
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.268966656
Short name T667
Test name
Test status
Simulation time 47935207 ps
CPU time 0.91 seconds
Started Jun 13 01:50:12 PM PDT 24
Finished Jun 13 01:50:16 PM PDT 24
Peak memory 214608 kb
Host smart-800e7968-36f8-4ed9-820a-ef2d1bfe7920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268966656 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.268966656
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.810168422
Short name T238
Test name
Test status
Simulation time 202622633 ps
CPU time 4.31 seconds
Started Jun 13 01:50:08 PM PDT 24
Finished Jun 13 01:50:15 PM PDT 24
Peak memory 216320 kb
Host smart-d5080288-1984-4dbe-8501-a7c7c37c7583
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810168422 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.810168422
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2095742394
Short name T648
Test name
Test status
Simulation time 19073858451 ps
CPU time 439.77 seconds
Started Jun 13 01:50:10 PM PDT 24
Finished Jun 13 01:57:32 PM PDT 24
Peak memory 222880 kb
Host smart-3e393209-1266-409c-bf9f-9aa348c8b701
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095742394 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2095742394
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1765505919
Short name T298
Test name
Test status
Simulation time 50354318 ps
CPU time 1.25 seconds
Started Jun 13 01:50:10 PM PDT 24
Finished Jun 13 01:50:15 PM PDT 24
Peak memory 220536 kb
Host smart-7917979a-4ebb-4d14-9133-120a53acd9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765505919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1765505919
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1038874271
Short name T476
Test name
Test status
Simulation time 66698272 ps
CPU time 0.94 seconds
Started Jun 13 01:50:11 PM PDT 24
Finished Jun 13 01:50:15 PM PDT 24
Peak memory 214308 kb
Host smart-230e6407-d6c0-4264-83d7-82eeb3607a6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038874271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1038874271
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.168208761
Short name T895
Test name
Test status
Simulation time 12094563 ps
CPU time 0.92 seconds
Started Jun 13 01:50:11 PM PDT 24
Finished Jun 13 01:50:15 PM PDT 24
Peak memory 215940 kb
Host smart-32daa07a-1af1-44dc-b825-360f44989f73
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168208761 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.168208761
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3556116177
Short name T949
Test name
Test status
Simulation time 107590486 ps
CPU time 1.23 seconds
Started Jun 13 01:50:12 PM PDT 24
Finished Jun 13 01:50:16 PM PDT 24
Peak memory 216296 kb
Host smart-ff0f8895-0c18-4e6e-991e-ce3055952ec0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556116177 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3556116177
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3362703470
Short name T893
Test name
Test status
Simulation time 56155668 ps
CPU time 1.17 seconds
Started Jun 13 01:50:12 PM PDT 24
Finished Jun 13 01:50:16 PM PDT 24
Peak memory 229044 kb
Host smart-f35232bd-0740-4bfb-a337-4221186f68ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362703470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3362703470
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.563410194
Short name T56
Test name
Test status
Simulation time 63495191 ps
CPU time 1.36 seconds
Started Jun 13 01:50:11 PM PDT 24
Finished Jun 13 01:50:15 PM PDT 24
Peak memory 218064 kb
Host smart-ea6ac324-b528-4fd7-afe8-4fa74b486c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563410194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.563410194
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1258009405
Short name T749
Test name
Test status
Simulation time 22794768 ps
CPU time 1.25 seconds
Started Jun 13 01:50:09 PM PDT 24
Finished Jun 13 01:50:14 PM PDT 24
Peak memory 223348 kb
Host smart-ac3a1698-6e10-42e2-b506-c315b687e8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258009405 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1258009405
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1555492503
Short name T588
Test name
Test status
Simulation time 29601708 ps
CPU time 0.89 seconds
Started Jun 13 01:50:09 PM PDT 24
Finished Jun 13 01:50:12 PM PDT 24
Peak memory 214620 kb
Host smart-2bfcd333-3c5f-464e-a80f-e26f3fc4ff92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555492503 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1555492503
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.4163568171
Short name T867
Test name
Test status
Simulation time 113334321 ps
CPU time 1.62 seconds
Started Jun 13 01:50:12 PM PDT 24
Finished Jun 13 01:50:17 PM PDT 24
Peak memory 214544 kb
Host smart-921f6e5a-6a56-4519-bbc7-d7e91d48bab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163568171 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.4163568171
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2717311611
Short name T475
Test name
Test status
Simulation time 29163191273 ps
CPU time 707.86 seconds
Started Jun 13 01:50:09 PM PDT 24
Finished Jun 13 02:02:00 PM PDT 24
Peak memory 217068 kb
Host smart-284fadc1-d4a9-46a9-9bdc-c4668eb09e28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717311611 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2717311611
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3319945864
Short name T3
Test name
Test status
Simulation time 28642747 ps
CPU time 1.22 seconds
Started Jun 13 01:50:14 PM PDT 24
Finished Jun 13 01:50:18 PM PDT 24
Peak memory 220104 kb
Host smart-9073f768-7b22-433a-a69d-ac11d5474a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319945864 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3319945864
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3841711066
Short name T72
Test name
Test status
Simulation time 80801800 ps
CPU time 0.84 seconds
Started Jun 13 01:50:15 PM PDT 24
Finished Jun 13 01:50:18 PM PDT 24
Peak memory 214160 kb
Host smart-d0bbc42e-c7c3-48f9-8d83-e5f68c59b5b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841711066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3841711066
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.4010295465
Short name T221
Test name
Test status
Simulation time 35524035 ps
CPU time 0.89 seconds
Started Jun 13 01:50:26 PM PDT 24
Finished Jun 13 01:50:28 PM PDT 24
Peak memory 214992 kb
Host smart-830d228c-5a05-445a-aea7-3514e8d4db13
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010295465 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.4010295465
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.55472350
Short name T113
Test name
Test status
Simulation time 41010933 ps
CPU time 1.46 seconds
Started Jun 13 01:50:25 PM PDT 24
Finished Jun 13 01:50:27 PM PDT 24
Peak memory 216524 kb
Host smart-ff7924ab-8d46-4f31-b372-a3c65a84d615
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55472350 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_dis
able_auto_req_mode.55472350
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3662489930
Short name T168
Test name
Test status
Simulation time 28705888 ps
CPU time 0.89 seconds
Started Jun 13 01:50:15 PM PDT 24
Finished Jun 13 01:50:18 PM PDT 24
Peak memory 217580 kb
Host smart-538fc628-99e1-463e-a658-248dbe8e7ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662489930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3662489930
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.4098504728
Short name T373
Test name
Test status
Simulation time 36952956 ps
CPU time 1.43 seconds
Started Jun 13 01:50:13 PM PDT 24
Finished Jun 13 01:50:17 PM PDT 24
Peak memory 218016 kb
Host smart-4c925e61-6f0d-46c9-bc22-09a47a442c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098504728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.4098504728
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2456602357
Short name T772
Test name
Test status
Simulation time 52932115 ps
CPU time 0.83 seconds
Started Jun 13 01:50:12 PM PDT 24
Finished Jun 13 01:50:16 PM PDT 24
Peak memory 214588 kb
Host smart-56e370ef-d6bf-45e6-a836-3192abda4c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456602357 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2456602357
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.427195581
Short name T491
Test name
Test status
Simulation time 58463632 ps
CPU time 0.93 seconds
Started Jun 13 01:50:12 PM PDT 24
Finished Jun 13 01:50:16 PM PDT 24
Peak memory 214616 kb
Host smart-b9276ba1-e024-4843-8296-1ac1b2bb357c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427195581 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.427195581
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2886896256
Short name T199
Test name
Test status
Simulation time 2125053434 ps
CPU time 3.74 seconds
Started Jun 13 01:50:11 PM PDT 24
Finished Jun 13 01:50:17 PM PDT 24
Peak memory 216512 kb
Host smart-abe67d84-499d-4763-8ce5-562a14f12713
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886896256 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2886896256
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3123426375
Short name T645
Test name
Test status
Simulation time 188408477154 ps
CPU time 1415.69 seconds
Started Jun 13 01:50:10 PM PDT 24
Finished Jun 13 02:13:49 PM PDT 24
Peak memory 224360 kb
Host smart-4a19951c-1ae7-443c-ba70-9c493a3e3451
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123426375 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3123426375
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2766049893
Short name T820
Test name
Test status
Simulation time 30748148 ps
CPU time 1.36 seconds
Started Jun 13 01:48:59 PM PDT 24
Finished Jun 13 01:49:02 PM PDT 24
Peak memory 220108 kb
Host smart-62f33993-dedf-4073-86a2-3cbad773c766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766049893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2766049893
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1324655940
Short name T952
Test name
Test status
Simulation time 34252448 ps
CPU time 0.98 seconds
Started Jun 13 01:49:00 PM PDT 24
Finished Jun 13 01:49:04 PM PDT 24
Peak memory 206084 kb
Host smart-ee0594d2-7a10-4df9-ba1c-f5d06458a7d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324655940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1324655940
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1394365316
Short name T698
Test name
Test status
Simulation time 16697595 ps
CPU time 0.87 seconds
Started Jun 13 01:49:02 PM PDT 24
Finished Jun 13 01:49:04 PM PDT 24
Peak memory 215312 kb
Host smart-5b84e8bd-bede-46d3-b0e0-8f4dad1bc964
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394365316 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1394365316
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2014408716
Short name T956
Test name
Test status
Simulation time 37108160 ps
CPU time 1.27 seconds
Started Jun 13 01:48:58 PM PDT 24
Finished Jun 13 01:49:01 PM PDT 24
Peak memory 216292 kb
Host smart-71e4b7c3-1fbb-4333-8626-a636c134db06
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014408716 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2014408716
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2209051905
Short name T672
Test name
Test status
Simulation time 24550743 ps
CPU time 1.29 seconds
Started Jun 13 01:49:01 PM PDT 24
Finished Jun 13 01:49:04 PM PDT 24
Peak memory 219432 kb
Host smart-fcaa7c8f-a4f4-4c07-ad1d-0230bc175d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209051905 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2209051905
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3272740412
Short name T439
Test name
Test status
Simulation time 41066904 ps
CPU time 1.68 seconds
Started Jun 13 01:48:57 PM PDT 24
Finished Jun 13 01:49:01 PM PDT 24
Peak memory 216692 kb
Host smart-8b711c8f-539e-4575-932a-1e95124f8058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272740412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3272740412
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2568047384
Short name T54
Test name
Test status
Simulation time 27131381 ps
CPU time 1.06 seconds
Started Jun 13 01:49:04 PM PDT 24
Finished Jun 13 01:49:06 PM PDT 24
Peak memory 223352 kb
Host smart-7de4e973-78b8-4e4c-944c-d1a3808f7bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568047384 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2568047384
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.3294189319
Short name T299
Test name
Test status
Simulation time 20756136 ps
CPU time 1.03 seconds
Started Jun 13 01:48:52 PM PDT 24
Finished Jun 13 01:48:54 PM PDT 24
Peak memory 206408 kb
Host smart-5f8e61c3-89cc-47cd-a668-f84d2bd137b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294189319 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3294189319
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1636292
Short name T58
Test name
Test status
Simulation time 307824219 ps
CPU time 4.21 seconds
Started Jun 13 01:49:01 PM PDT 24
Finished Jun 13 01:49:07 PM PDT 24
Peak memory 234840 kb
Host smart-a5cb5571-1f49-432e-be49-616d67ae05ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1636292
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3252528338
Short name T381
Test name
Test status
Simulation time 28530458 ps
CPU time 1.02 seconds
Started Jun 13 01:48:55 PM PDT 24
Finished Jun 13 01:48:58 PM PDT 24
Peak memory 214612 kb
Host smart-6512ee79-7143-47f7-9ab9-a65b3da0f76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252528338 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3252528338
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2134078398
Short name T628
Test name
Test status
Simulation time 119715300 ps
CPU time 2.74 seconds
Started Jun 13 01:49:01 PM PDT 24
Finished Jun 13 01:49:06 PM PDT 24
Peak memory 206492 kb
Host smart-bc2757a2-44d5-4947-a149-e735a73c71d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134078398 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2134078398
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1772523567
Short name T920
Test name
Test status
Simulation time 165916681374 ps
CPU time 1255.07 seconds
Started Jun 13 01:49:05 PM PDT 24
Finished Jun 13 02:10:01 PM PDT 24
Peak memory 222888 kb
Host smart-297266a7-00bb-49b4-9fa1-80fc4484dc21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772523567 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1772523567
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1681282113
Short name T844
Test name
Test status
Simulation time 32681997 ps
CPU time 1.31 seconds
Started Jun 13 01:50:25 PM PDT 24
Finished Jun 13 01:50:27 PM PDT 24
Peak memory 220536 kb
Host smart-9335d699-2bba-4f90-9811-42ba5dc42a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681282113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1681282113
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3376013868
Short name T537
Test name
Test status
Simulation time 18286706 ps
CPU time 1.04 seconds
Started Jun 13 01:50:14 PM PDT 24
Finished Jun 13 01:50:17 PM PDT 24
Peak memory 214560 kb
Host smart-b0a102b5-5024-4a68-8ede-fc5f4ad5950f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376013868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3376013868
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3065010109
Short name T156
Test name
Test status
Simulation time 22863274 ps
CPU time 0.92 seconds
Started Jun 13 01:50:14 PM PDT 24
Finished Jun 13 01:50:17 PM PDT 24
Peak memory 214824 kb
Host smart-2c7e2cfc-4e44-4d35-a8d6-74a437f1cad7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065010109 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3065010109
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2169354005
Short name T793
Test name
Test status
Simulation time 107761370 ps
CPU time 1.23 seconds
Started Jun 13 01:50:17 PM PDT 24
Finished Jun 13 01:50:20 PM PDT 24
Peak memory 216360 kb
Host smart-50c504f3-f4f5-4684-8e5d-6b7346292d0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169354005 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2169354005
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3857657623
Short name T218
Test name
Test status
Simulation time 22442841 ps
CPU time 0.91 seconds
Started Jun 13 01:50:15 PM PDT 24
Finished Jun 13 01:50:18 PM PDT 24
Peak memory 218092 kb
Host smart-451ca90e-741a-4fb4-b09d-bc71d9e69b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857657623 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3857657623
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3482034155
Short name T878
Test name
Test status
Simulation time 39361651 ps
CPU time 1.53 seconds
Started Jun 13 01:50:16 PM PDT 24
Finished Jun 13 01:50:20 PM PDT 24
Peak memory 217724 kb
Host smart-3334fb45-7caf-415e-bab7-08c6243c6df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482034155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3482034155
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3202239857
Short name T34
Test name
Test status
Simulation time 27468753 ps
CPU time 0.87 seconds
Started Jun 13 01:50:16 PM PDT 24
Finished Jun 13 01:50:19 PM PDT 24
Peak memory 214884 kb
Host smart-894eda72-2292-4ae5-9493-60f3aa7f8697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202239857 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3202239857
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.679828802
Short name T683
Test name
Test status
Simulation time 133181025 ps
CPU time 0.95 seconds
Started Jun 13 01:50:17 PM PDT 24
Finished Jun 13 01:50:19 PM PDT 24
Peak memory 214720 kb
Host smart-ec0a5abf-2f01-437c-a339-ac2662184076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679828802 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.679828802
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2502378990
Short name T747
Test name
Test status
Simulation time 725736953 ps
CPU time 4.12 seconds
Started Jun 13 01:50:17 PM PDT 24
Finished Jun 13 01:50:23 PM PDT 24
Peak memory 214600 kb
Host smart-b6360668-62a9-4151-9d17-7e4000fbb1de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502378990 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2502378990
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3790173360
Short name T226
Test name
Test status
Simulation time 11174457303 ps
CPU time 275.09 seconds
Started Jun 13 01:50:17 PM PDT 24
Finished Jun 13 01:54:54 PM PDT 24
Peak memory 217008 kb
Host smart-4c2b82de-8378-4297-9646-10acdc4e59a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790173360 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3790173360
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.628006173
Short name T612
Test name
Test status
Simulation time 76835230 ps
CPU time 1.16 seconds
Started Jun 13 01:50:26 PM PDT 24
Finished Jun 13 01:50:28 PM PDT 24
Peak memory 219004 kb
Host smart-afdf6be1-883d-4140-937e-12bc72054135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628006173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.628006173
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1690058569
Short name T971
Test name
Test status
Simulation time 58111090 ps
CPU time 1.16 seconds
Started Jun 13 01:50:17 PM PDT 24
Finished Jun 13 01:50:20 PM PDT 24
Peak memory 206172 kb
Host smart-9b97bf57-a63a-47ca-b2c9-6b5125a7f9df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690058569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1690058569
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3769550483
Short name T82
Test name
Test status
Simulation time 57673990 ps
CPU time 0.88 seconds
Started Jun 13 01:50:16 PM PDT 24
Finished Jun 13 01:50:18 PM PDT 24
Peak memory 214808 kb
Host smart-94771c58-ed7a-4733-bd46-57171d3b4b68
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769550483 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3769550483
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1644187430
Short name T546
Test name
Test status
Simulation time 89243403 ps
CPU time 1.07 seconds
Started Jun 13 01:50:17 PM PDT 24
Finished Jun 13 01:50:20 PM PDT 24
Peak memory 216172 kb
Host smart-68bdcb85-494d-4cfc-9218-3f320a3a3af8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644187430 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1644187430
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.4137627127
Short name T911
Test name
Test status
Simulation time 33849150 ps
CPU time 0.89 seconds
Started Jun 13 01:50:17 PM PDT 24
Finished Jun 13 01:50:19 PM PDT 24
Peak memory 217816 kb
Host smart-a6d3bde8-46e7-4ef7-84cc-7c65882d88ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137627127 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.4137627127
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2016624657
Short name T924
Test name
Test status
Simulation time 32778192 ps
CPU time 1.29 seconds
Started Jun 13 01:50:16 PM PDT 24
Finished Jun 13 01:50:19 PM PDT 24
Peak memory 216632 kb
Host smart-445c15c8-767a-46f7-9535-0de614d49d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016624657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2016624657
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3793523988
Short name T520
Test name
Test status
Simulation time 39529784 ps
CPU time 1.01 seconds
Started Jun 13 01:50:15 PM PDT 24
Finished Jun 13 01:50:18 PM PDT 24
Peak memory 223376 kb
Host smart-3126de4b-c35c-479d-a6c2-5410dc1d0cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793523988 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3793523988
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1049499754
Short name T909
Test name
Test status
Simulation time 46039278 ps
CPU time 0.94 seconds
Started Jun 13 01:50:15 PM PDT 24
Finished Jun 13 01:50:18 PM PDT 24
Peak memory 214560 kb
Host smart-4398a7c7-8c9c-49d8-8b4d-f5124d278317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049499754 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1049499754
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3306048672
Short name T488
Test name
Test status
Simulation time 164401440 ps
CPU time 2.04 seconds
Started Jun 13 01:50:13 PM PDT 24
Finished Jun 13 01:50:18 PM PDT 24
Peak memory 216516 kb
Host smart-7cb3a01f-487f-4f2c-9c67-31a4fc2397e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306048672 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3306048672
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_alert.1290244873
Short name T222
Test name
Test status
Simulation time 84324845 ps
CPU time 1.26 seconds
Started Jun 13 01:50:16 PM PDT 24
Finished Jun 13 01:50:19 PM PDT 24
Peak memory 218700 kb
Host smart-0da8227e-a17e-46a0-80f1-a0d8a58a1774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290244873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1290244873
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2811414089
Short name T466
Test name
Test status
Simulation time 34261469 ps
CPU time 0.92 seconds
Started Jun 13 01:50:21 PM PDT 24
Finished Jun 13 01:50:23 PM PDT 24
Peak memory 206076 kb
Host smart-b5daa94e-b7f4-4d84-bb7a-bfd17a5c27bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811414089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2811414089
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2812199776
Short name T425
Test name
Test status
Simulation time 20788382 ps
CPU time 0.85 seconds
Started Jun 13 01:50:20 PM PDT 24
Finished Jun 13 01:50:21 PM PDT 24
Peak memory 215692 kb
Host smart-8c203a8f-82ef-45c3-9dd8-f5e1fc9934ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812199776 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2812199776
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1330664486
Short name T437
Test name
Test status
Simulation time 109572515 ps
CPU time 1.19 seconds
Started Jun 13 01:50:23 PM PDT 24
Finished Jun 13 01:50:25 PM PDT 24
Peak memory 216188 kb
Host smart-bf5e4550-e61e-4bde-abd6-db22be745555
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330664486 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1330664486
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.909766378
Short name T646
Test name
Test status
Simulation time 22584123 ps
CPU time 1.07 seconds
Started Jun 13 01:50:17 PM PDT 24
Finished Jun 13 01:50:20 PM PDT 24
Peak memory 223376 kb
Host smart-5e1881ef-37da-43ca-859f-01a1b7d0290c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909766378 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.909766378
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3752075378
Short name T47
Test name
Test status
Simulation time 133500299 ps
CPU time 1.43 seconds
Started Jun 13 01:50:17 PM PDT 24
Finished Jun 13 01:50:20 PM PDT 24
Peak memory 217980 kb
Host smart-0bdb78d6-3df0-4396-956a-11398db0c229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752075378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3752075378
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.4082232046
Short name T587
Test name
Test status
Simulation time 43830716 ps
CPU time 0.89 seconds
Started Jun 13 01:50:26 PM PDT 24
Finished Jun 13 01:50:28 PM PDT 24
Peak memory 215004 kb
Host smart-be489541-d3a2-49fd-8dc7-8a0ba132e2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082232046 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.4082232046
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.687156333
Short name T421
Test name
Test status
Simulation time 16409923 ps
CPU time 1 seconds
Started Jun 13 01:50:24 PM PDT 24
Finished Jun 13 01:50:26 PM PDT 24
Peak memory 214776 kb
Host smart-5836fff7-c178-4a9b-84c3-303815603824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687156333 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.687156333
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2924033980
Short name T623
Test name
Test status
Simulation time 179341232 ps
CPU time 3.83 seconds
Started Jun 13 01:50:26 PM PDT 24
Finished Jun 13 01:50:31 PM PDT 24
Peak memory 216672 kb
Host smart-92ba32f4-c787-4849-8009-793137fd7590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924033980 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2924033980
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.579991530
Short name T715
Test name
Test status
Simulation time 83568770651 ps
CPU time 1033.15 seconds
Started Jun 13 01:50:16 PM PDT 24
Finished Jun 13 02:07:31 PM PDT 24
Peak memory 222932 kb
Host smart-d3a81877-dbbc-4697-b9ef-fbc00c435eba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579991530 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.579991530
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.426382800
Short name T29
Test name
Test status
Simulation time 50428555 ps
CPU time 1.26 seconds
Started Jun 13 01:50:22 PM PDT 24
Finished Jun 13 01:50:24 PM PDT 24
Peak memory 217904 kb
Host smart-e7de7b73-d9d7-44bf-b511-8ebbcf62312d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426382800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.426382800
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3284871816
Short name T981
Test name
Test status
Simulation time 13832424 ps
CPU time 0.91 seconds
Started Jun 13 01:50:22 PM PDT 24
Finished Jun 13 01:50:24 PM PDT 24
Peak memory 206084 kb
Host smart-a7238312-4b9b-4012-afb5-b272375d5982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284871816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3284871816
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.670818727
Short name T535
Test name
Test status
Simulation time 20912591 ps
CPU time 0.86 seconds
Started Jun 13 01:50:21 PM PDT 24
Finished Jun 13 01:50:22 PM PDT 24
Peak memory 215816 kb
Host smart-ef1a229a-366f-4c65-9185-c5161ef8475a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670818727 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.670818727
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1631107086
Short name T861
Test name
Test status
Simulation time 131056119 ps
CPU time 1.19 seconds
Started Jun 13 01:50:24 PM PDT 24
Finished Jun 13 01:50:25 PM PDT 24
Peak memory 216424 kb
Host smart-ae841cf8-b806-45cb-9df3-a7325ab65314
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631107086 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1631107086
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.145769250
Short name T154
Test name
Test status
Simulation time 47862682 ps
CPU time 1.24 seconds
Started Jun 13 01:50:24 PM PDT 24
Finished Jun 13 01:50:25 PM PDT 24
Peak memory 225136 kb
Host smart-e946389b-5b52-411d-a9f3-d9a2b1578b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145769250 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.145769250
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.325828429
Short name T500
Test name
Test status
Simulation time 42062937 ps
CPU time 1.2 seconds
Started Jun 13 01:50:21 PM PDT 24
Finished Jun 13 01:50:23 PM PDT 24
Peak memory 216996 kb
Host smart-9313452d-9b2c-4d2b-b9fb-a4757eb30f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325828429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.325828429
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2310449531
Short name T904
Test name
Test status
Simulation time 34057796 ps
CPU time 1.02 seconds
Started Jun 13 01:50:20 PM PDT 24
Finished Jun 13 01:50:22 PM PDT 24
Peak memory 223368 kb
Host smart-6abb18e6-3146-4d71-abde-6af554dbcc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310449531 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2310449531
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1824161518
Short name T447
Test name
Test status
Simulation time 17032288 ps
CPU time 1.02 seconds
Started Jun 13 01:50:22 PM PDT 24
Finished Jun 13 01:50:24 PM PDT 24
Peak memory 214568 kb
Host smart-fd5cffe8-b524-4ccc-bf0f-0b51dfd0bc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824161518 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1824161518
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1061151799
Short name T845
Test name
Test status
Simulation time 74646810 ps
CPU time 1.36 seconds
Started Jun 13 01:50:29 PM PDT 24
Finished Jun 13 01:50:31 PM PDT 24
Peak memory 216480 kb
Host smart-6a82b0ec-6308-438b-88a6-6dfb0f80bb8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061151799 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1061151799
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1310240877
Short name T750
Test name
Test status
Simulation time 208946921556 ps
CPU time 1337.01 seconds
Started Jun 13 01:50:22 PM PDT 24
Finished Jun 13 02:12:41 PM PDT 24
Peak memory 223896 kb
Host smart-12c90001-4a90-4524-bbbc-58f1bd030d4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310240877 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1310240877
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3565279080
Short name T193
Test name
Test status
Simulation time 100111305 ps
CPU time 1.2 seconds
Started Jun 13 01:50:22 PM PDT 24
Finished Jun 13 01:50:25 PM PDT 24
Peak memory 215088 kb
Host smart-119daf13-e147-49a2-a6e1-cb9aba6b2395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565279080 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3565279080
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1657890568
Short name T843
Test name
Test status
Simulation time 54339840 ps
CPU time 0.87 seconds
Started Jun 13 01:50:21 PM PDT 24
Finished Jun 13 01:50:22 PM PDT 24
Peak memory 206064 kb
Host smart-e1277aed-ff0b-4915-baf2-feba851b3cfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657890568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1657890568
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3059156003
Short name T419
Test name
Test status
Simulation time 31617621 ps
CPU time 0.85 seconds
Started Jun 13 01:50:22 PM PDT 24
Finished Jun 13 01:50:24 PM PDT 24
Peak memory 215448 kb
Host smart-96209093-f292-4a8e-bdea-74093ccee15e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059156003 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3059156003
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2029088529
Short name T881
Test name
Test status
Simulation time 84786307 ps
CPU time 1.16 seconds
Started Jun 13 01:50:20 PM PDT 24
Finished Jun 13 01:50:22 PM PDT 24
Peak memory 216304 kb
Host smart-eba675cc-95dd-42b3-847e-43fdad271743
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029088529 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2029088529
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2339693520
Short name T567
Test name
Test status
Simulation time 29964409 ps
CPU time 1.42 seconds
Started Jun 13 01:50:21 PM PDT 24
Finished Jun 13 01:50:23 PM PDT 24
Peak memory 225060 kb
Host smart-255094ee-2d3b-4cd4-8c7e-5eb7a146f2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339693520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2339693520
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2270530051
Short name T436
Test name
Test status
Simulation time 67530295 ps
CPU time 2.25 seconds
Started Jun 13 01:50:21 PM PDT 24
Finished Jun 13 01:50:24 PM PDT 24
Peak memory 219548 kb
Host smart-a63f169e-7f4e-4d44-bda9-a5c02fea77ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270530051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2270530051
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_smoke.1602303086
Short name T799
Test name
Test status
Simulation time 16621177 ps
CPU time 1.05 seconds
Started Jun 13 01:50:22 PM PDT 24
Finished Jun 13 01:50:24 PM PDT 24
Peak memory 214684 kb
Host smart-dd052643-afb5-44e6-b6f2-84de618f1acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602303086 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1602303086
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1721037272
Short name T418
Test name
Test status
Simulation time 85765127 ps
CPU time 2.16 seconds
Started Jun 13 01:50:21 PM PDT 24
Finished Jun 13 01:50:24 PM PDT 24
Peak memory 218840 kb
Host smart-abe51c03-e703-4dab-8949-47dd9785695e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721037272 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1721037272
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2717376222
Short name T704
Test name
Test status
Simulation time 236335816520 ps
CPU time 1390.02 seconds
Started Jun 13 01:50:21 PM PDT 24
Finished Jun 13 02:13:32 PM PDT 24
Peak memory 223392 kb
Host smart-0b9e99fb-3c0f-4866-9d98-1d2728253f8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717376222 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2717376222
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.404948837
Short name T104
Test name
Test status
Simulation time 83933065 ps
CPU time 1.15 seconds
Started Jun 13 01:50:26 PM PDT 24
Finished Jun 13 01:50:29 PM PDT 24
Peak memory 219140 kb
Host smart-21765903-1b65-43e7-866a-5f7557694db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404948837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.404948837
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3494450
Short name T49
Test name
Test status
Simulation time 44455909 ps
CPU time 0.88 seconds
Started Jun 13 01:50:28 PM PDT 24
Finished Jun 13 01:50:30 PM PDT 24
Peak memory 206112 kb
Host smart-11a02004-7a2f-4acc-9fc8-7f56821bc0ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3494450
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3889291201
Short name T928
Test name
Test status
Simulation time 41561753 ps
CPU time 0.82 seconds
Started Jun 13 01:50:26 PM PDT 24
Finished Jun 13 01:50:28 PM PDT 24
Peak memory 215580 kb
Host smart-e02988b9-5a5c-4d04-872d-4c2daf4f16f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889291201 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3889291201
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2846415191
Short name T802
Test name
Test status
Simulation time 19703647 ps
CPU time 0.96 seconds
Started Jun 13 01:50:26 PM PDT 24
Finished Jun 13 01:50:29 PM PDT 24
Peak memory 217624 kb
Host smart-1019c4aa-94f7-447c-a834-001e61f2dc92
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846415191 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2846415191
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.238441672
Short name T52
Test name
Test status
Simulation time 33170786 ps
CPU time 0.98 seconds
Started Jun 13 01:50:28 PM PDT 24
Finished Jun 13 01:50:30 PM PDT 24
Peak memory 223196 kb
Host smart-04a5a124-e121-4a2c-813f-1808aeefec7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238441672 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.238441672
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.983458085
Short name T2
Test name
Test status
Simulation time 67217427 ps
CPU time 1.33 seconds
Started Jun 13 01:50:29 PM PDT 24
Finished Jun 13 01:50:31 PM PDT 24
Peak memory 216728 kb
Host smart-02e88d25-721c-4113-a3af-4e29a5d3c937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983458085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.983458085
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2772376807
Short name T937
Test name
Test status
Simulation time 22837035 ps
CPU time 1.14 seconds
Started Jun 13 01:50:20 PM PDT 24
Finished Jun 13 01:50:22 PM PDT 24
Peak memory 214736 kb
Host smart-7bf2fbc0-b880-4999-a5c8-4bead2233479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772376807 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2772376807
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.4217309092
Short name T558
Test name
Test status
Simulation time 14612831 ps
CPU time 0.98 seconds
Started Jun 13 01:50:29 PM PDT 24
Finished Jun 13 01:50:31 PM PDT 24
Peak memory 206396 kb
Host smart-48ee87a7-3650-4d91-a576-89d80f075e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217309092 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.4217309092
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.91975952
Short name T815
Test name
Test status
Simulation time 544940504 ps
CPU time 3.34 seconds
Started Jun 13 01:50:30 PM PDT 24
Finished Jun 13 01:50:34 PM PDT 24
Peak memory 219616 kb
Host smart-20f5123d-126c-4908-a48e-bb007e3f29bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91975952 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.91975952
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2229575583
Short name T449
Test name
Test status
Simulation time 185263576360 ps
CPU time 2246.6 seconds
Started Jun 13 01:50:22 PM PDT 24
Finished Jun 13 02:27:50 PM PDT 24
Peak memory 226900 kb
Host smart-b8018ef3-195c-46f8-b9c9-bdd111e0b4b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229575583 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2229575583
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2143485062
Short name T969
Test name
Test status
Simulation time 26699653 ps
CPU time 1.21 seconds
Started Jun 13 01:50:27 PM PDT 24
Finished Jun 13 01:50:29 PM PDT 24
Peak memory 218988 kb
Host smart-0ace1dac-7ac5-4f4a-8a28-cbfa6cc2a2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143485062 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2143485062
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2851102242
Short name T507
Test name
Test status
Simulation time 49004935 ps
CPU time 0.99 seconds
Started Jun 13 01:50:39 PM PDT 24
Finished Jun 13 01:50:41 PM PDT 24
Peak memory 214344 kb
Host smart-a14a068c-f844-413e-a53c-6b57b63d48f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851102242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2851102242
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.4217584576
Short name T483
Test name
Test status
Simulation time 149813072 ps
CPU time 0.88 seconds
Started Jun 13 01:50:26 PM PDT 24
Finished Jun 13 01:50:27 PM PDT 24
Peak memory 214860 kb
Host smart-42bc3f38-9a90-4147-ba98-ad268b0edcd3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217584576 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.4217584576
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2308163047
Short name T581
Test name
Test status
Simulation time 65532465 ps
CPU time 1.11 seconds
Started Jun 13 01:50:26 PM PDT 24
Finished Jun 13 01:50:28 PM PDT 24
Peak memory 218944 kb
Host smart-0ee9ede3-77ad-4795-9904-44622196aca0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308163047 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2308163047
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1374098782
Short name T847
Test name
Test status
Simulation time 28776202 ps
CPU time 0.88 seconds
Started Jun 13 01:50:35 PM PDT 24
Finished Jun 13 01:50:37 PM PDT 24
Peak memory 218752 kb
Host smart-32844e7f-ac27-4445-8610-2e11e79d0506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374098782 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1374098782
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1117836942
Short name T448
Test name
Test status
Simulation time 325296872 ps
CPU time 1.57 seconds
Started Jun 13 01:50:26 PM PDT 24
Finished Jun 13 01:50:28 PM PDT 24
Peak memory 219268 kb
Host smart-0fbd6bd4-5073-488e-87e4-640f7903337b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117836942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1117836942
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.56007018
Short name T93
Test name
Test status
Simulation time 34271474 ps
CPU time 0.9 seconds
Started Jun 13 01:50:27 PM PDT 24
Finished Jun 13 01:50:29 PM PDT 24
Peak memory 214872 kb
Host smart-f9df7383-a481-439b-afc4-9f412b99fff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56007018 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.56007018
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2402136234
Short name T240
Test name
Test status
Simulation time 73357771 ps
CPU time 0.92 seconds
Started Jun 13 01:50:28 PM PDT 24
Finished Jun 13 01:50:30 PM PDT 24
Peak memory 214616 kb
Host smart-b8f1d2ff-fec1-49a8-9ffd-2f3998e1c196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402136234 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2402136234
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3068182732
Short name T351
Test name
Test status
Simulation time 45454373 ps
CPU time 1.64 seconds
Started Jun 13 01:50:28 PM PDT 24
Finished Jun 13 01:50:31 PM PDT 24
Peak memory 214680 kb
Host smart-a4f1f3e9-4559-4b36-ae64-38d1b709f57a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068182732 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3068182732
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2692636055
Short name T533
Test name
Test status
Simulation time 98481608060 ps
CPU time 1307.66 seconds
Started Jun 13 01:50:28 PM PDT 24
Finished Jun 13 02:12:17 PM PDT 24
Peak memory 224908 kb
Host smart-49274457-9d5c-4c2d-8968-17b67b01665a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692636055 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2692636055
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1147137109
Short name T81
Test name
Test status
Simulation time 48970094 ps
CPU time 1.23 seconds
Started Jun 13 01:50:39 PM PDT 24
Finished Jun 13 01:50:41 PM PDT 24
Peak memory 218224 kb
Host smart-4499796f-bebb-4fe7-8cf0-4e09f770f402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147137109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1147137109
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1509029385
Short name T907
Test name
Test status
Simulation time 62611026 ps
CPU time 0.98 seconds
Started Jun 13 01:50:35 PM PDT 24
Finished Jun 13 01:50:36 PM PDT 24
Peak memory 214364 kb
Host smart-6c074832-e17c-4235-a56f-edaf6c838fec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509029385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1509029385
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.902910383
Short name T550
Test name
Test status
Simulation time 16357840 ps
CPU time 0.87 seconds
Started Jun 13 01:50:35 PM PDT 24
Finished Jun 13 01:50:37 PM PDT 24
Peak memory 214828 kb
Host smart-30bce468-f7a9-40c6-a271-a2ed5c81419a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902910383 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.902910383
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2043877793
Short name T121
Test name
Test status
Simulation time 27933902 ps
CPU time 1.11 seconds
Started Jun 13 01:50:31 PM PDT 24
Finished Jun 13 01:50:32 PM PDT 24
Peak memory 216248 kb
Host smart-f650552e-85cb-482f-9cfb-0f77c5d7170f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043877793 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2043877793
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.4200815815
Short name T125
Test name
Test status
Simulation time 122420335 ps
CPU time 1.06 seconds
Started Jun 13 01:50:35 PM PDT 24
Finished Jun 13 01:50:37 PM PDT 24
Peak memory 219092 kb
Host smart-6910d192-4d91-4a56-90dc-58d62a872e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200815815 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.4200815815
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1994910746
Short name T352
Test name
Test status
Simulation time 64496425 ps
CPU time 1.02 seconds
Started Jun 13 01:50:41 PM PDT 24
Finished Jun 13 01:50:44 PM PDT 24
Peak memory 216624 kb
Host smart-13970b95-8a58-4537-9e4e-518b9fe92357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994910746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1994910746
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.902344601
Short name T357
Test name
Test status
Simulation time 24216534 ps
CPU time 1.13 seconds
Started Jun 13 01:50:33 PM PDT 24
Finished Jun 13 01:50:35 PM PDT 24
Peak memory 214748 kb
Host smart-747bec36-e95c-4e13-a1f2-bdea50a5c923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902344601 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.902344601
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.974533309
Short name T353
Test name
Test status
Simulation time 22416729 ps
CPU time 0.96 seconds
Started Jun 13 01:50:33 PM PDT 24
Finished Jun 13 01:50:35 PM PDT 24
Peak memory 214580 kb
Host smart-43858053-fb0f-4384-b786-35017b4f5148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974533309 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.974533309
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1845216540
Short name T913
Test name
Test status
Simulation time 284629951 ps
CPU time 3.41 seconds
Started Jun 13 01:50:39 PM PDT 24
Finished Jun 13 01:50:44 PM PDT 24
Peak memory 214616 kb
Host smart-893cdc0b-e36b-441a-8df3-d860a6c3353e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845216540 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1845216540
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.4140725029
Short name T231
Test name
Test status
Simulation time 260952637103 ps
CPU time 645.87 seconds
Started Jun 13 01:50:34 PM PDT 24
Finished Jun 13 02:01:20 PM PDT 24
Peak memory 226612 kb
Host smart-aeabc585-efa7-4dfc-ba5f-857d00447ac5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140725029 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.4140725029
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.387194915
Short name T482
Test name
Test status
Simulation time 52070994 ps
CPU time 1.23 seconds
Started Jun 13 01:50:33 PM PDT 24
Finished Jun 13 01:50:35 PM PDT 24
Peak memory 218972 kb
Host smart-0c7ada2c-6ff5-4e2c-b1dc-fa3494f44b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387194915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.387194915
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.71411278
Short name T369
Test name
Test status
Simulation time 27120529 ps
CPU time 0.87 seconds
Started Jun 13 01:50:34 PM PDT 24
Finished Jun 13 01:50:36 PM PDT 24
Peak memory 206080 kb
Host smart-7d9ae7de-82d1-44b6-94e5-fe3b7b9908a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71411278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.71411278
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1837774569
Short name T585
Test name
Test status
Simulation time 21199546 ps
CPU time 0.84 seconds
Started Jun 13 01:50:40 PM PDT 24
Finished Jun 13 01:50:44 PM PDT 24
Peak memory 215672 kb
Host smart-a53e567b-fc8f-45c0-9445-f97e9fba6e59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837774569 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1837774569
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1957522685
Short name T714
Test name
Test status
Simulation time 32826581 ps
CPU time 1.19 seconds
Started Jun 13 01:50:40 PM PDT 24
Finished Jun 13 01:50:44 PM PDT 24
Peak memory 217540 kb
Host smart-3d927bb5-76b2-4e2f-89ff-b103f883c363
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957522685 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1957522685
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.76653936
Short name T929
Test name
Test status
Simulation time 18397924 ps
CPU time 1.06 seconds
Started Jun 13 01:50:35 PM PDT 24
Finished Jun 13 01:50:37 PM PDT 24
Peak memory 217700 kb
Host smart-fcdbd09d-71a2-4160-b6d6-eac5c7abc2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76653936 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.76653936
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1913989835
Short name T708
Test name
Test status
Simulation time 64102375 ps
CPU time 1.01 seconds
Started Jun 13 01:50:39 PM PDT 24
Finished Jun 13 01:50:41 PM PDT 24
Peak memory 216644 kb
Host smart-88945eea-5acc-4a12-a79e-5028c984304e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913989835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1913989835
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1535276574
Short name T968
Test name
Test status
Simulation time 22356568 ps
CPU time 1.21 seconds
Started Jun 13 01:50:39 PM PDT 24
Finished Jun 13 01:50:42 PM PDT 24
Peak memory 223372 kb
Host smart-4d0afedb-6696-4fc7-a90d-1e7ecff7e649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535276574 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1535276574
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2951982468
Short name T689
Test name
Test status
Simulation time 32063388 ps
CPU time 0.93 seconds
Started Jun 13 01:50:32 PM PDT 24
Finished Jun 13 01:50:34 PM PDT 24
Peak memory 214588 kb
Host smart-ae1e9cad-a0b6-43bf-af6a-01b4bb28b8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951982468 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2951982468
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.228890111
Short name T807
Test name
Test status
Simulation time 158285068 ps
CPU time 1.88 seconds
Started Jun 13 01:50:32 PM PDT 24
Finished Jun 13 01:50:35 PM PDT 24
Peak memory 214568 kb
Host smart-d1dea442-c525-4920-9294-5a71de4a8d4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228890111 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.228890111
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.676914052
Short name T230
Test name
Test status
Simulation time 254271707051 ps
CPU time 1489.24 seconds
Started Jun 13 01:50:39 PM PDT 24
Finished Jun 13 02:15:31 PM PDT 24
Peak memory 223308 kb
Host smart-052b1663-950f-48a5-94e0-35bd9e53f93e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676914052 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.676914052
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1349936400
Short name T833
Test name
Test status
Simulation time 41114599 ps
CPU time 1.24 seconds
Started Jun 13 01:50:39 PM PDT 24
Finished Jun 13 01:50:42 PM PDT 24
Peak memory 219216 kb
Host smart-46235c19-6727-43a5-8d66-90bb818535d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349936400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1349936400
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.949447379
Short name T754
Test name
Test status
Simulation time 20732038 ps
CPU time 0.87 seconds
Started Jun 13 01:50:39 PM PDT 24
Finished Jun 13 01:50:42 PM PDT 24
Peak memory 205952 kb
Host smart-340b22e9-40b9-4011-8124-8d637fe088fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949447379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.949447379
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1623958589
Short name T204
Test name
Test status
Simulation time 16094867 ps
CPU time 0.85 seconds
Started Jun 13 01:50:40 PM PDT 24
Finished Jun 13 01:50:43 PM PDT 24
Peak memory 215580 kb
Host smart-7a16a25b-17f3-49ac-92a3-a634918343ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623958589 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1623958589
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3363928976
Short name T120
Test name
Test status
Simulation time 48014795 ps
CPU time 1.34 seconds
Started Jun 13 01:50:39 PM PDT 24
Finished Jun 13 01:50:42 PM PDT 24
Peak memory 216200 kb
Host smart-66811cfc-e4be-4b9f-bd5c-9a7df11b686f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363928976 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3363928976
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3219376850
Short name T599
Test name
Test status
Simulation time 20671316 ps
CPU time 1.09 seconds
Started Jun 13 01:50:40 PM PDT 24
Finished Jun 13 01:50:43 PM PDT 24
Peak memory 219128 kb
Host smart-1bd334ad-0f4c-4297-a4bc-d7b6a44c620e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219376850 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3219376850
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1053400694
Short name T748
Test name
Test status
Simulation time 44262636 ps
CPU time 1.64 seconds
Started Jun 13 01:50:35 PM PDT 24
Finished Jun 13 01:50:38 PM PDT 24
Peak memory 216736 kb
Host smart-33bbce8c-35c6-4f0f-b717-9995d66ceb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053400694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1053400694
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3438103005
Short name T790
Test name
Test status
Simulation time 36666265 ps
CPU time 1.01 seconds
Started Jun 13 01:50:36 PM PDT 24
Finished Jun 13 01:50:38 PM PDT 24
Peak memory 223212 kb
Host smart-e95f5e73-5ab0-4825-83e3-db67bfb061f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438103005 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3438103005
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.753723717
Short name T800
Test name
Test status
Simulation time 47192152 ps
CPU time 0.93 seconds
Started Jun 13 01:50:34 PM PDT 24
Finished Jun 13 01:50:36 PM PDT 24
Peak memory 214608 kb
Host smart-7b7e0b4b-5655-4fff-92dc-76e491b39e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753723717 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.753723717
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1429794038
Short name T827
Test name
Test status
Simulation time 1386562444 ps
CPU time 4.8 seconds
Started Jun 13 01:50:40 PM PDT 24
Finished Jun 13 01:50:48 PM PDT 24
Peak memory 216644 kb
Host smart-1497d172-e5ca-43f7-9b9f-c0051e2cfe38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429794038 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1429794038
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3634372556
Short name T813
Test name
Test status
Simulation time 63220368700 ps
CPU time 712.56 seconds
Started Jun 13 01:50:37 PM PDT 24
Finished Jun 13 02:02:30 PM PDT 24
Peak memory 218868 kb
Host smart-434e7c6b-dba6-4f2e-9afa-b1404e489575
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634372556 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3634372556
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.334755836
Short name T707
Test name
Test status
Simulation time 116131984 ps
CPU time 1.15 seconds
Started Jun 13 01:49:06 PM PDT 24
Finished Jun 13 01:49:10 PM PDT 24
Peak memory 219140 kb
Host smart-b82dd92a-5f2c-4a6b-b18b-174bfe0fc3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334755836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.334755836
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1693001387
Short name T460
Test name
Test status
Simulation time 39381580 ps
CPU time 0.92 seconds
Started Jun 13 01:49:07 PM PDT 24
Finished Jun 13 01:49:10 PM PDT 24
Peak memory 214132 kb
Host smart-c0f25b50-3898-46f0-9ee8-9122e89122e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693001387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1693001387
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3264409780
Short name T197
Test name
Test status
Simulation time 13400141 ps
CPU time 0.95 seconds
Started Jun 13 01:49:08 PM PDT 24
Finished Jun 13 01:49:10 PM PDT 24
Peak memory 215764 kb
Host smart-42580aa5-9ee1-48e1-9438-07e014f831b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264409780 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3264409780
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.887113120
Short name T966
Test name
Test status
Simulation time 42297457 ps
CPU time 1.06 seconds
Started Jun 13 01:49:08 PM PDT 24
Finished Jun 13 01:49:11 PM PDT 24
Peak memory 216116 kb
Host smart-707a1bea-e71d-416d-921b-20b46e4df6f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887113120 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.887113120
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2524318966
Short name T435
Test name
Test status
Simulation time 85066962 ps
CPU time 1.13 seconds
Started Jun 13 01:49:06 PM PDT 24
Finished Jun 13 01:49:09 PM PDT 24
Peak memory 218976 kb
Host smart-824d9b75-c7ad-43bd-9243-1b28de0929e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524318966 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2524318966
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3985821263
Short name T338
Test name
Test status
Simulation time 45985983 ps
CPU time 1.76 seconds
Started Jun 13 01:49:00 PM PDT 24
Finished Jun 13 01:49:04 PM PDT 24
Peak memory 217668 kb
Host smart-853fcb7b-db46-4a62-9b5c-ef4775f67333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985821263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3985821263
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.184478442
Short name T394
Test name
Test status
Simulation time 33282095 ps
CPU time 0.92 seconds
Started Jun 13 01:49:08 PM PDT 24
Finished Jun 13 01:49:11 PM PDT 24
Peak memory 214752 kb
Host smart-c690ea9d-4766-46e4-a644-e587219cc5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184478442 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.184478442
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3537744953
Short name T241
Test name
Test status
Simulation time 73998848 ps
CPU time 0.87 seconds
Started Jun 13 01:49:03 PM PDT 24
Finished Jun 13 01:49:05 PM PDT 24
Peak memory 206280 kb
Host smart-ac27bb06-5908-48d6-8037-39e5cf487726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537744953 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3537744953
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2059476671
Short name T553
Test name
Test status
Simulation time 177392667 ps
CPU time 0.94 seconds
Started Jun 13 01:49:00 PM PDT 24
Finished Jun 13 01:49:04 PM PDT 24
Peak memory 214596 kb
Host smart-43421df9-595c-4356-a2e0-8c6b853a0dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059476671 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2059476671
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3739089353
Short name T992
Test name
Test status
Simulation time 863333318 ps
CPU time 5.67 seconds
Started Jun 13 01:49:02 PM PDT 24
Finished Jun 13 01:49:09 PM PDT 24
Peak memory 214668 kb
Host smart-03982735-77ab-458b-96de-42664d0effb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739089353 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3739089353
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.4251674430
Short name T453
Test name
Test status
Simulation time 123172826250 ps
CPU time 2611.43 seconds
Started Jun 13 01:48:59 PM PDT 24
Finished Jun 13 02:32:32 PM PDT 24
Peak memory 228572 kb
Host smart-02765755-bc7b-4fad-8d80-fc5247e60882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251674430 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.4251674430
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.4277737436
Short name T866
Test name
Test status
Simulation time 40562945 ps
CPU time 1.19 seconds
Started Jun 13 01:50:42 PM PDT 24
Finished Jun 13 01:50:45 PM PDT 24
Peak memory 219304 kb
Host smart-0c0d5e3a-d271-4c81-977f-2174aed4c94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277737436 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.4277737436
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.4290622525
Short name T158
Test name
Test status
Simulation time 46871955 ps
CPU time 0.84 seconds
Started Jun 13 01:50:40 PM PDT 24
Finished Jun 13 01:50:44 PM PDT 24
Peak memory 217640 kb
Host smart-7961373c-1021-40fc-9b70-bd620490164f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290622525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.4290622525
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3948671187
Short name T20
Test name
Test status
Simulation time 81936715 ps
CPU time 2.91 seconds
Started Jun 13 01:50:40 PM PDT 24
Finished Jun 13 01:50:46 PM PDT 24
Peak memory 219340 kb
Host smart-0ef8ecda-b629-4845-b903-8e537972367f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948671187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3948671187
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.2759611791
Short name T879
Test name
Test status
Simulation time 49128587 ps
CPU time 1.47 seconds
Started Jun 13 01:50:39 PM PDT 24
Finished Jun 13 01:50:43 PM PDT 24
Peak memory 215120 kb
Host smart-501d2691-0dcd-46b9-867f-e2212c051c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759611791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.2759611791
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.3410836153
Short name T164
Test name
Test status
Simulation time 17980223 ps
CPU time 1.05 seconds
Started Jun 13 01:50:40 PM PDT 24
Finished Jun 13 01:50:43 PM PDT 24
Peak memory 217884 kb
Host smart-5092de46-6949-4245-9354-060da8ccfe37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410836153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3410836153
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.651141294
Short name T531
Test name
Test status
Simulation time 70382895 ps
CPU time 1.65 seconds
Started Jun 13 01:50:42 PM PDT 24
Finished Jun 13 01:50:46 PM PDT 24
Peak memory 218096 kb
Host smart-e781ed7f-2902-444d-a864-6ca554047098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651141294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.651141294
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.2340375819
Short name T445
Test name
Test status
Simulation time 60660349 ps
CPU time 1.08 seconds
Started Jun 13 01:50:42 PM PDT 24
Finished Jun 13 01:50:45 PM PDT 24
Peak memory 217948 kb
Host smart-421b1e31-b07e-4c3b-b6d3-f851ce2efa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340375819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.2340375819
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.3953414036
Short name T51
Test name
Test status
Simulation time 48973418 ps
CPU time 1.28 seconds
Started Jun 13 01:50:38 PM PDT 24
Finished Jun 13 01:50:40 PM PDT 24
Peak memory 224864 kb
Host smart-38a53d09-9b6f-4374-a88c-51b0c1d9e4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953414036 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3953414036
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.195269024
Short name T62
Test name
Test status
Simulation time 99420185 ps
CPU time 1.36 seconds
Started Jun 13 01:50:42 PM PDT 24
Finished Jun 13 01:50:45 PM PDT 24
Peak memory 217832 kb
Host smart-7c8d5d33-860a-470f-bf7e-047408217ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195269024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.195269024
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.140878552
Short name T700
Test name
Test status
Simulation time 76885801 ps
CPU time 1.3 seconds
Started Jun 13 01:50:39 PM PDT 24
Finished Jun 13 01:50:42 PM PDT 24
Peak memory 218396 kb
Host smart-66c0d338-6315-4c19-bfb3-a0445f954e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140878552 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.140878552
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.3334120895
Short name T579
Test name
Test status
Simulation time 34496925 ps
CPU time 1.27 seconds
Started Jun 13 01:50:41 PM PDT 24
Finished Jun 13 01:50:45 PM PDT 24
Peak memory 223344 kb
Host smart-aaf43e9e-8552-47fd-847d-4527af890dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334120895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3334120895
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.57524682
Short name T666
Test name
Test status
Simulation time 67487104 ps
CPU time 1.09 seconds
Started Jun 13 01:50:42 PM PDT 24
Finished Jun 13 01:50:45 PM PDT 24
Peak memory 216756 kb
Host smart-efc0e4bb-7977-45b9-ab9f-ca03e52e9d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57524682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.57524682
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.2738918557
Short name T153
Test name
Test status
Simulation time 148567468 ps
CPU time 1.29 seconds
Started Jun 13 01:50:40 PM PDT 24
Finished Jun 13 01:50:44 PM PDT 24
Peak memory 217992 kb
Host smart-64cf69d6-6e26-46e0-876b-29b5444db8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738918557 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.2738918557
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.3341619579
Short name T830
Test name
Test status
Simulation time 25396476 ps
CPU time 1.32 seconds
Started Jun 13 01:50:42 PM PDT 24
Finished Jun 13 01:50:46 PM PDT 24
Peak memory 229092 kb
Host smart-636d1e41-addc-410e-acdd-ccf3abfd4d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341619579 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3341619579
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1457527847
Short name T388
Test name
Test status
Simulation time 42147117 ps
CPU time 1.66 seconds
Started Jun 13 01:50:40 PM PDT 24
Finished Jun 13 01:50:44 PM PDT 24
Peak memory 217840 kb
Host smart-de1dfa08-3971-44b4-b6da-d10547b9f280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457527847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1457527847
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.2774949657
Short name T721
Test name
Test status
Simulation time 33701205 ps
CPU time 1.21 seconds
Started Jun 13 01:50:42 PM PDT 24
Finished Jun 13 01:50:45 PM PDT 24
Peak memory 217828 kb
Host smart-f0087cb1-7299-436b-9fd6-511a4d001370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774949657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.2774949657
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.365610653
Short name T119
Test name
Test status
Simulation time 36833225 ps
CPU time 1 seconds
Started Jun 13 01:50:40 PM PDT 24
Finished Jun 13 01:50:44 PM PDT 24
Peak memory 219288 kb
Host smart-2c5bf895-1014-473d-ad04-dd025fc0cbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365610653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.365610653
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3534039492
Short name T930
Test name
Test status
Simulation time 133704379 ps
CPU time 1.39 seconds
Started Jun 13 01:50:42 PM PDT 24
Finished Jun 13 01:50:45 PM PDT 24
Peak memory 218192 kb
Host smart-311f5d99-8663-4a9f-906f-76ee96a6fea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534039492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3534039492
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.4117427145
Short name T967
Test name
Test status
Simulation time 72876555 ps
CPU time 1.12 seconds
Started Jun 13 01:50:40 PM PDT 24
Finished Jun 13 01:50:43 PM PDT 24
Peak memory 219304 kb
Host smart-70992ba9-6ea6-4d71-9266-3008f9e04c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117427145 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.4117427145
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.1797833792
Short name T544
Test name
Test status
Simulation time 51118467 ps
CPU time 1.01 seconds
Started Jun 13 01:50:41 PM PDT 24
Finished Jun 13 01:50:44 PM PDT 24
Peak memory 219276 kb
Host smart-a08431db-ad03-4397-a26f-3402e4ce6078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797833792 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1797833792
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.115292347
Short name T991
Test name
Test status
Simulation time 62106352 ps
CPU time 1.05 seconds
Started Jun 13 01:50:40 PM PDT 24
Finished Jun 13 01:50:43 PM PDT 24
Peak memory 216464 kb
Host smart-778e99fd-fe40-4a08-b470-8c11c842837b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115292347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.115292347
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.4128641496
Short name T397
Test name
Test status
Simulation time 67181280 ps
CPU time 0.94 seconds
Started Jun 13 01:50:40 PM PDT 24
Finished Jun 13 01:50:43 PM PDT 24
Peak memory 217616 kb
Host smart-94e905ad-7f46-4d35-9920-d6162a7e014a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128641496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.4128641496
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2570946788
Short name T995
Test name
Test status
Simulation time 121489029 ps
CPU time 1.42 seconds
Started Jun 13 01:50:44 PM PDT 24
Finished Jun 13 01:50:47 PM PDT 24
Peak memory 218208 kb
Host smart-961cae9c-e408-4785-8941-083c951aacfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570946788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2570946788
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.1281550009
Short name T687
Test name
Test status
Simulation time 30384741 ps
CPU time 1.31 seconds
Started Jun 13 01:50:38 PM PDT 24
Finished Jun 13 01:50:40 PM PDT 24
Peak memory 219156 kb
Host smart-2ccbb6ad-ee25-459a-b1a5-7fa176276a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281550009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.1281550009
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.3520940328
Short name T214
Test name
Test status
Simulation time 20241429 ps
CPU time 1.09 seconds
Started Jun 13 01:50:40 PM PDT 24
Finished Jun 13 01:50:44 PM PDT 24
Peak memory 218128 kb
Host smart-c70e0fd4-635e-4cdc-96d8-9811008d1914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520940328 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3520940328
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2397794276
Short name T368
Test name
Test status
Simulation time 55057097 ps
CPU time 1.65 seconds
Started Jun 13 01:50:40 PM PDT 24
Finished Jun 13 01:50:44 PM PDT 24
Peak memory 218108 kb
Host smart-85cc2596-c676-494b-887e-aea49647d010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397794276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2397794276
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.2774509081
Short name T652
Test name
Test status
Simulation time 55339624 ps
CPU time 1.29 seconds
Started Jun 13 01:50:51 PM PDT 24
Finished Jun 13 01:50:54 PM PDT 24
Peak memory 219396 kb
Host smart-75a7cdd6-a07f-466e-95d8-7d6ece0055ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774509081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.2774509081
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.3387002510
Short name T678
Test name
Test status
Simulation time 25274568 ps
CPU time 1.32 seconds
Started Jun 13 01:50:53 PM PDT 24
Finished Jun 13 01:50:57 PM PDT 24
Peak memory 228940 kb
Host smart-a14a4cad-04b7-4871-9ac7-8d8f29d8071c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387002510 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3387002510
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.709397404
Short name T309
Test name
Test status
Simulation time 28674850 ps
CPU time 1.34 seconds
Started Jun 13 01:50:40 PM PDT 24
Finished Jun 13 01:50:44 PM PDT 24
Peak memory 217796 kb
Host smart-be29c7c0-981d-4f2e-8bda-0312f5cf13aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709397404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.709397404
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2381290030
Short name T134
Test name
Test status
Simulation time 65259332 ps
CPU time 1.12 seconds
Started Jun 13 01:49:07 PM PDT 24
Finished Jun 13 01:49:10 PM PDT 24
Peak memory 219208 kb
Host smart-3db6a4d7-ed45-4017-9171-3dc1c0df4382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381290030 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2381290030
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.4125617226
Short name T688
Test name
Test status
Simulation time 46906323 ps
CPU time 0.89 seconds
Started Jun 13 01:49:06 PM PDT 24
Finished Jun 13 01:49:07 PM PDT 24
Peak memory 206096 kb
Host smart-21b1eda4-7dc2-47e9-a22f-3f78e81e4c4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125617226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.4125617226
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3763945304
Short name T741
Test name
Test status
Simulation time 68346037 ps
CPU time 1.41 seconds
Started Jun 13 01:49:06 PM PDT 24
Finished Jun 13 01:49:09 PM PDT 24
Peak memory 216416 kb
Host smart-c4982559-26d3-43f8-91cc-a4a38e939338
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763945304 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3763945304
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.454354510
Short name T136
Test name
Test status
Simulation time 36482008 ps
CPU time 1.54 seconds
Started Jun 13 01:49:06 PM PDT 24
Finished Jun 13 01:49:08 PM PDT 24
Peak memory 225016 kb
Host smart-49412fae-e061-4a2f-a81e-b1d4bcb282fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454354510 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.454354510
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2299692000
Short name T710
Test name
Test status
Simulation time 122464676 ps
CPU time 3.13 seconds
Started Jun 13 01:49:07 PM PDT 24
Finished Jun 13 01:49:12 PM PDT 24
Peak memory 217844 kb
Host smart-528e0e53-80cf-4972-a5ff-0d9ae89e27dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299692000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2299692000
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2473511015
Short name T39
Test name
Test status
Simulation time 21403268 ps
CPU time 1.1 seconds
Started Jun 13 01:49:05 PM PDT 24
Finished Jun 13 01:49:07 PM PDT 24
Peak memory 215020 kb
Host smart-0b937360-6aa0-4178-9e7e-9ffe9a48ce6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473511015 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2473511015
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.3281021739
Short name T339
Test name
Test status
Simulation time 49665462 ps
CPU time 1 seconds
Started Jun 13 01:49:04 PM PDT 24
Finished Jun 13 01:49:06 PM PDT 24
Peak memory 214612 kb
Host smart-9655d101-b929-454f-9a71-e11604ff6718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281021739 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3281021739
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.4107215442
Short name T349
Test name
Test status
Simulation time 203081680 ps
CPU time 4.11 seconds
Started Jun 13 01:49:06 PM PDT 24
Finished Jun 13 01:49:12 PM PDT 24
Peak memory 214608 kb
Host smart-8cbfd710-4ebf-4443-a148-aff0186f08ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107215442 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.4107215442
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2402369614
Short name T229
Test name
Test status
Simulation time 93483949599 ps
CPU time 1077.23 seconds
Started Jun 13 01:49:07 PM PDT 24
Finished Jun 13 02:07:06 PM PDT 24
Peak memory 221616 kb
Host smart-92507271-5087-476f-a789-c2bc1e5bad17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402369614 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2402369614
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.3765554419
Short name T147
Test name
Test status
Simulation time 48893575 ps
CPU time 1.27 seconds
Started Jun 13 01:51:01 PM PDT 24
Finished Jun 13 01:51:04 PM PDT 24
Peak memory 219008 kb
Host smart-39929855-4b3e-4f71-9735-bb0d4778332b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765554419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.3765554419
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.747690193
Short name T864
Test name
Test status
Simulation time 23021472 ps
CPU time 1.18 seconds
Started Jun 13 01:50:53 PM PDT 24
Finished Jun 13 01:50:56 PM PDT 24
Peak memory 219280 kb
Host smart-a2081dce-d72a-46b8-ab68-711e7b4554ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747690193 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.747690193
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.613928406
Short name T374
Test name
Test status
Simulation time 84686686 ps
CPU time 1.22 seconds
Started Jun 13 01:50:52 PM PDT 24
Finished Jun 13 01:50:55 PM PDT 24
Peak memory 218132 kb
Host smart-970aa36d-d68a-4d0f-8a54-e6495d3f61c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613928406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.613928406
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.151110041
Short name T245
Test name
Test status
Simulation time 86354824 ps
CPU time 1.21 seconds
Started Jun 13 01:50:50 PM PDT 24
Finished Jun 13 01:50:52 PM PDT 24
Peak memory 218120 kb
Host smart-34b5da47-73cf-44f8-a6e1-d7033726a1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151110041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.151110041
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1058233118
Short name T742
Test name
Test status
Simulation time 19538241 ps
CPU time 1.22 seconds
Started Jun 13 01:50:54 PM PDT 24
Finished Jun 13 01:50:58 PM PDT 24
Peak memory 223380 kb
Host smart-320c72c7-74ec-45b3-90a3-47e9c45eb9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058233118 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1058233118
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1182635126
Short name T643
Test name
Test status
Simulation time 144754230 ps
CPU time 1.5 seconds
Started Jun 13 01:50:52 PM PDT 24
Finished Jun 13 01:50:55 PM PDT 24
Peak memory 218840 kb
Host smart-9751c301-4fe0-408c-a8e1-1db6a10277ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182635126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1182635126
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.2134200321
Short name T889
Test name
Test status
Simulation time 40765576 ps
CPU time 1.12 seconds
Started Jun 13 01:50:52 PM PDT 24
Finished Jun 13 01:50:54 PM PDT 24
Peak memory 218128 kb
Host smart-c70ec90a-c3b9-45d6-a380-20e20f7d2640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134200321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.2134200321
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.2198411104
Short name T148
Test name
Test status
Simulation time 31419483 ps
CPU time 1.18 seconds
Started Jun 13 01:50:52 PM PDT 24
Finished Jun 13 01:50:55 PM PDT 24
Peak memory 229032 kb
Host smart-55f8d7fd-1040-4942-8af8-e8e59ceba6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198411104 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2198411104
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1348390136
Short name T75
Test name
Test status
Simulation time 46953926 ps
CPU time 1.71 seconds
Started Jun 13 01:50:52 PM PDT 24
Finished Jun 13 01:50:55 PM PDT 24
Peak memory 217716 kb
Host smart-cf015b06-e5ce-415f-805e-2958a9a7d094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348390136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1348390136
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.1609016385
Short name T684
Test name
Test status
Simulation time 41528988 ps
CPU time 1.14 seconds
Started Jun 13 01:50:52 PM PDT 24
Finished Jun 13 01:50:54 PM PDT 24
Peak memory 219224 kb
Host smart-9bb13a38-4d6e-44c7-8eff-64e0b70ac95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609016385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.1609016385
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.3437142621
Short name T60
Test name
Test status
Simulation time 24774640 ps
CPU time 0.93 seconds
Started Jun 13 01:50:54 PM PDT 24
Finished Jun 13 01:50:58 PM PDT 24
Peak memory 217748 kb
Host smart-4b3af8d0-c720-4d58-9935-d5f9f0de3436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437142621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3437142621
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1553521149
Short name T398
Test name
Test status
Simulation time 38786361 ps
CPU time 1.56 seconds
Started Jun 13 01:50:52 PM PDT 24
Finished Jun 13 01:50:56 PM PDT 24
Peak memory 216756 kb
Host smart-da342570-ae7b-45a0-bc03-68d8df054405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553521149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1553521149
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.2640548290
Short name T988
Test name
Test status
Simulation time 26685111 ps
CPU time 1.24 seconds
Started Jun 13 01:50:50 PM PDT 24
Finished Jun 13 01:50:53 PM PDT 24
Peak memory 219964 kb
Host smart-72b17237-58c4-469f-ac55-7346b124ccad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640548290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.2640548290
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.2393592615
Short name T468
Test name
Test status
Simulation time 29588213 ps
CPU time 0.96 seconds
Started Jun 13 01:50:53 PM PDT 24
Finished Jun 13 01:50:56 PM PDT 24
Peak memory 223192 kb
Host smart-73f4dc3f-0dba-4222-865b-4ad01841b4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393592615 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2393592615
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1188545173
Short name T798
Test name
Test status
Simulation time 72864946 ps
CPU time 1.05 seconds
Started Jun 13 01:50:56 PM PDT 24
Finished Jun 13 01:50:59 PM PDT 24
Peak memory 216460 kb
Host smart-5f1fd0a1-df1a-4618-8168-73d3df432230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188545173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1188545173
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.988585983
Short name T5
Test name
Test status
Simulation time 18377705 ps
CPU time 1.18 seconds
Started Jun 13 01:50:54 PM PDT 24
Finished Jun 13 01:50:58 PM PDT 24
Peak memory 223364 kb
Host smart-3b36e00c-ca72-4c21-a9f4-fbfb329211cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988585983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.988585983
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1204517549
Short name T24
Test name
Test status
Simulation time 110339587 ps
CPU time 1.13 seconds
Started Jun 13 01:50:51 PM PDT 24
Finished Jun 13 01:50:54 PM PDT 24
Peak memory 219172 kb
Host smart-8f1020e6-7636-4878-82b9-0618b9e0011a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204517549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1204517549
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.333103568
Short name T735
Test name
Test status
Simulation time 70681395 ps
CPU time 1.12 seconds
Started Jun 13 01:50:50 PM PDT 24
Finished Jun 13 01:50:53 PM PDT 24
Peak memory 217800 kb
Host smart-b1ba81ce-59af-483a-aad0-4984e6714225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333103568 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.333103568
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1535967317
Short name T977
Test name
Test status
Simulation time 27712074 ps
CPU time 0.98 seconds
Started Jun 13 01:50:50 PM PDT 24
Finished Jun 13 01:50:52 PM PDT 24
Peak memory 219128 kb
Host smart-5ebc6776-f8cb-41db-8e07-62fe8a503c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535967317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1535967317
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1717814340
Short name T400
Test name
Test status
Simulation time 352562917 ps
CPU time 3.39 seconds
Started Jun 13 01:50:50 PM PDT 24
Finished Jun 13 01:50:55 PM PDT 24
Peak memory 219548 kb
Host smart-3db284fa-544c-4a61-be4c-0c2d8b627546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717814340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1717814340
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.3699694466
Short name T745
Test name
Test status
Simulation time 47845672 ps
CPU time 1.12 seconds
Started Jun 13 01:50:50 PM PDT 24
Finished Jun 13 01:50:52 PM PDT 24
Peak memory 218260 kb
Host smart-5a3479ec-b495-4b1e-a485-f16aa959f8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699694466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.3699694466
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1261813248
Short name T187
Test name
Test status
Simulation time 25123888 ps
CPU time 1.09 seconds
Started Jun 13 01:50:53 PM PDT 24
Finished Jun 13 01:50:57 PM PDT 24
Peak memory 223444 kb
Host smart-7150c119-5761-405b-8935-6768d9c087f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261813248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1261813248
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1011357420
Short name T424
Test name
Test status
Simulation time 33748313 ps
CPU time 1.45 seconds
Started Jun 13 01:50:52 PM PDT 24
Finished Jun 13 01:50:55 PM PDT 24
Peak memory 217672 kb
Host smart-bdd94a53-6726-4c0c-b75d-68049e05956e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011357420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1011357420
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.2195066934
Short name T703
Test name
Test status
Simulation time 282172721 ps
CPU time 1.35 seconds
Started Jun 13 01:50:50 PM PDT 24
Finished Jun 13 01:50:52 PM PDT 24
Peak memory 219088 kb
Host smart-4a50ee8d-648e-4dbe-bb12-911d109fcba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195066934 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.2195066934
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.1740377073
Short name T141
Test name
Test status
Simulation time 36163111 ps
CPU time 0.93 seconds
Started Jun 13 01:50:53 PM PDT 24
Finished Jun 13 01:50:56 PM PDT 24
Peak memory 219124 kb
Host smart-3ee73fac-0bce-428a-b4f7-58e85f7a70b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740377073 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1740377073
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3958644512
Short name T372
Test name
Test status
Simulation time 103446690 ps
CPU time 1.09 seconds
Started Jun 13 01:50:51 PM PDT 24
Finished Jun 13 01:50:54 PM PDT 24
Peak memory 216524 kb
Host smart-adf909ec-467f-4e6c-9869-c145a0fe9d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958644512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3958644512
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.3662847438
Short name T732
Test name
Test status
Simulation time 24212944 ps
CPU time 1.11 seconds
Started Jun 13 01:50:55 PM PDT 24
Finished Jun 13 01:50:59 PM PDT 24
Peak memory 218844 kb
Host smart-ef322570-413a-4232-bdc0-87da95685c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662847438 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.3662847438
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.315984600
Short name T659
Test name
Test status
Simulation time 35279665 ps
CPU time 1.16 seconds
Started Jun 13 01:50:53 PM PDT 24
Finished Jun 13 01:50:56 PM PDT 24
Peak memory 223368 kb
Host smart-97967ebd-dc98-4b39-8cdf-43673fb8837a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315984600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.315984600
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.3492102295
Short name T440
Test name
Test status
Simulation time 75710056 ps
CPU time 1.61 seconds
Started Jun 13 01:50:50 PM PDT 24
Finished Jun 13 01:50:52 PM PDT 24
Peak memory 219232 kb
Host smart-e24819df-4671-4e9b-9dae-a5236e6ace59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492102295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3492102295
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2072494592
Short name T958
Test name
Test status
Simulation time 24352068 ps
CPU time 1.17 seconds
Started Jun 13 01:49:06 PM PDT 24
Finished Jun 13 01:49:09 PM PDT 24
Peak memory 220104 kb
Host smart-205b2feb-5a50-40db-a49e-d26d140bc642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072494592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2072494592
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1968163352
Short name T459
Test name
Test status
Simulation time 15090905 ps
CPU time 0.9 seconds
Started Jun 13 01:49:06 PM PDT 24
Finished Jun 13 01:49:09 PM PDT 24
Peak memory 206068 kb
Host smart-a264ac36-5708-4144-b7b6-2e34a0cef7a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968163352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1968163352
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.297918383
Short name T203
Test name
Test status
Simulation time 15116964 ps
CPU time 0.9 seconds
Started Jun 13 01:49:07 PM PDT 24
Finished Jun 13 01:49:10 PM PDT 24
Peak memory 215676 kb
Host smart-02265234-58cf-451e-a3d8-b7dc97dae123
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297918383 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.297918383
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1971345525
Short name T633
Test name
Test status
Simulation time 389735199 ps
CPU time 1.25 seconds
Started Jun 13 01:49:07 PM PDT 24
Finished Jun 13 01:49:10 PM PDT 24
Peak memory 215012 kb
Host smart-e1645743-9453-407e-b8c1-774e1733fcc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971345525 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1971345525
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3277193308
Short name T548
Test name
Test status
Simulation time 33886258 ps
CPU time 0.94 seconds
Started Jun 13 01:49:08 PM PDT 24
Finished Jun 13 01:49:11 PM PDT 24
Peak memory 218696 kb
Host smart-c2dae7fa-c4c2-4ffb-bc86-698629e4bbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277193308 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3277193308
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1644267466
Short name T955
Test name
Test status
Simulation time 37296189 ps
CPU time 1.7 seconds
Started Jun 13 01:49:05 PM PDT 24
Finished Jun 13 01:49:08 PM PDT 24
Peak memory 216660 kb
Host smart-98c5373a-832c-4607-a22b-c815c7272e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644267466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1644267466
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3096213199
Short name T106
Test name
Test status
Simulation time 31429344 ps
CPU time 0.89 seconds
Started Jun 13 01:49:06 PM PDT 24
Finished Jun 13 01:49:09 PM PDT 24
Peak memory 215044 kb
Host smart-649d1549-7899-4301-8d70-dec805160dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096213199 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3096213199
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.1993329412
Short name T293
Test name
Test status
Simulation time 25621718 ps
CPU time 0.94 seconds
Started Jun 13 01:49:10 PM PDT 24
Finished Jun 13 01:49:12 PM PDT 24
Peak memory 206424 kb
Host smart-a5a5e57a-7fb6-4d0b-bd71-02a2c85f2259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993329412 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1993329412
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.552326278
Short name T743
Test name
Test status
Simulation time 35419911 ps
CPU time 0.98 seconds
Started Jun 13 01:49:06 PM PDT 24
Finished Jun 13 01:49:08 PM PDT 24
Peak memory 214624 kb
Host smart-60cbe717-ef67-4774-83d8-325eca9e91d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552326278 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.552326278
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1120768409
Short name T610
Test name
Test status
Simulation time 434904535 ps
CPU time 3.01 seconds
Started Jun 13 01:49:06 PM PDT 24
Finished Jun 13 01:49:10 PM PDT 24
Peak memory 214648 kb
Host smart-8e8a1cef-847c-4c1e-a206-4ddbf7be3ab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120768409 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1120768409
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1805035907
Short name T225
Test name
Test status
Simulation time 50939295455 ps
CPU time 648.59 seconds
Started Jun 13 01:49:09 PM PDT 24
Finished Jun 13 01:59:59 PM PDT 24
Peak memory 218364 kb
Host smart-eb6cb3ed-330c-4289-923d-74b0dde91d12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805035907 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1805035907
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.4086703528
Short name T725
Test name
Test status
Simulation time 22259339 ps
CPU time 1.14 seconds
Started Jun 13 01:50:53 PM PDT 24
Finished Jun 13 01:50:56 PM PDT 24
Peak memory 220224 kb
Host smart-657d60a6-c5a2-4517-bb10-5506a6103411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086703528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.4086703528
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.1614811157
Short name T149
Test name
Test status
Simulation time 25121728 ps
CPU time 1.16 seconds
Started Jun 13 01:50:52 PM PDT 24
Finished Jun 13 01:50:55 PM PDT 24
Peak memory 219852 kb
Host smart-3091b160-946b-4a2c-bdee-ab764acf8eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614811157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1614811157
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.969873468
Short name T635
Test name
Test status
Simulation time 42941988 ps
CPU time 1.19 seconds
Started Jun 13 01:50:54 PM PDT 24
Finished Jun 13 01:50:58 PM PDT 24
Peak memory 218732 kb
Host smart-1038cabf-bb81-410e-8d00-66027493e368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969873468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.969873468
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2636921840
Short name T984
Test name
Test status
Simulation time 34982560 ps
CPU time 1.05 seconds
Started Jun 13 01:50:52 PM PDT 24
Finished Jun 13 01:50:55 PM PDT 24
Peak memory 219328 kb
Host smart-e51822d3-c488-4c25-88b8-d2fd0822dae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636921840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2636921840
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.3914460142
Short name T565
Test name
Test status
Simulation time 30656742 ps
CPU time 0.86 seconds
Started Jun 13 01:50:52 PM PDT 24
Finished Jun 13 01:50:55 PM PDT 24
Peak memory 218488 kb
Host smart-f3af2b22-02b1-4846-a67b-8f8fc6f8233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914460142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3914460142
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.354671967
Short name T595
Test name
Test status
Simulation time 46777581 ps
CPU time 1.55 seconds
Started Jun 13 01:50:55 PM PDT 24
Finished Jun 13 01:50:59 PM PDT 24
Peak memory 218124 kb
Host smart-b279dcdf-710e-45b1-8e59-36562a0f219b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354671967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.354671967
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.3356995018
Short name T891
Test name
Test status
Simulation time 265506102 ps
CPU time 1.28 seconds
Started Jun 13 01:50:54 PM PDT 24
Finished Jun 13 01:50:58 PM PDT 24
Peak memory 217908 kb
Host smart-f4f823d2-0b81-4d1b-a561-354af71290f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356995018 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.3356995018
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.2664461523
Short name T518
Test name
Test status
Simulation time 28594833 ps
CPU time 0.87 seconds
Started Jun 13 01:50:54 PM PDT 24
Finished Jun 13 01:50:57 PM PDT 24
Peak memory 217912 kb
Host smart-63008c6f-c890-49eb-89e9-5fbd583def27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664461523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2664461523
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.838083247
Short name T408
Test name
Test status
Simulation time 53676182 ps
CPU time 1.28 seconds
Started Jun 13 01:50:53 PM PDT 24
Finished Jun 13 01:50:56 PM PDT 24
Peak memory 216420 kb
Host smart-8677ed1a-d209-431e-a0f1-91ec4080e00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838083247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.838083247
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.821494288
Short name T244
Test name
Test status
Simulation time 174435510 ps
CPU time 1.4 seconds
Started Jun 13 01:50:56 PM PDT 24
Finished Jun 13 01:51:00 PM PDT 24
Peak memory 215036 kb
Host smart-45685812-84d5-43ca-b2d1-1541774894dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821494288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.821494288
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.334204798
Short name T392
Test name
Test status
Simulation time 25240398 ps
CPU time 1.21 seconds
Started Jun 13 01:50:58 PM PDT 24
Finished Jun 13 01:51:02 PM PDT 24
Peak memory 217816 kb
Host smart-0d56f71c-3a60-46cc-8b31-21ca1a3e222b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334204798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.334204798
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3711516103
Short name T926
Test name
Test status
Simulation time 47346144 ps
CPU time 1.25 seconds
Started Jun 13 01:50:54 PM PDT 24
Finished Jun 13 01:50:58 PM PDT 24
Peak memory 216576 kb
Host smart-555cad42-62ef-4579-b0ab-2635eb16d2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711516103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3711516103
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.2128268659
Short name T569
Test name
Test status
Simulation time 48130424 ps
CPU time 1.2 seconds
Started Jun 13 01:50:55 PM PDT 24
Finished Jun 13 01:50:59 PM PDT 24
Peak memory 219088 kb
Host smart-34fae9da-fb82-43a8-84cc-2fc81f5de98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128268659 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.2128268659
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2498049509
Short name T574
Test name
Test status
Simulation time 103974303 ps
CPU time 1.36 seconds
Started Jun 13 01:50:54 PM PDT 24
Finished Jun 13 01:50:58 PM PDT 24
Peak memory 225092 kb
Host smart-4f9706c3-67f8-49fa-aa74-8bd323eb6f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498049509 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2498049509
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3603259191
Short name T838
Test name
Test status
Simulation time 92482796 ps
CPU time 1.25 seconds
Started Jun 13 01:50:52 PM PDT 24
Finished Jun 13 01:50:55 PM PDT 24
Peak memory 216600 kb
Host smart-4ce1feba-b423-465c-9221-23157ad735b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603259191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3603259191
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.1618363798
Short name T270
Test name
Test status
Simulation time 30016851 ps
CPU time 1.31 seconds
Started Jun 13 01:50:54 PM PDT 24
Finished Jun 13 01:50:58 PM PDT 24
Peak memory 220092 kb
Host smart-3aa0edaf-7388-4b46-a4c5-8f91753e137e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618363798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.1618363798
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.1757458766
Short name T671
Test name
Test status
Simulation time 49977320 ps
CPU time 1.09 seconds
Started Jun 13 01:50:55 PM PDT 24
Finished Jun 13 01:50:59 PM PDT 24
Peak memory 229040 kb
Host smart-3f5413f4-346a-4d64-a5ba-8bb8c93f1634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757458766 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1757458766
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2373718768
Short name T415
Test name
Test status
Simulation time 61635956 ps
CPU time 2.25 seconds
Started Jun 13 01:50:55 PM PDT 24
Finished Jun 13 01:51:00 PM PDT 24
Peak memory 218820 kb
Host smart-5716bc89-8e98-4aad-a97c-bc5f81659e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373718768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2373718768
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.187340765
Short name T167
Test name
Test status
Simulation time 22965718 ps
CPU time 1.16 seconds
Started Jun 13 01:50:57 PM PDT 24
Finished Jun 13 01:51:01 PM PDT 24
Peak memory 217888 kb
Host smart-bd7d2818-3dce-4158-a7b3-840f6be29c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187340765 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.187340765
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.1081978045
Short name T912
Test name
Test status
Simulation time 19157083 ps
CPU time 1.1 seconds
Started Jun 13 01:50:55 PM PDT 24
Finished Jun 13 01:50:58 PM PDT 24
Peak memory 218288 kb
Host smart-8a24a8e0-65d4-4b20-95bc-2f7b03740673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081978045 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1081978045
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.622035488
Short name T662
Test name
Test status
Simulation time 86628467 ps
CPU time 2.48 seconds
Started Jun 13 01:50:54 PM PDT 24
Finished Jun 13 01:50:59 PM PDT 24
Peak memory 216848 kb
Host smart-104ca20b-a80f-4fae-8eea-78005ab8a8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622035488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.622035488
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.469357057
Short name T467
Test name
Test status
Simulation time 38957288 ps
CPU time 1.16 seconds
Started Jun 13 01:50:58 PM PDT 24
Finished Jun 13 01:51:02 PM PDT 24
Peak memory 217716 kb
Host smart-eb73a567-27e6-4943-9a54-68123c73c25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469357057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.469357057
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.2185435982
Short name T660
Test name
Test status
Simulation time 27689267 ps
CPU time 0.87 seconds
Started Jun 13 01:50:55 PM PDT 24
Finished Jun 13 01:50:58 PM PDT 24
Peak memory 217800 kb
Host smart-e7fc7ef3-08e6-4f5f-a330-9dada1619430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185435982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2185435982
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2119386091
Short name T305
Test name
Test status
Simulation time 71868902 ps
CPU time 1.5 seconds
Started Jun 13 01:50:53 PM PDT 24
Finished Jun 13 01:50:56 PM PDT 24
Peak memory 218044 kb
Host smart-0f6083d9-2af6-4646-b0d1-9e9d396feaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119386091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2119386091
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.4233222328
Short name T502
Test name
Test status
Simulation time 72044807 ps
CPU time 1.23 seconds
Started Jun 13 01:50:55 PM PDT 24
Finished Jun 13 01:50:58 PM PDT 24
Peak memory 219504 kb
Host smart-f9b41029-ab94-4dad-8493-1e977db290fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233222328 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.4233222328
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.4181109375
Short name T209
Test name
Test status
Simulation time 20570477 ps
CPU time 1.28 seconds
Started Jun 13 01:50:56 PM PDT 24
Finished Jun 13 01:50:59 PM PDT 24
Peak memory 223368 kb
Host smart-85565203-6d5a-4c17-9848-edf91e413106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181109375 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.4181109375
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2764373179
Short name T465
Test name
Test status
Simulation time 81796534 ps
CPU time 1.33 seconds
Started Jun 13 01:50:58 PM PDT 24
Finished Jun 13 01:51:01 PM PDT 24
Peak memory 217020 kb
Host smart-74839869-7d67-419e-b6e1-d317eab717c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764373179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2764373179
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.1417799959
Short name T682
Test name
Test status
Simulation time 84934861 ps
CPU time 1.24 seconds
Started Jun 13 01:50:54 PM PDT 24
Finished Jun 13 01:50:58 PM PDT 24
Peak memory 219144 kb
Host smart-513dc214-e7ca-41f7-a932-5d5b3413b659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417799959 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1417799959
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.3552991907
Short name T837
Test name
Test status
Simulation time 24049222 ps
CPU time 1.28 seconds
Started Jun 13 01:50:55 PM PDT 24
Finished Jun 13 01:50:58 PM PDT 24
Peak memory 223396 kb
Host smart-4055eaef-4cda-47db-833f-4923d3831c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552991907 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3552991907
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2302056573
Short name T301
Test name
Test status
Simulation time 45367637 ps
CPU time 1.51 seconds
Started Jun 13 01:50:55 PM PDT 24
Finished Jun 13 01:50:59 PM PDT 24
Peak memory 217812 kb
Host smart-2d15682f-5da1-4406-87b8-3eef9308237d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302056573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2302056573
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1880369390
Short name T673
Test name
Test status
Simulation time 92681637 ps
CPU time 1.2 seconds
Started Jun 13 01:49:13 PM PDT 24
Finished Jun 13 01:49:16 PM PDT 24
Peak memory 215092 kb
Host smart-718cb8b2-9bc6-4c4b-b390-bd02d22a21a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880369390 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1880369390
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1955826643
Short name T753
Test name
Test status
Simulation time 29297085 ps
CPU time 0.93 seconds
Started Jun 13 01:49:14 PM PDT 24
Finished Jun 13 01:49:16 PM PDT 24
Peak memory 206100 kb
Host smart-85444d1d-fba9-460d-8088-49c6651eaf93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955826643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1955826643
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3086395072
Short name T619
Test name
Test status
Simulation time 26807280 ps
CPU time 0.85 seconds
Started Jun 13 01:49:10 PM PDT 24
Finished Jun 13 01:49:12 PM PDT 24
Peak memory 215668 kb
Host smart-b0d2c7a1-5b2b-4774-935c-ea768da4231a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086395072 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3086395072
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3277515922
Short name T860
Test name
Test status
Simulation time 39600074 ps
CPU time 1.14 seconds
Started Jun 13 01:49:14 PM PDT 24
Finished Jun 13 01:49:16 PM PDT 24
Peak memory 217528 kb
Host smart-ef0fda8b-6f03-4f7f-ba4b-f627db05b76d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277515922 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3277515922
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3408265384
Short name T217
Test name
Test status
Simulation time 33381234 ps
CPU time 0.91 seconds
Started Jun 13 01:49:15 PM PDT 24
Finished Jun 13 01:49:17 PM PDT 24
Peak memory 218780 kb
Host smart-6f289d94-1438-4084-a999-58b30a5189a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408265384 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3408265384
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.4274841032
Short name T525
Test name
Test status
Simulation time 59954147 ps
CPU time 1.33 seconds
Started Jun 13 01:49:06 PM PDT 24
Finished Jun 13 01:49:09 PM PDT 24
Peak memory 217720 kb
Host smart-e633076e-63eb-497a-b192-ec4c28e2287d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274841032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.4274841032
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3461284675
Short name T877
Test name
Test status
Simulation time 24848249 ps
CPU time 1.08 seconds
Started Jun 13 01:49:12 PM PDT 24
Finished Jun 13 01:49:15 PM PDT 24
Peak memory 214976 kb
Host smart-df336a06-1cd1-4cb3-8c34-3e10b3e1b0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461284675 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3461284675
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1932232754
Short name T31
Test name
Test status
Simulation time 49086654 ps
CPU time 1 seconds
Started Jun 13 01:49:09 PM PDT 24
Finished Jun 13 01:49:12 PM PDT 24
Peak memory 206428 kb
Host smart-532423bf-85b2-4c16-88e8-46c20aabf9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932232754 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1932232754
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2545922372
Short name T470
Test name
Test status
Simulation time 57439689 ps
CPU time 0.97 seconds
Started Jun 13 01:49:08 PM PDT 24
Finished Jun 13 01:49:11 PM PDT 24
Peak memory 214628 kb
Host smart-514abff0-8882-4349-b6ff-8ecaf3236aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545922372 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2545922372
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.544577587
Short name T607
Test name
Test status
Simulation time 140373644 ps
CPU time 3.23 seconds
Started Jun 13 01:49:06 PM PDT 24
Finished Jun 13 01:49:11 PM PDT 24
Peak memory 219416 kb
Host smart-8defc1b5-b490-40b1-bdc2-c2c4c03a85ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544577587 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.544577587
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.83847513
Short name T603
Test name
Test status
Simulation time 457865476376 ps
CPU time 1108.28 seconds
Started Jun 13 01:49:06 PM PDT 24
Finished Jun 13 02:07:36 PM PDT 24
Peak memory 221332 kb
Host smart-ceaa690d-3b7f-4b11-a3c6-57ec6984c6bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83847513 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.83847513
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.344285670
Short name T431
Test name
Test status
Simulation time 64874390 ps
CPU time 1.13 seconds
Started Jun 13 01:50:57 PM PDT 24
Finished Jun 13 01:51:00 PM PDT 24
Peak memory 218168 kb
Host smart-94590546-f99c-43ac-97e3-d04ccdbd3037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344285670 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.344285670
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_genbits.955790368
Short name T740
Test name
Test status
Simulation time 9100807434 ps
CPU time 94.32 seconds
Started Jun 13 01:50:53 PM PDT 24
Finished Jun 13 01:52:30 PM PDT 24
Peak memory 219216 kb
Host smart-50eb1232-c259-43a8-a722-4911507c0f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955790368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.955790368
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.678726745
Short name T812
Test name
Test status
Simulation time 35798089 ps
CPU time 1.16 seconds
Started Jun 13 01:50:56 PM PDT 24
Finished Jun 13 01:50:59 PM PDT 24
Peak memory 218052 kb
Host smart-e4fbd19e-0667-4cf2-82a2-9949ceeb97c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678726745 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.678726745
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.4005523118
Short name T163
Test name
Test status
Simulation time 19873219 ps
CPU time 1.03 seconds
Started Jun 13 01:50:57 PM PDT 24
Finished Jun 13 01:51:00 PM PDT 24
Peak memory 217936 kb
Host smart-f3ca20d5-765d-4a8f-aaed-c77edfc5e9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005523118 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.4005523118
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3821537890
Short name T235
Test name
Test status
Simulation time 43873889 ps
CPU time 1.67 seconds
Started Jun 13 01:50:57 PM PDT 24
Finished Jun 13 01:51:01 PM PDT 24
Peak memory 217996 kb
Host smart-3b77e2a3-9728-462b-92e3-5f8fbe2731cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821537890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3821537890
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.4242298242
Short name T417
Test name
Test status
Simulation time 27053247 ps
CPU time 1.29 seconds
Started Jun 13 01:51:00 PM PDT 24
Finished Jun 13 01:51:03 PM PDT 24
Peak memory 220220 kb
Host smart-444d18aa-0207-47e4-b540-8bf1fb02f2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242298242 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.4242298242
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.2333621954
Short name T129
Test name
Test status
Simulation time 31083341 ps
CPU time 1.1 seconds
Started Jun 13 01:51:01 PM PDT 24
Finished Jun 13 01:51:04 PM PDT 24
Peak memory 219204 kb
Host smart-c2efead5-9be9-4d51-b5c9-de7d4a597ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333621954 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2333621954
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.4117160009
Short name T651
Test name
Test status
Simulation time 131736915 ps
CPU time 1.37 seconds
Started Jun 13 01:51:06 PM PDT 24
Finished Jun 13 01:51:09 PM PDT 24
Peak memory 218092 kb
Host smart-48e7957d-d0c7-4d02-925d-c9333339fc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117160009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.4117160009
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.2255896504
Short name T989
Test name
Test status
Simulation time 25496117 ps
CPU time 1.2 seconds
Started Jun 13 01:50:59 PM PDT 24
Finished Jun 13 01:51:02 PM PDT 24
Peak memory 219012 kb
Host smart-9e623a65-343f-4d03-bb1d-fb4e9325b659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255896504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.2255896504
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.602043962
Short name T79
Test name
Test status
Simulation time 64145314 ps
CPU time 0.87 seconds
Started Jun 13 01:51:00 PM PDT 24
Finished Jun 13 01:51:03 PM PDT 24
Peak memory 218544 kb
Host smart-b54a8199-57d5-438c-9841-17c29efc67f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602043962 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.602043962
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3386028715
Short name T457
Test name
Test status
Simulation time 52172055 ps
CPU time 1.5 seconds
Started Jun 13 01:51:00 PM PDT 24
Finished Jun 13 01:51:03 PM PDT 24
Peak memory 217872 kb
Host smart-8efba155-680e-4fab-8ac6-7458bda53fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386028715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3386028715
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.2882737252
Short name T181
Test name
Test status
Simulation time 27254627 ps
CPU time 1.23 seconds
Started Jun 13 01:51:06 PM PDT 24
Finished Jun 13 01:51:09 PM PDT 24
Peak memory 215076 kb
Host smart-d39e8fe7-f78d-498c-8354-1599bd16c539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882737252 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2882737252
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.1504891446
Short name T763
Test name
Test status
Simulation time 24169922 ps
CPU time 1.1 seconds
Started Jun 13 01:50:57 PM PDT 24
Finished Jun 13 01:51:00 PM PDT 24
Peak memory 223352 kb
Host smart-ab4268b9-bcc0-431e-b40d-dd56d4087552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504891446 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1504891446
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.4013824233
Short name T600
Test name
Test status
Simulation time 56590929 ps
CPU time 1.17 seconds
Started Jun 13 01:51:06 PM PDT 24
Finished Jun 13 01:51:09 PM PDT 24
Peak memory 216788 kb
Host smart-9dbbb56d-cb01-4439-a29f-cc59ea5c16f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013824233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.4013824233
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.3765280667
Short name T274
Test name
Test status
Simulation time 71988514 ps
CPU time 1.24 seconds
Started Jun 13 01:50:59 PM PDT 24
Finished Jun 13 01:51:03 PM PDT 24
Peak memory 218244 kb
Host smart-18d01841-f4d5-462d-8fc3-90a45f81de99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765280667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.3765280667
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.2569267485
Short name T95
Test name
Test status
Simulation time 200038988 ps
CPU time 1.19 seconds
Started Jun 13 01:50:59 PM PDT 24
Finished Jun 13 01:51:03 PM PDT 24
Peak memory 219280 kb
Host smart-eb327432-36ae-4358-bd95-7f441982584d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569267485 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2569267485
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1937340510
Short name T521
Test name
Test status
Simulation time 150532758 ps
CPU time 3.34 seconds
Started Jun 13 01:50:58 PM PDT 24
Finished Jun 13 01:51:04 PM PDT 24
Peak memory 219548 kb
Host smart-0e89e5f6-321e-4182-aca0-c8ccfbbce04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937340510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1937340510
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.1206969872
Short name T829
Test name
Test status
Simulation time 133347434 ps
CPU time 1.16 seconds
Started Jun 13 01:50:59 PM PDT 24
Finished Jun 13 01:51:03 PM PDT 24
Peak memory 217904 kb
Host smart-5e767129-bf9d-4dd5-8daf-a09d9a33240f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206969872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1206969872
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.3340214286
Short name T492
Test name
Test status
Simulation time 21986060 ps
CPU time 1.06 seconds
Started Jun 13 01:50:58 PM PDT 24
Finished Jun 13 01:51:01 PM PDT 24
Peak memory 218156 kb
Host smart-0ea81d66-503f-4d71-ad2d-c31fade52449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340214286 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3340214286
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.735034723
Short name T536
Test name
Test status
Simulation time 169426647 ps
CPU time 1.05 seconds
Started Jun 13 01:50:57 PM PDT 24
Finished Jun 13 01:51:01 PM PDT 24
Peak memory 214688 kb
Host smart-42fba8ef-3a63-4f54-80d4-c1baadfe2dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735034723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.735034723
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.4172015341
Short name T876
Test name
Test status
Simulation time 21587216 ps
CPU time 1.18 seconds
Started Jun 13 01:51:01 PM PDT 24
Finished Jun 13 01:51:04 PM PDT 24
Peak memory 217944 kb
Host smart-0c3dcc72-23f9-481e-8b0f-5af430166cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172015341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.4172015341
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.1343177938
Short name T885
Test name
Test status
Simulation time 19143312 ps
CPU time 1.22 seconds
Started Jun 13 01:50:59 PM PDT 24
Finished Jun 13 01:51:03 PM PDT 24
Peak memory 223300 kb
Host smart-ea0e94df-ff6d-4542-9c30-36ae4d26f53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343177938 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1343177938
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.1913982822
Short name T656
Test name
Test status
Simulation time 33749403 ps
CPU time 1.38 seconds
Started Jun 13 01:51:00 PM PDT 24
Finished Jun 13 01:51:03 PM PDT 24
Peak memory 219252 kb
Host smart-f6662b53-f704-4a14-be6e-b277f1bf1037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913982822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1913982822
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.1617353676
Short name T66
Test name
Test status
Simulation time 23948490 ps
CPU time 1.18 seconds
Started Jun 13 01:51:01 PM PDT 24
Finished Jun 13 01:51:04 PM PDT 24
Peak memory 217752 kb
Host smart-1b061995-4985-43d6-ad92-c209c8d2cf96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617353676 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.1617353676
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.4013353347
Short name T176
Test name
Test status
Simulation time 32657919 ps
CPU time 0.84 seconds
Started Jun 13 01:51:02 PM PDT 24
Finished Jun 13 01:51:04 PM PDT 24
Peak memory 217584 kb
Host smart-c0163fb6-2234-4a7a-9dae-2a73569b61a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013353347 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.4013353347
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2148714526
Short name T586
Test name
Test status
Simulation time 67295360 ps
CPU time 1.98 seconds
Started Jun 13 01:51:00 PM PDT 24
Finished Jun 13 01:51:04 PM PDT 24
Peak memory 216744 kb
Host smart-60cbdd40-319b-4864-a5d6-a76abab3aec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148714526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2148714526
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.661736275
Short name T863
Test name
Test status
Simulation time 66598944 ps
CPU time 1.16 seconds
Started Jun 13 01:51:00 PM PDT 24
Finished Jun 13 01:51:03 PM PDT 24
Peak memory 218040 kb
Host smart-e192925b-2898-470b-91f1-31c10738203e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661736275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.661736275
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.3546213012
Short name T101
Test name
Test status
Simulation time 20689066 ps
CPU time 1.16 seconds
Started Jun 13 01:50:59 PM PDT 24
Finished Jun 13 01:51:02 PM PDT 24
Peak memory 219260 kb
Host smart-463dd998-65c0-456c-aeaf-ec422d181c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546213012 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3546213012
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.372305370
Short name T281
Test name
Test status
Simulation time 37629738 ps
CPU time 1.56 seconds
Started Jun 13 01:50:58 PM PDT 24
Finished Jun 13 01:51:02 PM PDT 24
Peak memory 216776 kb
Host smart-3d66521d-00cd-46b4-9399-eea44a21ada2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372305370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.372305370
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1867424844
Short name T291
Test name
Test status
Simulation time 36611039 ps
CPU time 1.21 seconds
Started Jun 13 01:49:13 PM PDT 24
Finished Jun 13 01:49:15 PM PDT 24
Peak memory 218084 kb
Host smart-6a28ba5e-e705-4c46-bc64-6a7144bf1449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867424844 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1867424844
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.669862804
Short name T797
Test name
Test status
Simulation time 20137338 ps
CPU time 1.15 seconds
Started Jun 13 01:49:12 PM PDT 24
Finished Jun 13 01:49:14 PM PDT 24
Peak memory 214696 kb
Host smart-aeabc9e7-1547-4538-b517-82071ac9b822
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669862804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.669862804
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3057670162
Short name T951
Test name
Test status
Simulation time 37935211 ps
CPU time 0.87 seconds
Started Jun 13 01:49:12 PM PDT 24
Finished Jun 13 01:49:15 PM PDT 24
Peak memory 215676 kb
Host smart-8145e6ae-ce32-4466-979b-d840d8a590f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057670162 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3057670162
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.950035689
Short name T572
Test name
Test status
Simulation time 297190463 ps
CPU time 1.41 seconds
Started Jun 13 01:49:11 PM PDT 24
Finished Jun 13 01:49:14 PM PDT 24
Peak memory 216156 kb
Host smart-2188e1b3-be3a-4272-9d4a-cb2690cec653
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950035689 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.950035689
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.124226229
Short name T821
Test name
Test status
Simulation time 79618266 ps
CPU time 1.19 seconds
Started Jun 13 01:49:13 PM PDT 24
Finished Jun 13 01:49:15 PM PDT 24
Peak memory 224772 kb
Host smart-c2b255ee-2b24-4b8b-999d-2e07ebc258cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124226229 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.124226229
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1072656849
Short name T451
Test name
Test status
Simulation time 55116850 ps
CPU time 1.52 seconds
Started Jun 13 01:49:10 PM PDT 24
Finished Jun 13 01:49:13 PM PDT 24
Peak memory 217828 kb
Host smart-ebdb6d38-27b8-4df8-b2a4-7e75348554ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072656849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1072656849
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.4129864123
Short name T559
Test name
Test status
Simulation time 27452277 ps
CPU time 0.98 seconds
Started Jun 13 01:49:13 PM PDT 24
Finished Jun 13 01:49:15 PM PDT 24
Peak memory 214972 kb
Host smart-91502151-ebf0-4278-bf46-a409c9968341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129864123 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.4129864123
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3800801576
Short name T32
Test name
Test status
Simulation time 78748502 ps
CPU time 0.97 seconds
Started Jun 13 01:49:14 PM PDT 24
Finished Jun 13 01:49:16 PM PDT 24
Peak memory 206424 kb
Host smart-1ad27a25-e6f7-44e6-a3bd-95fa8720deda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800801576 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3800801576
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2756821864
Short name T597
Test name
Test status
Simulation time 19206915 ps
CPU time 0.98 seconds
Started Jun 13 01:49:11 PM PDT 24
Finished Jun 13 01:49:13 PM PDT 24
Peak memory 214620 kb
Host smart-d4d463d4-9988-423a-a6e7-fc7ff4ae6882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756821864 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2756821864
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1265894132
Short name T474
Test name
Test status
Simulation time 581046467 ps
CPU time 6.31 seconds
Started Jun 13 01:49:12 PM PDT 24
Finished Jun 13 01:49:19 PM PDT 24
Peak memory 217988 kb
Host smart-a3824354-b1c1-41d1-899c-b5ef17355892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265894132 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1265894132
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2518740562
Short name T669
Test name
Test status
Simulation time 75436254995 ps
CPU time 374.22 seconds
Started Jun 13 01:49:12 PM PDT 24
Finished Jun 13 01:55:28 PM PDT 24
Peak memory 222936 kb
Host smart-994d9120-4df0-4527-a753-80fc4945ff51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518740562 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2518740562
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.2048563344
Short name T720
Test name
Test status
Simulation time 26249957 ps
CPU time 1.26 seconds
Started Jun 13 01:51:00 PM PDT 24
Finished Jun 13 01:51:03 PM PDT 24
Peak memory 219156 kb
Host smart-13b79c6c-d5ad-4913-859c-ebf1f44001b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048563344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.2048563344
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.974031767
Short name T205
Test name
Test status
Simulation time 19284478 ps
CPU time 1.06 seconds
Started Jun 13 01:51:00 PM PDT 24
Finished Jun 13 01:51:04 PM PDT 24
Peak memory 217944 kb
Host smart-5a6f13a6-268f-4656-ab84-d909004082fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974031767 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.974031767
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3214995766
Short name T389
Test name
Test status
Simulation time 138404957 ps
CPU time 1.14 seconds
Started Jun 13 01:51:00 PM PDT 24
Finished Jun 13 01:51:03 PM PDT 24
Peak memory 214620 kb
Host smart-27724471-c30b-40c0-8496-516f0711d758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214995766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3214995766
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.1271909785
Short name T655
Test name
Test status
Simulation time 183521053 ps
CPU time 1.34 seconds
Started Jun 13 01:51:04 PM PDT 24
Finished Jun 13 01:51:07 PM PDT 24
Peak memory 215076 kb
Host smart-474b506f-e708-4d8d-b9bd-23b3beffe12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271909785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.1271909785
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.1728438058
Short name T591
Test name
Test status
Simulation time 24240896 ps
CPU time 1.08 seconds
Started Jun 13 01:50:59 PM PDT 24
Finished Jun 13 01:51:02 PM PDT 24
Peak memory 223368 kb
Host smart-b69d6c86-8c58-44a7-bb65-1731d96674f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728438058 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1728438058
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.692697656
Short name T668
Test name
Test status
Simulation time 50940893 ps
CPU time 1.41 seconds
Started Jun 13 01:51:00 PM PDT 24
Finished Jun 13 01:51:04 PM PDT 24
Peak memory 217768 kb
Host smart-75b045e8-8796-4a14-96c5-202f9c256be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692697656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.692697656
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.977503715
Short name T186
Test name
Test status
Simulation time 108333510 ps
CPU time 1.22 seconds
Started Jun 13 01:51:04 PM PDT 24
Finished Jun 13 01:51:07 PM PDT 24
Peak memory 220832 kb
Host smart-227e7853-6dc0-4f7b-9e43-044f31cabc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977503715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.977503715
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.1610983074
Short name T401
Test name
Test status
Simulation time 27690984 ps
CPU time 0.97 seconds
Started Jun 13 01:51:02 PM PDT 24
Finished Jun 13 01:51:04 PM PDT 24
Peak memory 231624 kb
Host smart-c5b48c81-2af6-46d3-beb2-c32bf958499e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610983074 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1610983074
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1330874084
Short name T549
Test name
Test status
Simulation time 65160218 ps
CPU time 1.09 seconds
Started Jun 13 01:51:01 PM PDT 24
Finished Jun 13 01:51:04 PM PDT 24
Peak memory 216760 kb
Host smart-e638f7a7-b286-4fef-b940-35681f656e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330874084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1330874084
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.2033689798
Short name T219
Test name
Test status
Simulation time 162492488 ps
CPU time 1.32 seconds
Started Jun 13 01:51:02 PM PDT 24
Finished Jun 13 01:51:05 PM PDT 24
Peak memory 218048 kb
Host smart-39033f90-03c7-426d-b81b-3f7425c486e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033689798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.2033689798
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.3998760562
Short name T183
Test name
Test status
Simulation time 24117648 ps
CPU time 0.87 seconds
Started Jun 13 01:51:05 PM PDT 24
Finished Jun 13 01:51:08 PM PDT 24
Peak memory 217544 kb
Host smart-1686088f-497a-48b7-ada8-06ca3bea19b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998760562 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3998760562
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2963386192
Short name T980
Test name
Test status
Simulation time 100916839 ps
CPU time 1.6 seconds
Started Jun 13 01:51:06 PM PDT 24
Finished Jun 13 01:51:10 PM PDT 24
Peak memory 218352 kb
Host smart-65d0aad6-fefb-4172-a0f0-c0b99b3345ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963386192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2963386192
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.302190324
Short name T632
Test name
Test status
Simulation time 29647878 ps
CPU time 1.29 seconds
Started Jun 13 01:51:05 PM PDT 24
Finished Jun 13 01:51:08 PM PDT 24
Peak memory 219996 kb
Host smart-560cf9b9-2eb4-4039-ad98-855d7b8f60dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302190324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.302190324
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.2354673930
Short name T130
Test name
Test status
Simulation time 76287120 ps
CPU time 1.1 seconds
Started Jun 13 01:51:05 PM PDT 24
Finished Jun 13 01:51:08 PM PDT 24
Peak memory 219844 kb
Host smart-140cd5ec-01a9-4221-a32b-6c8b435d9e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354673930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2354673930
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3332779602
Short name T791
Test name
Test status
Simulation time 62773503 ps
CPU time 1.11 seconds
Started Jun 13 01:51:15 PM PDT 24
Finished Jun 13 01:51:17 PM PDT 24
Peak memory 216636 kb
Host smart-22a17641-405d-4101-819b-c2943d1992b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332779602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3332779602
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.600366319
Short name T115
Test name
Test status
Simulation time 43991886 ps
CPU time 1.08 seconds
Started Jun 13 01:51:04 PM PDT 24
Finished Jun 13 01:51:06 PM PDT 24
Peak memory 219368 kb
Host smart-2eb2294c-3c0c-4343-879d-6c3a3035d435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600366319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.600366319
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.4255050040
Short name T464
Test name
Test status
Simulation time 63295356 ps
CPU time 1.08 seconds
Started Jun 13 01:51:04 PM PDT 24
Finished Jun 13 01:51:07 PM PDT 24
Peak memory 214752 kb
Host smart-d92128d5-c545-43a2-b688-f88483f58bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255050040 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.4255050040
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3912600455
Short name T900
Test name
Test status
Simulation time 35368940 ps
CPU time 1.32 seconds
Started Jun 13 01:51:06 PM PDT 24
Finished Jun 13 01:51:09 PM PDT 24
Peak memory 216588 kb
Host smart-cf2c26bc-2847-4ec3-89f6-1519b24b9b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912600455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3912600455
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1695779069
Short name T835
Test name
Test status
Simulation time 120245701 ps
CPU time 1.28 seconds
Started Jun 13 01:51:06 PM PDT 24
Finished Jun 13 01:51:10 PM PDT 24
Peak memory 215076 kb
Host smart-3f71b947-dc8b-4dd1-9ef4-fe84b56b1459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695779069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1695779069
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.902253600
Short name T112
Test name
Test status
Simulation time 25665035 ps
CPU time 1.04 seconds
Started Jun 13 01:51:04 PM PDT 24
Finished Jun 13 01:51:07 PM PDT 24
Peak memory 219048 kb
Host smart-2e6d98ef-e24c-4fb8-988a-4a937fbe10e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902253600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.902253600
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.172352327
Short name T334
Test name
Test status
Simulation time 57402694 ps
CPU time 1.58 seconds
Started Jun 13 01:51:05 PM PDT 24
Finished Jun 13 01:51:08 PM PDT 24
Peak memory 217740 kb
Host smart-8c492068-ec62-4e0b-8862-30c1e092a2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172352327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.172352327
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.1682472294
Short name T914
Test name
Test status
Simulation time 36298985 ps
CPU time 1.19 seconds
Started Jun 13 01:51:13 PM PDT 24
Finished Jun 13 01:51:15 PM PDT 24
Peak memory 218128 kb
Host smart-0eb187da-638b-46f3-8ae6-3228f7aa331d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682472294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.1682472294
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.877786621
Short name T196
Test name
Test status
Simulation time 52355839 ps
CPU time 0.93 seconds
Started Jun 13 01:51:07 PM PDT 24
Finished Jun 13 01:51:09 PM PDT 24
Peak memory 218560 kb
Host smart-4b0046bc-45f8-4514-b854-53ebdc449963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877786621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.877786621
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3786029428
Short name T345
Test name
Test status
Simulation time 269786680 ps
CPU time 1.07 seconds
Started Jun 13 01:51:05 PM PDT 24
Finished Jun 13 01:51:08 PM PDT 24
Peak memory 216524 kb
Host smart-9b5f0791-fad2-4eb7-839b-8d2c8211838c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786029428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3786029428
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.2908245160
Short name T16
Test name
Test status
Simulation time 26698886 ps
CPU time 0.96 seconds
Started Jun 13 01:51:14 PM PDT 24
Finished Jun 13 01:51:16 PM PDT 24
Peak memory 228808 kb
Host smart-9ef7247f-79de-4463-b4a4-a5fb0e5749c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908245160 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2908245160
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2647777595
Short name T918
Test name
Test status
Simulation time 86244828 ps
CPU time 1.8 seconds
Started Jun 13 01:51:06 PM PDT 24
Finished Jun 13 01:51:10 PM PDT 24
Peak memory 216844 kb
Host smart-91c0d1c2-3c97-4b50-85fb-6ffcb68f3c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647777595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2647777595
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.3576155229
Short name T853
Test name
Test status
Simulation time 168734174 ps
CPU time 1.36 seconds
Started Jun 13 01:51:06 PM PDT 24
Finished Jun 13 01:51:09 PM PDT 24
Peak memory 219132 kb
Host smart-3fb393d9-0266-45c4-8794-57db13d3ff44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576155229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.3576155229
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.3932410668
Short name T933
Test name
Test status
Simulation time 35032294 ps
CPU time 0.88 seconds
Started Jun 13 01:51:14 PM PDT 24
Finished Jun 13 01:51:16 PM PDT 24
Peak memory 217824 kb
Host smart-324a766f-b278-43b9-8b5b-d7b9f034694b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932410668 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3932410668
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.146943170
Short name T412
Test name
Test status
Simulation time 53696795 ps
CPU time 1.3 seconds
Started Jun 13 01:51:04 PM PDT 24
Finished Jun 13 01:51:07 PM PDT 24
Peak memory 216804 kb
Host smart-2b3bb22e-79d3-4a5e-91d5-b7041a12df7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146943170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.146943170
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%