Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.51 98.25 93.97 97.07 91.28 96.37 99.77 91.89


Total test records in report: 1130
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T245 /workspace/coverage/cover_reg_top/0.edn_csr_rw.1608349217 Jun 21 06:35:55 PM PDT 24 Jun 21 06:35:57 PM PDT 24 18259155 ps
T260 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3147560339 Jun 21 06:35:55 PM PDT 24 Jun 21 06:35:58 PM PDT 24 35714688 ps
T1018 /workspace/coverage/cover_reg_top/28.edn_intr_test.85453507 Jun 21 06:37:00 PM PDT 24 Jun 21 06:37:04 PM PDT 24 24674192 ps
T1019 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1308559685 Jun 21 06:36:11 PM PDT 24 Jun 21 06:36:13 PM PDT 24 23212053 ps
T1020 /workspace/coverage/cover_reg_top/20.edn_intr_test.2619236739 Jun 21 06:36:53 PM PDT 24 Jun 21 06:36:55 PM PDT 24 32425518 ps
T1021 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2684291506 Jun 21 06:36:43 PM PDT 24 Jun 21 06:36:46 PM PDT 24 32429551 ps
T283 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2879763383 Jun 21 06:36:18 PM PDT 24 Jun 21 06:36:25 PM PDT 24 223142460 ps
T253 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.688608 Jun 21 06:36:11 PM PDT 24 Jun 21 06:36:17 PM PDT 24 166188009 ps
T1022 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1684936506 Jun 21 06:36:35 PM PDT 24 Jun 21 06:36:42 PM PDT 24 370916822 ps
T1023 /workspace/coverage/cover_reg_top/16.edn_tl_errors.642794533 Jun 21 06:36:44 PM PDT 24 Jun 21 06:36:49 PM PDT 24 176448198 ps
T1024 /workspace/coverage/cover_reg_top/31.edn_intr_test.1430888379 Jun 21 06:37:02 PM PDT 24 Jun 21 06:37:07 PM PDT 24 17122967 ps
T1025 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2378695338 Jun 21 06:36:34 PM PDT 24 Jun 21 06:36:40 PM PDT 24 343622753 ps
T1026 /workspace/coverage/cover_reg_top/16.edn_intr_test.3845021628 Jun 21 06:36:42 PM PDT 24 Jun 21 06:36:45 PM PDT 24 31710210 ps
T1027 /workspace/coverage/cover_reg_top/21.edn_intr_test.254887207 Jun 21 06:36:54 PM PDT 24 Jun 21 06:36:57 PM PDT 24 16333048 ps
T1028 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3911230588 Jun 21 06:36:04 PM PDT 24 Jun 21 06:36:07 PM PDT 24 43406514 ps
T1029 /workspace/coverage/cover_reg_top/12.edn_intr_test.2353500516 Jun 21 06:36:34 PM PDT 24 Jun 21 06:36:37 PM PDT 24 14500178 ps
T1030 /workspace/coverage/cover_reg_top/9.edn_csr_rw.588151538 Jun 21 06:36:29 PM PDT 24 Jun 21 06:36:32 PM PDT 24 33281476 ps
T1031 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3367629695 Jun 21 06:36:26 PM PDT 24 Jun 21 06:36:30 PM PDT 24 31491437 ps
T1032 /workspace/coverage/cover_reg_top/1.edn_intr_test.3594206112 Jun 21 06:36:04 PM PDT 24 Jun 21 06:36:07 PM PDT 24 14291778 ps
T1033 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1573618994 Jun 21 06:36:37 PM PDT 24 Jun 21 06:36:41 PM PDT 24 15730573 ps
T1034 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2498688824 Jun 21 06:36:18 PM PDT 24 Jun 21 06:36:24 PM PDT 24 275900345 ps
T1035 /workspace/coverage/cover_reg_top/38.edn_intr_test.640823986 Jun 21 06:37:04 PM PDT 24 Jun 21 06:37:09 PM PDT 24 13012910 ps
T1036 /workspace/coverage/cover_reg_top/7.edn_tl_errors.178281654 Jun 21 06:36:28 PM PDT 24 Jun 21 06:36:34 PM PDT 24 44981902 ps
T1037 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.189026480 Jun 21 06:36:34 PM PDT 24 Jun 21 06:36:39 PM PDT 24 71429694 ps
T246 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3817049117 Jun 21 06:36:19 PM PDT 24 Jun 21 06:36:22 PM PDT 24 18816983 ps
T1038 /workspace/coverage/cover_reg_top/7.edn_intr_test.2863400882 Jun 21 06:36:27 PM PDT 24 Jun 21 06:36:30 PM PDT 24 38793618 ps
T1039 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3428541061 Jun 21 06:36:11 PM PDT 24 Jun 21 06:36:15 PM PDT 24 49511651 ps
T1040 /workspace/coverage/cover_reg_top/19.edn_intr_test.1843261413 Jun 21 06:36:53 PM PDT 24 Jun 21 06:36:56 PM PDT 24 20472373 ps
T284 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2774625582 Jun 21 06:36:32 PM PDT 24 Jun 21 06:36:36 PM PDT 24 120337738 ps
T247 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1868213317 Jun 21 06:36:53 PM PDT 24 Jun 21 06:36:57 PM PDT 24 53470443 ps
T1041 /workspace/coverage/cover_reg_top/14.edn_intr_test.3804971676 Jun 21 06:36:43 PM PDT 24 Jun 21 06:36:46 PM PDT 24 32363901 ps
T1042 /workspace/coverage/cover_reg_top/8.edn_intr_test.491311897 Jun 21 06:36:29 PM PDT 24 Jun 21 06:36:33 PM PDT 24 22446268 ps
T1043 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2797168747 Jun 21 06:36:18 PM PDT 24 Jun 21 06:36:21 PM PDT 24 11083821 ps
T1044 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2750505549 Jun 21 06:36:26 PM PDT 24 Jun 21 06:36:29 PM PDT 24 14667375 ps
T1045 /workspace/coverage/cover_reg_top/11.edn_intr_test.662448368 Jun 21 06:36:34 PM PDT 24 Jun 21 06:36:38 PM PDT 24 20026322 ps
T248 /workspace/coverage/cover_reg_top/8.edn_csr_rw.422005585 Jun 21 06:36:26 PM PDT 24 Jun 21 06:36:30 PM PDT 24 19599360 ps
T1046 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1130298513 Jun 21 06:36:04 PM PDT 24 Jun 21 06:36:08 PM PDT 24 325664276 ps
T1047 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2370683697 Jun 21 06:36:53 PM PDT 24 Jun 21 06:36:57 PM PDT 24 80825181 ps
T285 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3838639117 Jun 21 06:36:53 PM PDT 24 Jun 21 06:36:57 PM PDT 24 40814132 ps
T1048 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.111212582 Jun 21 06:36:43 PM PDT 24 Jun 21 06:36:46 PM PDT 24 105312587 ps
T1049 /workspace/coverage/cover_reg_top/6.edn_intr_test.1461713186 Jun 21 06:36:19 PM PDT 24 Jun 21 06:36:22 PM PDT 24 127909434 ps
T1050 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2339275310 Jun 21 06:36:03 PM PDT 24 Jun 21 06:36:06 PM PDT 24 86408975 ps
T1051 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1363914695 Jun 21 06:36:28 PM PDT 24 Jun 21 06:36:32 PM PDT 24 15809681 ps
T1052 /workspace/coverage/cover_reg_top/17.edn_intr_test.2273976325 Jun 21 06:36:43 PM PDT 24 Jun 21 06:36:45 PM PDT 24 15371100 ps
T1053 /workspace/coverage/cover_reg_top/45.edn_intr_test.3649539267 Jun 21 06:37:01 PM PDT 24 Jun 21 06:37:06 PM PDT 24 16306741 ps
T1054 /workspace/coverage/cover_reg_top/34.edn_intr_test.2747963214 Jun 21 06:37:02 PM PDT 24 Jun 21 06:37:07 PM PDT 24 10897040 ps
T1055 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3971058463 Jun 21 06:36:22 PM PDT 24 Jun 21 06:36:28 PM PDT 24 102957023 ps
T1056 /workspace/coverage/cover_reg_top/18.edn_intr_test.3487543286 Jun 21 06:36:52 PM PDT 24 Jun 21 06:36:55 PM PDT 24 19902795 ps
T1057 /workspace/coverage/cover_reg_top/22.edn_intr_test.1734512108 Jun 21 06:36:54 PM PDT 24 Jun 21 06:36:57 PM PDT 24 45743034 ps
T1058 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3211290557 Jun 21 06:35:56 PM PDT 24 Jun 21 06:35:58 PM PDT 24 204855707 ps
T1059 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2030099958 Jun 21 06:36:18 PM PDT 24 Jun 21 06:36:21 PM PDT 24 16001828 ps
T1060 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2063099292 Jun 21 06:36:29 PM PDT 24 Jun 21 06:36:33 PM PDT 24 41409184 ps
T1061 /workspace/coverage/cover_reg_top/32.edn_intr_test.3417595707 Jun 21 06:37:03 PM PDT 24 Jun 21 06:37:08 PM PDT 24 17223468 ps
T1062 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2283008405 Jun 21 06:36:11 PM PDT 24 Jun 21 06:36:15 PM PDT 24 370557234 ps
T1063 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2911726695 Jun 21 06:36:54 PM PDT 24 Jun 21 06:36:58 PM PDT 24 44147302 ps
T1064 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1087305217 Jun 21 06:36:37 PM PDT 24 Jun 21 06:36:41 PM PDT 24 61755715 ps
T1065 /workspace/coverage/cover_reg_top/5.edn_intr_test.3431705937 Jun 21 06:36:19 PM PDT 24 Jun 21 06:36:22 PM PDT 24 29143219 ps
T1066 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2019618664 Jun 21 06:36:29 PM PDT 24 Jun 21 06:36:33 PM PDT 24 108409459 ps
T1067 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1586988294 Jun 21 06:36:33 PM PDT 24 Jun 21 06:36:36 PM PDT 24 12672966 ps
T1068 /workspace/coverage/cover_reg_top/41.edn_intr_test.2875912644 Jun 21 06:37:02 PM PDT 24 Jun 21 06:37:07 PM PDT 24 16156319 ps
T1069 /workspace/coverage/cover_reg_top/36.edn_intr_test.3534824427 Jun 21 06:37:00 PM PDT 24 Jun 21 06:37:04 PM PDT 24 21636869 ps
T1070 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1341007434 Jun 21 06:36:04 PM PDT 24 Jun 21 06:36:09 PM PDT 24 96919888 ps
T281 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4154179587 Jun 21 06:36:43 PM PDT 24 Jun 21 06:36:46 PM PDT 24 67776258 ps
T1071 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.788002297 Jun 21 06:36:34 PM PDT 24 Jun 21 06:36:38 PM PDT 24 39873549 ps
T1072 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.623675755 Jun 21 06:36:15 PM PDT 24 Jun 21 06:36:20 PM PDT 24 286367186 ps
T1073 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3935966093 Jun 21 06:36:35 PM PDT 24 Jun 21 06:36:39 PM PDT 24 29682854 ps
T1074 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3366629461 Jun 21 06:36:16 PM PDT 24 Jun 21 06:36:22 PM PDT 24 315908474 ps
T249 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2595551499 Jun 21 06:36:43 PM PDT 24 Jun 21 06:36:46 PM PDT 24 30392585 ps
T250 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2103577715 Jun 21 06:36:43 PM PDT 24 Jun 21 06:36:45 PM PDT 24 17203961 ps
T1075 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.708678500 Jun 21 06:35:54 PM PDT 24 Jun 21 06:35:58 PM PDT 24 341030554 ps
T1076 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2162778703 Jun 21 06:36:55 PM PDT 24 Jun 21 06:36:58 PM PDT 24 147919936 ps
T1077 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.75702053 Jun 21 06:36:28 PM PDT 24 Jun 21 06:36:32 PM PDT 24 14237552 ps
T1078 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1282588412 Jun 21 06:36:55 PM PDT 24 Jun 21 06:36:58 PM PDT 24 17537002 ps
T1079 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1702570754 Jun 21 06:36:34 PM PDT 24 Jun 21 06:36:38 PM PDT 24 301047269 ps
T1080 /workspace/coverage/cover_reg_top/13.edn_intr_test.2851859181 Jun 21 06:36:34 PM PDT 24 Jun 21 06:36:37 PM PDT 24 26465858 ps
T1081 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1946943544 Jun 21 06:36:11 PM PDT 24 Jun 21 06:36:14 PM PDT 24 75425020 ps
T1082 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.145973560 Jun 21 06:36:27 PM PDT 24 Jun 21 06:36:33 PM PDT 24 557634428 ps
T251 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.292965851 Jun 21 06:36:02 PM PDT 24 Jun 21 06:36:05 PM PDT 24 16913932 ps
T1083 /workspace/coverage/cover_reg_top/39.edn_intr_test.3090566913 Jun 21 06:37:00 PM PDT 24 Jun 21 06:37:03 PM PDT 24 31887219 ps
T1084 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3378506363 Jun 21 06:36:12 PM PDT 24 Jun 21 06:36:16 PM PDT 24 103941131 ps
T1085 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2742572269 Jun 21 06:36:33 PM PDT 24 Jun 21 06:36:37 PM PDT 24 22075888 ps
T1086 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3866368656 Jun 21 06:36:14 PM PDT 24 Jun 21 06:36:18 PM PDT 24 73238825 ps
T1087 /workspace/coverage/cover_reg_top/10.edn_intr_test.4271295183 Jun 21 06:36:34 PM PDT 24 Jun 21 06:36:37 PM PDT 24 13597263 ps
T1088 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1937985919 Jun 21 06:36:19 PM PDT 24 Jun 21 06:36:23 PM PDT 24 29530155 ps
T252 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3994684857 Jun 21 06:36:44 PM PDT 24 Jun 21 06:36:47 PM PDT 24 23292264 ps
T1089 /workspace/coverage/cover_reg_top/0.edn_intr_test.1758689489 Jun 21 06:35:55 PM PDT 24 Jun 21 06:35:57 PM PDT 24 46836174 ps
T1090 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3092906382 Jun 21 06:36:06 PM PDT 24 Jun 21 06:36:10 PM PDT 24 45158441 ps
T1091 /workspace/coverage/cover_reg_top/48.edn_intr_test.2490285662 Jun 21 06:37:00 PM PDT 24 Jun 21 06:37:03 PM PDT 24 18734920 ps
T1092 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3414424854 Jun 21 06:36:34 PM PDT 24 Jun 21 06:36:41 PM PDT 24 178562734 ps
T254 /workspace/coverage/cover_reg_top/18.edn_csr_rw.546409886 Jun 21 06:36:53 PM PDT 24 Jun 21 06:36:57 PM PDT 24 19125690 ps
T1093 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.664427118 Jun 21 06:36:43 PM PDT 24 Jun 21 06:36:46 PM PDT 24 323217896 ps
T1094 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1783824088 Jun 21 06:36:35 PM PDT 24 Jun 21 06:36:41 PM PDT 24 41443147 ps
T1095 /workspace/coverage/cover_reg_top/30.edn_intr_test.2382271168 Jun 21 06:37:01 PM PDT 24 Jun 21 06:37:05 PM PDT 24 59110168 ps
T1096 /workspace/coverage/cover_reg_top/26.edn_intr_test.1805196562 Jun 21 06:36:53 PM PDT 24 Jun 21 06:36:56 PM PDT 24 40483974 ps
T1097 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2194602081 Jun 21 06:36:18 PM PDT 24 Jun 21 06:36:23 PM PDT 24 185832286 ps
T1098 /workspace/coverage/cover_reg_top/3.edn_intr_test.4136704502 Jun 21 06:36:14 PM PDT 24 Jun 21 06:36:17 PM PDT 24 26948303 ps
T1099 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1697563200 Jun 21 06:36:29 PM PDT 24 Jun 21 06:36:35 PM PDT 24 110788414 ps
T1100 /workspace/coverage/cover_reg_top/25.edn_intr_test.2747598930 Jun 21 06:36:56 PM PDT 24 Jun 21 06:36:59 PM PDT 24 31081592 ps
T255 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1212783933 Jun 21 06:35:54 PM PDT 24 Jun 21 06:35:57 PM PDT 24 41128075 ps
T1101 /workspace/coverage/cover_reg_top/19.edn_tl_errors.753803018 Jun 21 06:36:52 PM PDT 24 Jun 21 06:36:55 PM PDT 24 88421462 ps
T1102 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2357428455 Jun 21 06:36:35 PM PDT 24 Jun 21 06:36:40 PM PDT 24 106010540 ps
T256 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3264662079 Jun 21 06:36:22 PM PDT 24 Jun 21 06:36:25 PM PDT 24 19661776 ps
T1103 /workspace/coverage/cover_reg_top/29.edn_intr_test.1913393396 Jun 21 06:37:01 PM PDT 24 Jun 21 06:37:04 PM PDT 24 41193053 ps
T1104 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.4293422801 Jun 21 06:36:32 PM PDT 24 Jun 21 06:36:35 PM PDT 24 28939951 ps
T1105 /workspace/coverage/cover_reg_top/2.edn_intr_test.1681524393 Jun 21 06:36:11 PM PDT 24 Jun 21 06:36:13 PM PDT 24 12367888 ps
T1106 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1418797943 Jun 21 06:36:53 PM PDT 24 Jun 21 06:36:55 PM PDT 24 125943524 ps
T1107 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4090865896 Jun 21 06:36:33 PM PDT 24 Jun 21 06:36:39 PM PDT 24 100812327 ps
T1108 /workspace/coverage/cover_reg_top/4.edn_intr_test.4139844483 Jun 21 06:36:20 PM PDT 24 Jun 21 06:36:23 PM PDT 24 61074841 ps
T1109 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2721398269 Jun 21 06:36:36 PM PDT 24 Jun 21 06:36:41 PM PDT 24 129497364 ps
T1110 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2540337414 Jun 21 06:36:14 PM PDT 24 Jun 21 06:36:17 PM PDT 24 24702260 ps
T1111 /workspace/coverage/cover_reg_top/37.edn_intr_test.1648513303 Jun 21 06:37:02 PM PDT 24 Jun 21 06:37:06 PM PDT 24 80210533 ps
T1112 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1326974481 Jun 21 06:36:54 PM PDT 24 Jun 21 06:36:57 PM PDT 24 25782705 ps
T1113 /workspace/coverage/cover_reg_top/42.edn_intr_test.2734415061 Jun 21 06:37:01 PM PDT 24 Jun 21 06:37:06 PM PDT 24 57033211 ps
T1114 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3687555939 Jun 21 06:35:55 PM PDT 24 Jun 21 06:35:58 PM PDT 24 42266845 ps
T1115 /workspace/coverage/cover_reg_top/33.edn_intr_test.227246535 Jun 21 06:37:02 PM PDT 24 Jun 21 06:37:06 PM PDT 24 15793083 ps
T1116 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1782563032 Jun 21 06:36:52 PM PDT 24 Jun 21 06:36:55 PM PDT 24 28400883 ps
T1117 /workspace/coverage/cover_reg_top/18.edn_tl_errors.258830098 Jun 21 06:36:53 PM PDT 24 Jun 21 06:36:57 PM PDT 24 21244033 ps
T1118 /workspace/coverage/cover_reg_top/12.edn_csr_rw.314453132 Jun 21 06:36:35 PM PDT 24 Jun 21 06:36:39 PM PDT 24 16521260 ps
T1119 /workspace/coverage/cover_reg_top/9.edn_intr_test.2442868901 Jun 21 06:36:27 PM PDT 24 Jun 21 06:36:30 PM PDT 24 20174000 ps
T1120 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3672693987 Jun 21 06:36:04 PM PDT 24 Jun 21 06:36:07 PM PDT 24 36041413 ps
T1121 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2626649518 Jun 21 06:36:36 PM PDT 24 Jun 21 06:36:40 PM PDT 24 21672938 ps
T1122 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1757105633 Jun 21 06:36:37 PM PDT 24 Jun 21 06:36:41 PM PDT 24 149711449 ps
T1123 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3430570930 Jun 21 06:36:36 PM PDT 24 Jun 21 06:36:43 PM PDT 24 320845200 ps
T1124 /workspace/coverage/cover_reg_top/23.edn_intr_test.3094865703 Jun 21 06:36:54 PM PDT 24 Jun 21 06:36:57 PM PDT 24 22223268 ps
T1125 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3655807652 Jun 21 06:36:21 PM PDT 24 Jun 21 06:36:24 PM PDT 24 40363052 ps
T1126 /workspace/coverage/cover_reg_top/40.edn_intr_test.1958121898 Jun 21 06:37:05 PM PDT 24 Jun 21 06:37:10 PM PDT 24 91151371 ps
T1127 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3550443306 Jun 21 06:36:15 PM PDT 24 Jun 21 06:36:18 PM PDT 24 67063652 ps
T1128 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.793286912 Jun 21 06:36:43 PM PDT 24 Jun 21 06:36:54 PM PDT 24 494066889 ps
T1129 /workspace/coverage/cover_reg_top/27.edn_intr_test.1730765451 Jun 21 06:36:52 PM PDT 24 Jun 21 06:36:54 PM PDT 24 15189117 ps
T1130 /workspace/coverage/cover_reg_top/44.edn_intr_test.4012968887 Jun 21 06:37:01 PM PDT 24 Jun 21 06:37:04 PM PDT 24 31876977 ps

Test location /workspace/coverage/default/253.edn_genbits.2843583006
Short name T21
Test name
Test status
Simulation time 240090393 ps
CPU time 1.58 seconds
Started Jun 21 06:45:38 PM PDT 24
Finished Jun 21 06:46:03 PM PDT 24
Peak memory 218328 kb
Host smart-66fe4710-b743-4a96-8ff8-8111f194faaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843583006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2843583006
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.4018009272
Short name T34
Test name
Test status
Simulation time 104840793125 ps
CPU time 551.43 seconds
Started Jun 21 06:43:27 PM PDT 24
Finished Jun 21 06:53:09 PM PDT 24
Peak memory 218636 kb
Host smart-e21826c9-3550-4ffa-8259-d9a94accdbb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018009272 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.4018009272
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2528844876
Short name T2
Test name
Test status
Simulation time 2345060645 ps
CPU time 8.21 seconds
Started Jun 21 06:41:06 PM PDT 24
Finished Jun 21 06:42:11 PM PDT 24
Peak memory 240544 kb
Host smart-1e5038a1-b9f6-4edc-8bf6-61b866002f44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528844876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2528844876
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.56049480
Short name T1
Test name
Test status
Simulation time 30384102 ps
CPU time 1.08 seconds
Started Jun 21 06:42:13 PM PDT 24
Finished Jun 21 06:43:06 PM PDT 24
Peak memory 217552 kb
Host smart-e21472cc-cfcd-4ee7-a207-33bf2836f91f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56049480 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_dis
able_auto_req_mode.56049480
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/139.edn_alert.3334854008
Short name T41
Test name
Test status
Simulation time 27965698 ps
CPU time 1.25 seconds
Started Jun 21 06:44:49 PM PDT 24
Finished Jun 21 06:45:20 PM PDT 24
Peak memory 218068 kb
Host smart-0be78f6f-2066-4ca2-9655-0588d4c5a1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334854008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.3334854008
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/241.edn_genbits.3029855433
Short name T38
Test name
Test status
Simulation time 32390164 ps
CPU time 1.3 seconds
Started Jun 21 06:45:35 PM PDT 24
Finished Jun 21 06:46:01 PM PDT 24
Peak memory 216940 kb
Host smart-5472ac72-84e1-4714-bb47-ad57ee016102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029855433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3029855433
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_stress_all.616210644
Short name T23
Test name
Test status
Simulation time 620677697 ps
CPU time 3.92 seconds
Started Jun 21 06:42:32 PM PDT 24
Finished Jun 21 06:43:18 PM PDT 24
Peak memory 216484 kb
Host smart-c1d31e2e-dec8-4227-8996-ca694b98c129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616210644 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.616210644
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/186.edn_alert.735586914
Short name T91
Test name
Test status
Simulation time 70955078 ps
CPU time 1.27 seconds
Started Jun 21 06:45:20 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 215104 kb
Host smart-8a2a8456-0feb-4204-87e7-dbd71223a96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735586914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.735586914
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/0.edn_regwen.2115013883
Short name T24
Test name
Test status
Simulation time 18515808 ps
CPU time 1.01 seconds
Started Jun 21 06:41:01 PM PDT 24
Finished Jun 21 06:41:51 PM PDT 24
Peak memory 206448 kb
Host smart-5f5d49fb-5cce-4b92-a98e-6db7e3faa92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115013883 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2115013883
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/83.edn_alert.1221148606
Short name T195
Test name
Test status
Simulation time 26399917 ps
CPU time 1.17 seconds
Started Jun 21 06:44:13 PM PDT 24
Finished Jun 21 06:44:51 PM PDT 24
Peak memory 219188 kb
Host smart-ace4403c-0e45-4a8a-8681-bfac55790770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221148606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.1221148606
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert.495040749
Short name T105
Test name
Test status
Simulation time 24741003 ps
CPU time 1.21 seconds
Started Jun 21 06:42:33 PM PDT 24
Finished Jun 21 06:43:17 PM PDT 24
Peak memory 219124 kb
Host smart-a9e73605-402d-40d5-b89e-e9ce2ea3d496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495040749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.495040749
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/177.edn_alert.3268086900
Short name T261
Test name
Test status
Simulation time 92936087 ps
CPU time 1.25 seconds
Started Jun 21 06:45:12 PM PDT 24
Finished Jun 21 06:45:39 PM PDT 24
Peak memory 218712 kb
Host smart-ace4e858-d8c1-4119-8bf7-81079e363c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268086900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.3268086900
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/21.edn_disable.2459951126
Short name T22
Test name
Test status
Simulation time 12515061 ps
CPU time 0.91 seconds
Started Jun 21 06:42:14 PM PDT 24
Finished Jun 21 06:43:07 PM PDT 24
Peak memory 215812 kb
Host smart-71a2394a-7d98-4c81-9ad1-faec984b47e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459951126 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2459951126
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3838639117
Short name T285
Test name
Test status
Simulation time 40814132 ps
CPU time 1.6 seconds
Started Jun 21 06:36:53 PM PDT 24
Finished Jun 21 06:36:57 PM PDT 24
Peak memory 206384 kb
Host smart-0a9e2fd7-b3b8-42c2-888f-1db27526c42f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838639117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3838639117
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1608349217
Short name T245
Test name
Test status
Simulation time 18259155 ps
CPU time 0.79 seconds
Started Jun 21 06:35:55 PM PDT 24
Finished Jun 21 06:35:57 PM PDT 24
Peak memory 206256 kb
Host smart-5c177057-f0db-4681-82b6-03290114010e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608349217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1608349217
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.10148002
Short name T77
Test name
Test status
Simulation time 33019735 ps
CPU time 1.26 seconds
Started Jun 21 06:43:46 PM PDT 24
Finished Jun 21 06:44:19 PM PDT 24
Peak memory 216136 kb
Host smart-f0b25784-4a8f-4bb7-bbf7-8bf28faf923d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10148002 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_dis
able_auto_req_mode.10148002
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_disable.3450032839
Short name T162
Test name
Test status
Simulation time 38610202 ps
CPU time 0.86 seconds
Started Jun 21 06:42:13 PM PDT 24
Finished Jun 21 06:43:06 PM PDT 24
Peak memory 215688 kb
Host smart-dfe57fd3-faf7-482b-9a03-96ccfbdd2b6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450032839 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3450032839
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable.3563383585
Short name T201
Test name
Test status
Simulation time 14454411 ps
CPU time 0.89 seconds
Started Jun 21 06:43:40 PM PDT 24
Finished Jun 21 06:44:10 PM PDT 24
Peak memory 215596 kb
Host smart-71bf5867-202c-4e5f-a888-3fd6063b05a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563383585 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3563383585
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.3072833347
Short name T182
Test name
Test status
Simulation time 20912345 ps
CPU time 1.12 seconds
Started Jun 21 06:41:58 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 217940 kb
Host smart-4230353d-7fd3-49ab-99c3-1959c65ca1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072833347 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3072833347
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1905564200
Short name T142
Test name
Test status
Simulation time 53783398 ps
CPU time 1.86 seconds
Started Jun 21 06:42:33 PM PDT 24
Finished Jun 21 06:43:18 PM PDT 24
Peak memory 216204 kb
Host smart-b05c16fc-8777-47f6-ad7e-f225f6b2f3ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905564200 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1905564200
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_disable.4178102044
Short name T169
Test name
Test status
Simulation time 23961346 ps
CPU time 0.86 seconds
Started Jun 21 06:42:52 PM PDT 24
Finished Jun 21 06:43:26 PM PDT 24
Peak memory 215692 kb
Host smart-c8e05291-1f58-4422-b53a-53b3b49ceb7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178102044 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.4178102044
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/127.edn_genbits.475375036
Short name T11
Test name
Test status
Simulation time 55782722 ps
CPU time 1.25 seconds
Started Jun 21 06:44:40 PM PDT 24
Finished Jun 21 06:45:14 PM PDT 24
Peak memory 214632 kb
Host smart-de1c7046-2546-49f2-8060-9791f7ce473c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475375036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.475375036
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2470661793
Short name T36
Test name
Test status
Simulation time 12875832969 ps
CPU time 154.87 seconds
Started Jun 21 06:41:49 PM PDT 24
Finished Jun 21 06:45:26 PM PDT 24
Peak memory 217304 kb
Host smart-2e59c2b4-c77c-436d-a317-aed3cb7d254f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470661793 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2470661793
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/187.edn_alert.2343400788
Short name T150
Test name
Test status
Simulation time 67713960 ps
CPU time 1.27 seconds
Started Jun 21 06:45:20 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 217776 kb
Host smart-2d10c2e4-c6db-404e-b00f-5b18a499c876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343400788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.2343400788
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/29.edn_intr.1357378731
Short name T93
Test name
Test status
Simulation time 36045726 ps
CPU time 0.84 seconds
Started Jun 21 06:42:56 PM PDT 24
Finished Jun 21 06:43:29 PM PDT 24
Peak memory 214912 kb
Host smart-9a12b86b-d478-469f-ad58-9c3028d3cbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357378731 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1357378731
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/104.edn_alert.3081792337
Short name T112
Test name
Test status
Simulation time 42039813 ps
CPU time 1.13 seconds
Started Jun 21 06:44:32 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 218240 kb
Host smart-361f931d-ddd5-4246-bd35-0394b4fb5c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081792337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.3081792337
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/112.edn_alert.3816468737
Short name T71
Test name
Test status
Simulation time 78376266 ps
CPU time 1.16 seconds
Started Jun 21 06:44:44 PM PDT 24
Finished Jun 21 06:45:17 PM PDT 24
Peak memory 217880 kb
Host smart-42a8c785-3805-4cfa-a96c-97c4b2b15a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816468737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3816468737
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/2.edn_intr.3147851381
Short name T32
Test name
Test status
Simulation time 20521545 ps
CPU time 1.05 seconds
Started Jun 21 06:41:12 PM PDT 24
Finished Jun 21 06:42:14 PM PDT 24
Peak memory 215136 kb
Host smart-9a2010ac-95de-46d9-81f7-3a90400da4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147851381 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3147851381
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/100.edn_alert.1213741211
Short name T171
Test name
Test status
Simulation time 28504728 ps
CPU time 1.24 seconds
Started Jun 21 06:44:33 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 219176 kb
Host smart-bc2ea719-e659-4521-bf7a-1259c44b6489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213741211 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.1213741211
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/111.edn_alert.3414025013
Short name T122
Test name
Test status
Simulation time 88599550 ps
CPU time 1.16 seconds
Started Jun 21 06:44:46 PM PDT 24
Finished Jun 21 06:45:18 PM PDT 24
Peak memory 217808 kb
Host smart-69e95fb8-28ae-4663-8de9-78707aa29ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414025013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.3414025013
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/198.edn_alert.3291710008
Short name T587
Test name
Test status
Simulation time 238042661 ps
CPU time 1.14 seconds
Started Jun 21 06:45:21 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 217896 kb
Host smart-28f6ed4b-b482-4bbd-b4ac-4ee31c4f4fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291710008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.3291710008
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.3463379493
Short name T301
Test name
Test status
Simulation time 45212452 ps
CPU time 1.34 seconds
Started Jun 21 06:45:04 PM PDT 24
Finished Jun 21 06:45:33 PM PDT 24
Peak memory 217912 kb
Host smart-754cc737-b0c3-4ac7-9650-1d9009bef4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463379493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3463379493
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2405905765
Short name T297
Test name
Test status
Simulation time 61420739 ps
CPU time 1.42 seconds
Started Jun 21 06:45:50 PM PDT 24
Finished Jun 21 06:46:11 PM PDT 24
Peak memory 218156 kb
Host smart-2c03e3a7-ddb8-45ae-95b8-d62fa0823e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405905765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2405905765
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2158519762
Short name T222
Test name
Test status
Simulation time 44269401 ps
CPU time 1.13 seconds
Started Jun 21 06:41:46 PM PDT 24
Finished Jun 21 06:42:51 PM PDT 24
Peak memory 218316 kb
Host smart-f996dc32-e007-43d8-a44a-000f3b3a15d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158519762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2158519762
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2370256227
Short name T149
Test name
Test status
Simulation time 125420038 ps
CPU time 1.18 seconds
Started Jun 21 06:42:08 PM PDT 24
Finished Jun 21 06:43:03 PM PDT 24
Peak memory 216452 kb
Host smart-5b7dcea4-0e7b-4e62-9512-0156712ee986
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370256227 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2370256227
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_disable.1526302807
Short name T163
Test name
Test status
Simulation time 12290570 ps
CPU time 0.88 seconds
Started Jun 21 06:43:48 PM PDT 24
Finished Jun 21 06:44:19 PM PDT 24
Peak memory 216032 kb
Host smart-ae6c1db0-a5f3-4ee1-ab2f-e45e3f7e23f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526302807 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1526302807
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.795957884
Short name T192
Test name
Test status
Simulation time 30900109 ps
CPU time 0.95 seconds
Started Jun 21 06:41:12 PM PDT 24
Finished Jun 21 06:42:14 PM PDT 24
Peak memory 217616 kb
Host smart-002b7998-4605-45c8-a387-1b9bee985244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795957884 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.795957884
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/103.edn_alert.1998303303
Short name T454
Test name
Test status
Simulation time 150497393 ps
CPU time 1.08 seconds
Started Jun 21 06:44:35 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 217956 kb
Host smart-5470b739-5fea-4671-8027-dfeaf9f36ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998303303 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1998303303
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1617312317
Short name T119
Test name
Test status
Simulation time 93095377 ps
CPU time 1.07 seconds
Started Jun 21 06:41:41 PM PDT 24
Finished Jun 21 06:42:47 PM PDT 24
Peak memory 216392 kb
Host smart-4d0a74d5-6185-44ca-ab24-a3a9fe9fc453
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617312317 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1617312317
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/113.edn_alert.1133992058
Short name T756
Test name
Test status
Simulation time 32001461 ps
CPU time 1.35 seconds
Started Jun 21 06:44:40 PM PDT 24
Finished Jun 21 06:45:14 PM PDT 24
Peak memory 219160 kb
Host smart-d32fbf03-d5f3-4d5b-806b-0154f255c7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133992058 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.1133992058
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable.4265676335
Short name T469
Test name
Test status
Simulation time 11540643 ps
CPU time 0.87 seconds
Started Jun 21 06:41:45 PM PDT 24
Finished Jun 21 06:42:48 PM PDT 24
Peak memory 215744 kb
Host smart-3affeef8-e414-4cc5-a406-6d0841eaeeab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265676335 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.4265676335
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1609233779
Short name T440
Test name
Test status
Simulation time 107506243 ps
CPU time 1.14 seconds
Started Jun 21 06:41:46 PM PDT 24
Finished Jun 21 06:42:48 PM PDT 24
Peak memory 216392 kb
Host smart-c69d1d51-bf40-485d-91a8-a717caba0c83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609233779 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1609233779
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/142.edn_alert.434969812
Short name T20
Test name
Test status
Simulation time 23887702 ps
CPU time 1.17 seconds
Started Jun 21 06:44:49 PM PDT 24
Finished Jun 21 06:45:20 PM PDT 24
Peak memory 217988 kb
Host smart-8a2534f8-cdd0-41c5-b391-2ed452e49b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434969812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.434969812
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1976649927
Short name T764
Test name
Test status
Simulation time 113559307 ps
CPU time 1.1 seconds
Started Jun 21 06:41:56 PM PDT 24
Finished Jun 21 06:42:58 PM PDT 24
Peak memory 219068 kb
Host smart-ebe3e860-2700-4e8f-8cf1-b7b3c9eb0a28
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976649927 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1976649927
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/166.edn_alert.1740500252
Short name T185
Test name
Test status
Simulation time 23208273 ps
CPU time 1.16 seconds
Started Jun 21 06:45:14 PM PDT 24
Finished Jun 21 06:45:40 PM PDT 24
Peak memory 215180 kb
Host smart-1d9cb8dc-358f-4337-a5c1-9284a5b48f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740500252 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.1740500252
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/22.edn_err.1949764056
Short name T198
Test name
Test status
Simulation time 19501257 ps
CPU time 1.22 seconds
Started Jun 21 06:42:19 PM PDT 24
Finished Jun 21 06:43:09 PM PDT 24
Peak memory 228932 kb
Host smart-9998b6bb-9947-478e-858b-17c7b51c205a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949764056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1949764056
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/137.edn_genbits.2596367482
Short name T13
Test name
Test status
Simulation time 86810374 ps
CPU time 2 seconds
Started Jun 21 06:44:49 PM PDT 24
Finished Jun 21 06:45:21 PM PDT 24
Peak memory 216712 kb
Host smart-ce0e94e5-052a-4fce-aa1b-614fa02e6074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596367482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2596367482
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.480765447
Short name T298
Test name
Test status
Simulation time 572160280 ps
CPU time 4.32 seconds
Started Jun 21 06:45:47 PM PDT 24
Finished Jun 21 06:46:12 PM PDT 24
Peak memory 219720 kb
Host smart-32ade1a8-be0b-444a-89a4-cb0ce391ecf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480765447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.480765447
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_alert_test.2931190618
Short name T58
Test name
Test status
Simulation time 61119592 ps
CPU time 0.96 seconds
Started Jun 21 06:41:38 PM PDT 24
Finished Jun 21 06:42:45 PM PDT 24
Peak memory 214536 kb
Host smart-2bf3f46b-ab31-43e2-8a5e-c89ecf1f245c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931190618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2931190618
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/114.edn_alert.4095137485
Short name T286
Test name
Test status
Simulation time 26921526 ps
CPU time 1.3 seconds
Started Jun 21 06:44:40 PM PDT 24
Finished Jun 21 06:45:14 PM PDT 24
Peak memory 218028 kb
Host smart-eee57243-94cc-475d-a908-5d7d02ea9899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095137485 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.4095137485
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.920523133
Short name T227
Test name
Test status
Simulation time 835108072939 ps
CPU time 1564.5 seconds
Started Jun 21 06:41:22 PM PDT 24
Finished Jun 21 07:08:33 PM PDT 24
Peak memory 224052 kb
Host smart-4c656392-c5f1-454b-8847-82345d1b775e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920523133 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.920523133
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_intr.1392730042
Short name T29
Test name
Test status
Simulation time 34038199 ps
CPU time 0.83 seconds
Started Jun 21 06:41:23 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 214988 kb
Host smart-d5337f43-2845-4020-9cd6-9da45fde659e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392730042 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1392730042
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/125.edn_alert.3856138143
Short name T822
Test name
Test status
Simulation time 52957786 ps
CPU time 1.25 seconds
Started Jun 21 06:44:39 PM PDT 24
Finished Jun 21 06:45:14 PM PDT 24
Peak memory 219308 kb
Host smart-9deaa8ee-131f-40ad-bc83-78fd9e1b4708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856138143 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.3856138143
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/33.edn_err.265050340
Short name T5
Test name
Test status
Simulation time 89007116 ps
CPU time 1.06 seconds
Started Jun 21 06:43:09 PM PDT 24
Finished Jun 21 06:43:43 PM PDT 24
Peak memory 229068 kb
Host smart-9a8c19fd-fd73-439f-ac3e-e923e45ee98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265050340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.265050340
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.685749381
Short name T275
Test name
Test status
Simulation time 130136712 ps
CPU time 2.21 seconds
Started Jun 21 06:36:44 PM PDT 24
Finished Jun 21 06:36:48 PM PDT 24
Peak memory 206572 kb
Host smart-e116ae7a-76e9-495b-b46e-26dfb03f114c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685749381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.685749381
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.1921232779
Short name T893
Test name
Test status
Simulation time 162655295 ps
CPU time 1.28 seconds
Started Jun 21 06:41:05 PM PDT 24
Finished Jun 21 06:41:57 PM PDT 24
Peak memory 217972 kb
Host smart-09f26344-3d42-4cbd-bcb3-a233f150ee93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921232779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1921232779
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2144087453
Short name T974
Test name
Test status
Simulation time 39918923975 ps
CPU time 667.31 seconds
Started Jun 21 06:41:07 PM PDT 24
Finished Jun 21 06:53:15 PM PDT 24
Peak memory 216040 kb
Host smart-27e9b289-f72b-4cbf-912c-d8a37e894ca5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144087453 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2144087453
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.2605424571
Short name T349
Test name
Test status
Simulation time 80613502 ps
CPU time 1.2 seconds
Started Jun 21 06:44:32 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 216556 kb
Host smart-66a34627-d845-43f0-8310-0c015ba9387c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605424571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2605424571
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.3978351775
Short name T718
Test name
Test status
Simulation time 42744747 ps
CPU time 1.12 seconds
Started Jun 21 06:44:42 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 216688 kb
Host smart-4d263808-98b9-4827-8f12-74479838cd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978351775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3978351775
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_genbits.696920115
Short name T94
Test name
Test status
Simulation time 33290634 ps
CPU time 1.46 seconds
Started Jun 21 06:41:48 PM PDT 24
Finished Jun 21 06:42:53 PM PDT 24
Peak memory 219128 kb
Host smart-73213c54-85cf-4520-b915-574d5dcc5f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696920115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.696920115
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.175176494
Short name T914
Test name
Test status
Simulation time 317475081497 ps
CPU time 1910 seconds
Started Jun 21 06:41:56 PM PDT 24
Finished Jun 21 07:14:47 PM PDT 24
Peak memory 224592 kb
Host smart-2391cb1c-de9c-4bf5-a28c-f08afe20f2d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175176494 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.175176494
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/155.edn_genbits.3118028982
Short name T299
Test name
Test status
Simulation time 25154351 ps
CPU time 1.24 seconds
Started Jun 21 06:45:04 PM PDT 24
Finished Jun 21 06:45:33 PM PDT 24
Peak memory 217760 kb
Host smart-271fbaf6-ab89-45c8-bf06-80d791df4852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118028982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3118028982
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.1065250718
Short name T75
Test name
Test status
Simulation time 49002590 ps
CPU time 1.37 seconds
Started Jun 21 06:45:20 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 218012 kb
Host smart-40bfcd44-b6c2-4669-a019-d2a4977bebda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065250718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1065250718
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/220.edn_genbits.3876496567
Short name T304
Test name
Test status
Simulation time 40152344 ps
CPU time 1.68 seconds
Started Jun 21 06:45:33 PM PDT 24
Finished Jun 21 06:46:00 PM PDT 24
Peak memory 219192 kb
Host smart-c6cd90ea-b623-437e-ad19-7574902d668b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876496567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3876496567
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2239766000
Short name T863
Test name
Test status
Simulation time 103658656 ps
CPU time 1.6 seconds
Started Jun 21 06:45:49 PM PDT 24
Finished Jun 21 06:46:10 PM PDT 24
Peak memory 218236 kb
Host smart-eab51248-c194-4dc0-bdf0-5a8eba983fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239766000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2239766000
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3515955040
Short name T864
Test name
Test status
Simulation time 25590859 ps
CPU time 0.97 seconds
Started Jun 21 06:42:09 PM PDT 24
Finished Jun 21 06:43:03 PM PDT 24
Peak memory 215052 kb
Host smart-9eccf7fd-092b-4555-8b86-1b785379ed20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515955040 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3515955040
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/214.edn_genbits.1345974681
Short name T327
Test name
Test status
Simulation time 208048230 ps
CPU time 1.5 seconds
Started Jun 21 06:45:33 PM PDT 24
Finished Jun 21 06:46:00 PM PDT 24
Peak memory 218968 kb
Host smart-55852d4a-589e-42a2-adaa-4da0dfc6c595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345974681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1345974681
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_disable.2645460429
Short name T49
Test name
Test status
Simulation time 11503957 ps
CPU time 0.91 seconds
Started Jun 21 06:41:11 PM PDT 24
Finished Jun 21 06:42:14 PM PDT 24
Peak memory 214828 kb
Host smart-e6aaede3-15ab-4754-b720-5752b32b6d1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645460429 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2645460429
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/93.edn_alert.866046841
Short name T115
Test name
Test status
Simulation time 23009152 ps
CPU time 1.26 seconds
Started Jun 21 06:44:22 PM PDT 24
Finished Jun 21 06:45:01 PM PDT 24
Peak memory 218668 kb
Host smart-34a076b1-abc5-4ca4-9708-9f53ec730690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866046841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.866046841
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.589143143
Short name T780
Test name
Test status
Simulation time 50504591 ps
CPU time 1.82 seconds
Started Jun 21 06:44:39 PM PDT 24
Finished Jun 21 06:45:14 PM PDT 24
Peak memory 219276 kb
Host smart-5f3f93ab-6231-47d6-8fb9-bf0a30414711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589143143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.589143143
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3211290557
Short name T1058
Test name
Test status
Simulation time 204855707 ps
CPU time 1.23 seconds
Started Jun 21 06:35:56 PM PDT 24
Finished Jun 21 06:35:58 PM PDT 24
Peak memory 206356 kb
Host smart-a77ca076-b028-4a12-bbef-5636d006f3fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211290557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3211290557
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.901823765
Short name T1003
Test name
Test status
Simulation time 202423856 ps
CPU time 2.14 seconds
Started Jun 21 06:35:53 PM PDT 24
Finished Jun 21 06:35:57 PM PDT 24
Peak memory 206276 kb
Host smart-8239dd81-c2ed-4773-a823-c0f2ed26cfd4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901823765 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.901823765
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1212783933
Short name T255
Test name
Test status
Simulation time 41128075 ps
CPU time 0.89 seconds
Started Jun 21 06:35:54 PM PDT 24
Finished Jun 21 06:35:57 PM PDT 24
Peak memory 206352 kb
Host smart-68316226-d050-4b52-a252-80abb92182a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212783933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1212783933
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3687555939
Short name T1114
Test name
Test status
Simulation time 42266845 ps
CPU time 1.52 seconds
Started Jun 21 06:35:55 PM PDT 24
Finished Jun 21 06:35:58 PM PDT 24
Peak memory 214632 kb
Host smart-06f0dcc5-b0d4-472f-8e92-18744d9becaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687555939 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3687555939
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1758689489
Short name T1089
Test name
Test status
Simulation time 46836174 ps
CPU time 0.83 seconds
Started Jun 21 06:35:55 PM PDT 24
Finished Jun 21 06:35:57 PM PDT 24
Peak memory 206372 kb
Host smart-03e708ea-2b0d-4e47-a1ca-0f0a92415ebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758689489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1758689489
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3147560339
Short name T260
Test name
Test status
Simulation time 35714688 ps
CPU time 1.44 seconds
Started Jun 21 06:35:55 PM PDT 24
Finished Jun 21 06:35:58 PM PDT 24
Peak memory 206420 kb
Host smart-ae794ef2-6973-4240-a8a9-9e9c17d62e3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147560339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3147560339
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3998847228
Short name T1011
Test name
Test status
Simulation time 210707832 ps
CPU time 3.18 seconds
Started Jun 21 06:35:55 PM PDT 24
Finished Jun 21 06:36:00 PM PDT 24
Peak memory 214744 kb
Host smart-9fd9cfdf-0d00-40ef-bb5d-80c941c77e35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998847228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3998847228
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.708678500
Short name T1075
Test name
Test status
Simulation time 341030554 ps
CPU time 2.46 seconds
Started Jun 21 06:35:54 PM PDT 24
Finished Jun 21 06:35:58 PM PDT 24
Peak memory 206492 kb
Host smart-189c4ab4-500d-42b8-9886-e37d34ee2ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708678500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.708678500
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2339275310
Short name T1050
Test name
Test status
Simulation time 86408975 ps
CPU time 1.21 seconds
Started Jun 21 06:36:03 PM PDT 24
Finished Jun 21 06:36:06 PM PDT 24
Peak memory 206416 kb
Host smart-5b3fcf1b-cc16-457e-8786-b8cb1390bca8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339275310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2339275310
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1341007434
Short name T1070
Test name
Test status
Simulation time 96919888 ps
CPU time 3.13 seconds
Started Jun 21 06:36:04 PM PDT 24
Finished Jun 21 06:36:09 PM PDT 24
Peak memory 206472 kb
Host smart-32f04b1f-3ccf-49c3-84ab-501a8fadc1b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341007434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1341007434
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.292965851
Short name T251
Test name
Test status
Simulation time 16913932 ps
CPU time 1.01 seconds
Started Jun 21 06:36:02 PM PDT 24
Finished Jun 21 06:36:05 PM PDT 24
Peak memory 206228 kb
Host smart-7b866ca2-9c1b-47dc-b220-ba8ad74e16eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292965851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.292965851
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2646038340
Short name T999
Test name
Test status
Simulation time 22913075 ps
CPU time 1.26 seconds
Started Jun 21 06:36:03 PM PDT 24
Finished Jun 21 06:36:06 PM PDT 24
Peak memory 214724 kb
Host smart-2fa34738-6c0f-4be1-af1e-cc25efd6ff1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646038340 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2646038340
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3911230588
Short name T1028
Test name
Test status
Simulation time 43406514 ps
CPU time 0.95 seconds
Started Jun 21 06:36:04 PM PDT 24
Finished Jun 21 06:36:07 PM PDT 24
Peak memory 206344 kb
Host smart-2c7bc049-cb04-4f64-bdbe-18f867f12991
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911230588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3911230588
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3594206112
Short name T1032
Test name
Test status
Simulation time 14291778 ps
CPU time 0.85 seconds
Started Jun 21 06:36:04 PM PDT 24
Finished Jun 21 06:36:07 PM PDT 24
Peak memory 206352 kb
Host smart-67b48568-2ca9-4573-bf1a-d329e93e700e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594206112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3594206112
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3672693987
Short name T1120
Test name
Test status
Simulation time 36041413 ps
CPU time 1.03 seconds
Started Jun 21 06:36:04 PM PDT 24
Finished Jun 21 06:36:07 PM PDT 24
Peak memory 206416 kb
Host smart-15f402c0-e142-44ef-914e-3783f124d06b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672693987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3672693987
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3092906382
Short name T1090
Test name
Test status
Simulation time 45158441 ps
CPU time 3.04 seconds
Started Jun 21 06:36:06 PM PDT 24
Finished Jun 21 06:36:10 PM PDT 24
Peak memory 214632 kb
Host smart-845b689f-0963-4c87-8cec-5a8dd113cac9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092906382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3092906382
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1130298513
Short name T1046
Test name
Test status
Simulation time 325664276 ps
CPU time 2.41 seconds
Started Jun 21 06:36:04 PM PDT 24
Finished Jun 21 06:36:08 PM PDT 24
Peak memory 206388 kb
Host smart-ea677766-1261-4daf-9f63-35827c6edb75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130298513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1130298513
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1702570754
Short name T1079
Test name
Test status
Simulation time 301047269 ps
CPU time 1.27 seconds
Started Jun 21 06:36:34 PM PDT 24
Finished Jun 21 06:36:38 PM PDT 24
Peak memory 217172 kb
Host smart-7b2e4279-3785-4336-b4b9-32a79df36892
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702570754 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1702570754
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1573618994
Short name T1033
Test name
Test status
Simulation time 15730573 ps
CPU time 0.94 seconds
Started Jun 21 06:36:37 PM PDT 24
Finished Jun 21 06:36:41 PM PDT 24
Peak memory 206328 kb
Host smart-9d527ba1-639b-43f4-b5b6-ba476b81a985
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573618994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1573618994
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.4271295183
Short name T1087
Test name
Test status
Simulation time 13597263 ps
CPU time 0.87 seconds
Started Jun 21 06:36:34 PM PDT 24
Finished Jun 21 06:36:37 PM PDT 24
Peak memory 206372 kb
Host smart-a18595ab-6ba3-4e8c-a18a-fa741d37aeb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271295183 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.4271295183
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2742572269
Short name T1085
Test name
Test status
Simulation time 22075888 ps
CPU time 1.12 seconds
Started Jun 21 06:36:33 PM PDT 24
Finished Jun 21 06:36:37 PM PDT 24
Peak memory 206388 kb
Host smart-33e9415d-3cf4-4205-8592-9aa23126258e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742572269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2742572269
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3430570930
Short name T1123
Test name
Test status
Simulation time 320845200 ps
CPU time 3.79 seconds
Started Jun 21 06:36:36 PM PDT 24
Finished Jun 21 06:36:43 PM PDT 24
Peak memory 218528 kb
Host smart-39bc451c-55df-4327-a2d5-e9dfb531adec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430570930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3430570930
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2357428455
Short name T1102
Test name
Test status
Simulation time 106010540 ps
CPU time 1.69 seconds
Started Jun 21 06:36:35 PM PDT 24
Finished Jun 21 06:36:40 PM PDT 24
Peak memory 206600 kb
Host smart-356154c8-a6b9-494a-b34b-bc0ae61c6dd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357428455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2357428455
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3935966093
Short name T1073
Test name
Test status
Simulation time 29682854 ps
CPU time 1.17 seconds
Started Jun 21 06:36:35 PM PDT 24
Finished Jun 21 06:36:39 PM PDT 24
Peak memory 214684 kb
Host smart-3cefb986-094d-40ec-8425-6b093c667133
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935966093 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3935966093
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1586988294
Short name T1067
Test name
Test status
Simulation time 12672966 ps
CPU time 0.85 seconds
Started Jun 21 06:36:33 PM PDT 24
Finished Jun 21 06:36:36 PM PDT 24
Peak memory 206348 kb
Host smart-c8a3268b-1b57-4036-bd1f-bfaeb2883232
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586988294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1586988294
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.662448368
Short name T1045
Test name
Test status
Simulation time 20026322 ps
CPU time 0.82 seconds
Started Jun 21 06:36:34 PM PDT 24
Finished Jun 21 06:36:38 PM PDT 24
Peak memory 206260 kb
Host smart-0ea76178-5b0e-48a7-9324-3048068ec682
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662448368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.662448368
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2626649518
Short name T1121
Test name
Test status
Simulation time 21672938 ps
CPU time 0.98 seconds
Started Jun 21 06:36:36 PM PDT 24
Finished Jun 21 06:36:40 PM PDT 24
Peak memory 206408 kb
Host smart-fc07cb0a-7daa-47e8-bb5b-0dafda559417
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626649518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2626649518
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1757105633
Short name T1122
Test name
Test status
Simulation time 149711449 ps
CPU time 1.6 seconds
Started Jun 21 06:36:37 PM PDT 24
Finished Jun 21 06:36:41 PM PDT 24
Peak memory 214664 kb
Host smart-08b20177-9319-44c4-8f74-20bd04babad9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757105633 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1757105633
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.189026480
Short name T1037
Test name
Test status
Simulation time 71429694 ps
CPU time 1.92 seconds
Started Jun 21 06:36:34 PM PDT 24
Finished Jun 21 06:36:39 PM PDT 24
Peak memory 206564 kb
Host smart-4cc7e649-5185-4348-a493-1076f7fe7b3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189026480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.189026480
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2051138931
Short name T1001
Test name
Test status
Simulation time 29851251 ps
CPU time 1 seconds
Started Jun 21 06:36:34 PM PDT 24
Finished Jun 21 06:36:37 PM PDT 24
Peak memory 214768 kb
Host smart-f417b7e3-166c-48b8-89b8-88a307b533b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051138931 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2051138931
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.314453132
Short name T1118
Test name
Test status
Simulation time 16521260 ps
CPU time 0.92 seconds
Started Jun 21 06:36:35 PM PDT 24
Finished Jun 21 06:36:39 PM PDT 24
Peak memory 206304 kb
Host smart-53712754-41e9-4025-bfde-e6bc7b3b2caf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314453132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.314453132
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2353500516
Short name T1029
Test name
Test status
Simulation time 14500178 ps
CPU time 0.87 seconds
Started Jun 21 06:36:34 PM PDT 24
Finished Jun 21 06:36:37 PM PDT 24
Peak memory 206364 kb
Host smart-20f73471-7fdb-49fa-b038-3a59bd0c15cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353500516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2353500516
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1087305217
Short name T1064
Test name
Test status
Simulation time 61755715 ps
CPU time 1.36 seconds
Started Jun 21 06:36:37 PM PDT 24
Finished Jun 21 06:36:41 PM PDT 24
Peak memory 206492 kb
Host smart-ef016dc3-5758-4655-9eed-ac3e0bd397ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087305217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1087305217
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1684936506
Short name T1022
Test name
Test status
Simulation time 370916822 ps
CPU time 3.75 seconds
Started Jun 21 06:36:35 PM PDT 24
Finished Jun 21 06:36:42 PM PDT 24
Peak memory 214680 kb
Host smart-c8728cf9-df73-4b05-9799-d6f9599ffb0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684936506 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1684936506
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4090865896
Short name T1107
Test name
Test status
Simulation time 100812327 ps
CPU time 2.9 seconds
Started Jun 21 06:36:33 PM PDT 24
Finished Jun 21 06:36:39 PM PDT 24
Peak memory 214612 kb
Host smart-382dc8a9-c3cb-42da-9d4a-a1b7164b8e95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090865896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.4090865896
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2721398269
Short name T1109
Test name
Test status
Simulation time 129497364 ps
CPU time 1.32 seconds
Started Jun 21 06:36:36 PM PDT 24
Finished Jun 21 06:36:41 PM PDT 24
Peak memory 218032 kb
Host smart-d68a75ef-3fcc-4251-92eb-0dfe6664b16e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721398269 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2721398269
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2314239617
Short name T259
Test name
Test status
Simulation time 24814188 ps
CPU time 0.85 seconds
Started Jun 21 06:36:35 PM PDT 24
Finished Jun 21 06:36:38 PM PDT 24
Peak memory 206304 kb
Host smart-a1685344-8ba5-4854-9d17-2b6e9485f1c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314239617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2314239617
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2851859181
Short name T1080
Test name
Test status
Simulation time 26465858 ps
CPU time 0.86 seconds
Started Jun 21 06:36:34 PM PDT 24
Finished Jun 21 06:36:37 PM PDT 24
Peak memory 206364 kb
Host smart-19009166-4332-4d0c-96f3-218ee506a2d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851859181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2851859181
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.4293422801
Short name T1104
Test name
Test status
Simulation time 28939951 ps
CPU time 1.26 seconds
Started Jun 21 06:36:32 PM PDT 24
Finished Jun 21 06:36:35 PM PDT 24
Peak memory 206432 kb
Host smart-b05db4d9-dbdb-4c9c-becf-1bdec816960a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293422801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.4293422801
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1783824088
Short name T1094
Test name
Test status
Simulation time 41443147 ps
CPU time 2.66 seconds
Started Jun 21 06:36:35 PM PDT 24
Finished Jun 21 06:36:41 PM PDT 24
Peak memory 214780 kb
Host smart-7f084ffe-0201-4000-926f-e12dc59eac3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783824088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1783824088
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3414424854
Short name T1092
Test name
Test status
Simulation time 178562734 ps
CPU time 3.99 seconds
Started Jun 21 06:36:34 PM PDT 24
Finished Jun 21 06:36:41 PM PDT 24
Peak memory 206412 kb
Host smart-dcd72a24-4375-4d2f-8549-e09ff40c725a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414424854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3414424854
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.111212582
Short name T1048
Test name
Test status
Simulation time 105312587 ps
CPU time 1.21 seconds
Started Jun 21 06:36:43 PM PDT 24
Finished Jun 21 06:36:46 PM PDT 24
Peak memory 214776 kb
Host smart-746b41dd-810c-4485-bfba-b5a1bb965730
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111212582 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.111212582
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2103577715
Short name T250
Test name
Test status
Simulation time 17203961 ps
CPU time 0.99 seconds
Started Jun 21 06:36:43 PM PDT 24
Finished Jun 21 06:36:45 PM PDT 24
Peak memory 206328 kb
Host smart-b53bc2c3-8787-413f-a9b2-3cbb854e70fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103577715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2103577715
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3804971676
Short name T1041
Test name
Test status
Simulation time 32363901 ps
CPU time 0.93 seconds
Started Jun 21 06:36:43 PM PDT 24
Finished Jun 21 06:36:46 PM PDT 24
Peak memory 206348 kb
Host smart-f749b489-0136-44b0-b06d-5e8c0b69fc41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804971676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3804971676
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.664427118
Short name T1093
Test name
Test status
Simulation time 323217896 ps
CPU time 1.57 seconds
Started Jun 21 06:36:43 PM PDT 24
Finished Jun 21 06:36:46 PM PDT 24
Peak memory 206412 kb
Host smart-841035de-8174-4833-8d40-ee2143561524
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664427118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.664427118
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2378695338
Short name T1025
Test name
Test status
Simulation time 343622753 ps
CPU time 3.38 seconds
Started Jun 21 06:36:34 PM PDT 24
Finished Jun 21 06:36:40 PM PDT 24
Peak memory 214704 kb
Host smart-31fdd906-b59f-4ed0-beae-731d42fb2c60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378695338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2378695338
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.793286912
Short name T1128
Test name
Test status
Simulation time 494066889 ps
CPU time 8.66 seconds
Started Jun 21 06:36:43 PM PDT 24
Finished Jun 21 06:36:54 PM PDT 24
Peak memory 206640 kb
Host smart-979a33cf-f883-44a3-859f-70de5b2f1310
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793286912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.793286912
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2684291506
Short name T1021
Test name
Test status
Simulation time 32429551 ps
CPU time 1.51 seconds
Started Jun 21 06:36:43 PM PDT 24
Finished Jun 21 06:36:46 PM PDT 24
Peak memory 214856 kb
Host smart-3a4ccda7-f830-4a6d-83f9-f3ca08d2d7ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684291506 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2684291506
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2595551499
Short name T249
Test name
Test status
Simulation time 30392585 ps
CPU time 0.98 seconds
Started Jun 21 06:36:43 PM PDT 24
Finished Jun 21 06:36:46 PM PDT 24
Peak memory 206316 kb
Host smart-e73b83af-ae26-45a2-b628-0c0d8f5806ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595551499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2595551499
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.824991188
Short name T1005
Test name
Test status
Simulation time 185905425 ps
CPU time 0.91 seconds
Started Jun 21 06:36:44 PM PDT 24
Finished Jun 21 06:36:47 PM PDT 24
Peak memory 206380 kb
Host smart-63380e22-7632-44e9-a29f-9b6d3fafdf98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824991188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.824991188
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2293398360
Short name T258
Test name
Test status
Simulation time 73388580 ps
CPU time 1.13 seconds
Started Jun 21 06:36:43 PM PDT 24
Finished Jun 21 06:36:46 PM PDT 24
Peak memory 206564 kb
Host smart-e9371f27-2cd7-46ca-91d3-66118855e05d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293398360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2293398360
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3705214654
Short name T1000
Test name
Test status
Simulation time 152731555 ps
CPU time 1.51 seconds
Started Jun 21 06:36:43 PM PDT 24
Finished Jun 21 06:36:46 PM PDT 24
Peak memory 214636 kb
Host smart-e4708bf1-6c78-4670-baef-17eee0f26f34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705214654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3705214654
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3239234241
Short name T1014
Test name
Test status
Simulation time 37476963 ps
CPU time 1.53 seconds
Started Jun 21 06:36:42 PM PDT 24
Finished Jun 21 06:36:45 PM PDT 24
Peak memory 214708 kb
Host smart-ef88e907-6bb2-4cb4-8e70-1ef1c118bc8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239234241 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3239234241
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3994684857
Short name T252
Test name
Test status
Simulation time 23292264 ps
CPU time 0.9 seconds
Started Jun 21 06:36:44 PM PDT 24
Finished Jun 21 06:36:47 PM PDT 24
Peak memory 206348 kb
Host smart-1cd515c2-fea3-4026-bf55-ffd9a4e88d75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994684857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3994684857
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3845021628
Short name T1026
Test name
Test status
Simulation time 31710210 ps
CPU time 0.79 seconds
Started Jun 21 06:36:42 PM PDT 24
Finished Jun 21 06:36:45 PM PDT 24
Peak memory 206148 kb
Host smart-90390627-8abf-4a33-9f50-3eef9033ca11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845021628 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3845021628
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3335810459
Short name T242
Test name
Test status
Simulation time 77459104 ps
CPU time 1.17 seconds
Started Jun 21 06:36:44 PM PDT 24
Finished Jun 21 06:36:47 PM PDT 24
Peak memory 206472 kb
Host smart-1f213390-c807-4abc-ac0b-d8eb1df06074
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335810459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3335810459
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.642794533
Short name T1023
Test name
Test status
Simulation time 176448198 ps
CPU time 3.5 seconds
Started Jun 21 06:36:44 PM PDT 24
Finished Jun 21 06:36:49 PM PDT 24
Peak memory 214664 kb
Host smart-aacb54ad-265e-442a-bc4a-25e313c4ef9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642794533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.642794533
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4154179587
Short name T281
Test name
Test status
Simulation time 67776258 ps
CPU time 1.45 seconds
Started Jun 21 06:36:43 PM PDT 24
Finished Jun 21 06:36:46 PM PDT 24
Peak memory 206660 kb
Host smart-90c6fed8-dac8-4b10-86e1-7a78a7a0f3d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154179587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.4154179587
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1861216791
Short name T1006
Test name
Test status
Simulation time 60420684 ps
CPU time 1.22 seconds
Started Jun 21 06:36:54 PM PDT 24
Finished Jun 21 06:36:58 PM PDT 24
Peak memory 214684 kb
Host smart-8181043d-565a-4249-ad1d-b4f569f7330f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861216791 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1861216791
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1282588412
Short name T1078
Test name
Test status
Simulation time 17537002 ps
CPU time 0.96 seconds
Started Jun 21 06:36:55 PM PDT 24
Finished Jun 21 06:36:58 PM PDT 24
Peak memory 206364 kb
Host smart-0758079e-04b6-4a77-a7e9-18178fdb9b5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282588412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1282588412
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2273976325
Short name T1052
Test name
Test status
Simulation time 15371100 ps
CPU time 0.87 seconds
Started Jun 21 06:36:43 PM PDT 24
Finished Jun 21 06:36:45 PM PDT 24
Peak memory 206384 kb
Host smart-c9c42ec0-1cf7-4727-b88e-a334c4d999f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273976325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2273976325
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2162778703
Short name T1076
Test name
Test status
Simulation time 147919936 ps
CPU time 0.99 seconds
Started Jun 21 06:36:55 PM PDT 24
Finished Jun 21 06:36:58 PM PDT 24
Peak memory 206412 kb
Host smart-c5c70345-1736-450b-9914-880e468e3625
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162778703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2162778703
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2188037422
Short name T1010
Test name
Test status
Simulation time 135144541 ps
CPU time 2.72 seconds
Started Jun 21 06:36:43 PM PDT 24
Finished Jun 21 06:36:47 PM PDT 24
Peak memory 214744 kb
Host smart-871cde64-15cd-4187-8f78-f422a6478383
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188037422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2188037422
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2168184961
Short name T282
Test name
Test status
Simulation time 156338034 ps
CPU time 3.01 seconds
Started Jun 21 06:36:44 PM PDT 24
Finished Jun 21 06:36:49 PM PDT 24
Peak memory 206420 kb
Host smart-69c3c62e-eab2-455e-9790-1563080e5f2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168184961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2168184961
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2370683697
Short name T1047
Test name
Test status
Simulation time 80825181 ps
CPU time 1.16 seconds
Started Jun 21 06:36:53 PM PDT 24
Finished Jun 21 06:36:57 PM PDT 24
Peak memory 214808 kb
Host smart-fe147f2e-41a4-4c62-a378-4729a3938303
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370683697 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2370683697
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.546409886
Short name T254
Test name
Test status
Simulation time 19125690 ps
CPU time 1.08 seconds
Started Jun 21 06:36:53 PM PDT 24
Finished Jun 21 06:36:57 PM PDT 24
Peak memory 206348 kb
Host smart-09f5d672-0407-48e7-9d69-cb4707578720
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546409886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.546409886
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3487543286
Short name T1056
Test name
Test status
Simulation time 19902795 ps
CPU time 0.87 seconds
Started Jun 21 06:36:52 PM PDT 24
Finished Jun 21 06:36:55 PM PDT 24
Peak memory 206324 kb
Host smart-5905ab3b-3370-4645-bc55-e227c26cb0b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487543286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3487543286
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1782563032
Short name T1116
Test name
Test status
Simulation time 28400883 ps
CPU time 1.15 seconds
Started Jun 21 06:36:52 PM PDT 24
Finished Jun 21 06:36:55 PM PDT 24
Peak memory 206480 kb
Host smart-1d7287b4-db80-482c-92b5-ebbb2ebce948
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782563032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1782563032
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.258830098
Short name T1117
Test name
Test status
Simulation time 21244033 ps
CPU time 1.54 seconds
Started Jun 21 06:36:53 PM PDT 24
Finished Jun 21 06:36:57 PM PDT 24
Peak memory 214856 kb
Host smart-a888a0d7-a633-4237-8846-b52d57609523
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258830098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.258830098
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1326974481
Short name T1112
Test name
Test status
Simulation time 25782705 ps
CPU time 1.27 seconds
Started Jun 21 06:36:54 PM PDT 24
Finished Jun 21 06:36:57 PM PDT 24
Peak memory 214932 kb
Host smart-43c18986-66b7-4591-a547-09f84a3b6fc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326974481 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1326974481
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1868213317
Short name T247
Test name
Test status
Simulation time 53470443 ps
CPU time 0.9 seconds
Started Jun 21 06:36:53 PM PDT 24
Finished Jun 21 06:36:57 PM PDT 24
Peak memory 206344 kb
Host smart-0fb71a84-cc1f-4fdf-825f-ab6d49061e12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868213317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1868213317
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1843261413
Short name T1040
Test name
Test status
Simulation time 20472373 ps
CPU time 0.83 seconds
Started Jun 21 06:36:53 PM PDT 24
Finished Jun 21 06:36:56 PM PDT 24
Peak memory 206268 kb
Host smart-8f7b61cb-352a-4e52-8bb3-5df74f3a4bea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843261413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1843261413
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1418797943
Short name T1106
Test name
Test status
Simulation time 125943524 ps
CPU time 1.41 seconds
Started Jun 21 06:36:53 PM PDT 24
Finished Jun 21 06:36:55 PM PDT 24
Peak memory 206372 kb
Host smart-0da56af6-498e-4992-8e4d-768a5dad9232
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418797943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1418797943
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.753803018
Short name T1101
Test name
Test status
Simulation time 88421462 ps
CPU time 2.38 seconds
Started Jun 21 06:36:52 PM PDT 24
Finished Jun 21 06:36:55 PM PDT 24
Peak memory 222712 kb
Host smart-b99615e0-665a-4bec-a316-5524cf7e4a30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753803018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.753803018
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2911726695
Short name T1063
Test name
Test status
Simulation time 44147302 ps
CPU time 1.63 seconds
Started Jun 21 06:36:54 PM PDT 24
Finished Jun 21 06:36:58 PM PDT 24
Peak memory 214604 kb
Host smart-a30438da-b287-4416-8bba-0051d42fb8d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911726695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2911726695
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3428541061
Short name T1039
Test name
Test status
Simulation time 49511651 ps
CPU time 1.65 seconds
Started Jun 21 06:36:11 PM PDT 24
Finished Jun 21 06:36:15 PM PDT 24
Peak memory 206352 kb
Host smart-0090d5eb-47ac-43d8-a050-0a1fe8caa352
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428541061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3428541061
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.688608
Short name T253
Test name
Test status
Simulation time 166188009 ps
CPU time 3.87 seconds
Started Jun 21 06:36:11 PM PDT 24
Finished Jun 21 06:36:17 PM PDT 24
Peak memory 206352 kb
Host smart-5a1c9394-d28f-4725-91cd-9aac95a90e70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.688608
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3866368656
Short name T1086
Test name
Test status
Simulation time 73238825 ps
CPU time 0.87 seconds
Started Jun 21 06:36:14 PM PDT 24
Finished Jun 21 06:36:18 PM PDT 24
Peak memory 206368 kb
Host smart-4065800e-0803-4438-8c4b-a7fd3aa570e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866368656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3866368656
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1681128595
Short name T1012
Test name
Test status
Simulation time 78369964 ps
CPU time 1.05 seconds
Started Jun 21 06:36:11 PM PDT 24
Finished Jun 21 06:36:13 PM PDT 24
Peak memory 214676 kb
Host smart-79de4cbb-fb4c-4906-a742-4b084bb7ef30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681128595 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1681128595
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1308559685
Short name T1019
Test name
Test status
Simulation time 23212053 ps
CPU time 0.88 seconds
Started Jun 21 06:36:11 PM PDT 24
Finished Jun 21 06:36:13 PM PDT 24
Peak memory 206344 kb
Host smart-d3ba1ae7-7908-49e2-bea3-7f14271c57c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308559685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1308559685
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1681524393
Short name T1105
Test name
Test status
Simulation time 12367888 ps
CPU time 0.84 seconds
Started Jun 21 06:36:11 PM PDT 24
Finished Jun 21 06:36:13 PM PDT 24
Peak memory 206348 kb
Host smart-5876344b-2766-4e11-a8c0-d7314856b395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681524393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1681524393
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3550443306
Short name T1127
Test name
Test status
Simulation time 67063652 ps
CPU time 1.01 seconds
Started Jun 21 06:36:15 PM PDT 24
Finished Jun 21 06:36:18 PM PDT 24
Peak memory 206344 kb
Host smart-d0020a82-7093-4cdd-9b08-13800de1f5e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550443306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3550443306
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3887095492
Short name T998
Test name
Test status
Simulation time 161141048 ps
CPU time 3.96 seconds
Started Jun 21 06:36:03 PM PDT 24
Finished Jun 21 06:36:09 PM PDT 24
Peak memory 218796 kb
Host smart-f64c71b9-b2de-41a1-9d77-72792dfa1b3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887095492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3887095492
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1043516333
Short name T276
Test name
Test status
Simulation time 149114348 ps
CPU time 2.33 seconds
Started Jun 21 06:36:03 PM PDT 24
Finished Jun 21 06:36:07 PM PDT 24
Peak memory 206492 kb
Host smart-4a2f50d0-c4e7-445b-b2bc-d5d352fc8399
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043516333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1043516333
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2619236739
Short name T1020
Test name
Test status
Simulation time 32425518 ps
CPU time 0.84 seconds
Started Jun 21 06:36:53 PM PDT 24
Finished Jun 21 06:36:55 PM PDT 24
Peak memory 206284 kb
Host smart-599f759e-1954-4915-a320-6ec9b4167b09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619236739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2619236739
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.254887207
Short name T1027
Test name
Test status
Simulation time 16333048 ps
CPU time 1.01 seconds
Started Jun 21 06:36:54 PM PDT 24
Finished Jun 21 06:36:57 PM PDT 24
Peak memory 206364 kb
Host smart-94c09dac-cf74-49c8-b3bb-5e6f496d8e1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254887207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.254887207
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1734512108
Short name T1057
Test name
Test status
Simulation time 45743034 ps
CPU time 0.82 seconds
Started Jun 21 06:36:54 PM PDT 24
Finished Jun 21 06:36:57 PM PDT 24
Peak memory 206348 kb
Host smart-1daafe1b-b7bc-4c4d-9422-e4de59b0c46f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734512108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1734512108
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3094865703
Short name T1124
Test name
Test status
Simulation time 22223268 ps
CPU time 0.85 seconds
Started Jun 21 06:36:54 PM PDT 24
Finished Jun 21 06:36:57 PM PDT 24
Peak memory 206304 kb
Host smart-9c7b8b97-a096-4ce0-8a3b-dbfbcfeb6aaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094865703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3094865703
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.805335141
Short name T997
Test name
Test status
Simulation time 34027398 ps
CPU time 0.81 seconds
Started Jun 21 06:36:53 PM PDT 24
Finished Jun 21 06:36:55 PM PDT 24
Peak memory 206256 kb
Host smart-d75862d1-003e-4bfb-b780-fd8adc6421f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805335141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.805335141
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2747598930
Short name T1100
Test name
Test status
Simulation time 31081592 ps
CPU time 0.83 seconds
Started Jun 21 06:36:56 PM PDT 24
Finished Jun 21 06:36:59 PM PDT 24
Peak memory 206264 kb
Host smart-82e0aeba-85cf-41d9-a8cb-a6bcb92980f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747598930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2747598930
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1805196562
Short name T1096
Test name
Test status
Simulation time 40483974 ps
CPU time 0.89 seconds
Started Jun 21 06:36:53 PM PDT 24
Finished Jun 21 06:36:56 PM PDT 24
Peak memory 206356 kb
Host smart-6d6e0f30-1aa4-459d-8706-483da3adf606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805196562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1805196562
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1730765451
Short name T1129
Test name
Test status
Simulation time 15189117 ps
CPU time 0.93 seconds
Started Jun 21 06:36:52 PM PDT 24
Finished Jun 21 06:36:54 PM PDT 24
Peak memory 206368 kb
Host smart-be5db248-0d3a-4f63-9270-22fe5fca7f97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730765451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1730765451
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.85453507
Short name T1018
Test name
Test status
Simulation time 24674192 ps
CPU time 0.88 seconds
Started Jun 21 06:37:00 PM PDT 24
Finished Jun 21 06:37:04 PM PDT 24
Peak memory 206384 kb
Host smart-5ef735b6-6b48-4993-ba01-2014d32cc9d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85453507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.85453507
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1913393396
Short name T1103
Test name
Test status
Simulation time 41193053 ps
CPU time 0.93 seconds
Started Jun 21 06:37:01 PM PDT 24
Finished Jun 21 06:37:04 PM PDT 24
Peak memory 206360 kb
Host smart-9bbc4607-435a-4075-9daa-5a0ce8c5afd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913393396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1913393396
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1345263004
Short name T1017
Test name
Test status
Simulation time 14955527 ps
CPU time 1.04 seconds
Started Jun 21 06:36:14 PM PDT 24
Finished Jun 21 06:36:17 PM PDT 24
Peak memory 206392 kb
Host smart-f2d19ec6-37e9-4ae3-b444-2912895888da
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345263004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1345263004
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2283008405
Short name T1062
Test name
Test status
Simulation time 370557234 ps
CPU time 2.95 seconds
Started Jun 21 06:36:11 PM PDT 24
Finished Jun 21 06:36:15 PM PDT 24
Peak memory 206240 kb
Host smart-bf6740f7-39d4-4589-b274-36dab93420ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283008405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2283008405
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2540337414
Short name T1110
Test name
Test status
Simulation time 24702260 ps
CPU time 0.88 seconds
Started Jun 21 06:36:14 PM PDT 24
Finished Jun 21 06:36:17 PM PDT 24
Peak memory 206344 kb
Host smart-16ca1624-71ef-4740-aac0-d157cf8d6ece
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540337414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2540337414
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1800032629
Short name T1004
Test name
Test status
Simulation time 64091992 ps
CPU time 1.17 seconds
Started Jun 21 06:36:11 PM PDT 24
Finished Jun 21 06:36:14 PM PDT 24
Peak memory 214836 kb
Host smart-9ea3f0d6-e828-412d-b712-388963a8da02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800032629 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1800032629
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.593795529
Short name T244
Test name
Test status
Simulation time 38015093 ps
CPU time 0.86 seconds
Started Jun 21 06:36:11 PM PDT 24
Finished Jun 21 06:36:14 PM PDT 24
Peak memory 206304 kb
Host smart-2bc1bb10-3820-4c22-852d-46607f941ae0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593795529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.593795529
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.4136704502
Short name T1098
Test name
Test status
Simulation time 26948303 ps
CPU time 0.76 seconds
Started Jun 21 06:36:14 PM PDT 24
Finished Jun 21 06:36:17 PM PDT 24
Peak memory 206276 kb
Host smart-fe6dfdf6-4dad-4293-b4fe-6092e4d30c4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136704502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.4136704502
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1946943544
Short name T1081
Test name
Test status
Simulation time 75425020 ps
CPU time 1.08 seconds
Started Jun 21 06:36:11 PM PDT 24
Finished Jun 21 06:36:14 PM PDT 24
Peak memory 206416 kb
Host smart-82d2ef88-4ad9-4404-828b-b448e242a132
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946943544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1946943544
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3378506363
Short name T1084
Test name
Test status
Simulation time 103941131 ps
CPU time 2.35 seconds
Started Jun 21 06:36:12 PM PDT 24
Finished Jun 21 06:36:16 PM PDT 24
Peak memory 214636 kb
Host smart-dcdf165a-c076-4164-9b5d-7dbae1ad692a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378506363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3378506363
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.623675755
Short name T1072
Test name
Test status
Simulation time 286367186 ps
CPU time 2.24 seconds
Started Jun 21 06:36:15 PM PDT 24
Finished Jun 21 06:36:20 PM PDT 24
Peak memory 206412 kb
Host smart-486cbf63-78dd-4fe7-a46a-b4e70aaa4dbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623675755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.623675755
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2382271168
Short name T1095
Test name
Test status
Simulation time 59110168 ps
CPU time 0.82 seconds
Started Jun 21 06:37:01 PM PDT 24
Finished Jun 21 06:37:05 PM PDT 24
Peak memory 206264 kb
Host smart-f16f5b00-73da-4e4d-9a92-91f2678e03a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382271168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2382271168
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1430888379
Short name T1024
Test name
Test status
Simulation time 17122967 ps
CPU time 0.86 seconds
Started Jun 21 06:37:02 PM PDT 24
Finished Jun 21 06:37:07 PM PDT 24
Peak memory 206368 kb
Host smart-ab8a2d8a-cd83-47e8-9fe0-3a8336ddb14f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430888379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1430888379
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3417595707
Short name T1061
Test name
Test status
Simulation time 17223468 ps
CPU time 0.93 seconds
Started Jun 21 06:37:03 PM PDT 24
Finished Jun 21 06:37:08 PM PDT 24
Peak memory 206356 kb
Host smart-b0cb8fd3-75d8-44c2-a56c-1c852816a788
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417595707 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3417595707
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.227246535
Short name T1115
Test name
Test status
Simulation time 15793083 ps
CPU time 0.88 seconds
Started Jun 21 06:37:02 PM PDT 24
Finished Jun 21 06:37:06 PM PDT 24
Peak memory 206348 kb
Host smart-2c49ca5b-c82f-405a-903c-fd291fb2e7c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227246535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.227246535
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2747963214
Short name T1054
Test name
Test status
Simulation time 10897040 ps
CPU time 0.86 seconds
Started Jun 21 06:37:02 PM PDT 24
Finished Jun 21 06:37:07 PM PDT 24
Peak memory 206368 kb
Host smart-6d3f480f-5b65-403d-912c-95de15f2848b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747963214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2747963214
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1392508711
Short name T1009
Test name
Test status
Simulation time 22650777 ps
CPU time 0.87 seconds
Started Jun 21 06:37:04 PM PDT 24
Finished Jun 21 06:37:09 PM PDT 24
Peak memory 206308 kb
Host smart-e6b4bcd4-0ac9-4260-9bba-9c3a473082e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392508711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1392508711
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3534824427
Short name T1069
Test name
Test status
Simulation time 21636869 ps
CPU time 0.82 seconds
Started Jun 21 06:37:00 PM PDT 24
Finished Jun 21 06:37:04 PM PDT 24
Peak memory 206360 kb
Host smart-7c585cbe-0028-42bc-b719-99845591fb7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534824427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3534824427
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1648513303
Short name T1111
Test name
Test status
Simulation time 80210533 ps
CPU time 0.84 seconds
Started Jun 21 06:37:02 PM PDT 24
Finished Jun 21 06:37:06 PM PDT 24
Peak memory 206268 kb
Host smart-89d74f29-13ee-4ce7-b1c9-8e326930f2ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648513303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1648513303
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.640823986
Short name T1035
Test name
Test status
Simulation time 13012910 ps
CPU time 0.91 seconds
Started Jun 21 06:37:04 PM PDT 24
Finished Jun 21 06:37:09 PM PDT 24
Peak memory 206304 kb
Host smart-19769a51-0d04-4434-a567-9579012cdde6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640823986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.640823986
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3090566913
Short name T1083
Test name
Test status
Simulation time 31887219 ps
CPU time 0.83 seconds
Started Jun 21 06:37:00 PM PDT 24
Finished Jun 21 06:37:03 PM PDT 24
Peak memory 206272 kb
Host smart-fe3de3a1-ce2a-4e23-aad6-63b0a3343240
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090566913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3090566913
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3264662079
Short name T256
Test name
Test status
Simulation time 19661776 ps
CPU time 1.07 seconds
Started Jun 21 06:36:22 PM PDT 24
Finished Jun 21 06:36:25 PM PDT 24
Peak memory 206364 kb
Host smart-5181d1d9-61ad-4797-8a46-64fefd6d3819
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264662079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3264662079
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2498688824
Short name T1034
Test name
Test status
Simulation time 275900345 ps
CPU time 3.85 seconds
Started Jun 21 06:36:18 PM PDT 24
Finished Jun 21 06:36:24 PM PDT 24
Peak memory 206356 kb
Host smart-47c31248-5433-4796-9f79-64a0305b9e63
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498688824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2498688824
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2030099958
Short name T1059
Test name
Test status
Simulation time 16001828 ps
CPU time 0.95 seconds
Started Jun 21 06:36:18 PM PDT 24
Finished Jun 21 06:36:21 PM PDT 24
Peak memory 206348 kb
Host smart-d7b8940c-2cbf-4608-9d0f-d02a2ab095f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030099958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2030099958
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1989989714
Short name T995
Test name
Test status
Simulation time 22959228 ps
CPU time 1.26 seconds
Started Jun 21 06:36:18 PM PDT 24
Finished Jun 21 06:36:22 PM PDT 24
Peak memory 214808 kb
Host smart-6ba3fb18-2fce-4f69-8d75-344055c9772d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989989714 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1989989714
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2797168747
Short name T1043
Test name
Test status
Simulation time 11083821 ps
CPU time 0.83 seconds
Started Jun 21 06:36:18 PM PDT 24
Finished Jun 21 06:36:21 PM PDT 24
Peak memory 206260 kb
Host smart-7f6e3eb7-8ddc-4d59-b1c7-7a8b324f1dc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797168747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2797168747
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.4139844483
Short name T1108
Test name
Test status
Simulation time 61074841 ps
CPU time 0.79 seconds
Started Jun 21 06:36:20 PM PDT 24
Finished Jun 21 06:36:23 PM PDT 24
Peak memory 206276 kb
Host smart-af04751f-7c64-4eb1-8564-42de54af58e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139844483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.4139844483
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4055352963
Short name T240
Test name
Test status
Simulation time 63090400 ps
CPU time 1.09 seconds
Started Jun 21 06:36:17 PM PDT 24
Finished Jun 21 06:36:21 PM PDT 24
Peak memory 206504 kb
Host smart-eec6020a-3c25-4613-8259-9fcee784e7ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055352963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.4055352963
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3971058463
Short name T1055
Test name
Test status
Simulation time 102957023 ps
CPU time 4.01 seconds
Started Jun 21 06:36:22 PM PDT 24
Finished Jun 21 06:36:28 PM PDT 24
Peak memory 214692 kb
Host smart-312c726f-2842-4ac5-af30-617fc5b661e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971058463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3971058463
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2194602081
Short name T1097
Test name
Test status
Simulation time 185832286 ps
CPU time 2.54 seconds
Started Jun 21 06:36:18 PM PDT 24
Finished Jun 21 06:36:23 PM PDT 24
Peak memory 214612 kb
Host smart-ba2bb364-350b-41af-acd5-ba6134a2d4ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194602081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2194602081
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1958121898
Short name T1126
Test name
Test status
Simulation time 91151371 ps
CPU time 0.88 seconds
Started Jun 21 06:37:05 PM PDT 24
Finished Jun 21 06:37:10 PM PDT 24
Peak memory 206336 kb
Host smart-1e792e6b-4544-4fe5-8cb9-cc4e9742d82a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958121898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1958121898
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2875912644
Short name T1068
Test name
Test status
Simulation time 16156319 ps
CPU time 0.96 seconds
Started Jun 21 06:37:02 PM PDT 24
Finished Jun 21 06:37:07 PM PDT 24
Peak memory 206356 kb
Host smart-40bfb3d8-7c72-4373-b253-ff80f2adf0dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875912644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2875912644
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2734415061
Short name T1113
Test name
Test status
Simulation time 57033211 ps
CPU time 0.87 seconds
Started Jun 21 06:37:01 PM PDT 24
Finished Jun 21 06:37:06 PM PDT 24
Peak memory 206268 kb
Host smart-dc3dda90-7c58-4fb2-aea8-6c1fb0d6a75b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734415061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2734415061
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2898127495
Short name T1007
Test name
Test status
Simulation time 80672111 ps
CPU time 0.91 seconds
Started Jun 21 06:37:02 PM PDT 24
Finished Jun 21 06:37:06 PM PDT 24
Peak memory 206336 kb
Host smart-9126d1da-2081-43f1-8779-0ca9a284e7af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898127495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2898127495
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.4012968887
Short name T1130
Test name
Test status
Simulation time 31876977 ps
CPU time 0.85 seconds
Started Jun 21 06:37:01 PM PDT 24
Finished Jun 21 06:37:04 PM PDT 24
Peak memory 206144 kb
Host smart-9b4a0ab6-a072-41db-acaa-953ec256b61f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012968887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.4012968887
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3649539267
Short name T1053
Test name
Test status
Simulation time 16306741 ps
CPU time 1 seconds
Started Jun 21 06:37:01 PM PDT 24
Finished Jun 21 06:37:06 PM PDT 24
Peak memory 206368 kb
Host smart-a85bea68-de78-4e24-9a24-e952b02183a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649539267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3649539267
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2208368298
Short name T1008
Test name
Test status
Simulation time 14360577 ps
CPU time 0.94 seconds
Started Jun 21 06:37:02 PM PDT 24
Finished Jun 21 06:37:06 PM PDT 24
Peak memory 206352 kb
Host smart-5afc92be-eb41-46db-92e5-12846af6b12f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208368298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2208368298
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2941110905
Short name T1016
Test name
Test status
Simulation time 30099867 ps
CPU time 0.83 seconds
Started Jun 21 06:37:00 PM PDT 24
Finished Jun 21 06:37:04 PM PDT 24
Peak memory 206280 kb
Host smart-da4a853e-679e-4668-b2b6-bc3534b81fb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941110905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2941110905
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2490285662
Short name T1091
Test name
Test status
Simulation time 18734920 ps
CPU time 0.92 seconds
Started Jun 21 06:37:00 PM PDT 24
Finished Jun 21 06:37:03 PM PDT 24
Peak memory 206360 kb
Host smart-8513c819-22de-4996-9d38-5e7b44dc9419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490285662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2490285662
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2162223104
Short name T1013
Test name
Test status
Simulation time 39179390 ps
CPU time 0.83 seconds
Started Jun 21 06:37:02 PM PDT 24
Finished Jun 21 06:37:06 PM PDT 24
Peak memory 206256 kb
Host smart-107d79ca-ee95-4017-b8b5-4370165d246b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162223104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2162223104
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1937985919
Short name T1088
Test name
Test status
Simulation time 29530155 ps
CPU time 1.38 seconds
Started Jun 21 06:36:19 PM PDT 24
Finished Jun 21 06:36:23 PM PDT 24
Peak memory 214684 kb
Host smart-5f91e1de-f025-4e03-9564-f54103e93eb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937985919 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1937985919
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3817049117
Short name T246
Test name
Test status
Simulation time 18816983 ps
CPU time 0.83 seconds
Started Jun 21 06:36:19 PM PDT 24
Finished Jun 21 06:36:22 PM PDT 24
Peak memory 206208 kb
Host smart-00f0cdc7-f4c7-4d4b-bc4e-6b9fea4fe42c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817049117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3817049117
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3431705937
Short name T1065
Test name
Test status
Simulation time 29143219 ps
CPU time 0.82 seconds
Started Jun 21 06:36:19 PM PDT 24
Finished Jun 21 06:36:22 PM PDT 24
Peak memory 206260 kb
Host smart-065edadf-6e54-47eb-a03f-0d0300d4071f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431705937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3431705937
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3655807652
Short name T1125
Test name
Test status
Simulation time 40363052 ps
CPU time 1.14 seconds
Started Jun 21 06:36:21 PM PDT 24
Finished Jun 21 06:36:24 PM PDT 24
Peak memory 206452 kb
Host smart-f031c679-c127-4fa4-ad2f-75e0a44c66c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655807652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3655807652
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3515190210
Short name T1002
Test name
Test status
Simulation time 155128940 ps
CPU time 2.57 seconds
Started Jun 21 06:36:18 PM PDT 24
Finished Jun 21 06:36:23 PM PDT 24
Peak memory 214816 kb
Host smart-d949869e-7f6b-4969-b3f2-7f9f2e28af9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515190210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3515190210
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2513555423
Short name T1015
Test name
Test status
Simulation time 175463194 ps
CPU time 1.61 seconds
Started Jun 21 06:36:19 PM PDT 24
Finished Jun 21 06:36:23 PM PDT 24
Peak memory 206556 kb
Host smart-4084250c-8430-4897-9045-6836e0ccd994
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513555423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2513555423
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2750505549
Short name T1044
Test name
Test status
Simulation time 14667375 ps
CPU time 0.99 seconds
Started Jun 21 06:36:26 PM PDT 24
Finished Jun 21 06:36:29 PM PDT 24
Peak memory 214832 kb
Host smart-2118214f-8720-4732-b48b-6676f597594e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750505549 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2750505549
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2669857287
Short name T243
Test name
Test status
Simulation time 15464306 ps
CPU time 0.92 seconds
Started Jun 21 06:36:26 PM PDT 24
Finished Jun 21 06:36:30 PM PDT 24
Peak memory 206328 kb
Host smart-5708ebc2-9c68-4f8e-9cc4-e3b1cc3eb284
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669857287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2669857287
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1461713186
Short name T1049
Test name
Test status
Simulation time 127909434 ps
CPU time 0.8 seconds
Started Jun 21 06:36:19 PM PDT 24
Finished Jun 21 06:36:22 PM PDT 24
Peak memory 206256 kb
Host smart-987fd9a8-81e7-496d-b35c-0ad9d22d4b16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461713186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1461713186
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2026100406
Short name T257
Test name
Test status
Simulation time 63711593 ps
CPU time 1.41 seconds
Started Jun 21 06:36:26 PM PDT 24
Finished Jun 21 06:36:29 PM PDT 24
Peak memory 206408 kb
Host smart-f561405c-74f2-461a-af9b-7af8df3be3d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026100406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2026100406
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3366629461
Short name T1074
Test name
Test status
Simulation time 315908474 ps
CPU time 2.91 seconds
Started Jun 21 06:36:16 PM PDT 24
Finished Jun 21 06:36:22 PM PDT 24
Peak memory 214804 kb
Host smart-bbfbbdad-6eca-41a1-9fe9-6930879461a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366629461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3366629461
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2879763383
Short name T283
Test name
Test status
Simulation time 223142460 ps
CPU time 4.25 seconds
Started Jun 21 06:36:18 PM PDT 24
Finished Jun 21 06:36:25 PM PDT 24
Peak memory 206440 kb
Host smart-b44386ca-f1d8-4355-9eae-86444f534cb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879763383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2879763383
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1363914695
Short name T1051
Test name
Test status
Simulation time 15809681 ps
CPU time 1.02 seconds
Started Jun 21 06:36:28 PM PDT 24
Finished Jun 21 06:36:32 PM PDT 24
Peak memory 206492 kb
Host smart-4b97743f-5e2b-41ab-967f-4ecb9452199e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363914695 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1363914695
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3367629695
Short name T1031
Test name
Test status
Simulation time 31491437 ps
CPU time 0.97 seconds
Started Jun 21 06:36:26 PM PDT 24
Finished Jun 21 06:36:30 PM PDT 24
Peak memory 206376 kb
Host smart-9cd0aeb3-bd26-45cd-8638-e813df3fb085
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367629695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3367629695
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2863400882
Short name T1038
Test name
Test status
Simulation time 38793618 ps
CPU time 0.83 seconds
Started Jun 21 06:36:27 PM PDT 24
Finished Jun 21 06:36:30 PM PDT 24
Peak memory 206352 kb
Host smart-e9e48ccf-b6f5-458f-a371-d37aa8a18a58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863400882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2863400882
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.75702053
Short name T1077
Test name
Test status
Simulation time 14237552 ps
CPU time 1.01 seconds
Started Jun 21 06:36:28 PM PDT 24
Finished Jun 21 06:36:32 PM PDT 24
Peak memory 206568 kb
Host smart-a4b8297d-f9b7-428f-aaa3-94b92084ad72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75702053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outs
tanding.75702053
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.178281654
Short name T1036
Test name
Test status
Simulation time 44981902 ps
CPU time 2.98 seconds
Started Jun 21 06:36:28 PM PDT 24
Finished Jun 21 06:36:34 PM PDT 24
Peak memory 222868 kb
Host smart-9fd46ab6-1c75-4425-961c-e7567d0c0493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178281654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.178281654
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2637393610
Short name T274
Test name
Test status
Simulation time 88785433 ps
CPU time 1.63 seconds
Started Jun 21 06:36:26 PM PDT 24
Finished Jun 21 06:36:30 PM PDT 24
Peak memory 214588 kb
Host smart-991e3662-f1db-4629-9003-ba4fb4bce79b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637393610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2637393610
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2019618664
Short name T1066
Test name
Test status
Simulation time 108409459 ps
CPU time 1.91 seconds
Started Jun 21 06:36:29 PM PDT 24
Finished Jun 21 06:36:33 PM PDT 24
Peak memory 214700 kb
Host smart-98e62e0a-5ce9-491a-8e38-d155383d64b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019618664 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2019618664
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.422005585
Short name T248
Test name
Test status
Simulation time 19599360 ps
CPU time 0.89 seconds
Started Jun 21 06:36:26 PM PDT 24
Finished Jun 21 06:36:30 PM PDT 24
Peak memory 206348 kb
Host smart-93bc92dc-79d0-4486-9a53-6b9bc15e24a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422005585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.422005585
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.491311897
Short name T1042
Test name
Test status
Simulation time 22446268 ps
CPU time 0.85 seconds
Started Jun 21 06:36:29 PM PDT 24
Finished Jun 21 06:36:33 PM PDT 24
Peak memory 206444 kb
Host smart-6ddabde1-819a-4f1f-8c65-cabb43c358f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491311897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.491311897
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2471837549
Short name T241
Test name
Test status
Simulation time 19212341 ps
CPU time 1.2 seconds
Started Jun 21 06:36:28 PM PDT 24
Finished Jun 21 06:36:32 PM PDT 24
Peak memory 206436 kb
Host smart-f78281a0-50dc-4c90-9883-6526d9f57ff3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471837549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2471837549
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.4093961668
Short name T996
Test name
Test status
Simulation time 642714792 ps
CPU time 3.84 seconds
Started Jun 21 06:36:25 PM PDT 24
Finished Jun 21 06:36:32 PM PDT 24
Peak memory 214836 kb
Host smart-eb8be2a0-6b0d-426b-b77b-213e1f97ec28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093961668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.4093961668
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.145973560
Short name T1082
Test name
Test status
Simulation time 557634428 ps
CPU time 3.26 seconds
Started Jun 21 06:36:27 PM PDT 24
Finished Jun 21 06:36:33 PM PDT 24
Peak memory 214608 kb
Host smart-7863d916-5e0e-4c90-aacd-0ac688c9aa08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145973560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.145973560
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.788002297
Short name T1071
Test name
Test status
Simulation time 39873549 ps
CPU time 1.17 seconds
Started Jun 21 06:36:34 PM PDT 24
Finished Jun 21 06:36:38 PM PDT 24
Peak memory 222832 kb
Host smart-9673110b-7d04-411d-aecb-4efd2e3c5d39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788002297 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.788002297
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.588151538
Short name T1030
Test name
Test status
Simulation time 33281476 ps
CPU time 0.84 seconds
Started Jun 21 06:36:29 PM PDT 24
Finished Jun 21 06:36:32 PM PDT 24
Peak memory 206268 kb
Host smart-8b33f28f-df25-4a89-9c73-b6149be521c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588151538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.588151538
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2442868901
Short name T1119
Test name
Test status
Simulation time 20174000 ps
CPU time 0.91 seconds
Started Jun 21 06:36:27 PM PDT 24
Finished Jun 21 06:36:30 PM PDT 24
Peak memory 206364 kb
Host smart-20896370-389b-4e6b-afe1-5af4132a4b13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442868901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2442868901
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2063099292
Short name T1060
Test name
Test status
Simulation time 41409184 ps
CPU time 1.15 seconds
Started Jun 21 06:36:29 PM PDT 24
Finished Jun 21 06:36:33 PM PDT 24
Peak memory 206544 kb
Host smart-3c6cb261-8b99-484f-b258-d4a068ba5ee6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063099292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2063099292
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1697563200
Short name T1099
Test name
Test status
Simulation time 110788414 ps
CPU time 3.98 seconds
Started Jun 21 06:36:29 PM PDT 24
Finished Jun 21 06:36:35 PM PDT 24
Peak memory 214696 kb
Host smart-b89634aa-4dac-43e6-88cd-0397eaf728ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697563200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1697563200
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2774625582
Short name T284
Test name
Test status
Simulation time 120337738 ps
CPU time 1.73 seconds
Started Jun 21 06:36:32 PM PDT 24
Finished Jun 21 06:36:36 PM PDT 24
Peak memory 206712 kb
Host smart-d1a37f4d-88dd-4997-8408-42953e5e4e7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774625582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2774625582
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.2294842072
Short name T600
Test name
Test status
Simulation time 32386584 ps
CPU time 0.89 seconds
Started Jun 21 06:41:02 PM PDT 24
Finished Jun 21 06:41:52 PM PDT 24
Peak memory 206132 kb
Host smart-a83d057d-fe3c-409f-b4a3-394f3fe0af6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294842072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2294842072
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.438108553
Short name T758
Test name
Test status
Simulation time 12709746 ps
CPU time 0.92 seconds
Started Jun 21 06:41:09 PM PDT 24
Finished Jun 21 06:42:09 PM PDT 24
Peak memory 215832 kb
Host smart-34f26db5-2cff-4bee-b690-87d61e1bd786
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438108553 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.438108553
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1476825976
Short name T40
Test name
Test status
Simulation time 116247173 ps
CPU time 1.27 seconds
Started Jun 21 06:41:03 PM PDT 24
Finished Jun 21 06:41:52 PM PDT 24
Peak memory 215656 kb
Host smart-1639aca6-2e79-43d0-b5db-2f1326f55f7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476825976 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1476825976
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.857679701
Short name T153
Test name
Test status
Simulation time 34821998 ps
CPU time 1.03 seconds
Started Jun 21 06:41:03 PM PDT 24
Finished Jun 21 06:41:57 PM PDT 24
Peak memory 223236 kb
Host smart-152d26c9-ff41-4b37-87d9-ff24187797c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857679701 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.857679701
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.4161282644
Short name T437
Test name
Test status
Simulation time 294987279 ps
CPU time 1.86 seconds
Started Jun 21 06:41:03 PM PDT 24
Finished Jun 21 06:41:58 PM PDT 24
Peak memory 218028 kb
Host smart-7a69ee77-4782-4c00-8365-0bfae944ec9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161282644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.4161282644
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.4292890058
Short name T52
Test name
Test status
Simulation time 39092440 ps
CPU time 0.93 seconds
Started Jun 21 06:41:03 PM PDT 24
Finished Jun 21 06:41:52 PM PDT 24
Peak memory 223204 kb
Host smart-67f86235-4949-496e-9bd1-6a8fecd90b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292890058 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.4292890058
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_smoke.529431583
Short name T985
Test name
Test status
Simulation time 26961050 ps
CPU time 0.91 seconds
Started Jun 21 06:41:05 PM PDT 24
Finished Jun 21 06:41:57 PM PDT 24
Peak memory 214620 kb
Host smart-3de0e12c-4d2b-4aae-b6b9-81c05094d213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529431583 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.529431583
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2109070668
Short name T540
Test name
Test status
Simulation time 75609169 ps
CPU time 2.05 seconds
Started Jun 21 06:41:02 PM PDT 24
Finished Jun 21 06:41:53 PM PDT 24
Peak memory 206432 kb
Host smart-0225befa-0e20-4289-947a-a131c30b86d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109070668 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2109070668
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert.745486600
Short name T934
Test name
Test status
Simulation time 57521770 ps
CPU time 1.05 seconds
Started Jun 21 06:41:16 PM PDT 24
Finished Jun 21 06:42:20 PM PDT 24
Peak memory 218996 kb
Host smart-976b5a65-9081-471f-9333-624ed678e2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745486600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.745486600
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.619596227
Short name T636
Test name
Test status
Simulation time 27259639 ps
CPU time 0.84 seconds
Started Jun 21 06:41:11 PM PDT 24
Finished Jun 21 06:42:14 PM PDT 24
Peak memory 205952 kb
Host smart-8d4aae89-5a64-4aba-9469-68eb83c64b1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619596227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.619596227
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.4159244701
Short name T90
Test name
Test status
Simulation time 261717739 ps
CPU time 1 seconds
Started Jun 21 06:41:11 PM PDT 24
Finished Jun 21 06:42:14 PM PDT 24
Peak memory 216116 kb
Host smart-cf41c2e0-ae87-48c3-b5ff-ec22df2f6e46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159244701 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.4159244701
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_genbits.2977528118
Short name T714
Test name
Test status
Simulation time 38341692 ps
CPU time 1.19 seconds
Started Jun 21 06:41:03 PM PDT 24
Finished Jun 21 06:41:52 PM PDT 24
Peak memory 216280 kb
Host smart-fe8d1c84-d5ad-4da4-8d8e-d4a6104c7aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977528118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2977528118
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2424218928
Short name T380
Test name
Test status
Simulation time 61527716 ps
CPU time 0.83 seconds
Started Jun 21 06:41:12 PM PDT 24
Finished Jun 21 06:42:14 PM PDT 24
Peak memory 214800 kb
Host smart-328fdfa9-7358-4ecb-8851-00a98522c604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424218928 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2424218928
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.1643443888
Short name T700
Test name
Test status
Simulation time 18291661 ps
CPU time 1 seconds
Started Jun 21 06:41:09 PM PDT 24
Finished Jun 21 06:42:10 PM PDT 24
Peak memory 206416 kb
Host smart-cf921e0c-0d4c-4952-8bba-5ccae2f1c682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643443888 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1643443888
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.398331330
Short name T56
Test name
Test status
Simulation time 984909362 ps
CPU time 7.93 seconds
Started Jun 21 06:41:12 PM PDT 24
Finished Jun 21 06:42:21 PM PDT 24
Peak memory 235868 kb
Host smart-8e589a2f-ed07-42ff-b85d-bc721c98777d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398331330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.398331330
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.3358846191
Short name T381
Test name
Test status
Simulation time 16317393 ps
CPU time 1 seconds
Started Jun 21 06:41:07 PM PDT 24
Finished Jun 21 06:42:08 PM PDT 24
Peak memory 214648 kb
Host smart-7e4720e7-6fb6-4c7e-9484-93d4bfb101b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358846191 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3358846191
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1849977960
Short name T971
Test name
Test status
Simulation time 379819826 ps
CPU time 4.27 seconds
Started Jun 21 06:41:06 PM PDT 24
Finished Jun 21 06:42:07 PM PDT 24
Peak memory 216556 kb
Host smart-615a97ff-c4b3-49b4-815e-7c6636aa727a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849977960 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1849977960
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3893634902
Short name T670
Test name
Test status
Simulation time 9130765733 ps
CPU time 121.78 seconds
Started Jun 21 06:41:03 PM PDT 24
Finished Jun 21 06:43:57 PM PDT 24
Peak memory 216620 kb
Host smart-dd0b6b8e-a6af-4819-8bf3-9fe04a2a9ac5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893634902 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3893634902
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3086164621
Short name T429
Test name
Test status
Simulation time 52515944 ps
CPU time 1.27 seconds
Started Jun 21 06:41:37 PM PDT 24
Finished Jun 21 06:42:45 PM PDT 24
Peak memory 218084 kb
Host smart-02b2478d-e66f-40c9-8c6b-685c4b72b3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086164621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3086164621
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.3042681101
Short name T428
Test name
Test status
Simulation time 39096949 ps
CPU time 1.05 seconds
Started Jun 21 06:41:41 PM PDT 24
Finished Jun 21 06:42:48 PM PDT 24
Peak memory 215512 kb
Host smart-98b66a8f-e1a9-462a-8af7-4370b29d6d15
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042681101 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3042681101
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.2725145587
Short name T141
Test name
Test status
Simulation time 80287299 ps
CPU time 1.42 seconds
Started Jun 21 06:41:38 PM PDT 24
Finished Jun 21 06:42:45 PM PDT 24
Peak memory 216364 kb
Host smart-b25dfc94-daed-4660-b19b-492f785333bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725145587 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.2725145587
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.1449445469
Short name T900
Test name
Test status
Simulation time 43685705 ps
CPU time 1.1 seconds
Started Jun 21 06:41:38 PM PDT 24
Finished Jun 21 06:42:45 PM PDT 24
Peak memory 219092 kb
Host smart-f6497daa-5da3-4c3e-84c1-f1a97c28b3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449445469 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1449445469
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3601002311
Short name T84
Test name
Test status
Simulation time 36865355 ps
CPU time 1.58 seconds
Started Jun 21 06:41:38 PM PDT 24
Finished Jun 21 06:42:45 PM PDT 24
Peak memory 219488 kb
Host smart-ac7cbd1c-73c9-4fba-bb12-c7bee2f3e817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601002311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3601002311
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3925151753
Short name T441
Test name
Test status
Simulation time 29074921 ps
CPU time 0.96 seconds
Started Jun 21 06:41:39 PM PDT 24
Finished Jun 21 06:42:45 PM PDT 24
Peak memory 214980 kb
Host smart-680bbfd9-8b98-4064-b8fe-ebea4d5e1d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925151753 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3925151753
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1703575345
Short name T402
Test name
Test status
Simulation time 15226116 ps
CPU time 0.94 seconds
Started Jun 21 06:41:37 PM PDT 24
Finished Jun 21 06:42:44 PM PDT 24
Peak memory 214612 kb
Host smart-978e0ff6-f174-4dc3-9336-a9d70b3ac81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703575345 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1703575345
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1133466630
Short name T236
Test name
Test status
Simulation time 298776051 ps
CPU time 4.78 seconds
Started Jun 21 06:41:37 PM PDT 24
Finished Jun 21 06:42:48 PM PDT 24
Peak memory 214744 kb
Host smart-49af1234-f76a-4611-b39b-d9ffc5fe22aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133466630 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1133466630
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.799994169
Short name T403
Test name
Test status
Simulation time 139852625349 ps
CPU time 348.85 seconds
Started Jun 21 06:41:38 PM PDT 24
Finished Jun 21 06:48:32 PM PDT 24
Peak memory 222356 kb
Host smart-2ff8c3bc-cd02-42a9-b31f-f5e48c58921b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799994169 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.799994169
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.edn_alert.3261924131
Short name T972
Test name
Test status
Simulation time 28829781 ps
CPU time 1.38 seconds
Started Jun 21 06:44:34 PM PDT 24
Finished Jun 21 06:45:10 PM PDT 24
Peak memory 219956 kb
Host smart-1490a26f-28aa-4fa3-b4d0-fde45aaae04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261924131 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.3261924131
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.3860137406
Short name T941
Test name
Test status
Simulation time 49453761 ps
CPU time 1.45 seconds
Started Jun 21 06:44:35 PM PDT 24
Finished Jun 21 06:45:10 PM PDT 24
Peak memory 219476 kb
Host smart-44944963-b71a-41a9-a822-bb21086c3e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860137406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3860137406
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.2127221180
Short name T964
Test name
Test status
Simulation time 33285167 ps
CPU time 1.34 seconds
Started Jun 21 06:44:32 PM PDT 24
Finished Jun 21 06:45:08 PM PDT 24
Peak memory 220012 kb
Host smart-0d1b97e7-f4b4-4f34-82cc-14661a0df21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127221180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.2127221180
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.2478604267
Short name T742
Test name
Test status
Simulation time 53747055 ps
CPU time 1.38 seconds
Started Jun 21 06:44:32 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 217788 kb
Host smart-b611e095-7d6e-4b10-9951-75644be7b4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478604267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2478604267
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3463342605
Short name T365
Test name
Test status
Simulation time 103501724 ps
CPU time 1.49 seconds
Started Jun 21 06:44:33 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 218288 kb
Host smart-8fa418b5-023b-4a55-8082-093749732ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463342605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3463342605
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.508886685
Short name T605
Test name
Test status
Simulation time 199979740 ps
CPU time 1.04 seconds
Started Jun 21 06:44:33 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 216764 kb
Host smart-d0fce47f-3fd6-4762-98f4-7de33d1fecc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508886685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.508886685
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.1356433557
Short name T857
Test name
Test status
Simulation time 46267826 ps
CPU time 1.22 seconds
Started Jun 21 06:44:31 PM PDT 24
Finished Jun 21 06:45:08 PM PDT 24
Peak memory 218036 kb
Host smart-a1aa42d9-c8dc-4db5-bd4b-d25a8c058fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356433557 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.1356433557
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.1939316175
Short name T505
Test name
Test status
Simulation time 27582153 ps
CPU time 1.24 seconds
Started Jun 21 06:44:32 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 219288 kb
Host smart-2e17d7d3-75e3-4654-a845-9f3d19fe4a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939316175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1939316175
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.2085099734
Short name T946
Test name
Test status
Simulation time 84337674 ps
CPU time 1.22 seconds
Started Jun 21 06:44:33 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 215052 kb
Host smart-a37ccb03-c1b2-432b-8cb1-00f086d17a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085099734 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2085099734
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.2555720086
Short name T708
Test name
Test status
Simulation time 192452075 ps
CPU time 1.6 seconds
Started Jun 21 06:44:33 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 218108 kb
Host smart-f71fbbcf-ce75-4533-8d90-8f2faf352bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555720086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2555720086
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.1019605155
Short name T688
Test name
Test status
Simulation time 28636514 ps
CPU time 1.25 seconds
Started Jun 21 06:44:34 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 215088 kb
Host smart-e5547760-74ec-4c59-8038-f98d51015e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019605155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.1019605155
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.4048483729
Short name T361
Test name
Test status
Simulation time 59548094 ps
CPU time 1.54 seconds
Started Jun 21 06:44:32 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 217872 kb
Host smart-9f477ab2-c2b5-4a68-bbd3-c9c1eff9e440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048483729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.4048483729
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.1404399921
Short name T508
Test name
Test status
Simulation time 85161521 ps
CPU time 1.2 seconds
Started Jun 21 06:44:42 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 218100 kb
Host smart-aeff50a0-6e29-471e-b8e6-369b5ae751a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404399921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.1404399921
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.1096131827
Short name T775
Test name
Test status
Simulation time 80886397 ps
CPU time 1.31 seconds
Started Jun 21 06:44:39 PM PDT 24
Finished Jun 21 06:45:13 PM PDT 24
Peak memory 216636 kb
Host smart-6c58ef33-6294-4408-bd02-4ad5aacbbaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096131827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1096131827
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.409485000
Short name T686
Test name
Test status
Simulation time 137786425 ps
CPU time 1.18 seconds
Started Jun 21 06:44:39 PM PDT 24
Finished Jun 21 06:45:14 PM PDT 24
Peak memory 218236 kb
Host smart-09700703-3457-474e-b589-7483e4a8b337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409485000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.409485000
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.2242384747
Short name T516
Test name
Test status
Simulation time 41367555 ps
CPU time 1.09 seconds
Started Jun 21 06:44:39 PM PDT 24
Finished Jun 21 06:45:13 PM PDT 24
Peak memory 217864 kb
Host smart-c49b51f5-45bb-4feb-8999-43c69a819cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242384747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2242384747
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1104902682
Short name T70
Test name
Test status
Simulation time 40133943 ps
CPU time 1.14 seconds
Started Jun 21 06:41:39 PM PDT 24
Finished Jun 21 06:42:45 PM PDT 24
Peak memory 219492 kb
Host smart-f5800326-e3aa-4a9d-97a7-f5a882f682ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104902682 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1104902682
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3475717344
Short name T750
Test name
Test status
Simulation time 162513823 ps
CPU time 0.95 seconds
Started Jun 21 06:41:38 PM PDT 24
Finished Jun 21 06:42:45 PM PDT 24
Peak memory 214576 kb
Host smart-a02f8e0f-baf2-40d0-ab46-fc5ff659ff2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475717344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3475717344
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3330082182
Short name T981
Test name
Test status
Simulation time 20321725 ps
CPU time 0.88 seconds
Started Jun 21 06:41:38 PM PDT 24
Finished Jun 21 06:42:44 PM PDT 24
Peak memory 215820 kb
Host smart-b39f8c89-0cbe-4adc-9d2b-9799a2cbf0fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330082182 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3330082182
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.3134478359
Short name T212
Test name
Test status
Simulation time 74918337 ps
CPU time 1.11 seconds
Started Jun 21 06:41:38 PM PDT 24
Finished Jun 21 06:42:45 PM PDT 24
Peak memory 219124 kb
Host smart-645d50e5-322b-4798-8c01-cdc1c047228b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134478359 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3134478359
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.3689096074
Short name T363
Test name
Test status
Simulation time 198879928 ps
CPU time 1.22 seconds
Started Jun 21 06:41:37 PM PDT 24
Finished Jun 21 06:42:45 PM PDT 24
Peak memory 216840 kb
Host smart-552a6294-d286-4756-9a1c-62c45cb1f56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689096074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3689096074
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.500840710
Short name T500
Test name
Test status
Simulation time 21134648 ps
CPU time 1.23 seconds
Started Jun 21 06:41:39 PM PDT 24
Finished Jun 21 06:42:45 PM PDT 24
Peak memory 223380 kb
Host smart-dd108452-4dec-476e-bc51-8d11dfda1274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500840710 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.500840710
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3835129999
Short name T862
Test name
Test status
Simulation time 93988342 ps
CPU time 0.96 seconds
Started Jun 21 06:41:37 PM PDT 24
Finished Jun 21 06:42:45 PM PDT 24
Peak memory 214568 kb
Host smart-351263a2-9e52-4eb7-8a26-0351d51b3aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835129999 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3835129999
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1131351565
Short name T719
Test name
Test status
Simulation time 164164133 ps
CPU time 1.49 seconds
Started Jun 21 06:41:38 PM PDT 24
Finished Jun 21 06:42:45 PM PDT 24
Peak memory 217856 kb
Host smart-2fbe571b-1705-4146-b893-5458dd330f8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131351565 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1131351565
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2901830576
Short name T439
Test name
Test status
Simulation time 146873444102 ps
CPU time 977.83 seconds
Started Jun 21 06:41:38 PM PDT 24
Finished Jun 21 06:59:02 PM PDT 24
Peak memory 222928 kb
Host smart-bbd133df-ee7d-4696-9ee4-75e4268d2c84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901830576 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2901830576
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.1348550728
Short name T902
Test name
Test status
Simulation time 54932348 ps
CPU time 1.3 seconds
Started Jun 21 06:44:40 PM PDT 24
Finished Jun 21 06:45:14 PM PDT 24
Peak memory 215092 kb
Host smart-0749885e-9b32-483f-ac60-d464a12c5049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348550728 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.1348550728
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.994905627
Short name T884
Test name
Test status
Simulation time 143389202 ps
CPU time 1.31 seconds
Started Jun 21 06:44:40 PM PDT 24
Finished Jun 21 06:45:15 PM PDT 24
Peak memory 219316 kb
Host smart-007de845-0c4e-410b-b29c-369e6275b8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994905627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.994905627
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.614745900
Short name T940
Test name
Test status
Simulation time 65749102 ps
CPU time 1.16 seconds
Started Jun 21 06:44:42 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 216780 kb
Host smart-b830e23e-90ba-41b6-9528-adb1d6e3c0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614745900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.614745900
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2502234975
Short name T888
Test name
Test status
Simulation time 224861688 ps
CPU time 0.99 seconds
Started Jun 21 06:44:38 PM PDT 24
Finished Jun 21 06:45:13 PM PDT 24
Peak memory 216664 kb
Host smart-aa55fea5-82b5-4784-87b5-2534259bd847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502234975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2502234975
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.40521930
Short name T445
Test name
Test status
Simulation time 84439763 ps
CPU time 1.44 seconds
Started Jun 21 06:44:43 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 218132 kb
Host smart-18521af7-66f3-4902-a730-c46dbef55415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40521930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.40521930
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.3536229687
Short name T867
Test name
Test status
Simulation time 48097575 ps
CPU time 1.13 seconds
Started Jun 21 06:44:38 PM PDT 24
Finished Jun 21 06:45:13 PM PDT 24
Peak memory 217756 kb
Host smart-3852932c-1d34-499d-a28b-a8a5acc776a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536229687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3536229687
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.2577404704
Short name T679
Test name
Test status
Simulation time 29594622 ps
CPU time 1.36 seconds
Started Jun 21 06:44:39 PM PDT 24
Finished Jun 21 06:45:14 PM PDT 24
Peak memory 218088 kb
Host smart-14fe2070-3a0a-44d5-b8e0-f0caaa27172a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577404704 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.2577404704
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.2871721115
Short name T551
Test name
Test status
Simulation time 37967197 ps
CPU time 1.26 seconds
Started Jun 21 06:44:40 PM PDT 24
Finished Jun 21 06:45:15 PM PDT 24
Peak memory 216828 kb
Host smart-70cea7cf-c0bc-44b7-9e5f-e5d75a1622a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871721115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2871721115
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.379987703
Short name T634
Test name
Test status
Simulation time 46011881 ps
CPU time 1.09 seconds
Started Jun 21 06:44:39 PM PDT 24
Finished Jun 21 06:45:13 PM PDT 24
Peak memory 219588 kb
Host smart-f9ef96a9-db4a-4a19-a8b3-726fc428ec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379987703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.379987703
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.174841433
Short name T682
Test name
Test status
Simulation time 24231719 ps
CPU time 1.23 seconds
Started Jun 21 06:44:41 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 218896 kb
Host smart-295834b9-f99d-4363-8864-220c823cef06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174841433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.174841433
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.793397740
Short name T85
Test name
Test status
Simulation time 33096335 ps
CPU time 1.3 seconds
Started Jun 21 06:44:43 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 215088 kb
Host smart-e1c9e599-3516-4ed1-a154-38cf757f8100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793397740 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.793397740
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.2720357602
Short name T393
Test name
Test status
Simulation time 57940986 ps
CPU time 1.11 seconds
Started Jun 21 06:44:40 PM PDT 24
Finished Jun 21 06:45:15 PM PDT 24
Peak memory 217888 kb
Host smart-ecc42546-4f6f-440c-a087-a3a89508df61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720357602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2720357602
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.245266018
Short name T898
Test name
Test status
Simulation time 25966583 ps
CPU time 1.26 seconds
Started Jun 21 06:44:38 PM PDT 24
Finished Jun 21 06:45:13 PM PDT 24
Peak memory 220124 kb
Host smart-109470a0-b666-4f56-9367-fdf8e9d9e7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245266018 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.245266018
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/119.edn_alert.3341838396
Short name T293
Test name
Test status
Simulation time 25422653 ps
CPU time 1.13 seconds
Started Jun 21 06:44:38 PM PDT 24
Finished Jun 21 06:45:13 PM PDT 24
Peak memory 218988 kb
Host smart-0e2431bc-c377-4337-af04-84026128a141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341838396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.3341838396
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.3647104694
Short name T494
Test name
Test status
Simulation time 90863070 ps
CPU time 1.4 seconds
Started Jun 21 06:44:44 PM PDT 24
Finished Jun 21 06:45:17 PM PDT 24
Peak memory 218268 kb
Host smart-3a8e237f-a8d7-42c2-a383-0bb912c37eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647104694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3647104694
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.1494068757
Short name T265
Test name
Test status
Simulation time 38021211 ps
CPU time 0.84 seconds
Started Jun 21 06:41:47 PM PDT 24
Finished Jun 21 06:42:52 PM PDT 24
Peak memory 205888 kb
Host smart-ffa5543b-564a-4770-a13f-3aa21c63b39f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494068757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1494068757
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_err.3909833760
Short name T517
Test name
Test status
Simulation time 30160096 ps
CPU time 1.28 seconds
Started Jun 21 06:41:49 PM PDT 24
Finished Jun 21 06:42:52 PM PDT 24
Peak memory 219140 kb
Host smart-d8a6e508-7e54-4bba-8ac6-f8ce06c0496d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909833760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3909833760
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1832937948
Short name T767
Test name
Test status
Simulation time 45590228 ps
CPU time 1.48 seconds
Started Jun 21 06:41:38 PM PDT 24
Finished Jun 21 06:42:45 PM PDT 24
Peak memory 217816 kb
Host smart-24bd3f11-1c85-4944-b36b-ae276cb58653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832937948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1832937948
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1525923391
Short name T490
Test name
Test status
Simulation time 22970941 ps
CPU time 0.96 seconds
Started Jun 21 06:41:47 PM PDT 24
Finished Jun 21 06:42:51 PM PDT 24
Peak memory 215140 kb
Host smart-fd8c65a6-95ce-4bd8-8308-6b64bdfd352a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525923391 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1525923391
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.3013135778
Short name T701
Test name
Test status
Simulation time 40070291 ps
CPU time 0.9 seconds
Started Jun 21 06:41:38 PM PDT 24
Finished Jun 21 06:42:45 PM PDT 24
Peak memory 214640 kb
Host smart-0016dbad-817a-4070-92e6-84b0a6a431f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013135778 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3013135778
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3981634734
Short name T627
Test name
Test status
Simulation time 699970299 ps
CPU time 3.72 seconds
Started Jun 21 06:41:39 PM PDT 24
Finished Jun 21 06:42:47 PM PDT 24
Peak memory 216624 kb
Host smart-ed8a4d8c-9334-4f36-91fb-da5b0e115f7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981634734 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3981634734
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.225538334
Short name T100
Test name
Test status
Simulation time 132488496452 ps
CPU time 1646.35 seconds
Started Jun 21 06:41:38 PM PDT 24
Finished Jun 21 07:10:10 PM PDT 24
Peak memory 223916 kb
Host smart-ecf76506-955a-47a9-a592-210e11a00de9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225538334 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.225538334
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.1104401486
Short name T374
Test name
Test status
Simulation time 85242488 ps
CPU time 1.15 seconds
Started Jun 21 06:44:41 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 219072 kb
Host smart-6c435408-f988-4f4d-8b56-e9db4c6cd39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104401486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.1104401486
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.970425298
Short name T534
Test name
Test status
Simulation time 42655937 ps
CPU time 1.17 seconds
Started Jun 21 06:44:46 PM PDT 24
Finished Jun 21 06:45:18 PM PDT 24
Peak memory 216820 kb
Host smart-4d4b11b2-733b-4d68-a97d-a7e8ada3b68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970425298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.970425298
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.741788320
Short name T512
Test name
Test status
Simulation time 32154703 ps
CPU time 1.35 seconds
Started Jun 21 06:44:42 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 219560 kb
Host smart-ed11a938-5fb0-43c9-9f75-fe80b29a7746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741788320 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.741788320
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.233243952
Short name T789
Test name
Test status
Simulation time 48180770 ps
CPU time 1.04 seconds
Started Jun 21 06:44:42 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 216760 kb
Host smart-688bd854-e16b-4f45-a173-bbb78b705c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233243952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.233243952
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.2437978474
Short name T871
Test name
Test status
Simulation time 53008505 ps
CPU time 1.14 seconds
Started Jun 21 06:44:39 PM PDT 24
Finished Jun 21 06:45:13 PM PDT 24
Peak memory 219340 kb
Host smart-f54ea266-98de-4ab4-ab5f-96950afff440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437978474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.2437978474
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/123.edn_alert.2723936896
Short name T69
Test name
Test status
Simulation time 43258467 ps
CPU time 1.22 seconds
Started Jun 21 06:44:42 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 217944 kb
Host smart-3aadf685-f0ed-4cfc-86d5-560c304247bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723936896 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2723936896
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.2825924832
Short name T568
Test name
Test status
Simulation time 46694634 ps
CPU time 1.53 seconds
Started Jun 21 06:44:42 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 217640 kb
Host smart-2504b742-2dd7-4f72-8202-091cd5707890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825924832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2825924832
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.3039632116
Short name T854
Test name
Test status
Simulation time 26625892 ps
CPU time 1.2 seconds
Started Jun 21 06:44:47 PM PDT 24
Finished Jun 21 06:45:18 PM PDT 24
Peak memory 217980 kb
Host smart-e3c1ff2b-a4cb-4258-b480-84ae17648edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039632116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.3039632116
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.3036064375
Short name T537
Test name
Test status
Simulation time 68778606 ps
CPU time 1.22 seconds
Started Jun 21 06:44:42 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 218744 kb
Host smart-7250e5bb-65cb-4b2f-95c2-bc5624f9111d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036064375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3036064375
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2273596074
Short name T591
Test name
Test status
Simulation time 33015330 ps
CPU time 1.43 seconds
Started Jun 21 06:44:47 PM PDT 24
Finished Jun 21 06:45:20 PM PDT 24
Peak memory 218320 kb
Host smart-e4f3216e-d523-4e6e-b0e1-ca3829e854f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273596074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2273596074
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.3554073713
Short name T849
Test name
Test status
Simulation time 103584517 ps
CPU time 1.14 seconds
Started Jun 21 06:44:39 PM PDT 24
Finished Jun 21 06:45:13 PM PDT 24
Peak memory 219056 kb
Host smart-19953bce-6b25-4e33-a9ab-21497c7ecaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554073713 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.3554073713
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.463091178
Short name T487
Test name
Test status
Simulation time 75758677 ps
CPU time 1.28 seconds
Started Jun 21 06:44:41 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 218432 kb
Host smart-4ac982c1-6057-4bf8-9a40-dcb031f4a82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463091178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.463091178
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.1586284650
Short name T818
Test name
Test status
Simulation time 29074790 ps
CPU time 1.23 seconds
Started Jun 21 06:44:40 PM PDT 24
Finished Jun 21 06:45:14 PM PDT 24
Peak memory 218136 kb
Host smart-555d674f-a7f4-4f1c-875e-7cc4149ae8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586284650 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.1586284650
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/128.edn_alert.3830038799
Short name T178
Test name
Test status
Simulation time 35484090 ps
CPU time 1.1 seconds
Started Jun 21 06:44:41 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 218864 kb
Host smart-3d739004-e20a-4ec0-8e1f-d149a55e06ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830038799 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.3830038799
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.3554899250
Short name T502
Test name
Test status
Simulation time 38858706 ps
CPU time 1.6 seconds
Started Jun 21 06:44:40 PM PDT 24
Finished Jun 21 06:45:14 PM PDT 24
Peak memory 219560 kb
Host smart-3bb69705-96f7-4051-89dc-edec8f5c4d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554899250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3554899250
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.2384339277
Short name T552
Test name
Test status
Simulation time 42477916 ps
CPU time 1.13 seconds
Started Jun 21 06:44:47 PM PDT 24
Finished Jun 21 06:45:20 PM PDT 24
Peak memory 220172 kb
Host smart-c796a0c8-7f19-4e9b-8fc1-a9b0f1f6417f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384339277 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.2384339277
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.4197929723
Short name T343
Test name
Test status
Simulation time 106315105 ps
CPU time 1.1 seconds
Started Jun 21 06:44:43 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 216604 kb
Host smart-03d37171-c9e8-42e4-84e4-dc7c9d47d236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197929723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.4197929723
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3597664314
Short name T624
Test name
Test status
Simulation time 110098299 ps
CPU time 1.1 seconds
Started Jun 21 06:41:48 PM PDT 24
Finished Jun 21 06:42:52 PM PDT 24
Peak memory 217988 kb
Host smart-8275a7c7-f9d8-4e0e-83d0-867b3bb85fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597664314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3597664314
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.694161560
Short name T476
Test name
Test status
Simulation time 11843313 ps
CPU time 0.85 seconds
Started Jun 21 06:41:49 PM PDT 24
Finished Jun 21 06:42:52 PM PDT 24
Peak memory 205896 kb
Host smart-8254002a-f5e3-4bd7-a71f-c2e3b9acb5e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694161560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.694161560
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.2366416140
Short name T208
Test name
Test status
Simulation time 34480766 ps
CPU time 0.84 seconds
Started Jun 21 06:41:47 PM PDT 24
Finished Jun 21 06:42:51 PM PDT 24
Peak memory 215660 kb
Host smart-fd883749-d072-4aef-a7c4-37e96c9a4239
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366416140 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2366416140
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.4078101346
Short name T148
Test name
Test status
Simulation time 44456128 ps
CPU time 1.09 seconds
Started Jun 21 06:41:47 PM PDT 24
Finished Jun 21 06:42:52 PM PDT 24
Peak memory 216164 kb
Host smart-43aacb4c-9175-4161-b411-7f4d79ee79e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078101346 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.4078101346
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2772473652
Short name T808
Test name
Test status
Simulation time 51727862 ps
CPU time 0.97 seconds
Started Jun 21 06:41:47 PM PDT 24
Finished Jun 21 06:42:51 PM PDT 24
Peak memory 218180 kb
Host smart-49816521-182f-4d79-bf5c-eeddd30ac248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772473652 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2772473652
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_intr.2598896056
Short name T897
Test name
Test status
Simulation time 24128458 ps
CPU time 0.93 seconds
Started Jun 21 06:41:46 PM PDT 24
Finished Jun 21 06:42:51 PM PDT 24
Peak memory 215120 kb
Host smart-2380f590-cfc6-4078-9250-47209f115752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598896056 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2598896056
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2318142555
Short name T378
Test name
Test status
Simulation time 48807951 ps
CPU time 0.94 seconds
Started Jun 21 06:41:47 PM PDT 24
Finished Jun 21 06:42:52 PM PDT 24
Peak memory 214596 kb
Host smart-0144593d-9e6e-42ff-89fc-0828cf6fcc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318142555 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2318142555
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1626236881
Short name T569
Test name
Test status
Simulation time 849690846 ps
CPU time 4.44 seconds
Started Jun 21 06:41:47 PM PDT 24
Finished Jun 21 06:42:55 PM PDT 24
Peak memory 216768 kb
Host smart-ffaf72d3-bce8-44b8-be96-67be3b8bb479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626236881 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1626236881
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.4102027811
Short name T936
Test name
Test status
Simulation time 25702012254 ps
CPU time 638.86 seconds
Started Jun 21 06:41:48 PM PDT 24
Finished Jun 21 06:53:30 PM PDT 24
Peak memory 217196 kb
Host smart-58e263bc-5f54-4663-8d02-49ee7eb0bb71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102027811 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.4102027811
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.4049376818
Short name T949
Test name
Test status
Simulation time 27921108 ps
CPU time 1.2 seconds
Started Jun 21 06:44:40 PM PDT 24
Finished Jun 21 06:45:14 PM PDT 24
Peak memory 215064 kb
Host smart-94cabbb7-3a6e-41e3-ac58-b8d861433dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049376818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.4049376818
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.14915129
Short name T294
Test name
Test status
Simulation time 33143106 ps
CPU time 1.06 seconds
Started Jun 21 06:44:43 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 217892 kb
Host smart-ad7116a4-fac0-44b4-9412-a494c586dbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14915129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.14915129
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.3955469784
Short name T478
Test name
Test status
Simulation time 42123672 ps
CPU time 1.18 seconds
Started Jun 21 06:44:42 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 218792 kb
Host smart-c28e989d-eaea-4471-ab06-fc4ba44b4782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955469784 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.3955469784
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.1125418116
Short name T781
Test name
Test status
Simulation time 36425893 ps
CPU time 1.2 seconds
Started Jun 21 06:44:43 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 216480 kb
Host smart-b80d3901-2d88-4cae-be11-b6b66fb8b7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125418116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1125418116
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.2013823003
Short name T628
Test name
Test status
Simulation time 41090536 ps
CPU time 1.2 seconds
Started Jun 21 06:44:44 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 220516 kb
Host smart-c263f314-5d3a-47f0-9595-584fe624f29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013823003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.2013823003
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.2262134349
Short name T465
Test name
Test status
Simulation time 69640237 ps
CPU time 1.65 seconds
Started Jun 21 06:44:41 PM PDT 24
Finished Jun 21 06:45:16 PM PDT 24
Peak memory 218052 kb
Host smart-41c4a3be-1d5f-4a17-9aa4-b411f997747f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262134349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2262134349
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.594899325
Short name T196
Test name
Test status
Simulation time 39281055 ps
CPU time 1.12 seconds
Started Jun 21 06:44:51 PM PDT 24
Finished Jun 21 06:45:23 PM PDT 24
Peak memory 219216 kb
Host smart-ece613eb-e982-4949-9f0f-260428a25393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594899325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.594899325
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.1375385100
Short name T466
Test name
Test status
Simulation time 43820162 ps
CPU time 1.46 seconds
Started Jun 21 06:44:51 PM PDT 24
Finished Jun 21 06:45:23 PM PDT 24
Peak memory 217868 kb
Host smart-ccc3dbae-4c44-41d6-8b03-8dfbd3d821e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375385100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1375385100
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.3194372433
Short name T239
Test name
Test status
Simulation time 51564557 ps
CPU time 1.22 seconds
Started Jun 21 06:44:50 PM PDT 24
Finished Jun 21 06:45:23 PM PDT 24
Peak memory 217968 kb
Host smart-a24dac13-ab7d-42e9-8b38-9e92ac8c66eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194372433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.3194372433
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.1211857099
Short name T653
Test name
Test status
Simulation time 104298850 ps
CPU time 1.35 seconds
Started Jun 21 06:44:51 PM PDT 24
Finished Jun 21 06:45:23 PM PDT 24
Peak memory 216660 kb
Host smart-f6a56a51-3b77-49df-a04a-c1e956a6229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211857099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1211857099
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.3896552981
Short name T905
Test name
Test status
Simulation time 50546063 ps
CPU time 1.28 seconds
Started Jun 21 06:44:51 PM PDT 24
Finished Jun 21 06:45:23 PM PDT 24
Peak memory 219992 kb
Host smart-3b00de4c-bfd3-4a35-aec6-e1a5f36919ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896552981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.3896552981
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.3685892020
Short name T773
Test name
Test status
Simulation time 101350457 ps
CPU time 1.16 seconds
Started Jun 21 06:44:49 PM PDT 24
Finished Jun 21 06:45:21 PM PDT 24
Peak memory 218028 kb
Host smart-b38011b2-cd82-4f93-ac7c-3a266fe68bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685892020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3685892020
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.1581920097
Short name T518
Test name
Test status
Simulation time 29843634 ps
CPU time 1.28 seconds
Started Jun 21 06:44:50 PM PDT 24
Finished Jun 21 06:45:23 PM PDT 24
Peak memory 215084 kb
Host smart-bc677b40-4642-4df5-a3ea-78f4b1c5edf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581920097 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1581920097
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.2127348795
Short name T425
Test name
Test status
Simulation time 35551256 ps
CPU time 1.37 seconds
Started Jun 21 06:44:50 PM PDT 24
Finished Jun 21 06:45:23 PM PDT 24
Peak memory 216632 kb
Host smart-a6da03e7-66c1-40cc-9be7-9e9310df64a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127348795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2127348795
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.145044541
Short name T978
Test name
Test status
Simulation time 181387350 ps
CPU time 1.14 seconds
Started Jun 21 06:44:51 PM PDT 24
Finished Jun 21 06:45:23 PM PDT 24
Peak memory 219120 kb
Host smart-080bf390-42ff-4428-83fe-b6053646d17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145044541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.145044541
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/138.edn_alert.4221088798
Short name T104
Test name
Test status
Simulation time 45244752 ps
CPU time 1.16 seconds
Started Jun 21 06:44:50 PM PDT 24
Finished Jun 21 06:45:23 PM PDT 24
Peak memory 219208 kb
Host smart-d7d83d9c-6b1e-45ff-816c-7217b64691ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221088798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.4221088798
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.1332375022
Short name T364
Test name
Test status
Simulation time 114552561 ps
CPU time 1.1 seconds
Started Jun 21 06:44:50 PM PDT 24
Finished Jun 21 06:45:23 PM PDT 24
Peak memory 216740 kb
Host smart-220b83b4-f668-4b25-a36b-80caacb47610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332375022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1332375022
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.22597300
Short name T601
Test name
Test status
Simulation time 37797068 ps
CPU time 1.38 seconds
Started Jun 21 06:44:50 PM PDT 24
Finished Jun 21 06:45:23 PM PDT 24
Peak memory 217616 kb
Host smart-5ec26d44-4522-4e69-9efc-4494f7f06415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22597300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.22597300
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.197516644
Short name T562
Test name
Test status
Simulation time 126761229 ps
CPU time 1.23 seconds
Started Jun 21 06:41:49 PM PDT 24
Finished Jun 21 06:42:52 PM PDT 24
Peak memory 217648 kb
Host smart-56c3913b-42db-4450-9465-1c67742aafd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197516644 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.197516644
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1603672927
Short name T577
Test name
Test status
Simulation time 33454018 ps
CPU time 0.94 seconds
Started Jun 21 06:41:58 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 206108 kb
Host smart-6bd0a48c-3573-4455-910a-e8b293588882
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603672927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1603672927
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1993800363
Short name T176
Test name
Test status
Simulation time 31155951 ps
CPU time 0.84 seconds
Started Jun 21 06:41:47 PM PDT 24
Finished Jun 21 06:42:52 PM PDT 24
Peak memory 215684 kb
Host smart-d29bfdee-ae59-4d10-b94d-f53bdb8cb9f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993800363 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1993800363
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3241282331
Short name T334
Test name
Test status
Simulation time 38118176 ps
CPU time 1.18 seconds
Started Jun 21 06:41:58 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 217508 kb
Host smart-355b2864-f8ad-449b-87e1-8f3b4d6be02e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241282331 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3241282331
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.4266512402
Short name T468
Test name
Test status
Simulation time 42700515 ps
CPU time 1.18 seconds
Started Jun 21 06:41:47 PM PDT 24
Finished Jun 21 06:42:52 PM PDT 24
Peak memory 224264 kb
Host smart-12907992-174f-4b86-8520-8453ece8411b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266512402 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.4266512402
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1184271789
Short name T738
Test name
Test status
Simulation time 62264695 ps
CPU time 1.43 seconds
Started Jun 21 06:41:48 PM PDT 24
Finished Jun 21 06:42:53 PM PDT 24
Peak memory 218076 kb
Host smart-ac6aff16-2638-444c-812f-f67a2ac29564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184271789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1184271789
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.4281438547
Short name T31
Test name
Test status
Simulation time 20623257 ps
CPU time 1.05 seconds
Started Jun 21 06:41:48 PM PDT 24
Finished Jun 21 06:42:52 PM PDT 24
Peak memory 215040 kb
Host smart-44ae7b70-b334-4388-9555-da7c28a836f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281438547 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.4281438547
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2943512320
Short name T331
Test name
Test status
Simulation time 47925556 ps
CPU time 0.92 seconds
Started Jun 21 06:41:49 PM PDT 24
Finished Jun 21 06:42:52 PM PDT 24
Peak memory 214500 kb
Host smart-92002fa9-47ab-436a-a571-50ad9cd37535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943512320 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2943512320
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.210240719
Short name T710
Test name
Test status
Simulation time 180641039 ps
CPU time 3.52 seconds
Started Jun 21 06:41:48 PM PDT 24
Finished Jun 21 06:42:55 PM PDT 24
Peak memory 214632 kb
Host smart-622514c7-8c23-420d-a6b7-e7f99b777c58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210240719 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.210240719
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/140.edn_alert.1458327179
Short name T786
Test name
Test status
Simulation time 51690876 ps
CPU time 1.17 seconds
Started Jun 21 06:44:48 PM PDT 24
Finished Jun 21 06:45:20 PM PDT 24
Peak memory 218064 kb
Host smart-a87ea2de-7e81-4fbc-813e-e8b572e76e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458327179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.1458327179
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.2928892040
Short name T81
Test name
Test status
Simulation time 68754695 ps
CPU time 1.28 seconds
Started Jun 21 06:44:50 PM PDT 24
Finished Jun 21 06:45:23 PM PDT 24
Peak memory 219256 kb
Host smart-7b1e3789-db2f-48cb-b96a-17d2ab7290fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928892040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2928892040
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.4221705193
Short name T810
Test name
Test status
Simulation time 26697194 ps
CPU time 1.21 seconds
Started Jun 21 06:44:49 PM PDT 24
Finished Jun 21 06:45:20 PM PDT 24
Peak memory 218972 kb
Host smart-679436d8-034a-4461-9f0a-5f3490b304ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221705193 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.4221705193
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.1636756610
Short name T765
Test name
Test status
Simulation time 64912195 ps
CPU time 1.12 seconds
Started Jun 21 06:44:49 PM PDT 24
Finished Jun 21 06:45:20 PM PDT 24
Peak memory 216956 kb
Host smart-544c23bc-7656-4981-aad5-73783e43e196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636756610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1636756610
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.3787035072
Short name T535
Test name
Test status
Simulation time 232679991 ps
CPU time 1.99 seconds
Started Jun 21 06:44:51 PM PDT 24
Finished Jun 21 06:45:24 PM PDT 24
Peak memory 219560 kb
Host smart-e71e4b4f-1e1f-4836-9057-298ef7282f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787035072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3787035072
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.1175022284
Short name T190
Test name
Test status
Simulation time 50405924 ps
CPU time 1.19 seconds
Started Jun 21 06:44:50 PM PDT 24
Finished Jun 21 06:45:23 PM PDT 24
Peak memory 218324 kb
Host smart-ec652db5-4ae9-4500-9c07-8aaf61d5ccd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175022284 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1175022284
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.1503227164
Short name T672
Test name
Test status
Simulation time 37906550 ps
CPU time 1.47 seconds
Started Jun 21 06:44:50 PM PDT 24
Finished Jun 21 06:45:23 PM PDT 24
Peak memory 217892 kb
Host smart-ef77fe7c-6f78-4ee3-a0ec-f8315710450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503227164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1503227164
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.1279294535
Short name T129
Test name
Test status
Simulation time 28006603 ps
CPU time 1.34 seconds
Started Jun 21 06:44:49 PM PDT 24
Finished Jun 21 06:45:20 PM PDT 24
Peak memory 219964 kb
Host smart-e6990570-f384-4b23-9be2-10f38c8a5da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279294535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.1279294535
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.618387371
Short name T340
Test name
Test status
Simulation time 170898521 ps
CPU time 1.61 seconds
Started Jun 21 06:44:51 PM PDT 24
Finished Jun 21 06:45:23 PM PDT 24
Peak memory 218128 kb
Host smart-f32e9873-f750-4a31-a089-f6c0e3eac71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618387371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.618387371
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.3513873441
Short name T597
Test name
Test status
Simulation time 45427519 ps
CPU time 1.14 seconds
Started Jun 21 06:45:05 PM PDT 24
Finished Jun 21 06:45:33 PM PDT 24
Peak memory 217900 kb
Host smart-42eea086-8b6d-4ec1-8981-5808827190fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513873441 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.3513873441
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.4276030870
Short name T325
Test name
Test status
Simulation time 53581677 ps
CPU time 1.86 seconds
Started Jun 21 06:45:03 PM PDT 24
Finished Jun 21 06:45:32 PM PDT 24
Peak memory 217912 kb
Host smart-a97ed6ed-9e4a-4afa-a6c4-fdfa3513fc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276030870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.4276030870
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.4278544390
Short name T573
Test name
Test status
Simulation time 64653413 ps
CPU time 1.14 seconds
Started Jun 21 06:45:05 PM PDT 24
Finished Jun 21 06:45:33 PM PDT 24
Peak memory 217952 kb
Host smart-3626a578-1eb8-492b-a5f2-4b3588a4ac4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278544390 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.4278544390
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.1636107508
Short name T370
Test name
Test status
Simulation time 29584001 ps
CPU time 1.29 seconds
Started Jun 21 06:45:06 PM PDT 24
Finished Jun 21 06:45:34 PM PDT 24
Peak memory 214584 kb
Host smart-c4129d61-783f-4477-82e7-f73db028337c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636107508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1636107508
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.184573426
Short name T271
Test name
Test status
Simulation time 29819197 ps
CPU time 1.22 seconds
Started Jun 21 06:45:06 PM PDT 24
Finished Jun 21 06:45:34 PM PDT 24
Peak memory 220056 kb
Host smart-99ccf211-1ace-4683-bee6-5bbcf3524d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184573426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.184573426
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.604138221
Short name T83
Test name
Test status
Simulation time 55439018 ps
CPU time 1.87 seconds
Started Jun 21 06:45:04 PM PDT 24
Finished Jun 21 06:45:33 PM PDT 24
Peak memory 216812 kb
Host smart-09f17558-6186-4841-b304-423cadc75fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604138221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.604138221
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.60851585
Short name T986
Test name
Test status
Simulation time 119921833 ps
CPU time 1.06 seconds
Started Jun 21 06:45:05 PM PDT 24
Finished Jun 21 06:45:32 PM PDT 24
Peak memory 218720 kb
Host smart-2cf0fc70-d1b4-4a6a-8be3-55ce88eacd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60851585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.60851585
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.544684296
Short name T894
Test name
Test status
Simulation time 212235408 ps
CPU time 1.83 seconds
Started Jun 21 06:45:04 PM PDT 24
Finished Jun 21 06:45:33 PM PDT 24
Peak memory 218768 kb
Host smart-e46b0b5f-9ab4-46db-bde6-8608d901f2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544684296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.544684296
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.118229915
Short name T477
Test name
Test status
Simulation time 92577363 ps
CPU time 1.23 seconds
Started Jun 21 06:45:06 PM PDT 24
Finished Jun 21 06:45:34 PM PDT 24
Peak memory 220152 kb
Host smart-5993f612-4231-4721-8edb-3193f5943eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118229915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.118229915
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.563072052
Short name T642
Test name
Test status
Simulation time 69846932 ps
CPU time 1.06 seconds
Started Jun 21 06:45:06 PM PDT 24
Finished Jun 21 06:45:34 PM PDT 24
Peak memory 216640 kb
Host smart-63f17610-3e89-47cf-80c7-176c2384c2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563072052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.563072052
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1605117713
Short name T581
Test name
Test status
Simulation time 84692316 ps
CPU time 1.2 seconds
Started Jun 21 06:41:58 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 220148 kb
Host smart-04c9330b-f85b-4069-b96b-b629df75b45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605117713 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1605117713
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1222928637
Short name T459
Test name
Test status
Simulation time 41462586 ps
CPU time 0.79 seconds
Started Jun 21 06:42:00 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 205864 kb
Host smart-5cb697f5-81a2-454e-b0d7-6e5d75f3ec56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222928637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1222928637
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.423174694
Short name T401
Test name
Test status
Simulation time 24257211 ps
CPU time 0.88 seconds
Started Jun 21 06:41:56 PM PDT 24
Finished Jun 21 06:42:58 PM PDT 24
Peak memory 215600 kb
Host smart-54183b63-d88c-476f-bcb5-5b08da250bdc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423174694 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.423174694
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_genbits.3367140193
Short name T335
Test name
Test status
Simulation time 58188978 ps
CPU time 1.31 seconds
Started Jun 21 06:41:57 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 214600 kb
Host smart-323e21a9-358d-4a59-af0e-b1f660b72648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367140193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3367140193
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2675862867
Short name T948
Test name
Test status
Simulation time 127380332 ps
CPU time 0.81 seconds
Started Jun 21 06:41:54 PM PDT 24
Finished Jun 21 06:42:55 PM PDT 24
Peak memory 214844 kb
Host smart-cfc17824-19e5-42ad-afd1-60d48236bafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675862867 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2675862867
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3471335717
Short name T843
Test name
Test status
Simulation time 44643799 ps
CPU time 0.95 seconds
Started Jun 21 06:41:55 PM PDT 24
Finished Jun 21 06:42:56 PM PDT 24
Peak memory 214620 kb
Host smart-41029026-2ccc-428e-a917-a170aff5897d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471335717 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3471335717
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2465306237
Short name T876
Test name
Test status
Simulation time 166074109 ps
CPU time 3.74 seconds
Started Jun 21 06:41:56 PM PDT 24
Finished Jun 21 06:43:01 PM PDT 24
Peak memory 214660 kb
Host smart-241f7657-671d-43f7-81a0-ad3fb4514c36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465306237 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2465306237
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/150.edn_alert.3220963952
Short name T744
Test name
Test status
Simulation time 33524401 ps
CPU time 1.05 seconds
Started Jun 21 06:45:05 PM PDT 24
Finished Jun 21 06:45:32 PM PDT 24
Peak memory 219040 kb
Host smart-1127549d-5136-4cd9-a15c-8e940004301b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220963952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.3220963952
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/151.edn_alert.302202368
Short name T618
Test name
Test status
Simulation time 35245193 ps
CPU time 1.17 seconds
Started Jun 21 06:45:06 PM PDT 24
Finished Jun 21 06:45:34 PM PDT 24
Peak memory 218092 kb
Host smart-9e9085f3-2d38-4121-9516-52a56feeaf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302202368 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.302202368
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.482646074
Short name T565
Test name
Test status
Simulation time 123345607 ps
CPU time 1.67 seconds
Started Jun 21 06:45:04 PM PDT 24
Finished Jun 21 06:45:33 PM PDT 24
Peak memory 216736 kb
Host smart-532bbb4b-ac19-410e-ad92-8906ef72b473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482646074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.482646074
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.4254525351
Short name T157
Test name
Test status
Simulation time 72288157 ps
CPU time 1.1 seconds
Started Jun 21 06:45:05 PM PDT 24
Finished Jun 21 06:45:33 PM PDT 24
Peak memory 220276 kb
Host smart-c8e4ee9d-0380-4e71-b0f2-a3f3cfc533c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254525351 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.4254525351
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.4129961365
Short name T886
Test name
Test status
Simulation time 45107783 ps
CPU time 1.56 seconds
Started Jun 21 06:45:05 PM PDT 24
Finished Jun 21 06:45:33 PM PDT 24
Peak memory 217648 kb
Host smart-0cc67610-74de-4849-b3a8-ade5ae6c30fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129961365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.4129961365
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.1590070079
Short name T847
Test name
Test status
Simulation time 38933521 ps
CPU time 1.2 seconds
Started Jun 21 06:45:07 PM PDT 24
Finished Jun 21 06:45:34 PM PDT 24
Peak memory 218692 kb
Host smart-93db97d7-ce27-4dab-8cf6-a70082b79a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590070079 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1590070079
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.1291213783
Short name T404
Test name
Test status
Simulation time 51308954 ps
CPU time 1.52 seconds
Started Jun 21 06:45:06 PM PDT 24
Finished Jun 21 06:45:35 PM PDT 24
Peak memory 218024 kb
Host smart-dbedeb81-5061-4866-838f-a9f3adbb0cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291213783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1291213783
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.3219261315
Short name T754
Test name
Test status
Simulation time 28123023 ps
CPU time 1.22 seconds
Started Jun 21 06:45:03 PM PDT 24
Finished Jun 21 06:45:31 PM PDT 24
Peak memory 215072 kb
Host smart-8f0647bc-6684-4199-af29-2df9f806474b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219261315 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.3219261315
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1440489415
Short name T880
Test name
Test status
Simulation time 38506871 ps
CPU time 1.47 seconds
Started Jun 21 06:45:05 PM PDT 24
Finished Jun 21 06:45:33 PM PDT 24
Peak memory 217012 kb
Host smart-2d2f6c6a-9300-4ba9-a150-f7f861e2e611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440489415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1440489415
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.138816619
Short name T272
Test name
Test status
Simulation time 25969741 ps
CPU time 1.23 seconds
Started Jun 21 06:45:06 PM PDT 24
Finished Jun 21 06:45:34 PM PDT 24
Peak memory 217960 kb
Host smart-093be49e-4eb8-4a27-a4ed-fb1afa1c6d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138816619 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.138816619
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/156.edn_alert.1645218061
Short name T736
Test name
Test status
Simulation time 29932545 ps
CPU time 1.18 seconds
Started Jun 21 06:45:06 PM PDT 24
Finished Jun 21 06:45:34 PM PDT 24
Peak memory 217764 kb
Host smart-99ba2183-5bd5-41c9-9aef-c0f92bdc10d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645218061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.1645218061
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.1790031206
Short name T903
Test name
Test status
Simulation time 120783091 ps
CPU time 1.52 seconds
Started Jun 21 06:45:04 PM PDT 24
Finished Jun 21 06:45:33 PM PDT 24
Peak memory 216772 kb
Host smart-17e95efc-0c21-4986-b914-699edb954ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790031206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1790031206
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.980724474
Short name T223
Test name
Test status
Simulation time 25093750 ps
CPU time 1.23 seconds
Started Jun 21 06:45:05 PM PDT 24
Finished Jun 21 06:45:33 PM PDT 24
Peak memory 219308 kb
Host smart-7e814f57-d9b6-42fb-be78-4a794cc249aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980724474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.980724474
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.2775425904
Short name T200
Test name
Test status
Simulation time 84124492 ps
CPU time 1.29 seconds
Started Jun 21 06:45:06 PM PDT 24
Finished Jun 21 06:45:34 PM PDT 24
Peak memory 218008 kb
Host smart-9d65ca81-f669-452a-bcd2-be97243c5331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775425904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2775425904
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.1036609329
Short name T585
Test name
Test status
Simulation time 111241114 ps
CPU time 1.22 seconds
Started Jun 21 06:45:06 PM PDT 24
Finished Jun 21 06:45:34 PM PDT 24
Peak memory 217904 kb
Host smart-691f3740-2f88-461f-abfa-58f067a2cf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036609329 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.1036609329
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.151885992
Short name T548
Test name
Test status
Simulation time 44007372 ps
CPU time 1.54 seconds
Started Jun 21 06:45:06 PM PDT 24
Finished Jun 21 06:45:34 PM PDT 24
Peak memory 217816 kb
Host smart-19302d4f-4301-416b-8cb0-ce4c9c0d85e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151885992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.151885992
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.3816409997
Short name T673
Test name
Test status
Simulation time 26566768 ps
CPU time 1.19 seconds
Started Jun 21 06:45:04 PM PDT 24
Finished Jun 21 06:45:33 PM PDT 24
Peak memory 217940 kb
Host smart-d6e043c6-7028-4817-8268-0f43b8ab834b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816409997 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.3816409997
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.1804637941
Short name T943
Test name
Test status
Simulation time 37262344 ps
CPU time 1.4 seconds
Started Jun 21 06:45:03 PM PDT 24
Finished Jun 21 06:45:32 PM PDT 24
Peak memory 217932 kb
Host smart-6ca44e7f-58a5-4c0f-8c57-3fdd35c3390c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804637941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1804637941
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1025426361
Short name T845
Test name
Test status
Simulation time 100990868 ps
CPU time 1.17 seconds
Started Jun 21 06:41:56 PM PDT 24
Finished Jun 21 06:42:56 PM PDT 24
Peak memory 218460 kb
Host smart-da1b114d-1144-444f-ab9d-c34685049616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025426361 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1025426361
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2229900097
Short name T563
Test name
Test status
Simulation time 13447871 ps
CPU time 0.85 seconds
Started Jun 21 06:41:59 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 206328 kb
Host smart-927355ce-1bb6-4fe0-95d4-83078a28a0f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229900097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2229900097
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2118905343
Short name T675
Test name
Test status
Simulation time 20430805 ps
CPU time 0.86 seconds
Started Jun 21 06:41:57 PM PDT 24
Finished Jun 21 06:42:58 PM PDT 24
Peak memory 214848 kb
Host smart-b4fa342b-5527-4f3a-a6d8-2d161a49818b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118905343 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2118905343
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.548404959
Short name T851
Test name
Test status
Simulation time 40151075 ps
CPU time 1.13 seconds
Started Jun 21 06:42:02 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 216016 kb
Host smart-02a69b78-4d27-4264-8256-1b2957109008
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548404959 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.548404959
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.284885940
Short name T146
Test name
Test status
Simulation time 21062602 ps
CPU time 1.2 seconds
Started Jun 21 06:42:00 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 219048 kb
Host smart-af5485a3-14ab-433f-b21d-51974e93eca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284885940 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.284885940
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2997107968
Short name T602
Test name
Test status
Simulation time 106370716 ps
CPU time 1.19 seconds
Started Jun 21 06:41:58 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 216448 kb
Host smart-246be3fa-7906-4eb7-840d-a12f057ce6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997107968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2997107968
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2244717133
Short name T427
Test name
Test status
Simulation time 24251343 ps
CPU time 0.93 seconds
Started Jun 21 06:41:57 PM PDT 24
Finished Jun 21 06:42:58 PM PDT 24
Peak memory 215088 kb
Host smart-f8f6709e-2440-43ff-9cd6-dbae989a8910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244717133 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2244717133
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.270112775
Short name T588
Test name
Test status
Simulation time 50830673 ps
CPU time 0.91 seconds
Started Jun 21 06:41:56 PM PDT 24
Finished Jun 21 06:42:58 PM PDT 24
Peak memory 214596 kb
Host smart-ef294105-943b-4632-a7e3-95596e0009b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270112775 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.270112775
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2692216493
Short name T524
Test name
Test status
Simulation time 21214358 ps
CPU time 1.06 seconds
Started Jun 21 06:41:58 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 214556 kb
Host smart-dcc1cf6e-e6f1-44fc-8579-c6a6bc7eb607
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692216493 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2692216493
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3260358659
Short name T713
Test name
Test status
Simulation time 110446169770 ps
CPU time 353.74 seconds
Started Jun 21 06:41:59 PM PDT 24
Finished Jun 21 06:48:52 PM PDT 24
Peak memory 217636 kb
Host smart-0f650bd7-ec3d-47df-a8c4-9c37a04ff051
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260358659 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3260358659
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.2724444480
Short name T399
Test name
Test status
Simulation time 25532405 ps
CPU time 1.21 seconds
Started Jun 21 06:45:09 PM PDT 24
Finished Jun 21 06:45:36 PM PDT 24
Peak memory 219164 kb
Host smart-8544d70a-1e14-409c-a1ed-63f9a3bd1316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724444480 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.2724444480
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1208730138
Short name T979
Test name
Test status
Simulation time 47847032 ps
CPU time 0.94 seconds
Started Jun 21 06:45:11 PM PDT 24
Finished Jun 21 06:45:38 PM PDT 24
Peak memory 216632 kb
Host smart-0e1279d8-94fa-4e88-a525-be7fb2bd6b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208730138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1208730138
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.2750123190
Short name T456
Test name
Test status
Simulation time 168606764 ps
CPU time 1.12 seconds
Started Jun 21 06:45:16 PM PDT 24
Finished Jun 21 06:45:44 PM PDT 24
Peak memory 219068 kb
Host smart-0a12832a-552e-44d9-b102-084493de8e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750123190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.2750123190
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.1832322980
Short name T831
Test name
Test status
Simulation time 137834642 ps
CPU time 2.98 seconds
Started Jun 21 06:45:14 PM PDT 24
Finished Jun 21 06:45:42 PM PDT 24
Peak memory 216320 kb
Host smart-8bb7e5d2-cd42-46ff-a7f6-30207cac0cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832322980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1832322980
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.1493030017
Short name T959
Test name
Test status
Simulation time 74339466 ps
CPU time 1.15 seconds
Started Jun 21 06:45:13 PM PDT 24
Finished Jun 21 06:45:40 PM PDT 24
Peak memory 219224 kb
Host smart-568b5157-63ec-4329-a4b4-ca72f4aa333c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493030017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.1493030017
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.2034670508
Short name T901
Test name
Test status
Simulation time 244186214 ps
CPU time 2.98 seconds
Started Jun 21 06:45:12 PM PDT 24
Finished Jun 21 06:45:42 PM PDT 24
Peak memory 214608 kb
Host smart-152726cd-e50e-4a12-9b4c-880a5434d0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034670508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2034670508
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.360316385
Short name T170
Test name
Test status
Simulation time 74010980 ps
CPU time 1.09 seconds
Started Jun 21 06:45:09 PM PDT 24
Finished Jun 21 06:45:38 PM PDT 24
Peak memory 215080 kb
Host smart-dc00d02e-de31-4a2d-973e-c0b6746f83b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360316385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.360316385
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.1256241487
Short name T353
Test name
Test status
Simulation time 75712621 ps
CPU time 1.22 seconds
Started Jun 21 06:45:12 PM PDT 24
Finished Jun 21 06:45:40 PM PDT 24
Peak memory 218300 kb
Host smart-864704b8-a411-4f49-9fc4-47160bc78f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256241487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1256241487
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.3143603788
Short name T413
Test name
Test status
Simulation time 217065168 ps
CPU time 1.31 seconds
Started Jun 21 06:45:14 PM PDT 24
Finished Jun 21 06:45:40 PM PDT 24
Peak memory 219792 kb
Host smart-3f69be01-7bc1-45b3-a54b-1806ddf8615b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143603788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.3143603788
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.2502509102
Short name T865
Test name
Test status
Simulation time 172122474 ps
CPU time 1.36 seconds
Started Jun 21 06:45:13 PM PDT 24
Finished Jun 21 06:45:40 PM PDT 24
Peak memory 219692 kb
Host smart-7d47eb55-f44d-4f1a-9f3b-ac956e561763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502509102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2502509102
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.3593590628
Short name T918
Test name
Test status
Simulation time 44822858 ps
CPU time 1.16 seconds
Started Jun 21 06:45:13 PM PDT 24
Finished Jun 21 06:45:40 PM PDT 24
Peak memory 218792 kb
Host smart-0b8d40a2-c8b1-44cf-8777-abea7cae40a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593590628 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.3593590628
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1857941736
Short name T78
Test name
Test status
Simulation time 36476155 ps
CPU time 1.49 seconds
Started Jun 21 06:45:16 PM PDT 24
Finished Jun 21 06:45:44 PM PDT 24
Peak memory 217796 kb
Host smart-cb7ee69f-abb0-45a5-a97c-a1de82abc379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857941736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1857941736
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.4002169062
Short name T387
Test name
Test status
Simulation time 57469100 ps
CPU time 1.21 seconds
Started Jun 21 06:45:14 PM PDT 24
Finished Jun 21 06:45:40 PM PDT 24
Peak memory 216616 kb
Host smart-066468fc-15e7-45a8-a52d-b4a8e6ae9c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002169062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.4002169062
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.2051124592
Short name T191
Test name
Test status
Simulation time 43924764 ps
CPU time 1.17 seconds
Started Jun 21 06:45:09 PM PDT 24
Finished Jun 21 06:45:36 PM PDT 24
Peak memory 220436 kb
Host smart-d94b8aed-ddb8-4b21-adf4-c7bedf057f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051124592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.2051124592
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.3733250099
Short name T324
Test name
Test status
Simulation time 124639011 ps
CPU time 1.17 seconds
Started Jun 21 06:45:14 PM PDT 24
Finished Jun 21 06:45:40 PM PDT 24
Peak memory 216800 kb
Host smart-bc25fb95-f67d-4e02-858a-54d6f9ba094f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733250099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3733250099
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.2510775641
Short name T660
Test name
Test status
Simulation time 29191719 ps
CPU time 1.26 seconds
Started Jun 21 06:45:11 PM PDT 24
Finished Jun 21 06:45:39 PM PDT 24
Peak memory 215048 kb
Host smart-330daf45-2ca6-4cfc-a961-13577cd1ef30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510775641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.2510775641
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1281532436
Short name T384
Test name
Test status
Simulation time 39849456 ps
CPU time 1.45 seconds
Started Jun 21 06:45:08 PM PDT 24
Finished Jun 21 06:45:36 PM PDT 24
Peak memory 216604 kb
Host smart-3ce5b4d9-82cf-4813-a707-fc61ae8f8ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281532436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1281532436
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.2537235995
Short name T237
Test name
Test status
Simulation time 28691235 ps
CPU time 1.29 seconds
Started Jun 21 06:45:13 PM PDT 24
Finished Jun 21 06:45:40 PM PDT 24
Peak memory 218916 kb
Host smart-dab01f5e-5a95-4c7a-a660-396277fca8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537235995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2537235995
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.3106624364
Short name T833
Test name
Test status
Simulation time 70527575 ps
CPU time 2.58 seconds
Started Jun 21 06:45:12 PM PDT 24
Finished Jun 21 06:45:41 PM PDT 24
Peak memory 219488 kb
Host smart-9aa53184-6be3-4230-a39d-07a3cb56056b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106624364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3106624364
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2108233597
Short name T689
Test name
Test status
Simulation time 80871964 ps
CPU time 1.14 seconds
Started Jun 21 06:42:00 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 221140 kb
Host smart-4d35fb5d-a723-4dc3-b847-5db497015237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108233597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2108233597
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.167007703
Short name T108
Test name
Test status
Simulation time 19279489 ps
CPU time 0.95 seconds
Started Jun 21 06:42:00 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 206112 kb
Host smart-92c3a5a1-8941-4b78-83e7-a7fc40f8f5c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167007703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.167007703
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.2419356140
Short name T168
Test name
Test status
Simulation time 104394944 ps
CPU time 0.89 seconds
Started Jun 21 06:41:57 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 215488 kb
Host smart-d8e92942-e702-4f52-80b5-9daf470cd4ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419356140 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2419356140
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.4040157820
Short name T460
Test name
Test status
Simulation time 292543257 ps
CPU time 1.02 seconds
Started Jun 21 06:42:00 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 216316 kb
Host smart-f197a4ee-c111-429e-af7c-edf0e0786b29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040157820 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.4040157820
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.69370111
Short name T368
Test name
Test status
Simulation time 51388617 ps
CPU time 1.05 seconds
Started Jun 21 06:42:00 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 218128 kb
Host smart-9be29fc3-9428-4d9e-9d3c-f5bef1694db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69370111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.69370111
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1761520725
Short name T547
Test name
Test status
Simulation time 75052696 ps
CPU time 1.21 seconds
Started Jun 21 06:42:02 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 219656 kb
Host smart-292bf3cb-3a3c-4576-96d3-2bd07bd20bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761520725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1761520725
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3477923136
Short name T785
Test name
Test status
Simulation time 95616037 ps
CPU time 0.94 seconds
Started Jun 21 06:41:58 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 223236 kb
Host smart-dc4aada1-8acd-4530-93b1-29115c684d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477923136 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3477923136
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3392260459
Short name T906
Test name
Test status
Simulation time 23400025 ps
CPU time 0.92 seconds
Started Jun 21 06:41:57 PM PDT 24
Finished Jun 21 06:42:58 PM PDT 24
Peak memory 214620 kb
Host smart-6e1189b5-a421-4ea2-a6ce-2c23a1b6a33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392260459 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3392260459
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1404406500
Short name T422
Test name
Test status
Simulation time 203452256 ps
CPU time 4.32 seconds
Started Jun 21 06:42:02 PM PDT 24
Finished Jun 21 06:43:02 PM PDT 24
Peak memory 217824 kb
Host smart-80e569af-9548-4a88-8cf5-72476010a27b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404406500 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1404406500
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3482924955
Short name T407
Test name
Test status
Simulation time 125107641646 ps
CPU time 1618.19 seconds
Started Jun 21 06:41:56 PM PDT 24
Finished Jun 21 07:09:55 PM PDT 24
Peak memory 226492 kb
Host smart-10ff72f6-0c2e-4897-a2ce-415138eb4255
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482924955 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3482924955
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.4166819665
Short name T151
Test name
Test status
Simulation time 26903389 ps
CPU time 1.19 seconds
Started Jun 21 06:45:11 PM PDT 24
Finished Jun 21 06:45:39 PM PDT 24
Peak memory 218592 kb
Host smart-2ddce34c-a1fd-47fc-91c2-ac78d7d8c740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166819665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.4166819665
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.3971867235
Short name T312
Test name
Test status
Simulation time 39205671 ps
CPU time 1.5 seconds
Started Jun 21 06:45:11 PM PDT 24
Finished Jun 21 06:45:39 PM PDT 24
Peak memory 217720 kb
Host smart-003b65f4-4aed-43a3-a244-66f55753154c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971867235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3971867235
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.2773347814
Short name T788
Test name
Test status
Simulation time 154216752 ps
CPU time 1.13 seconds
Started Jun 21 06:45:13 PM PDT 24
Finished Jun 21 06:45:40 PM PDT 24
Peak memory 218432 kb
Host smart-775d929d-24aa-41f7-a02d-3ba7ba05ad9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773347814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.2773347814
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.930223999
Short name T323
Test name
Test status
Simulation time 53675519 ps
CPU time 1.66 seconds
Started Jun 21 06:45:13 PM PDT 24
Finished Jun 21 06:45:40 PM PDT 24
Peak memory 217684 kb
Host smart-5fbcfa6a-d097-4bad-93cd-f1a3d4aafd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930223999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.930223999
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.579435816
Short name T137
Test name
Test status
Simulation time 22458575 ps
CPU time 1.2 seconds
Started Jun 21 06:45:16 PM PDT 24
Finished Jun 21 06:45:44 PM PDT 24
Peak memory 218080 kb
Host smart-6f530585-abfd-4162-b029-6fba911b7336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579435816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.579435816
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.3682767757
Short name T921
Test name
Test status
Simulation time 35520447 ps
CPU time 1.09 seconds
Started Jun 21 06:45:13 PM PDT 24
Finished Jun 21 06:45:40 PM PDT 24
Peak memory 216536 kb
Host smart-18b952a7-e58e-450e-b850-4575722158f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682767757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3682767757
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.3595135350
Short name T616
Test name
Test status
Simulation time 44795527 ps
CPU time 1.16 seconds
Started Jun 21 06:45:11 PM PDT 24
Finished Jun 21 06:45:38 PM PDT 24
Peak memory 217932 kb
Host smart-6f2654f3-fde6-4419-9686-ebe5e4b004d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595135350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3595135350
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.1588218774
Short name T400
Test name
Test status
Simulation time 219091727 ps
CPU time 1.23 seconds
Started Jun 21 06:45:11 PM PDT 24
Finished Jun 21 06:45:38 PM PDT 24
Peak memory 216708 kb
Host smart-bbfc2e78-5f06-482c-a7e8-6c5d640767a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588218774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1588218774
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.1556227332
Short name T510
Test name
Test status
Simulation time 68610644 ps
CPU time 1.08 seconds
Started Jun 21 06:45:13 PM PDT 24
Finished Jun 21 06:45:40 PM PDT 24
Peak memory 218176 kb
Host smart-e84c9eb8-2445-4ae0-9a86-679858330e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556227332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.1556227332
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.2008119051
Short name T72
Test name
Test status
Simulation time 59832677 ps
CPU time 1.68 seconds
Started Jun 21 06:45:10 PM PDT 24
Finished Jun 21 06:45:39 PM PDT 24
Peak memory 217804 kb
Host smart-fac7bca5-8fc1-4ef8-a63c-2996f883542d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008119051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2008119051
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3218660095
Short name T545
Test name
Test status
Simulation time 38849020 ps
CPU time 1.33 seconds
Started Jun 21 06:45:13 PM PDT 24
Finished Jun 21 06:45:40 PM PDT 24
Peak memory 219076 kb
Host smart-44d8ab3e-7882-4424-a0de-c953b4085cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218660095 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3218660095
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.1342890249
Short name T423
Test name
Test status
Simulation time 89698020 ps
CPU time 1.28 seconds
Started Jun 21 06:45:14 PM PDT 24
Finished Jun 21 06:45:40 PM PDT 24
Peak memory 218064 kb
Host smart-87a53965-cd53-4f15-abaa-acc022d9a459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342890249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1342890249
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.4133518721
Short name T492
Test name
Test status
Simulation time 38931042 ps
CPU time 1.14 seconds
Started Jun 21 06:45:14 PM PDT 24
Finished Jun 21 06:45:40 PM PDT 24
Peak memory 218992 kb
Host smart-b7152fb6-ece5-4e5d-8d45-b0be41cadffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133518721 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.4133518721
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.2898907780
Short name T342
Test name
Test status
Simulation time 2294418722 ps
CPU time 74.59 seconds
Started Jun 21 06:45:14 PM PDT 24
Finished Jun 21 06:46:53 PM PDT 24
Peak memory 219604 kb
Host smart-ca5beb5c-fa62-4744-b61d-c8f6e4458652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898907780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2898907780
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.1597008704
Short name T632
Test name
Test status
Simulation time 114356076 ps
CPU time 2.66 seconds
Started Jun 21 06:45:13 PM PDT 24
Finished Jun 21 06:45:41 PM PDT 24
Peak memory 219284 kb
Host smart-7bc52c59-be14-4cc6-b34a-c6c99a24c1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597008704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1597008704
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.1935406983
Short name T172
Test name
Test status
Simulation time 24032011 ps
CPU time 1.18 seconds
Started Jun 21 06:45:10 PM PDT 24
Finished Jun 21 06:45:38 PM PDT 24
Peak memory 219072 kb
Host smart-c8191b64-e65b-4f23-9571-f93b66feab31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935406983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.1935406983
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.860643921
Short name T825
Test name
Test status
Simulation time 68433106 ps
CPU time 1.52 seconds
Started Jun 21 06:45:10 PM PDT 24
Finished Jun 21 06:45:39 PM PDT 24
Peak memory 217948 kb
Host smart-3d468d70-a8f8-477f-b0a1-84b18041b0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860643921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.860643921
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.4017906455
Short name T64
Test name
Test status
Simulation time 22554824 ps
CPU time 1.15 seconds
Started Jun 21 06:45:20 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 219200 kb
Host smart-f80e220e-7d82-4802-a553-ee3b5cec9d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017906455 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.4017906455
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.959969790
Short name T582
Test name
Test status
Simulation time 42130122 ps
CPU time 1.15 seconds
Started Jun 21 06:45:20 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 216572 kb
Host smart-398210d8-a87a-4e41-87bb-777b9b54085a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959969790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.959969790
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.801910183
Short name T270
Test name
Test status
Simulation time 30159428 ps
CPU time 1.32 seconds
Started Jun 21 06:42:03 PM PDT 24
Finished Jun 21 06:43:01 PM PDT 24
Peak memory 218880 kb
Host smart-2422f361-f56c-4446-96fb-dce6f741e9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801910183 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.801910183
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2386086191
Short name T860
Test name
Test status
Simulation time 67909308 ps
CPU time 0.85 seconds
Started Jun 21 06:42:05 PM PDT 24
Finished Jun 21 06:43:01 PM PDT 24
Peak memory 205940 kb
Host smart-a8b63f52-75fb-4f56-bf75-dbffb7cda2f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386086191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2386086191
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3605402127
Short name T175
Test name
Test status
Simulation time 108107624 ps
CPU time 0.84 seconds
Started Jun 21 06:42:05 PM PDT 24
Finished Jun 21 06:43:01 PM PDT 24
Peak memory 215760 kb
Host smart-1aeadf11-75c0-4585-bc4e-a024803724be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605402127 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3605402127
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.1405635310
Short name T965
Test name
Test status
Simulation time 30674546 ps
CPU time 0.88 seconds
Started Jun 21 06:42:13 PM PDT 24
Finished Jun 21 06:43:06 PM PDT 24
Peak memory 217836 kb
Host smart-eed9c441-3ebe-401e-af20-eb712c11a007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405635310 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1405635310
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1616279632
Short name T557
Test name
Test status
Simulation time 33469783 ps
CPU time 1.42 seconds
Started Jun 21 06:41:58 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 217644 kb
Host smart-fc8dfb43-1fe4-414b-9ecd-3413a794c932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616279632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1616279632
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.252420787
Short name T697
Test name
Test status
Simulation time 19510291 ps
CPU time 1.07 seconds
Started Jun 21 06:42:04 PM PDT 24
Finished Jun 21 06:43:01 PM PDT 24
Peak memory 215080 kb
Host smart-95a73ea6-8b63-4cae-97b7-becd866dfb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252420787 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.252420787
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3936790722
Short name T338
Test name
Test status
Simulation time 62473408 ps
CPU time 0.96 seconds
Started Jun 21 06:42:02 PM PDT 24
Finished Jun 21 06:42:59 PM PDT 24
Peak memory 214620 kb
Host smart-5a08f8b8-266d-4c64-b69c-8e626d2dff66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936790722 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3936790722
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1391528207
Short name T474
Test name
Test status
Simulation time 2297726579 ps
CPU time 5.51 seconds
Started Jun 21 06:41:58 PM PDT 24
Finished Jun 21 06:43:03 PM PDT 24
Peak memory 219052 kb
Host smart-8b0379ad-981f-4131-876b-4dc8f9db0cc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391528207 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1391528207
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2591841863
Short name T295
Test name
Test status
Simulation time 267586634298 ps
CPU time 2703.3 seconds
Started Jun 21 06:41:58 PM PDT 24
Finished Jun 21 07:28:01 PM PDT 24
Peak memory 232356 kb
Host smart-1ae726d9-294a-4e7a-81d7-452a0c29f041
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591841863 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2591841863
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.1918473288
Short name T287
Test name
Test status
Simulation time 245646076 ps
CPU time 1.31 seconds
Started Jun 21 06:45:20 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 219796 kb
Host smart-37b4d681-59fd-456b-b38e-d4d485d8cd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918473288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.1918473288
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.3810168104
Short name T538
Test name
Test status
Simulation time 56938295 ps
CPU time 1.31 seconds
Started Jun 21 06:45:18 PM PDT 24
Finished Jun 21 06:45:45 PM PDT 24
Peak memory 216660 kb
Host smart-bdba9256-faa5-4f74-bcab-0daf46141763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810168104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3810168104
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.1681395133
Short name T74
Test name
Test status
Simulation time 119599746 ps
CPU time 1.16 seconds
Started Jun 21 06:45:20 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 218004 kb
Host smart-5bcaa8b2-be7f-4bc0-88c0-c158d56ad036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681395133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.1681395133
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.2751842921
Short name T966
Test name
Test status
Simulation time 41800404 ps
CPU time 1.45 seconds
Started Jun 21 06:45:17 PM PDT 24
Finished Jun 21 06:45:45 PM PDT 24
Peak memory 217808 kb
Host smart-9ed1b18b-8b2b-490a-abe8-a30d0b933b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751842921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2751842921
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.2197997307
Short name T973
Test name
Test status
Simulation time 27065221 ps
CPU time 1.26 seconds
Started Jun 21 06:45:19 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 219216 kb
Host smart-597c34d4-dfd9-4ef8-a42b-c694a55bc3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197997307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2197997307
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.1111562336
Short name T909
Test name
Test status
Simulation time 68547289 ps
CPU time 1.15 seconds
Started Jun 21 06:45:18 PM PDT 24
Finished Jun 21 06:45:45 PM PDT 24
Peak memory 216644 kb
Host smart-a18c2f8c-7745-4ff0-8866-749a392f73c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111562336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1111562336
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.731248191
Short name T706
Test name
Test status
Simulation time 21665147 ps
CPU time 1.14 seconds
Started Jun 21 06:45:19 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 218120 kb
Host smart-35559ccd-aa70-4e79-9e90-caaaedefe76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731248191 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.731248191
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.3490026470
Short name T657
Test name
Test status
Simulation time 50232313 ps
CPU time 1.58 seconds
Started Jun 21 06:45:20 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 219400 kb
Host smart-35a53ae7-019d-491e-9d3c-e38ed7103da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490026470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3490026470
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.1653818969
Short name T106
Test name
Test status
Simulation time 22816452 ps
CPU time 1.15 seconds
Started Jun 21 06:45:19 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 219304 kb
Host smart-3c73802b-de01-4a01-99f4-08c0ecbf7f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653818969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.1653818969
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.823690399
Short name T326
Test name
Test status
Simulation time 57764145 ps
CPU time 2.02 seconds
Started Jun 21 06:45:19 PM PDT 24
Finished Jun 21 06:45:48 PM PDT 24
Peak memory 216868 kb
Host smart-43839320-62b9-4371-99ea-d41dc6b13af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823690399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.823690399
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.981144445
Short name T509
Test name
Test status
Simulation time 121724668 ps
CPU time 1.27 seconds
Started Jun 21 06:45:19 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 217864 kb
Host smart-15475c8b-1a74-4ba2-a7cc-173ea23f540e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981144445 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.981144445
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.143641074
Short name T530
Test name
Test status
Simulation time 66661684 ps
CPU time 0.98 seconds
Started Jun 21 06:45:18 PM PDT 24
Finished Jun 21 06:45:45 PM PDT 24
Peak memory 216608 kb
Host smart-8bbf2b57-f6f6-4e53-947c-b8d96d653baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143641074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.143641074
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.1453959421
Short name T408
Test name
Test status
Simulation time 48766728 ps
CPU time 1.43 seconds
Started Jun 21 06:45:20 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 217868 kb
Host smart-1ad90241-c225-4eb2-a0c8-4c5c0bc14b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453959421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1453959421
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.3636788735
Short name T264
Test name
Test status
Simulation time 58492126 ps
CPU time 1.23 seconds
Started Jun 21 06:45:17 PM PDT 24
Finished Jun 21 06:45:45 PM PDT 24
Peak memory 217660 kb
Host smart-15665e4c-6c6b-41e1-a597-96172d89af08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636788735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3636788735
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.791240137
Short name T656
Test name
Test status
Simulation time 111704414 ps
CPU time 1.32 seconds
Started Jun 21 06:45:22 PM PDT 24
Finished Jun 21 06:45:49 PM PDT 24
Peak memory 215032 kb
Host smart-4446eb15-9b47-4f81-99a2-428d0388c8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791240137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.791240137
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.3308594130
Short name T463
Test name
Test status
Simulation time 88214131 ps
CPU time 1.25 seconds
Started Jun 21 06:45:19 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 216576 kb
Host smart-d74a8d75-afd7-4e25-bdb3-8034f73c565a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308594130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3308594130
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.3146600876
Short name T111
Test name
Test status
Simulation time 109686678 ps
CPU time 1.16 seconds
Started Jun 21 06:45:20 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 219216 kb
Host smart-3bd43d62-0bd0-4150-92e8-473c4b2ef7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146600876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.3146600876
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.3157159714
Short name T266
Test name
Test status
Simulation time 42640383 ps
CPU time 1.41 seconds
Started Jun 21 06:45:18 PM PDT 24
Finished Jun 21 06:45:45 PM PDT 24
Peak memory 214616 kb
Host smart-062101f2-e90f-4bd9-8802-53eb0b68cf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157159714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3157159714
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1887180027
Short name T120
Test name
Test status
Simulation time 23606921 ps
CPU time 1.25 seconds
Started Jun 21 06:42:08 PM PDT 24
Finished Jun 21 06:43:04 PM PDT 24
Peak memory 220040 kb
Host smart-fe93c768-e988-4581-b4a8-c8687801acfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887180027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1887180027
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3917529877
Short name T446
Test name
Test status
Simulation time 29853196 ps
CPU time 0.92 seconds
Started Jun 21 06:42:04 PM PDT 24
Finished Jun 21 06:43:01 PM PDT 24
Peak memory 214312 kb
Host smart-b46c00cd-34c1-4de9-84bd-1f46f36a347f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917529877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3917529877
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_err.1769888331
Short name T684
Test name
Test status
Simulation time 20915685 ps
CPU time 1.16 seconds
Started Jun 21 06:42:09 PM PDT 24
Finished Jun 21 06:43:03 PM PDT 24
Peak memory 219212 kb
Host smart-2a827d33-acfc-43ed-a5c9-60f3b4628d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769888331 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1769888331
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.236009792
Short name T390
Test name
Test status
Simulation time 35891810 ps
CPU time 1.42 seconds
Started Jun 21 06:42:04 PM PDT 24
Finished Jun 21 06:43:01 PM PDT 24
Peak memory 219384 kb
Host smart-3ee1b456-5ab0-4e71-99f8-8e1e7fbb059b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236009792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.236009792
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_smoke.2891485166
Short name T842
Test name
Test status
Simulation time 24451117 ps
CPU time 0.97 seconds
Started Jun 21 06:42:05 PM PDT 24
Finished Jun 21 06:43:01 PM PDT 24
Peak memory 214656 kb
Host smart-3462d535-02b2-43c8-98d8-daf4c4ec3ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891485166 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2891485166
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1661663510
Short name T546
Test name
Test status
Simulation time 318003286 ps
CPU time 3.91 seconds
Started Jun 21 06:42:13 PM PDT 24
Finished Jun 21 06:43:09 PM PDT 24
Peak memory 219560 kb
Host smart-8646349f-9ff6-4426-a70a-4008c7ec9575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661663510 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1661663510
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1119751326
Short name T322
Test name
Test status
Simulation time 228767303465 ps
CPU time 1001.38 seconds
Started Jun 21 06:42:05 PM PDT 24
Finished Jun 21 06:59:42 PM PDT 24
Peak memory 222904 kb
Host smart-90fdf346-dafc-41d4-9c8b-d8375fd7812b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119751326 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1119751326
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.819728225
Short name T82
Test name
Test status
Simulation time 28330695 ps
CPU time 1.31 seconds
Started Jun 21 06:45:22 PM PDT 24
Finished Jun 21 06:45:49 PM PDT 24
Peak memory 220088 kb
Host smart-db9da5b9-ce99-45eb-8171-e9d35281c31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819728225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.819728225
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.2070976146
Short name T495
Test name
Test status
Simulation time 108071104 ps
CPU time 1.03 seconds
Started Jun 21 06:45:17 PM PDT 24
Finished Jun 21 06:45:45 PM PDT 24
Peak memory 216540 kb
Host smart-c68db319-1bd6-4ada-9124-bcb380e228eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070976146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2070976146
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.3515072486
Short name T933
Test name
Test status
Simulation time 40489998 ps
CPU time 1.15 seconds
Started Jun 21 06:45:20 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 218048 kb
Host smart-22a4175b-83ff-4719-890d-3e6d79a0bfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515072486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.3515072486
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.932829177
Short name T828
Test name
Test status
Simulation time 74862036 ps
CPU time 1.18 seconds
Started Jun 21 06:45:20 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 219556 kb
Host smart-0bb27b99-ca2b-4f95-80f0-608552fcb330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932829177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.932829177
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.84025042
Short name T658
Test name
Test status
Simulation time 75335514 ps
CPU time 1.14 seconds
Started Jun 21 06:45:20 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 217996 kb
Host smart-6e672850-3a60-425e-8a80-2a1184061f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84025042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.84025042
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.2469461279
Short name T455
Test name
Test status
Simulation time 51828685 ps
CPU time 1.22 seconds
Started Jun 21 06:45:18 PM PDT 24
Finished Jun 21 06:45:45 PM PDT 24
Peak memory 216656 kb
Host smart-e93b0bb9-8f1b-4fa9-ba8f-8d89e1e8fb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469461279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2469461279
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.938818277
Short name T66
Test name
Test status
Simulation time 167197758 ps
CPU time 1.14 seconds
Started Jun 21 06:45:18 PM PDT 24
Finished Jun 21 06:45:45 PM PDT 24
Peak memory 218012 kb
Host smart-36929197-0163-49f2-8f0c-186e49e8c84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938818277 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.938818277
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.1217333213
Short name T315
Test name
Test status
Simulation time 35096157 ps
CPU time 1.37 seconds
Started Jun 21 06:45:18 PM PDT 24
Finished Jun 21 06:45:45 PM PDT 24
Peak memory 217884 kb
Host smart-e690a6fb-9054-4414-ad56-175e40e5ad51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217333213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1217333213
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.2462900358
Short name T652
Test name
Test status
Simulation time 112616516 ps
CPU time 1.31 seconds
Started Jun 21 06:45:16 PM PDT 24
Finished Jun 21 06:45:42 PM PDT 24
Peak memory 215096 kb
Host smart-f3c99dff-8cc7-400e-83af-5776b8278f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462900358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.2462900358
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.62061130
Short name T954
Test name
Test status
Simulation time 51090082 ps
CPU time 1.17 seconds
Started Jun 21 06:45:18 PM PDT 24
Finished Jun 21 06:45:45 PM PDT 24
Peak memory 216592 kb
Host smart-4a8ce050-99cf-4e87-902b-01a3201edafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62061130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.62061130
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.4228694024
Short name T180
Test name
Test status
Simulation time 61430203 ps
CPU time 1.13 seconds
Started Jun 21 06:45:19 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 219028 kb
Host smart-e8043db8-6482-4fa1-a132-07e0c1afae38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228694024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.4228694024
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.1768503321
Short name T615
Test name
Test status
Simulation time 71073439 ps
CPU time 1.1 seconds
Started Jun 21 06:45:20 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 216660 kb
Host smart-45054a9b-5956-4e4a-93ca-b7059095025a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768503321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1768503321
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.2671652586
Short name T583
Test name
Test status
Simulation time 104610689 ps
CPU time 1.21 seconds
Started Jun 21 06:45:19 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 215056 kb
Host smart-6ec90043-aed4-45db-8c54-1c8b580fe282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671652586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.2671652586
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.2215962710
Short name T458
Test name
Test status
Simulation time 68858108 ps
CPU time 2.35 seconds
Started Jun 21 06:45:19 PM PDT 24
Finished Jun 21 06:45:48 PM PDT 24
Peak memory 219204 kb
Host smart-cfc3ee83-6829-440b-bce4-3c1cca93ff8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215962710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2215962710
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.3215126142
Short name T953
Test name
Test status
Simulation time 22517533 ps
CPU time 1.22 seconds
Started Jun 21 06:45:20 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 220316 kb
Host smart-33cc2845-073b-455b-ba03-a779a08bf1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215126142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3215126142
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.3467455767
Short name T532
Test name
Test status
Simulation time 138010391 ps
CPU time 1.31 seconds
Started Jun 21 06:45:19 PM PDT 24
Finished Jun 21 06:45:47 PM PDT 24
Peak memory 216508 kb
Host smart-2c8d32e4-3a19-4907-8362-20684ad9eaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467455767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3467455767
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.545089494
Short name T711
Test name
Test status
Simulation time 35792763 ps
CPU time 1.27 seconds
Started Jun 21 06:45:30 PM PDT 24
Finished Jun 21 06:45:56 PM PDT 24
Peak memory 215184 kb
Host smart-96f81de6-ad0e-4945-a10d-5de01e1ace3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545089494 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.545089494
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.1119312815
Short name T712
Test name
Test status
Simulation time 60239108 ps
CPU time 1.36 seconds
Started Jun 21 06:45:34 PM PDT 24
Finished Jun 21 06:46:00 PM PDT 24
Peak memory 216820 kb
Host smart-94a81ef1-2e59-4153-acaa-acfce5f7a9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119312815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1119312815
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.4257332993
Short name T778
Test name
Test status
Simulation time 29154808 ps
CPU time 1.14 seconds
Started Jun 21 06:41:13 PM PDT 24
Finished Jun 21 06:42:20 PM PDT 24
Peak memory 219220 kb
Host smart-33c2f308-51fe-4bca-854d-d8d97ef177ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257332993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.4257332993
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.78328413
Short name T926
Test name
Test status
Simulation time 29684305 ps
CPU time 1.03 seconds
Started Jun 21 06:41:10 PM PDT 24
Finished Jun 21 06:42:14 PM PDT 24
Peak memory 206084 kb
Host smart-01c1e8b0-bbab-463c-a1be-81ec00cc9ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78328413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.78328413
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3266602731
Short name T550
Test name
Test status
Simulation time 21295395 ps
CPU time 0.91 seconds
Started Jun 21 06:41:11 PM PDT 24
Finished Jun 21 06:42:14 PM PDT 24
Peak memory 214880 kb
Host smart-01f370e5-1839-4b9e-aaf5-bebed14eb334
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266602731 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3266602731
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2235554077
Short name T461
Test name
Test status
Simulation time 58805446 ps
CPU time 1.06 seconds
Started Jun 21 06:41:13 PM PDT 24
Finished Jun 21 06:42:19 PM PDT 24
Peak memory 216256 kb
Host smart-4016310c-a2d9-49ba-8457-33a1a7a9c12e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235554077 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2235554077
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.2290914732
Short name T970
Test name
Test status
Simulation time 25710884 ps
CPU time 1.04 seconds
Started Jun 21 06:41:13 PM PDT 24
Finished Jun 21 06:42:19 PM PDT 24
Peak memory 223440 kb
Host smart-ac1779dc-7cfd-4c69-a4f0-fbfd20e69f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290914732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2290914732
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3936361159
Short name T488
Test name
Test status
Simulation time 325780394 ps
CPU time 1.81 seconds
Started Jun 21 06:41:11 PM PDT 24
Finished Jun 21 06:42:15 PM PDT 24
Peak memory 214688 kb
Host smart-8b2d3cf7-85b1-4a15-9f11-2a60573c45c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936361159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3936361159
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.1069691888
Short name T620
Test name
Test status
Simulation time 46140166 ps
CPU time 0.9 seconds
Started Jun 21 06:41:13 PM PDT 24
Finished Jun 21 06:42:19 PM PDT 24
Peak memory 206372 kb
Host smart-049cde98-e641-40ab-b2a3-78fd884f17f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069691888 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1069691888
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1662771086
Short name T15
Test name
Test status
Simulation time 852848348 ps
CPU time 12.64 seconds
Started Jun 21 06:41:21 PM PDT 24
Finished Jun 21 06:42:40 PM PDT 24
Peak memory 236960 kb
Host smart-8bd7a594-0e7c-4ecf-bba7-7515eb959063
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662771086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1662771086
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1618775197
Short name T358
Test name
Test status
Simulation time 17609603 ps
CPU time 1 seconds
Started Jun 21 06:41:10 PM PDT 24
Finished Jun 21 06:42:14 PM PDT 24
Peak memory 214600 kb
Host smart-c9f04c59-9a23-4d6d-8203-8a81a31ecb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618775197 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1618775197
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2560378569
Short name T344
Test name
Test status
Simulation time 212829123 ps
CPU time 2.71 seconds
Started Jun 21 06:41:10 PM PDT 24
Finished Jun 21 06:42:15 PM PDT 24
Peak memory 217844 kb
Host smart-1fc20ece-f150-4369-93b6-1e82857f937b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560378569 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2560378569
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3808449600
Short name T730
Test name
Test status
Simulation time 56527752754 ps
CPU time 1292.1 seconds
Started Jun 21 06:41:14 PM PDT 24
Finished Jun 21 07:03:51 PM PDT 24
Peak memory 221236 kb
Host smart-3624d29e-5258-4214-8531-4c919594a3fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808449600 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3808449600
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.4049057173
Short name T110
Test name
Test status
Simulation time 53460936 ps
CPU time 1.34 seconds
Started Jun 21 06:42:16 PM PDT 24
Finished Jun 21 06:43:07 PM PDT 24
Peak memory 217768 kb
Host smart-48c8c51b-03bc-4682-818b-3ca278dc87d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049057173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.4049057173
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3534931453
Short name T955
Test name
Test status
Simulation time 42769479 ps
CPU time 0.84 seconds
Started Jun 21 06:42:17 PM PDT 24
Finished Jun 21 06:43:07 PM PDT 24
Peak memory 205936 kb
Host smart-13b7c3b1-10b9-40da-90c2-35f66374d5d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534931453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3534931453
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1908966228
Short name T526
Test name
Test status
Simulation time 33526502 ps
CPU time 0.88 seconds
Started Jun 21 06:42:16 PM PDT 24
Finished Jun 21 06:43:07 PM PDT 24
Peak memory 214832 kb
Host smart-8e2b9459-2d38-486b-a080-91d3b2acd743
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908966228 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1908966228
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1588772501
Short name T610
Test name
Test status
Simulation time 16879860 ps
CPU time 0.96 seconds
Started Jun 21 06:42:17 PM PDT 24
Finished Jun 21 06:43:07 PM PDT 24
Peak memory 219012 kb
Host smart-a0591a33-5dee-4171-90ad-e3dc07672642
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588772501 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1588772501
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.534780782
Short name T770
Test name
Test status
Simulation time 31996882 ps
CPU time 1.03 seconds
Started Jun 21 06:42:16 PM PDT 24
Finished Jun 21 06:43:07 PM PDT 24
Peak memory 223384 kb
Host smart-d6a2398c-227d-4099-896d-4b069f9fdecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534780782 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.534780782
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1656377462
Short name T759
Test name
Test status
Simulation time 99839072 ps
CPU time 1.2 seconds
Started Jun 21 06:42:04 PM PDT 24
Finished Jun 21 06:43:01 PM PDT 24
Peak memory 216652 kb
Host smart-72883ecc-79a4-4faf-9441-7c1c9b8a9db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656377462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1656377462
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3774653563
Short name T97
Test name
Test status
Simulation time 24259452 ps
CPU time 1.06 seconds
Started Jun 21 06:42:15 PM PDT 24
Finished Jun 21 06:43:07 PM PDT 24
Peak memory 215012 kb
Host smart-234dbc71-65a8-41b9-856b-695fc30bfc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774653563 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3774653563
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.808685834
Short name T65
Test name
Test status
Simulation time 51954264 ps
CPU time 0.93 seconds
Started Jun 21 06:42:05 PM PDT 24
Finished Jun 21 06:43:01 PM PDT 24
Peak memory 206464 kb
Host smart-50fc9ff1-7702-4c7a-9e3a-2050003ab9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808685834 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.808685834
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2704732476
Short name T735
Test name
Test status
Simulation time 694464709 ps
CPU time 3.74 seconds
Started Jun 21 06:42:04 PM PDT 24
Finished Jun 21 06:43:03 PM PDT 24
Peak memory 216524 kb
Host smart-cdfca506-245c-4d50-acbd-955ba4c43679
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704732476 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2704732476
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.947349723
Short name T622
Test name
Test status
Simulation time 73172839032 ps
CPU time 472.1 seconds
Started Jun 21 06:42:13 PM PDT 24
Finished Jun 21 06:50:57 PM PDT 24
Peak memory 218288 kb
Host smart-b984e7ac-4b6e-4f95-9ffa-be9eb5c39c5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947349723 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.947349723
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1094642084
Short name T868
Test name
Test status
Simulation time 25049782 ps
CPU time 1.28 seconds
Started Jun 21 06:45:27 PM PDT 24
Finished Jun 21 06:45:54 PM PDT 24
Peak memory 217848 kb
Host smart-87336788-7909-42a5-9a0f-781b0b9dda44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094642084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1094642084
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.198014227
Short name T362
Test name
Test status
Simulation time 53522688 ps
CPU time 1.22 seconds
Started Jun 21 06:45:35 PM PDT 24
Finished Jun 21 06:46:00 PM PDT 24
Peak memory 217732 kb
Host smart-514e618f-69a9-4cd7-89ac-ca2fb97ae59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198014227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.198014227
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.516416357
Short name T553
Test name
Test status
Simulation time 80346450 ps
CPU time 1.1 seconds
Started Jun 21 06:45:35 PM PDT 24
Finished Jun 21 06:46:01 PM PDT 24
Peak memory 218012 kb
Host smart-40e52e5f-64ae-4b6b-af6f-069dc32d8e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516416357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.516416357
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.3643855853
Short name T560
Test name
Test status
Simulation time 49264456 ps
CPU time 1.85 seconds
Started Jun 21 06:45:35 PM PDT 24
Finished Jun 21 06:46:01 PM PDT 24
Peak memory 217824 kb
Host smart-31431699-b70f-4799-ac03-93fd934a5649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643855853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3643855853
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.369698918
Short name T728
Test name
Test status
Simulation time 150536341 ps
CPU time 1.22 seconds
Started Jun 21 06:45:29 PM PDT 24
Finished Jun 21 06:45:55 PM PDT 24
Peak memory 216692 kb
Host smart-1617db65-54f6-427d-b710-1d5483a1385c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369698918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.369698918
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3697574762
Short name T475
Test name
Test status
Simulation time 103961313 ps
CPU time 1.3 seconds
Started Jun 21 06:45:31 PM PDT 24
Finished Jun 21 06:45:58 PM PDT 24
Peak memory 219328 kb
Host smart-41c1269d-dfb5-4e01-9636-e1f0d0bbf5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697574762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3697574762
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.365180871
Short name T774
Test name
Test status
Simulation time 70325136 ps
CPU time 1.31 seconds
Started Jun 21 06:45:34 PM PDT 24
Finished Jun 21 06:46:00 PM PDT 24
Peak memory 218360 kb
Host smart-5553a003-bbf1-4a4f-a87c-a3d250d8ad18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365180871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.365180871
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1952250914
Short name T947
Test name
Test status
Simulation time 218339018 ps
CPU time 2.62 seconds
Started Jun 21 06:45:29 PM PDT 24
Finished Jun 21 06:45:56 PM PDT 24
Peak memory 219744 kb
Host smart-3120398b-59cf-4705-be55-e6120b0ff0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952250914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1952250914
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2564552685
Short name T698
Test name
Test status
Simulation time 45837508 ps
CPU time 1.65 seconds
Started Jun 21 06:45:28 PM PDT 24
Finished Jun 21 06:45:55 PM PDT 24
Peak memory 217736 kb
Host smart-4bf77a9f-21cd-451d-9dc4-22c1c44845ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564552685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2564552685
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.560307505
Short name T899
Test name
Test status
Simulation time 52751006 ps
CPU time 1.54 seconds
Started Jun 21 06:45:30 PM PDT 24
Finished Jun 21 06:45:56 PM PDT 24
Peak memory 219320 kb
Host smart-d6fb07b7-9c6d-49d3-8de7-7d1df8a8506a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560307505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.560307505
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.331533743
Short name T292
Test name
Test status
Simulation time 29730144 ps
CPU time 1.35 seconds
Started Jun 21 06:42:17 PM PDT 24
Finished Jun 21 06:43:07 PM PDT 24
Peak memory 219552 kb
Host smart-d6855463-6c8c-4115-bd72-668c4cf0cdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331533743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.331533743
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1143706588
Short name T804
Test name
Test status
Simulation time 45297284 ps
CPU time 0.85 seconds
Started Jun 21 06:42:17 PM PDT 24
Finished Jun 21 06:43:07 PM PDT 24
Peak memory 205936 kb
Host smart-48af59e5-8dbf-4c9e-bc9c-30e5c6b36e7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143706588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1143706588
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1017156200
Short name T814
Test name
Test status
Simulation time 89545081 ps
CPU time 1.14 seconds
Started Jun 21 06:42:17 PM PDT 24
Finished Jun 21 06:43:07 PM PDT 24
Peak memory 216192 kb
Host smart-c072b8a8-7b44-43f5-8077-9a52eeb0734e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017156200 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1017156200
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.219933237
Short name T203
Test name
Test status
Simulation time 28110549 ps
CPU time 0.93 seconds
Started Jun 21 06:42:18 PM PDT 24
Finished Jun 21 06:43:07 PM PDT 24
Peak memory 218000 kb
Host smart-9d5f0969-e43a-440d-b7e2-016a8950d19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219933237 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.219933237
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.455368481
Short name T415
Test name
Test status
Simulation time 86069734 ps
CPU time 1.71 seconds
Started Jun 21 06:42:17 PM PDT 24
Finished Jun 21 06:43:08 PM PDT 24
Peak memory 219204 kb
Host smart-8a3a2197-b7ea-4ae8-85ba-b9db16065672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455368481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.455368481
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2255769910
Short name T462
Test name
Test status
Simulation time 33237567 ps
CPU time 0.88 seconds
Started Jun 21 06:42:18 PM PDT 24
Finished Jun 21 06:43:07 PM PDT 24
Peak memory 214976 kb
Host smart-685e3fe8-aefd-4bf5-96f3-04772a8df296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255769910 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2255769910
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2447920828
Short name T519
Test name
Test status
Simulation time 40316526 ps
CPU time 0.96 seconds
Started Jun 21 06:42:19 PM PDT 24
Finished Jun 21 06:43:09 PM PDT 24
Peak memory 214640 kb
Host smart-b00b170a-55c2-41e7-b96f-d425b502e78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447920828 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2447920828
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.910658853
Short name T962
Test name
Test status
Simulation time 915248144 ps
CPU time 4.85 seconds
Started Jun 21 06:42:17 PM PDT 24
Finished Jun 21 06:43:11 PM PDT 24
Peak memory 214724 kb
Host smart-a57aff78-143c-4af3-bfc8-1a5b769fc13e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910658853 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.910658853
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1142860905
Short name T232
Test name
Test status
Simulation time 8354522835 ps
CPU time 195.57 seconds
Started Jun 21 06:42:17 PM PDT 24
Finished Jun 21 06:46:22 PM PDT 24
Peak memory 217604 kb
Host smart-f8338cc1-1c29-48c9-a55b-fb9d193007df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142860905 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1142860905
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2595590731
Short name T379
Test name
Test status
Simulation time 72213940 ps
CPU time 1.31 seconds
Started Jun 21 06:45:29 PM PDT 24
Finished Jun 21 06:45:55 PM PDT 24
Peak memory 217720 kb
Host smart-d0fcf46f-0b57-442d-983f-9af120aa5806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595590731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2595590731
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2912308879
Short name T321
Test name
Test status
Simulation time 39424374 ps
CPU time 1.41 seconds
Started Jun 21 06:45:31 PM PDT 24
Finished Jun 21 06:45:58 PM PDT 24
Peak memory 216508 kb
Host smart-8366a41b-11e1-4da1-b75b-ba1907d4521a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912308879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2912308879
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2327396400
Short name T904
Test name
Test status
Simulation time 85996129 ps
CPU time 1.25 seconds
Started Jun 21 06:45:34 PM PDT 24
Finished Jun 21 06:46:00 PM PDT 24
Peak memory 216840 kb
Host smart-4cbbab9b-b54b-4613-a8c8-d4a8f7795c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327396400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2327396400
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3768073773
Short name T776
Test name
Test status
Simulation time 238246168 ps
CPU time 3.18 seconds
Started Jun 21 06:45:29 PM PDT 24
Finished Jun 21 06:45:57 PM PDT 24
Peak memory 217872 kb
Host smart-9c15c755-3827-4bb2-b75d-e5a06005b584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768073773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3768073773
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.568601318
Short name T309
Test name
Test status
Simulation time 46421625 ps
CPU time 1.22 seconds
Started Jun 21 06:45:29 PM PDT 24
Finished Jun 21 06:45:55 PM PDT 24
Peak memory 219248 kb
Host smart-7bda9134-01ae-4115-a31f-100c40df8dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568601318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.568601318
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.4152448443
Short name T305
Test name
Test status
Simulation time 62631025 ps
CPU time 1.08 seconds
Started Jun 21 06:45:33 PM PDT 24
Finished Jun 21 06:45:59 PM PDT 24
Peak memory 216548 kb
Host smart-f7de518d-5279-4b30-945f-dea874eee79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152448443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.4152448443
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.33233426
Short name T664
Test name
Test status
Simulation time 118098403 ps
CPU time 3.07 seconds
Started Jun 21 06:45:31 PM PDT 24
Finished Jun 21 06:45:58 PM PDT 24
Peak memory 218200 kb
Host smart-c3a57a61-3a41-40bf-b3d5-009395912f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33233426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.33233426
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1655268233
Short name T960
Test name
Test status
Simulation time 64635227 ps
CPU time 1.15 seconds
Started Jun 21 06:45:29 PM PDT 24
Finished Jun 21 06:45:55 PM PDT 24
Peak memory 219324 kb
Host smart-ea8c7074-0234-40bb-b96d-0545c04caf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655268233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1655268233
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2440328531
Short name T771
Test name
Test status
Simulation time 91738272 ps
CPU time 1.15 seconds
Started Jun 21 06:45:28 PM PDT 24
Finished Jun 21 06:45:55 PM PDT 24
Peak memory 216676 kb
Host smart-ffb5b4c9-be61-4186-aa53-388a16568624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440328531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2440328531
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.359981440
Short name T128
Test name
Test status
Simulation time 138465910 ps
CPU time 1.27 seconds
Started Jun 21 06:42:15 PM PDT 24
Finished Jun 21 06:43:07 PM PDT 24
Peak memory 217944 kb
Host smart-c1279da2-6ad2-4b87-b75d-5e625274f4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359981440 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.359981440
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3276959623
Short name T629
Test name
Test status
Simulation time 22996579 ps
CPU time 1 seconds
Started Jun 21 06:42:24 PM PDT 24
Finished Jun 21 06:43:12 PM PDT 24
Peak memory 206108 kb
Host smart-575d6f56-c33e-4808-8911-11ebf3cbb684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276959623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3276959623
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.831834002
Short name T727
Test name
Test status
Simulation time 12640488 ps
CPU time 0.86 seconds
Started Jun 21 06:42:16 PM PDT 24
Finished Jun 21 06:43:07 PM PDT 24
Peak memory 215776 kb
Host smart-f20d5063-d12d-4e64-b6a0-d3d1da711a55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831834002 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.831834002
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1740158199
Short name T879
Test name
Test status
Simulation time 26179340 ps
CPU time 1.02 seconds
Started Jun 21 06:42:18 PM PDT 24
Finished Jun 21 06:43:07 PM PDT 24
Peak memory 217460 kb
Host smart-1d2caa5c-7043-4536-839e-dd4fcf68786f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740158199 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1740158199
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_genbits.3293106263
Short name T645
Test name
Test status
Simulation time 65364286 ps
CPU time 2.39 seconds
Started Jun 21 06:42:17 PM PDT 24
Finished Jun 21 06:43:08 PM PDT 24
Peak memory 217896 kb
Host smart-c039b088-1a92-4d9f-82ec-d25d30694a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293106263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3293106263
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.4155997595
Short name T96
Test name
Test status
Simulation time 22106873 ps
CPU time 0.91 seconds
Started Jun 21 06:42:23 PM PDT 24
Finished Jun 21 06:43:09 PM PDT 24
Peak memory 215148 kb
Host smart-7fc7410e-6db2-427a-85a5-def160367add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155997595 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.4155997595
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3793153697
Short name T499
Test name
Test status
Simulation time 22009933 ps
CPU time 0.99 seconds
Started Jun 21 06:42:16 PM PDT 24
Finished Jun 21 06:43:07 PM PDT 24
Peak memory 214628 kb
Host smart-ea54ddc2-aafe-4c2b-baf2-8507740ffb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793153697 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3793153697
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2380402949
Short name T346
Test name
Test status
Simulation time 247383526 ps
CPU time 3.19 seconds
Started Jun 21 06:42:17 PM PDT 24
Finished Jun 21 06:43:09 PM PDT 24
Peak memory 216532 kb
Host smart-7c40a7d6-21dd-44eb-ae14-6c9de0984a48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380402949 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2380402949
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.4071121919
Short name T984
Test name
Test status
Simulation time 163699522193 ps
CPU time 1310.29 seconds
Started Jun 21 06:42:16 PM PDT 24
Finished Jun 21 07:04:56 PM PDT 24
Peak memory 222928 kb
Host smart-d8cbbfc1-4c9d-4ecf-a7b4-d6a5e3386aeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071121919 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.4071121919
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/221.edn_genbits.3234419180
Short name T391
Test name
Test status
Simulation time 73623307 ps
CPU time 1.21 seconds
Started Jun 21 06:45:35 PM PDT 24
Finished Jun 21 06:46:01 PM PDT 24
Peak memory 216608 kb
Host smart-38b16502-1bcc-4cc5-a927-2dc654a38776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234419180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3234419180
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3876130885
Short name T438
Test name
Test status
Simulation time 87135875 ps
CPU time 1.11 seconds
Started Jun 21 06:45:31 PM PDT 24
Finished Jun 21 06:45:57 PM PDT 24
Peak memory 218212 kb
Host smart-f93f1087-3704-4ed9-adbf-31ce36d7cd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876130885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3876130885
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.719627368
Short name T910
Test name
Test status
Simulation time 117669551 ps
CPU time 1.37 seconds
Started Jun 21 06:45:31 PM PDT 24
Finished Jun 21 06:45:58 PM PDT 24
Peak memory 219088 kb
Host smart-e5a71cd6-25ef-482f-8f3a-3ab909a9abee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719627368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.719627368
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3058743090
Short name T426
Test name
Test status
Simulation time 25579872 ps
CPU time 1.24 seconds
Started Jun 21 06:45:35 PM PDT 24
Finished Jun 21 06:46:01 PM PDT 24
Peak memory 217776 kb
Host smart-5ad277ed-4948-489a-94b9-3f1a4d08d94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058743090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3058743090
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1765418159
Short name T42
Test name
Test status
Simulation time 116293625 ps
CPU time 1.6 seconds
Started Jun 21 06:45:33 PM PDT 24
Finished Jun 21 06:46:00 PM PDT 24
Peak memory 218288 kb
Host smart-1719c49f-34e9-4e01-af42-e260d6a12714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765418159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1765418159
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2471071791
Short name T803
Test name
Test status
Simulation time 97873186 ps
CPU time 1.75 seconds
Started Jun 21 06:45:34 PM PDT 24
Finished Jun 21 06:46:01 PM PDT 24
Peak memory 219556 kb
Host smart-16c7a907-c854-4f19-ae3f-65eb17934147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471071791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2471071791
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2460160739
Short name T376
Test name
Test status
Simulation time 58585064 ps
CPU time 1.34 seconds
Started Jun 21 06:45:27 PM PDT 24
Finished Jun 21 06:45:54 PM PDT 24
Peak memory 219100 kb
Host smart-2a826654-7b71-451f-bffb-0c51f39bd477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460160739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2460160739
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1680598042
Short name T382
Test name
Test status
Simulation time 118356608 ps
CPU time 1.38 seconds
Started Jun 21 06:45:33 PM PDT 24
Finished Jun 21 06:46:00 PM PDT 24
Peak memory 216836 kb
Host smart-c4adf280-7620-4858-9bbb-325fcfa108a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680598042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1680598042
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1000675780
Short name T43
Test name
Test status
Simulation time 112763771 ps
CPU time 1.12 seconds
Started Jun 21 06:45:36 PM PDT 24
Finished Jun 21 06:46:01 PM PDT 24
Peak memory 216720 kb
Host smart-7281d37a-5c14-49c7-b8ff-54a93d77bffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000675780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1000675780
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2613127605
Short name T121
Test name
Test status
Simulation time 22743321 ps
CPU time 1.25 seconds
Started Jun 21 06:42:26 PM PDT 24
Finished Jun 21 06:43:13 PM PDT 24
Peak memory 217308 kb
Host smart-756136b0-bb91-4ee5-aabe-7e56373cbbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613127605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2613127605
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.744608751
Short name T594
Test name
Test status
Simulation time 22027843 ps
CPU time 0.86 seconds
Started Jun 21 06:42:25 PM PDT 24
Finished Jun 21 06:43:12 PM PDT 24
Peak memory 206264 kb
Host smart-1d2d5194-f3f6-41e2-8b20-8d0d13614a18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744608751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.744608751
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3402621521
Short name T525
Test name
Test status
Simulation time 46850519 ps
CPU time 0.91 seconds
Started Jun 21 06:42:29 PM PDT 24
Finished Jun 21 06:43:15 PM PDT 24
Peak memory 215656 kb
Host smart-e4c3c9c9-7f7f-48da-bbad-71b239440172
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402621521 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3402621521
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1009662190
Short name T882
Test name
Test status
Simulation time 39162528 ps
CPU time 1.13 seconds
Started Jun 21 06:42:26 PM PDT 24
Finished Jun 21 06:43:13 PM PDT 24
Peak memory 217720 kb
Host smart-2cdd7b4f-bb35-48fc-a448-dc870b082f5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009662190 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1009662190
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1416307317
Short name T124
Test name
Test status
Simulation time 43403672 ps
CPU time 1.26 seconds
Started Jun 21 06:42:27 PM PDT 24
Finished Jun 21 06:43:13 PM PDT 24
Peak memory 227980 kb
Host smart-dbdf3d5b-f89f-4194-85eb-9cf1ab380c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416307317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1416307317
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3562882789
Short name T836
Test name
Test status
Simulation time 36564468 ps
CPU time 0.99 seconds
Started Jun 21 06:42:27 PM PDT 24
Finished Jun 21 06:43:13 PM PDT 24
Peak memory 216512 kb
Host smart-90f59ef2-6b18-4252-b8be-f580857b6f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562882789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3562882789
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1716609142
Short name T908
Test name
Test status
Simulation time 59341383 ps
CPU time 1.03 seconds
Started Jun 21 06:42:26 PM PDT 24
Finished Jun 21 06:43:13 PM PDT 24
Peak memory 222704 kb
Host smart-02e7e0e9-58d3-4209-84c4-1d1651afa1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716609142 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1716609142
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1968205056
Short name T328
Test name
Test status
Simulation time 20315388 ps
CPU time 1.08 seconds
Started Jun 21 06:42:29 PM PDT 24
Finished Jun 21 06:43:15 PM PDT 24
Peak memory 214592 kb
Host smart-8f9ebb2b-36a2-47fc-8061-46744e9d5991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968205056 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1968205056
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.301138069
Short name T937
Test name
Test status
Simulation time 2095730919 ps
CPU time 3.54 seconds
Started Jun 21 06:42:25 PM PDT 24
Finished Jun 21 06:43:14 PM PDT 24
Peak memory 214632 kb
Host smart-6ae115d2-078c-40d0-9aa1-38b334f0ca61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301138069 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.301138069
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2746258199
Short name T768
Test name
Test status
Simulation time 6690181393 ps
CPU time 165.28 seconds
Started Jun 21 06:42:27 PM PDT 24
Finished Jun 21 06:45:57 PM PDT 24
Peak memory 217744 kb
Host smart-e552ca01-52c8-4b7a-8be2-970f8fccba66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746258199 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2746258199
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2281207096
Short name T479
Test name
Test status
Simulation time 44154672 ps
CPU time 1.74 seconds
Started Jun 21 06:45:29 PM PDT 24
Finished Jun 21 06:45:55 PM PDT 24
Peak memory 219172 kb
Host smart-6c529e54-3415-4ff6-ae41-a54d157c7af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281207096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2281207096
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1120768050
Short name T703
Test name
Test status
Simulation time 22223017 ps
CPU time 1.18 seconds
Started Jun 21 06:45:33 PM PDT 24
Finished Jun 21 06:45:59 PM PDT 24
Peak memory 218192 kb
Host smart-d3ddd366-050b-4a45-a2a4-9159a490d82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120768050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1120768050
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.4286813787
Short name T815
Test name
Test status
Simulation time 40020472 ps
CPU time 1.4 seconds
Started Jun 21 06:45:30 PM PDT 24
Finished Jun 21 06:45:56 PM PDT 24
Peak memory 219276 kb
Host smart-8896ed7b-c288-435a-a2b2-8f215aee20a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286813787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.4286813787
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2298781575
Short name T369
Test name
Test status
Simulation time 39386795 ps
CPU time 1.24 seconds
Started Jun 21 06:45:34 PM PDT 24
Finished Jun 21 06:46:00 PM PDT 24
Peak memory 219124 kb
Host smart-014eb901-1992-4d7d-ad66-7a57f19d39ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298781575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2298781575
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2066615085
Short name T497
Test name
Test status
Simulation time 81300863 ps
CPU time 1.3 seconds
Started Jun 21 06:45:33 PM PDT 24
Finished Jun 21 06:46:00 PM PDT 24
Peak memory 216824 kb
Host smart-8364df54-3bde-4e1f-8749-37d8eda15a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066615085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2066615085
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1758321844
Short name T639
Test name
Test status
Simulation time 30279792 ps
CPU time 1.28 seconds
Started Jun 21 06:45:29 PM PDT 24
Finished Jun 21 06:45:56 PM PDT 24
Peak memory 219244 kb
Host smart-cdb7078d-3e23-4b9a-a1c7-cfceb7fd1b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758321844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1758321844
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3335818585
Short name T920
Test name
Test status
Simulation time 26935945 ps
CPU time 1.2 seconds
Started Jun 21 06:45:36 PM PDT 24
Finished Jun 21 06:46:01 PM PDT 24
Peak memory 216744 kb
Host smart-482aac42-e227-41f9-b69d-5b6e999d99d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335818585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3335818585
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1393218111
Short name T593
Test name
Test status
Simulation time 34153678 ps
CPU time 1.44 seconds
Started Jun 21 06:45:31 PM PDT 24
Finished Jun 21 06:45:57 PM PDT 24
Peak memory 218300 kb
Host smart-87e7165f-d377-4684-8d03-399bd0a56ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393218111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1393218111
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3081059648
Short name T783
Test name
Test status
Simulation time 296309809 ps
CPU time 3.56 seconds
Started Jun 21 06:45:27 PM PDT 24
Finished Jun 21 06:45:56 PM PDT 24
Peak memory 219296 kb
Host smart-8063d999-290b-41cc-a117-7f9ef6c6b81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081059648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3081059648
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2099387101
Short name T556
Test name
Test status
Simulation time 50618029 ps
CPU time 1.35 seconds
Started Jun 21 06:45:28 PM PDT 24
Finished Jun 21 06:45:55 PM PDT 24
Peak memory 217640 kb
Host smart-9c00b3d0-e751-4717-af36-0bc4acc40d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099387101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2099387101
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.878489373
Short name T640
Test name
Test status
Simulation time 86640399 ps
CPU time 1.2 seconds
Started Jun 21 06:42:29 PM PDT 24
Finished Jun 21 06:43:15 PM PDT 24
Peak memory 219028 kb
Host smart-8266ddce-73a6-4f9e-8a68-e3c6192a12b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878489373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.878489373
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1239477332
Short name T449
Test name
Test status
Simulation time 13968957 ps
CPU time 0.88 seconds
Started Jun 21 06:42:25 PM PDT 24
Finished Jun 21 06:43:12 PM PDT 24
Peak memory 206408 kb
Host smart-5ca045e5-e226-42fd-874f-e27f0cc1ad3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239477332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1239477332
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2577417482
Short name T188
Test name
Test status
Simulation time 20581402 ps
CPU time 0.89 seconds
Started Jun 21 06:42:25 PM PDT 24
Finished Jun 21 06:43:12 PM PDT 24
Peak memory 215664 kb
Host smart-ba08dd98-d0a4-41c4-9fec-ac6bf13102eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577417482 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2577417482
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2006008012
Short name T668
Test name
Test status
Simulation time 256058154 ps
CPU time 1.21 seconds
Started Jun 21 06:42:25 PM PDT 24
Finished Jun 21 06:43:12 PM PDT 24
Peak memory 216164 kb
Host smart-c4dda116-06d1-40bb-bd67-2a248c6a853f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006008012 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2006008012
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.674095702
Short name T53
Test name
Test status
Simulation time 29443890 ps
CPU time 1.34 seconds
Started Jun 21 06:42:30 PM PDT 24
Finished Jun 21 06:43:16 PM PDT 24
Peak memory 225040 kb
Host smart-39a3266c-a622-4ac6-8752-6e751af677c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674095702 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.674095702
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.294206635
Short name T330
Test name
Test status
Simulation time 86597333 ps
CPU time 1.25 seconds
Started Jun 21 06:42:25 PM PDT 24
Finished Jun 21 06:43:13 PM PDT 24
Peak memory 216728 kb
Host smart-32f1b1ee-7bc7-4897-a0a2-f351414017d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294206635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.294206635
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.143405774
Short name T762
Test name
Test status
Simulation time 35699742 ps
CPU time 0.93 seconds
Started Jun 21 06:42:29 PM PDT 24
Finished Jun 21 06:43:15 PM PDT 24
Peak memory 214604 kb
Host smart-15368d5a-cb0a-4f53-a6e7-7ecfe9953b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143405774 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.143405774
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3072956107
Short name T397
Test name
Test status
Simulation time 36757569 ps
CPU time 0.92 seconds
Started Jun 21 06:42:25 PM PDT 24
Finished Jun 21 06:43:12 PM PDT 24
Peak memory 214644 kb
Host smart-384745d5-0973-4ad9-9979-df3203c6f38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072956107 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3072956107
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1033693553
Short name T829
Test name
Test status
Simulation time 620496232 ps
CPU time 3.53 seconds
Started Jun 21 06:42:26 PM PDT 24
Finished Jun 21 06:43:15 PM PDT 24
Peak memory 216536 kb
Host smart-32223311-f001-41db-8604-641b8da0450f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033693553 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1033693553
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3369821852
Short name T746
Test name
Test status
Simulation time 48151302168 ps
CPU time 292.06 seconds
Started Jun 21 06:42:24 PM PDT 24
Finished Jun 21 06:48:03 PM PDT 24
Peak memory 217228 kb
Host smart-5e332cef-c86f-4125-a805-8b3743c53bfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369821852 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3369821852
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.4079606074
Short name T844
Test name
Test status
Simulation time 127862759 ps
CPU time 2.63 seconds
Started Jun 21 06:45:33 PM PDT 24
Finished Jun 21 06:46:01 PM PDT 24
Peak memory 217832 kb
Host smart-e2e9b07e-6df0-4d49-9006-6617e4ed3d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079606074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.4079606074
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3899890799
Short name T633
Test name
Test status
Simulation time 51463583 ps
CPU time 1.69 seconds
Started Jun 21 06:45:31 PM PDT 24
Finished Jun 21 06:45:57 PM PDT 24
Peak memory 217836 kb
Host smart-a9afafe8-7545-4c03-b00f-e9f47c03c796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899890799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3899890799
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3774059607
Short name T752
Test name
Test status
Simulation time 49631280 ps
CPU time 1.28 seconds
Started Jun 21 06:45:31 PM PDT 24
Finished Jun 21 06:45:57 PM PDT 24
Peak memory 218040 kb
Host smart-86012def-a401-4726-a617-853f12bea146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774059607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3774059607
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.4121539449
Short name T470
Test name
Test status
Simulation time 212285253 ps
CPU time 2.58 seconds
Started Jun 21 06:45:32 PM PDT 24
Finished Jun 21 06:46:00 PM PDT 24
Peak memory 216740 kb
Host smart-4178a35a-e1e1-41d3-ba97-dcc5065864d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121539449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.4121539449
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.738064457
Short name T599
Test name
Test status
Simulation time 55723260 ps
CPU time 2.04 seconds
Started Jun 21 06:45:26 PM PDT 24
Finished Jun 21 06:45:54 PM PDT 24
Peak memory 218944 kb
Host smart-aa28e50b-84af-4556-907a-d19bb6c29c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738064457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.738064457
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1321317583
Short name T451
Test name
Test status
Simulation time 165718854 ps
CPU time 3.49 seconds
Started Jun 21 06:45:35 PM PDT 24
Finished Jun 21 06:46:03 PM PDT 24
Peak memory 218364 kb
Host smart-67cf9170-d73b-449b-9dd5-c061e3873845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321317583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1321317583
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2332025961
Short name T574
Test name
Test status
Simulation time 53886561 ps
CPU time 1.18 seconds
Started Jun 21 06:45:36 PM PDT 24
Finished Jun 21 06:46:01 PM PDT 24
Peak memory 217824 kb
Host smart-7c07f0b5-e09a-417e-8402-f5b9e1e5f0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332025961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2332025961
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.942015035
Short name T709
Test name
Test status
Simulation time 85689515 ps
CPU time 1.46 seconds
Started Jun 21 06:45:42 PM PDT 24
Finished Jun 21 06:46:06 PM PDT 24
Peak memory 218092 kb
Host smart-61287223-59ab-44b9-a119-28f22d247e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942015035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.942015035
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.101733877
Short name T608
Test name
Test status
Simulation time 71605083 ps
CPU time 1.13 seconds
Started Jun 21 06:45:41 PM PDT 24
Finished Jun 21 06:46:05 PM PDT 24
Peak memory 218900 kb
Host smart-8aded438-e3c3-4dc9-8e15-98ba63681178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101733877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.101733877
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.508449604
Short name T289
Test name
Test status
Simulation time 40543576 ps
CPU time 1.2 seconds
Started Jun 21 06:42:33 PM PDT 24
Finished Jun 21 06:43:17 PM PDT 24
Peak memory 220176 kb
Host smart-a87e19f0-1f7e-413a-811b-40fd2c267cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508449604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.508449604
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1457940307
Short name T662
Test name
Test status
Simulation time 142551168 ps
CPU time 0.94 seconds
Started Jun 21 06:42:33 PM PDT 24
Finished Jun 21 06:43:16 PM PDT 24
Peak memory 206144 kb
Host smart-e72fb503-0e5e-445f-8c6b-f60638157209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457940307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1457940307
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2785130150
Short name T19
Test name
Test status
Simulation time 29605980 ps
CPU time 0.8 seconds
Started Jun 21 06:42:33 PM PDT 24
Finished Jun 21 06:43:16 PM PDT 24
Peak memory 215796 kb
Host smart-d231eeca-4a64-4a03-b66d-4fe064eb14a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785130150 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2785130150
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.400072254
Short name T598
Test name
Test status
Simulation time 18323340 ps
CPU time 1.15 seconds
Started Jun 21 06:42:33 PM PDT 24
Finished Jun 21 06:43:17 PM PDT 24
Peak memory 223392 kb
Host smart-abd1bfc4-4bc4-4ffc-a695-93060132ba81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400072254 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.400072254
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.565635727
Short name T73
Test name
Test status
Simulation time 34365088 ps
CPU time 1.55 seconds
Started Jun 21 06:42:24 PM PDT 24
Finished Jun 21 06:43:12 PM PDT 24
Peak memory 217808 kb
Host smart-b5ec698b-e734-4eac-8193-9baebafa1d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565635727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.565635727
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.869959764
Short name T50
Test name
Test status
Simulation time 25099606 ps
CPU time 1.07 seconds
Started Jun 21 06:42:34 PM PDT 24
Finished Jun 21 06:43:17 PM PDT 24
Peak memory 223400 kb
Host smart-34d49bff-9096-483b-b93a-85f2be1a2e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869959764 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.869959764
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3731517518
Short name T398
Test name
Test status
Simulation time 19371991 ps
CPU time 1.05 seconds
Started Jun 21 06:42:25 PM PDT 24
Finished Jun 21 06:43:12 PM PDT 24
Peak memory 214732 kb
Host smart-d8341004-9ac6-461c-bf5b-552c725546fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731517518 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3731517518
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1170674766
Short name T234
Test name
Test status
Simulation time 415873744 ps
CPU time 4.23 seconds
Started Jun 21 06:42:26 PM PDT 24
Finished Jun 21 06:43:16 PM PDT 24
Peak memory 214640 kb
Host smart-aca2a7e9-3a64-45a5-b5a2-a2b9643902f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170674766 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1170674766
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3021969482
Short name T395
Test name
Test status
Simulation time 33526135920 ps
CPU time 387.33 seconds
Started Jun 21 06:42:24 PM PDT 24
Finished Jun 21 06:49:38 PM PDT 24
Peak memory 218272 kb
Host smart-8e73d091-5dcd-419c-b3db-139ad00711a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021969482 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3021969482
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1822129532
Short name T406
Test name
Test status
Simulation time 98602805 ps
CPU time 1.4 seconds
Started Jun 21 06:45:39 PM PDT 24
Finished Jun 21 06:46:04 PM PDT 24
Peak memory 218400 kb
Host smart-fcf3403b-5a72-46ab-a3ff-1467f371f349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822129532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1822129532
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.3626653738
Short name T796
Test name
Test status
Simulation time 53585648 ps
CPU time 1.01 seconds
Started Jun 21 06:45:50 PM PDT 24
Finished Jun 21 06:46:10 PM PDT 24
Peak memory 216836 kb
Host smart-76114884-7b2d-47db-a5f7-fcf7118aaa7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626653738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3626653738
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3374721989
Short name T303
Test name
Test status
Simulation time 302798590 ps
CPU time 3.8 seconds
Started Jun 21 06:45:43 PM PDT 24
Finished Jun 21 06:46:08 PM PDT 24
Peak memory 219396 kb
Host smart-c2091f4e-e2b5-4262-b45e-0139f23934d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374721989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3374721989
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.182202026
Short name T734
Test name
Test status
Simulation time 32403085 ps
CPU time 1.29 seconds
Started Jun 21 06:45:42 PM PDT 24
Finished Jun 21 06:46:06 PM PDT 24
Peak memory 216632 kb
Host smart-d82b825b-5715-4378-90e6-365e483edfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182202026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.182202026
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3416386695
Short name T447
Test name
Test status
Simulation time 134044199 ps
CPU time 1.14 seconds
Started Jun 21 06:45:50 PM PDT 24
Finished Jun 21 06:46:11 PM PDT 24
Peak memory 216692 kb
Host smart-3bf3ecfd-f077-419d-ac50-be60eb0ccaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416386695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3416386695
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.546890455
Short name T12
Test name
Test status
Simulation time 54420170 ps
CPU time 1.27 seconds
Started Jun 21 06:45:37 PM PDT 24
Finished Jun 21 06:46:02 PM PDT 24
Peak memory 216844 kb
Host smart-db72f04d-f2c7-416b-91ae-4e64e72f5888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546890455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.546890455
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3504252759
Short name T103
Test name
Test status
Simulation time 31421624 ps
CPU time 1.08 seconds
Started Jun 21 06:45:37 PM PDT 24
Finished Jun 21 06:46:02 PM PDT 24
Peak memory 216704 kb
Host smart-38a888e2-d396-4859-8a55-b85b6d2a33c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504252759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3504252759
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.902758267
Short name T10
Test name
Test status
Simulation time 285833279 ps
CPU time 1.23 seconds
Started Jun 21 06:45:36 PM PDT 24
Finished Jun 21 06:46:01 PM PDT 24
Peak memory 217048 kb
Host smart-60859556-8f11-4d4d-8e69-5e1e4002cc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902758267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.902758267
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3861655754
Short name T850
Test name
Test status
Simulation time 51260223 ps
CPU time 1.77 seconds
Started Jun 21 06:45:50 PM PDT 24
Finished Jun 21 06:46:11 PM PDT 24
Peak memory 217812 kb
Host smart-8d10fab1-4d1e-4cfe-b605-a3751b8ef7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861655754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3861655754
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert_test.3449195840
Short name T650
Test name
Test status
Simulation time 16001028 ps
CPU time 0.94 seconds
Started Jun 21 06:42:33 PM PDT 24
Finished Jun 21 06:43:16 PM PDT 24
Peak memory 206116 kb
Host smart-56183784-9b83-4f72-b3d2-3a2b54ff73b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449195840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3449195840
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.793575158
Short name T167
Test name
Test status
Simulation time 10735298 ps
CPU time 0.87 seconds
Started Jun 21 06:42:32 PM PDT 24
Finished Jun 21 06:43:15 PM PDT 24
Peak memory 215724 kb
Host smart-1093d7db-81db-459e-8343-58b3843bd155
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793575158 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.793575158
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.760233739
Short name T837
Test name
Test status
Simulation time 33090571 ps
CPU time 1.18 seconds
Started Jun 21 06:42:33 PM PDT 24
Finished Jun 21 06:43:17 PM PDT 24
Peak memory 216188 kb
Host smart-7244f8ad-cf39-42b8-aab1-25c44189bd0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760233739 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_di
sable_auto_req_mode.760233739
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.513593128
Short name T173
Test name
Test status
Simulation time 33838724 ps
CPU time 0.98 seconds
Started Jun 21 06:42:33 PM PDT 24
Finished Jun 21 06:43:17 PM PDT 24
Peak memory 217732 kb
Host smart-f1743e12-9ee3-4b71-b7cb-129afb63fa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513593128 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.513593128
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.29583171
Short name T931
Test name
Test status
Simulation time 75198459 ps
CPU time 1.36 seconds
Started Jun 21 06:42:34 PM PDT 24
Finished Jun 21 06:43:17 PM PDT 24
Peak memory 216588 kb
Host smart-03fc44fa-c627-493c-bfea-4e64c30c3d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29583171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.29583171
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2637865938
Short name T28
Test name
Test status
Simulation time 48091679 ps
CPU time 0.89 seconds
Started Jun 21 06:42:33 PM PDT 24
Finished Jun 21 06:43:15 PM PDT 24
Peak memory 214560 kb
Host smart-4d4ad86a-b6d2-485c-8052-d38ccef0bbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637865938 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2637865938
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3995209049
Short name T481
Test name
Test status
Simulation time 17690943 ps
CPU time 1.02 seconds
Started Jun 21 06:42:35 PM PDT 24
Finished Jun 21 06:43:17 PM PDT 24
Peak memory 214632 kb
Host smart-f97d84dc-f799-4a48-be37-fe87c81da742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995209049 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3995209049
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1323948752
Short name T685
Test name
Test status
Simulation time 49189986303 ps
CPU time 614.82 seconds
Started Jun 21 06:42:33 PM PDT 24
Finished Jun 21 06:53:31 PM PDT 24
Peak memory 222940 kb
Host smart-5998eb4c-35b7-4e0e-ac85-97b8bbc16f6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323948752 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1323948752
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.4146965202
Short name T332
Test name
Test status
Simulation time 47758855 ps
CPU time 1.76 seconds
Started Jun 21 06:45:50 PM PDT 24
Finished Jun 21 06:46:11 PM PDT 24
Peak memory 216768 kb
Host smart-a76e9b5c-739d-49ee-8688-c6e34b1db1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146965202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.4146965202
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.853458798
Short name T590
Test name
Test status
Simulation time 40595527 ps
CPU time 1.62 seconds
Started Jun 21 06:45:37 PM PDT 24
Finished Jun 21 06:46:03 PM PDT 24
Peak memory 218992 kb
Host smart-5c9cfa02-20e8-4cee-a449-65de0a4931d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853458798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.853458798
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2940246672
Short name T779
Test name
Test status
Simulation time 43249095 ps
CPU time 1.14 seconds
Started Jun 21 06:45:43 PM PDT 24
Finished Jun 21 06:46:06 PM PDT 24
Peak memory 216524 kb
Host smart-b4839caf-5934-42b1-9787-8ef775af9ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940246672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2940246672
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3290834983
Short name T489
Test name
Test status
Simulation time 62744577 ps
CPU time 1.28 seconds
Started Jun 21 06:45:43 PM PDT 24
Finished Jun 21 06:46:07 PM PDT 24
Peak memory 217836 kb
Host smart-83c49f8c-ea04-496d-8a99-6471b52f4598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290834983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3290834983
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2182232768
Short name T760
Test name
Test status
Simulation time 42320880 ps
CPU time 1.84 seconds
Started Jun 21 06:45:42 PM PDT 24
Finished Jun 21 06:46:06 PM PDT 24
Peak memory 219668 kb
Host smart-bea5d288-6ff4-44fe-a6a2-a1b142db4f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182232768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2182232768
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3772225280
Short name T354
Test name
Test status
Simulation time 92053281 ps
CPU time 1.06 seconds
Started Jun 21 06:45:50 PM PDT 24
Finished Jun 21 06:46:10 PM PDT 24
Peak memory 216624 kb
Host smart-b63f3285-7e80-416d-8e35-90330cb5e3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772225280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3772225280
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.30752952
Short name T348
Test name
Test status
Simulation time 55325299 ps
CPU time 1.04 seconds
Started Jun 21 06:45:41 PM PDT 24
Finished Jun 21 06:46:05 PM PDT 24
Peak memory 216624 kb
Host smart-b04ba5c0-1624-49f2-8931-da7cc545a20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30752952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.30752952
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3208019226
Short name T603
Test name
Test status
Simulation time 263013676 ps
CPU time 3.54 seconds
Started Jun 21 06:45:38 PM PDT 24
Finished Jun 21 06:46:05 PM PDT 24
Peak memory 219352 kb
Host smart-5f4eac6b-b78d-47f0-a72e-cc27daac33f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208019226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3208019226
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.369259731
Short name T503
Test name
Test status
Simulation time 114478627 ps
CPU time 1.25 seconds
Started Jun 21 06:45:38 PM PDT 24
Finished Jun 21 06:46:02 PM PDT 24
Peak memory 216664 kb
Host smart-70326a09-643b-4d2f-8fd4-5426532219b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369259731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.369259731
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.568888892
Short name T520
Test name
Test status
Simulation time 44562068 ps
CPU time 1.37 seconds
Started Jun 21 06:45:42 PM PDT 24
Finished Jun 21 06:46:06 PM PDT 24
Peak memory 218148 kb
Host smart-ad9b7a11-4084-45df-9b70-0181ce929ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568888892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.568888892
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2810517619
Short name T858
Test name
Test status
Simulation time 28565536 ps
CPU time 1.27 seconds
Started Jun 21 06:42:43 PM PDT 24
Finished Jun 21 06:43:22 PM PDT 24
Peak memory 219156 kb
Host smart-5919c5d5-15de-4e4b-963a-fc5e6fda6b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810517619 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2810517619
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1775152455
Short name T852
Test name
Test status
Simulation time 40988997 ps
CPU time 0.82 seconds
Started Jun 21 06:42:45 PM PDT 24
Finished Jun 21 06:43:22 PM PDT 24
Peak memory 206280 kb
Host smart-045afb32-a265-4475-8ee1-4bb979c82b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775152455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1775152455
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.2489631849
Short name T431
Test name
Test status
Simulation time 31982052 ps
CPU time 0.85 seconds
Started Jun 21 06:42:45 PM PDT 24
Finished Jun 21 06:43:22 PM PDT 24
Peak memory 214836 kb
Host smart-592b93fd-78e4-47df-9cfe-c0ca37026958
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489631849 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2489631849
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2446804018
Short name T958
Test name
Test status
Simulation time 220627934 ps
CPU time 1.09 seconds
Started Jun 21 06:42:43 PM PDT 24
Finished Jun 21 06:43:22 PM PDT 24
Peak memory 219060 kb
Host smart-f64cd8c7-cfe4-4404-8754-6cde840a3267
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446804018 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2446804018
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3478053535
Short name T885
Test name
Test status
Simulation time 63178066 ps
CPU time 1.01 seconds
Started Jun 21 06:42:44 PM PDT 24
Finished Jun 21 06:43:22 PM PDT 24
Peak memory 218080 kb
Host smart-707c7169-2f5c-4f65-9d94-fada853ece94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478053535 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3478053535
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.369298398
Short name T725
Test name
Test status
Simulation time 54196164 ps
CPU time 1.42 seconds
Started Jun 21 06:42:33 PM PDT 24
Finished Jun 21 06:43:17 PM PDT 24
Peak memory 219396 kb
Host smart-1a7a2bbc-098b-40ee-bbcf-7efe44594a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369298398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.369298398
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.149487869
Short name T114
Test name
Test status
Simulation time 22623691 ps
CPU time 0.95 seconds
Started Jun 21 06:42:45 PM PDT 24
Finished Jun 21 06:43:22 PM PDT 24
Peak memory 215032 kb
Host smart-bf37d663-1a19-4867-9d29-2a096090d0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149487869 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.149487869
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3192788036
Short name T472
Test name
Test status
Simulation time 16830967 ps
CPU time 0.96 seconds
Started Jun 21 06:42:33 PM PDT 24
Finished Jun 21 06:43:15 PM PDT 24
Peak memory 214564 kb
Host smart-060a70ba-cca8-4e66-b527-f1564c2a0217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192788036 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3192788036
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1400754385
Short name T575
Test name
Test status
Simulation time 537535706 ps
CPU time 1.66 seconds
Started Jun 21 06:42:42 PM PDT 24
Finished Jun 21 06:43:22 PM PDT 24
Peak memory 216668 kb
Host smart-f1a96d38-c770-4815-942c-a3187ffcac78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400754385 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1400754385
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.106054192
Short name T231
Test name
Test status
Simulation time 168726569367 ps
CPU time 324.65 seconds
Started Jun 21 06:42:42 PM PDT 24
Finished Jun 21 06:48:43 PM PDT 24
Peak memory 218444 kb
Host smart-10352c6d-00fa-41c9-89e3-2e56a255be12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106054192 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.106054192
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.146724841
Short name T339
Test name
Test status
Simulation time 29400740 ps
CPU time 1.06 seconds
Started Jun 21 06:45:41 PM PDT 24
Finished Jun 21 06:46:05 PM PDT 24
Peak memory 216620 kb
Host smart-951f72ef-3abc-4376-bc36-d8ea9874136f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146724841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.146724841
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.4059008917
Short name T420
Test name
Test status
Simulation time 52614110 ps
CPU time 1.84 seconds
Started Jun 21 06:45:50 PM PDT 24
Finished Jun 21 06:46:11 PM PDT 24
Peak memory 217848 kb
Host smart-06c04605-864c-4ece-a90e-02dc9b9a19c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059008917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.4059008917
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3168328581
Short name T757
Test name
Test status
Simulation time 41879020 ps
CPU time 1.53 seconds
Started Jun 21 06:45:37 PM PDT 24
Finished Jun 21 06:46:02 PM PDT 24
Peak memory 217724 kb
Host smart-c46ebb16-2a68-49f9-a7df-8c2259e43462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168328581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3168328581
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3620892428
Short name T367
Test name
Test status
Simulation time 48900455 ps
CPU time 1.27 seconds
Started Jun 21 06:45:47 PM PDT 24
Finished Jun 21 06:46:09 PM PDT 24
Peak memory 217956 kb
Host smart-fb1ab362-be80-41c1-8916-11a42c875b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620892428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3620892428
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.2267351748
Short name T840
Test name
Test status
Simulation time 43283880 ps
CPU time 1.15 seconds
Started Jun 21 06:45:49 PM PDT 24
Finished Jun 21 06:46:10 PM PDT 24
Peak memory 219216 kb
Host smart-58d7184f-af0f-427d-b789-0e8697256289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267351748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.2267351748
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1481286175
Short name T280
Test name
Test status
Simulation time 47691689 ps
CPU time 1.26 seconds
Started Jun 21 06:45:47 PM PDT 24
Finished Jun 21 06:46:09 PM PDT 24
Peak memory 216584 kb
Host smart-805f35a1-9dfa-47a2-be53-5ce6ed4afa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481286175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1481286175
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.477717478
Short name T3
Test name
Test status
Simulation time 33423284 ps
CPU time 1.3 seconds
Started Jun 21 06:45:47 PM PDT 24
Finished Jun 21 06:46:09 PM PDT 24
Peak memory 218964 kb
Host smart-efa9a69a-b3a5-438c-8bd9-0f2543ae9d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477717478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.477717478
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2619287325
Short name T536
Test name
Test status
Simulation time 102825126 ps
CPU time 1.2 seconds
Started Jun 21 06:45:47 PM PDT 24
Finished Jun 21 06:46:08 PM PDT 24
Peak memory 216596 kb
Host smart-9825b99d-9134-47de-b050-06239fa209f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619287325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2619287325
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2871674961
Short name T648
Test name
Test status
Simulation time 69836020 ps
CPU time 1.31 seconds
Started Jun 21 06:45:49 PM PDT 24
Finished Jun 21 06:46:10 PM PDT 24
Peak memory 218356 kb
Host smart-8eceb948-ed87-4158-a9d7-ac2995e6ecda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871674961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2871674961
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2904537034
Short name T238
Test name
Test status
Simulation time 50000610 ps
CPU time 1.28 seconds
Started Jun 21 06:42:45 PM PDT 24
Finished Jun 21 06:43:22 PM PDT 24
Peak memory 217808 kb
Host smart-f42f0d06-d569-4905-88cb-bfd4a49c2b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904537034 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2904537034
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3066568869
Short name T631
Test name
Test status
Simulation time 94734500 ps
CPU time 0.85 seconds
Started Jun 21 06:42:44 PM PDT 24
Finished Jun 21 06:43:22 PM PDT 24
Peak memory 206140 kb
Host smart-2fbb5647-bb6e-4415-b10d-f8e75eadc074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066568869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3066568869
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.4197349243
Short name T571
Test name
Test status
Simulation time 17213028 ps
CPU time 0.88 seconds
Started Jun 21 06:42:44 PM PDT 24
Finished Jun 21 06:43:22 PM PDT 24
Peak memory 215632 kb
Host smart-3d623aad-02b0-48b5-86c2-69b156e00cf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197349243 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.4197349243
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3990777308
Short name T126
Test name
Test status
Simulation time 34091504 ps
CPU time 1.22 seconds
Started Jun 21 06:42:49 PM PDT 24
Finished Jun 21 06:43:25 PM PDT 24
Peak memory 216344 kb
Host smart-d2294365-962b-4471-b0d3-035e6f63327b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990777308 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3990777308
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.144894045
Short name T214
Test name
Test status
Simulation time 28704321 ps
CPU time 1.24 seconds
Started Jun 21 06:42:48 PM PDT 24
Finished Jun 21 06:43:25 PM PDT 24
Peak memory 215012 kb
Host smart-e55d4b45-5c05-459d-b4b7-ee30ce36466b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144894045 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.144894045
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.967687734
Short name T834
Test name
Test status
Simulation time 33582831 ps
CPU time 1.36 seconds
Started Jun 21 06:42:42 PM PDT 24
Finished Jun 21 06:43:22 PM PDT 24
Peak memory 217640 kb
Host smart-5792175e-35b3-4084-bc8a-a0c7e7b25e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967687734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.967687734
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.233525131
Short name T30
Test name
Test status
Simulation time 29329847 ps
CPU time 0.86 seconds
Started Jun 21 06:42:48 PM PDT 24
Finished Jun 21 06:43:25 PM PDT 24
Peak memory 214980 kb
Host smart-0c40bc46-73cf-4a03-ae87-ba63246f9d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233525131 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.233525131
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1884750305
Short name T62
Test name
Test status
Simulation time 17406693 ps
CPU time 0.98 seconds
Started Jun 21 06:42:44 PM PDT 24
Finished Jun 21 06:43:22 PM PDT 24
Peak memory 214612 kb
Host smart-e9d2e44d-5a36-4623-9432-f611d1d02ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884750305 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1884750305
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.523772677
Short name T589
Test name
Test status
Simulation time 195486146 ps
CPU time 1.6 seconds
Started Jun 21 06:42:44 PM PDT 24
Finished Jun 21 06:43:23 PM PDT 24
Peak memory 216672 kb
Host smart-ca455b29-f7b8-433e-9266-a737a36b31fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523772677 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.523772677
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2826991259
Short name T386
Test name
Test status
Simulation time 157694308318 ps
CPU time 1046.04 seconds
Started Jun 21 06:42:49 PM PDT 24
Finished Jun 21 07:00:50 PM PDT 24
Peak memory 223200 kb
Host smart-7164041a-8f6e-4453-b216-bee90c8c37d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826991259 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2826991259
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.182746228
Short name T695
Test name
Test status
Simulation time 83336525 ps
CPU time 1.13 seconds
Started Jun 21 06:45:47 PM PDT 24
Finished Jun 21 06:46:08 PM PDT 24
Peak memory 219124 kb
Host smart-9bb1453b-2f0e-48af-a162-1001f4671c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182746228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.182746228
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.861324409
Short name T579
Test name
Test status
Simulation time 63090823 ps
CPU time 1.35 seconds
Started Jun 21 06:45:49 PM PDT 24
Finished Jun 21 06:46:10 PM PDT 24
Peak memory 218036 kb
Host smart-7fc74271-dadd-41cd-a3a1-9cdf554b8a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861324409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.861324409
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.373284780
Short name T666
Test name
Test status
Simulation time 231056224 ps
CPU time 1.03 seconds
Started Jun 21 06:45:49 PM PDT 24
Finished Jun 21 06:46:09 PM PDT 24
Peak memory 216708 kb
Host smart-48ca9a24-c052-43ec-8a2d-caa90b56569e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373284780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.373284780
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.4182334040
Short name T939
Test name
Test status
Simulation time 255686330 ps
CPU time 3.37 seconds
Started Jun 21 06:45:48 PM PDT 24
Finished Jun 21 06:46:12 PM PDT 24
Peak memory 217952 kb
Host smart-924d128f-9e5a-42fe-9bb0-d64f54dfe208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182334040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.4182334040
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1620939760
Short name T511
Test name
Test status
Simulation time 98009203 ps
CPU time 1.56 seconds
Started Jun 21 06:45:48 PM PDT 24
Finished Jun 21 06:46:10 PM PDT 24
Peak memory 216800 kb
Host smart-006da989-95e5-4e0d-b834-a66da6944dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620939760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1620939760
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.724754770
Short name T604
Test name
Test status
Simulation time 100212573 ps
CPU time 1 seconds
Started Jun 21 06:45:48 PM PDT 24
Finished Jun 21 06:46:09 PM PDT 24
Peak memory 216772 kb
Host smart-ba24151f-250e-44e4-8eb4-d2c937f8b171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724754770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.724754770
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.379079157
Short name T310
Test name
Test status
Simulation time 33561295 ps
CPU time 1.44 seconds
Started Jun 21 06:45:48 PM PDT 24
Finished Jun 21 06:46:10 PM PDT 24
Peak memory 217964 kb
Host smart-affb08e6-16cb-4b2d-80b8-3051ab021e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379079157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.379079157
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3732711051
Short name T812
Test name
Test status
Simulation time 76677425 ps
CPU time 1.19 seconds
Started Jun 21 06:45:46 PM PDT 24
Finished Jun 21 06:46:08 PM PDT 24
Peak memory 216544 kb
Host smart-d1e3bd65-aef0-4ca8-a479-969be868902f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732711051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3732711051
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.926091735
Short name T832
Test name
Test status
Simulation time 24957011 ps
CPU time 1.13 seconds
Started Jun 21 06:42:50 PM PDT 24
Finished Jun 21 06:43:25 PM PDT 24
Peak memory 219292 kb
Host smart-66d47894-8727-4196-aa6e-d69c0f9dc531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926091735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.926091735
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1115265481
Short name T838
Test name
Test status
Simulation time 13647264 ps
CPU time 0.89 seconds
Started Jun 21 06:42:51 PM PDT 24
Finished Jun 21 06:43:26 PM PDT 24
Peak memory 214308 kb
Host smart-24d4fa9b-5911-4c9e-ad07-d653a6636f3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115265481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1115265481
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.344774683
Short name T102
Test name
Test status
Simulation time 36234128 ps
CPU time 1.18 seconds
Started Jun 21 06:42:51 PM PDT 24
Finished Jun 21 06:43:26 PM PDT 24
Peak memory 219264 kb
Host smart-722c458b-61e8-4e35-969f-56a1fd01a9b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344774683 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.344774683
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.747451854
Short name T109
Test name
Test status
Simulation time 27676726 ps
CPU time 1.01 seconds
Started Jun 21 06:42:50 PM PDT 24
Finished Jun 21 06:43:26 PM PDT 24
Peak memory 219068 kb
Host smart-cb460efc-ef01-4472-8167-e566c24a2589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747451854 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.747451854
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3005240743
Short name T302
Test name
Test status
Simulation time 89448350 ps
CPU time 2.14 seconds
Started Jun 21 06:42:50 PM PDT 24
Finished Jun 21 06:43:26 PM PDT 24
Peak memory 219352 kb
Host smart-44dbda9d-b082-46a2-a155-9bf96bdc17dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005240743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3005240743
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_smoke.2033631697
Short name T347
Test name
Test status
Simulation time 22485938 ps
CPU time 0.89 seconds
Started Jun 21 06:42:49 PM PDT 24
Finished Jun 21 06:43:25 PM PDT 24
Peak memory 214624 kb
Host smart-45ba9d92-82d0-4676-994c-bc976a4dcd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033631697 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2033631697
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.548885992
Short name T874
Test name
Test status
Simulation time 158726753 ps
CPU time 3.39 seconds
Started Jun 21 06:42:55 PM PDT 24
Finished Jun 21 06:43:32 PM PDT 24
Peak memory 216632 kb
Host smart-31275d7c-aecb-4445-9227-b57a32c26a8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548885992 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.548885992
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.4032870940
Short name T99
Test name
Test status
Simulation time 74385608156 ps
CPU time 1591.91 seconds
Started Jun 21 06:42:54 PM PDT 24
Finished Jun 21 07:10:00 PM PDT 24
Peak memory 223184 kb
Host smart-c8f61e16-0eb1-493b-bbd8-1e4e7775cb66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032870940 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.4032870940
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.719370706
Short name T592
Test name
Test status
Simulation time 78192364 ps
CPU time 1.69 seconds
Started Jun 21 06:45:48 PM PDT 24
Finished Jun 21 06:46:10 PM PDT 24
Peak memory 218088 kb
Host smart-c6a51caa-e569-4b67-95f4-8a7adc3eff33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719370706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.719370706
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2566446927
Short name T491
Test name
Test status
Simulation time 260350520 ps
CPU time 3.36 seconds
Started Jun 21 06:45:49 PM PDT 24
Finished Jun 21 06:46:12 PM PDT 24
Peak memory 219704 kb
Host smart-95844263-03b0-4dc3-833a-14d382830626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566446927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2566446927
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.740403635
Short name T586
Test name
Test status
Simulation time 60283873 ps
CPU time 1.64 seconds
Started Jun 21 06:45:46 PM PDT 24
Finished Jun 21 06:46:08 PM PDT 24
Peak memory 217964 kb
Host smart-5765014f-db94-4021-a043-721f5112865a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740403635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.740403635
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2087246188
Short name T935
Test name
Test status
Simulation time 31078550 ps
CPU time 1.07 seconds
Started Jun 21 06:45:47 PM PDT 24
Finished Jun 21 06:46:08 PM PDT 24
Peak memory 216732 kb
Host smart-ecf5d1c3-a402-45b4-9957-54018f3907cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087246188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2087246188
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3983865922
Short name T928
Test name
Test status
Simulation time 84025850 ps
CPU time 1.52 seconds
Started Jun 21 06:45:50 PM PDT 24
Finished Jun 21 06:46:11 PM PDT 24
Peak memory 218024 kb
Host smart-e454fcb2-1470-44eb-ac20-3f19feb048ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983865922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3983865922
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3920806768
Short name T570
Test name
Test status
Simulation time 68554443 ps
CPU time 1.26 seconds
Started Jun 21 06:45:47 PM PDT 24
Finished Jun 21 06:46:09 PM PDT 24
Peak memory 217952 kb
Host smart-24104540-7a1d-4bfb-a453-475ca8bb40c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920806768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3920806768
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2696096260
Short name T968
Test name
Test status
Simulation time 33513970 ps
CPU time 1.17 seconds
Started Jun 21 06:45:46 PM PDT 24
Finished Jun 21 06:46:08 PM PDT 24
Peak memory 219252 kb
Host smart-7f653f7f-0a0f-4e96-b8fb-f5d40cb0ada6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696096260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2696096260
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.378506777
Short name T761
Test name
Test status
Simulation time 46337478 ps
CPU time 1.78 seconds
Started Jun 21 06:45:49 PM PDT 24
Finished Jun 21 06:46:10 PM PDT 24
Peak memory 219244 kb
Host smart-009ab846-fab6-4f63-b24a-3c24f255fa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378506777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.378506777
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3303318074
Short name T989
Test name
Test status
Simulation time 50796033 ps
CPU time 1.64 seconds
Started Jun 21 06:45:50 PM PDT 24
Finished Jun 21 06:46:11 PM PDT 24
Peak memory 217780 kb
Host smart-e3f804b9-5e45-4ae7-bf7d-90f6cd087706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303318074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3303318074
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1836663067
Short name T433
Test name
Test status
Simulation time 69307136 ps
CPU time 1.05 seconds
Started Jun 21 06:45:48 PM PDT 24
Finished Jun 21 06:46:09 PM PDT 24
Peak memory 217848 kb
Host smart-4a57819e-f1e6-48ff-810f-562e9b3a4a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836663067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1836663067
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.754433637
Short name T164
Test name
Test status
Simulation time 38492666 ps
CPU time 1.18 seconds
Started Jun 21 06:41:12 PM PDT 24
Finished Jun 21 06:42:14 PM PDT 24
Peak memory 219256 kb
Host smart-5f66f9da-3753-4e60-b295-92f9191abdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754433637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.754433637
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2134682144
Short name T383
Test name
Test status
Simulation time 60966398 ps
CPU time 1.01 seconds
Started Jun 21 06:41:14 PM PDT 24
Finished Jun 21 06:42:20 PM PDT 24
Peak memory 214388 kb
Host smart-c2cb3cc3-10d8-4d5b-8384-9e67d846d9fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134682144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2134682144
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3247576727
Short name T501
Test name
Test status
Simulation time 14420238 ps
CPU time 0.9 seconds
Started Jun 21 06:41:11 PM PDT 24
Finished Jun 21 06:42:14 PM PDT 24
Peak memory 215832 kb
Host smart-d556c0bf-b40a-4b8b-875a-d75d6ca32e5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247576727 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3247576727
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.299564892
Short name T147
Test name
Test status
Simulation time 28775647 ps
CPU time 1.14 seconds
Started Jun 21 06:41:13 PM PDT 24
Finished Jun 21 06:42:19 PM PDT 24
Peak memory 216320 kb
Host smart-d89f3590-fc58-429b-83a3-d5f7dec8181e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299564892 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.299564892
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2210365877
Short name T158
Test name
Test status
Simulation time 20343893 ps
CPU time 1.12 seconds
Started Jun 21 06:41:11 PM PDT 24
Finished Jun 21 06:42:14 PM PDT 24
Peak memory 217800 kb
Host smart-7ddbcd91-fd92-484a-926d-243580aa0d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210365877 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2210365877
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1853637957
Short name T319
Test name
Test status
Simulation time 58836871 ps
CPU time 2.07 seconds
Started Jun 21 06:41:13 PM PDT 24
Finished Jun 21 06:42:20 PM PDT 24
Peak memory 219064 kb
Host smart-ba69da42-5e2a-4812-9746-4d574d17f776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853637957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1853637957
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2756014539
Short name T388
Test name
Test status
Simulation time 22593631 ps
CPU time 1.04 seconds
Started Jun 21 06:41:13 PM PDT 24
Finished Jun 21 06:42:20 PM PDT 24
Peak memory 214732 kb
Host smart-9d7323a5-9231-4e5e-9cd5-a57923486fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756014539 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2756014539
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.827406165
Short name T26
Test name
Test status
Simulation time 29107851 ps
CPU time 0.96 seconds
Started Jun 21 06:41:16 PM PDT 24
Finished Jun 21 06:42:20 PM PDT 24
Peak memory 206408 kb
Host smart-06cd88f1-ed46-4064-bbb3-9c8db132ffe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827406165 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.827406165
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.2886631672
Short name T57
Test name
Test status
Simulation time 891051807 ps
CPU time 4.84 seconds
Started Jun 21 06:41:13 PM PDT 24
Finished Jun 21 06:42:23 PM PDT 24
Peak memory 242340 kb
Host smart-7eac97ee-fb83-4384-8021-0b747e7afade
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886631672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2886631672
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2135879769
Short name T669
Test name
Test status
Simulation time 20901513 ps
CPU time 0.95 seconds
Started Jun 21 06:41:16 PM PDT 24
Finished Jun 21 06:42:20 PM PDT 24
Peak memory 214572 kb
Host smart-d3ccaf94-0191-49f9-8c9a-6ea884040f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135879769 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2135879769
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3725564849
Short name T416
Test name
Test status
Simulation time 947574244 ps
CPU time 2.68 seconds
Started Jun 21 06:41:12 PM PDT 24
Finished Jun 21 06:42:16 PM PDT 24
Peak memory 216652 kb
Host smart-e3351b61-e26f-43eb-8bb1-23c113f24a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725564849 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3725564849
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1818356994
Short name T870
Test name
Test status
Simulation time 71710760815 ps
CPU time 1042.38 seconds
Started Jun 21 06:41:11 PM PDT 24
Finished Jun 21 06:59:36 PM PDT 24
Peak memory 223016 kb
Host smart-72a071aa-cb29-4abe-845c-d6a16ebccae3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818356994 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1818356994
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1121172155
Short name T184
Test name
Test status
Simulation time 44830291 ps
CPU time 1.15 seconds
Started Jun 21 06:43:00 PM PDT 24
Finished Jun 21 06:43:34 PM PDT 24
Peak memory 218296 kb
Host smart-175e86bb-1aaa-4840-8190-e209ec2ad9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121172155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1121172155
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.4040975121
Short name T817
Test name
Test status
Simulation time 17292313 ps
CPU time 0.99 seconds
Started Jun 21 06:42:58 PM PDT 24
Finished Jun 21 06:43:32 PM PDT 24
Peak memory 206144 kb
Host smart-0828be54-9cc4-4350-94ef-be98945b60fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040975121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.4040975121
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1410690392
Short name T922
Test name
Test status
Simulation time 13001258 ps
CPU time 0.88 seconds
Started Jun 21 06:43:01 PM PDT 24
Finished Jun 21 06:43:33 PM PDT 24
Peak memory 215012 kb
Host smart-825e2f89-a61e-438a-b61c-c19bb91c8a55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410690392 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1410690392
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2084987637
Short name T782
Test name
Test status
Simulation time 53357612 ps
CPU time 1.31 seconds
Started Jun 21 06:42:59 PM PDT 24
Finished Jun 21 06:43:34 PM PDT 24
Peak memory 216420 kb
Host smart-06548501-c7a6-4d89-b7df-04e4a4831914
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084987637 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2084987637
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.4100140553
Short name T211
Test name
Test status
Simulation time 21833318 ps
CPU time 1.08 seconds
Started Jun 21 06:43:00 PM PDT 24
Finished Jun 21 06:43:33 PM PDT 24
Peak memory 217952 kb
Host smart-f1672cf9-a935-476c-a2f8-79199783402d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100140553 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.4100140553
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2930886213
Short name T63
Test name
Test status
Simulation time 42470256 ps
CPU time 1.48 seconds
Started Jun 21 06:42:56 PM PDT 24
Finished Jun 21 06:43:30 PM PDT 24
Peak memory 218972 kb
Host smart-9e72d07d-4829-47c0-ac2f-357b51a6c52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930886213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2930886213
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3886772482
Short name T576
Test name
Test status
Simulation time 45804940 ps
CPU time 0.89 seconds
Started Jun 21 06:42:51 PM PDT 24
Finished Jun 21 06:43:26 PM PDT 24
Peak memory 214588 kb
Host smart-5d44cb53-d470-4446-960a-1df87f3f0fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886772482 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3886772482
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1667913362
Short name T992
Test name
Test status
Simulation time 63566683 ps
CPU time 0.92 seconds
Started Jun 21 06:42:49 PM PDT 24
Finished Jun 21 06:43:25 PM PDT 24
Peak memory 214624 kb
Host smart-59ee35df-0a5e-4601-a380-c8be60a2e4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667913362 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1667913362
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1955698903
Short name T485
Test name
Test status
Simulation time 241263690 ps
CPU time 1.95 seconds
Started Jun 21 06:42:52 PM PDT 24
Finished Jun 21 06:43:27 PM PDT 24
Peak memory 214632 kb
Host smart-34c318f1-c58f-4c67-ba8e-3b32f2e0af69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955698903 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1955698903
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.119248617
Short name T483
Test name
Test status
Simulation time 378287627594 ps
CPU time 809.82 seconds
Started Jun 21 06:42:52 PM PDT 24
Finished Jun 21 06:56:55 PM PDT 24
Peak memory 233976 kb
Host smart-f8951ce1-a730-4052-a797-45b6b8eb22b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119248617 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.119248617
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2566293692
Short name T715
Test name
Test status
Simulation time 29812209 ps
CPU time 1.23 seconds
Started Jun 21 06:42:57 PM PDT 24
Finished Jun 21 06:43:32 PM PDT 24
Peak memory 219832 kb
Host smart-43ab4c90-e129-46a7-83f1-ac8582783b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566293692 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2566293692
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3829785934
Short name T464
Test name
Test status
Simulation time 43739207 ps
CPU time 0.97 seconds
Started Jun 21 06:43:00 PM PDT 24
Finished Jun 21 06:43:33 PM PDT 24
Peak memory 206116 kb
Host smart-c0b6a1f9-15f7-47dc-9541-7ac1bd4167b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829785934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3829785934
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.4278718971
Short name T811
Test name
Test status
Simulation time 21942034 ps
CPU time 0.84 seconds
Started Jun 21 06:42:59 PM PDT 24
Finished Jun 21 06:43:33 PM PDT 24
Peak memory 214836 kb
Host smart-220a3b13-d7f5-4766-80fc-7b7596816eb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278718971 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.4278718971
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2206464476
Short name T625
Test name
Test status
Simulation time 206048092 ps
CPU time 1.1 seconds
Started Jun 21 06:42:59 PM PDT 24
Finished Jun 21 06:43:32 PM PDT 24
Peak memory 217600 kb
Host smart-3b403c43-7ccc-4907-9bf3-bfcfed7cd332
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206464476 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2206464476
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1516613899
Short name T197
Test name
Test status
Simulation time 19849133 ps
CPU time 1.19 seconds
Started Jun 21 06:42:59 PM PDT 24
Finished Jun 21 06:43:32 PM PDT 24
Peak memory 228936 kb
Host smart-2b9fd05d-34ec-4483-9c9b-f84988eb64db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516613899 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1516613899
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1632332436
Short name T541
Test name
Test status
Simulation time 84687126 ps
CPU time 1.42 seconds
Started Jun 21 06:43:01 PM PDT 24
Finished Jun 21 06:43:34 PM PDT 24
Peak memory 218144 kb
Host smart-05a58ac9-9441-4c95-ac93-a365b7049ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632332436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1632332436
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.4272455292
Short name T424
Test name
Test status
Simulation time 95351025 ps
CPU time 0.96 seconds
Started Jun 21 06:43:00 PM PDT 24
Finished Jun 21 06:43:33 PM PDT 24
Peak memory 223184 kb
Host smart-41c9a4d0-4634-4997-9a31-14bf17614bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272455292 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.4272455292
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3372759930
Short name T794
Test name
Test status
Simulation time 28037481 ps
CPU time 0.98 seconds
Started Jun 21 06:42:59 PM PDT 24
Finished Jun 21 06:43:32 PM PDT 24
Peak memory 214596 kb
Host smart-0f4423e6-8978-4e42-869e-4f1e108bd1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372759930 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3372759930
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3057150198
Short name T452
Test name
Test status
Simulation time 182521482 ps
CPU time 3.87 seconds
Started Jun 21 06:42:58 PM PDT 24
Finished Jun 21 06:43:35 PM PDT 24
Peak memory 216568 kb
Host smart-7ccf1e12-d708-45ba-8d2b-892e30570acb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057150198 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3057150198
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1332178903
Short name T60
Test name
Test status
Simulation time 20965088448 ps
CPU time 401.11 seconds
Started Jun 21 06:42:58 PM PDT 24
Finished Jun 21 06:50:12 PM PDT 24
Peak memory 222872 kb
Host smart-b9986feb-f8ba-43c7-ae58-3a11e8a470db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332178903 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1332178903
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1915855288
Short name T496
Test name
Test status
Simulation time 131454283 ps
CPU time 1.3 seconds
Started Jun 21 06:42:59 PM PDT 24
Finished Jun 21 06:43:34 PM PDT 24
Peak memory 218376 kb
Host smart-6f779830-398a-482f-bc53-08218e64291a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915855288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1915855288
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1560645583
Short name T528
Test name
Test status
Simulation time 17338103 ps
CPU time 0.96 seconds
Started Jun 21 06:43:10 PM PDT 24
Finished Jun 21 06:43:43 PM PDT 24
Peak memory 206092 kb
Host smart-4b82223d-5bb4-40fd-9bb9-e6b509de7a03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560645583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1560645583
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.4246562352
Short name T217
Test name
Test status
Simulation time 37032854 ps
CPU time 0.87 seconds
Started Jun 21 06:43:00 PM PDT 24
Finished Jun 21 06:43:33 PM PDT 24
Peak memory 215684 kb
Host smart-7a9933e8-4be8-4924-ab40-06f8b8509b64
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246562352 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.4246562352
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.169513979
Short name T131
Test name
Test status
Simulation time 122857709 ps
CPU time 1.22 seconds
Started Jun 21 06:43:10 PM PDT 24
Finished Jun 21 06:43:43 PM PDT 24
Peak memory 218576 kb
Host smart-b14bec01-ce85-47d8-a401-cd3c95038b4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169513979 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.169513979
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2467128955
Short name T186
Test name
Test status
Simulation time 44930296 ps
CPU time 0.89 seconds
Started Jun 21 06:42:59 PM PDT 24
Finished Jun 21 06:43:32 PM PDT 24
Peak memory 217612 kb
Host smart-5c7f8e3e-3fdf-4fbe-8196-d2af2d07991f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467128955 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2467128955
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.4022747642
Short name T638
Test name
Test status
Simulation time 45584440 ps
CPU time 1.53 seconds
Started Jun 21 06:43:00 PM PDT 24
Finished Jun 21 06:43:34 PM PDT 24
Peak memory 217920 kb
Host smart-bf853620-063c-49d6-a3c9-d8cdd91af621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022747642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.4022747642
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1060185672
Short name T856
Test name
Test status
Simulation time 40536103 ps
CPU time 0.87 seconds
Started Jun 21 06:43:00 PM PDT 24
Finished Jun 21 06:43:33 PM PDT 24
Peak memory 214584 kb
Host smart-9356c6b6-0373-4d6f-9c71-5f594619157b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060185672 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1060185672
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3412935459
Short name T329
Test name
Test status
Simulation time 23440027 ps
CPU time 0.94 seconds
Started Jun 21 06:43:00 PM PDT 24
Finished Jun 21 06:43:33 PM PDT 24
Peak memory 214616 kb
Host smart-21ec6341-ad03-4863-986b-542764e302e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412935459 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3412935459
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1086110559
Short name T480
Test name
Test status
Simulation time 76751302 ps
CPU time 1.12 seconds
Started Jun 21 06:42:58 PM PDT 24
Finished Jun 21 06:43:32 PM PDT 24
Peak memory 206240 kb
Host smart-c659cd00-f1bf-4075-9025-5c41244bc3af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086110559 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1086110559
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1552448420
Short name T467
Test name
Test status
Simulation time 101340848862 ps
CPU time 895.07 seconds
Started Jun 21 06:42:59 PM PDT 24
Finished Jun 21 06:58:26 PM PDT 24
Peak memory 221380 kb
Host smart-6dddbf90-3daa-4c4f-9de5-c1ec965dc57d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552448420 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1552448420
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.482742173
Short name T138
Test name
Test status
Simulation time 80115943 ps
CPU time 1.14 seconds
Started Jun 21 06:43:12 PM PDT 24
Finished Jun 21 06:43:44 PM PDT 24
Peak memory 220036 kb
Host smart-962306f5-7626-4a2d-be3c-3834eda2c399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482742173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.482742173
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3562162665
Short name T821
Test name
Test status
Simulation time 17634646 ps
CPU time 0.96 seconds
Started Jun 21 06:43:10 PM PDT 24
Finished Jun 21 06:43:43 PM PDT 24
Peak memory 206080 kb
Host smart-bdf1cfd4-1809-465a-96d0-1c6aff03aac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562162665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3562162665
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2721886875
Short name T967
Test name
Test status
Simulation time 16077971 ps
CPU time 0.88 seconds
Started Jun 21 06:43:08 PM PDT 24
Finished Jun 21 06:43:42 PM PDT 24
Peak memory 215620 kb
Host smart-244ef465-d968-4d6e-ad6d-0e84479f9f27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721886875 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2721886875
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2669964769
Short name T745
Test name
Test status
Simulation time 26832286 ps
CPU time 1.1 seconds
Started Jun 21 06:43:10 PM PDT 24
Finished Jun 21 06:43:43 PM PDT 24
Peak memory 217328 kb
Host smart-51afd6c0-9af8-4c83-a813-d2e9f7f373f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669964769 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2669964769
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_genbits.546167081
Short name T37
Test name
Test status
Simulation time 24621861 ps
CPU time 1.16 seconds
Started Jun 21 06:43:08 PM PDT 24
Finished Jun 21 06:43:42 PM PDT 24
Peak memory 217772 kb
Host smart-95024874-d0ca-4de0-b14e-c4a8ec56d492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546167081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.546167081
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.805794388
Short name T678
Test name
Test status
Simulation time 23794442 ps
CPU time 0.99 seconds
Started Jun 21 06:43:09 PM PDT 24
Finished Jun 21 06:43:43 PM PDT 24
Peak memory 215136 kb
Host smart-d3ef1b78-0d29-4b22-ac27-5f26c1b64035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805794388 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.805794388
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.915841474
Short name T61
Test name
Test status
Simulation time 41255574 ps
CPU time 0.93 seconds
Started Jun 21 06:43:10 PM PDT 24
Finished Jun 21 06:43:43 PM PDT 24
Peak memory 214636 kb
Host smart-cf5f7cb0-6a85-4ea9-baa9-acf49161afb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915841474 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.915841474
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.4097226763
Short name T204
Test name
Test status
Simulation time 127475265 ps
CPU time 3.01 seconds
Started Jun 21 06:43:09 PM PDT 24
Finished Jun 21 06:43:45 PM PDT 24
Peak memory 216664 kb
Host smart-d2f59a38-cd9f-49d4-8d13-74f72696ce22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097226763 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.4097226763
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.46875324
Short name T316
Test name
Test status
Simulation time 39024405878 ps
CPU time 962.28 seconds
Started Jun 21 06:43:10 PM PDT 24
Finished Jun 21 06:59:44 PM PDT 24
Peak memory 222912 kb
Host smart-1887ac30-36a3-427f-8790-7e5d33e9337e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46875324 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.46875324
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.4153723285
Short name T482
Test name
Test status
Simulation time 38153580 ps
CPU time 1.07 seconds
Started Jun 21 06:43:10 PM PDT 24
Finished Jun 21 06:43:43 PM PDT 24
Peak memory 220060 kb
Host smart-c6aecb80-d0e6-4be1-812e-ea04a9e04d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153723285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.4153723285
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2554421156
Short name T341
Test name
Test status
Simulation time 13907268 ps
CPU time 0.86 seconds
Started Jun 21 06:43:18 PM PDT 24
Finished Jun 21 06:43:51 PM PDT 24
Peak memory 206420 kb
Host smart-6d187a5a-810a-4713-bf9a-415bc447fe87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554421156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2554421156
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3755842518
Short name T805
Test name
Test status
Simulation time 16256776 ps
CPU time 0.85 seconds
Started Jun 21 06:43:14 PM PDT 24
Finished Jun 21 06:43:46 PM PDT 24
Peak memory 214836 kb
Host smart-d1d9601b-fa51-474c-a9d7-2ba1d0ecf507
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755842518 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3755842518
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3115073392
Short name T207
Test name
Test status
Simulation time 76142548 ps
CPU time 1.08 seconds
Started Jun 21 06:43:10 PM PDT 24
Finished Jun 21 06:43:43 PM PDT 24
Peak memory 216260 kb
Host smart-00af60cc-63e9-426a-9d9d-a5d5e39b2e0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115073392 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3115073392
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2756209394
Short name T671
Test name
Test status
Simulation time 165493670 ps
CPU time 1.15 seconds
Started Jun 21 06:43:14 PM PDT 24
Finished Jun 21 06:43:47 PM PDT 24
Peak memory 219180 kb
Host smart-617973f3-e0d6-4d90-ab0c-50660366c81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756209394 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2756209394
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3797954236
Short name T360
Test name
Test status
Simulation time 50374300 ps
CPU time 1.22 seconds
Started Jun 21 06:43:10 PM PDT 24
Finished Jun 21 06:43:43 PM PDT 24
Peak memory 218168 kb
Host smart-bf5ef433-a016-4ea7-8d51-9f2790d19ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797954236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3797954236
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.4001569900
Short name T98
Test name
Test status
Simulation time 25144662 ps
CPU time 0.97 seconds
Started Jun 21 06:43:13 PM PDT 24
Finished Jun 21 06:43:44 PM PDT 24
Peak memory 215092 kb
Host smart-26867d6b-6b10-49dc-aafe-f8aa80347c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001569900 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.4001569900
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.591378889
Short name T414
Test name
Test status
Simulation time 17783264 ps
CPU time 1.02 seconds
Started Jun 21 06:43:12 PM PDT 24
Finished Jun 21 06:43:44 PM PDT 24
Peak memory 214588 kb
Host smart-0b0ff43e-3734-4502-91f2-3f83008d5dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591378889 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.591378889
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3883781859
Short name T747
Test name
Test status
Simulation time 126758327 ps
CPU time 1.6 seconds
Started Jun 21 06:43:10 PM PDT 24
Finished Jun 21 06:43:43 PM PDT 24
Peak memory 216620 kb
Host smart-ecfedf6f-041f-4baf-a57f-6c880c60dcff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883781859 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3883781859
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3201059377
Short name T228
Test name
Test status
Simulation time 504419185494 ps
CPU time 1982.53 seconds
Started Jun 21 06:43:12 PM PDT 24
Finished Jun 21 07:16:46 PM PDT 24
Peak memory 228312 kb
Host smart-95f98c30-ad69-4051-b4e0-93bdbbdad358
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201059377 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3201059377
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1721419595
Short name T994
Test name
Test status
Simulation time 25284910 ps
CPU time 1.17 seconds
Started Jun 21 06:43:21 PM PDT 24
Finished Jun 21 06:43:53 PM PDT 24
Peak memory 218076 kb
Host smart-503e54a1-7f92-4a1a-ae27-224a7abd46fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721419595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1721419595
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1731539179
Short name T544
Test name
Test status
Simulation time 56618419 ps
CPU time 0.82 seconds
Started Jun 21 06:43:20 PM PDT 24
Finished Jun 21 06:43:51 PM PDT 24
Peak memory 205868 kb
Host smart-68c584d2-89ea-43be-88b7-f69b6068472a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731539179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1731539179
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.537412559
Short name T216
Test name
Test status
Simulation time 13489480 ps
CPU time 0.91 seconds
Started Jun 21 06:43:19 PM PDT 24
Finished Jun 21 06:43:51 PM PDT 24
Peak memory 215820 kb
Host smart-7c14a596-08ce-4cef-9ebd-a8be95c07f20
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537412559 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.537412559
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2960229156
Short name T555
Test name
Test status
Simulation time 386999867 ps
CPU time 1.11 seconds
Started Jun 21 06:43:17 PM PDT 24
Finished Jun 21 06:43:50 PM PDT 24
Peak memory 219040 kb
Host smart-4a1de20b-6c41-4d73-b886-7d84bbe84f70
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960229156 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2960229156
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2298137883
Short name T674
Test name
Test status
Simulation time 24996594 ps
CPU time 0.88 seconds
Started Jun 21 06:43:18 PM PDT 24
Finished Jun 21 06:43:51 PM PDT 24
Peak memory 217804 kb
Host smart-be8fa044-7463-4a93-971a-2d57d0dd3780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298137883 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2298137883
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3852930526
Short name T963
Test name
Test status
Simulation time 114603211 ps
CPU time 1.4 seconds
Started Jun 21 06:43:19 PM PDT 24
Finished Jun 21 06:43:52 PM PDT 24
Peak memory 214700 kb
Host smart-b890d011-e52b-4e02-a4b3-3dc17d7d5863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852930526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3852930526
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1457852235
Short name T4
Test name
Test status
Simulation time 31549786 ps
CPU time 0.87 seconds
Started Jun 21 06:43:20 PM PDT 24
Finished Jun 21 06:43:51 PM PDT 24
Peak memory 215004 kb
Host smart-387e2ab3-4b66-46ee-a8f4-8cbacc8e90c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457852235 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1457852235
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.4250811066
Short name T432
Test name
Test status
Simulation time 25408295 ps
CPU time 0.96 seconds
Started Jun 21 06:43:21 PM PDT 24
Finished Jun 21 06:43:53 PM PDT 24
Peak memory 214592 kb
Host smart-4d9b4211-11d3-4c01-a344-7b8c52550bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250811066 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.4250811066
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.630816292
Short name T614
Test name
Test status
Simulation time 490942459 ps
CPU time 4.01 seconds
Started Jun 21 06:43:20 PM PDT 24
Finished Jun 21 06:43:54 PM PDT 24
Peak memory 216520 kb
Host smart-0235db17-2a62-48f4-96b5-c564f2584b4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630816292 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.630816292
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3075857821
Short name T917
Test name
Test status
Simulation time 52036205378 ps
CPU time 356.01 seconds
Started Jun 21 06:43:19 PM PDT 24
Finished Jun 21 06:49:46 PM PDT 24
Peak memory 216676 kb
Host smart-14806b37-c25c-490a-a125-602d9efb4052
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075857821 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3075857821
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3934238370
Short name T819
Test name
Test status
Simulation time 116712466 ps
CPU time 1.2 seconds
Started Jun 21 06:43:21 PM PDT 24
Finished Jun 21 06:43:53 PM PDT 24
Peak memory 218000 kb
Host smart-994c410d-ecd4-46ad-973e-fc94d0886e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934238370 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3934238370
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1207912093
Short name T352
Test name
Test status
Simulation time 27686428 ps
CPU time 0.9 seconds
Started Jun 21 06:43:17 PM PDT 24
Finished Jun 21 06:43:49 PM PDT 24
Peak memory 206048 kb
Host smart-8ddbc27c-5e70-4385-85b0-917470d9295d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207912093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1207912093
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2814584922
Short name T224
Test name
Test status
Simulation time 15255646 ps
CPU time 0.9 seconds
Started Jun 21 06:43:20 PM PDT 24
Finished Jun 21 06:43:51 PM PDT 24
Peak memory 215836 kb
Host smart-1faf1aee-f9cd-4a6e-a1bc-3bcb637455ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814584922 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2814584922
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.4139719088
Short name T125
Test name
Test status
Simulation time 32255271 ps
CPU time 1.22 seconds
Started Jun 21 06:43:18 PM PDT 24
Finished Jun 21 06:43:51 PM PDT 24
Peak memory 216212 kb
Host smart-92bfe7fc-d7c1-4b4e-a4b4-61f313e454ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139719088 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.4139719088
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1111982794
Short name T976
Test name
Test status
Simulation time 42991032 ps
CPU time 0.97 seconds
Started Jun 21 06:43:19 PM PDT 24
Finished Jun 21 06:43:51 PM PDT 24
Peak memory 223216 kb
Host smart-bf7f5571-5512-47e8-816c-a4799c6d0d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111982794 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1111982794
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2055940313
Short name T486
Test name
Test status
Simulation time 61015615 ps
CPU time 1.07 seconds
Started Jun 21 06:43:20 PM PDT 24
Finished Jun 21 06:43:52 PM PDT 24
Peak memory 219012 kb
Host smart-e04510b1-9d05-492a-a17d-69be27c5ca24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055940313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2055940313
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2124255787
Short name T95
Test name
Test status
Simulation time 24317054 ps
CPU time 1.01 seconds
Started Jun 21 06:43:18 PM PDT 24
Finished Jun 21 06:43:51 PM PDT 24
Peak memory 215076 kb
Host smart-285607d2-e3a7-4e31-a9d6-c123a5e83d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124255787 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2124255787
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1515363673
Short name T373
Test name
Test status
Simulation time 17236209 ps
CPU time 1 seconds
Started Jun 21 06:43:19 PM PDT 24
Finished Jun 21 06:43:51 PM PDT 24
Peak memory 214716 kb
Host smart-0450a32d-c7b0-4c5d-8fad-1c0ed1257ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515363673 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1515363673
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2524896370
Short name T493
Test name
Test status
Simulation time 510761306 ps
CPU time 5.41 seconds
Started Jun 21 06:43:20 PM PDT 24
Finished Jun 21 06:43:56 PM PDT 24
Peak memory 214640 kb
Host smart-15acaee2-9139-4f20-b2d5-22ac6cde54bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524896370 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2524896370
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2677600553
Short name T230
Test name
Test status
Simulation time 46212707176 ps
CPU time 512.96 seconds
Started Jun 21 06:43:21 PM PDT 24
Finished Jun 21 06:52:25 PM PDT 24
Peak memory 217168 kb
Host smart-54075f8d-abb8-4d06-b9d5-53b9ea438204
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677600553 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2677600553
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2270302430
Short name T938
Test name
Test status
Simulation time 30331900 ps
CPU time 1.31 seconds
Started Jun 21 06:43:18 PM PDT 24
Finished Jun 21 06:43:51 PM PDT 24
Peak memory 219308 kb
Host smart-7e6f872f-9ec0-4001-929a-7285981a3769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270302430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2270302430
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3291958249
Short name T609
Test name
Test status
Simulation time 36823881 ps
CPU time 1.02 seconds
Started Jun 21 06:43:21 PM PDT 24
Finished Jun 21 06:43:53 PM PDT 24
Peak memory 214320 kb
Host smart-8f5315f5-5e09-4779-84a5-0fa68281b327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291958249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3291958249
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3243153483
Short name T769
Test name
Test status
Simulation time 32988902 ps
CPU time 0.85 seconds
Started Jun 21 06:43:21 PM PDT 24
Finished Jun 21 06:43:53 PM PDT 24
Peak memory 215632 kb
Host smart-3d10d108-72a6-4637-bd00-492998166b71
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243153483 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3243153483
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3033708443
Short name T644
Test name
Test status
Simulation time 110476914 ps
CPU time 1.13 seconds
Started Jun 21 06:43:20 PM PDT 24
Finished Jun 21 06:43:52 PM PDT 24
Peak memory 217624 kb
Host smart-bafe52a7-a0d3-4394-8a5e-39e5b184748d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033708443 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3033708443
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.438589731
Short name T181
Test name
Test status
Simulation time 24352189 ps
CPU time 0.98 seconds
Started Jun 21 06:43:20 PM PDT 24
Finished Jun 21 06:43:51 PM PDT 24
Peak memory 217932 kb
Host smart-29dd402a-0b8c-44fc-8f4c-c8f47552d460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438589731 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.438589731
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2850456627
Short name T951
Test name
Test status
Simulation time 78761304 ps
CPU time 1.14 seconds
Started Jun 21 06:43:21 PM PDT 24
Finished Jun 21 06:43:53 PM PDT 24
Peak memory 216704 kb
Host smart-ba5c8f8d-957b-4887-b088-29c22db56615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850456627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2850456627
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2657184068
Short name T584
Test name
Test status
Simulation time 23999021 ps
CPU time 1.17 seconds
Started Jun 21 06:43:19 PM PDT 24
Finished Jun 21 06:43:51 PM PDT 24
Peak memory 214984 kb
Host smart-aa781423-8bcf-4503-9a1e-3492393e6945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657184068 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2657184068
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2124542890
Short name T723
Test name
Test status
Simulation time 135531585 ps
CPU time 0.91 seconds
Started Jun 21 06:43:18 PM PDT 24
Finished Jun 21 06:43:51 PM PDT 24
Peak memory 214484 kb
Host smart-b19f4264-95f3-4c78-8ba6-4f9ef402bf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124542890 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2124542890
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.928787399
Short name T235
Test name
Test status
Simulation time 234181729 ps
CPU time 4.36 seconds
Started Jun 21 06:43:20 PM PDT 24
Finished Jun 21 06:43:55 PM PDT 24
Peak memory 219108 kb
Host smart-c9289cc6-7b06-4682-9640-1f3daf7934ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928787399 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.928787399
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2211778158
Short name T890
Test name
Test status
Simulation time 517257533107 ps
CPU time 1223.63 seconds
Started Jun 21 06:43:21 PM PDT 24
Finished Jun 21 07:04:16 PM PDT 24
Peak memory 224240 kb
Host smart-7f601a66-a633-41fe-bf33-b94d86270b57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211778158 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2211778158
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3158076157
Short name T824
Test name
Test status
Simulation time 90023902 ps
CPU time 1.18 seconds
Started Jun 21 06:43:19 PM PDT 24
Finished Jun 21 06:43:52 PM PDT 24
Peak memory 218284 kb
Host smart-94e25a2f-0229-4867-b3a0-b23b82023004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158076157 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3158076157
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2000424341
Short name T578
Test name
Test status
Simulation time 28836953 ps
CPU time 0.95 seconds
Started Jun 21 06:43:34 PM PDT 24
Finished Jun 21 06:44:05 PM PDT 24
Peak memory 214528 kb
Host smart-11b87e8b-5664-4fb0-a803-de4da51b6690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000424341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2000424341
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3955653349
Short name T912
Test name
Test status
Simulation time 41279899 ps
CPU time 0.9 seconds
Started Jun 21 06:43:28 PM PDT 24
Finished Jun 21 06:44:00 PM PDT 24
Peak memory 214836 kb
Host smart-35f02f94-857a-472c-9f90-aef41945abba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955653349 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3955653349
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3770005104
Short name T87
Test name
Test status
Simulation time 179242699 ps
CPU time 1.29 seconds
Started Jun 21 06:43:29 PM PDT 24
Finished Jun 21 06:44:00 PM PDT 24
Peak memory 216300 kb
Host smart-7219988a-8b21-4544-ad31-c16a3ddd6931
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770005104 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3770005104
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3910089786
Short name T661
Test name
Test status
Simulation time 28448919 ps
CPU time 0.94 seconds
Started Jun 21 06:43:30 PM PDT 24
Finished Jun 21 06:44:02 PM PDT 24
Peak memory 217860 kb
Host smart-5cd59fc7-3497-4033-b2bc-3ae111fc9c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910089786 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3910089786
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3581536864
Short name T787
Test name
Test status
Simulation time 203260083 ps
CPU time 1.98 seconds
Started Jun 21 06:43:17 PM PDT 24
Finished Jun 21 06:43:50 PM PDT 24
Peak memory 219712 kb
Host smart-7ee80761-2511-4b40-a57b-6ae26e7f7662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581536864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3581536864
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3391451240
Short name T740
Test name
Test status
Simulation time 25696246 ps
CPU time 0.94 seconds
Started Jun 21 06:43:18 PM PDT 24
Finished Jun 21 06:43:51 PM PDT 24
Peak memory 215044 kb
Host smart-9df5b22c-0e4f-4694-8ca4-c90d48db7e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391451240 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3391451240
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.609785792
Short name T513
Test name
Test status
Simulation time 41894070 ps
CPU time 0.93 seconds
Started Jun 21 06:43:22 PM PDT 24
Finished Jun 21 06:43:53 PM PDT 24
Peak memory 214600 kb
Host smart-ecc26794-24d4-4fe6-8e65-a221597b2a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609785792 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.609785792
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2346481385
Short name T777
Test name
Test status
Simulation time 418120850 ps
CPU time 4.29 seconds
Started Jun 21 06:43:19 PM PDT 24
Finished Jun 21 06:43:55 PM PDT 24
Peak memory 214644 kb
Host smart-6c153798-6091-4d5d-abcd-c30e4b50f6fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346481385 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2346481385
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1144466560
Short name T533
Test name
Test status
Simulation time 76122252107 ps
CPU time 453.78 seconds
Started Jun 21 06:43:18 PM PDT 24
Finished Jun 21 06:51:24 PM PDT 24
Peak memory 217624 kb
Host smart-8d57fd34-34f9-4b76-9aca-118cbf37911f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144466560 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1144466560
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1389524317
Short name T179
Test name
Test status
Simulation time 37816305 ps
CPU time 1.14 seconds
Started Jun 21 06:43:27 PM PDT 24
Finished Jun 21 06:43:58 PM PDT 24
Peak memory 219148 kb
Host smart-0c4cb330-6adb-43f7-a646-cdc12e0d6a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389524317 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1389524317
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3101809245
Short name T952
Test name
Test status
Simulation time 13353275 ps
CPU time 0.9 seconds
Started Jun 21 06:43:34 PM PDT 24
Finished Jun 21 06:44:05 PM PDT 24
Peak memory 206408 kb
Host smart-6004a35e-da58-47d9-a7a9-802b202a6562
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101809245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3101809245
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.319632457
Short name T816
Test name
Test status
Simulation time 26558522 ps
CPU time 0.9 seconds
Started Jun 21 06:43:30 PM PDT 24
Finished Jun 21 06:44:02 PM PDT 24
Peak memory 215680 kb
Host smart-94f09fd7-df97-4941-b33c-c11c350a317c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319632457 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.319632457
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.470928258
Short name T394
Test name
Test status
Simulation time 44058540 ps
CPU time 1.38 seconds
Started Jun 21 06:43:30 PM PDT 24
Finished Jun 21 06:44:01 PM PDT 24
Peak memory 216320 kb
Host smart-0d3354ec-799a-4e37-b3e9-84e8b105bf98
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470928258 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.470928258
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.554685237
Short name T54
Test name
Test status
Simulation time 35697296 ps
CPU time 1.04 seconds
Started Jun 21 06:43:29 PM PDT 24
Finished Jun 21 06:44:00 PM PDT 24
Peak memory 229024 kb
Host smart-082a1002-6e4a-49db-8f1a-536d29cce574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554685237 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.554685237
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3967380376
Short name T694
Test name
Test status
Simulation time 44046833 ps
CPU time 1.6 seconds
Started Jun 21 06:43:29 PM PDT 24
Finished Jun 21 06:44:01 PM PDT 24
Peak memory 218500 kb
Host smart-042f93ac-d8ef-4fe7-9b66-3ed14d2e35cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967380376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3967380376
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3085788953
Short name T741
Test name
Test status
Simulation time 48591851 ps
CPU time 0.89 seconds
Started Jun 21 06:43:27 PM PDT 24
Finished Jun 21 06:43:58 PM PDT 24
Peak memory 214832 kb
Host smart-2601c145-44a9-4e92-9308-cf42778e802c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085788953 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3085788953
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.375249200
Short name T377
Test name
Test status
Simulation time 23970550 ps
CPU time 0.99 seconds
Started Jun 21 06:43:30 PM PDT 24
Finished Jun 21 06:44:02 PM PDT 24
Peak memory 214644 kb
Host smart-b76cdbd3-bf9b-4ad7-8d09-1680aaba05e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375249200 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.375249200
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.89869968
Short name T607
Test name
Test status
Simulation time 2099481429 ps
CPU time 6.06 seconds
Started Jun 21 06:43:30 PM PDT 24
Finished Jun 21 06:44:05 PM PDT 24
Peak memory 216516 kb
Host smart-b3435cd7-ca4c-4986-a2a2-cc5c54063f25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89869968 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.89869968
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1779479012
Short name T436
Test name
Test status
Simulation time 306884354908 ps
CPU time 881.76 seconds
Started Jun 21 06:43:28 PM PDT 24
Finished Jun 21 06:58:41 PM PDT 24
Peak memory 231112 kb
Host smart-76e71ea2-8309-40bc-96ed-c1ac49b0df83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779479012 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1779479012
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3324011343
Short name T915
Test name
Test status
Simulation time 27356102 ps
CPU time 1.23 seconds
Started Jun 21 06:41:20 PM PDT 24
Finished Jun 21 06:42:26 PM PDT 24
Peak memory 217892 kb
Host smart-b7b043d3-5092-4162-9391-6a84032db831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324011343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3324011343
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1995931694
Short name T869
Test name
Test status
Simulation time 57473843 ps
CPU time 0.94 seconds
Started Jun 21 06:41:20 PM PDT 24
Finished Jun 21 06:42:26 PM PDT 24
Peak memory 214612 kb
Host smart-22d1e07a-4813-4b13-9bc5-ca8b11546879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995931694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1995931694
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.541396856
Short name T820
Test name
Test status
Simulation time 28178805 ps
CPU time 0.88 seconds
Started Jun 21 06:41:23 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 215800 kb
Host smart-243e2ffe-985e-44f8-b499-4bd4d053d8b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541396856 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.541396856
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.693160993
Short name T539
Test name
Test status
Simulation time 112481830 ps
CPU time 1.07 seconds
Started Jun 21 06:41:21 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 216244 kb
Host smart-d1ad8e0f-f46c-4612-91ab-3a57b1d28061
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693160993 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.693160993
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.980010889
Short name T907
Test name
Test status
Simulation time 26156105 ps
CPU time 1.04 seconds
Started Jun 21 06:41:19 PM PDT 24
Finished Jun 21 06:42:26 PM PDT 24
Peak memory 223388 kb
Host smart-2f3e1b41-8683-4682-bdc9-ff11dc02bcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980010889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.980010889
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2732414161
Short name T412
Test name
Test status
Simulation time 41964888 ps
CPU time 1.47 seconds
Started Jun 21 06:41:16 PM PDT 24
Finished Jun 21 06:42:25 PM PDT 24
Peak memory 217932 kb
Host smart-0650a0a3-a13a-47f7-bbe8-87f2dc2e92ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732414161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2732414161
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_regwen.1615135432
Short name T25
Test name
Test status
Simulation time 45008462 ps
CPU time 0.97 seconds
Started Jun 21 06:41:13 PM PDT 24
Finished Jun 21 06:42:14 PM PDT 24
Peak memory 206416 kb
Host smart-ab185c8a-fd96-41eb-b391-bd1f0f81d7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615135432 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1615135432
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3192634926
Short name T16
Test name
Test status
Simulation time 896612292 ps
CPU time 4.15 seconds
Started Jun 21 06:41:20 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 235052 kb
Host smart-aee43334-621d-46dd-a8c1-a57c2de23842
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192634926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3192634926
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3736569995
Short name T611
Test name
Test status
Simulation time 50868743 ps
CPU time 0.93 seconds
Started Jun 21 06:41:10 PM PDT 24
Finished Jun 21 06:42:14 PM PDT 24
Peak memory 214636 kb
Host smart-fec1d3c8-a6d0-4ec0-8dbf-3d9f2bfaedb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736569995 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3736569995
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1057772570
Short name T442
Test name
Test status
Simulation time 2393399949 ps
CPU time 4.87 seconds
Started Jun 21 06:41:17 PM PDT 24
Finished Jun 21 06:42:30 PM PDT 24
Peak memory 214708 kb
Host smart-6d330ba9-cff5-4c51-abd7-3be1f946575d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057772570 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1057772570
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2387054599
Short name T549
Test name
Test status
Simulation time 509738463262 ps
CPU time 2701.58 seconds
Started Jun 21 06:41:20 PM PDT 24
Finished Jun 21 07:27:27 PM PDT 24
Peak memory 229584 kb
Host smart-73b6e936-cbf0-4ed6-aa8f-ab745df41b33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387054599 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2387054599
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.782469585
Short name T504
Test name
Test status
Simulation time 146237449 ps
CPU time 1.2 seconds
Started Jun 21 06:43:27 PM PDT 24
Finished Jun 21 06:43:58 PM PDT 24
Peak memory 215100 kb
Host smart-9c39f5b4-eaea-4425-804c-8c9c92607e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782469585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.782469585
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3918531287
Short name T932
Test name
Test status
Simulation time 12463168 ps
CPU time 0.86 seconds
Started Jun 21 06:43:30 PM PDT 24
Finished Jun 21 06:44:02 PM PDT 24
Peak memory 206120 kb
Host smart-6de8ad41-afc6-4f89-903f-ca98b0eb9cdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918531287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3918531287
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.214338383
Short name T873
Test name
Test status
Simulation time 20886914 ps
CPU time 0.9 seconds
Started Jun 21 06:43:31 PM PDT 24
Finished Jun 21 06:44:02 PM PDT 24
Peak memory 215816 kb
Host smart-2a04365c-64ed-44d2-9e7f-88bd37bb27ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214338383 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.214338383
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_err.682171227
Short name T749
Test name
Test status
Simulation time 26659134 ps
CPU time 0.91 seconds
Started Jun 21 06:43:31 PM PDT 24
Finished Jun 21 06:44:02 PM PDT 24
Peak memory 217740 kb
Host smart-00347e1f-a828-4ba6-85c7-21d273fd0883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682171227 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.682171227
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2278484345
Short name T683
Test name
Test status
Simulation time 40582673 ps
CPU time 1.5 seconds
Started Jun 21 06:43:28 PM PDT 24
Finished Jun 21 06:43:59 PM PDT 24
Peak memory 217784 kb
Host smart-ed3afdbe-3567-4cf5-9167-23aea67b39e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278484345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2278484345
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3133855973
Short name T337
Test name
Test status
Simulation time 28064640 ps
CPU time 0.94 seconds
Started Jun 21 06:43:34 PM PDT 24
Finished Jun 21 06:44:05 PM PDT 24
Peak memory 214700 kb
Host smart-61ca0f4f-f9c5-40b2-865e-c25fd7ab7757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133855973 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3133855973
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3564745157
Short name T732
Test name
Test status
Simulation time 47155263 ps
CPU time 0.9 seconds
Started Jun 21 06:43:28 PM PDT 24
Finished Jun 21 06:44:00 PM PDT 24
Peak memory 206440 kb
Host smart-f3072a28-77b7-432f-94b2-acdee5f29480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564745157 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3564745157
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3856516907
Short name T748
Test name
Test status
Simulation time 120683971 ps
CPU time 1.83 seconds
Started Jun 21 06:43:29 PM PDT 24
Finished Jun 21 06:44:01 PM PDT 24
Peak memory 214588 kb
Host smart-cfb46fc4-6c95-45e3-b517-aaa76d14dec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856516907 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3856516907
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3514883791
Short name T59
Test name
Test status
Simulation time 124853632324 ps
CPU time 829.51 seconds
Started Jun 21 06:43:43 PM PDT 24
Finished Jun 21 06:58:02 PM PDT 24
Peak memory 222184 kb
Host smart-92ac0f91-0ceb-4460-9eea-c83c27cae1eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514883791 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3514883791
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1166149365
Short name T753
Test name
Test status
Simulation time 52081323 ps
CPU time 1.1 seconds
Started Jun 21 06:43:28 PM PDT 24
Finished Jun 21 06:44:00 PM PDT 24
Peak memory 218996 kb
Host smart-79c43509-723e-48f2-96f7-c713bf11888f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166149365 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1166149365
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.4023184228
Short name T107
Test name
Test status
Simulation time 35336750 ps
CPU time 0.82 seconds
Started Jun 21 06:43:45 PM PDT 24
Finished Jun 21 06:44:16 PM PDT 24
Peak memory 205916 kb
Host smart-b374ce0c-b48d-4231-ab4d-88bdd5368705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023184228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.4023184228
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2662191710
Short name T161
Test name
Test status
Simulation time 17437098 ps
CPU time 0.82 seconds
Started Jun 21 06:43:29 PM PDT 24
Finished Jun 21 06:44:00 PM PDT 24
Peak memory 215632 kb
Host smart-552a5660-a7e6-4efe-92eb-7b0119875e27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662191710 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2662191710
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3034441625
Short name T911
Test name
Test status
Simulation time 25009465 ps
CPU time 1.04 seconds
Started Jun 21 06:43:41 PM PDT 24
Finished Jun 21 06:44:10 PM PDT 24
Peak memory 216132 kb
Host smart-f0852301-b68e-441e-8442-243c36fb02b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034441625 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3034441625
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3035632176
Short name T68
Test name
Test status
Simulation time 67854002 ps
CPU time 0.86 seconds
Started Jun 21 06:43:30 PM PDT 24
Finished Jun 21 06:44:00 PM PDT 24
Peak memory 217656 kb
Host smart-4d7d1ddc-7f9a-4d8c-805d-790b2ba56f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035632176 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3035632176
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1021428158
Short name T484
Test name
Test status
Simulation time 139497437 ps
CPU time 1.61 seconds
Started Jun 21 06:43:31 PM PDT 24
Finished Jun 21 06:44:03 PM PDT 24
Peak memory 217844 kb
Host smart-87c4f588-5e92-4f8e-8db8-3197dbfc7d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021428158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1021428158
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2686209471
Short name T457
Test name
Test status
Simulation time 33335232 ps
CPU time 1.24 seconds
Started Jun 21 06:43:31 PM PDT 24
Finished Jun 21 06:44:02 PM PDT 24
Peak memory 214816 kb
Host smart-b2d580df-5ee2-4c0b-86ee-1c7cdb7cd396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686209471 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2686209471
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2986554979
Short name T506
Test name
Test status
Simulation time 20512309 ps
CPU time 1.01 seconds
Started Jun 21 06:43:29 PM PDT 24
Finished Jun 21 06:44:00 PM PDT 24
Peak memory 206544 kb
Host smart-46256dba-7c78-4571-9241-8f19c374b007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986554979 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2986554979
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2472778074
Short name T942
Test name
Test status
Simulation time 237001729 ps
CPU time 1.19 seconds
Started Jun 21 06:43:28 PM PDT 24
Finished Jun 21 06:44:00 PM PDT 24
Peak memory 214632 kb
Host smart-aca28aa1-39f7-4095-b455-6bcd94877fd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472778074 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2472778074
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1924920102
Short name T229
Test name
Test status
Simulation time 103606888576 ps
CPU time 2653.36 seconds
Started Jun 21 06:43:29 PM PDT 24
Finished Jun 21 07:28:13 PM PDT 24
Peak memory 232620 kb
Host smart-e36a82a4-440b-4b55-9e3d-313c50c6cfde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924920102 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1924920102
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2443011855
Short name T278
Test name
Test status
Simulation time 75331130 ps
CPU time 1.17 seconds
Started Jun 21 06:43:33 PM PDT 24
Finished Jun 21 06:44:05 PM PDT 24
Peak memory 218764 kb
Host smart-13ad91c4-2b4a-4f1b-bee7-dec9cf50378a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443011855 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2443011855
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3962986181
Short name T913
Test name
Test status
Simulation time 30820460 ps
CPU time 0.78 seconds
Started Jun 21 06:43:42 PM PDT 24
Finished Jun 21 06:44:13 PM PDT 24
Peak memory 206280 kb
Host smart-9239e6e6-b89d-466b-ad02-80ad7372b4db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962986181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3962986181
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1613973597
Short name T220
Test name
Test status
Simulation time 15093079 ps
CPU time 0.96 seconds
Started Jun 21 06:43:27 PM PDT 24
Finished Jun 21 06:43:58 PM PDT 24
Peak memory 215972 kb
Host smart-2a37f7f8-df05-4351-b078-36beb4bcd04e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613973597 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1613973597
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.4184466677
Short name T982
Test name
Test status
Simulation time 53662438 ps
CPU time 1.14 seconds
Started Jun 21 06:43:30 PM PDT 24
Finished Jun 21 06:44:02 PM PDT 24
Peak memory 216232 kb
Host smart-6d666052-3da1-4a64-aaf2-21effa1bf384
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184466677 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.4184466677
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2525889377
Short name T209
Test name
Test status
Simulation time 32277740 ps
CPU time 0.91 seconds
Started Jun 21 06:43:28 PM PDT 24
Finished Jun 21 06:44:00 PM PDT 24
Peak memory 218064 kb
Host smart-5d2bd4bb-026a-44ae-9d46-43c29dfed003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525889377 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2525889377
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2086462620
Short name T637
Test name
Test status
Simulation time 39929177 ps
CPU time 1.4 seconds
Started Jun 21 06:43:31 PM PDT 24
Finished Jun 21 06:44:02 PM PDT 24
Peak memory 216800 kb
Host smart-0923e971-16b5-4a7a-a0cc-0246ca52a9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086462620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2086462620
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.849251238
Short name T543
Test name
Test status
Simulation time 27495651 ps
CPU time 0.89 seconds
Started Jun 21 06:43:43 PM PDT 24
Finished Jun 21 06:44:13 PM PDT 24
Peak memory 214920 kb
Host smart-e283a01f-db63-41c3-8956-cedd913e8604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849251238 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.849251238
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.1901430385
Short name T983
Test name
Test status
Simulation time 22598897 ps
CPU time 0.98 seconds
Started Jun 21 06:43:29 PM PDT 24
Finished Jun 21 06:44:00 PM PDT 24
Peak memory 214624 kb
Host smart-65c04d64-d1d3-4621-9b1a-dea64d06e099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901430385 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1901430385
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3633137233
Short name T705
Test name
Test status
Simulation time 626664885 ps
CPU time 3.6 seconds
Started Jun 21 06:43:29 PM PDT 24
Finished Jun 21 06:44:03 PM PDT 24
Peak memory 216728 kb
Host smart-e6620245-d63f-481f-8dc4-6ff228bffeef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633137233 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3633137233
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_alert.2596894887
Short name T596
Test name
Test status
Simulation time 81035173 ps
CPU time 1.26 seconds
Started Jun 21 06:43:41 PM PDT 24
Finished Jun 21 06:44:11 PM PDT 24
Peak memory 218340 kb
Host smart-472a87e3-1ed6-472d-80a3-f96281cec285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596894887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2596894887
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2185495150
Short name T421
Test name
Test status
Simulation time 15620438 ps
CPU time 0.97 seconds
Started Jun 21 06:43:38 PM PDT 24
Finished Jun 21 06:44:08 PM PDT 24
Peak memory 206136 kb
Host smart-538bc088-120a-43cc-99a7-9800af4ad113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185495150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2185495150
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2629398573
Short name T206
Test name
Test status
Simulation time 39717818 ps
CPU time 0.85 seconds
Started Jun 21 06:43:41 PM PDT 24
Finished Jun 21 06:44:10 PM PDT 24
Peak memory 215688 kb
Host smart-1708ea0b-e223-47a4-bc50-20c3654c7a35
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629398573 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2629398573
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3277467781
Short name T580
Test name
Test status
Simulation time 52399137 ps
CPU time 1.08 seconds
Started Jun 21 06:43:40 PM PDT 24
Finished Jun 21 06:44:10 PM PDT 24
Peak memory 216340 kb
Host smart-c57b0de2-36b3-4488-be43-47450b33f2af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277467781 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3277467781
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.880838813
Short name T210
Test name
Test status
Simulation time 32055244 ps
CPU time 0.87 seconds
Started Jun 21 06:43:44 PM PDT 24
Finished Jun 21 06:44:16 PM PDT 24
Peak memory 217748 kb
Host smart-e3741e61-7e2d-45b7-b7cf-8ecbe8074d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880838813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.880838813
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2621867298
Short name T919
Test name
Test status
Simulation time 55520597 ps
CPU time 1.45 seconds
Started Jun 21 06:43:40 PM PDT 24
Finished Jun 21 06:44:11 PM PDT 24
Peak memory 217928 kb
Host smart-fd0ccca3-8e79-431c-a89c-b253917db8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621867298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2621867298
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2998649211
Short name T883
Test name
Test status
Simulation time 28141719 ps
CPU time 0.91 seconds
Started Jun 21 06:43:41 PM PDT 24
Finished Jun 21 06:44:10 PM PDT 24
Peak memory 215140 kb
Host smart-635f5e32-d6b9-43d6-b0f0-a7c981316445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998649211 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2998649211
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.598160422
Short name T875
Test name
Test status
Simulation time 21434495 ps
CPU time 0.99 seconds
Started Jun 21 06:43:38 PM PDT 24
Finished Jun 21 06:44:10 PM PDT 24
Peak memory 214604 kb
Host smart-810d65aa-3cfe-49a2-b7c2-2dcf208ef067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598160422 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.598160422
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2322418856
Short name T716
Test name
Test status
Simulation time 36035241 ps
CPU time 1.27 seconds
Started Jun 21 06:43:43 PM PDT 24
Finished Jun 21 06:44:14 PM PDT 24
Peak memory 214640 kb
Host smart-02303929-3232-41b6-b294-ec69c59fad93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322418856 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2322418856
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2076048348
Short name T991
Test name
Test status
Simulation time 39241853769 ps
CPU time 492.35 seconds
Started Jun 21 06:43:39 PM PDT 24
Finished Jun 21 06:52:21 PM PDT 24
Peak memory 217456 kb
Host smart-1991779c-8986-4ab5-bd3e-642cdb2cb1fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076048348 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2076048348
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.46911993
Short name T726
Test name
Test status
Simulation time 75551716 ps
CPU time 1.22 seconds
Started Jun 21 06:43:38 PM PDT 24
Finished Jun 21 06:44:10 PM PDT 24
Peak memory 218012 kb
Host smart-6b518893-1ebb-41ba-a6d2-e32a0da912cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46911993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.46911993
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2893256755
Short name T855
Test name
Test status
Simulation time 29838126 ps
CPU time 0.92 seconds
Started Jun 21 06:43:38 PM PDT 24
Finished Jun 21 06:44:08 PM PDT 24
Peak memory 206100 kb
Host smart-ed5a7b44-578d-4264-946a-7bb967387d05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893256755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2893256755
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2309769412
Short name T655
Test name
Test status
Simulation time 48100248 ps
CPU time 1.41 seconds
Started Jun 21 06:43:37 PM PDT 24
Finished Jun 21 06:44:08 PM PDT 24
Peak memory 216176 kb
Host smart-86a84dd7-4046-4a7b-a73a-c14e84465bc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309769412 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2309769412
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1811917027
Short name T872
Test name
Test status
Simulation time 40652990 ps
CPU time 0.92 seconds
Started Jun 21 06:43:41 PM PDT 24
Finished Jun 21 06:44:10 PM PDT 24
Peak memory 217804 kb
Host smart-18fa67c2-d4f3-444d-a874-d9c5c7c795aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811917027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1811917027
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.231784102
Short name T848
Test name
Test status
Simulation time 46775900 ps
CPU time 1.63 seconds
Started Jun 21 06:43:39 PM PDT 24
Finished Jun 21 06:44:11 PM PDT 24
Peak memory 217784 kb
Host smart-4224eea5-5d36-43e4-b817-4874847fc22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231784102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.231784102
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2730823947
Short name T507
Test name
Test status
Simulation time 31746674 ps
CPU time 1.03 seconds
Started Jun 21 06:43:40 PM PDT 24
Finished Jun 21 06:44:10 PM PDT 24
Peak memory 223364 kb
Host smart-27ac99cc-3ed7-4206-9b7f-09ff8ff7794d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730823947 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2730823947
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.4264305046
Short name T643
Test name
Test status
Simulation time 38970200 ps
CPU time 0.91 seconds
Started Jun 21 06:43:38 PM PDT 24
Finished Jun 21 06:44:08 PM PDT 24
Peak memory 214632 kb
Host smart-ad2e8794-48ef-4cbf-8b02-8868dfc26d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264305046 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.4264305046
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.4184053031
Short name T355
Test name
Test status
Simulation time 348605888 ps
CPU time 3.92 seconds
Started Jun 21 06:43:39 PM PDT 24
Finished Jun 21 06:44:13 PM PDT 24
Peak memory 216792 kb
Host smart-95b7308d-b07f-49c3-a877-ddc9deebaa5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184053031 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.4184053031
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2461179247
Short name T830
Test name
Test status
Simulation time 228355226139 ps
CPU time 2725.11 seconds
Started Jun 21 06:43:41 PM PDT 24
Finished Jun 21 07:29:35 PM PDT 24
Peak memory 228632 kb
Host smart-6366c9c8-7025-4c7c-be12-eba6fef8e262
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461179247 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2461179247
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1756978403
Short name T127
Test name
Test status
Simulation time 75660240 ps
CPU time 1.28 seconds
Started Jun 21 06:43:39 PM PDT 24
Finished Jun 21 06:44:10 PM PDT 24
Peak memory 218040 kb
Host smart-f4c2db33-2396-45cd-bb0b-17369aee77e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756978403 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1756978403
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1166928687
Short name T434
Test name
Test status
Simulation time 23711440 ps
CPU time 0.89 seconds
Started Jun 21 06:43:38 PM PDT 24
Finished Jun 21 06:44:08 PM PDT 24
Peak memory 214552 kb
Host smart-e348b2c3-da0d-4b98-9416-421cd9bfbecd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166928687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1166928687
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3497166101
Short name T155
Test name
Test status
Simulation time 39666744 ps
CPU time 0.88 seconds
Started Jun 21 06:43:39 PM PDT 24
Finished Jun 21 06:44:10 PM PDT 24
Peak memory 214824 kb
Host smart-697ec7a7-3d6c-4dca-ae24-97458fb35f53
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497166101 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3497166101
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1782360769
Short name T987
Test name
Test status
Simulation time 80634227 ps
CPU time 1.22 seconds
Started Jun 21 06:43:45 PM PDT 24
Finished Jun 21 06:44:16 PM PDT 24
Peak memory 216356 kb
Host smart-fb3685ad-3e07-4cec-a483-df2d3a10dafd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782360769 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1782360769
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1145833490
Short name T199
Test name
Test status
Simulation time 33997818 ps
CPU time 0.86 seconds
Started Jun 21 06:43:38 PM PDT 24
Finished Jun 21 06:44:08 PM PDT 24
Peak memory 218580 kb
Host smart-404c03f7-1807-4724-88e3-e83b0a80f226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145833490 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1145833490
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.4188828631
Short name T990
Test name
Test status
Simulation time 93716664 ps
CPU time 1.22 seconds
Started Jun 21 06:43:39 PM PDT 24
Finished Jun 21 06:44:10 PM PDT 24
Peak memory 216792 kb
Host smart-92c07784-ee82-43f2-bc5f-29b7c3a1a1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188828631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.4188828631
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1932910808
Short name T647
Test name
Test status
Simulation time 31305751 ps
CPU time 0.95 seconds
Started Jun 21 06:43:41 PM PDT 24
Finished Jun 21 06:44:10 PM PDT 24
Peak memory 214620 kb
Host smart-3a62dcac-076d-418a-a1ef-0494cddf6643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932910808 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1932910808
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.637367441
Short name T733
Test name
Test status
Simulation time 16579254 ps
CPU time 0.97 seconds
Started Jun 21 06:43:38 PM PDT 24
Finished Jun 21 06:44:08 PM PDT 24
Peak memory 214620 kb
Host smart-9772b46f-e5c4-4fec-9e63-ffe214a589bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637367441 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.637367441
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2833132534
Short name T311
Test name
Test status
Simulation time 267744077 ps
CPU time 2.08 seconds
Started Jun 21 06:43:44 PM PDT 24
Finished Jun 21 06:44:17 PM PDT 24
Peak memory 216728 kb
Host smart-a2027481-861f-42fb-bfbe-9dc9eef2ca1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833132534 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2833132534
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3799463783
Short name T617
Test name
Test status
Simulation time 53045804956 ps
CPU time 1202.64 seconds
Started Jun 21 06:43:39 PM PDT 24
Finished Jun 21 07:04:12 PM PDT 24
Peak memory 219040 kb
Host smart-e54bfc41-159c-49a1-a9d9-0e4335341c86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799463783 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3799463783
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.675379618
Short name T8
Test name
Test status
Simulation time 28455871 ps
CPU time 1.21 seconds
Started Jun 21 06:43:51 PM PDT 24
Finished Jun 21 06:44:25 PM PDT 24
Peak memory 220024 kb
Host smart-d75af5c2-caaa-4afc-b1c6-4e5965c366da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675379618 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.675379618
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.229541050
Short name T336
Test name
Test status
Simulation time 16697305 ps
CPU time 0.95 seconds
Started Jun 21 06:43:55 PM PDT 24
Finished Jun 21 06:44:30 PM PDT 24
Peak memory 214536 kb
Host smart-f9dae7bc-61ef-4e57-a8d8-c8e3f056d260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229541050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.229541050
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.202638815
Short name T189
Test name
Test status
Simulation time 36583655 ps
CPU time 0.85 seconds
Started Jun 21 06:43:48 PM PDT 24
Finished Jun 21 06:44:22 PM PDT 24
Peak memory 215700 kb
Host smart-e422a2de-80a5-481d-855b-e342c38bcf7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202638815 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.202638815
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1485359437
Short name T17
Test name
Test status
Simulation time 83632948 ps
CPU time 1.06 seconds
Started Jun 21 06:43:49 PM PDT 24
Finished Jun 21 06:44:22 PM PDT 24
Peak memory 217680 kb
Host smart-40607d5d-a373-4fdc-aefc-29c8da20e29f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485359437 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1485359437
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1897848713
Short name T144
Test name
Test status
Simulation time 27371693 ps
CPU time 1.18 seconds
Started Jun 21 06:43:49 PM PDT 24
Finished Jun 21 06:44:23 PM PDT 24
Peak memory 220020 kb
Host smart-b7c482ee-528f-48d6-a6ec-b20853e9120d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897848713 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1897848713
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.4275650380
Short name T320
Test name
Test status
Simulation time 46071553 ps
CPU time 1.29 seconds
Started Jun 21 06:43:38 PM PDT 24
Finished Jun 21 06:44:10 PM PDT 24
Peak memory 216820 kb
Host smart-d2081571-3a09-451b-8e34-aba9a1ffdfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275650380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.4275650380
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1434457213
Short name T27
Test name
Test status
Simulation time 30373588 ps
CPU time 0.84 seconds
Started Jun 21 06:43:50 PM PDT 24
Finished Jun 21 06:44:22 PM PDT 24
Peak memory 215072 kb
Host smart-62d8638c-e41b-48b0-a31a-b9d5faf49758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434457213 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1434457213
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3904492841
Short name T396
Test name
Test status
Simulation time 40345856 ps
CPU time 0.87 seconds
Started Jun 21 06:43:40 PM PDT 24
Finished Jun 21 06:44:10 PM PDT 24
Peak memory 214596 kb
Host smart-4727f470-bf5a-4bfa-9ed0-9897363eaff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904492841 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3904492841
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3974368942
Short name T861
Test name
Test status
Simulation time 464254025 ps
CPU time 5 seconds
Started Jun 21 06:43:41 PM PDT 24
Finished Jun 21 06:44:14 PM PDT 24
Peak memory 214664 kb
Host smart-4542e5cd-cf01-4e0f-87a3-b807e5f4f9d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974368942 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3974368942
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1512205818
Short name T233
Test name
Test status
Simulation time 71088401632 ps
CPU time 925.26 seconds
Started Jun 21 06:43:48 PM PDT 24
Finished Jun 21 06:59:46 PM PDT 24
Peak memory 220148 kb
Host smart-66154485-3c07-414d-85d1-6fc9fc2118b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512205818 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1512205818
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2911036465
Short name T498
Test name
Test status
Simulation time 83945985 ps
CPU time 1.19 seconds
Started Jun 21 06:43:49 PM PDT 24
Finished Jun 21 06:44:23 PM PDT 24
Peak memory 220848 kb
Host smart-1ae83ce8-8ffe-4df2-9788-1f1b837d90d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911036465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2911036465
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.4068657799
Short name T351
Test name
Test status
Simulation time 18141800 ps
CPU time 0.99 seconds
Started Jun 21 06:43:55 PM PDT 24
Finished Jun 21 06:44:30 PM PDT 24
Peak memory 206092 kb
Host smart-a3456c2c-4f67-4c5d-a196-59722198100f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068657799 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.4068657799
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.463688909
Short name T80
Test name
Test status
Simulation time 33156110 ps
CPU time 1.15 seconds
Started Jun 21 06:43:48 PM PDT 24
Finished Jun 21 06:44:22 PM PDT 24
Peak memory 216132 kb
Host smart-de37d909-8d3b-41d9-91ae-cf669fb005be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463688909 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.463688909
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3486090832
Short name T722
Test name
Test status
Simulation time 19042757 ps
CPU time 1.05 seconds
Started Jun 21 06:43:48 PM PDT 24
Finished Jun 21 06:44:22 PM PDT 24
Peak memory 218064 kb
Host smart-f352c0b9-6f5e-49d8-8a00-195aad5414be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486090832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3486090832
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3001489096
Short name T729
Test name
Test status
Simulation time 36625866 ps
CPU time 1.32 seconds
Started Jun 21 06:43:52 PM PDT 24
Finished Jun 21 06:44:27 PM PDT 24
Peak memory 217680 kb
Host smart-8a79e663-0ccf-4377-8fa0-682a0770ff3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001489096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3001489096
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.690039679
Short name T33
Test name
Test status
Simulation time 26912516 ps
CPU time 0.86 seconds
Started Jun 21 06:43:50 PM PDT 24
Finished Jun 21 06:44:22 PM PDT 24
Peak memory 214984 kb
Host smart-6dc4665b-f5e3-444b-a167-71b98f949339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690039679 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.690039679
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3962872012
Short name T807
Test name
Test status
Simulation time 45917378 ps
CPU time 0.93 seconds
Started Jun 21 06:43:52 PM PDT 24
Finished Jun 21 06:44:27 PM PDT 24
Peak memory 214624 kb
Host smart-19b94a8e-cf1a-49cc-8862-a829b78c09e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962872012 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3962872012
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3208449578
Short name T751
Test name
Test status
Simulation time 100009807 ps
CPU time 2.51 seconds
Started Jun 21 06:43:50 PM PDT 24
Finished Jun 21 06:44:24 PM PDT 24
Peak memory 214696 kb
Host smart-0b77e204-3409-4288-b0ae-4ec94f9a60a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208449578 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3208449578
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2280122169
Short name T450
Test name
Test status
Simulation time 105931994396 ps
CPU time 1341.19 seconds
Started Jun 21 06:43:50 PM PDT 24
Finished Jun 21 07:06:45 PM PDT 24
Peak memory 223956 kb
Host smart-6bc9cd77-5a26-459a-86a9-0dc344c032bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280122169 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2280122169
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1631797092
Short name T980
Test name
Test status
Simulation time 29837705 ps
CPU time 1.18 seconds
Started Jun 21 06:43:49 PM PDT 24
Finished Jun 21 06:44:23 PM PDT 24
Peak memory 218764 kb
Host smart-4839eda3-f51e-486a-b02e-930b143f7056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631797092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1631797092
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1817594920
Short name T809
Test name
Test status
Simulation time 23840507 ps
CPU time 0.85 seconds
Started Jun 21 06:43:50 PM PDT 24
Finished Jun 21 06:44:24 PM PDT 24
Peak memory 206088 kb
Host smart-4a8aaf09-8d92-497b-8888-5e53e16a968c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817594920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1817594920
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.4080828615
Short name T720
Test name
Test status
Simulation time 20927749 ps
CPU time 0.87 seconds
Started Jun 21 06:43:54 PM PDT 24
Finished Jun 21 06:44:29 PM PDT 24
Peak memory 215664 kb
Host smart-f14c4361-6c4d-4332-ad92-0ba804e21d01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080828615 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.4080828615
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.160303472
Short name T567
Test name
Test status
Simulation time 25532909 ps
CPU time 1.13 seconds
Started Jun 21 06:43:53 PM PDT 24
Finished Jun 21 06:44:28 PM PDT 24
Peak memory 216188 kb
Host smart-a7c10af1-5bb7-4da6-8815-e5b3c7f22129
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160303472 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.160303472
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.4191383272
Short name T975
Test name
Test status
Simulation time 28126176 ps
CPU time 0.92 seconds
Started Jun 21 06:43:49 PM PDT 24
Finished Jun 21 06:44:22 PM PDT 24
Peak memory 218096 kb
Host smart-e61b70f8-ce52-40ab-871d-404927438a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191383272 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.4191383272
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1350718190
Short name T944
Test name
Test status
Simulation time 49568077 ps
CPU time 1.02 seconds
Started Jun 21 06:43:49 PM PDT 24
Finished Jun 21 06:44:22 PM PDT 24
Peak memory 216852 kb
Host smart-4745caa7-6939-4c17-a3e8-46381984f542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350718190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1350718190
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.300369069
Short name T619
Test name
Test status
Simulation time 45361605 ps
CPU time 0.85 seconds
Started Jun 21 06:43:55 PM PDT 24
Finished Jun 21 06:44:30 PM PDT 24
Peak memory 214760 kb
Host smart-4cf325ab-9de7-43f2-bbe2-df0dd987eb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300369069 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.300369069
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1543567119
Short name T333
Test name
Test status
Simulation time 72863165 ps
CPU time 0.91 seconds
Started Jun 21 06:43:48 PM PDT 24
Finished Jun 21 06:44:19 PM PDT 24
Peak memory 214616 kb
Host smart-ede0a06a-e2c2-4bc5-96e4-7a97941a5fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543567119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1543567119
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2358264123
Short name T737
Test name
Test status
Simulation time 285466097 ps
CPU time 1.94 seconds
Started Jun 21 06:43:54 PM PDT 24
Finished Jun 21 06:44:29 PM PDT 24
Peak memory 216524 kb
Host smart-06d35be8-c3fe-4c14-a418-78003581d840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358264123 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2358264123
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3259597016
Short name T35
Test name
Test status
Simulation time 22011850566 ps
CPU time 466.68 seconds
Started Jun 21 06:43:48 PM PDT 24
Finished Jun 21 06:52:08 PM PDT 24
Peak memory 222960 kb
Host smart-e8dddd3d-d3e0-44d4-9027-28480fde0a3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259597016 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3259597016
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2377337090
Short name T993
Test name
Test status
Simulation time 38567765 ps
CPU time 1.13 seconds
Started Jun 21 06:43:54 PM PDT 24
Finished Jun 21 06:44:30 PM PDT 24
Peak memory 218272 kb
Host smart-55aa6cbf-d213-4601-89f1-f7023e8583b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377337090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2377337090
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.438107497
Short name T790
Test name
Test status
Simulation time 89061262 ps
CPU time 1 seconds
Started Jun 21 06:43:51 PM PDT 24
Finished Jun 21 06:44:25 PM PDT 24
Peak memory 214608 kb
Host smart-39887219-b8da-49b0-8872-39b6cf7838c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438107497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.438107497
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1065292734
Short name T213
Test name
Test status
Simulation time 34634162 ps
CPU time 0.86 seconds
Started Jun 21 06:43:51 PM PDT 24
Finished Jun 21 06:44:24 PM PDT 24
Peak memory 215704 kb
Host smart-18060b6c-1521-4e28-9a2f-6b1a6ccd1526
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065292734 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1065292734
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1311815480
Short name T529
Test name
Test status
Simulation time 101846581 ps
CPU time 1.04 seconds
Started Jun 21 06:43:48 PM PDT 24
Finished Jun 21 06:44:22 PM PDT 24
Peak memory 217472 kb
Host smart-2257f75e-8b20-439c-8371-1cf337110cad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311815480 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1311815480
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.849500765
Short name T55
Test name
Test status
Simulation time 39381877 ps
CPU time 1.15 seconds
Started Jun 21 06:43:54 PM PDT 24
Finished Jun 21 06:44:30 PM PDT 24
Peak memory 229124 kb
Host smart-81b697c6-14e5-40d9-891b-00c0d05b4fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849500765 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.849500765
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3843341520
Short name T930
Test name
Test status
Simulation time 77091304 ps
CPU time 1.15 seconds
Started Jun 21 06:43:50 PM PDT 24
Finished Jun 21 06:44:24 PM PDT 24
Peak memory 216608 kb
Host smart-deb10962-0cb6-489b-a06b-74594739f957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843341520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3843341520
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1156846329
Short name T350
Test name
Test status
Simulation time 23947165 ps
CPU time 0.98 seconds
Started Jun 21 06:43:54 PM PDT 24
Finished Jun 21 06:44:30 PM PDT 24
Peak memory 214964 kb
Host smart-977da435-3cd9-47ef-b6a2-3eca1c341fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156846329 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1156846329
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3259025774
Short name T927
Test name
Test status
Simulation time 57979222 ps
CPU time 0.92 seconds
Started Jun 21 06:43:46 PM PDT 24
Finished Jun 21 06:44:19 PM PDT 24
Peak memory 214604 kb
Host smart-bfd487c2-be92-486d-9709-f821aea4d00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259025774 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3259025774
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3672358734
Short name T724
Test name
Test status
Simulation time 134178511 ps
CPU time 1.86 seconds
Started Jun 21 06:43:50 PM PDT 24
Finished Jun 21 06:44:25 PM PDT 24
Peak memory 214640 kb
Host smart-63620920-170f-4ccf-8ecd-ed9e8baa00ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672358734 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3672358734
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1567590066
Short name T262
Test name
Test status
Simulation time 66029668036 ps
CPU time 380.51 seconds
Started Jun 21 06:43:51 PM PDT 24
Finished Jun 21 06:50:44 PM PDT 24
Peak memory 217032 kb
Host smart-ae7dfca7-a9f8-4e44-8817-22e75b73f4b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567590066 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1567590066
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1080704334
Short name T841
Test name
Test status
Simulation time 52963443 ps
CPU time 1.11 seconds
Started Jun 21 06:41:21 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 218192 kb
Host smart-1edb1410-7c5d-4e6f-a266-152a1621ad45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080704334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1080704334
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.981066815
Short name T925
Test name
Test status
Simulation time 48373784 ps
CPU time 0.89 seconds
Started Jun 21 06:41:20 PM PDT 24
Finished Jun 21 06:42:26 PM PDT 24
Peak memory 206144 kb
Host smart-8f19f8a5-8e58-4643-b997-56ce05968193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981066815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.981066815
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2113465464
Short name T187
Test name
Test status
Simulation time 34401945 ps
CPU time 0.88 seconds
Started Jun 21 06:41:22 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 215692 kb
Host smart-ec531cb1-493d-43da-8ea9-305c1af58ecb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113465464 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2113465464
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.807214345
Short name T646
Test name
Test status
Simulation time 177866375 ps
CPU time 1 seconds
Started Jun 21 06:41:23 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 216132 kb
Host smart-d18fcdb3-0516-4f0a-bcb9-1be7d56c7f60
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807214345 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.807214345
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3251653469
Short name T687
Test name
Test status
Simulation time 30737999 ps
CPU time 1.04 seconds
Started Jun 21 06:41:21 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 223288 kb
Host smart-3de442a9-f5f6-4474-b93b-19a16804d4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251653469 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3251653469
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.811223872
Short name T443
Test name
Test status
Simulation time 55937848 ps
CPU time 1.12 seconds
Started Jun 21 06:41:20 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 216688 kb
Host smart-f64db97f-3b41-42e8-8cae-499bba1f2257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811223872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.811223872
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2995579636
Short name T823
Test name
Test status
Simulation time 21991822 ps
CPU time 1.07 seconds
Started Jun 21 06:41:23 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 215204 kb
Host smart-61e227ee-d584-40f6-9b7f-947728f4f469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995579636 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2995579636
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2926952775
Short name T448
Test name
Test status
Simulation time 68112090 ps
CPU time 0.86 seconds
Started Jun 21 06:41:22 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 206392 kb
Host smart-6652e0a7-13e3-4b50-8886-a825a420aaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926952775 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2926952775
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3048518682
Short name T635
Test name
Test status
Simulation time 19307763 ps
CPU time 1.02 seconds
Started Jun 21 06:41:20 PM PDT 24
Finished Jun 21 06:42:26 PM PDT 24
Peak memory 214644 kb
Host smart-f2127c21-ee35-4a4a-8fce-3ba7af9e9c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048518682 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3048518682
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2158329360
Short name T896
Test name
Test status
Simulation time 816385390 ps
CPU time 4.63 seconds
Started Jun 21 06:41:20 PM PDT 24
Finished Jun 21 06:42:30 PM PDT 24
Peak memory 216676 kb
Host smart-eb61d65e-302a-469d-811c-ae1deb805e69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158329360 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2158329360
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/50.edn_alert.1701989595
Short name T290
Test name
Test status
Simulation time 212923360 ps
CPU time 1.22 seconds
Started Jun 21 06:43:49 PM PDT 24
Finished Jun 21 06:44:22 PM PDT 24
Peak memory 218948 kb
Host smart-31698a10-e7c3-4204-af0b-06135bf7b5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701989595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.1701989595
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.575611592
Short name T877
Test name
Test status
Simulation time 18417439 ps
CPU time 1.03 seconds
Started Jun 21 06:43:48 PM PDT 24
Finished Jun 21 06:44:22 PM PDT 24
Peak memory 217844 kb
Host smart-b6a178a7-0c8e-4b82-b497-0958b10cafe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575611592 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.575611592
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.834013414
Short name T950
Test name
Test status
Simulation time 135217967 ps
CPU time 1.49 seconds
Started Jun 21 06:43:50 PM PDT 24
Finished Jun 21 06:44:23 PM PDT 24
Peak memory 217972 kb
Host smart-51c39528-9bfb-4534-9db0-81ca24ba0f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834013414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.834013414
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.1042619481
Short name T957
Test name
Test status
Simulation time 101531205 ps
CPU time 1.09 seconds
Started Jun 21 06:43:48 PM PDT 24
Finished Jun 21 06:44:22 PM PDT 24
Peak memory 220188 kb
Host smart-ed994381-fe42-495c-a0ee-4f2693558e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042619481 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.1042619481
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.3668900284
Short name T166
Test name
Test status
Simulation time 33509463 ps
CPU time 0.89 seconds
Started Jun 21 06:43:48 PM PDT 24
Finished Jun 21 06:44:22 PM PDT 24
Peak memory 217728 kb
Host smart-9407ee5a-d4e1-4f1f-9938-40061003c5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668900284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3668900284
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1549464137
Short name T79
Test name
Test status
Simulation time 43101603 ps
CPU time 1.63 seconds
Started Jun 21 06:43:48 PM PDT 24
Finished Jun 21 06:44:20 PM PDT 24
Peak memory 216640 kb
Host smart-cb3221d9-0f40-4c8b-bef3-044bdcd48d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549464137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1549464137
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.2504468951
Short name T621
Test name
Test status
Simulation time 85042169 ps
CPU time 1.17 seconds
Started Jun 21 06:43:48 PM PDT 24
Finished Jun 21 06:44:22 PM PDT 24
Peak memory 217776 kb
Host smart-23a97009-33d9-46de-812d-8cd598d3cf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504468951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.2504468951
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.719129449
Short name T792
Test name
Test status
Simulation time 20176549 ps
CPU time 1.18 seconds
Started Jun 21 06:43:51 PM PDT 24
Finished Jun 21 06:44:25 PM PDT 24
Peak memory 223380 kb
Host smart-61cb7d94-2c78-4386-9fd3-92aba7ff2844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719129449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.719129449
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1924864391
Short name T300
Test name
Test status
Simulation time 31919698 ps
CPU time 1.48 seconds
Started Jun 21 06:43:49 PM PDT 24
Finished Jun 21 06:44:23 PM PDT 24
Peak memory 219468 kb
Host smart-57a6b260-d6b7-4be0-80fd-b17971982fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924864391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1924864391
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.3561427740
Short name T226
Test name
Test status
Simulation time 46577008 ps
CPU time 1.14 seconds
Started Jun 21 06:44:01 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 218252 kb
Host smart-a4b4b3f6-0619-4991-887a-5fe6e4613eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561427740 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.3561427740
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.503189941
Short name T183
Test name
Test status
Simulation time 19227089 ps
CPU time 1.16 seconds
Started Jun 21 06:44:02 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 223388 kb
Host smart-815f4648-ff6a-4639-80ca-c28156bddcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503189941 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.503189941
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.311293061
Short name T366
Test name
Test status
Simulation time 40436180 ps
CPU time 1.17 seconds
Started Jun 21 06:43:49 PM PDT 24
Finished Jun 21 06:44:23 PM PDT 24
Peak memory 217980 kb
Host smart-3c83f54e-6e83-4cfd-8289-47a20196469d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311293061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.311293061
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.2421373586
Short name T755
Test name
Test status
Simulation time 33175108 ps
CPU time 1.34 seconds
Started Jun 21 06:44:01 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 219984 kb
Host smart-e37206a9-3895-47bc-a5c6-3e2d82446a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421373586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.2421373586
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2996809443
Short name T651
Test name
Test status
Simulation time 25832849 ps
CPU time 1 seconds
Started Jun 21 06:44:02 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 219168 kb
Host smart-aa666288-0f99-4bd0-a7dc-1721f8522d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996809443 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2996809443
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1074420585
Short name T44
Test name
Test status
Simulation time 33222705 ps
CPU time 1.55 seconds
Started Jun 21 06:43:59 PM PDT 24
Finished Jun 21 06:44:37 PM PDT 24
Peak memory 219192 kb
Host smart-5025cd3f-6b3a-4c88-8a22-1100a9fc5997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074420585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1074420585
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.3600229638
Short name T116
Test name
Test status
Simulation time 48177180 ps
CPU time 1.13 seconds
Started Jun 21 06:44:03 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 219416 kb
Host smart-c8e1f009-6ff2-4833-a077-2d499abfccfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600229638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.3600229638
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.1566998667
Short name T956
Test name
Test status
Simulation time 24130523 ps
CPU time 1.18 seconds
Started Jun 21 06:44:01 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 218988 kb
Host smart-20d2f174-bdd2-43d1-9f64-9a2a4ba46b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566998667 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1566998667
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.4160750270
Short name T839
Test name
Test status
Simulation time 53710856 ps
CPU time 1 seconds
Started Jun 21 06:44:01 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 216672 kb
Host smart-a4e5fa9b-aa9d-430e-b63e-59d77e60fac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160750270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.4160750270
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.1927053049
Short name T802
Test name
Test status
Simulation time 41744282 ps
CPU time 1.26 seconds
Started Jun 21 06:43:58 PM PDT 24
Finished Jun 21 06:44:34 PM PDT 24
Peak memory 220080 kb
Host smart-f52ceea0-c21c-42c4-aff4-9b8dee77037a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927053049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.1927053049
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.264154438
Short name T221
Test name
Test status
Simulation time 20670261 ps
CPU time 1.11 seconds
Started Jun 21 06:44:03 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 223396 kb
Host smart-6c61c077-0246-4d68-a0ba-0a3e09891cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264154438 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.264154438
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.760304680
Short name T707
Test name
Test status
Simulation time 107708430 ps
CPU time 1.57 seconds
Started Jun 21 06:44:01 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 218208 kb
Host smart-0d61b608-772e-462c-9844-3d2ef7a7e897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760304680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.760304680
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.3714651019
Short name T156
Test name
Test status
Simulation time 31333110 ps
CPU time 1.2 seconds
Started Jun 21 06:44:02 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 219288 kb
Host smart-2947f61f-9e18-401d-9633-a3b8cd66beb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714651019 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.3714651019
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.983206604
Short name T139
Test name
Test status
Simulation time 50716745 ps
CPU time 1.03 seconds
Started Jun 21 06:43:58 PM PDT 24
Finished Jun 21 06:44:33 PM PDT 24
Peak memory 220020 kb
Host smart-3a4deb95-54d2-40ce-8728-de0cd4fdb2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983206604 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.983206604
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.449611802
Short name T891
Test name
Test status
Simulation time 77378127 ps
CPU time 1.08 seconds
Started Jun 21 06:44:02 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 216708 kb
Host smart-28f94d08-af0b-42e6-b877-324257b8b1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449611802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.449611802
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.2591375427
Short name T853
Test name
Test status
Simulation time 28588660 ps
CPU time 1.23 seconds
Started Jun 21 06:44:01 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 215092 kb
Host smart-661c5788-229c-4b7e-8830-9182235eb425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591375427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.2591375427
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.486659753
Short name T800
Test name
Test status
Simulation time 96935520 ps
CPU time 1.22 seconds
Started Jun 21 06:43:58 PM PDT 24
Finished Jun 21 06:44:33 PM PDT 24
Peak memory 225144 kb
Host smart-c1979ab9-3895-4f15-b428-a2d8d691ce3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486659753 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.486659753
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.4207992832
Short name T307
Test name
Test status
Simulation time 46859981 ps
CPU time 1.34 seconds
Started Jun 21 06:43:58 PM PDT 24
Finished Jun 21 06:44:34 PM PDT 24
Peak memory 217912 kb
Host smart-62ed06fd-d820-442e-bac6-58992cbf90e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207992832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.4207992832
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.1174542954
Short name T291
Test name
Test status
Simulation time 27196189 ps
CPU time 1.29 seconds
Started Jun 21 06:44:00 PM PDT 24
Finished Jun 21 06:44:37 PM PDT 24
Peak memory 219104 kb
Host smart-77af2450-7be3-48d7-92ec-89dfc213bc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174542954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.1174542954
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.716982316
Short name T160
Test name
Test status
Simulation time 65670035 ps
CPU time 0.85 seconds
Started Jun 21 06:44:04 PM PDT 24
Finished Jun 21 06:44:41 PM PDT 24
Peak memory 217360 kb
Host smart-991ac077-e8ef-406e-94ca-449574d51e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716982316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.716982316
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.805470732
Short name T895
Test name
Test status
Simulation time 60011710 ps
CPU time 1.07 seconds
Started Jun 21 06:44:02 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 216696 kb
Host smart-46966c72-fb67-4e0f-a144-73313a5f5155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805470732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.805470732
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.1907948865
Short name T267
Test name
Test status
Simulation time 27926015 ps
CPU time 1.23 seconds
Started Jun 21 06:41:24 PM PDT 24
Finished Jun 21 06:42:30 PM PDT 24
Peak memory 218960 kb
Host smart-ff9a71da-894e-4186-85f5-3964ef560a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907948865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1907948865
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3418419395
Short name T692
Test name
Test status
Simulation time 30117164 ps
CPU time 0.97 seconds
Started Jun 21 06:41:23 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 206104 kb
Host smart-0403674f-c6e9-40a1-8045-5b31a5069427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418419395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3418419395
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3475578383
Short name T721
Test name
Test status
Simulation time 24655593 ps
CPU time 0.91 seconds
Started Jun 21 06:41:22 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 215696 kb
Host smart-574e896d-de16-4594-960f-d28138121ef7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475578383 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3475578383
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.77819542
Short name T269
Test name
Test status
Simulation time 28387860 ps
CPU time 1.09 seconds
Started Jun 21 06:41:23 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 216352 kb
Host smart-ffaaa4a6-a69e-4408-a624-79ca43a2405d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77819542 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disa
ble_auto_req_mode.77819542
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.608962482
Short name T766
Test name
Test status
Simulation time 42724564 ps
CPU time 1.09 seconds
Started Jun 21 06:41:25 PM PDT 24
Finished Jun 21 06:42:30 PM PDT 24
Peak memory 218936 kb
Host smart-3176b990-ede8-4f51-816e-88370523782e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608962482 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.608962482
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1253882861
Short name T101
Test name
Test status
Simulation time 32277202 ps
CPU time 1.2 seconds
Started Jun 21 06:41:23 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 214648 kb
Host smart-b6e79f9a-a458-4a3a-acda-bdf956b54ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253882861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1253882861
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2979449300
Short name T417
Test name
Test status
Simulation time 60207774 ps
CPU time 0.88 seconds
Started Jun 21 06:41:24 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 214848 kb
Host smart-0e6ef389-8aec-4a72-9e09-406c9d243e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979449300 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2979449300
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.459758835
Short name T612
Test name
Test status
Simulation time 19092404 ps
CPU time 1.03 seconds
Started Jun 21 06:41:21 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 206440 kb
Host smart-fa2a250b-baed-4c21-80fd-6e1452988764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459758835 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.459758835
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3830143788
Short name T515
Test name
Test status
Simulation time 129214803 ps
CPU time 0.9 seconds
Started Jun 21 06:41:22 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 214660 kb
Host smart-086c6634-89c0-4c0c-8aa3-8123a3fc71f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830143788 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3830143788
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.514106350
Short name T799
Test name
Test status
Simulation time 1497942116 ps
CPU time 3.54 seconds
Started Jun 21 06:41:22 PM PDT 24
Finished Jun 21 06:42:32 PM PDT 24
Peak memory 214636 kb
Host smart-12eb4ca0-6eef-4d95-8ce6-3010b03fc255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514106350 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.514106350
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.41373896
Short name T988
Test name
Test status
Simulation time 138860695728 ps
CPU time 768.74 seconds
Started Jun 21 06:41:22 PM PDT 24
Finished Jun 21 06:55:17 PM PDT 24
Peak memory 219544 kb
Host smart-4afb69c6-9db4-4c44-a077-84ddb3ac8b20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41373896 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.41373896
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.1138398413
Short name T659
Test name
Test status
Simulation time 375365202 ps
CPU time 1.15 seconds
Started Jun 21 06:44:02 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 217968 kb
Host smart-2d0c58b1-c102-4fff-9134-7468d6e30f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138398413 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1138398413
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.3150036153
Short name T193
Test name
Test status
Simulation time 21779921 ps
CPU time 0.97 seconds
Started Jun 21 06:44:01 PM PDT 24
Finished Jun 21 06:44:38 PM PDT 24
Peak memory 217492 kb
Host smart-03c9752a-1df6-4bac-b06a-6980148fb009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150036153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3150036153
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.809837503
Short name T514
Test name
Test status
Simulation time 88245336 ps
CPU time 1.13 seconds
Started Jun 21 06:44:02 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 218260 kb
Host smart-c6af5357-730f-4101-b1a0-a3fa51b18198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809837503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.809837503
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.4230191638
Short name T813
Test name
Test status
Simulation time 23336460 ps
CPU time 1.14 seconds
Started Jun 21 06:44:00 PM PDT 24
Finished Jun 21 06:44:37 PM PDT 24
Peak memory 219212 kb
Host smart-53994207-b72f-4f18-abac-05dfae777b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230191638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.4230191638
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1465132934
Short name T435
Test name
Test status
Simulation time 19858945 ps
CPU time 1.06 seconds
Started Jun 21 06:44:00 PM PDT 24
Finished Jun 21 06:44:37 PM PDT 24
Peak memory 217788 kb
Host smart-695f6316-0777-4f38-89f9-304c900845b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465132934 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1465132934
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.414723033
Short name T375
Test name
Test status
Simulation time 100182340 ps
CPU time 1.24 seconds
Started Jun 21 06:44:01 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 216776 kb
Host smart-32a22988-557a-44a6-a315-f8104fe2a801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414723033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.414723033
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.2910914931
Short name T846
Test name
Test status
Simulation time 90020653 ps
CPU time 1.17 seconds
Started Jun 21 06:44:03 PM PDT 24
Finished Jun 21 06:44:41 PM PDT 24
Peak memory 218772 kb
Host smart-887e6e4b-5abd-4c8d-b15e-bd631dc045c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910914931 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.2910914931
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.3207743178
Short name T174
Test name
Test status
Simulation time 27322791 ps
CPU time 1.03 seconds
Started Jun 21 06:44:00 PM PDT 24
Finished Jun 21 06:44:37 PM PDT 24
Peak memory 223260 kb
Host smart-2ee6722f-c99b-49a7-9131-e41551b76bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207743178 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3207743178
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1693947415
Short name T826
Test name
Test status
Simulation time 62684497 ps
CPU time 1.51 seconds
Started Jun 21 06:44:01 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 217908 kb
Host smart-288d6f9e-8dcf-4d93-aa7e-0dd5d2f07782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693947415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1693947415
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.3979823194
Short name T9
Test name
Test status
Simulation time 28703865 ps
CPU time 1.24 seconds
Started Jun 21 06:44:02 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 219116 kb
Host smart-7e95b883-1e01-45aa-a102-ff92b1c8991e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979823194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.3979823194
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.839163111
Short name T67
Test name
Test status
Simulation time 33566149 ps
CPU time 0.89 seconds
Started Jun 21 06:44:03 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 217820 kb
Host smart-59a9393e-3f1a-4a0d-8e5e-39f908447f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839163111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.839163111
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.26322709
Short name T561
Test name
Test status
Simulation time 251363144 ps
CPU time 3.04 seconds
Started Jun 21 06:44:00 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 218016 kb
Host smart-ebdb2e85-07be-4950-bf60-8cdb800eb00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26322709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.26322709
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.3542035762
Short name T89
Test name
Test status
Simulation time 105843787 ps
CPU time 1.19 seconds
Started Jun 21 06:44:00 PM PDT 24
Finished Jun 21 06:44:37 PM PDT 24
Peak memory 218028 kb
Host smart-3dd2ec43-bf29-4f67-9720-db2a3c7030b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542035762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.3542035762
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.3325014942
Short name T523
Test name
Test status
Simulation time 19195531 ps
CPU time 1.01 seconds
Started Jun 21 06:43:59 PM PDT 24
Finished Jun 21 06:44:36 PM PDT 24
Peak memory 217572 kb
Host smart-1fe64aef-d675-474b-a8cb-ffbad015402f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325014942 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3325014942
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3949236000
Short name T308
Test name
Test status
Simulation time 46147544 ps
CPU time 1.59 seconds
Started Jun 21 06:44:00 PM PDT 24
Finished Jun 21 06:44:37 PM PDT 24
Peak memory 217956 kb
Host smart-e5cf9878-66d7-4b7e-9729-0f1e23b1f641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949236000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3949236000
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.1303290900
Short name T558
Test name
Test status
Simulation time 35152223 ps
CPU time 1.08 seconds
Started Jun 21 06:44:03 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 218920 kb
Host smart-ebb942c9-c34f-4307-a25f-92d6c7756445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303290900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.1303290900
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.1217145535
Short name T791
Test name
Test status
Simulation time 44907932 ps
CPU time 1.02 seconds
Started Jun 21 06:43:59 PM PDT 24
Finished Jun 21 06:44:36 PM PDT 24
Peak memory 220088 kb
Host smart-c5d94000-815d-42da-a99b-7279c34bf721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217145535 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1217145535
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3615846337
Short name T969
Test name
Test status
Simulation time 43965613 ps
CPU time 1.6 seconds
Started Jun 21 06:44:01 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 217908 kb
Host smart-7e7c2740-f236-4c71-9894-c69e3aa4cb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615846337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3615846337
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.396236556
Short name T717
Test name
Test status
Simulation time 69962181 ps
CPU time 1.19 seconds
Started Jun 21 06:44:01 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 217984 kb
Host smart-becff740-88f2-44d1-8487-a3f8087e1a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396236556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.396236556
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.3112041170
Short name T194
Test name
Test status
Simulation time 37463125 ps
CPU time 1.04 seconds
Started Jun 21 06:44:01 PM PDT 24
Finished Jun 21 06:44:38 PM PDT 24
Peak memory 217740 kb
Host smart-c779fa06-0e0e-467b-953f-c1dbcd72ad43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112041170 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3112041170
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2236233012
Short name T696
Test name
Test status
Simulation time 74853834 ps
CPU time 1.04 seconds
Started Jun 21 06:44:01 PM PDT 24
Finished Jun 21 06:44:38 PM PDT 24
Peak memory 216620 kb
Host smart-90dccf2f-4f49-4da6-b389-b3fd3d604219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236233012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2236233012
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.945022194
Short name T566
Test name
Test status
Simulation time 97971287 ps
CPU time 1.16 seconds
Started Jun 21 06:44:00 PM PDT 24
Finished Jun 21 06:44:37 PM PDT 24
Peak memory 218056 kb
Host smart-59daa801-7752-4005-ac09-be4dc552a21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945022194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.945022194
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.3870059596
Short name T806
Test name
Test status
Simulation time 22492412 ps
CPU time 1.07 seconds
Started Jun 21 06:44:00 PM PDT 24
Finished Jun 21 06:44:37 PM PDT 24
Peak memory 217716 kb
Host smart-4eedc3db-7cdc-4944-8735-112c7516b37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870059596 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3870059596
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3535975489
Short name T916
Test name
Test status
Simulation time 155836166 ps
CPU time 2.57 seconds
Started Jun 21 06:44:00 PM PDT 24
Finished Jun 21 06:44:38 PM PDT 24
Peak memory 216832 kb
Host smart-63e636ab-bf1c-46a5-b692-44a316933f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535975489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3535975489
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.1435365981
Short name T681
Test name
Test status
Simulation time 30751304 ps
CPU time 1.27 seconds
Started Jun 21 06:44:04 PM PDT 24
Finished Jun 21 06:44:42 PM PDT 24
Peak memory 219096 kb
Host smart-d2f0f2cf-2df6-4130-a065-06eafffc77f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435365981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.1435365981
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.1127519863
Short name T135
Test name
Test status
Simulation time 22578832 ps
CPU time 1.21 seconds
Started Jun 21 06:44:00 PM PDT 24
Finished Jun 21 06:44:37 PM PDT 24
Peak memory 217800 kb
Host smart-b47842cc-5e6a-46a1-a051-8f31c50215b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127519863 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1127519863
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3890258023
Short name T691
Test name
Test status
Simulation time 71649134 ps
CPU time 1.38 seconds
Started Jun 21 06:43:59 PM PDT 24
Finished Jun 21 06:44:36 PM PDT 24
Peak memory 216672 kb
Host smart-e199a7d8-374c-47e8-a154-3e51d3a0f709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890258023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3890258023
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.1285992629
Short name T866
Test name
Test status
Simulation time 34303736 ps
CPU time 1.39 seconds
Started Jun 21 06:44:04 PM PDT 24
Finished Jun 21 06:44:42 PM PDT 24
Peak memory 215084 kb
Host smart-14dca960-789d-42cb-8efa-f15427f85a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285992629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.1285992629
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.1427561711
Short name T7
Test name
Test status
Simulation time 44376075 ps
CPU time 0.93 seconds
Started Jun 21 06:44:01 PM PDT 24
Finished Jun 21 06:44:39 PM PDT 24
Peak memory 219348 kb
Host smart-e98be22a-4273-465d-a371-ac20aa7f512a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427561711 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1427561711
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2415343339
Short name T409
Test name
Test status
Simulation time 29446765 ps
CPU time 1.36 seconds
Started Jun 21 06:44:00 PM PDT 24
Finished Jun 21 06:44:37 PM PDT 24
Peak memory 217844 kb
Host smart-d0c5e85b-1ada-4729-8f51-8c702b32f67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415343339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2415343339
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.827177316
Short name T86
Test name
Test status
Simulation time 64535564 ps
CPU time 1.1 seconds
Started Jun 21 06:41:23 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 218152 kb
Host smart-1eba77b5-e459-4f03-a001-3cb24acea78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827177316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.827177316
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2709180711
Short name T411
Test name
Test status
Simulation time 185571562 ps
CPU time 0.85 seconds
Started Jun 21 06:41:21 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 214316 kb
Host smart-20c72779-1a66-4561-a57e-b4b5cec0da05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709180711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2709180711
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1546469784
Short name T177
Test name
Test status
Simulation time 36409229 ps
CPU time 0.81 seconds
Started Jun 21 06:41:23 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 215680 kb
Host smart-3a3e8cf8-8739-414d-a873-a6c83fcc6231
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546469784 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1546469784
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.4110647233
Short name T132
Test name
Test status
Simulation time 127460201 ps
CPU time 1.17 seconds
Started Jun 21 06:41:22 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 219156 kb
Host smart-25a9fe79-11e5-4f77-9239-27cfab3477e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110647233 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.4110647233
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3220174412
Short name T881
Test name
Test status
Simulation time 24871189 ps
CPU time 0.92 seconds
Started Jun 21 06:41:23 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 217904 kb
Host smart-3da9675d-d152-4169-aee1-027be67c876e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220174412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3220174412
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1834147432
Short name T763
Test name
Test status
Simulation time 48879173 ps
CPU time 1.08 seconds
Started Jun 21 06:41:24 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 216560 kb
Host smart-25953332-cfe9-4e2b-ae32-89b5f67b04b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834147432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1834147432
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3996206271
Short name T663
Test name
Test status
Simulation time 34429150 ps
CPU time 1.03 seconds
Started Jun 21 06:41:24 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 223404 kb
Host smart-33ac6cd4-dd49-4936-912b-c931f9c982ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996206271 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3996206271
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.43476748
Short name T797
Test name
Test status
Simulation time 23532463 ps
CPU time 0.96 seconds
Started Jun 21 06:41:24 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 206432 kb
Host smart-6a55744f-feea-47e9-8166-c6c3c439ea46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43476748 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.43476748
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3215644298
Short name T798
Test name
Test status
Simulation time 24818391 ps
CPU time 1.03 seconds
Started Jun 21 06:41:23 PM PDT 24
Finished Jun 21 06:42:29 PM PDT 24
Peak memory 214584 kb
Host smart-02b2c610-ab1c-4ec7-b370-2775d655878c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215644298 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3215644298
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2752101291
Short name T702
Test name
Test status
Simulation time 455801445 ps
CPU time 8.2 seconds
Started Jun 21 06:41:23 PM PDT 24
Finished Jun 21 06:42:36 PM PDT 24
Peak memory 217908 kb
Host smart-020d1f01-be15-4ddc-8508-ae53a9036995
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752101291 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2752101291
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1540494159
Short name T641
Test name
Test status
Simulation time 28199555584 ps
CPU time 381.51 seconds
Started Jun 21 06:41:22 PM PDT 24
Finished Jun 21 06:48:50 PM PDT 24
Peak memory 222652 kb
Host smart-af94a122-2f4f-4800-b621-84560af5d3ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540494159 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1540494159
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.73271228
Short name T268
Test name
Test status
Simulation time 96148529 ps
CPU time 1.15 seconds
Started Jun 21 06:44:05 PM PDT 24
Finished Jun 21 06:44:42 PM PDT 24
Peak memory 218976 kb
Host smart-58abae1c-2e24-4332-85cb-b8056f544083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73271228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.73271228
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.4064682148
Short name T795
Test name
Test status
Simulation time 18251697 ps
CPU time 1.03 seconds
Started Jun 21 06:44:03 PM PDT 24
Finished Jun 21 06:44:41 PM PDT 24
Peak memory 217640 kb
Host smart-ada9de4a-b57a-492b-99a1-e5c9454c17de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064682148 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.4064682148
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2468083911
Short name T279
Test name
Test status
Simulation time 99413248 ps
CPU time 1.15 seconds
Started Jun 21 06:44:04 PM PDT 24
Finished Jun 21 06:44:42 PM PDT 24
Peak memory 216472 kb
Host smart-8289051d-143e-4717-a157-4cc65ecedf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468083911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2468083911
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.3383688365
Short name T827
Test name
Test status
Simulation time 193934313 ps
CPU time 1.1 seconds
Started Jun 21 06:44:03 PM PDT 24
Finished Jun 21 06:44:41 PM PDT 24
Peak memory 219924 kb
Host smart-5647a0c1-1150-4096-af96-cdb6f51590e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383688365 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.3383688365
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.2964656166
Short name T154
Test name
Test status
Simulation time 144437657 ps
CPU time 1.16 seconds
Started Jun 21 06:44:03 PM PDT 24
Finished Jun 21 06:44:41 PM PDT 24
Peak memory 224936 kb
Host smart-636edb5f-5f31-4e66-8b42-4ff09b61bf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964656166 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2964656166
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3494731069
Short name T317
Test name
Test status
Simulation time 99150814 ps
CPU time 1.42 seconds
Started Jun 21 06:44:04 PM PDT 24
Finished Jun 21 06:44:42 PM PDT 24
Peak memory 218236 kb
Host smart-e8de112f-6768-4fc3-9611-e00ceda2ae8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494731069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3494731069
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.2692377912
Short name T47
Test name
Test status
Simulation time 53227715 ps
CPU time 1.19 seconds
Started Jun 21 06:44:07 PM PDT 24
Finished Jun 21 06:44:46 PM PDT 24
Peak memory 219156 kb
Host smart-8c35bf10-4fed-4862-a6d8-bb930ff6be39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692377912 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.2692377912
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.2886668621
Short name T152
Test name
Test status
Simulation time 46998341 ps
CPU time 1.24 seconds
Started Jun 21 06:44:07 PM PDT 24
Finished Jun 21 06:44:46 PM PDT 24
Peak memory 225148 kb
Host smart-64c531ba-2616-4a86-9c0c-7f4e8e72eceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886668621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2886668621
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3534234406
Short name T46
Test name
Test status
Simulation time 46509230 ps
CPU time 1.85 seconds
Started Jun 21 06:44:04 PM PDT 24
Finished Jun 21 06:44:42 PM PDT 24
Peak memory 217932 kb
Host smart-15c9ad08-5520-48de-9b5d-a365d0d769b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534234406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3534234406
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.2030695609
Short name T923
Test name
Test status
Simulation time 71843361 ps
CPU time 1.04 seconds
Started Jun 21 06:44:00 PM PDT 24
Finished Jun 21 06:44:37 PM PDT 24
Peak memory 218996 kb
Host smart-62d73b60-8ccc-42ff-90c1-9ca9583e053f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030695609 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2030695609
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.3520762780
Short name T215
Test name
Test status
Simulation time 20099016 ps
CPU time 1.08 seconds
Started Jun 21 06:44:06 PM PDT 24
Finished Jun 21 06:44:45 PM PDT 24
Peak memory 219252 kb
Host smart-b97e6d90-c128-463e-a7aa-bbb5aee0b8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520762780 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3520762780
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3090731489
Short name T345
Test name
Test status
Simulation time 66636336 ps
CPU time 1.45 seconds
Started Jun 21 06:43:58 PM PDT 24
Finished Jun 21 06:44:34 PM PDT 24
Peak memory 218232 kb
Host smart-3dc174a9-b0f3-42ee-b7e6-6466060330f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090731489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3090731489
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.872837885
Short name T801
Test name
Test status
Simulation time 27952673 ps
CPU time 1.22 seconds
Started Jun 21 06:44:04 PM PDT 24
Finished Jun 21 06:44:41 PM PDT 24
Peak memory 220248 kb
Host smart-b80fd0cb-812c-4c80-abe3-762a708e49c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872837885 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.872837885
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2392175393
Short name T145
Test name
Test status
Simulation time 23357674 ps
CPU time 1.14 seconds
Started Jun 21 06:44:01 PM PDT 24
Finished Jun 21 06:44:37 PM PDT 24
Peak memory 220032 kb
Host smart-044994d8-a71e-465d-bc4a-e7a68a8b0ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392175393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2392175393
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.957855318
Short name T314
Test name
Test status
Simulation time 74038376 ps
CPU time 1.8 seconds
Started Jun 21 06:44:07 PM PDT 24
Finished Jun 21 06:44:46 PM PDT 24
Peak memory 219404 kb
Host smart-36aacca4-c2ce-4630-ab03-bc232c70711c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957855318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.957855318
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.294606773
Short name T924
Test name
Test status
Simulation time 75491421 ps
CPU time 1.1 seconds
Started Jun 21 06:44:04 PM PDT 24
Finished Jun 21 06:44:41 PM PDT 24
Peak memory 217912 kb
Host smart-0591d872-305c-49f3-85f8-36ec160d6819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294606773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.294606773
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.730525197
Short name T118
Test name
Test status
Simulation time 50033177 ps
CPU time 1.02 seconds
Started Jun 21 06:44:13 PM PDT 24
Finished Jun 21 06:44:51 PM PDT 24
Peak memory 219080 kb
Host smart-4333d63a-5dd0-4e6f-be15-c187477421f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730525197 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.730525197
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.248692267
Short name T676
Test name
Test status
Simulation time 60379940 ps
CPU time 1.27 seconds
Started Jun 21 06:44:01 PM PDT 24
Finished Jun 21 06:44:37 PM PDT 24
Peak memory 218132 kb
Host smart-8b497c07-e96d-47b9-aa35-0bc0aed85182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248692267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.248692267
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.3690427196
Short name T887
Test name
Test status
Simulation time 101500906 ps
CPU time 1.25 seconds
Started Jun 21 06:44:08 PM PDT 24
Finished Jun 21 06:44:46 PM PDT 24
Peak memory 215084 kb
Host smart-a13b8606-396e-49ce-a1b9-f0c916bf6968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690427196 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.3690427196
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.2335526889
Short name T159
Test name
Test status
Simulation time 37706793 ps
CPU time 0.93 seconds
Started Jun 21 06:44:08 PM PDT 24
Finished Jun 21 06:44:46 PM PDT 24
Peak memory 223252 kb
Host smart-3da0bf71-e962-44e8-9389-0133037fc4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335526889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2335526889
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3626057819
Short name T473
Test name
Test status
Simulation time 82259717 ps
CPU time 1.28 seconds
Started Jun 21 06:44:09 PM PDT 24
Finished Jun 21 06:44:48 PM PDT 24
Peak memory 216756 kb
Host smart-1f6829f7-8ddf-4d94-8d23-fb4d80b72040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626057819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3626057819
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.2574782804
Short name T531
Test name
Test status
Simulation time 44194602 ps
CPU time 1.18 seconds
Started Jun 21 06:44:17 PM PDT 24
Finished Jun 21 06:44:54 PM PDT 24
Peak memory 218032 kb
Host smart-22e623d8-9cb7-4a7b-aa3d-e2bc47216c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574782804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.2574782804
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.2832258927
Short name T202
Test name
Test status
Simulation time 20102808 ps
CPU time 1.14 seconds
Started Jun 21 06:44:11 PM PDT 24
Finished Jun 21 06:44:49 PM PDT 24
Peak memory 219080 kb
Host smart-e3e0f880-20ef-491d-a80e-766068b1b08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832258927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2832258927
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.333540809
Short name T419
Test name
Test status
Simulation time 76321431 ps
CPU time 2.53 seconds
Started Jun 21 06:44:11 PM PDT 24
Finished Jun 21 06:44:50 PM PDT 24
Peak memory 219456 kb
Host smart-83f0f2dc-ab1e-4f42-bdf5-9c71c4b6e4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333540809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.333540809
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.127582654
Short name T961
Test name
Test status
Simulation time 40077961 ps
CPU time 1.14 seconds
Started Jun 21 06:44:08 PM PDT 24
Finished Jun 21 06:44:46 PM PDT 24
Peak memory 219020 kb
Host smart-0384ceb9-f362-4582-91b5-b0168fc50f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127582654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.127582654
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.4253998713
Short name T623
Test name
Test status
Simulation time 23619229 ps
CPU time 0.93 seconds
Started Jun 21 06:44:18 PM PDT 24
Finished Jun 21 06:44:54 PM PDT 24
Peak memory 217592 kb
Host smart-96c7da0f-2674-4b8f-919a-4400368a4870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253998713 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.4253998713
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2178826949
Short name T306
Test name
Test status
Simulation time 72111389 ps
CPU time 1.22 seconds
Started Jun 21 06:44:09 PM PDT 24
Finished Jun 21 06:44:48 PM PDT 24
Peak memory 218208 kb
Host smart-32136e5d-8ac6-4540-b897-48efbd4db915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178826949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2178826949
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.3226287588
Short name T277
Test name
Test status
Simulation time 39875067 ps
CPU time 1.25 seconds
Started Jun 21 06:44:17 PM PDT 24
Finished Jun 21 06:44:54 PM PDT 24
Peak memory 219156 kb
Host smart-70095790-8cce-4ee0-bb7f-42a929735b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226287588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.3226287588
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.1949886599
Short name T889
Test name
Test status
Simulation time 28783521 ps
CPU time 0.87 seconds
Started Jun 21 06:44:17 PM PDT 24
Finished Jun 21 06:44:53 PM PDT 24
Peak memory 217384 kb
Host smart-df3c6cb5-8b09-4ea6-8b39-a6f60c28ee3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949886599 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1949886599
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3704445349
Short name T389
Test name
Test status
Simulation time 144318700 ps
CPU time 2.01 seconds
Started Jun 21 06:44:11 PM PDT 24
Finished Jun 21 06:44:50 PM PDT 24
Peak memory 219868 kb
Host smart-32bd1a9c-e3d1-4309-b2fe-fd7486df14cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704445349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3704445349
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3655417040
Short name T45
Test name
Test status
Simulation time 53387491 ps
CPU time 1.12 seconds
Started Jun 21 06:41:28 PM PDT 24
Finished Jun 21 06:42:35 PM PDT 24
Peak memory 217976 kb
Host smart-60a96981-94c7-42bf-8562-e3a71d6a8df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655417040 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3655417040
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1069284633
Short name T929
Test name
Test status
Simulation time 19426674 ps
CPU time 1.03 seconds
Started Jun 21 06:41:27 PM PDT 24
Finished Jun 21 06:42:35 PM PDT 24
Peak memory 214580 kb
Host smart-6bf9690d-5cc3-47d3-8efb-69ff47712eeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069284633 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1069284633
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3937036300
Short name T205
Test name
Test status
Simulation time 29432735 ps
CPU time 0.86 seconds
Started Jun 21 06:41:29 PM PDT 24
Finished Jun 21 06:42:39 PM PDT 24
Peak memory 215688 kb
Host smart-19b2d9c4-860f-42d8-b768-472d1c610fca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937036300 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3937036300
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2333919333
Short name T18
Test name
Test status
Simulation time 92889092 ps
CPU time 1.15 seconds
Started Jun 21 06:41:32 PM PDT 24
Finished Jun 21 06:42:40 PM PDT 24
Peak memory 215032 kb
Host smart-93e5cae9-78a6-49ab-b319-56ceaee41616
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333919333 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2333919333
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1869594663
Short name T784
Test name
Test status
Simulation time 22323039 ps
CPU time 1.15 seconds
Started Jun 21 06:41:27 PM PDT 24
Finished Jun 21 06:42:35 PM PDT 24
Peak memory 219148 kb
Host smart-eb40ca02-6c71-42ef-9828-02472b4a8885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869594663 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1869594663
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3066281295
Short name T313
Test name
Test status
Simulation time 91676878 ps
CPU time 1.18 seconds
Started Jun 21 06:41:28 PM PDT 24
Finished Jun 21 06:42:35 PM PDT 24
Peak memory 218280 kb
Host smart-1d820f35-b6c0-4b03-9161-804bcc3639dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066281295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3066281295
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2014424905
Short name T92
Test name
Test status
Simulation time 38023056 ps
CPU time 0.92 seconds
Started Jun 21 06:41:32 PM PDT 24
Finished Jun 21 06:42:40 PM PDT 24
Peak memory 215020 kb
Host smart-39bac665-e4f3-4f18-bacc-280a8293fc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014424905 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2014424905
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.302975546
Short name T793
Test name
Test status
Simulation time 38076022 ps
CPU time 0.86 seconds
Started Jun 21 06:41:30 PM PDT 24
Finished Jun 21 06:42:39 PM PDT 24
Peak memory 206440 kb
Host smart-90babbdd-6da2-4fec-a41a-edfbe32e2fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302975546 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.302975546
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.4036336916
Short name T522
Test name
Test status
Simulation time 17318565 ps
CPU time 0.97 seconds
Started Jun 21 06:41:28 PM PDT 24
Finished Jun 21 06:42:35 PM PDT 24
Peak memory 214724 kb
Host smart-c516b09e-3d3a-4c94-a891-1ae5c40f31bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036336916 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.4036336916
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.277592947
Short name T667
Test name
Test status
Simulation time 843950538 ps
CPU time 4.53 seconds
Started Jun 21 06:41:29 PM PDT 24
Finished Jun 21 06:42:39 PM PDT 24
Peak memory 216544 kb
Host smart-e180d57f-3085-444c-8476-8041c76ad3d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277592947 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.277592947
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.898588862
Short name T677
Test name
Test status
Simulation time 50159281490 ps
CPU time 1134.68 seconds
Started Jun 21 06:41:27 PM PDT 24
Finished Jun 21 07:01:29 PM PDT 24
Peak memory 218828 kb
Host smart-cf871b94-6af7-4d25-903b-17386979fa82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898588862 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.898588862
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.1648974821
Short name T859
Test name
Test status
Simulation time 91267394 ps
CPU time 1.14 seconds
Started Jun 21 06:44:10 PM PDT 24
Finished Jun 21 06:44:49 PM PDT 24
Peak memory 219004 kb
Host smart-47c5d89b-8c4f-4d7f-976a-f95247163ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648974821 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.1648974821
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.2074337091
Short name T165
Test name
Test status
Simulation time 34270111 ps
CPU time 0.86 seconds
Started Jun 21 06:44:11 PM PDT 24
Finished Jun 21 06:44:48 PM PDT 24
Peak memory 217648 kb
Host smart-e151ebb6-a806-4eac-b5a5-66cf0ee29d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074337091 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2074337091
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1493901041
Short name T665
Test name
Test status
Simulation time 42540787 ps
CPU time 1.45 seconds
Started Jun 21 06:44:11 PM PDT 24
Finished Jun 21 06:44:49 PM PDT 24
Peak memory 216588 kb
Host smart-9897bfce-779d-4e11-9103-9c9c015ec430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493901041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1493901041
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1245250853
Short name T263
Test name
Test status
Simulation time 27242630 ps
CPU time 1.29 seconds
Started Jun 21 06:44:10 PM PDT 24
Finished Jun 21 06:44:49 PM PDT 24
Peak memory 219208 kb
Host smart-da090d49-3aa6-4432-a992-d73b0ad11651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245250853 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1245250853
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.488435180
Short name T878
Test name
Test status
Simulation time 36103003 ps
CPU time 0.92 seconds
Started Jun 21 06:44:13 PM PDT 24
Finished Jun 21 06:44:51 PM PDT 24
Peak memory 219280 kb
Host smart-a6202404-64ea-4ae7-8903-f62a45642973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488435180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.488435180
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2141045865
Short name T430
Test name
Test status
Simulation time 416590435 ps
CPU time 3.45 seconds
Started Jun 21 06:44:10 PM PDT 24
Finished Jun 21 06:44:51 PM PDT 24
Peak memory 216876 kb
Host smart-2043f804-7cd9-489e-99e6-d6c487a3b5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141045865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2141045865
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.2291809239
Short name T743
Test name
Test status
Simulation time 31666629 ps
CPU time 1.3 seconds
Started Jun 21 06:44:11 PM PDT 24
Finished Jun 21 06:44:49 PM PDT 24
Peak memory 220044 kb
Host smart-c0d1bc6e-ab44-473d-9f1d-d884c5e6893d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291809239 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.2291809239
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.3083905414
Short name T51
Test name
Test status
Simulation time 20631680 ps
CPU time 1.14 seconds
Started Jun 21 06:44:12 PM PDT 24
Finished Jun 21 06:44:49 PM PDT 24
Peak memory 223376 kb
Host smart-dadb5d1f-3ed8-4592-a278-3521b2c1d982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083905414 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3083905414
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2364034501
Short name T392
Test name
Test status
Simulation time 37658965 ps
CPU time 1.44 seconds
Started Jun 21 06:44:17 PM PDT 24
Finished Jun 21 06:44:54 PM PDT 24
Peak memory 217736 kb
Host smart-4bb93a66-b119-4c50-8baf-63d1eb6e57f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364034501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2364034501
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.459292291
Short name T6
Test name
Test status
Simulation time 20476142 ps
CPU time 1.04 seconds
Started Jun 21 06:44:11 PM PDT 24
Finished Jun 21 06:44:49 PM PDT 24
Peak memory 219048 kb
Host smart-9c9d422c-ab64-4582-a5a6-0aa3c7ade051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459292291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.459292291
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2412140899
Short name T693
Test name
Test status
Simulation time 41480000 ps
CPU time 1.7 seconds
Started Jun 21 06:44:10 PM PDT 24
Finished Jun 21 06:44:49 PM PDT 24
Peak memory 219312 kb
Host smart-d217fcff-aeae-4eaf-89fb-6ed21d6090d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412140899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2412140899
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.2135668372
Short name T133
Test name
Test status
Simulation time 45222973 ps
CPU time 1.16 seconds
Started Jun 21 06:44:13 PM PDT 24
Finished Jun 21 06:44:51 PM PDT 24
Peak memory 217904 kb
Host smart-e779d93c-3b03-4bde-96d7-5782a5ebc6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135668372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2135668372
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.3843617765
Short name T130
Test name
Test status
Simulation time 26078025 ps
CPU time 1.04 seconds
Started Jun 21 06:44:09 PM PDT 24
Finished Jun 21 06:44:46 PM PDT 24
Peak memory 219056 kb
Host smart-e84b2af8-58d9-4976-8ed9-15e9639c1342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843617765 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3843617765
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2540923203
Short name T76
Test name
Test status
Simulation time 61421198 ps
CPU time 1.04 seconds
Started Jun 21 06:44:16 PM PDT 24
Finished Jun 21 06:44:53 PM PDT 24
Peak memory 219308 kb
Host smart-dee17bb5-ef8a-411a-9507-22fb641c3959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540923203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2540923203
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.812518907
Short name T680
Test name
Test status
Simulation time 165194834 ps
CPU time 1.15 seconds
Started Jun 21 06:44:09 PM PDT 24
Finished Jun 21 06:44:48 PM PDT 24
Peak memory 221088 kb
Host smart-f3bc513e-c5de-4f9c-9298-9bdc14183d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812518907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.812518907
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.886190790
Short name T892
Test name
Test status
Simulation time 26856278 ps
CPU time 1.23 seconds
Started Jun 21 06:44:23 PM PDT 24
Finished Jun 21 06:45:01 PM PDT 24
Peak memory 216660 kb
Host smart-b90aebbe-43f2-4225-8431-040496ec44db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886190790 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.886190790
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.732266739
Short name T613
Test name
Test status
Simulation time 33520608 ps
CPU time 1.3 seconds
Started Jun 21 06:44:14 PM PDT 24
Finished Jun 21 06:44:51 PM PDT 24
Peak memory 217964 kb
Host smart-8b18f9a3-f738-4527-a25a-6f9ddf6e4069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732266739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.732266739
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.2085639216
Short name T385
Test name
Test status
Simulation time 33480491 ps
CPU time 1.11 seconds
Started Jun 21 06:44:22 PM PDT 24
Finished Jun 21 06:45:01 PM PDT 24
Peak memory 219160 kb
Host smart-35df5cf9-b757-4c8c-94c3-b3f3a01e1d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085639216 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.2085639216
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2544665175
Short name T14
Test name
Test status
Simulation time 24320558 ps
CPU time 0.96 seconds
Started Jun 21 06:44:22 PM PDT 24
Finished Jun 21 06:45:00 PM PDT 24
Peak memory 223216 kb
Host smart-b1a4f84c-cd69-47ab-a1e2-105e8fcee423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544665175 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2544665175
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3450528517
Short name T318
Test name
Test status
Simulation time 127117013 ps
CPU time 1.42 seconds
Started Jun 21 06:44:21 PM PDT 24
Finished Jun 21 06:45:00 PM PDT 24
Peak memory 218036 kb
Host smart-fdd9e63f-9747-45eb-90fa-41a324b68719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450528517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3450528517
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.107001364
Short name T772
Test name
Test status
Simulation time 28950951 ps
CPU time 1.28 seconds
Started Jun 21 06:44:23 PM PDT 24
Finished Jun 21 06:45:01 PM PDT 24
Peak memory 217972 kb
Host smart-6ce62a27-fca2-49b2-aa35-0d73ccb49d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107001364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.107001364
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.3454706409
Short name T649
Test name
Test status
Simulation time 38843651 ps
CPU time 1.03 seconds
Started Jun 21 06:44:21 PM PDT 24
Finished Jun 21 06:45:00 PM PDT 24
Peak memory 223524 kb
Host smart-759a518b-8946-4f53-9d3f-d46a2532caa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454706409 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3454706409
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2565518309
Short name T48
Test name
Test status
Simulation time 36478144 ps
CPU time 1.53 seconds
Started Jun 21 06:44:24 PM PDT 24
Finished Jun 21 06:45:03 PM PDT 24
Peak memory 216868 kb
Host smart-4fda1e80-56ef-4963-ae1a-23b45a825db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565518309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2565518309
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.400717268
Short name T273
Test name
Test status
Simulation time 90677042 ps
CPU time 1.28 seconds
Started Jun 21 06:44:24 PM PDT 24
Finished Jun 21 06:45:03 PM PDT 24
Peak memory 219488 kb
Host smart-c5eedb55-80bd-4e21-b1da-bc730793199b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400717268 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.400717268
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.1875190671
Short name T136
Test name
Test status
Simulation time 43983755 ps
CPU time 0.95 seconds
Started Jun 21 06:44:22 PM PDT 24
Finished Jun 21 06:45:00 PM PDT 24
Peak memory 218068 kb
Host smart-582e4594-2aeb-4744-a51f-9284e60c5818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875190671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1875190671
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2917019632
Short name T296
Test name
Test status
Simulation time 264899422 ps
CPU time 3.16 seconds
Started Jun 21 06:44:21 PM PDT 24
Finished Jun 21 06:45:00 PM PDT 24
Peak memory 219032 kb
Host smart-64b94421-9276-4c03-ac0a-9fdb72331a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917019632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2917019632
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.1100192845
Short name T453
Test name
Test status
Simulation time 72291085 ps
CPU time 1.09 seconds
Started Jun 21 06:44:25 PM PDT 24
Finished Jun 21 06:45:03 PM PDT 24
Peak memory 218088 kb
Host smart-e368c9bb-c2a2-4da7-8e8a-f89e4ca54de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100192845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.1100192845
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.2003807413
Short name T405
Test name
Test status
Simulation time 108461637 ps
CPU time 1.17 seconds
Started Jun 21 06:44:25 PM PDT 24
Finished Jun 21 06:45:03 PM PDT 24
Peak memory 219128 kb
Host smart-3d30e041-61d5-44d5-9a4f-d3939e644160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003807413 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2003807413
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.790087761
Short name T357
Test name
Test status
Simulation time 50879989 ps
CPU time 1.64 seconds
Started Jun 21 06:44:19 PM PDT 24
Finished Jun 21 06:44:58 PM PDT 24
Peak memory 217960 kb
Host smart-23219d2e-0399-43bb-ae5a-60e61f55b4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790087761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.790087761
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1262093796
Short name T88
Test name
Test status
Simulation time 52104267 ps
CPU time 1.31 seconds
Started Jun 21 06:41:29 PM PDT 24
Finished Jun 21 06:42:36 PM PDT 24
Peak memory 219464 kb
Host smart-bb4adf22-f267-46d2-bde0-716236f03584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262093796 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1262093796
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.4247391102
Short name T564
Test name
Test status
Simulation time 13137126 ps
CPU time 0.9 seconds
Started Jun 21 06:41:39 PM PDT 24
Finished Jun 21 06:42:44 PM PDT 24
Peak memory 206076 kb
Host smart-8b3a163d-5d68-4681-b11d-ed1483809211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247391102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.4247391102
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2338849600
Short name T219
Test name
Test status
Simulation time 10697146 ps
CPU time 0.89 seconds
Started Jun 21 06:41:32 PM PDT 24
Finished Jun 21 06:42:40 PM PDT 24
Peak memory 215748 kb
Host smart-2d4d40ec-4515-41fe-aa96-d1dde8dc4406
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338849600 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2338849600
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1116626015
Short name T140
Test name
Test status
Simulation time 43830808 ps
CPU time 1.05 seconds
Started Jun 21 06:41:29 PM PDT 24
Finished Jun 21 06:42:35 PM PDT 24
Peak memory 216280 kb
Host smart-7aa5ce7d-3cc4-4c9a-aded-acd55b9e6fac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116626015 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1116626015
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3376932332
Short name T704
Test name
Test status
Simulation time 24402926 ps
CPU time 0.89 seconds
Started Jun 21 06:41:31 PM PDT 24
Finished Jun 21 06:42:39 PM PDT 24
Peak memory 217604 kb
Host smart-413b64dc-930d-41df-a912-d488e3ebb80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376932332 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3376932332
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3569574229
Short name T471
Test name
Test status
Simulation time 54385959 ps
CPU time 1.41 seconds
Started Jun 21 06:41:27 PM PDT 24
Finished Jun 21 06:42:36 PM PDT 24
Peak memory 217964 kb
Host smart-1b7b17a1-9b12-4a71-9696-acfc8d3e7b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569574229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3569574229
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2848488090
Short name T356
Test name
Test status
Simulation time 56445269 ps
CPU time 0.92 seconds
Started Jun 21 06:41:28 PM PDT 24
Finished Jun 21 06:42:35 PM PDT 24
Peak memory 214624 kb
Host smart-576e5387-4e55-475e-b881-125692436eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848488090 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2848488090
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1395000296
Short name T654
Test name
Test status
Simulation time 51268953 ps
CPU time 0.96 seconds
Started Jun 21 06:41:27 PM PDT 24
Finished Jun 21 06:42:35 PM PDT 24
Peak memory 206436 kb
Host smart-042cf93e-ab7d-4e88-b5d6-39d7696508f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395000296 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1395000296
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.712470077
Short name T542
Test name
Test status
Simulation time 45099387 ps
CPU time 0.9 seconds
Started Jun 21 06:41:27 PM PDT 24
Finished Jun 21 06:42:35 PM PDT 24
Peak memory 214640 kb
Host smart-af72959d-aad8-4eab-9e66-e60bf87fd5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712470077 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.712470077
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.4164348809
Short name T359
Test name
Test status
Simulation time 83337496 ps
CPU time 1.6 seconds
Started Jun 21 06:41:30 PM PDT 24
Finished Jun 21 06:42:40 PM PDT 24
Peak memory 214660 kb
Host smart-28c63285-89ec-4c03-9c99-9937e9e0ba00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164348809 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.4164348809
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1954272881
Short name T521
Test name
Test status
Simulation time 18403338931 ps
CPU time 456.39 seconds
Started Jun 21 06:41:30 PM PDT 24
Finished Jun 21 06:50:14 PM PDT 24
Peak memory 222932 kb
Host smart-cefe2d53-9740-4511-a67a-991fb17ad307
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954272881 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1954272881
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.906351910
Short name T739
Test name
Test status
Simulation time 69955433 ps
CPU time 1.06 seconds
Started Jun 21 06:44:21 PM PDT 24
Finished Jun 21 06:45:00 PM PDT 24
Peak memory 219172 kb
Host smart-f5e3113a-f9df-498a-a91d-cd65dab85116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906351910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.906351910
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.2390684864
Short name T626
Test name
Test status
Simulation time 27931218 ps
CPU time 0.94 seconds
Started Jun 21 06:44:22 PM PDT 24
Finished Jun 21 06:45:00 PM PDT 24
Peak memory 223236 kb
Host smart-b5228c1b-f537-46a2-8348-f4089bc28fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390684864 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2390684864
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3199773778
Short name T418
Test name
Test status
Simulation time 129470193 ps
CPU time 1.01 seconds
Started Jun 21 06:44:24 PM PDT 24
Finished Jun 21 06:45:02 PM PDT 24
Peak memory 216616 kb
Host smart-6aa84857-c6c5-40e1-b54b-07849ab5b4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199773778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3199773778
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.48880270
Short name T572
Test name
Test status
Simulation time 43534922 ps
CPU time 1.18 seconds
Started Jun 21 06:44:21 PM PDT 24
Finished Jun 21 06:45:00 PM PDT 24
Peak memory 220060 kb
Host smart-e16db83a-2581-4668-8593-7dacbd907561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48880270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.48880270
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.1236550415
Short name T527
Test name
Test status
Simulation time 21446600 ps
CPU time 0.91 seconds
Started Jun 21 06:44:22 PM PDT 24
Finished Jun 21 06:45:00 PM PDT 24
Peak memory 217744 kb
Host smart-12028fba-c200-4268-a0e7-2b91b651dce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236550415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1236550415
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1781399696
Short name T630
Test name
Test status
Simulation time 61942305 ps
CPU time 1.24 seconds
Started Jun 21 06:44:22 PM PDT 24
Finished Jun 21 06:45:00 PM PDT 24
Peak memory 214656 kb
Host smart-df979eb9-4e31-413d-8625-2bb8a1c3de8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781399696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1781399696
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.2214152663
Short name T559
Test name
Test status
Simulation time 49665986 ps
CPU time 1.21 seconds
Started Jun 21 06:44:20 PM PDT 24
Finished Jun 21 06:44:58 PM PDT 24
Peak memory 217992 kb
Host smart-1a41c123-61f4-44f8-a6c0-9362d1c6363a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214152663 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.2214152663
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.4215386494
Short name T117
Test name
Test status
Simulation time 49422930 ps
CPU time 1 seconds
Started Jun 21 06:44:20 PM PDT 24
Finished Jun 21 06:44:57 PM PDT 24
Peak memory 218800 kb
Host smart-497cf4af-4aa7-4d3a-8727-7e3d7591c049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215386494 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.4215386494
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.960658153
Short name T444
Test name
Test status
Simulation time 52455943 ps
CPU time 1.87 seconds
Started Jun 21 06:44:21 PM PDT 24
Finished Jun 21 06:45:01 PM PDT 24
Peak memory 217936 kb
Host smart-03a1b561-e446-46f0-a995-f7b2fe59b2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960658153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.960658153
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.1140690049
Short name T372
Test name
Test status
Simulation time 33087804 ps
CPU time 0.97 seconds
Started Jun 21 06:44:23 PM PDT 24
Finished Jun 21 06:45:00 PM PDT 24
Peak memory 218068 kb
Host smart-6b54fa30-307f-4ad7-9115-0f4a0d2cc2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140690049 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1140690049
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3525780596
Short name T371
Test name
Test status
Simulation time 42257690 ps
CPU time 1.52 seconds
Started Jun 21 06:44:23 PM PDT 24
Finished Jun 21 06:45:01 PM PDT 24
Peak memory 218076 kb
Host smart-4b1d0394-86f0-44b9-8043-2e24c142a679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525780596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3525780596
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1084160799
Short name T699
Test name
Test status
Simulation time 48594933 ps
CPU time 1.21 seconds
Started Jun 21 06:44:23 PM PDT 24
Finished Jun 21 06:45:01 PM PDT 24
Peak memory 217888 kb
Host smart-87399fcf-327e-4b06-8947-1fbdde9451d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084160799 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1084160799
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.3247735156
Short name T134
Test name
Test status
Simulation time 58421293 ps
CPU time 1.06 seconds
Started Jun 21 06:44:21 PM PDT 24
Finished Jun 21 06:45:00 PM PDT 24
Peak memory 218100 kb
Host smart-219524b2-5c26-4ffe-a724-2871c65dcecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247735156 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3247735156
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1581319313
Short name T554
Test name
Test status
Simulation time 27074139 ps
CPU time 1.09 seconds
Started Jun 21 06:44:23 PM PDT 24
Finished Jun 21 06:45:01 PM PDT 24
Peak memory 216600 kb
Host smart-d04f6c7b-3458-4ebe-8a18-f56149728a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581319313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1581319313
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.2745423692
Short name T945
Test name
Test status
Simulation time 44589999 ps
CPU time 1.18 seconds
Started Jun 21 06:44:33 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 218072 kb
Host smart-e0318e12-15a6-4a05-ae5c-3697c053adc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745423692 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.2745423692
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1259940440
Short name T218
Test name
Test status
Simulation time 20323610 ps
CPU time 1.27 seconds
Started Jun 21 06:44:33 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 229028 kb
Host smart-9f7c45be-e237-4d06-83eb-42a441f39e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259940440 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1259940440
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2675793351
Short name T39
Test name
Test status
Simulation time 67902150 ps
CPU time 1.55 seconds
Started Jun 21 06:44:30 PM PDT 24
Finished Jun 21 06:45:08 PM PDT 24
Peak memory 218188 kb
Host smart-de893aab-7b30-4103-9526-235db75c8087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675793351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2675793351
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.2661820577
Short name T113
Test name
Test status
Simulation time 203898428 ps
CPU time 1.27 seconds
Started Jun 21 06:44:30 PM PDT 24
Finished Jun 21 06:45:07 PM PDT 24
Peak memory 220264 kb
Host smart-32388d99-2795-462a-9696-d21328a029bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661820577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.2661820577
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.3641124227
Short name T123
Test name
Test status
Simulation time 26981691 ps
CPU time 1.01 seconds
Started Jun 21 06:44:35 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 219032 kb
Host smart-a1e6e892-a702-4870-8493-92c11aa1bec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641124227 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3641124227
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.566464099
Short name T731
Test name
Test status
Simulation time 55311501 ps
CPU time 1.6 seconds
Started Jun 21 06:44:32 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 217732 kb
Host smart-99c502ba-5a08-426d-868b-5b9a51693927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566464099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.566464099
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.3365385387
Short name T288
Test name
Test status
Simulation time 24054239 ps
CPU time 1.16 seconds
Started Jun 21 06:44:32 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 220016 kb
Host smart-d6056906-b51c-4a70-9aad-9c8c7b82d324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365385387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.3365385387
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.4264088189
Short name T977
Test name
Test status
Simulation time 33712113 ps
CPU time 0.95 seconds
Started Jun 21 06:44:32 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 217856 kb
Host smart-4c7911bb-f048-4448-839f-21ec1f7d81d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264088189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.4264088189
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.4294512706
Short name T690
Test name
Test status
Simulation time 29340662 ps
CPU time 1.25 seconds
Started Jun 21 06:44:31 PM PDT 24
Finished Jun 21 06:45:08 PM PDT 24
Peak memory 216896 kb
Host smart-962b7f01-ff13-45d3-9cf5-ce4fdecdc23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294512706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.4294512706
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.1951939812
Short name T143
Test name
Test status
Simulation time 52777397 ps
CPU time 1.2 seconds
Started Jun 21 06:44:31 PM PDT 24
Finished Jun 21 06:45:08 PM PDT 24
Peak memory 218004 kb
Host smart-5047f70e-e8a0-4173-93d9-5a6fb3cc3482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951939812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.1951939812
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.1041698525
Short name T606
Test name
Test status
Simulation time 23639767 ps
CPU time 1.17 seconds
Started Jun 21 06:44:33 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 217760 kb
Host smart-8a0ca358-e303-402c-8505-53936b833b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041698525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1041698525
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.4054912506
Short name T595
Test name
Test status
Simulation time 84464868 ps
CPU time 1.43 seconds
Started Jun 21 06:44:33 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 219200 kb
Host smart-9ab28f8e-2661-49be-9101-0ee35256864a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054912506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.4054912506
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.4103989264
Short name T225
Test name
Test status
Simulation time 23452479 ps
CPU time 1.14 seconds
Started Jun 21 06:44:34 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 218184 kb
Host smart-d775a18c-f10f-46a0-b6fd-af543b89c283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103989264 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.4103989264
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.3992166301
Short name T410
Test name
Test status
Simulation time 38385052 ps
CPU time 0.92 seconds
Started Jun 21 06:44:32 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 223240 kb
Host smart-6d23d020-acc2-4706-be96-53ae976ee9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992166301 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3992166301
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2080654376
Short name T835
Test name
Test status
Simulation time 148150495 ps
CPU time 1.04 seconds
Started Jun 21 06:44:32 PM PDT 24
Finished Jun 21 06:45:09 PM PDT 24
Peak memory 216724 kb
Host smart-a41a9b9e-af75-4a84-91b1-4336e734cd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080654376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2080654376
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%