Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.62 98.25 93.97 97.02 91.86 96.37 99.77 92.08


Total test records in report: 1129
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T1019 /workspace/coverage/cover_reg_top/2.edn_tl_errors.2337493372 Jun 22 04:53:30 PM PDT 24 Jun 22 04:53:32 PM PDT 24 26227329 ps
T270 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4120625240 Jun 22 04:53:56 PM PDT 24 Jun 22 04:54:00 PM PDT 24 581340213 ps
T1020 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1452111809 Jun 22 04:53:46 PM PDT 24 Jun 22 04:53:47 PM PDT 24 30322063 ps
T1021 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2758860239 Jun 22 04:53:30 PM PDT 24 Jun 22 04:53:32 PM PDT 24 61832411 ps
T1022 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3551266363 Jun 22 04:54:01 PM PDT 24 Jun 22 04:54:05 PM PDT 24 169856425 ps
T264 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3147781104 Jun 22 04:53:35 PM PDT 24 Jun 22 04:53:38 PM PDT 24 24861101 ps
T247 /workspace/coverage/cover_reg_top/8.edn_csr_rw.281918256 Jun 22 04:53:49 PM PDT 24 Jun 22 04:53:52 PM PDT 24 25812565 ps
T1023 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2807234535 Jun 22 04:53:27 PM PDT 24 Jun 22 04:53:30 PM PDT 24 370861256 ps
T1024 /workspace/coverage/cover_reg_top/20.edn_intr_test.3085846000 Jun 22 04:54:04 PM PDT 24 Jun 22 04:54:07 PM PDT 24 153472365 ps
T1025 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.214396762 Jun 22 04:54:01 PM PDT 24 Jun 22 04:54:03 PM PDT 24 268796397 ps
T1026 /workspace/coverage/cover_reg_top/43.edn_intr_test.2702497762 Jun 22 04:54:11 PM PDT 24 Jun 22 04:54:14 PM PDT 24 18179834 ps
T1027 /workspace/coverage/cover_reg_top/40.edn_intr_test.1398391058 Jun 22 04:54:11 PM PDT 24 Jun 22 04:54:13 PM PDT 24 58516725 ps
T1028 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2401580101 Jun 22 04:53:55 PM PDT 24 Jun 22 04:53:57 PM PDT 24 117662795 ps
T1029 /workspace/coverage/cover_reg_top/37.edn_intr_test.2795421981 Jun 22 04:54:09 PM PDT 24 Jun 22 04:54:11 PM PDT 24 24167094 ps
T1030 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3131082328 Jun 22 04:53:55 PM PDT 24 Jun 22 04:54:00 PM PDT 24 436154523 ps
T1031 /workspace/coverage/cover_reg_top/29.edn_intr_test.1764820622 Jun 22 04:54:02 PM PDT 24 Jun 22 04:54:04 PM PDT 24 16782813 ps
T274 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3667366860 Jun 22 04:53:31 PM PDT 24 Jun 22 04:53:34 PM PDT 24 152379010 ps
T1032 /workspace/coverage/cover_reg_top/28.edn_intr_test.2021265421 Jun 22 04:54:11 PM PDT 24 Jun 22 04:54:13 PM PDT 24 12539910 ps
T248 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2411048006 Jun 22 04:53:41 PM PDT 24 Jun 22 04:53:43 PM PDT 24 45200390 ps
T1033 /workspace/coverage/cover_reg_top/32.edn_intr_test.2256705167 Jun 22 04:54:01 PM PDT 24 Jun 22 04:54:04 PM PDT 24 18089037 ps
T249 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1649010412 Jun 22 04:53:41 PM PDT 24 Jun 22 04:53:42 PM PDT 24 28695638 ps
T1034 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2569539028 Jun 22 04:53:49 PM PDT 24 Jun 22 04:53:54 PM PDT 24 229712685 ps
T1035 /workspace/coverage/cover_reg_top/49.edn_intr_test.1692312470 Jun 22 04:54:10 PM PDT 24 Jun 22 04:54:11 PM PDT 24 21035621 ps
T1036 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2290874614 Jun 22 04:54:00 PM PDT 24 Jun 22 04:54:04 PM PDT 24 90081518 ps
T265 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1442015926 Jun 22 04:53:48 PM PDT 24 Jun 22 04:53:52 PM PDT 24 260005923 ps
T1037 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1402356501 Jun 22 04:53:50 PM PDT 24 Jun 22 04:53:53 PM PDT 24 128502920 ps
T1038 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.4079341002 Jun 22 04:53:47 PM PDT 24 Jun 22 04:53:50 PM PDT 24 81396136 ps
T1039 /workspace/coverage/cover_reg_top/44.edn_intr_test.1500772186 Jun 22 04:54:12 PM PDT 24 Jun 22 04:54:15 PM PDT 24 41878407 ps
T1040 /workspace/coverage/cover_reg_top/16.edn_csr_rw.758172448 Jun 22 04:53:56 PM PDT 24 Jun 22 04:53:58 PM PDT 24 126562784 ps
T1041 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1245935040 Jun 22 04:53:27 PM PDT 24 Jun 22 04:53:29 PM PDT 24 21638405 ps
T1042 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3839756441 Jun 22 04:53:48 PM PDT 24 Jun 22 04:53:53 PM PDT 24 121520583 ps
T1043 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3478933293 Jun 22 04:53:31 PM PDT 24 Jun 22 04:53:33 PM PDT 24 39403708 ps
T1044 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2243578268 Jun 22 04:53:57 PM PDT 24 Jun 22 04:54:00 PM PDT 24 57097185 ps
T1045 /workspace/coverage/cover_reg_top/22.edn_intr_test.3870075757 Jun 22 04:54:00 PM PDT 24 Jun 22 04:54:03 PM PDT 24 14505567 ps
T1046 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3470403021 Jun 22 04:53:33 PM PDT 24 Jun 22 04:53:37 PM PDT 24 809806948 ps
T1047 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2828918993 Jun 22 04:53:58 PM PDT 24 Jun 22 04:54:01 PM PDT 24 120290661 ps
T1048 /workspace/coverage/cover_reg_top/9.edn_tl_errors.4208492462 Jun 22 04:53:50 PM PDT 24 Jun 22 04:53:55 PM PDT 24 454752114 ps
T1049 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1708303996 Jun 22 04:53:49 PM PDT 24 Jun 22 04:53:52 PM PDT 24 66504640 ps
T1050 /workspace/coverage/cover_reg_top/10.edn_intr_test.1909202469 Jun 22 04:53:57 PM PDT 24 Jun 22 04:54:00 PM PDT 24 21984985 ps
T1051 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2715007096 Jun 22 04:54:01 PM PDT 24 Jun 22 04:54:07 PM PDT 24 141404757 ps
T1052 /workspace/coverage/cover_reg_top/3.edn_tl_errors.18608696 Jun 22 04:53:35 PM PDT 24 Jun 22 04:53:38 PM PDT 24 75644796 ps
T1053 /workspace/coverage/cover_reg_top/5.edn_intr_test.1772562229 Jun 22 04:53:46 PM PDT 24 Jun 22 04:53:48 PM PDT 24 51861719 ps
T1054 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.963338357 Jun 22 04:53:38 PM PDT 24 Jun 22 04:53:40 PM PDT 24 39047227 ps
T1055 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2715777187 Jun 22 04:54:03 PM PDT 24 Jun 22 04:54:06 PM PDT 24 30960355 ps
T1056 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2225183595 Jun 22 04:54:04 PM PDT 24 Jun 22 04:54:08 PM PDT 24 285352978 ps
T1057 /workspace/coverage/cover_reg_top/30.edn_intr_test.2647116705 Jun 22 04:54:03 PM PDT 24 Jun 22 04:54:05 PM PDT 24 49126529 ps
T250 /workspace/coverage/cover_reg_top/4.edn_csr_rw.404133609 Jun 22 04:53:43 PM PDT 24 Jun 22 04:53:45 PM PDT 24 22916863 ps
T1058 /workspace/coverage/cover_reg_top/46.edn_intr_test.736914401 Jun 22 04:54:10 PM PDT 24 Jun 22 04:54:13 PM PDT 24 38275173 ps
T1059 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.289928128 Jun 22 04:53:29 PM PDT 24 Jun 22 04:53:30 PM PDT 24 14092944 ps
T1060 /workspace/coverage/cover_reg_top/8.edn_intr_test.4085681075 Jun 22 04:53:48 PM PDT 24 Jun 22 04:53:51 PM PDT 24 30641111 ps
T1061 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.777831630 Jun 22 04:53:38 PM PDT 24 Jun 22 04:53:42 PM PDT 24 604841765 ps
T251 /workspace/coverage/cover_reg_top/15.edn_csr_rw.3758890210 Jun 22 04:53:54 PM PDT 24 Jun 22 04:53:56 PM PDT 24 14522149 ps
T1062 /workspace/coverage/cover_reg_top/14.edn_intr_test.4161154532 Jun 22 04:53:57 PM PDT 24 Jun 22 04:53:59 PM PDT 24 25737025 ps
T1063 /workspace/coverage/cover_reg_top/27.edn_intr_test.1188490841 Jun 22 04:54:11 PM PDT 24 Jun 22 04:54:15 PM PDT 24 18538915 ps
T1064 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1123210625 Jun 22 04:54:05 PM PDT 24 Jun 22 04:54:08 PM PDT 24 292046939 ps
T1065 /workspace/coverage/cover_reg_top/1.edn_intr_test.2722497256 Jun 22 04:53:35 PM PDT 24 Jun 22 04:53:37 PM PDT 24 15837657 ps
T1066 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2008122906 Jun 22 04:53:56 PM PDT 24 Jun 22 04:53:58 PM PDT 24 24574549 ps
T1067 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2628814828 Jun 22 04:54:02 PM PDT 24 Jun 22 04:54:05 PM PDT 24 26679454 ps
T252 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1954027076 Jun 22 04:54:05 PM PDT 24 Jun 22 04:54:07 PM PDT 24 35930572 ps
T1068 /workspace/coverage/cover_reg_top/16.edn_intr_test.3857213512 Jun 22 04:53:54 PM PDT 24 Jun 22 04:53:55 PM PDT 24 22881652 ps
T1069 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1828854253 Jun 22 04:54:11 PM PDT 24 Jun 22 04:54:15 PM PDT 24 56548549 ps
T1070 /workspace/coverage/cover_reg_top/48.edn_intr_test.3645735320 Jun 22 04:54:15 PM PDT 24 Jun 22 04:54:16 PM PDT 24 14261738 ps
T1071 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2996970535 Jun 22 04:53:54 PM PDT 24 Jun 22 04:53:56 PM PDT 24 77778836 ps
T1072 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1312331152 Jun 22 04:53:57 PM PDT 24 Jun 22 04:54:00 PM PDT 24 104699643 ps
T1073 /workspace/coverage/cover_reg_top/38.edn_intr_test.3928680029 Jun 22 04:54:09 PM PDT 24 Jun 22 04:54:11 PM PDT 24 17230097 ps
T1074 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1820947467 Jun 22 04:53:30 PM PDT 24 Jun 22 04:53:32 PM PDT 24 44668775 ps
T1075 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1945797468 Jun 22 04:54:03 PM PDT 24 Jun 22 04:54:05 PM PDT 24 305581735 ps
T1076 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.721382908 Jun 22 04:53:44 PM PDT 24 Jun 22 04:53:46 PM PDT 24 55749094 ps
T1077 /workspace/coverage/cover_reg_top/16.edn_tl_errors.642978229 Jun 22 04:53:54 PM PDT 24 Jun 22 04:53:56 PM PDT 24 65980225 ps
T1078 /workspace/coverage/cover_reg_top/17.edn_intr_test.3801170271 Jun 22 04:54:04 PM PDT 24 Jun 22 04:54:06 PM PDT 24 13121135 ps
T1079 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1628434424 Jun 22 04:53:40 PM PDT 24 Jun 22 04:53:42 PM PDT 24 64668004 ps
T1080 /workspace/coverage/cover_reg_top/6.edn_intr_test.781875547 Jun 22 04:53:42 PM PDT 24 Jun 22 04:53:43 PM PDT 24 43479742 ps
T1081 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4021428154 Jun 22 04:54:01 PM PDT 24 Jun 22 04:54:04 PM PDT 24 46940691 ps
T1082 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.692475942 Jun 22 04:53:34 PM PDT 24 Jun 22 04:53:36 PM PDT 24 231854995 ps
T1083 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2437283830 Jun 22 04:54:01 PM PDT 24 Jun 22 04:54:04 PM PDT 24 209164954 ps
T1084 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.149093042 Jun 22 04:53:53 PM PDT 24 Jun 22 04:53:54 PM PDT 24 22276343 ps
T1085 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1699257069 Jun 22 04:54:07 PM PDT 24 Jun 22 04:54:08 PM PDT 24 58684614 ps
T1086 /workspace/coverage/cover_reg_top/12.edn_intr_test.3250870638 Jun 22 04:53:56 PM PDT 24 Jun 22 04:53:57 PM PDT 24 40632492 ps
T1087 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.141813975 Jun 22 04:53:54 PM PDT 24 Jun 22 04:53:56 PM PDT 24 125222688 ps
T1088 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1057392173 Jun 22 04:53:49 PM PDT 24 Jun 22 04:53:52 PM PDT 24 73682785 ps
T256 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3312700049 Jun 22 04:53:28 PM PDT 24 Jun 22 04:53:35 PM PDT 24 905633395 ps
T253 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1367641458 Jun 22 04:53:47 PM PDT 24 Jun 22 04:53:49 PM PDT 24 149097409 ps
T1089 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1860908728 Jun 22 04:53:56 PM PDT 24 Jun 22 04:53:58 PM PDT 24 62513357 ps
T254 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2712791304 Jun 22 04:53:34 PM PDT 24 Jun 22 04:53:36 PM PDT 24 52335170 ps
T1090 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2002303813 Jun 22 04:53:54 PM PDT 24 Jun 22 04:53:58 PM PDT 24 1133057354 ps
T1091 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.532768273 Jun 22 04:54:02 PM PDT 24 Jun 22 04:54:05 PM PDT 24 273933052 ps
T1092 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1147967717 Jun 22 04:53:49 PM PDT 24 Jun 22 04:53:53 PM PDT 24 746809443 ps
T1093 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.706693205 Jun 22 04:54:48 PM PDT 24 Jun 22 04:54:50 PM PDT 24 104274522 ps
T255 /workspace/coverage/cover_reg_top/12.edn_csr_rw.568672336 Jun 22 04:54:00 PM PDT 24 Jun 22 04:54:02 PM PDT 24 46919363 ps
T1094 /workspace/coverage/cover_reg_top/21.edn_intr_test.898860980 Jun 22 04:54:01 PM PDT 24 Jun 22 04:54:03 PM PDT 24 16757916 ps
T273 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1265270071 Jun 22 04:53:29 PM PDT 24 Jun 22 04:53:31 PM PDT 24 538617873 ps
T1095 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3358333443 Jun 22 04:53:42 PM PDT 24 Jun 22 04:53:43 PM PDT 24 70504853 ps
T1096 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1804943326 Jun 22 04:53:49 PM PDT 24 Jun 22 04:53:52 PM PDT 24 18654426 ps
T259 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1796455450 Jun 22 04:53:48 PM PDT 24 Jun 22 04:53:50 PM PDT 24 43799583 ps
T1097 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2962473988 Jun 22 04:53:55 PM PDT 24 Jun 22 04:53:58 PM PDT 24 75078182 ps
T1098 /workspace/coverage/cover_reg_top/34.edn_intr_test.650857925 Jun 22 04:54:01 PM PDT 24 Jun 22 04:54:03 PM PDT 24 40609236 ps
T1099 /workspace/coverage/cover_reg_top/33.edn_intr_test.614515164 Jun 22 04:54:06 PM PDT 24 Jun 22 04:54:07 PM PDT 24 25937344 ps
T1100 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3687401339 Jun 22 04:53:51 PM PDT 24 Jun 22 04:53:54 PM PDT 24 28050732 ps
T1101 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.294318350 Jun 22 04:54:03 PM PDT 24 Jun 22 04:54:05 PM PDT 24 101217990 ps
T1102 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3527925605 Jun 22 04:53:41 PM PDT 24 Jun 22 04:53:44 PM PDT 24 55168410 ps
T1103 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2350772106 Jun 22 04:53:47 PM PDT 24 Jun 22 04:53:49 PM PDT 24 88897273 ps
T1104 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2206690804 Jun 22 04:53:56 PM PDT 24 Jun 22 04:53:58 PM PDT 24 57648300 ps
T1105 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2276726190 Jun 22 04:53:55 PM PDT 24 Jun 22 04:54:00 PM PDT 24 131713934 ps
T1106 /workspace/coverage/cover_reg_top/11.edn_intr_test.3560963394 Jun 22 04:53:54 PM PDT 24 Jun 22 04:53:56 PM PDT 24 60896763 ps
T1107 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2337782656 Jun 22 04:53:46 PM PDT 24 Jun 22 04:53:48 PM PDT 24 174468429 ps
T257 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3421187985 Jun 22 04:53:39 PM PDT 24 Jun 22 04:53:40 PM PDT 24 13653521 ps
T1108 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.54696961 Jun 22 04:53:55 PM PDT 24 Jun 22 04:53:59 PM PDT 24 122580833 ps
T1109 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1301085416 Jun 22 04:53:34 PM PDT 24 Jun 22 04:53:38 PM PDT 24 81694615 ps
T1110 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.498935653 Jun 22 04:53:38 PM PDT 24 Jun 22 04:53:39 PM PDT 24 105138436 ps
T1111 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.522394057 Jun 22 04:53:55 PM PDT 24 Jun 22 04:53:57 PM PDT 24 324404755 ps
T258 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3239021719 Jun 22 04:54:04 PM PDT 24 Jun 22 04:54:07 PM PDT 24 15046937 ps
T1112 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3322743601 Jun 22 04:53:38 PM PDT 24 Jun 22 04:53:41 PM PDT 24 53501189 ps
T1113 /workspace/coverage/cover_reg_top/18.edn_intr_test.298157472 Jun 22 04:54:03 PM PDT 24 Jun 22 04:54:06 PM PDT 24 39783012 ps
T1114 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.342559486 Jun 22 04:53:42 PM PDT 24 Jun 22 04:53:44 PM PDT 24 68475845 ps
T1115 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2319532473 Jun 22 04:53:54 PM PDT 24 Jun 22 04:53:55 PM PDT 24 24617588 ps
T1116 /workspace/coverage/cover_reg_top/3.edn_intr_test.1386152448 Jun 22 04:53:38 PM PDT 24 Jun 22 04:53:39 PM PDT 24 57979454 ps
T1117 /workspace/coverage/cover_reg_top/23.edn_intr_test.928147148 Jun 22 04:54:02 PM PDT 24 Jun 22 04:54:05 PM PDT 24 45666871 ps
T1118 /workspace/coverage/cover_reg_top/7.edn_intr_test.871993792 Jun 22 04:53:47 PM PDT 24 Jun 22 04:53:49 PM PDT 24 28423414 ps
T1119 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1852389267 Jun 22 04:53:56 PM PDT 24 Jun 22 04:53:58 PM PDT 24 24385961 ps
T1120 /workspace/coverage/cover_reg_top/24.edn_intr_test.1987540644 Jun 22 04:54:03 PM PDT 24 Jun 22 04:54:06 PM PDT 24 28231061 ps
T1121 /workspace/coverage/cover_reg_top/35.edn_intr_test.1231353430 Jun 22 04:54:11 PM PDT 24 Jun 22 04:54:14 PM PDT 24 11923407 ps
T1122 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.960059352 Jun 22 04:53:27 PM PDT 24 Jun 22 04:53:29 PM PDT 24 35189672 ps
T1123 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3632931958 Jun 22 04:53:55 PM PDT 24 Jun 22 04:53:57 PM PDT 24 111211747 ps
T1124 /workspace/coverage/cover_reg_top/9.edn_intr_test.2698162195 Jun 22 04:53:46 PM PDT 24 Jun 22 04:53:47 PM PDT 24 14006005 ps
T1125 /workspace/coverage/cover_reg_top/47.edn_intr_test.321744684 Jun 22 04:54:09 PM PDT 24 Jun 22 04:54:10 PM PDT 24 25613917 ps
T1126 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1234966219 Jun 22 04:53:35 PM PDT 24 Jun 22 04:53:37 PM PDT 24 90268146 ps
T1127 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.4111324779 Jun 22 04:53:56 PM PDT 24 Jun 22 04:53:58 PM PDT 24 40693689 ps
T1128 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.269625642 Jun 22 04:53:41 PM PDT 24 Jun 22 04:53:44 PM PDT 24 261168589 ps
T1129 /workspace/coverage/cover_reg_top/0.edn_intr_test.4254282242 Jun 22 04:53:30 PM PDT 24 Jun 22 04:53:32 PM PDT 24 29363406 ps

Test location /workspace/coverage/default/5.edn_genbits.577816534
Short name T13
Test name
Test status
Simulation time 35184888 ps
CPU time 1.44 seconds
Started Jun 22 06:19:25 PM PDT 24
Finished Jun 22 06:19:27 PM PDT 24
Peak memory 219440 kb
Host smart-12f87435-55aa-4f5c-87a8-e6849ac1fb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577816534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.577816534
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.100643576
Short name T26
Test name
Test status
Simulation time 44118211 ps
CPU time 1.22 seconds
Started Jun 22 06:23:25 PM PDT 24
Finished Jun 22 06:23:26 PM PDT 24
Peak memory 219080 kb
Host smart-dcb1ea99-59c6-4756-b408-56f8adc605c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100643576 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.100643576
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3907689132
Short name T39
Test name
Test status
Simulation time 14759490439 ps
CPU time 178.73 seconds
Started Jun 22 06:19:35 PM PDT 24
Finished Jun 22 06:22:34 PM PDT 24
Peak memory 216644 kb
Host smart-12b13238-b1f3-49b6-89d0-810cd996e10d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907689132 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3907689132
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_sec_cm.455242490
Short name T18
Test name
Test status
Simulation time 474997991 ps
CPU time 7.49 seconds
Started Jun 22 06:19:07 PM PDT 24
Finished Jun 22 06:19:15 PM PDT 24
Peak memory 235316 kb
Host smart-0649c221-d407-4995-b977-d82ccf4e1200
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455242490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.455242490
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/96.edn_genbits.295960052
Short name T25
Test name
Test status
Simulation time 63676939 ps
CPU time 2.57 seconds
Started Jun 22 06:23:00 PM PDT 24
Finished Jun 22 06:23:03 PM PDT 24
Peak memory 219684 kb
Host smart-625ecf82-7ec7-4399-b3c0-80e7e1a4f802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295960052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.295960052
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.825053246
Short name T8
Test name
Test status
Simulation time 54508888 ps
CPU time 1.15 seconds
Started Jun 22 06:22:23 PM PDT 24
Finished Jun 22 06:22:25 PM PDT 24
Peak memory 223400 kb
Host smart-749e5457-2081-4c8e-95df-8ad12fd38524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825053246 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.825053246
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/8.edn_stress_all.3165444480
Short name T6
Test name
Test status
Simulation time 887096830 ps
CPU time 5.27 seconds
Started Jun 22 06:19:42 PM PDT 24
Finished Jun 22 06:19:48 PM PDT 24
Peak memory 216624 kb
Host smart-80013e97-2a6c-448c-8463-ca219edc1fab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165444480 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3165444480
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_alert.18078190
Short name T47
Test name
Test status
Simulation time 54407171 ps
CPU time 1.3 seconds
Started Jun 22 06:22:07 PM PDT 24
Finished Jun 22 06:22:08 PM PDT 24
Peak memory 219832 kb
Host smart-e86ae8ad-5429-4a6d-ba97-a090c7475f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18078190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.18078190
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2262698625
Short name T21
Test name
Test status
Simulation time 43079484 ps
CPU time 1.09 seconds
Started Jun 22 06:19:16 PM PDT 24
Finished Jun 22 06:19:17 PM PDT 24
Peak memory 217828 kb
Host smart-af24a43f-4045-4384-ac11-12aee1a97c0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262698625 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2262698625
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_regwen.396168488
Short name T277
Test name
Test status
Simulation time 22322326 ps
CPU time 1.04 seconds
Started Jun 22 06:19:26 PM PDT 24
Finished Jun 22 06:19:27 PM PDT 24
Peak memory 206404 kb
Host smart-98bbb802-c8c5-42de-bd15-37d6263a7184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396168488 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.396168488
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_disable.234086645
Short name T1
Test name
Test status
Simulation time 62117419 ps
CPU time 0.9 seconds
Started Jun 22 06:19:42 PM PDT 24
Finished Jun 22 06:19:43 PM PDT 24
Peak memory 215888 kb
Host smart-f96295e7-d4dc-4773-a041-dbadcbc2e72e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234086645 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.234086645
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/138.edn_alert.929392147
Short name T42
Test name
Test status
Simulation time 85637055 ps
CPU time 1.1 seconds
Started Jun 22 06:23:20 PM PDT 24
Finished Jun 22 06:23:21 PM PDT 24
Peak memory 218028 kb
Host smart-1bb8abf2-935e-4ab8-a90f-7f6f9a1efa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929392147 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.929392147
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1215892875
Short name T145
Test name
Test status
Simulation time 49812162 ps
CPU time 1.1 seconds
Started Jun 22 06:19:38 PM PDT 24
Finished Jun 22 06:19:39 PM PDT 24
Peak memory 216524 kb
Host smart-0349996b-225a-4b9b-a81e-7ec812004f48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215892875 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1215892875
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/114.edn_alert.3425238646
Short name T76
Test name
Test status
Simulation time 94234002 ps
CPU time 1.17 seconds
Started Jun 22 06:23:00 PM PDT 24
Finished Jun 22 06:23:02 PM PDT 24
Peak memory 218032 kb
Host smart-d6e61024-f0bc-4a23-a20a-e4d86169c569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425238646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3425238646
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3667366860
Short name T274
Test name
Test status
Simulation time 152379010 ps
CPU time 2.26 seconds
Started Jun 22 04:53:31 PM PDT 24
Finished Jun 22 04:53:34 PM PDT 24
Peak memory 206420 kb
Host smart-099aba60-990e-47f1-b02d-1ebee4af7bb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667366860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3667366860
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3907517292
Short name T189
Test name
Test status
Simulation time 37219263 ps
CPU time 1.17 seconds
Started Jun 22 06:18:58 PM PDT 24
Finished Jun 22 06:18:59 PM PDT 24
Peak memory 218248 kb
Host smart-c07385db-f86b-4f46-b613-24eda17ed1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907517292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3907517292
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.281918256
Short name T247
Test name
Test status
Simulation time 25812565 ps
CPU time 0.9 seconds
Started Jun 22 04:53:49 PM PDT 24
Finished Jun 22 04:53:52 PM PDT 24
Peak memory 206292 kb
Host smart-6096d6d1-9fab-489d-aca4-f00c12b591f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281918256 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.281918256
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/default/31.edn_disable.4287981068
Short name T203
Test name
Test status
Simulation time 34814380 ps
CPU time 0.92 seconds
Started Jun 22 06:21:17 PM PDT 24
Finished Jun 22 06:21:19 PM PDT 24
Peak memory 215688 kb
Host smart-42b46313-ba66-4bf6-97fd-55f870b1b9d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287981068 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.4287981068
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable.1839898248
Short name T173
Test name
Test status
Simulation time 14643994 ps
CPU time 0.87 seconds
Started Jun 22 06:22:00 PM PDT 24
Finished Jun 22 06:22:01 PM PDT 24
Peak memory 215688 kb
Host smart-d84b4241-608e-4ff8-81d8-873360bb2327
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839898248 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1839898248
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable.1904297282
Short name T82
Test name
Test status
Simulation time 15997511 ps
CPU time 0.9 seconds
Started Jun 22 06:21:37 PM PDT 24
Finished Jun 22 06:21:38 PM PDT 24
Peak memory 215688 kb
Host smart-bcc6f180-2dd7-49a9-8a9d-a0d546666b4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904297282 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1904297282
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1798782531
Short name T122
Test name
Test status
Simulation time 48304318 ps
CPU time 1.14 seconds
Started Jun 22 06:18:57 PM PDT 24
Finished Jun 22 06:18:59 PM PDT 24
Peak memory 216308 kb
Host smart-92ba2e39-d340-4110-aa5f-c466c74f2b35
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798782531 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1798782531
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_alert.3031245492
Short name T85
Test name
Test status
Simulation time 26126536 ps
CPU time 1.14 seconds
Started Jun 22 06:20:55 PM PDT 24
Finished Jun 22 06:20:57 PM PDT 24
Peak memory 219136 kb
Host smart-338e684b-faca-470f-a2ce-43de7aa93cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031245492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3031245492
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/185.edn_alert.1037138163
Short name T112
Test name
Test status
Simulation time 54448179 ps
CPU time 1.28 seconds
Started Jun 22 06:23:43 PM PDT 24
Finished Jun 22 06:23:45 PM PDT 24
Peak memory 219304 kb
Host smart-6f19e160-4192-4ef7-84e1-f524fb9c7360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037138163 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.1037138163
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1695350772
Short name T290
Test name
Test status
Simulation time 70273285 ps
CPU time 1.49 seconds
Started Jun 22 06:23:40 PM PDT 24
Finished Jun 22 06:23:42 PM PDT 24
Peak memory 219548 kb
Host smart-cca4ef57-ef4a-4fd4-b202-ad529c635584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695350772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1695350772
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.952559623
Short name T220
Test name
Test status
Simulation time 74630450989 ps
CPU time 1731.46 seconds
Started Jun 22 06:21:11 PM PDT 24
Finished Jun 22 06:50:03 PM PDT 24
Peak memory 223468 kb
Host smart-6843497f-6058-45f4-a2fb-bca4063f1b42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952559623 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.952559623
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2625313761
Short name T380
Test name
Test status
Simulation time 77361733 ps
CPU time 1.14 seconds
Started Jun 22 06:21:26 PM PDT 24
Finished Jun 22 06:21:27 PM PDT 24
Peak memory 219016 kb
Host smart-dc154f8e-93bb-49a8-9bbd-6db2fb904e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625313761 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2625313761
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/39.edn_intr.3650687266
Short name T32
Test name
Test status
Simulation time 21656783 ps
CPU time 1.12 seconds
Started Jun 22 06:21:39 PM PDT 24
Finished Jun 22 06:21:41 PM PDT 24
Peak memory 215136 kb
Host smart-476ddeb3-3c42-4321-acde-c1a450be53a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650687266 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3650687266
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/122.edn_alert.560664701
Short name T158
Test name
Test status
Simulation time 165890329 ps
CPU time 1.22 seconds
Started Jun 22 06:23:08 PM PDT 24
Finished Jun 22 06:23:09 PM PDT 24
Peak memory 221120 kb
Host smart-7a047a8f-dcae-42bb-8861-460c76140e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560664701 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.560664701
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert.4235931908
Short name T438
Test name
Test status
Simulation time 83036808 ps
CPU time 1.11 seconds
Started Jun 22 06:19:57 PM PDT 24
Finished Jun 22 06:19:58 PM PDT 24
Peak memory 219120 kb
Host smart-e10dc9fa-699f-458a-bf22-d6a7c9fa68da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235931908 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.4235931908
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/102.edn_alert.2620699900
Short name T62
Test name
Test status
Simulation time 38951908 ps
CPU time 1.21 seconds
Started Jun 22 06:23:02 PM PDT 24
Finished Jun 22 06:23:04 PM PDT 24
Peak memory 220064 kb
Host smart-3ee1e68e-6ae6-42a7-90b1-e2f7c445ed4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620699900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.2620699900
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/103.edn_alert.1762361871
Short name T511
Test name
Test status
Simulation time 88862510 ps
CPU time 1.16 seconds
Started Jun 22 06:23:08 PM PDT 24
Finished Jun 22 06:23:09 PM PDT 24
Peak memory 219336 kb
Host smart-82a5aa07-c4cc-417c-8a72-29fba1a123c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762361871 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1762361871
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/108.edn_alert.664998638
Short name T134
Test name
Test status
Simulation time 29810938 ps
CPU time 1.33 seconds
Started Jun 22 06:23:04 PM PDT 24
Finished Jun 22 06:23:06 PM PDT 24
Peak memory 219340 kb
Host smart-250207d1-9dfd-46fd-8750-9c1cd1ba0ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664998638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.664998638
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/141.edn_alert.1266152963
Short name T279
Test name
Test status
Simulation time 40121315 ps
CPU time 1.1 seconds
Started Jun 22 06:23:22 PM PDT 24
Finished Jun 22 06:23:23 PM PDT 24
Peak memory 218040 kb
Host smart-25e2e51c-3b83-4e94-acae-e735ee5e4f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266152963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.1266152963
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/93.edn_alert.3644133311
Short name T124
Test name
Test status
Simulation time 145483396 ps
CPU time 1.16 seconds
Started Jun 22 06:22:54 PM PDT 24
Finished Jun 22 06:22:56 PM PDT 24
Peak memory 217856 kb
Host smart-4383c69c-4d50-415d-b075-d33fee779bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644133311 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.3644133311
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/41.edn_genbits.3347582236
Short name T88
Test name
Test status
Simulation time 77414297 ps
CPU time 1.38 seconds
Started Jun 22 06:21:46 PM PDT 24
Finished Jun 22 06:21:48 PM PDT 24
Peak memory 217932 kb
Host smart-2aea6e89-c9ae-40f7-baa1-d860cb2bb77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347582236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3347582236
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_genbits.2932561194
Short name T305
Test name
Test status
Simulation time 93621969 ps
CPU time 1.13 seconds
Started Jun 22 06:21:32 PM PDT 24
Finished Jun 22 06:21:34 PM PDT 24
Peak memory 216612 kb
Host smart-12807053-827a-4e3e-932c-4b08c29f5d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932561194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2932561194
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.14076395
Short name T127
Test name
Test status
Simulation time 109789356 ps
CPU time 1.26 seconds
Started Jun 22 06:20:48 PM PDT 24
Finished Jun 22 06:20:50 PM PDT 24
Peak memory 216152 kb
Host smart-eb30c784-5175-4b28-a2fb-89c2d2432609
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14076395 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_dis
able_auto_req_mode.14076395
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_disable.3070540482
Short name T156
Test name
Test status
Simulation time 13407225 ps
CPU time 0.91 seconds
Started Jun 22 06:22:07 PM PDT 24
Finished Jun 22 06:22:09 PM PDT 24
Peak memory 214996 kb
Host smart-60a442d1-eb22-4541-976a-463974aa2b3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070540482 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3070540482
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/0.edn_intr.387224522
Short name T99
Test name
Test status
Simulation time 33290943 ps
CPU time 0.86 seconds
Started Jun 22 06:18:53 PM PDT 24
Finished Jun 22 06:18:54 PM PDT 24
Peak memory 214828 kb
Host smart-7f236f5d-eb6a-4e05-bc86-54f26656f9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387224522 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.387224522
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_err.1647902135
Short name T190
Test name
Test status
Simulation time 26877661 ps
CPU time 0.99 seconds
Started Jun 22 06:18:51 PM PDT 24
Finished Jun 22 06:18:53 PM PDT 24
Peak memory 228812 kb
Host smart-9d1bee5f-6061-4072-8622-08a227937af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647902135 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1647902135
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3063672209
Short name T754
Test name
Test status
Simulation time 70414159 ps
CPU time 1.3 seconds
Started Jun 22 06:20:13 PM PDT 24
Finished Jun 22 06:20:15 PM PDT 24
Peak memory 216232 kb
Host smart-f7578a35-aa42-44f1-b243-6ea54da22e19
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063672209 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3063672209
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/171.edn_alert.778119441
Short name T131
Test name
Test status
Simulation time 52344408 ps
CPU time 1.26 seconds
Started Jun 22 06:23:37 PM PDT 24
Finished Jun 22 06:23:40 PM PDT 24
Peak memory 218072 kb
Host smart-7291ebb6-421a-48bb-a469-4800f75e9207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778119441 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.778119441
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/24.edn_disable.1310614456
Short name T211
Test name
Test status
Simulation time 17544758 ps
CPU time 0.84 seconds
Started Jun 22 06:20:55 PM PDT 24
Finished Jun 22 06:20:56 PM PDT 24
Peak memory 215696 kb
Host smart-21102dfe-6d58-4540-bcb8-ae718bbf5302
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310614456 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1310614456
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable.3201042285
Short name T184
Test name
Test status
Simulation time 11887470 ps
CPU time 0.89 seconds
Started Jun 22 06:20:56 PM PDT 24
Finished Jun 22 06:20:57 PM PDT 24
Peak memory 215744 kb
Host smart-40e78460-8c18-4343-8379-0a381a84245c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201042285 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3201042285
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.2650346862
Short name T181
Test name
Test status
Simulation time 19439446 ps
CPU time 1.08 seconds
Started Jun 22 06:21:11 PM PDT 24
Finished Jun 22 06:21:13 PM PDT 24
Peak memory 217864 kb
Host smart-0a9bc2be-8b11-4658-87da-17421cec1d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650346862 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2650346862
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/30.edn_disable.1529894351
Short name T206
Test name
Test status
Simulation time 12079022 ps
CPU time 1.05 seconds
Started Jun 22 06:21:16 PM PDT 24
Finished Jun 22 06:21:17 PM PDT 24
Peak memory 215952 kb
Host smart-31ba21ee-9b1a-4e49-a706-ffcd637f251d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529894351 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1529894351
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable.1972951169
Short name T198
Test name
Test status
Simulation time 40188881 ps
CPU time 0.79 seconds
Started Jun 22 06:21:33 PM PDT 24
Finished Jun 22 06:21:34 PM PDT 24
Peak memory 215752 kb
Host smart-2889c2b7-d924-42fd-9249-b002d710a9d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972951169 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1972951169
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable.99399414
Short name T87
Test name
Test status
Simulation time 21058649 ps
CPU time 0.88 seconds
Started Jun 22 06:21:32 PM PDT 24
Finished Jun 22 06:21:34 PM PDT 24
Peak memory 215680 kb
Host smart-92f846be-88ce-4706-ae54-bf29afc0c64c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99399414 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.99399414
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/10.edn_alert_test.1809952267
Short name T336
Test name
Test status
Simulation time 32328563 ps
CPU time 0.92 seconds
Started Jun 22 06:20:05 PM PDT 24
Finished Jun 22 06:20:07 PM PDT 24
Peak memory 206124 kb
Host smart-3b68594a-4612-4890-96aa-e6995a1ed4b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809952267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1809952267
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/101.edn_genbits.3738876021
Short name T631
Test name
Test status
Simulation time 41734437 ps
CPU time 1.57 seconds
Started Jun 22 06:23:03 PM PDT 24
Finished Jun 22 06:23:05 PM PDT 24
Peak memory 217728 kb
Host smart-d05fbc10-45c0-4f36-b959-1147b9ec05c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738876021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3738876021
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.576294802
Short name T303
Test name
Test status
Simulation time 229061466 ps
CPU time 3.48 seconds
Started Jun 22 06:23:06 PM PDT 24
Finished Jun 22 06:23:10 PM PDT 24
Peak memory 216752 kb
Host smart-a3c202d1-1007-46fe-a2e1-10ab2143ddd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576294802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.576294802
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_genbits.2707024216
Short name T297
Test name
Test status
Simulation time 51934164 ps
CPU time 1.9 seconds
Started Jun 22 06:20:06 PM PDT 24
Finished Jun 22 06:20:08 PM PDT 24
Peak memory 216828 kb
Host smart-32f3c949-9ef6-404d-b587-6aad22db9a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707024216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2707024216
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3550631688
Short name T283
Test name
Test status
Simulation time 61592937 ps
CPU time 1.35 seconds
Started Jun 22 06:23:16 PM PDT 24
Finished Jun 22 06:23:17 PM PDT 24
Peak memory 218248 kb
Host smart-fa42368e-a4f1-4a3a-8528-6e417efdcbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550631688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3550631688
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1174777695
Short name T5
Test name
Test status
Simulation time 34003879 ps
CPU time 0.95 seconds
Started Jun 22 06:20:14 PM PDT 24
Finished Jun 22 06:20:16 PM PDT 24
Peak memory 214896 kb
Host smart-42fc7b3e-bb80-49f3-866b-d7af563be4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174777695 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1174777695
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/10.edn_intr.3192277879
Short name T335
Test name
Test status
Simulation time 23612589 ps
CPU time 1.02 seconds
Started Jun 22 06:19:58 PM PDT 24
Finished Jun 22 06:19:59 PM PDT 24
Peak memory 214980 kb
Host smart-72fb929d-31b5-4f7b-b21a-6d592fd852ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192277879 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3192277879
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1265270071
Short name T273
Test name
Test status
Simulation time 538617873 ps
CPU time 1.59 seconds
Started Jun 22 04:53:29 PM PDT 24
Finished Jun 22 04:53:31 PM PDT 24
Peak memory 206412 kb
Host smart-0252f824-ceec-4e4b-a407-d2583feebc76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265270071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1265270071
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_stress_all.123585082
Short name T450
Test name
Test status
Simulation time 49231377 ps
CPU time 1.57 seconds
Started Jun 22 06:18:53 PM PDT 24
Finished Jun 22 06:18:55 PM PDT 24
Peak memory 214648 kb
Host smart-f45ba119-fedd-4b5c-8109-58909ad08832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123585082 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.123585082
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1362831645
Short name T892
Test name
Test status
Simulation time 56780783949 ps
CPU time 1259.35 seconds
Started Jun 22 06:20:08 PM PDT 24
Finished Jun 22 06:41:08 PM PDT 24
Peak memory 219724 kb
Host smart-ede6a18b-8e7f-42a6-9d6b-66dcff3f27f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362831645 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1362831645
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/125.edn_alert.491902100
Short name T152
Test name
Test status
Simulation time 31790619 ps
CPU time 1.31 seconds
Started Jun 22 06:23:10 PM PDT 24
Finished Jun 22 06:23:11 PM PDT 24
Peak memory 218080 kb
Host smart-609e40a0-22ae-4961-a42c-03d01a752c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491902100 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.491902100
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/13.edn_stress_all.1025885466
Short name T630
Test name
Test status
Simulation time 296019257 ps
CPU time 5.74 seconds
Started Jun 22 06:20:05 PM PDT 24
Finished Jun 22 06:20:11 PM PDT 24
Peak memory 215104 kb
Host smart-6afb9608-4968-4a7a-941c-c8d199cd7216
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025885466 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1025885466
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/136.edn_genbits.2496429543
Short name T325
Test name
Test status
Simulation time 39787579 ps
CPU time 1.39 seconds
Started Jun 22 06:23:14 PM PDT 24
Finished Jun 22 06:23:16 PM PDT 24
Peak memory 216548 kb
Host smart-f038aa63-f7d3-4ca6-a9e1-98516aca5bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496429543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2496429543
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.2961627859
Short name T84
Test name
Test status
Simulation time 46418105 ps
CPU time 1.39 seconds
Started Jun 22 06:23:30 PM PDT 24
Finished Jun 22 06:23:32 PM PDT 24
Peak memory 218136 kb
Host smart-75652737-9676-4c55-8dd8-f9a9c6dd3b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961627859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2961627859
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.639346167
Short name T309
Test name
Test status
Simulation time 356680511 ps
CPU time 4.03 seconds
Started Jun 22 06:23:41 PM PDT 24
Finished Jun 22 06:23:46 PM PDT 24
Peak memory 216960 kb
Host smart-585a6790-e6c4-4b15-abd2-83de6322adda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639346167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.639346167
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1620705589
Short name T300
Test name
Test status
Simulation time 71165398 ps
CPU time 1.37 seconds
Started Jun 22 06:23:54 PM PDT 24
Finished Jun 22 06:23:56 PM PDT 24
Peak memory 218884 kb
Host smart-8781d07c-d6da-45f4-83e0-ab917c267220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620705589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1620705589
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3421150679
Short name T307
Test name
Test status
Simulation time 84304846 ps
CPU time 1.38 seconds
Started Jun 22 06:23:50 PM PDT 24
Finished Jun 22 06:23:52 PM PDT 24
Peak memory 218040 kb
Host smart-3b241e46-cc36-4190-b18c-88c6673f4d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421150679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3421150679
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_genbits.4156095381
Short name T313
Test name
Test status
Simulation time 42363473 ps
CPU time 1.68 seconds
Started Jun 22 06:22:16 PM PDT 24
Finished Jun 22 06:22:18 PM PDT 24
Peak memory 218060 kb
Host smart-557e54cb-d7c7-4841-b363-fc43ee76aa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156095381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.4156095381
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.3071254092
Short name T38
Test name
Test status
Simulation time 28171969 ps
CPU time 0.87 seconds
Started Jun 22 06:20:06 PM PDT 24
Finished Jun 22 06:20:07 PM PDT 24
Peak memory 214992 kb
Host smart-da85105d-16b6-4470-964f-1599caf472ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071254092 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3071254092
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/156.edn_alert.1021165371
Short name T481
Test name
Test status
Simulation time 79206407 ps
CPU time 1.18 seconds
Started Jun 22 06:23:32 PM PDT 24
Finished Jun 22 06:23:34 PM PDT 24
Peak memory 218064 kb
Host smart-c95ac03d-d8de-48eb-bdef-cfd852b99914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021165371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.1021165371
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert.1510281000
Short name T117
Test name
Test status
Simulation time 28193097 ps
CPU time 1.29 seconds
Started Jun 22 06:20:47 PM PDT 24
Finished Jun 22 06:20:50 PM PDT 24
Peak memory 219868 kb
Host smart-25faa375-ec9d-4ed8-b1f0-eb1f543c0d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510281000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1510281000
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.2283602778
Short name T519
Test name
Test status
Simulation time 100458661 ps
CPU time 1.25 seconds
Started Jun 22 06:23:02 PM PDT 24
Finished Jun 22 06:23:04 PM PDT 24
Peak memory 218752 kb
Host smart-31eeb6b1-855c-48d9-8e46-ffcbf5f7344a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283602778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2283602778
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3293914938
Short name T949
Test name
Test status
Simulation time 128458031 ps
CPU time 1.56 seconds
Started Jun 22 06:24:15 PM PDT 24
Finished Jun 22 06:24:17 PM PDT 24
Peak memory 219180 kb
Host smart-a45096ae-3d9c-4cec-be12-78425a33089b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293914938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3293914938
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.960059352
Short name T1122
Test name
Test status
Simulation time 35189672 ps
CPU time 1.27 seconds
Started Jun 22 04:53:27 PM PDT 24
Finished Jun 22 04:53:29 PM PDT 24
Peak memory 206372 kb
Host smart-fcef4900-3b31-4988-91fc-a01f65354cd0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960059352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.960059352
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3312700049
Short name T256
Test name
Test status
Simulation time 905633395 ps
CPU time 6.28 seconds
Started Jun 22 04:53:28 PM PDT 24
Finished Jun 22 04:53:35 PM PDT 24
Peak memory 206360 kb
Host smart-6e3b52bb-3243-4d26-95d9-67a3268ed7eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312700049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3312700049
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.289928128
Short name T1059
Test name
Test status
Simulation time 14092944 ps
CPU time 0.93 seconds
Started Jun 22 04:53:29 PM PDT 24
Finished Jun 22 04:53:30 PM PDT 24
Peak memory 206356 kb
Host smart-ae888ce7-b24f-45ed-8a50-d52771072019
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289928128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.289928128
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2758860239
Short name T1021
Test name
Test status
Simulation time 61832411 ps
CPU time 1.31 seconds
Started Jun 22 04:53:30 PM PDT 24
Finished Jun 22 04:53:32 PM PDT 24
Peak memory 214688 kb
Host smart-d401486f-5504-4498-b6c6-5e1ea0ce1f90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758860239 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2758860239
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3881460569
Short name T1007
Test name
Test status
Simulation time 42336177 ps
CPU time 0.85 seconds
Started Jun 22 04:53:27 PM PDT 24
Finished Jun 22 04:53:29 PM PDT 24
Peak memory 206088 kb
Host smart-3942c125-feb5-45b7-a0d5-5d9674e7078a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881460569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3881460569
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.4254282242
Short name T1129
Test name
Test status
Simulation time 29363406 ps
CPU time 0.86 seconds
Started Jun 22 04:53:30 PM PDT 24
Finished Jun 22 04:53:32 PM PDT 24
Peak memory 206268 kb
Host smart-d3880f50-209e-4d04-a722-f0866c3cf2ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254282242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.4254282242
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1245935040
Short name T1041
Test name
Test status
Simulation time 21638405 ps
CPU time 1.25 seconds
Started Jun 22 04:53:27 PM PDT 24
Finished Jun 22 04:53:29 PM PDT 24
Peak memory 206424 kb
Host smart-4c7faebf-c4b9-4b8c-b6ea-547075742ad5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245935040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1245935040
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2807234535
Short name T1023
Test name
Test status
Simulation time 370861256 ps
CPU time 2.09 seconds
Started Jun 22 04:53:27 PM PDT 24
Finished Jun 22 04:53:30 PM PDT 24
Peak memory 214644 kb
Host smart-5dd92afb-de95-4be5-8e3c-c899885907ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807234535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2807234535
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.692475942
Short name T1082
Test name
Test status
Simulation time 231854995 ps
CPU time 1.24 seconds
Started Jun 22 04:53:34 PM PDT 24
Finished Jun 22 04:53:36 PM PDT 24
Peak memory 206352 kb
Host smart-6df2f7e2-cc01-4c6a-aa2e-e8827a8d873e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692475942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.692475942
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.481424172
Short name T1003
Test name
Test status
Simulation time 188753087 ps
CPU time 3.14 seconds
Started Jun 22 04:53:36 PM PDT 24
Finished Jun 22 04:53:40 PM PDT 24
Peak memory 206316 kb
Host smart-4df03bf5-becb-4941-8812-0122f2a559aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481424172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.481424172
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3478933293
Short name T1043
Test name
Test status
Simulation time 39403708 ps
CPU time 0.84 seconds
Started Jun 22 04:53:31 PM PDT 24
Finished Jun 22 04:53:33 PM PDT 24
Peak memory 206260 kb
Host smart-06cf9353-7a2b-47dd-ab1a-d6932cbce11b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478933293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3478933293
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.22467292
Short name T1016
Test name
Test status
Simulation time 71259295 ps
CPU time 1.19 seconds
Started Jun 22 04:53:39 PM PDT 24
Finished Jun 22 04:53:41 PM PDT 24
Peak memory 214688 kb
Host smart-b9783d5f-a311-416f-ae30-ffe8fd477a7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22467292 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.22467292
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3826376970
Short name T246
Test name
Test status
Simulation time 25007464 ps
CPU time 0.9 seconds
Started Jun 22 04:53:31 PM PDT 24
Finished Jun 22 04:53:33 PM PDT 24
Peak memory 206184 kb
Host smart-83b65a60-90ba-4750-b7fd-64e798a4d43a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826376970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3826376970
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2722497256
Short name T1065
Test name
Test status
Simulation time 15837657 ps
CPU time 0.86 seconds
Started Jun 22 04:53:35 PM PDT 24
Finished Jun 22 04:53:37 PM PDT 24
Peak memory 206360 kb
Host smart-5a9d48a9-f82a-48e0-ae79-4130e62e17be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722497256 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2722497256
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1820947467
Short name T1074
Test name
Test status
Simulation time 44668775 ps
CPU time 1.12 seconds
Started Jun 22 04:53:30 PM PDT 24
Finished Jun 22 04:53:32 PM PDT 24
Peak memory 206420 kb
Host smart-ea0548c9-3492-4dee-ad3c-eb9638116c3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820947467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1820947467
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1301085416
Short name T1109
Test name
Test status
Simulation time 81694615 ps
CPU time 2.76 seconds
Started Jun 22 04:53:34 PM PDT 24
Finished Jun 22 04:53:38 PM PDT 24
Peak memory 214696 kb
Host smart-8efe6694-e138-4f6a-adc9-d4c1ac9374a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301085416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1301085416
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2255115685
Short name T1008
Test name
Test status
Simulation time 18960811 ps
CPU time 1.08 seconds
Started Jun 22 04:53:54 PM PDT 24
Finished Jun 22 04:53:56 PM PDT 24
Peak memory 214636 kb
Host smart-c0e3f8f7-80d8-4647-9745-4c902a0cca2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255115685 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2255115685
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3810625940
Short name T260
Test name
Test status
Simulation time 46725281 ps
CPU time 0.94 seconds
Started Jun 22 04:54:00 PM PDT 24
Finished Jun 22 04:54:02 PM PDT 24
Peak memory 206352 kb
Host smart-15bbe376-44bf-4a74-82e7-1adcafc4e8f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810625940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3810625940
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1909202469
Short name T1050
Test name
Test status
Simulation time 21984985 ps
CPU time 0.86 seconds
Started Jun 22 04:53:57 PM PDT 24
Finished Jun 22 04:54:00 PM PDT 24
Peak memory 206176 kb
Host smart-f51e77d0-10d3-4601-9ef6-4c01f434346d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909202469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1909202469
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2779227012
Short name T245
Test name
Test status
Simulation time 30795748 ps
CPU time 1.36 seconds
Started Jun 22 04:54:00 PM PDT 24
Finished Jun 22 04:54:03 PM PDT 24
Peak memory 206336 kb
Host smart-6e6484fb-06e6-4ee8-bf97-a23b7204a4c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779227012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2779227012
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2276726190
Short name T1105
Test name
Test status
Simulation time 131713934 ps
CPU time 4.09 seconds
Started Jun 22 04:53:55 PM PDT 24
Finished Jun 22 04:54:00 PM PDT 24
Peak memory 214712 kb
Host smart-023e1277-68ce-4a0e-95ac-5a72c15c8a1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276726190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2276726190
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2437283830
Short name T1083
Test name
Test status
Simulation time 209164954 ps
CPU time 1.53 seconds
Started Jun 22 04:54:01 PM PDT 24
Finished Jun 22 04:54:04 PM PDT 24
Peak memory 206060 kb
Host smart-aca78456-1c84-43f3-b6f1-8d27e8a9331b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437283830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2437283830
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2996970535
Short name T1071
Test name
Test status
Simulation time 77778836 ps
CPU time 1.55 seconds
Started Jun 22 04:53:54 PM PDT 24
Finished Jun 22 04:53:56 PM PDT 24
Peak memory 214732 kb
Host smart-b74fad5d-6e32-474c-9a81-7285f61f33d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996970535 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2996970535
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2319532473
Short name T1115
Test name
Test status
Simulation time 24617588 ps
CPU time 0.88 seconds
Started Jun 22 04:53:54 PM PDT 24
Finished Jun 22 04:53:55 PM PDT 24
Peak memory 206348 kb
Host smart-f6a95d7c-b452-45f6-9f9e-a03c296a7a29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319532473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2319532473
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3560963394
Short name T1106
Test name
Test status
Simulation time 60896763 ps
CPU time 0.94 seconds
Started Jun 22 04:53:54 PM PDT 24
Finished Jun 22 04:53:56 PM PDT 24
Peak memory 206360 kb
Host smart-32af72c6-9374-410d-babc-d5fbe8ce1ea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560963394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3560963394
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2206690804
Short name T1104
Test name
Test status
Simulation time 57648300 ps
CPU time 1.09 seconds
Started Jun 22 04:53:56 PM PDT 24
Finished Jun 22 04:53:58 PM PDT 24
Peak memory 206372 kb
Host smart-aa43bcf4-a2aa-416d-ba9e-e8b432f2d0ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206690804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2206690804
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2290874614
Short name T1036
Test name
Test status
Simulation time 90081518 ps
CPU time 3.16 seconds
Started Jun 22 04:54:00 PM PDT 24
Finished Jun 22 04:54:04 PM PDT 24
Peak memory 214692 kb
Host smart-96ac583e-e442-471a-b95c-d86d82c4c739
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290874614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2290874614
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1312331152
Short name T1072
Test name
Test status
Simulation time 104699643 ps
CPU time 2.48 seconds
Started Jun 22 04:53:57 PM PDT 24
Finished Jun 22 04:54:00 PM PDT 24
Peak memory 214644 kb
Host smart-bc6ebe06-8cae-485c-8a0f-9e61117d198b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312331152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1312331152
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.4111324779
Short name T1127
Test name
Test status
Simulation time 40693689 ps
CPU time 1.4 seconds
Started Jun 22 04:53:56 PM PDT 24
Finished Jun 22 04:53:58 PM PDT 24
Peak memory 214568 kb
Host smart-8418e8c2-9790-4aeb-b23e-9f97e8b9882e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111324779 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.4111324779
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.568672336
Short name T255
Test name
Test status
Simulation time 46919363 ps
CPU time 0.9 seconds
Started Jun 22 04:54:00 PM PDT 24
Finished Jun 22 04:54:02 PM PDT 24
Peak memory 206348 kb
Host smart-181539b3-be33-4e23-8a4c-f93af57db255
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568672336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.568672336
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3250870638
Short name T1086
Test name
Test status
Simulation time 40632492 ps
CPU time 0.82 seconds
Started Jun 22 04:53:56 PM PDT 24
Finished Jun 22 04:53:57 PM PDT 24
Peak memory 206268 kb
Host smart-8d034375-aeef-4eac-97aa-f82ff47f9a1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250870638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3250870638
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3632931958
Short name T1123
Test name
Test status
Simulation time 111211747 ps
CPU time 1.34 seconds
Started Jun 22 04:53:55 PM PDT 24
Finished Jun 22 04:53:57 PM PDT 24
Peak memory 206356 kb
Host smart-14fd32e5-c109-453a-ae17-95ad15d232be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632931958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3632931958
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.804748603
Short name T1006
Test name
Test status
Simulation time 100141120 ps
CPU time 1.41 seconds
Started Jun 22 04:53:57 PM PDT 24
Finished Jun 22 04:54:00 PM PDT 24
Peak memory 214688 kb
Host smart-6eebaa0c-9a6b-4875-a7e6-fe934a4e14d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804748603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.804748603
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.214396762
Short name T1025
Test name
Test status
Simulation time 268796397 ps
CPU time 1.39 seconds
Started Jun 22 04:54:01 PM PDT 24
Finished Jun 22 04:54:03 PM PDT 24
Peak memory 214196 kb
Host smart-ad02b773-e5e6-425a-a88e-b33ab0ca3ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214396762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.214396762
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.149093042
Short name T1084
Test name
Test status
Simulation time 22276343 ps
CPU time 0.99 seconds
Started Jun 22 04:53:53 PM PDT 24
Finished Jun 22 04:53:54 PM PDT 24
Peak memory 206488 kb
Host smart-6c9d1e4d-f4e8-4e11-8445-f289e249d62c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149093042 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.149093042
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1852389267
Short name T1119
Test name
Test status
Simulation time 24385961 ps
CPU time 0.87 seconds
Started Jun 22 04:53:56 PM PDT 24
Finished Jun 22 04:53:58 PM PDT 24
Peak memory 206352 kb
Host smart-c3c05bd0-3d20-498e-9613-0ad4e8eceaba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852389267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1852389267
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3784209541
Short name T1018
Test name
Test status
Simulation time 57573407 ps
CPU time 0.92 seconds
Started Jun 22 04:53:58 PM PDT 24
Finished Jun 22 04:54:00 PM PDT 24
Peak memory 206192 kb
Host smart-4aac8bf3-51b7-411f-b78e-1ab95378f873
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784209541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3784209541
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2962473988
Short name T1097
Test name
Test status
Simulation time 75078182 ps
CPU time 1.49 seconds
Started Jun 22 04:53:55 PM PDT 24
Finished Jun 22 04:53:58 PM PDT 24
Peak memory 206656 kb
Host smart-893e580a-5030-4b33-be7c-5f0338aee081
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962473988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2962473988
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3131082328
Short name T1030
Test name
Test status
Simulation time 436154523 ps
CPU time 3.91 seconds
Started Jun 22 04:53:55 PM PDT 24
Finished Jun 22 04:54:00 PM PDT 24
Peak memory 214596 kb
Host smart-3913a40d-fe5f-4974-b4b0-482c880f4011
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131082328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3131082328
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.54696961
Short name T1108
Test name
Test status
Simulation time 122580833 ps
CPU time 3.05 seconds
Started Jun 22 04:53:55 PM PDT 24
Finished Jun 22 04:53:59 PM PDT 24
Peak memory 206572 kb
Host smart-c0cb33f3-36f7-4b96-8f44-a18a7747b422
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54696961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.54696961
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2401580101
Short name T1028
Test name
Test status
Simulation time 117662795 ps
CPU time 1.56 seconds
Started Jun 22 04:53:55 PM PDT 24
Finished Jun 22 04:53:57 PM PDT 24
Peak memory 214664 kb
Host smart-011e4546-fc07-4526-8754-dc9dd50eec77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401580101 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2401580101
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1198932214
Short name T244
Test name
Test status
Simulation time 11430051 ps
CPU time 0.86 seconds
Started Jun 22 04:53:57 PM PDT 24
Finished Jun 22 04:53:59 PM PDT 24
Peak memory 206316 kb
Host smart-d1ee2861-1e44-4233-9985-c6ad4eef5849
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198932214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1198932214
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.4161154532
Short name T1062
Test name
Test status
Simulation time 25737025 ps
CPU time 0.83 seconds
Started Jun 22 04:53:57 PM PDT 24
Finished Jun 22 04:53:59 PM PDT 24
Peak memory 206360 kb
Host smart-6af27130-0f71-4648-8ecb-9f38ad45b152
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161154532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.4161154532
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.522394057
Short name T1111
Test name
Test status
Simulation time 324404755 ps
CPU time 1.32 seconds
Started Jun 22 04:53:55 PM PDT 24
Finished Jun 22 04:53:57 PM PDT 24
Peak memory 206308 kb
Host smart-110d57a9-ff92-4e56-9bc5-907bffc953d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522394057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.522394057
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2008122906
Short name T1066
Test name
Test status
Simulation time 24574549 ps
CPU time 1.54 seconds
Started Jun 22 04:53:56 PM PDT 24
Finished Jun 22 04:53:58 PM PDT 24
Peak memory 214776 kb
Host smart-bcf9ab52-d4ce-496c-8691-8bdc881be499
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008122906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2008122906
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2002303813
Short name T1090
Test name
Test status
Simulation time 1133057354 ps
CPU time 2.57 seconds
Started Jun 22 04:53:54 PM PDT 24
Finished Jun 22 04:53:58 PM PDT 24
Peak memory 214536 kb
Host smart-f6f2e1a1-d698-4d3d-905f-5c3d4ecb0303
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002303813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2002303813
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.141813975
Short name T1087
Test name
Test status
Simulation time 125222688 ps
CPU time 1.42 seconds
Started Jun 22 04:53:54 PM PDT 24
Finished Jun 22 04:53:56 PM PDT 24
Peak memory 214684 kb
Host smart-3c51dc6c-16d2-4763-b3f3-f9ed578d42f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141813975 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.141813975
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3758890210
Short name T251
Test name
Test status
Simulation time 14522149 ps
CPU time 0.94 seconds
Started Jun 22 04:53:54 PM PDT 24
Finished Jun 22 04:53:56 PM PDT 24
Peak memory 206348 kb
Host smart-56f19e58-0c69-4dec-b266-9cdcb7907afe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758890210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3758890210
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3535341828
Short name T994
Test name
Test status
Simulation time 112798450 ps
CPU time 0.87 seconds
Started Jun 22 04:54:00 PM PDT 24
Finished Jun 22 04:54:02 PM PDT 24
Peak memory 206284 kb
Host smart-4d36dae7-7fe0-4dee-91b6-094865f2eb2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535341828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3535341828
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1860908728
Short name T1089
Test name
Test status
Simulation time 62513357 ps
CPU time 1.12 seconds
Started Jun 22 04:53:56 PM PDT 24
Finished Jun 22 04:53:58 PM PDT 24
Peak memory 206416 kb
Host smart-040dd86e-f749-4668-a6f8-d42effc3d0c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860908728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1860908728
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2828918993
Short name T1047
Test name
Test status
Simulation time 120290661 ps
CPU time 2.14 seconds
Started Jun 22 04:53:58 PM PDT 24
Finished Jun 22 04:54:01 PM PDT 24
Peak memory 214672 kb
Host smart-f7f78e7b-f0b3-4b30-80ec-a92dab35d6ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828918993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2828918993
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2243578268
Short name T1044
Test name
Test status
Simulation time 57097185 ps
CPU time 1.75 seconds
Started Jun 22 04:53:57 PM PDT 24
Finished Jun 22 04:54:00 PM PDT 24
Peak memory 206480 kb
Host smart-ceb9a9c1-06e3-49c6-9c72-0eb7629613b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243578268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2243578268
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.532768273
Short name T1091
Test name
Test status
Simulation time 273933052 ps
CPU time 1.11 seconds
Started Jun 22 04:54:02 PM PDT 24
Finished Jun 22 04:54:05 PM PDT 24
Peak memory 217088 kb
Host smart-8e34e70d-63ed-486d-b639-981c8c62d722
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532768273 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.532768273
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.758172448
Short name T1040
Test name
Test status
Simulation time 126562784 ps
CPU time 0.88 seconds
Started Jun 22 04:53:56 PM PDT 24
Finished Jun 22 04:53:58 PM PDT 24
Peak memory 206396 kb
Host smart-ca75d367-1684-482c-8355-87ea3759992b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758172448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.758172448
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3857213512
Short name T1068
Test name
Test status
Simulation time 22881652 ps
CPU time 0.92 seconds
Started Jun 22 04:53:54 PM PDT 24
Finished Jun 22 04:53:55 PM PDT 24
Peak memory 206372 kb
Host smart-4299f081-c94e-4b88-950a-4f3f724bd557
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857213512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3857213512
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4021428154
Short name T1081
Test name
Test status
Simulation time 46940691 ps
CPU time 1.18 seconds
Started Jun 22 04:54:01 PM PDT 24
Finished Jun 22 04:54:04 PM PDT 24
Peak memory 206412 kb
Host smart-88f5f66d-1d9f-4fda-9382-d39835cf42ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021428154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.4021428154
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.642978229
Short name T1077
Test name
Test status
Simulation time 65980225 ps
CPU time 1.31 seconds
Started Jun 22 04:53:54 PM PDT 24
Finished Jun 22 04:53:56 PM PDT 24
Peak memory 214844 kb
Host smart-473e9073-9508-46fb-964f-0ed5886cc9fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642978229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.642978229
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4120625240
Short name T270
Test name
Test status
Simulation time 581340213 ps
CPU time 2.6 seconds
Started Jun 22 04:53:56 PM PDT 24
Finished Jun 22 04:54:00 PM PDT 24
Peak memory 206616 kb
Host smart-89645bf7-868f-4623-835e-a05f80d20adf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120625240 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.4120625240
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2628814828
Short name T1067
Test name
Test status
Simulation time 26679454 ps
CPU time 1.36 seconds
Started Jun 22 04:54:02 PM PDT 24
Finished Jun 22 04:54:05 PM PDT 24
Peak memory 214668 kb
Host smart-37dd1cd2-090b-458b-b889-1b6eda36dd07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628814828 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2628814828
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2199893292
Short name T997
Test name
Test status
Simulation time 56738241 ps
CPU time 0.85 seconds
Started Jun 22 04:54:07 PM PDT 24
Finished Jun 22 04:54:08 PM PDT 24
Peak memory 206240 kb
Host smart-e5b6507c-bf73-4526-8146-10778634b674
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199893292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2199893292
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3801170271
Short name T1078
Test name
Test status
Simulation time 13121135 ps
CPU time 0.85 seconds
Started Jun 22 04:54:04 PM PDT 24
Finished Jun 22 04:54:06 PM PDT 24
Peak memory 206360 kb
Host smart-12ce5850-9754-4c83-872b-d3167172cffe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801170271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3801170271
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1945797468
Short name T1075
Test name
Test status
Simulation time 305581735 ps
CPU time 1.18 seconds
Started Jun 22 04:54:03 PM PDT 24
Finished Jun 22 04:54:05 PM PDT 24
Peak memory 206444 kb
Host smart-204fe38e-9002-42b9-b163-d763f078560a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945797468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1945797468
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2225183595
Short name T1056
Test name
Test status
Simulation time 285352978 ps
CPU time 2 seconds
Started Jun 22 04:54:04 PM PDT 24
Finished Jun 22 04:54:08 PM PDT 24
Peak memory 214696 kb
Host smart-46d4e339-4668-49fa-b545-f07fea166b9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225183595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2225183595
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3551266363
Short name T1022
Test name
Test status
Simulation time 169856425 ps
CPU time 1.84 seconds
Started Jun 22 04:54:01 PM PDT 24
Finished Jun 22 04:54:05 PM PDT 24
Peak memory 214616 kb
Host smart-2f35900e-d8a8-4626-9c13-0385833e954c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551266363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3551266363
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2715777187
Short name T1055
Test name
Test status
Simulation time 30960355 ps
CPU time 1.48 seconds
Started Jun 22 04:54:03 PM PDT 24
Finished Jun 22 04:54:06 PM PDT 24
Peak memory 217660 kb
Host smart-277ca9ff-adb3-40d9-9128-8dbe5c77aff4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715777187 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2715777187
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1954027076
Short name T252
Test name
Test status
Simulation time 35930572 ps
CPU time 0.93 seconds
Started Jun 22 04:54:05 PM PDT 24
Finished Jun 22 04:54:07 PM PDT 24
Peak memory 206348 kb
Host smart-cb4baf75-675d-4531-8c49-04b12af9327e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954027076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1954027076
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.298157472
Short name T1113
Test name
Test status
Simulation time 39783012 ps
CPU time 0.89 seconds
Started Jun 22 04:54:03 PM PDT 24
Finished Jun 22 04:54:06 PM PDT 24
Peak memory 206264 kb
Host smart-94d89e0b-01f7-4c65-b8ad-f2952b820806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298157472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.298157472
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1699257069
Short name T1085
Test name
Test status
Simulation time 58684614 ps
CPU time 0.98 seconds
Started Jun 22 04:54:07 PM PDT 24
Finished Jun 22 04:54:08 PM PDT 24
Peak memory 206548 kb
Host smart-dc0e6fc2-b3bb-4887-a7de-edd476d017bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699257069 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1699257069
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.32086294
Short name T1017
Test name
Test status
Simulation time 340642624 ps
CPU time 3.33 seconds
Started Jun 22 04:54:11 PM PDT 24
Finished Jun 22 04:54:17 PM PDT 24
Peak memory 222896 kb
Host smart-13d57fe1-980f-4fe8-a673-82ec98badd45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32086294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.32086294
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2668820509
Short name T268
Test name
Test status
Simulation time 79412417 ps
CPU time 2.21 seconds
Started Jun 22 04:54:03 PM PDT 24
Finished Jun 22 04:54:06 PM PDT 24
Peak memory 206400 kb
Host smart-fd05c211-5464-4e7d-94ba-33790410b538
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668820509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2668820509
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.294318350
Short name T1101
Test name
Test status
Simulation time 101217990 ps
CPU time 0.93 seconds
Started Jun 22 04:54:03 PM PDT 24
Finished Jun 22 04:54:05 PM PDT 24
Peak memory 206444 kb
Host smart-55fbfa08-3399-4312-b420-23f05166dd7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294318350 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.294318350
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3239021719
Short name T258
Test name
Test status
Simulation time 15046937 ps
CPU time 0.91 seconds
Started Jun 22 04:54:04 PM PDT 24
Finished Jun 22 04:54:07 PM PDT 24
Peak memory 206240 kb
Host smart-ccfc4e1a-c2bb-45c8-813b-f783ad21d840
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239021719 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3239021719
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1704276503
Short name T1005
Test name
Test status
Simulation time 32787968 ps
CPU time 0.8 seconds
Started Jun 22 04:54:05 PM PDT 24
Finished Jun 22 04:54:07 PM PDT 24
Peak memory 206220 kb
Host smart-f03ebc53-5ea5-46fe-a3eb-17ba45f71b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704276503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1704276503
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1828854253
Short name T1069
Test name
Test status
Simulation time 56548549 ps
CPU time 1.32 seconds
Started Jun 22 04:54:11 PM PDT 24
Finished Jun 22 04:54:15 PM PDT 24
Peak memory 206480 kb
Host smart-1109e1a5-84a2-44ee-9aa0-45350e67e0a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828854253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1828854253
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2715007096
Short name T1051
Test name
Test status
Simulation time 141404757 ps
CPU time 4.72 seconds
Started Jun 22 04:54:01 PM PDT 24
Finished Jun 22 04:54:07 PM PDT 24
Peak memory 214776 kb
Host smart-879b62b1-66ab-4477-a66b-da1d1fa15aa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715007096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2715007096
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1123210625
Short name T1064
Test name
Test status
Simulation time 292046939 ps
CPU time 2.27 seconds
Started Jun 22 04:54:05 PM PDT 24
Finished Jun 22 04:54:08 PM PDT 24
Peak memory 206400 kb
Host smart-18e78d9d-b687-49eb-9846-3433ab035219
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123210625 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1123210625
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.963338357
Short name T1054
Test name
Test status
Simulation time 39047227 ps
CPU time 1.53 seconds
Started Jun 22 04:53:38 PM PDT 24
Finished Jun 22 04:53:40 PM PDT 24
Peak memory 206428 kb
Host smart-9c74304f-7d39-45a7-afdc-b0106a793c11
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963338357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.963338357
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3564950267
Short name T1001
Test name
Test status
Simulation time 676812476 ps
CPU time 5.03 seconds
Started Jun 22 04:53:31 PM PDT 24
Finished Jun 22 04:53:37 PM PDT 24
Peak memory 206352 kb
Host smart-85de72cc-82cd-4355-b794-82aaa3608b6a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564950267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3564950267
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2712791304
Short name T254
Test name
Test status
Simulation time 52335170 ps
CPU time 0.87 seconds
Started Jun 22 04:53:34 PM PDT 24
Finished Jun 22 04:53:36 PM PDT 24
Peak memory 206356 kb
Host smart-6e457b6d-952a-462f-b7c8-657468931f00
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712791304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2712791304
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2025917417
Short name T1012
Test name
Test status
Simulation time 32441682 ps
CPU time 1.41 seconds
Started Jun 22 04:53:33 PM PDT 24
Finished Jun 22 04:53:35 PM PDT 24
Peak memory 222836 kb
Host smart-5d295fc6-99c6-42ab-9f2d-68de365d4005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025917417 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2025917417
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2677478695
Short name T1014
Test name
Test status
Simulation time 70061468 ps
CPU time 0.84 seconds
Started Jun 22 04:53:37 PM PDT 24
Finished Jun 22 04:53:39 PM PDT 24
Peak memory 206236 kb
Host smart-a0dfcfd3-dbb8-4e90-aca6-e1667c7223d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677478695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2677478695
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1642629990
Short name T1000
Test name
Test status
Simulation time 30002539 ps
CPU time 0.81 seconds
Started Jun 22 04:53:41 PM PDT 24
Finished Jun 22 04:53:43 PM PDT 24
Peak memory 206348 kb
Host smart-4e37beae-83d7-4f43-bcfc-eedc6cbf7b69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642629990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1642629990
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4200494220
Short name T262
Test name
Test status
Simulation time 108023490 ps
CPU time 0.93 seconds
Started Jun 22 04:53:35 PM PDT 24
Finished Jun 22 04:53:37 PM PDT 24
Peak memory 206564 kb
Host smart-cfabd273-0758-4d6b-84cf-6af992a52775
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200494220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.4200494220
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2337493372
Short name T1019
Test name
Test status
Simulation time 26227329 ps
CPU time 1.49 seconds
Started Jun 22 04:53:30 PM PDT 24
Finished Jun 22 04:53:32 PM PDT 24
Peak memory 214688 kb
Host smart-2f950d64-12cb-4d90-9956-e9ade175bea1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337493372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2337493372
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1939807446
Short name T269
Test name
Test status
Simulation time 123249518 ps
CPU time 1.64 seconds
Started Jun 22 04:54:33 PM PDT 24
Finished Jun 22 04:54:35 PM PDT 24
Peak memory 206420 kb
Host smart-13b0deef-9a98-4542-85ed-59f9b3f15d3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939807446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1939807446
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3085846000
Short name T1024
Test name
Test status
Simulation time 153472365 ps
CPU time 0.88 seconds
Started Jun 22 04:54:04 PM PDT 24
Finished Jun 22 04:54:07 PM PDT 24
Peak memory 206220 kb
Host smart-ebc78ffd-fc4e-42bf-b28c-cc8b4ca68465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085846000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3085846000
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.898860980
Short name T1094
Test name
Test status
Simulation time 16757916 ps
CPU time 0.9 seconds
Started Jun 22 04:54:01 PM PDT 24
Finished Jun 22 04:54:03 PM PDT 24
Peak memory 206320 kb
Host smart-34fef3fa-2943-46a4-879c-13787fe51e76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898860980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.898860980
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3870075757
Short name T1045
Test name
Test status
Simulation time 14505567 ps
CPU time 0.87 seconds
Started Jun 22 04:54:00 PM PDT 24
Finished Jun 22 04:54:03 PM PDT 24
Peak memory 206360 kb
Host smart-d9227192-e441-4763-93b9-aa348f73371f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870075757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3870075757
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.928147148
Short name T1117
Test name
Test status
Simulation time 45666871 ps
CPU time 0.83 seconds
Started Jun 22 04:54:02 PM PDT 24
Finished Jun 22 04:54:05 PM PDT 24
Peak memory 206364 kb
Host smart-d6784de4-723d-4138-93cb-81ce78f41f0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928147148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.928147148
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1987540644
Short name T1120
Test name
Test status
Simulation time 28231061 ps
CPU time 0.79 seconds
Started Jun 22 04:54:03 PM PDT 24
Finished Jun 22 04:54:06 PM PDT 24
Peak memory 206204 kb
Host smart-305bfba5-ff47-4c7e-a51a-7668c677526e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987540644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1987540644
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1847742694
Short name T996
Test name
Test status
Simulation time 37305645 ps
CPU time 0.87 seconds
Started Jun 22 04:54:03 PM PDT 24
Finished Jun 22 04:54:06 PM PDT 24
Peak memory 206360 kb
Host smart-60b35798-6566-4cd4-8f1e-f745e9fca1c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847742694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1847742694
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.172266261
Short name T999
Test name
Test status
Simulation time 75404340 ps
CPU time 0.81 seconds
Started Jun 22 04:54:05 PM PDT 24
Finished Jun 22 04:54:07 PM PDT 24
Peak memory 206264 kb
Host smart-f8369c2b-0820-4d41-b5db-ae3d1802e5f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172266261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.172266261
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1188490841
Short name T1063
Test name
Test status
Simulation time 18538915 ps
CPU time 0.99 seconds
Started Jun 22 04:54:11 PM PDT 24
Finished Jun 22 04:54:15 PM PDT 24
Peak memory 206360 kb
Host smart-8b201e48-4452-43a0-88f2-b48b5388e3f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188490841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1188490841
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2021265421
Short name T1032
Test name
Test status
Simulation time 12539910 ps
CPU time 0.83 seconds
Started Jun 22 04:54:11 PM PDT 24
Finished Jun 22 04:54:13 PM PDT 24
Peak memory 206364 kb
Host smart-cb994e9b-8d01-4fed-b99e-7864c2af75de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021265421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2021265421
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1764820622
Short name T1031
Test name
Test status
Simulation time 16782813 ps
CPU time 0.9 seconds
Started Jun 22 04:54:02 PM PDT 24
Finished Jun 22 04:54:04 PM PDT 24
Peak memory 206256 kb
Host smart-8e970dd8-ab05-4d0d-ae8a-aac04ecd151c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764820622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1764820622
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3565917147
Short name T1010
Test name
Test status
Simulation time 28543785 ps
CPU time 0.98 seconds
Started Jun 22 04:53:41 PM PDT 24
Finished Jun 22 04:53:42 PM PDT 24
Peak memory 206364 kb
Host smart-8cc5af92-f0cb-4d39-afed-b14d61abd5b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565917147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3565917147
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3470403021
Short name T1046
Test name
Test status
Simulation time 809806948 ps
CPU time 4.01 seconds
Started Jun 22 04:53:33 PM PDT 24
Finished Jun 22 04:53:37 PM PDT 24
Peak memory 206404 kb
Host smart-3ed1185e-f6b8-43a7-ba48-35b952ff5166
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470403021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3470403021
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3358333443
Short name T1095
Test name
Test status
Simulation time 70504853 ps
CPU time 0.83 seconds
Started Jun 22 04:53:42 PM PDT 24
Finished Jun 22 04:53:43 PM PDT 24
Peak memory 206244 kb
Host smart-0ab0fbec-4261-45d7-9359-73a46dde8e61
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358333443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3358333443
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1234966219
Short name T1126
Test name
Test status
Simulation time 90268146 ps
CPU time 1.3 seconds
Started Jun 22 04:53:35 PM PDT 24
Finished Jun 22 04:53:37 PM PDT 24
Peak memory 217580 kb
Host smart-28d29b6d-e4ed-4fe3-b255-3601f7a8eb5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234966219 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1234966219
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2411048006
Short name T248
Test name
Test status
Simulation time 45200390 ps
CPU time 0.91 seconds
Started Jun 22 04:53:41 PM PDT 24
Finished Jun 22 04:53:43 PM PDT 24
Peak memory 206332 kb
Host smart-3c74a0ca-b805-4143-b273-0218da7010a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411048006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2411048006
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1386152448
Short name T1116
Test name
Test status
Simulation time 57979454 ps
CPU time 0.87 seconds
Started Jun 22 04:53:38 PM PDT 24
Finished Jun 22 04:53:39 PM PDT 24
Peak memory 206452 kb
Host smart-812a0172-38a3-4792-9ad7-f9b4278f2c95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386152448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1386152448
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3147781104
Short name T264
Test name
Test status
Simulation time 24861101 ps
CPU time 0.95 seconds
Started Jun 22 04:53:35 PM PDT 24
Finished Jun 22 04:53:38 PM PDT 24
Peak memory 206424 kb
Host smart-245519e7-7deb-4473-aefe-e2c9ddef4629
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147781104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3147781104
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.18608696
Short name T1052
Test name
Test status
Simulation time 75644796 ps
CPU time 2.69 seconds
Started Jun 22 04:53:35 PM PDT 24
Finished Jun 22 04:53:38 PM PDT 24
Peak memory 214688 kb
Host smart-a265fa04-a183-4755-898e-68395d28ee22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18608696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.18608696
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.498935653
Short name T1110
Test name
Test status
Simulation time 105138436 ps
CPU time 1.39 seconds
Started Jun 22 04:53:38 PM PDT 24
Finished Jun 22 04:53:39 PM PDT 24
Peak memory 206404 kb
Host smart-833860dc-4a25-49a5-91b2-0b3afe14875c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498935653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.498935653
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2647116705
Short name T1057
Test name
Test status
Simulation time 49126529 ps
CPU time 0.86 seconds
Started Jun 22 04:54:03 PM PDT 24
Finished Jun 22 04:54:05 PM PDT 24
Peak memory 206352 kb
Host smart-17e67b5c-1232-4f4d-974a-b8dad68c6c72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647116705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2647116705
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.974487093
Short name T1009
Test name
Test status
Simulation time 14682957 ps
CPU time 0.9 seconds
Started Jun 22 04:54:05 PM PDT 24
Finished Jun 22 04:54:07 PM PDT 24
Peak memory 206308 kb
Host smart-0b956df9-bd28-487f-92d5-c8245478e9d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974487093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.974487093
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2256705167
Short name T1033
Test name
Test status
Simulation time 18089037 ps
CPU time 0.88 seconds
Started Jun 22 04:54:01 PM PDT 24
Finished Jun 22 04:54:04 PM PDT 24
Peak memory 206256 kb
Host smart-333acd7b-7407-4427-a69c-3e43f8754932
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256705167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2256705167
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.614515164
Short name T1099
Test name
Test status
Simulation time 25937344 ps
CPU time 0.88 seconds
Started Jun 22 04:54:06 PM PDT 24
Finished Jun 22 04:54:07 PM PDT 24
Peak memory 206292 kb
Host smart-fba7941b-792d-40b4-8bec-bd75448f9458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614515164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.614515164
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.650857925
Short name T1098
Test name
Test status
Simulation time 40609236 ps
CPU time 0.92 seconds
Started Jun 22 04:54:01 PM PDT 24
Finished Jun 22 04:54:03 PM PDT 24
Peak memory 206268 kb
Host smart-b254ce02-3e22-49a3-94c2-b4d570eb91ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650857925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.650857925
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1231353430
Short name T1121
Test name
Test status
Simulation time 11923407 ps
CPU time 0.83 seconds
Started Jun 22 04:54:11 PM PDT 24
Finished Jun 22 04:54:14 PM PDT 24
Peak memory 206196 kb
Host smart-bb8848ad-7e53-4d17-9a81-83b1aca9f444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231353430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1231353430
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.499365162
Short name T993
Test name
Test status
Simulation time 14456564 ps
CPU time 0.86 seconds
Started Jun 22 04:54:11 PM PDT 24
Finished Jun 22 04:54:14 PM PDT 24
Peak memory 206232 kb
Host smart-3989d1a2-78e7-44be-bbb5-958637769ddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499365162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.499365162
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2795421981
Short name T1029
Test name
Test status
Simulation time 24167094 ps
CPU time 0.82 seconds
Started Jun 22 04:54:09 PM PDT 24
Finished Jun 22 04:54:11 PM PDT 24
Peak memory 206340 kb
Host smart-1ad10fd4-6095-4f64-a763-4bc7981343ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795421981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2795421981
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3928680029
Short name T1073
Test name
Test status
Simulation time 17230097 ps
CPU time 0.82 seconds
Started Jun 22 04:54:09 PM PDT 24
Finished Jun 22 04:54:11 PM PDT 24
Peak memory 206268 kb
Host smart-68f7fc81-c03d-4399-986c-0e32f8d2af7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928680029 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3928680029
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.110667712
Short name T1002
Test name
Test status
Simulation time 12857640 ps
CPU time 0.83 seconds
Started Jun 22 04:54:14 PM PDT 24
Finished Jun 22 04:54:16 PM PDT 24
Peak memory 206280 kb
Host smart-24b34d46-0f89-4132-8900-b73ac9f95847
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110667712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.110667712
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1367641458
Short name T253
Test name
Test status
Simulation time 149097409 ps
CPU time 1.66 seconds
Started Jun 22 04:53:47 PM PDT 24
Finished Jun 22 04:53:49 PM PDT 24
Peak memory 206340 kb
Host smart-44b377f8-d463-4128-b66a-de4e3cc01068
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367641458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1367641458
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1628434424
Short name T1079
Test name
Test status
Simulation time 64668004 ps
CPU time 1.96 seconds
Started Jun 22 04:53:40 PM PDT 24
Finished Jun 22 04:53:42 PM PDT 24
Peak memory 206328 kb
Host smart-b28bfdd0-20b0-45c9-bc22-973c0c2c5631
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628434424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1628434424
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3421187985
Short name T257
Test name
Test status
Simulation time 13653521 ps
CPU time 0.92 seconds
Started Jun 22 04:53:39 PM PDT 24
Finished Jun 22 04:53:40 PM PDT 24
Peak memory 206252 kb
Host smart-b8439846-25ab-4110-b433-d083a967104b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421187985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3421187985
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.342559486
Short name T1114
Test name
Test status
Simulation time 68475845 ps
CPU time 1.07 seconds
Started Jun 22 04:53:42 PM PDT 24
Finished Jun 22 04:53:44 PM PDT 24
Peak memory 214676 kb
Host smart-856be503-73a6-4307-978a-297e41f8ce65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342559486 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.342559486
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.404133609
Short name T250
Test name
Test status
Simulation time 22916863 ps
CPU time 0.86 seconds
Started Jun 22 04:53:43 PM PDT 24
Finished Jun 22 04:53:45 PM PDT 24
Peak memory 206380 kb
Host smart-b40ab2b0-f63c-4b14-81fd-5cb035576af6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404133609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.404133609
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2447157039
Short name T998
Test name
Test status
Simulation time 127286503 ps
CPU time 0.81 seconds
Started Jun 22 04:53:33 PM PDT 24
Finished Jun 22 04:53:35 PM PDT 24
Peak memory 206544 kb
Host smart-6c01d5f6-7185-47d4-a766-ced0df73f380
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447157039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2447157039
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1708303996
Short name T1049
Test name
Test status
Simulation time 66504640 ps
CPU time 0.99 seconds
Started Jun 22 04:53:49 PM PDT 24
Finished Jun 22 04:53:52 PM PDT 24
Peak memory 206484 kb
Host smart-48737f81-67d6-45ad-a1da-ef56a31fec36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708303996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1708303996
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3322743601
Short name T1112
Test name
Test status
Simulation time 53501189 ps
CPU time 1.95 seconds
Started Jun 22 04:53:38 PM PDT 24
Finished Jun 22 04:53:41 PM PDT 24
Peak memory 214832 kb
Host smart-28e80077-407e-4a42-aedf-475116b7c1e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322743601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3322743601
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.777831630
Short name T1061
Test name
Test status
Simulation time 604841765 ps
CPU time 3.06 seconds
Started Jun 22 04:53:38 PM PDT 24
Finished Jun 22 04:53:42 PM PDT 24
Peak memory 206372 kb
Host smart-7dbc9500-6084-4bde-85b3-b8ebb254cfe1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777831630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.777831630
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1398391058
Short name T1027
Test name
Test status
Simulation time 58516725 ps
CPU time 0.81 seconds
Started Jun 22 04:54:11 PM PDT 24
Finished Jun 22 04:54:13 PM PDT 24
Peak memory 206224 kb
Host smart-89eb117e-df07-4212-9288-493b1827146d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398391058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1398391058
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.418978007
Short name T1004
Test name
Test status
Simulation time 45206204 ps
CPU time 0.9 seconds
Started Jun 22 04:54:11 PM PDT 24
Finished Jun 22 04:54:14 PM PDT 24
Peak memory 206264 kb
Host smart-f81cc560-21bf-42af-8b60-9b33c3ea1894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418978007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.418978007
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3966718000
Short name T992
Test name
Test status
Simulation time 188025193 ps
CPU time 0.86 seconds
Started Jun 22 04:54:10 PM PDT 24
Finished Jun 22 04:54:11 PM PDT 24
Peak memory 206364 kb
Host smart-7dba7181-6964-4cad-8f5c-ee281e11305a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966718000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3966718000
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2702497762
Short name T1026
Test name
Test status
Simulation time 18179834 ps
CPU time 0.85 seconds
Started Jun 22 04:54:11 PM PDT 24
Finished Jun 22 04:54:14 PM PDT 24
Peak memory 206192 kb
Host smart-b5e6d7bb-b2fb-493e-a1a9-6b17aeeae4e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702497762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2702497762
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1500772186
Short name T1039
Test name
Test status
Simulation time 41878407 ps
CPU time 0.83 seconds
Started Jun 22 04:54:12 PM PDT 24
Finished Jun 22 04:54:15 PM PDT 24
Peak memory 206316 kb
Host smart-84a19af5-5588-4236-a383-30dd4d309408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500772186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1500772186
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2842846589
Short name T1011
Test name
Test status
Simulation time 23141529 ps
CPU time 0.78 seconds
Started Jun 22 04:54:13 PM PDT 24
Finished Jun 22 04:54:15 PM PDT 24
Peak memory 206268 kb
Host smart-afba0e27-ca7d-44b6-b5dc-bdf3089023db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842846589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2842846589
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.736914401
Short name T1058
Test name
Test status
Simulation time 38275173 ps
CPU time 0.88 seconds
Started Jun 22 04:54:10 PM PDT 24
Finished Jun 22 04:54:13 PM PDT 24
Peak memory 206364 kb
Host smart-c6744f10-67c4-4866-aaaa-7ef61b07dd04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736914401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.736914401
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.321744684
Short name T1125
Test name
Test status
Simulation time 25613917 ps
CPU time 0.86 seconds
Started Jun 22 04:54:09 PM PDT 24
Finished Jun 22 04:54:10 PM PDT 24
Peak memory 206548 kb
Host smart-15ab86c1-bdd0-4df0-a2a2-becb5f36b08d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321744684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.321744684
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3645735320
Short name T1070
Test name
Test status
Simulation time 14261738 ps
CPU time 0.91 seconds
Started Jun 22 04:54:15 PM PDT 24
Finished Jun 22 04:54:16 PM PDT 24
Peak memory 206272 kb
Host smart-37790eb7-94f0-4027-a419-2f28ed50a3fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645735320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3645735320
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1692312470
Short name T1035
Test name
Test status
Simulation time 21035621 ps
CPU time 0.83 seconds
Started Jun 22 04:54:10 PM PDT 24
Finished Jun 22 04:54:11 PM PDT 24
Peak memory 206356 kb
Host smart-23fb079a-08c2-4a4e-abc5-6fe82f51f7d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692312470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1692312470
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3527925605
Short name T1102
Test name
Test status
Simulation time 55168410 ps
CPU time 1.97 seconds
Started Jun 22 04:53:41 PM PDT 24
Finished Jun 22 04:53:44 PM PDT 24
Peak memory 214672 kb
Host smart-8937226a-268b-427a-8517-3a490044cfb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527925605 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3527925605
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2033395645
Short name T263
Test name
Test status
Simulation time 275417472 ps
CPU time 0.96 seconds
Started Jun 22 04:53:42 PM PDT 24
Finished Jun 22 04:53:44 PM PDT 24
Peak memory 206348 kb
Host smart-d8e587de-925c-4908-ac6f-ef6cf9806b00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033395645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2033395645
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1772562229
Short name T1053
Test name
Test status
Simulation time 51861719 ps
CPU time 0.82 seconds
Started Jun 22 04:53:46 PM PDT 24
Finished Jun 22 04:53:48 PM PDT 24
Peak memory 206360 kb
Host smart-2d7b1317-5fc7-4e9e-9137-a55ce9d31290
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772562229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1772562229
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1804943326
Short name T1096
Test name
Test status
Simulation time 18654426 ps
CPU time 1.17 seconds
Started Jun 22 04:53:49 PM PDT 24
Finished Jun 22 04:53:52 PM PDT 24
Peak memory 206424 kb
Host smart-a1a667a2-cf89-4585-9c1c-3f2aa95d909d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804943326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1804943326
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2569539028
Short name T1034
Test name
Test status
Simulation time 229712685 ps
CPU time 3.66 seconds
Started Jun 22 04:53:49 PM PDT 24
Finished Jun 22 04:53:54 PM PDT 24
Peak memory 214520 kb
Host smart-097cc802-c874-4cc8-af5b-9ddcf33aa302
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569539028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2569539028
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.269625642
Short name T1128
Test name
Test status
Simulation time 261168589 ps
CPU time 2.32 seconds
Started Jun 22 04:53:41 PM PDT 24
Finished Jun 22 04:53:44 PM PDT 24
Peak memory 214620 kb
Host smart-27886b8a-3610-495c-82ce-0fa742fd5788
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269625642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.269625642
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2419842517
Short name T995
Test name
Test status
Simulation time 31675126 ps
CPU time 1.13 seconds
Started Jun 22 04:53:41 PM PDT 24
Finished Jun 22 04:53:43 PM PDT 24
Peak memory 214736 kb
Host smart-5b8bb868-e632-49ce-ac54-dd888bec7f1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419842517 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2419842517
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1649010412
Short name T249
Test name
Test status
Simulation time 28695638 ps
CPU time 0.94 seconds
Started Jun 22 04:53:41 PM PDT 24
Finished Jun 22 04:53:42 PM PDT 24
Peak memory 206284 kb
Host smart-0024996b-4939-4858-9192-f26153f76953
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649010412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1649010412
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.781875547
Short name T1080
Test name
Test status
Simulation time 43479742 ps
CPU time 0.86 seconds
Started Jun 22 04:53:42 PM PDT 24
Finished Jun 22 04:53:43 PM PDT 24
Peak memory 206360 kb
Host smart-0714a08b-26f2-4cf1-ab00-8172e64905f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781875547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.781875547
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.706693205
Short name T1093
Test name
Test status
Simulation time 104274522 ps
CPU time 1.28 seconds
Started Jun 22 04:54:48 PM PDT 24
Finished Jun 22 04:54:50 PM PDT 24
Peak memory 206412 kb
Host smart-d43cf235-c02b-44d2-ab10-12adda62d710
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706693205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.706693205
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1057392173
Short name T1088
Test name
Test status
Simulation time 73682785 ps
CPU time 1.4 seconds
Started Jun 22 04:53:49 PM PDT 24
Finished Jun 22 04:53:52 PM PDT 24
Peak memory 222728 kb
Host smart-c6a1a3c4-94e4-498c-b7a1-81e243050187
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057392173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1057392173
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.721382908
Short name T1076
Test name
Test status
Simulation time 55749094 ps
CPU time 1.8 seconds
Started Jun 22 04:53:44 PM PDT 24
Finished Jun 22 04:53:46 PM PDT 24
Peak memory 214612 kb
Host smart-5f16772b-5548-40cf-b315-f5475ef23a23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721382908 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.721382908
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2350772106
Short name T1103
Test name
Test status
Simulation time 88897273 ps
CPU time 1.25 seconds
Started Jun 22 04:53:47 PM PDT 24
Finished Jun 22 04:53:49 PM PDT 24
Peak memory 217452 kb
Host smart-032c305c-4a3d-4a08-aba0-62a8762a050f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350772106 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2350772106
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1452111809
Short name T1020
Test name
Test status
Simulation time 30322063 ps
CPU time 0.94 seconds
Started Jun 22 04:53:46 PM PDT 24
Finished Jun 22 04:53:47 PM PDT 24
Peak memory 206356 kb
Host smart-c149bcf8-b222-425f-886a-4fe9d2b031cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452111809 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1452111809
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.871993792
Short name T1118
Test name
Test status
Simulation time 28423414 ps
CPU time 0.9 seconds
Started Jun 22 04:53:47 PM PDT 24
Finished Jun 22 04:53:49 PM PDT 24
Peak memory 206296 kb
Host smart-0a409d19-972b-4f3c-b696-8acafd97adbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871993792 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.871993792
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1402602630
Short name T261
Test name
Test status
Simulation time 123905301 ps
CPU time 1.41 seconds
Started Jun 22 04:53:49 PM PDT 24
Finished Jun 22 04:53:52 PM PDT 24
Peak memory 206476 kb
Host smart-4b402390-a7a8-4ad5-9262-cd1c7e805f7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402602630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1402602630
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.170238196
Short name T1015
Test name
Test status
Simulation time 80617944 ps
CPU time 1.66 seconds
Started Jun 22 04:53:46 PM PDT 24
Finished Jun 22 04:53:49 PM PDT 24
Peak memory 214712 kb
Host smart-3fe21037-4afa-43a6-8504-0f3c1454108e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170238196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.170238196
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.4079341002
Short name T1038
Test name
Test status
Simulation time 81396136 ps
CPU time 2.41 seconds
Started Jun 22 04:53:47 PM PDT 24
Finished Jun 22 04:53:50 PM PDT 24
Peak memory 206344 kb
Host smart-0415727f-3590-495b-bcf7-e3029ce471f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079341002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.4079341002
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2337782656
Short name T1107
Test name
Test status
Simulation time 174468429 ps
CPU time 2.02 seconds
Started Jun 22 04:53:46 PM PDT 24
Finished Jun 22 04:53:48 PM PDT 24
Peak memory 214704 kb
Host smart-045abe0e-de28-4907-acc5-3c4df023372b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337782656 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2337782656
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.4085681075
Short name T1060
Test name
Test status
Simulation time 30641111 ps
CPU time 0.83 seconds
Started Jun 22 04:53:48 PM PDT 24
Finished Jun 22 04:53:51 PM PDT 24
Peak memory 206360 kb
Host smart-4430d927-31e6-49ed-b813-8ecaf55a62e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085681075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.4085681075
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1442015926
Short name T265
Test name
Test status
Simulation time 260005923 ps
CPU time 1.58 seconds
Started Jun 22 04:53:48 PM PDT 24
Finished Jun 22 04:53:52 PM PDT 24
Peak memory 206416 kb
Host smart-f1c53b27-4efd-4eed-838c-390ccf0715e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442015926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1442015926
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3687401339
Short name T1100
Test name
Test status
Simulation time 28050732 ps
CPU time 1.96 seconds
Started Jun 22 04:53:51 PM PDT 24
Finished Jun 22 04:53:54 PM PDT 24
Peak memory 218764 kb
Host smart-da1e32e6-40f5-4fb2-be31-525331e48cb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687401339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3687401339
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1147967717
Short name T1092
Test name
Test status
Simulation time 746809443 ps
CPU time 2.14 seconds
Started Jun 22 04:53:49 PM PDT 24
Finished Jun 22 04:53:53 PM PDT 24
Peak memory 206476 kb
Host smart-105f0c6f-4d85-437f-a40f-ee34d86bbb92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147967717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1147967717
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4090625613
Short name T1013
Test name
Test status
Simulation time 98822180 ps
CPU time 1.07 seconds
Started Jun 22 04:53:55 PM PDT 24
Finished Jun 22 04:53:57 PM PDT 24
Peak memory 214640 kb
Host smart-f2685f30-886b-4d62-8714-989a6441360b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090625613 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.4090625613
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1796455450
Short name T259
Test name
Test status
Simulation time 43799583 ps
CPU time 0.85 seconds
Started Jun 22 04:53:48 PM PDT 24
Finished Jun 22 04:53:50 PM PDT 24
Peak memory 206340 kb
Host smart-39a759b5-4689-4a49-b58c-90d6cf25504c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796455450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1796455450
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2698162195
Short name T1124
Test name
Test status
Simulation time 14006005 ps
CPU time 0.86 seconds
Started Jun 22 04:53:46 PM PDT 24
Finished Jun 22 04:53:47 PM PDT 24
Peak memory 206360 kb
Host smart-439a1aef-a938-4e81-8f55-35d32d09d318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698162195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2698162195
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1402356501
Short name T1037
Test name
Test status
Simulation time 128502920 ps
CPU time 1.24 seconds
Started Jun 22 04:53:50 PM PDT 24
Finished Jun 22 04:53:53 PM PDT 24
Peak memory 206424 kb
Host smart-bbca8cb4-602d-4d6b-9220-b3d96ab485a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402356501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1402356501
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.4208492462
Short name T1048
Test name
Test status
Simulation time 454752114 ps
CPU time 4.06 seconds
Started Jun 22 04:53:50 PM PDT 24
Finished Jun 22 04:53:55 PM PDT 24
Peak memory 214520 kb
Host smart-ca32c63f-0377-40a3-a450-b87ec83b9c1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208492462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.4208492462
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3839756441
Short name T1042
Test name
Test status
Simulation time 121520583 ps
CPU time 2.93 seconds
Started Jun 22 04:53:48 PM PDT 24
Finished Jun 22 04:53:53 PM PDT 24
Peak memory 206508 kb
Host smart-5cfcd408-ea75-4cfd-850c-002ce06b5fd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839756441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3839756441
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.1297681553
Short name T531
Test name
Test status
Simulation time 41427226 ps
CPU time 0.88 seconds
Started Jun 22 06:19:00 PM PDT 24
Finished Jun 22 06:19:01 PM PDT 24
Peak memory 206116 kb
Host smart-cc75d123-fdfe-484f-a9c2-69baba451a0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297681553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1297681553
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.3912304446
Short name T918
Test name
Test status
Simulation time 12980411 ps
CPU time 0.93 seconds
Started Jun 22 06:18:58 PM PDT 24
Finished Jun 22 06:18:59 PM PDT 24
Peak memory 215720 kb
Host smart-327e7088-b43d-4d2c-9297-0bad07641128
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912304446 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3912304446
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_genbits.1827180391
Short name T376
Test name
Test status
Simulation time 796533545 ps
CPU time 5.12 seconds
Started Jun 22 06:18:51 PM PDT 24
Finished Jun 22 06:18:56 PM PDT 24
Peak memory 219564 kb
Host smart-8bdd4872-52f6-4ef2-8c43-cc1ef3aeee8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827180391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1827180391
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.1067713282
Short name T29
Test name
Test status
Simulation time 17005384 ps
CPU time 1.04 seconds
Started Jun 22 06:18:51 PM PDT 24
Finished Jun 22 06:18:53 PM PDT 24
Peak memory 206432 kb
Host smart-2c1e6cf7-8da2-4298-acf9-0ae3ad9070f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067713282 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1067713282
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2869388712
Short name T19
Test name
Test status
Simulation time 615048940 ps
CPU time 8.63 seconds
Started Jun 22 06:18:59 PM PDT 24
Finished Jun 22 06:19:08 PM PDT 24
Peak memory 237076 kb
Host smart-382fbf6d-59f7-4a41-8cef-21962596c181
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869388712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2869388712
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.4212433109
Short name T767
Test name
Test status
Simulation time 23881540 ps
CPU time 0.88 seconds
Started Jun 22 06:18:51 PM PDT 24
Finished Jun 22 06:18:52 PM PDT 24
Peak memory 214560 kb
Host smart-9fc8a8dc-d202-455f-b932-023717204a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212433109 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.4212433109
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3096151716
Short name T880
Test name
Test status
Simulation time 240520287393 ps
CPU time 1501.82 seconds
Started Jun 22 06:18:51 PM PDT 24
Finished Jun 22 06:43:53 PM PDT 24
Peak memory 225776 kb
Host smart-011f89dd-87ce-4d8a-ab72-83ffd4f3a266
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096151716 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3096151716
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.138418781
Short name T821
Test name
Test status
Simulation time 46795673 ps
CPU time 1.21 seconds
Started Jun 22 06:19:05 PM PDT 24
Finished Jun 22 06:19:06 PM PDT 24
Peak memory 217984 kb
Host smart-07f628b0-93ab-4cc5-a4b5-db1bc8355506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138418781 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.138418781
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.2212497439
Short name T729
Test name
Test status
Simulation time 38791631 ps
CPU time 0.85 seconds
Started Jun 22 06:19:05 PM PDT 24
Finished Jun 22 06:19:06 PM PDT 24
Peak memory 205992 kb
Host smart-aa54589e-9058-4d12-980f-5d60a24e0502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212497439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2212497439
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.3642020779
Short name T749
Test name
Test status
Simulation time 13825524 ps
CPU time 0.94 seconds
Started Jun 22 06:19:05 PM PDT 24
Finished Jun 22 06:19:06 PM PDT 24
Peak memory 215836 kb
Host smart-feae1e42-0558-49ea-b8c6-5522eda21030
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642020779 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3642020779
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1050826072
Short name T516
Test name
Test status
Simulation time 40305202 ps
CPU time 1.35 seconds
Started Jun 22 06:19:06 PM PDT 24
Finished Jun 22 06:19:08 PM PDT 24
Peak memory 216160 kb
Host smart-984108ce-f8c5-44ec-b244-a467fa243695
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050826072 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1050826072
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.87839464
Short name T726
Test name
Test status
Simulation time 100221211 ps
CPU time 1 seconds
Started Jun 22 06:19:08 PM PDT 24
Finished Jun 22 06:19:09 PM PDT 24
Peak memory 219172 kb
Host smart-678d4857-cdc4-4312-8e0b-8de2f4efc66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87839464 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.87839464
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.674732715
Short name T506
Test name
Test status
Simulation time 42652765 ps
CPU time 1.18 seconds
Started Jun 22 06:19:08 PM PDT 24
Finished Jun 22 06:19:10 PM PDT 24
Peak memory 218252 kb
Host smart-cd9663c7-f726-4253-9795-71c7296fa476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674732715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.674732715
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2300582176
Short name T713
Test name
Test status
Simulation time 36293432 ps
CPU time 0.93 seconds
Started Jun 22 06:19:06 PM PDT 24
Finished Jun 22 06:19:07 PM PDT 24
Peak memory 214748 kb
Host smart-45a4ab8c-4811-4031-935d-67cdd3ae446c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300582176 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2300582176
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.3094187925
Short name T30
Test name
Test status
Simulation time 28693426 ps
CPU time 0.99 seconds
Started Jun 22 06:19:07 PM PDT 24
Finished Jun 22 06:19:08 PM PDT 24
Peak memory 206436 kb
Host smart-9c4dabcc-10fe-4b76-a2b0-168f432b8a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094187925 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3094187925
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.1043844944
Short name T234
Test name
Test status
Simulation time 46161892 ps
CPU time 0.89 seconds
Started Jun 22 06:18:58 PM PDT 24
Finished Jun 22 06:19:00 PM PDT 24
Peak memory 206384 kb
Host smart-b381c28f-0e7d-4425-ab24-239c81d23eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043844944 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1043844944
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3851758490
Short name T905
Test name
Test status
Simulation time 416762452 ps
CPU time 2.59 seconds
Started Jun 22 06:19:03 PM PDT 24
Finished Jun 22 06:19:06 PM PDT 24
Peak memory 216572 kb
Host smart-51ca67bd-55f1-4897-9a31-b30a47548753
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851758490 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3851758490
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.659776957
Short name T604
Test name
Test status
Simulation time 33850640563 ps
CPU time 891.65 seconds
Started Jun 22 06:19:08 PM PDT 24
Finished Jun 22 06:34:00 PM PDT 24
Peak memory 222344 kb
Host smart-f5027716-3ec8-49e3-83e7-08efb975aca6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659776957 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.659776957
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_disable.3239176950
Short name T923
Test name
Test status
Simulation time 12012156 ps
CPU time 0.9 seconds
Started Jun 22 06:20:07 PM PDT 24
Finished Jun 22 06:20:08 PM PDT 24
Peak memory 215604 kb
Host smart-d4d823ec-bd5b-4f51-9894-39654140e816
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239176950 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3239176950
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1489713909
Short name T628
Test name
Test status
Simulation time 26338437 ps
CPU time 1.16 seconds
Started Jun 22 06:20:05 PM PDT 24
Finished Jun 22 06:20:07 PM PDT 24
Peak memory 215076 kb
Host smart-75f30718-4c14-4da8-a7a8-14b9b3abb3ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489713909 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1489713909
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.1902754958
Short name T142
Test name
Test status
Simulation time 51188080 ps
CPU time 0.99 seconds
Started Jun 22 06:20:07 PM PDT 24
Finished Jun 22 06:20:09 PM PDT 24
Peak memory 220016 kb
Host smart-5813de9b-1561-4f8c-999a-e1fbf89a2ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902754958 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1902754958
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3332912164
Short name T532
Test name
Test status
Simulation time 63763900 ps
CPU time 1.31 seconds
Started Jun 22 06:19:57 PM PDT 24
Finished Jun 22 06:19:58 PM PDT 24
Peak memory 217784 kb
Host smart-0bc13d08-c846-4b9b-a3ac-e8e1a60e7bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332912164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3332912164
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.1209096830
Short name T706
Test name
Test status
Simulation time 17281410 ps
CPU time 1.08 seconds
Started Jun 22 06:19:58 PM PDT 24
Finished Jun 22 06:20:00 PM PDT 24
Peak memory 214648 kb
Host smart-d0991ceb-4046-4352-a387-eb6c5ba2bb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209096830 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1209096830
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3183251303
Short name T935
Test name
Test status
Simulation time 545683083 ps
CPU time 3.53 seconds
Started Jun 22 06:19:57 PM PDT 24
Finished Jun 22 06:20:00 PM PDT 24
Peak memory 216616 kb
Host smart-aa4be663-5869-4621-a90c-ab9b091bc06b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183251303 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3183251303
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2371496962
Short name T378
Test name
Test status
Simulation time 298687670553 ps
CPU time 1671.14 seconds
Started Jun 22 06:19:59 PM PDT 24
Finished Jun 22 06:47:51 PM PDT 24
Peak memory 227024 kb
Host smart-d17f72af-37f2-4383-a88f-ee94277d620f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371496962 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2371496962
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.1714190958
Short name T933
Test name
Test status
Simulation time 24432393 ps
CPU time 1.19 seconds
Started Jun 22 06:23:08 PM PDT 24
Finished Jun 22 06:23:10 PM PDT 24
Peak memory 219284 kb
Host smart-b57664e8-d4e7-464c-8ee8-be4f676cc53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714190958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.1714190958
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.513227105
Short name T619
Test name
Test status
Simulation time 68231776 ps
CPU time 1.17 seconds
Started Jun 22 06:23:02 PM PDT 24
Finished Jun 22 06:23:04 PM PDT 24
Peak memory 216504 kb
Host smart-349223a5-0333-41d5-986d-14c5441af61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513227105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.513227105
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.2753352894
Short name T180
Test name
Test status
Simulation time 44378521 ps
CPU time 1.15 seconds
Started Jun 22 06:23:08 PM PDT 24
Finished Jun 22 06:23:09 PM PDT 24
Peak memory 217820 kb
Host smart-3804bfdd-313e-4eab-8db5-a44491359268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753352894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.2753352894
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.412493422
Short name T869
Test name
Test status
Simulation time 39721029 ps
CPU time 1.58 seconds
Started Jun 22 06:23:02 PM PDT 24
Finished Jun 22 06:23:05 PM PDT 24
Peak memory 217824 kb
Host smart-398eae2b-470c-4208-ad01-598afc4e1695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412493422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.412493422
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.841986664
Short name T568
Test name
Test status
Simulation time 28741150 ps
CPU time 1.3 seconds
Started Jun 22 06:23:02 PM PDT 24
Finished Jun 22 06:23:04 PM PDT 24
Peak memory 218976 kb
Host smart-8b1e5983-c8be-472e-908a-57be19c93728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841986664 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.841986664
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.4048374423
Short name T990
Test name
Test status
Simulation time 68795451 ps
CPU time 1.09 seconds
Started Jun 22 06:23:05 PM PDT 24
Finished Jun 22 06:23:07 PM PDT 24
Peak memory 216652 kb
Host smart-3c51391b-bf93-4211-a6d2-f24dac6469c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048374423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.4048374423
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.916084195
Short name T182
Test name
Test status
Simulation time 77044717 ps
CPU time 1.14 seconds
Started Jun 22 06:23:25 PM PDT 24
Finished Jun 22 06:23:27 PM PDT 24
Peak memory 219892 kb
Host smart-4ea81254-aaff-41dd-9707-0c52f5746b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916084195 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.916084195
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.2777840124
Short name T285
Test name
Test status
Simulation time 30392659 ps
CPU time 1.25 seconds
Started Jun 22 06:23:04 PM PDT 24
Finished Jun 22 06:23:06 PM PDT 24
Peak memory 219084 kb
Host smart-1e29f5b7-2d0e-47e9-887f-3b92d2b79c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777840124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2777840124
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.660930074
Short name T562
Test name
Test status
Simulation time 49934768 ps
CPU time 1.26 seconds
Started Jun 22 06:23:03 PM PDT 24
Finished Jun 22 06:23:05 PM PDT 24
Peak memory 218608 kb
Host smart-28fef23d-1d33-4449-b33d-9c23e86fc023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660930074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.660930074
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.3220187469
Short name T596
Test name
Test status
Simulation time 108263724 ps
CPU time 1.58 seconds
Started Jun 22 06:23:02 PM PDT 24
Finished Jun 22 06:23:05 PM PDT 24
Peak memory 219816 kb
Host smart-43fc2f05-b232-41e2-9f1f-5767d6f90438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220187469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3220187469
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.474242562
Short name T432
Test name
Test status
Simulation time 42585526 ps
CPU time 1.14 seconds
Started Jun 22 06:23:01 PM PDT 24
Finished Jun 22 06:23:03 PM PDT 24
Peak memory 217960 kb
Host smart-a9689fdb-912a-48dd-8008-463ba5f13c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474242562 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.474242562
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.619243013
Short name T80
Test name
Test status
Simulation time 48516174 ps
CPU time 1.1 seconds
Started Jun 22 06:23:01 PM PDT 24
Finished Jun 22 06:23:03 PM PDT 24
Peak memory 216532 kb
Host smart-4bd4419f-7fd4-4b00-90a8-1768017d2f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619243013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.619243013
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.207836890
Short name T540
Test name
Test status
Simulation time 51661591 ps
CPU time 1.17 seconds
Started Jun 22 06:23:04 PM PDT 24
Finished Jun 22 06:23:06 PM PDT 24
Peak memory 216552 kb
Host smart-5c676c67-289d-459d-8139-1252e8d1f3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207836890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.207836890
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.1200825535
Short name T733
Test name
Test status
Simulation time 67077892 ps
CPU time 1.11 seconds
Started Jun 22 06:23:04 PM PDT 24
Finished Jun 22 06:23:06 PM PDT 24
Peak memory 220056 kb
Host smart-7a82b9df-0594-4d4b-9b69-e4eb65391a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200825535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.1200825535
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.3721980716
Short name T637
Test name
Test status
Simulation time 31175241 ps
CPU time 1.36 seconds
Started Jun 22 06:23:02 PM PDT 24
Finished Jun 22 06:23:04 PM PDT 24
Peak memory 217764 kb
Host smart-c1377832-5db5-4b72-ad0c-c0617fbbe6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721980716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3721980716
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2260353476
Short name T91
Test name
Test status
Simulation time 54465167 ps
CPU time 1.2 seconds
Started Jun 22 06:20:08 PM PDT 24
Finished Jun 22 06:20:10 PM PDT 24
Peak memory 218744 kb
Host smart-fee143a3-1a1d-4039-aa8e-772070e6816f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260353476 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2260353476
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3869909517
Short name T893
Test name
Test status
Simulation time 20385170 ps
CPU time 0.86 seconds
Started Jun 22 06:20:06 PM PDT 24
Finished Jun 22 06:20:07 PM PDT 24
Peak memory 206020 kb
Host smart-624bbd36-9a61-4748-b1a9-15f12e4ed49e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869909517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3869909517
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3310229029
Short name T207
Test name
Test status
Simulation time 64541874 ps
CPU time 0.84 seconds
Started Jun 22 06:20:06 PM PDT 24
Finished Jun 22 06:20:07 PM PDT 24
Peak memory 215688 kb
Host smart-5153c88c-ecea-4d61-885d-eca3253fc641
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310229029 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3310229029
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3275592265
Short name T800
Test name
Test status
Simulation time 40646112 ps
CPU time 1.32 seconds
Started Jun 22 06:20:04 PM PDT 24
Finished Jun 22 06:20:05 PM PDT 24
Peak memory 217780 kb
Host smart-b07696ce-0160-4c60-9854-fd116e623289
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275592265 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3275592265
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.3920578426
Short name T497
Test name
Test status
Simulation time 66598528 ps
CPU time 1.17 seconds
Started Jun 22 06:20:05 PM PDT 24
Finished Jun 22 06:20:07 PM PDT 24
Peak memory 231628 kb
Host smart-3d251660-a528-4ccb-88ab-30d8abaabd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920578426 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3920578426
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_smoke.4286435471
Short name T857
Test name
Test status
Simulation time 39280094 ps
CPU time 0.93 seconds
Started Jun 22 06:20:05 PM PDT 24
Finished Jun 22 06:20:06 PM PDT 24
Peak memory 214592 kb
Host smart-2bcb7f2c-e9f7-412f-a311-1eead088b583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286435471 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.4286435471
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1098004485
Short name T286
Test name
Test status
Simulation time 714187564 ps
CPU time 4.83 seconds
Started Jun 22 06:20:06 PM PDT 24
Finished Jun 22 06:20:11 PM PDT 24
Peak memory 216592 kb
Host smart-1195a4db-d5b2-4886-a19e-b14c7825c98c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098004485 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1098004485
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/110.edn_alert.2587940647
Short name T753
Test name
Test status
Simulation time 26955512 ps
CPU time 1.18 seconds
Started Jun 22 06:23:04 PM PDT 24
Finished Jun 22 06:23:06 PM PDT 24
Peak memory 218132 kb
Host smart-ef1dd3eb-af8e-4205-8f0d-856b1a373d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587940647 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.2587940647
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.3518345428
Short name T437
Test name
Test status
Simulation time 57483483 ps
CPU time 1.3 seconds
Started Jun 22 06:23:04 PM PDT 24
Finished Jun 22 06:23:06 PM PDT 24
Peak memory 218016 kb
Host smart-1bd03c09-4c56-4c46-87fd-63b9a17dc45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518345428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3518345428
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.3218563347
Short name T114
Test name
Test status
Simulation time 77660708 ps
CPU time 1.12 seconds
Started Jun 22 06:23:02 PM PDT 24
Finished Jun 22 06:23:04 PM PDT 24
Peak memory 219144 kb
Host smart-bbca1119-87a8-435d-b201-2fab0e52cf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218563347 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.3218563347
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.2003018319
Short name T894
Test name
Test status
Simulation time 69893684 ps
CPU time 1.76 seconds
Started Jun 22 06:23:01 PM PDT 24
Finished Jun 22 06:23:03 PM PDT 24
Peak memory 219536 kb
Host smart-c59631e1-8d8f-4165-8d35-f535150d8022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003018319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2003018319
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.2925410931
Short name T759
Test name
Test status
Simulation time 46274450 ps
CPU time 1.15 seconds
Started Jun 22 06:23:05 PM PDT 24
Finished Jun 22 06:23:07 PM PDT 24
Peak memory 218216 kb
Host smart-fbec7c8b-5e5f-4b2f-976c-e6d59f5e5e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925410931 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.2925410931
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.14683506
Short name T962
Test name
Test status
Simulation time 84674893 ps
CPU time 1.13 seconds
Started Jun 22 06:23:00 PM PDT 24
Finished Jun 22 06:23:01 PM PDT 24
Peak memory 216660 kb
Host smart-b6a509ff-f4e6-4fd8-b0c6-edafb8a92570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14683506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.14683506
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.3176365385
Short name T791
Test name
Test status
Simulation time 31189257 ps
CPU time 1.34 seconds
Started Jun 22 06:23:05 PM PDT 24
Finished Jun 22 06:23:07 PM PDT 24
Peak memory 219464 kb
Host smart-df5e4431-5473-4005-abf7-0e2838e1a38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176365385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.3176365385
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.2523958444
Short name T558
Test name
Test status
Simulation time 67262821 ps
CPU time 1.06 seconds
Started Jun 22 06:23:08 PM PDT 24
Finished Jun 22 06:23:10 PM PDT 24
Peak memory 216572 kb
Host smart-9729cbbd-4fb1-4420-a957-0724430a6a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523958444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2523958444
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.1845023688
Short name T160
Test name
Test status
Simulation time 47627761 ps
CPU time 1.15 seconds
Started Jun 22 06:23:04 PM PDT 24
Finished Jun 22 06:23:06 PM PDT 24
Peak memory 220864 kb
Host smart-9cf86734-0d5f-467b-9801-f74c11abb267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845023688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.1845023688
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.2745720451
Short name T960
Test name
Test status
Simulation time 43733173 ps
CPU time 1.6 seconds
Started Jun 22 06:23:04 PM PDT 24
Finished Jun 22 06:23:07 PM PDT 24
Peak memory 217876 kb
Host smart-de33238d-dd8d-4d1c-969e-c045f0bbefd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745720451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2745720451
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.4119553639
Short name T670
Test name
Test status
Simulation time 63978112 ps
CPU time 1.25 seconds
Started Jun 22 06:23:03 PM PDT 24
Finished Jun 22 06:23:05 PM PDT 24
Peak memory 219824 kb
Host smart-528d8294-f66b-40f0-96aa-85929248945c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119553639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.4119553639
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.2790358580
Short name T67
Test name
Test status
Simulation time 52876022 ps
CPU time 1.57 seconds
Started Jun 22 06:23:02 PM PDT 24
Finished Jun 22 06:23:04 PM PDT 24
Peak memory 218024 kb
Host smart-476ee493-38fb-45a8-a1ba-45cbedf51ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790358580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2790358580
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.444076201
Short name T721
Test name
Test status
Simulation time 65650384 ps
CPU time 1.15 seconds
Started Jun 22 06:23:02 PM PDT 24
Finished Jun 22 06:23:04 PM PDT 24
Peak memory 219180 kb
Host smart-d732db56-58f1-4b57-9b85-2ff1244558c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444076201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.444076201
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.587316289
Short name T836
Test name
Test status
Simulation time 106456370 ps
CPU time 1.68 seconds
Started Jun 22 06:23:00 PM PDT 24
Finished Jun 22 06:23:02 PM PDT 24
Peak memory 218008 kb
Host smart-c2104d45-058b-49af-9ce9-6f1bbcee0dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587316289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.587316289
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.1052278905
Short name T266
Test name
Test status
Simulation time 90872816 ps
CPU time 1.14 seconds
Started Jun 22 06:23:03 PM PDT 24
Finished Jun 22 06:23:05 PM PDT 24
Peak memory 217752 kb
Host smart-4d8651b6-a757-4f88-9f28-ce3af41494e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052278905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1052278905
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.733472641
Short name T867
Test name
Test status
Simulation time 143628968 ps
CPU time 1.08 seconds
Started Jun 22 06:23:08 PM PDT 24
Finished Jun 22 06:23:10 PM PDT 24
Peak memory 216676 kb
Host smart-c9a0c260-910b-4c04-8613-a7826c5c0e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733472641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.733472641
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.3737333683
Short name T462
Test name
Test status
Simulation time 43643348 ps
CPU time 1.15 seconds
Started Jun 22 06:23:08 PM PDT 24
Finished Jun 22 06:23:09 PM PDT 24
Peak memory 217864 kb
Host smart-7b406f8f-db01-4986-b364-577a65b9a0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737333683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.3737333683
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.3546135092
Short name T361
Test name
Test status
Simulation time 248557606 ps
CPU time 1.16 seconds
Started Jun 22 06:23:07 PM PDT 24
Finished Jun 22 06:23:09 PM PDT 24
Peak memory 216792 kb
Host smart-535e221d-fc40-42a1-8bdf-63893792345f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546135092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3546135092
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2080924666
Short name T757
Test name
Test status
Simulation time 90846193 ps
CPU time 1.33 seconds
Started Jun 22 06:20:08 PM PDT 24
Finished Jun 22 06:20:10 PM PDT 24
Peak memory 219868 kb
Host smart-1200a1af-802c-465d-9d9a-00862e8c4cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080924666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2080924666
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.689073467
Short name T674
Test name
Test status
Simulation time 41395459 ps
CPU time 0.91 seconds
Started Jun 22 06:20:07 PM PDT 24
Finished Jun 22 06:20:09 PM PDT 24
Peak memory 206128 kb
Host smart-54840c5e-c65f-4e94-bf6a-07034c1a6340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689073467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.689073467
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2786157838
Short name T746
Test name
Test status
Simulation time 11581056 ps
CPU time 0.86 seconds
Started Jun 22 06:20:06 PM PDT 24
Finished Jun 22 06:20:08 PM PDT 24
Peak memory 215688 kb
Host smart-efa8aeef-418e-4724-ab84-a58adfa96c21
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786157838 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2786157838
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1547400096
Short name T22
Test name
Test status
Simulation time 77812778 ps
CPU time 1.21 seconds
Started Jun 22 06:20:04 PM PDT 24
Finished Jun 22 06:20:06 PM PDT 24
Peak memory 216396 kb
Host smart-56855616-453c-4fd8-883f-f37250b81544
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547400096 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1547400096
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.3652801427
Short name T120
Test name
Test status
Simulation time 39273930 ps
CPU time 0.98 seconds
Started Jun 22 06:20:07 PM PDT 24
Finished Jun 22 06:20:08 PM PDT 24
Peak memory 219212 kb
Host smart-81b46c48-2116-46a6-b3b0-8f5d301462fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652801427 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3652801427
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3865478561
Short name T370
Test name
Test status
Simulation time 95965474 ps
CPU time 1.06 seconds
Started Jun 22 06:20:03 PM PDT 24
Finished Jun 22 06:20:05 PM PDT 24
Peak memory 216664 kb
Host smart-294b2b06-b520-41f1-b175-4c7976cc3308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865478561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3865478561
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3411564350
Short name T418
Test name
Test status
Simulation time 27861084 ps
CPU time 1.01 seconds
Started Jun 22 06:20:04 PM PDT 24
Finished Jun 22 06:20:06 PM PDT 24
Peak memory 214988 kb
Host smart-9e9a8414-292d-43e3-8fb0-9bd0bc1d4c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411564350 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3411564350
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2245389061
Short name T690
Test name
Test status
Simulation time 40497757 ps
CPU time 0.94 seconds
Started Jun 22 06:20:07 PM PDT 24
Finished Jun 22 06:20:08 PM PDT 24
Peak memory 214644 kb
Host smart-383ddadf-fca5-4c80-99d4-8e5f47b6a009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245389061 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2245389061
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3877170332
Short name T650
Test name
Test status
Simulation time 269313316 ps
CPU time 5.66 seconds
Started Jun 22 06:20:07 PM PDT 24
Finished Jun 22 06:20:13 PM PDT 24
Peak memory 216564 kb
Host smart-bcc3279f-39f5-4aca-ae53-fc1a78a3d006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877170332 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3877170332
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.953497543
Short name T107
Test name
Test status
Simulation time 193756561260 ps
CPU time 1541.61 seconds
Started Jun 22 06:20:05 PM PDT 24
Finished Jun 22 06:45:47 PM PDT 24
Peak memory 226192 kb
Host smart-6597e6fd-0d7d-401f-8c85-52f17f63df8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953497543 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.953497543
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.3908879534
Short name T213
Test name
Test status
Simulation time 29565258 ps
CPU time 1.21 seconds
Started Jun 22 06:23:09 PM PDT 24
Finished Jun 22 06:23:11 PM PDT 24
Peak memory 220404 kb
Host smart-ba14f66e-1f62-4167-95b6-866a739ac7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908879534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.3908879534
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.1801920308
Short name T911
Test name
Test status
Simulation time 49315111 ps
CPU time 1.27 seconds
Started Jun 22 06:23:08 PM PDT 24
Finished Jun 22 06:23:11 PM PDT 24
Peak memory 218072 kb
Host smart-bb2100a4-379b-47e9-ab68-d64f21879cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801920308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1801920308
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.3499437069
Short name T77
Test name
Test status
Simulation time 87629059 ps
CPU time 1.26 seconds
Started Jun 22 06:23:07 PM PDT 24
Finished Jun 22 06:23:09 PM PDT 24
Peak memory 219104 kb
Host smart-4a9e61be-12e3-4584-acf3-96c1ec71c39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499437069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3499437069
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.683225495
Short name T734
Test name
Test status
Simulation time 74664658 ps
CPU time 1.14 seconds
Started Jun 22 06:23:07 PM PDT 24
Finished Jun 22 06:23:08 PM PDT 24
Peak memory 216724 kb
Host smart-6792d682-129f-42c2-ae03-3b8fe40c90c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683225495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.683225495
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.700821717
Short name T527
Test name
Test status
Simulation time 181194685 ps
CPU time 1.23 seconds
Started Jun 22 06:23:08 PM PDT 24
Finished Jun 22 06:23:10 PM PDT 24
Peak memory 216492 kb
Host smart-fb2ac5a4-6ebe-4308-a6a1-19bd659025d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700821717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.700821717
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.3786876474
Short name T885
Test name
Test status
Simulation time 79872873 ps
CPU time 1.19 seconds
Started Jun 22 06:23:09 PM PDT 24
Finished Jun 22 06:23:11 PM PDT 24
Peak memory 217956 kb
Host smart-4106c216-aae2-4aa8-8a4d-61f4e947d225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786876474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.3786876474
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.618072667
Short name T635
Test name
Test status
Simulation time 109037009 ps
CPU time 2.56 seconds
Started Jun 22 06:23:07 PM PDT 24
Finished Jun 22 06:23:10 PM PDT 24
Peak memory 216752 kb
Host smart-0040222e-b4a0-412a-ba9a-91b3418c15ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618072667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.618072667
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.2139974778
Short name T159
Test name
Test status
Simulation time 26392208 ps
CPU time 1.26 seconds
Started Jun 22 06:23:08 PM PDT 24
Finished Jun 22 06:23:10 PM PDT 24
Peak memory 215080 kb
Host smart-0b084bf0-dde5-42d8-84cd-8943d9c5b41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139974778 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.2139974778
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.2335669255
Short name T722
Test name
Test status
Simulation time 48085656 ps
CPU time 1.61 seconds
Started Jun 22 06:23:10 PM PDT 24
Finished Jun 22 06:23:12 PM PDT 24
Peak memory 216652 kb
Host smart-38410c95-dfc2-48ca-8384-72c1f397b40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335669255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2335669255
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2507028346
Short name T830
Test name
Test status
Simulation time 67561563 ps
CPU time 1.35 seconds
Started Jun 22 06:23:08 PM PDT 24
Finished Jun 22 06:23:10 PM PDT 24
Peak memory 216644 kb
Host smart-51dbb850-8845-43c6-bf22-cb543cb6295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507028346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2507028346
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.3975877643
Short name T742
Test name
Test status
Simulation time 125025140 ps
CPU time 1.2 seconds
Started Jun 22 06:23:10 PM PDT 24
Finished Jun 22 06:23:11 PM PDT 24
Peak memory 218708 kb
Host smart-61ec8495-4594-4ca4-ba57-da3337c9aa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975877643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.3975877643
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.3426593264
Short name T965
Test name
Test status
Simulation time 136571738 ps
CPU time 1.12 seconds
Started Jun 22 06:23:08 PM PDT 24
Finished Jun 22 06:23:10 PM PDT 24
Peak memory 216544 kb
Host smart-b1fce265-ea9c-47f6-a704-5324d60d6124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426593264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3426593264
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.4240784944
Short name T178
Test name
Test status
Simulation time 107702878 ps
CPU time 1.19 seconds
Started Jun 22 06:23:14 PM PDT 24
Finished Jun 22 06:23:15 PM PDT 24
Peak memory 219152 kb
Host smart-017a3a4d-71eb-44e4-9571-d0c9a593ee8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240784944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.4240784944
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.1983839480
Short name T738
Test name
Test status
Simulation time 44292019 ps
CPU time 1.72 seconds
Started Jun 22 06:23:17 PM PDT 24
Finished Jun 22 06:23:19 PM PDT 24
Peak memory 217844 kb
Host smart-19b4e583-b1f5-43d4-936e-37dc354be6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983839480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1983839480
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.3484735514
Short name T282
Test name
Test status
Simulation time 26280524 ps
CPU time 1.22 seconds
Started Jun 22 06:23:18 PM PDT 24
Finished Jun 22 06:23:20 PM PDT 24
Peak memory 218024 kb
Host smart-96bce917-37c7-455f-a3ac-7314f8989e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484735514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.3484735514
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.3865237653
Short name T24
Test name
Test status
Simulation time 73860009 ps
CPU time 2.65 seconds
Started Jun 22 06:23:17 PM PDT 24
Finished Jun 22 06:23:20 PM PDT 24
Peak memory 214644 kb
Host smart-bad4f6f1-010e-4850-9a0d-5f85ebc55fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865237653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3865237653
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.554457354
Short name T714
Test name
Test status
Simulation time 52703186 ps
CPU time 1.08 seconds
Started Jun 22 06:23:19 PM PDT 24
Finished Jun 22 06:23:20 PM PDT 24
Peak memory 218880 kb
Host smart-ca3dc7ce-ec10-453d-9dd2-0d2c49feb51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554457354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.554457354
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.2470480571
Short name T565
Test name
Test status
Simulation time 43074141 ps
CPU time 1.55 seconds
Started Jun 22 06:23:16 PM PDT 24
Finished Jun 22 06:23:18 PM PDT 24
Peak memory 217884 kb
Host smart-797f2f7e-182f-4557-9281-98ca3f64540c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470480571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2470480571
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1194449859
Short name T686
Test name
Test status
Simulation time 82754999 ps
CPU time 1.22 seconds
Started Jun 22 06:20:18 PM PDT 24
Finished Jun 22 06:20:21 PM PDT 24
Peak memory 218080 kb
Host smart-5c4cc7c8-26f1-40c5-8675-3abca5bce606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194449859 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1194449859
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.4190534897
Short name T560
Test name
Test status
Simulation time 244231601 ps
CPU time 0.97 seconds
Started Jun 22 06:20:11 PM PDT 24
Finished Jun 22 06:20:12 PM PDT 24
Peak memory 214320 kb
Host smart-1873a1e4-be1e-4d36-8318-a033a3228b45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190534897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.4190534897
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.2744736331
Short name T425
Test name
Test status
Simulation time 72999935 ps
CPU time 0.82 seconds
Started Jun 22 06:20:13 PM PDT 24
Finished Jun 22 06:20:14 PM PDT 24
Peak memory 215816 kb
Host smart-e05a6bbf-d418-4707-9668-f740ce47977b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744736331 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2744736331
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.759734116
Short name T571
Test name
Test status
Simulation time 42637126 ps
CPU time 0.84 seconds
Started Jun 22 06:20:11 PM PDT 24
Finished Jun 22 06:20:13 PM PDT 24
Peak memory 217712 kb
Host smart-dacec61f-c76e-43e8-bf32-bb315018ca93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759734116 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.759734116
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2615841403
Short name T399
Test name
Test status
Simulation time 59700515 ps
CPU time 1.68 seconds
Started Jun 22 06:20:08 PM PDT 24
Finished Jun 22 06:20:11 PM PDT 24
Peak memory 218048 kb
Host smart-98c09d1c-2e86-4da0-9c66-6d89c7c72c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615841403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2615841403
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.295810511
Short name T446
Test name
Test status
Simulation time 38703183 ps
CPU time 0.89 seconds
Started Jun 22 06:20:07 PM PDT 24
Finished Jun 22 06:20:08 PM PDT 24
Peak memory 214624 kb
Host smart-062186c8-d96d-426b-8102-46d89bb94db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295810511 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.295810511
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3317227990
Short name T695
Test name
Test status
Simulation time 13982946544 ps
CPU time 55.13 seconds
Started Jun 22 06:20:04 PM PDT 24
Finished Jun 22 06:20:59 PM PDT 24
Peak memory 217788 kb
Host smart-ed4c1625-d77c-4153-9dd0-8b61e86e1940
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317227990 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3317227990
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.1951285627
Short name T588
Test name
Test status
Simulation time 49769679 ps
CPU time 1.26 seconds
Started Jun 22 06:23:16 PM PDT 24
Finished Jun 22 06:23:18 PM PDT 24
Peak memory 218116 kb
Host smart-21d3ec73-adf3-450b-851c-7dd14ef38a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951285627 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.1951285627
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.82516435
Short name T407
Test name
Test status
Simulation time 44766452 ps
CPU time 1.85 seconds
Started Jun 22 06:23:19 PM PDT 24
Finished Jun 22 06:23:21 PM PDT 24
Peak memory 217896 kb
Host smart-d2f4f75b-2495-43e6-92fb-9614efa7b2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82516435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.82516435
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.2389624931
Short name T930
Test name
Test status
Simulation time 76338232 ps
CPU time 1.19 seconds
Started Jun 22 06:23:19 PM PDT 24
Finished Jun 22 06:23:21 PM PDT 24
Peak memory 218820 kb
Host smart-e230eff2-2f60-4ebe-9ad6-5ef5b8a22e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389624931 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.2389624931
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.4218999294
Short name T551
Test name
Test status
Simulation time 34786712 ps
CPU time 1.43 seconds
Started Jun 22 06:23:16 PM PDT 24
Finished Jun 22 06:23:18 PM PDT 24
Peak memory 217640 kb
Host smart-3ce24306-d696-4d4d-9c9d-fe091bb121e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218999294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.4218999294
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.718440098
Short name T278
Test name
Test status
Simulation time 54232082 ps
CPU time 1.29 seconds
Started Jun 22 06:23:18 PM PDT 24
Finished Jun 22 06:23:20 PM PDT 24
Peak memory 218908 kb
Host smart-723c3b04-6259-4602-a391-8e15a7fbe776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718440098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.718440098
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.1868446813
Short name T86
Test name
Test status
Simulation time 71813116 ps
CPU time 1.06 seconds
Started Jun 22 06:23:18 PM PDT 24
Finished Jun 22 06:23:19 PM PDT 24
Peak memory 216776 kb
Host smart-8c089bf6-ef1d-43da-bd2a-00d3038a49c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868446813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1868446813
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.3986037705
Short name T779
Test name
Test status
Simulation time 30256162 ps
CPU time 1.32 seconds
Started Jun 22 06:23:17 PM PDT 24
Finished Jun 22 06:23:19 PM PDT 24
Peak memory 215092 kb
Host smart-ddd837bd-7d8c-4bc0-ad76-a21a430e4921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986037705 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.3986037705
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.239311458
Short name T475
Test name
Test status
Simulation time 56012015 ps
CPU time 1.42 seconds
Started Jun 22 06:23:17 PM PDT 24
Finished Jun 22 06:23:19 PM PDT 24
Peak memory 217932 kb
Host smart-8bcfc69b-f2c1-4cd4-a049-c4fcdad387ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239311458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.239311458
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.1741399668
Short name T668
Test name
Test status
Simulation time 82457843 ps
CPU time 1.13 seconds
Started Jun 22 06:23:17 PM PDT 24
Finished Jun 22 06:23:19 PM PDT 24
Peak memory 220072 kb
Host smart-27bf49a3-a835-4b49-9d2d-2fe4aa8eb066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741399668 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1741399668
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/135.edn_alert.3652629091
Short name T135
Test name
Test status
Simulation time 42067198 ps
CPU time 1.19 seconds
Started Jun 22 06:23:19 PM PDT 24
Finished Jun 22 06:23:21 PM PDT 24
Peak memory 218040 kb
Host smart-75025331-c92f-4214-9c9f-8c890db2d4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652629091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.3652629091
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.4224591153
Short name T797
Test name
Test status
Simulation time 71681016 ps
CPU time 1.2 seconds
Started Jun 22 06:23:15 PM PDT 24
Finished Jun 22 06:23:16 PM PDT 24
Peak memory 218060 kb
Host smart-e76612c7-fb25-4539-bd54-a914d21b43c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224591153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.4224591153
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.2625978510
Short name T403
Test name
Test status
Simulation time 23401447 ps
CPU time 1.12 seconds
Started Jun 22 06:23:20 PM PDT 24
Finished Jun 22 06:23:21 PM PDT 24
Peak memory 218904 kb
Host smart-cacc7213-79e3-4b42-9494-539ed8c842e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625978510 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.2625978510
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/137.edn_alert.1922462518
Short name T109
Test name
Test status
Simulation time 74940843 ps
CPU time 1.24 seconds
Started Jun 22 06:23:18 PM PDT 24
Finished Jun 22 06:23:20 PM PDT 24
Peak memory 215072 kb
Host smart-93515a3a-556f-49fd-9887-c690f8b52fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922462518 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.1922462518
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.4157250279
Short name T675
Test name
Test status
Simulation time 60162016 ps
CPU time 1.07 seconds
Started Jun 22 06:23:18 PM PDT 24
Finished Jun 22 06:23:19 PM PDT 24
Peak memory 214564 kb
Host smart-0c7c60b4-37e7-49aa-b96d-2a3701ce5654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157250279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.4157250279
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.556569752
Short name T498
Test name
Test status
Simulation time 79770326 ps
CPU time 1.48 seconds
Started Jun 22 06:23:20 PM PDT 24
Finished Jun 22 06:23:21 PM PDT 24
Peak memory 217660 kb
Host smart-e62abd09-6bfa-456a-8cee-72cacfbf9a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556569752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.556569752
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.1222024480
Short name T442
Test name
Test status
Simulation time 65703604 ps
CPU time 1.1 seconds
Started Jun 22 06:23:16 PM PDT 24
Finished Jun 22 06:23:18 PM PDT 24
Peak memory 218140 kb
Host smart-894789d7-868e-45ac-8d8f-01ec49360741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222024480 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.1222024480
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.2564433177
Short name T15
Test name
Test status
Simulation time 33893544 ps
CPU time 1.6 seconds
Started Jun 22 06:23:18 PM PDT 24
Finished Jun 22 06:23:21 PM PDT 24
Peak memory 219420 kb
Host smart-54081b6a-5c21-4883-bdf2-1e0ab8ce7378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564433177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2564433177
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.103976570
Short name T423
Test name
Test status
Simulation time 22047826 ps
CPU time 1.17 seconds
Started Jun 22 06:20:14 PM PDT 24
Finished Jun 22 06:20:15 PM PDT 24
Peak memory 219184 kb
Host smart-4f71f9ed-cddc-40f6-822e-a30872d6a6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103976570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.103976570
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1321456961
Short name T807
Test name
Test status
Simulation time 16267883 ps
CPU time 0.99 seconds
Started Jun 22 06:20:15 PM PDT 24
Finished Jun 22 06:20:16 PM PDT 24
Peak memory 206164 kb
Host smart-73b0cf08-35b6-444a-9ec2-5530e47bb19e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321456961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1321456961
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1393955588
Short name T436
Test name
Test status
Simulation time 13870203 ps
CPU time 0.94 seconds
Started Jun 22 06:20:11 PM PDT 24
Finished Jun 22 06:20:13 PM PDT 24
Peak memory 215484 kb
Host smart-e2ea880e-827a-4f34-ac55-0449e94a01ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393955588 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1393955588
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3213583951
Short name T780
Test name
Test status
Simulation time 33305443 ps
CPU time 1.17 seconds
Started Jun 22 06:20:12 PM PDT 24
Finished Jun 22 06:20:13 PM PDT 24
Peak memory 219184 kb
Host smart-b3777b1b-fda5-4620-a785-9da2510b90ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213583951 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3213583951
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2846632067
Short name T383
Test name
Test status
Simulation time 50411062 ps
CPU time 1.09 seconds
Started Jun 22 06:20:11 PM PDT 24
Finished Jun 22 06:20:13 PM PDT 24
Peak memory 219308 kb
Host smart-cddec394-8179-45ea-a5ea-38e9cd15d49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846632067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2846632067
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.4267964217
Short name T810
Test name
Test status
Simulation time 68389385 ps
CPU time 1.09 seconds
Started Jun 22 06:20:14 PM PDT 24
Finished Jun 22 06:20:15 PM PDT 24
Peak memory 216868 kb
Host smart-45cf3a2b-e5f3-4928-8d5e-ef1a4e0bf237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267964217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.4267964217
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1857253743
Short name T447
Test name
Test status
Simulation time 33625406 ps
CPU time 0.98 seconds
Started Jun 22 06:20:13 PM PDT 24
Finished Jun 22 06:20:14 PM PDT 24
Peak memory 223400 kb
Host smart-ce8271da-8afa-48d4-b531-0b6082cbd688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857253743 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1857253743
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.1386393954
Short name T692
Test name
Test status
Simulation time 48389061 ps
CPU time 0.97 seconds
Started Jun 22 06:20:10 PM PDT 24
Finished Jun 22 06:20:12 PM PDT 24
Peak memory 214616 kb
Host smart-d7bd5e4f-21ef-45fa-88d9-1f5768cdf922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386393954 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1386393954
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.390839033
Short name T945
Test name
Test status
Simulation time 25550504 ps
CPU time 1.07 seconds
Started Jun 22 06:20:10 PM PDT 24
Finished Jun 22 06:20:12 PM PDT 24
Peak memory 214644 kb
Host smart-c945d779-ac6c-4a04-a51c-19bdf67c5ac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390839033 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.390839033
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1783571727
Short name T731
Test name
Test status
Simulation time 30364704094 ps
CPU time 817.6 seconds
Started Jun 22 06:20:12 PM PDT 24
Finished Jun 22 06:33:50 PM PDT 24
Peak memory 218360 kb
Host smart-5a0a8377-0d1a-40d0-9da5-744205614c71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783571727 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1783571727
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.1702625504
Short name T43
Test name
Test status
Simulation time 23879416 ps
CPU time 1.21 seconds
Started Jun 22 06:23:26 PM PDT 24
Finished Jun 22 06:23:28 PM PDT 24
Peak memory 219996 kb
Host smart-d7b8bab4-e832-44ba-8220-8195ec473a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702625504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.1702625504
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.2449318679
Short name T60
Test name
Test status
Simulation time 42496790 ps
CPU time 1.55 seconds
Started Jun 22 06:23:25 PM PDT 24
Finished Jun 22 06:23:27 PM PDT 24
Peak memory 217684 kb
Host smart-c82fc6c6-b0bd-4e0f-b193-ac274f0560a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449318679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2449318679
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.1009063217
Short name T421
Test name
Test status
Simulation time 68296478 ps
CPU time 1.27 seconds
Started Jun 22 06:23:22 PM PDT 24
Finished Jun 22 06:23:23 PM PDT 24
Peak memory 216628 kb
Host smart-9f74b0b6-60de-4bd0-941d-94e2bf1cfdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009063217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1009063217
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.1503153842
Short name T638
Test name
Test status
Simulation time 201178470 ps
CPU time 1.18 seconds
Started Jun 22 06:23:25 PM PDT 24
Finished Jun 22 06:23:26 PM PDT 24
Peak memory 218180 kb
Host smart-0f6a622c-de8f-402c-817d-ef6dfb814149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503153842 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.1503153842
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.1026712782
Short name T864
Test name
Test status
Simulation time 60032282 ps
CPU time 1.7 seconds
Started Jun 22 06:23:23 PM PDT 24
Finished Jun 22 06:23:26 PM PDT 24
Peak memory 217680 kb
Host smart-3eaaafc4-e23f-40be-bcc8-fbc71a7e21b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026712782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1026712782
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.892161336
Short name T927
Test name
Test status
Simulation time 117978727 ps
CPU time 1.14 seconds
Started Jun 22 06:23:23 PM PDT 24
Finished Jun 22 06:23:25 PM PDT 24
Peak memory 217920 kb
Host smart-fda8eedc-8c02-4913-85e4-d50cd6073f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892161336 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.892161336
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.3646868182
Short name T846
Test name
Test status
Simulation time 71899795 ps
CPU time 2.44 seconds
Started Jun 22 06:23:23 PM PDT 24
Finished Jun 22 06:23:26 PM PDT 24
Peak memory 219400 kb
Host smart-4d5861ee-fb09-45d3-8af8-ff8ad9ea8307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646868182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3646868182
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.55760530
Short name T659
Test name
Test status
Simulation time 49014169 ps
CPU time 1.17 seconds
Started Jun 22 06:23:24 PM PDT 24
Finished Jun 22 06:23:26 PM PDT 24
Peak memory 218044 kb
Host smart-6f50a027-213b-476e-82b2-09520373200d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55760530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.55760530
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.3088924163
Short name T272
Test name
Test status
Simulation time 63522334 ps
CPU time 1.59 seconds
Started Jun 22 06:23:25 PM PDT 24
Finished Jun 22 06:23:27 PM PDT 24
Peak memory 217784 kb
Host smart-bb9e17de-e9c9-420f-980b-8b5cffbad6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088924163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3088924163
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.772869683
Short name T981
Test name
Test status
Simulation time 74641583 ps
CPU time 1.09 seconds
Started Jun 22 06:23:23 PM PDT 24
Finished Jun 22 06:23:24 PM PDT 24
Peak memory 216924 kb
Host smart-b36b1758-d6d3-4704-8765-0da3c1c28839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772869683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.772869683
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.682229292
Short name T219
Test name
Test status
Simulation time 41246935 ps
CPU time 1.22 seconds
Started Jun 22 06:23:23 PM PDT 24
Finished Jun 22 06:23:25 PM PDT 24
Peak memory 218032 kb
Host smart-86686118-5c51-471a-b267-5b279085bd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682229292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.682229292
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2958360021
Short name T834
Test name
Test status
Simulation time 103028209 ps
CPU time 1.21 seconds
Started Jun 22 06:23:24 PM PDT 24
Finished Jun 22 06:23:25 PM PDT 24
Peak memory 216664 kb
Host smart-0d5fa1c0-6271-437f-9f33-f32d4c7978f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958360021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2958360021
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.4051699775
Short name T153
Test name
Test status
Simulation time 25790554 ps
CPU time 1.26 seconds
Started Jun 22 06:23:24 PM PDT 24
Finished Jun 22 06:23:26 PM PDT 24
Peak memory 218156 kb
Host smart-6bdf5ed0-4810-4095-a081-a0d50f788d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051699775 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.4051699775
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.1222946881
Short name T849
Test name
Test status
Simulation time 49334780 ps
CPU time 1.37 seconds
Started Jun 22 06:23:24 PM PDT 24
Finished Jun 22 06:23:25 PM PDT 24
Peak memory 218060 kb
Host smart-2c2f5263-b1a2-4481-9723-7faaa93a88f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222946881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1222946881
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.17676620
Short name T271
Test name
Test status
Simulation time 263517286 ps
CPU time 1.16 seconds
Started Jun 22 06:23:23 PM PDT 24
Finished Jun 22 06:23:25 PM PDT 24
Peak memory 218044 kb
Host smart-f71d31ea-1d1c-43e1-b370-ed749ce7e923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17676620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.17676620
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.208114303
Short name T982
Test name
Test status
Simulation time 38875616 ps
CPU time 1.09 seconds
Started Jun 22 06:23:23 PM PDT 24
Finished Jun 22 06:23:25 PM PDT 24
Peak memory 216760 kb
Host smart-59d5af2a-f19b-4c8d-afe5-a8bb25860567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208114303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.208114303
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.534758694
Short name T581
Test name
Test status
Simulation time 35706425 ps
CPU time 1.18 seconds
Started Jun 22 06:23:31 PM PDT 24
Finished Jun 22 06:23:32 PM PDT 24
Peak memory 217928 kb
Host smart-0f1223b2-4ee2-46e2-8b1a-5e08c811a543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534758694 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.534758694
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.208204570
Short name T238
Test name
Test status
Simulation time 45356437 ps
CPU time 1.12 seconds
Started Jun 22 06:23:24 PM PDT 24
Finished Jun 22 06:23:26 PM PDT 24
Peak memory 217688 kb
Host smart-659cf241-c925-4d47-8377-17f8d86ba7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208204570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.208204570
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3590799353
Short name T939
Test name
Test status
Simulation time 27784767 ps
CPU time 1.21 seconds
Started Jun 22 06:20:14 PM PDT 24
Finished Jun 22 06:20:16 PM PDT 24
Peak memory 217980 kb
Host smart-0c0e3936-c176-4fa0-85d3-009983e0c4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590799353 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3590799353
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.417378597
Short name T913
Test name
Test status
Simulation time 23763032 ps
CPU time 1.12 seconds
Started Jun 22 06:20:18 PM PDT 24
Finished Jun 22 06:20:20 PM PDT 24
Peak memory 206168 kb
Host smart-0305f981-22ec-46bd-9445-193733bc7926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417378597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.417378597
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3960282503
Short name T439
Test name
Test status
Simulation time 22714284 ps
CPU time 0.92 seconds
Started Jun 22 06:20:20 PM PDT 24
Finished Jun 22 06:20:22 PM PDT 24
Peak memory 215656 kb
Host smart-75f022fc-2cb7-4320-956d-9d4ffcf4d700
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960282503 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3960282503
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1448531679
Short name T555
Test name
Test status
Simulation time 36506366 ps
CPU time 1.16 seconds
Started Jun 22 06:20:21 PM PDT 24
Finished Jun 22 06:20:23 PM PDT 24
Peak memory 218788 kb
Host smart-de4a7364-2700-436c-afa8-259e60ad3d07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448531679 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1448531679
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1736135101
Short name T7
Test name
Test status
Simulation time 20316145 ps
CPU time 1.07 seconds
Started Jun 22 06:20:19 PM PDT 24
Finished Jun 22 06:20:21 PM PDT 24
Peak memory 217616 kb
Host smart-a0e97d2e-2a08-456f-9b46-290606023ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736135101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1736135101
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.70354566
Short name T952
Test name
Test status
Simulation time 71692969 ps
CPU time 1.5 seconds
Started Jun 22 06:20:12 PM PDT 24
Finished Jun 22 06:20:14 PM PDT 24
Peak memory 217896 kb
Host smart-1ee1e1d7-a3d8-4372-8da2-507eba343d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70354566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.70354566
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2708520304
Short name T494
Test name
Test status
Simulation time 50639134 ps
CPU time 1.03 seconds
Started Jun 22 06:20:14 PM PDT 24
Finished Jun 22 06:20:15 PM PDT 24
Peak memory 223136 kb
Host smart-fada233c-e701-4532-9979-91adef801fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708520304 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2708520304
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.171409047
Short name T977
Test name
Test status
Simulation time 29007683 ps
CPU time 0.95 seconds
Started Jun 22 06:20:13 PM PDT 24
Finished Jun 22 06:20:14 PM PDT 24
Peak memory 214628 kb
Host smart-8fa12b05-6c2d-445f-8265-6eecaaf21dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171409047 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.171409047
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.577025032
Short name T667
Test name
Test status
Simulation time 48076478 ps
CPU time 1.51 seconds
Started Jun 22 06:20:11 PM PDT 24
Finished Jun 22 06:20:13 PM PDT 24
Peak memory 217876 kb
Host smart-fde58b72-5278-4f99-8cd9-6c13bed26070
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577025032 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.577025032
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3276867427
Short name T886
Test name
Test status
Simulation time 7550727784 ps
CPU time 179.44 seconds
Started Jun 22 06:20:13 PM PDT 24
Finished Jun 22 06:23:13 PM PDT 24
Peak memory 217332 kb
Host smart-382319fc-7ce4-4415-bd5e-357edd43a3c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276867427 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3276867427
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.1505486673
Short name T663
Test name
Test status
Simulation time 67982740 ps
CPU time 1.09 seconds
Started Jun 22 06:23:33 PM PDT 24
Finished Jun 22 06:23:34 PM PDT 24
Peak memory 217880 kb
Host smart-26692803-f43c-4f98-837f-5fa4e88b37f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505486673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.1505486673
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.3879884862
Short name T972
Test name
Test status
Simulation time 61334438 ps
CPU time 1.9 seconds
Started Jun 22 06:23:29 PM PDT 24
Finished Jun 22 06:23:32 PM PDT 24
Peak memory 217792 kb
Host smart-4173c528-30b8-47ea-b9e3-25ad37195157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879884862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3879884862
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.1779790735
Short name T842
Test name
Test status
Simulation time 22008480 ps
CPU time 1.23 seconds
Started Jun 22 06:23:31 PM PDT 24
Finished Jun 22 06:23:32 PM PDT 24
Peak memory 218236 kb
Host smart-958c4d83-31cd-49d4-a95a-3773ca19ccbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779790735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1779790735
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.1689409169
Short name T748
Test name
Test status
Simulation time 52393978 ps
CPU time 1.25 seconds
Started Jun 22 06:23:29 PM PDT 24
Finished Jun 22 06:23:31 PM PDT 24
Peak memory 216720 kb
Host smart-9abe4085-79da-4241-a8ac-3afddf1b6c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689409169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1689409169
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.3434871529
Short name T183
Test name
Test status
Simulation time 29261602 ps
CPU time 1.27 seconds
Started Jun 22 06:23:30 PM PDT 24
Finished Jun 22 06:23:32 PM PDT 24
Peak memory 219360 kb
Host smart-a695790e-79a2-40b3-93a5-ccadf619b9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434871529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3434871529
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.1526883710
Short name T347
Test name
Test status
Simulation time 48426186 ps
CPU time 1.65 seconds
Started Jun 22 06:23:30 PM PDT 24
Finished Jun 22 06:23:32 PM PDT 24
Peak memory 217736 kb
Host smart-04fc22df-2d4a-45c2-9a30-38d6ebc6221b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526883710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1526883710
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.2761299016
Short name T641
Test name
Test status
Simulation time 80234623 ps
CPU time 1.18 seconds
Started Jun 22 06:23:31 PM PDT 24
Finished Jun 22 06:23:33 PM PDT 24
Peak memory 218956 kb
Host smart-a555bbcb-1360-47ca-a640-f725b07021d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761299016 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.2761299016
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/154.edn_alert.3107739929
Short name T524
Test name
Test status
Simulation time 36877055 ps
CPU time 1.33 seconds
Started Jun 22 06:23:30 PM PDT 24
Finished Jun 22 06:23:32 PM PDT 24
Peak memory 220188 kb
Host smart-19a7c862-5aa8-4b93-b295-49e8b164c8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107739929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.3107739929
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1335498999
Short name T467
Test name
Test status
Simulation time 49524259 ps
CPU time 1.17 seconds
Started Jun 22 06:23:33 PM PDT 24
Finished Jun 22 06:23:35 PM PDT 24
Peak memory 216576 kb
Host smart-16ddd86e-6aa5-4f89-a4e3-1788662d624e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335498999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1335498999
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.4171302029
Short name T896
Test name
Test status
Simulation time 22549551 ps
CPU time 1.17 seconds
Started Jun 22 06:23:30 PM PDT 24
Finished Jun 22 06:23:32 PM PDT 24
Peak memory 218020 kb
Host smart-0858ad24-ab42-48bc-970e-53f5ba8c37d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171302029 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.4171302029
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.3270826597
Short name T617
Test name
Test status
Simulation time 35960133 ps
CPU time 1.18 seconds
Started Jun 22 06:23:33 PM PDT 24
Finished Jun 22 06:23:34 PM PDT 24
Peak memory 218124 kb
Host smart-81746db0-79a6-429b-a674-b2e786b4a74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270826597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3270826597
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.2863301427
Short name T424
Test name
Test status
Simulation time 147899862 ps
CPU time 1.17 seconds
Started Jun 22 06:23:31 PM PDT 24
Finished Jun 22 06:23:32 PM PDT 24
Peak memory 216432 kb
Host smart-2e0224dc-286a-435e-95ce-fac359e85949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863301427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2863301427
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.158824567
Short name T499
Test name
Test status
Simulation time 25626693 ps
CPU time 1.27 seconds
Started Jun 22 06:23:37 PM PDT 24
Finished Jun 22 06:23:38 PM PDT 24
Peak memory 218948 kb
Host smart-978d7177-90a8-4bc0-b26e-b5abda6de2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158824567 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.158824567
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.2121429880
Short name T888
Test name
Test status
Simulation time 61649309 ps
CPU time 1.27 seconds
Started Jun 22 06:23:31 PM PDT 24
Finished Jun 22 06:23:33 PM PDT 24
Peak memory 217636 kb
Host smart-d190e991-2a56-4559-8d83-145c77c7d152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121429880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2121429880
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.2963956419
Short name T92
Test name
Test status
Simulation time 42673359 ps
CPU time 1.29 seconds
Started Jun 22 06:23:38 PM PDT 24
Finished Jun 22 06:23:41 PM PDT 24
Peak memory 217972 kb
Host smart-e092f087-505c-4662-987d-9dc5cd7e8002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963956419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.2963956419
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.807217983
Short name T640
Test name
Test status
Simulation time 122651335 ps
CPU time 1.22 seconds
Started Jun 22 06:23:36 PM PDT 24
Finished Jun 22 06:23:38 PM PDT 24
Peak memory 216644 kb
Host smart-984b59db-81dd-4753-9c2d-0c0302a28839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807217983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.807217983
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.3245437599
Short name T72
Test name
Test status
Simulation time 112323854 ps
CPU time 1.38 seconds
Started Jun 22 06:23:42 PM PDT 24
Finished Jun 22 06:23:44 PM PDT 24
Peak memory 215292 kb
Host smart-c486c6c3-bcda-43cb-b799-652ea66230b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245437599 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.3245437599
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.3735584139
Short name T602
Test name
Test status
Simulation time 55630760 ps
CPU time 1.33 seconds
Started Jun 22 06:23:38 PM PDT 24
Finished Jun 22 06:23:41 PM PDT 24
Peak memory 219284 kb
Host smart-c0979841-bead-4b31-b641-e159acc47128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735584139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3735584139
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3044637376
Short name T179
Test name
Test status
Simulation time 69784323 ps
CPU time 1.08 seconds
Started Jun 22 06:20:21 PM PDT 24
Finished Jun 22 06:20:23 PM PDT 24
Peak memory 217760 kb
Host smart-37e46652-7336-4244-9813-1d0e16b1633b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044637376 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3044637376
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3913710793
Short name T912
Test name
Test status
Simulation time 136797793 ps
CPU time 0.86 seconds
Started Jun 22 06:20:19 PM PDT 24
Finished Jun 22 06:20:21 PM PDT 24
Peak memory 205820 kb
Host smart-9e0d9430-1cbb-41ad-9c9c-f06cd5a0e4db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913710793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3913710793
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.930457044
Short name T93
Test name
Test status
Simulation time 89626699 ps
CPU time 0.82 seconds
Started Jun 22 06:20:20 PM PDT 24
Finished Jun 22 06:20:21 PM PDT 24
Peak memory 215688 kb
Host smart-a8c5c31d-090b-40b6-96e8-6c6d0a351e04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930457044 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.930457044
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1815161532
Short name T150
Test name
Test status
Simulation time 54018150 ps
CPU time 1.65 seconds
Started Jun 22 06:20:20 PM PDT 24
Finished Jun 22 06:20:23 PM PDT 24
Peak memory 216196 kb
Host smart-1e2ff3d4-0734-4ff9-a59a-276461a0233c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815161532 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1815161532
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1558600397
Short name T805
Test name
Test status
Simulation time 19054695 ps
CPU time 1.15 seconds
Started Jun 22 06:20:18 PM PDT 24
Finished Jun 22 06:20:19 PM PDT 24
Peak memory 223380 kb
Host smart-9c3c6000-644f-482e-b0ec-a345a4f2d783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558600397 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1558600397
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.24830375
Short name T582
Test name
Test status
Simulation time 52372907 ps
CPU time 1.45 seconds
Started Jun 22 06:20:19 PM PDT 24
Finished Jun 22 06:20:21 PM PDT 24
Peak memory 216820 kb
Host smart-d57a1220-1245-4c6d-8a19-d861bd7613b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24830375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.24830375
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.803829980
Short name T426
Test name
Test status
Simulation time 26402044 ps
CPU time 1.01 seconds
Started Jun 22 06:20:18 PM PDT 24
Finished Jun 22 06:20:20 PM PDT 24
Peak memory 214976 kb
Host smart-fa6f29e5-71d5-42b6-b870-181db0b4699b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803829980 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.803829980
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1381135692
Short name T689
Test name
Test status
Simulation time 48384359 ps
CPU time 1.01 seconds
Started Jun 22 06:20:22 PM PDT 24
Finished Jun 22 06:20:23 PM PDT 24
Peak memory 214644 kb
Host smart-57bb3708-0347-4b05-b3e2-7b70847a16c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381135692 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1381135692
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2710223945
Short name T350
Test name
Test status
Simulation time 105432116 ps
CPU time 1.22 seconds
Started Jun 22 06:20:20 PM PDT 24
Finished Jun 22 06:20:22 PM PDT 24
Peak memory 214688 kb
Host smart-6b4f405e-d965-41f9-b3ae-a758de67cd68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710223945 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2710223945
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2260897259
Short name T782
Test name
Test status
Simulation time 53877900447 ps
CPU time 1053.56 seconds
Started Jun 22 06:20:17 PM PDT 24
Finished Jun 22 06:37:51 PM PDT 24
Peak memory 222956 kb
Host smart-62a1c71d-6d43-4f35-8051-d6c579f5b929
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260897259 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2260897259
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.3638168883
Short name T970
Test name
Test status
Simulation time 72126944 ps
CPU time 1.1 seconds
Started Jun 22 06:23:39 PM PDT 24
Finished Jun 22 06:23:41 PM PDT 24
Peak memory 219760 kb
Host smart-7ab80e9c-3e7b-4050-9dc4-9265c864baee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638168883 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3638168883
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.4150028356
Short name T717
Test name
Test status
Simulation time 45812554 ps
CPU time 1.65 seconds
Started Jun 22 06:23:36 PM PDT 24
Finished Jun 22 06:23:38 PM PDT 24
Peak memory 217732 kb
Host smart-847f21f9-3c0d-4cae-bc53-f9a5b6556c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150028356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.4150028356
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.2113076248
Short name T925
Test name
Test status
Simulation time 31118480 ps
CPU time 1.27 seconds
Started Jun 22 06:23:40 PM PDT 24
Finished Jun 22 06:23:42 PM PDT 24
Peak memory 218060 kb
Host smart-9f6a503a-7aaf-4413-9b6b-3dcdf521d4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113076248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.2113076248
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.2205162910
Short name T48
Test name
Test status
Simulation time 108486168 ps
CPU time 1.23 seconds
Started Jun 22 06:23:38 PM PDT 24
Finished Jun 22 06:23:40 PM PDT 24
Peak memory 216820 kb
Host smart-1991f42d-c97f-4c38-9fef-c340229b471b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205162910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2205162910
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.1944518474
Short name T584
Test name
Test status
Simulation time 92811754 ps
CPU time 1.15 seconds
Started Jun 22 06:23:40 PM PDT 24
Finished Jun 22 06:23:41 PM PDT 24
Peak memory 217980 kb
Host smart-7242bd9a-3d27-4e7e-84f5-ee68b8318d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944518474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.1944518474
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.3256224937
Short name T712
Test name
Test status
Simulation time 120960960 ps
CPU time 1.32 seconds
Started Jun 22 06:23:36 PM PDT 24
Finished Jun 22 06:23:38 PM PDT 24
Peak memory 217840 kb
Host smart-b1dbe1fd-6b93-460b-a20a-55a6d0a40517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256224937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3256224937
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.3210507587
Short name T557
Test name
Test status
Simulation time 72285918 ps
CPU time 1.06 seconds
Started Jun 22 06:23:39 PM PDT 24
Finished Jun 22 06:23:40 PM PDT 24
Peak memory 218948 kb
Host smart-c2e61a85-c7d7-42e8-8bf7-284d2dcf8f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210507587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.3210507587
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.3951714941
Short name T381
Test name
Test status
Simulation time 42626168 ps
CPU time 1.75 seconds
Started Jun 22 06:23:40 PM PDT 24
Finished Jun 22 06:23:43 PM PDT 24
Peak memory 217972 kb
Host smart-487c442f-5eeb-4377-a0c1-08c2f2b6752f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951714941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3951714941
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.1558685556
Short name T877
Test name
Test status
Simulation time 40067311 ps
CPU time 1.08 seconds
Started Jun 22 06:23:36 PM PDT 24
Finished Jun 22 06:23:38 PM PDT 24
Peak memory 220252 kb
Host smart-f4492f35-51e4-445b-9b40-367a88d647e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558685556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.1558685556
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.1955601892
Short name T301
Test name
Test status
Simulation time 46135926 ps
CPU time 1.8 seconds
Started Jun 22 06:23:37 PM PDT 24
Finished Jun 22 06:23:40 PM PDT 24
Peak memory 217876 kb
Host smart-bb8f3b27-d917-451f-a13c-6f8d5a44df55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955601892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1955601892
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.3790884073
Short name T833
Test name
Test status
Simulation time 39269049 ps
CPU time 1.14 seconds
Started Jun 22 06:23:36 PM PDT 24
Finished Jun 22 06:23:38 PM PDT 24
Peak memory 218180 kb
Host smart-cb6c3620-dfd5-482b-8ce7-40361b6a48d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790884073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.3790884073
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/166.edn_alert.2819366812
Short name T11
Test name
Test status
Simulation time 30896848 ps
CPU time 1.31 seconds
Started Jun 22 06:23:38 PM PDT 24
Finished Jun 22 06:23:40 PM PDT 24
Peak memory 215096 kb
Host smart-be23742e-a29b-4e6e-a450-25395d91e357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819366812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.2819366812
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.497003651
Short name T61
Test name
Test status
Simulation time 46858250 ps
CPU time 1.54 seconds
Started Jun 22 06:23:39 PM PDT 24
Finished Jun 22 06:23:41 PM PDT 24
Peak memory 217992 kb
Host smart-09daf5aa-2d90-4d9f-a2ce-b18e4a971bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497003651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.497003651
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1002473924
Short name T529
Test name
Test status
Simulation time 27555170 ps
CPU time 1.25 seconds
Started Jun 22 06:23:35 PM PDT 24
Finished Jun 22 06:23:37 PM PDT 24
Peak memory 220148 kb
Host smart-4275ec9a-7730-4fc1-a048-b2dc0fe4eabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002473924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1002473924
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.3559221724
Short name T897
Test name
Test status
Simulation time 27742537 ps
CPU time 1.25 seconds
Started Jun 22 06:23:36 PM PDT 24
Finished Jun 22 06:23:38 PM PDT 24
Peak memory 218688 kb
Host smart-492e4aa2-457e-45f8-a77b-1ce86c27ea7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559221724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3559221724
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.1602426974
Short name T798
Test name
Test status
Simulation time 67719417 ps
CPU time 1.23 seconds
Started Jun 22 06:23:38 PM PDT 24
Finished Jun 22 06:23:40 PM PDT 24
Peak memory 219928 kb
Host smart-f74af4dd-ba4f-4466-92c2-beb6bf03ab75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602426974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.1602426974
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.3944549337
Short name T704
Test name
Test status
Simulation time 67273556 ps
CPU time 1 seconds
Started Jun 22 06:23:41 PM PDT 24
Finished Jun 22 06:23:42 PM PDT 24
Peak memory 216792 kb
Host smart-f9613101-f45a-452c-89e7-aed9e3f23f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944549337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3944549337
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.2008290006
Short name T928
Test name
Test status
Simulation time 42629667 ps
CPU time 1.36 seconds
Started Jun 22 06:23:37 PM PDT 24
Finished Jun 22 06:23:40 PM PDT 24
Peak memory 215088 kb
Host smart-66ecaa3c-2f7f-4a14-b9c7-2f81e5752081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008290006 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2008290006
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.2185873833
Short name T875
Test name
Test status
Simulation time 163562464 ps
CPU time 1.08 seconds
Started Jun 22 06:23:38 PM PDT 24
Finished Jun 22 06:23:40 PM PDT 24
Peak memory 216780 kb
Host smart-d863de31-f444-4594-9341-971dae3f37cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185873833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2185873833
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1526347485
Short name T639
Test name
Test status
Simulation time 23259820 ps
CPU time 1.19 seconds
Started Jun 22 06:20:26 PM PDT 24
Finished Jun 22 06:20:28 PM PDT 24
Peak memory 217940 kb
Host smart-422208ef-d855-43c9-8bc5-4f62dcdf2a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526347485 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1526347485
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3901892172
Short name T586
Test name
Test status
Simulation time 26368265 ps
CPU time 1.05 seconds
Started Jun 22 06:20:27 PM PDT 24
Finished Jun 22 06:20:29 PM PDT 24
Peak memory 206076 kb
Host smart-3ae1ba2d-e805-48e4-82da-9903e2cf771c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901892172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3901892172
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.194047842
Short name T471
Test name
Test status
Simulation time 31076675 ps
CPU time 0.81 seconds
Started Jun 22 06:20:26 PM PDT 24
Finished Jun 22 06:20:28 PM PDT 24
Peak memory 215816 kb
Host smart-b99da1a4-4e56-4285-9df7-d5a25b632470
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194047842 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.194047842
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.478200386
Short name T948
Test name
Test status
Simulation time 21136626 ps
CPU time 1.06 seconds
Started Jun 22 06:20:25 PM PDT 24
Finished Jun 22 06:20:27 PM PDT 24
Peak memory 217448 kb
Host smart-e2ce58a7-1bd9-4890-b275-b0f0fa7ae842
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478200386 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.478200386
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.947558077
Short name T55
Test name
Test status
Simulation time 27233415 ps
CPU time 1.34 seconds
Started Jun 22 06:20:26 PM PDT 24
Finished Jun 22 06:20:28 PM PDT 24
Peak memory 229320 kb
Host smart-dd0182f8-8fa2-48c5-a1ce-b689451c6772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947558077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.947558077
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3686137592
Short name T578
Test name
Test status
Simulation time 28833894 ps
CPU time 1.28 seconds
Started Jun 22 06:20:28 PM PDT 24
Finished Jun 22 06:20:30 PM PDT 24
Peak memory 217924 kb
Host smart-7a9ac508-dc4e-4141-ba20-db76ee47ad82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686137592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3686137592
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3178253527
Short name T192
Test name
Test status
Simulation time 22146094 ps
CPU time 1.14 seconds
Started Jun 22 06:20:27 PM PDT 24
Finished Jun 22 06:20:29 PM PDT 24
Peak memory 214756 kb
Host smart-9b2f2ea9-b72e-4007-b593-64089460916e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178253527 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3178253527
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.940099648
Short name T563
Test name
Test status
Simulation time 15075200 ps
CPU time 1 seconds
Started Jun 22 06:20:20 PM PDT 24
Finished Jun 22 06:20:21 PM PDT 24
Peak memory 214620 kb
Host smart-f998a323-8cef-4761-8e5b-be2d089eb13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940099648 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.940099648
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3734162236
Short name T974
Test name
Test status
Simulation time 377196833 ps
CPU time 2.36 seconds
Started Jun 22 06:20:25 PM PDT 24
Finished Jun 22 06:20:28 PM PDT 24
Peak memory 216660 kb
Host smart-94b9aaf9-bcff-4645-8cb3-41c99e8bd734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734162236 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3734162236
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1174782962
Short name T478
Test name
Test status
Simulation time 184925875209 ps
CPU time 2705.06 seconds
Started Jun 22 06:20:26 PM PDT 24
Finished Jun 22 07:05:32 PM PDT 24
Peak memory 233032 kb
Host smart-df680f16-3ba1-43d3-a8cf-3feca0c0eec1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174782962 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1174782962
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.742516220
Short name T513
Test name
Test status
Simulation time 35088368 ps
CPU time 1.3 seconds
Started Jun 22 06:23:37 PM PDT 24
Finished Jun 22 06:23:40 PM PDT 24
Peak memory 215088 kb
Host smart-6c10b428-db33-450a-989f-716e5dfe5a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742516220 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.742516220
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.3571072881
Short name T931
Test name
Test status
Simulation time 105848065 ps
CPU time 1.29 seconds
Started Jun 22 06:23:37 PM PDT 24
Finished Jun 22 06:23:39 PM PDT 24
Peak memory 219276 kb
Host smart-16cc32d6-533f-41c0-b13b-62154ff82e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571072881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3571072881
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.2846787259
Short name T358
Test name
Test status
Simulation time 66919896 ps
CPU time 1.38 seconds
Started Jun 22 06:23:39 PM PDT 24
Finished Jun 22 06:23:41 PM PDT 24
Peak memory 219608 kb
Host smart-11acff6f-ab81-4740-9b40-c6dd791fd460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846787259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2846787259
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.2939832152
Short name T899
Test name
Test status
Simulation time 92510424 ps
CPU time 0.99 seconds
Started Jun 22 06:23:37 PM PDT 24
Finished Jun 22 06:23:39 PM PDT 24
Peak memory 219460 kb
Host smart-02b4f69e-d394-483f-8113-f86293bfc748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939832152 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.2939832152
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.3574125113
Short name T523
Test name
Test status
Simulation time 70800086 ps
CPU time 1.38 seconds
Started Jun 22 06:23:38 PM PDT 24
Finished Jun 22 06:23:41 PM PDT 24
Peak memory 217812 kb
Host smart-11dffcb1-815a-4817-b2bb-b61b1039d2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574125113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3574125113
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.2311375404
Short name T415
Test name
Test status
Simulation time 23809912 ps
CPU time 1.15 seconds
Started Jun 22 06:23:38 PM PDT 24
Finished Jun 22 06:23:40 PM PDT 24
Peak memory 220080 kb
Host smart-e84e5748-91c3-43b6-87e9-19beaacc17dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311375404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.2311375404
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.4057559799
Short name T575
Test name
Test status
Simulation time 39780267 ps
CPU time 1.68 seconds
Started Jun 22 06:23:35 PM PDT 24
Finished Jun 22 06:23:37 PM PDT 24
Peak memory 217816 kb
Host smart-4d6ff463-aba3-4ff5-abc3-9fdbf88c80cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057559799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.4057559799
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.1224336564
Short name T141
Test name
Test status
Simulation time 24793245 ps
CPU time 1.16 seconds
Started Jun 22 06:23:37 PM PDT 24
Finished Jun 22 06:23:39 PM PDT 24
Peak memory 218856 kb
Host smart-e1a1114d-123e-46c1-9c09-1a36c04761a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224336564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.1224336564
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.3037006362
Short name T507
Test name
Test status
Simulation time 134704007 ps
CPU time 3.13 seconds
Started Jun 22 06:23:38 PM PDT 24
Finished Jun 22 06:23:42 PM PDT 24
Peak memory 219384 kb
Host smart-1080998e-635b-4712-bef9-88ca7f34418f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037006362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3037006362
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3458501033
Short name T444
Test name
Test status
Simulation time 67476889 ps
CPU time 1.24 seconds
Started Jun 22 06:23:35 PM PDT 24
Finished Jun 22 06:23:37 PM PDT 24
Peak memory 218192 kb
Host smart-0c94418d-c8f9-4d42-8d35-d7306fc4028c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458501033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3458501033
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/176.edn_alert.3579368923
Short name T818
Test name
Test status
Simulation time 93245721 ps
CPU time 1.25 seconds
Started Jun 22 06:23:37 PM PDT 24
Finished Jun 22 06:23:39 PM PDT 24
Peak memory 218604 kb
Host smart-976378dc-7f15-4918-ad06-07a53cee46b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579368923 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.3579368923
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.1831189048
Short name T806
Test name
Test status
Simulation time 37984126 ps
CPU time 1.43 seconds
Started Jun 22 06:23:37 PM PDT 24
Finished Jun 22 06:23:40 PM PDT 24
Peak memory 217576 kb
Host smart-a05b1c85-cfa4-4cab-af61-cf7be6766cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831189048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1831189048
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.2337257983
Short name T827
Test name
Test status
Simulation time 24268906 ps
CPU time 1.2 seconds
Started Jun 22 06:23:39 PM PDT 24
Finished Jun 22 06:23:41 PM PDT 24
Peak memory 219164 kb
Host smart-7ff945fb-be25-477d-92a3-aa6dbd51a2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337257983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.2337257983
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.4079446330
Short name T966
Test name
Test status
Simulation time 60282336 ps
CPU time 1.08 seconds
Started Jun 22 06:23:36 PM PDT 24
Finished Jun 22 06:23:38 PM PDT 24
Peak memory 218064 kb
Host smart-3f950152-8f28-431f-8238-babfeacae1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079446330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.4079446330
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.3741682763
Short name T934
Test name
Test status
Simulation time 215263515 ps
CPU time 1.36 seconds
Started Jun 22 06:23:43 PM PDT 24
Finished Jun 22 06:23:45 PM PDT 24
Peak memory 219044 kb
Host smart-bd07a6e9-952e-48ad-b09b-11b6852625d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741682763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.3741682763
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3138269456
Short name T472
Test name
Test status
Simulation time 59129255 ps
CPU time 1.33 seconds
Started Jun 22 06:23:38 PM PDT 24
Finished Jun 22 06:23:40 PM PDT 24
Peak memory 217688 kb
Host smart-78b36930-b089-4990-afb1-bd1b0b8bc86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138269456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3138269456
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.1584128029
Short name T768
Test name
Test status
Simulation time 28955626 ps
CPU time 1.31 seconds
Started Jun 22 06:23:45 PM PDT 24
Finished Jun 22 06:23:47 PM PDT 24
Peak memory 218064 kb
Host smart-29987be6-0df6-4fde-9621-70c5b830fbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584128029 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.1584128029
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.652659802
Short name T855
Test name
Test status
Simulation time 117083370 ps
CPU time 1.46 seconds
Started Jun 22 06:23:47 PM PDT 24
Finished Jun 22 06:23:49 PM PDT 24
Peak memory 216572 kb
Host smart-676d605f-4055-4fda-a09f-14698085f005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652659802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.652659802
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.2290364350
Short name T97
Test name
Test status
Simulation time 94816838 ps
CPU time 1.34 seconds
Started Jun 22 06:20:53 PM PDT 24
Finished Jun 22 06:20:55 PM PDT 24
Peak memory 219668 kb
Host smart-db3d2315-9e63-4df3-912c-4fd6f720fe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290364350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2290364350
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1914567846
Short name T339
Test name
Test status
Simulation time 26887120 ps
CPU time 1.1 seconds
Started Jun 22 06:20:25 PM PDT 24
Finished Jun 22 06:20:27 PM PDT 24
Peak memory 214388 kb
Host smart-6b2985cd-dcc4-4715-90c0-43716abf2753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914567846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1914567846
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3671371746
Short name T955
Test name
Test status
Simulation time 24896139 ps
CPU time 0.91 seconds
Started Jun 22 06:20:27 PM PDT 24
Finished Jun 22 06:20:29 PM PDT 24
Peak memory 215680 kb
Host smart-b0471874-089c-450f-95ec-ba53b96b90ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671371746 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3671371746
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1941688528
Short name T823
Test name
Test status
Simulation time 28789239 ps
CPU time 1 seconds
Started Jun 22 06:20:27 PM PDT 24
Finished Jun 22 06:20:28 PM PDT 24
Peak memory 215024 kb
Host smart-8aa9dd70-2a22-4ffe-90e9-0bc67095bb5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941688528 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1941688528
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.941919058
Short name T902
Test name
Test status
Simulation time 28686182 ps
CPU time 0.92 seconds
Started Jun 22 06:20:25 PM PDT 24
Finished Jun 22 06:20:26 PM PDT 24
Peak memory 217768 kb
Host smart-25c10ebe-1fde-47b7-820c-3b06b30ed277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941919058 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.941919058
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3508114973
Short name T359
Test name
Test status
Simulation time 236591700 ps
CPU time 1.57 seconds
Started Jun 22 06:20:25 PM PDT 24
Finished Jun 22 06:20:27 PM PDT 24
Peak memory 218340 kb
Host smart-35b373f8-fa3a-4057-921d-346a99626abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508114973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3508114973
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1423485608
Short name T101
Test name
Test status
Simulation time 41164145 ps
CPU time 0.85 seconds
Started Jun 22 06:20:26 PM PDT 24
Finished Jun 22 06:20:27 PM PDT 24
Peak memory 214984 kb
Host smart-68eb3be5-fdf6-4ec9-a30d-5d30c3e3e8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423485608 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1423485608
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1491905658
Short name T409
Test name
Test status
Simulation time 30718719 ps
CPU time 0.97 seconds
Started Jun 22 06:20:27 PM PDT 24
Finished Jun 22 06:20:29 PM PDT 24
Peak memory 214620 kb
Host smart-7690bf81-0c46-4cb3-829e-1dca98ae2b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491905658 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1491905658
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1355815670
Short name T288
Test name
Test status
Simulation time 1037023508 ps
CPU time 5.46 seconds
Started Jun 22 06:20:24 PM PDT 24
Finished Jun 22 06:20:30 PM PDT 24
Peak memory 216648 kb
Host smart-74254f5d-ffea-45ce-b635-245df64c0b65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355815670 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1355815670
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2543271574
Short name T672
Test name
Test status
Simulation time 43949987661 ps
CPU time 481.71 seconds
Started Jun 22 06:20:26 PM PDT 24
Finished Jun 22 06:28:29 PM PDT 24
Peak memory 222500 kb
Host smart-daaca037-2a97-4c41-b506-d16c4b8b44b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543271574 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2543271574
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.1735840582
Short name T816
Test name
Test status
Simulation time 343446965 ps
CPU time 1.37 seconds
Started Jun 22 06:23:46 PM PDT 24
Finished Jun 22 06:23:48 PM PDT 24
Peak memory 217812 kb
Host smart-142ea06a-30e6-4b0f-8491-49c2067421a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735840582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.1735840582
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.1911590691
Short name T796
Test name
Test status
Simulation time 67843594 ps
CPU time 1.06 seconds
Started Jun 22 06:23:43 PM PDT 24
Finished Jun 22 06:23:45 PM PDT 24
Peak memory 216656 kb
Host smart-e9f74c48-a959-4550-960a-568022a88d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911590691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1911590691
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.1420220466
Short name T591
Test name
Test status
Simulation time 73217303 ps
CPU time 1.14 seconds
Started Jun 22 06:23:44 PM PDT 24
Finished Jun 22 06:23:46 PM PDT 24
Peak memory 219828 kb
Host smart-525ba859-a4ec-4a69-9b7c-f832e732adf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420220466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.1420220466
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.2047279742
Short name T322
Test name
Test status
Simulation time 65096341 ps
CPU time 2.39 seconds
Started Jun 22 06:23:49 PM PDT 24
Finished Jun 22 06:23:52 PM PDT 24
Peak memory 218880 kb
Host smart-6c45f515-b692-4e2e-b179-3fd7ffd7eb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047279742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2047279742
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.3337754689
Short name T468
Test name
Test status
Simulation time 37196810 ps
CPU time 1.12 seconds
Started Jun 22 06:23:44 PM PDT 24
Finished Jun 22 06:23:46 PM PDT 24
Peak memory 218968 kb
Host smart-e5aee209-faa9-487a-9042-f8f04049db46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337754689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3337754689
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.2650419127
Short name T669
Test name
Test status
Simulation time 269534851 ps
CPU time 1.11 seconds
Started Jun 22 06:23:47 PM PDT 24
Finished Jun 22 06:23:48 PM PDT 24
Peak memory 216492 kb
Host smart-34e27443-da18-4d43-b849-6a3139b73427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650419127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2650419127
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.537485165
Short name T803
Test name
Test status
Simulation time 43467775 ps
CPU time 1.21 seconds
Started Jun 22 06:23:45 PM PDT 24
Finished Jun 22 06:23:47 PM PDT 24
Peak memory 219172 kb
Host smart-32fc5111-df9e-4949-8dd5-22f6090e0dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537485165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.537485165
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.1777025720
Short name T629
Test name
Test status
Simulation time 30613711 ps
CPU time 1.19 seconds
Started Jun 22 06:23:47 PM PDT 24
Finished Jun 22 06:23:49 PM PDT 24
Peak memory 217720 kb
Host smart-901970e0-3fa7-41a9-a954-f918acb780a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777025720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1777025720
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.3147306054
Short name T718
Test name
Test status
Simulation time 25828926 ps
CPU time 1.16 seconds
Started Jun 22 06:23:48 PM PDT 24
Finished Jun 22 06:23:50 PM PDT 24
Peak memory 219124 kb
Host smart-02407ffa-b28c-4695-8743-9d06e611ea9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147306054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.3147306054
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.600792475
Short name T770
Test name
Test status
Simulation time 43888556 ps
CPU time 1.53 seconds
Started Jun 22 06:23:48 PM PDT 24
Finished Jun 22 06:23:50 PM PDT 24
Peak memory 217876 kb
Host smart-1bdcba70-48a8-4cd8-a9ce-e29e67ae9a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600792475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.600792475
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.2614668383
Short name T793
Test name
Test status
Simulation time 33226181 ps
CPU time 1.31 seconds
Started Jun 22 06:23:44 PM PDT 24
Finished Jun 22 06:23:46 PM PDT 24
Peak memory 216764 kb
Host smart-4367b226-7c29-4eaa-bb75-46ccd6439761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614668383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2614668383
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.2903269270
Short name T975
Test name
Test status
Simulation time 62529583 ps
CPU time 1.09 seconds
Started Jun 22 06:23:48 PM PDT 24
Finished Jun 22 06:23:50 PM PDT 24
Peak memory 219212 kb
Host smart-3b7a6075-8084-4001-bebb-81e924b3dcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903269270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2903269270
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.4023729654
Short name T609
Test name
Test status
Simulation time 29004154 ps
CPU time 1.25 seconds
Started Jun 22 06:23:47 PM PDT 24
Finished Jun 22 06:23:49 PM PDT 24
Peak memory 216768 kb
Host smart-bcf85b7d-41ef-4d07-9705-c4bcfd065b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023729654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.4023729654
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.470001011
Short name T430
Test name
Test status
Simulation time 81370286 ps
CPU time 1.26 seconds
Started Jun 22 06:23:47 PM PDT 24
Finished Jun 22 06:23:48 PM PDT 24
Peak memory 218108 kb
Host smart-c432e43a-94be-400d-8c08-9d2b9c9afd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470001011 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.470001011
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.3209286334
Short name T306
Test name
Test status
Simulation time 284633730 ps
CPU time 1.22 seconds
Started Jun 22 06:23:46 PM PDT 24
Finished Jun 22 06:23:48 PM PDT 24
Peak memory 216464 kb
Host smart-5d58d029-8db2-4386-b8da-4e096d7e78cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209286334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3209286334
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.3769647959
Short name T942
Test name
Test status
Simulation time 91137867 ps
CPU time 1.23 seconds
Started Jun 22 06:23:45 PM PDT 24
Finished Jun 22 06:23:47 PM PDT 24
Peak memory 220236 kb
Host smart-9a4c3633-c6d6-4f1a-a75e-4abac0d0ff91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769647959 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.3769647959
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.3191074502
Short name T752
Test name
Test status
Simulation time 44048927 ps
CPU time 1.83 seconds
Started Jun 22 06:23:45 PM PDT 24
Finished Jun 22 06:23:47 PM PDT 24
Peak memory 217824 kb
Host smart-04a12d59-528f-441c-b904-ae7b9b9ff986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191074502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3191074502
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.3401025314
Short name T580
Test name
Test status
Simulation time 74443095 ps
CPU time 1.13 seconds
Started Jun 22 06:23:49 PM PDT 24
Finished Jun 22 06:23:51 PM PDT 24
Peak memory 218392 kb
Host smart-07e76f30-e4c3-4cdd-a444-33b14137f20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401025314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.3401025314
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.1949264391
Short name T348
Test name
Test status
Simulation time 174037978 ps
CPU time 1.1 seconds
Started Jun 22 06:23:46 PM PDT 24
Finished Jun 22 06:23:47 PM PDT 24
Peak memory 219356 kb
Host smart-e29a41c4-3b7d-4a60-8369-fe6cbf7ba907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949264391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1949264391
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.472487262
Short name T937
Test name
Test status
Simulation time 38072466 ps
CPU time 1.23 seconds
Started Jun 22 06:20:37 PM PDT 24
Finished Jun 22 06:20:39 PM PDT 24
Peak memory 218356 kb
Host smart-74591ce1-64e0-4bc0-b123-1d356be4c832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472487262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.472487262
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1501479965
Short name T652
Test name
Test status
Simulation time 39105052 ps
CPU time 0.99 seconds
Started Jun 22 06:20:39 PM PDT 24
Finished Jun 22 06:20:41 PM PDT 24
Peak memory 214316 kb
Host smart-1a4d12dc-756e-45ac-bd36-6466343f7511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501479965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1501479965
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1583033755
Short name T570
Test name
Test status
Simulation time 11643851 ps
CPU time 0.89 seconds
Started Jun 22 06:20:37 PM PDT 24
Finished Jun 22 06:20:39 PM PDT 24
Peak memory 215480 kb
Host smart-3ca2e649-6e5b-4097-8e23-7bd3ae30f92a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583033755 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1583033755
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3098118794
Short name T739
Test name
Test status
Simulation time 76763326 ps
CPU time 1.3 seconds
Started Jun 22 06:20:39 PM PDT 24
Finished Jun 22 06:20:41 PM PDT 24
Peak memory 216280 kb
Host smart-60444586-8338-4c4d-b64c-869bd28991f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098118794 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3098118794
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.992623933
Short name T148
Test name
Test status
Simulation time 25796902 ps
CPU time 1.12 seconds
Started Jun 22 06:20:38 PM PDT 24
Finished Jun 22 06:20:39 PM PDT 24
Peak memory 228996 kb
Host smart-5e7d0b8a-4eeb-479e-941c-3055551f047e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992623933 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.992623933
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2167802278
Short name T622
Test name
Test status
Simulation time 49307804 ps
CPU time 1.87 seconds
Started Jun 22 06:20:27 PM PDT 24
Finished Jun 22 06:20:29 PM PDT 24
Peak memory 218100 kb
Host smart-97ff7668-9a42-44bb-a0ec-6563830ee4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167802278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2167802278
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.378828761
Short name T66
Test name
Test status
Simulation time 23018652 ps
CPU time 1.18 seconds
Started Jun 22 06:20:37 PM PDT 24
Finished Jun 22 06:20:39 PM PDT 24
Peak memory 214996 kb
Host smart-b60d5f79-bd03-4195-9de8-c069a9806e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378828761 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.378828761
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2486141503
Short name T947
Test name
Test status
Simulation time 18172234 ps
CPU time 1.04 seconds
Started Jun 22 06:20:27 PM PDT 24
Finished Jun 22 06:20:28 PM PDT 24
Peak memory 214656 kb
Host smart-63e24060-91e3-4996-903a-ac70a8065533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486141503 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2486141503
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1915415247
Short name T919
Test name
Test status
Simulation time 272493843 ps
CPU time 5.35 seconds
Started Jun 22 06:20:27 PM PDT 24
Finished Jun 22 06:20:33 PM PDT 24
Peak memory 217992 kb
Host smart-fbd616f0-c68b-4c3a-8831-3ab6a2edf1eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915415247 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1915415247
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.501336298
Short name T783
Test name
Test status
Simulation time 52551005473 ps
CPU time 1235.29 seconds
Started Jun 22 06:20:38 PM PDT 24
Finished Jun 22 06:41:14 PM PDT 24
Peak memory 220496 kb
Host smart-082b82b4-50c0-40a3-88cc-9761315624cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501336298 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.501336298
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.726458176
Short name T920
Test name
Test status
Simulation time 51842361 ps
CPU time 1.25 seconds
Started Jun 22 06:23:45 PM PDT 24
Finished Jun 22 06:23:47 PM PDT 24
Peak memory 219148 kb
Host smart-3a76f06b-4278-4151-937a-c6dd47cc9d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726458176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.726458176
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3204659642
Short name T422
Test name
Test status
Simulation time 277593935 ps
CPU time 3.72 seconds
Started Jun 22 06:23:47 PM PDT 24
Finished Jun 22 06:23:51 PM PDT 24
Peak memory 219568 kb
Host smart-bf97631f-dd2a-4094-b891-70d60986df67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204659642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3204659642
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.3292434014
Short name T812
Test name
Test status
Simulation time 24419635 ps
CPU time 1.23 seconds
Started Jun 22 06:23:47 PM PDT 24
Finished Jun 22 06:23:49 PM PDT 24
Peak memory 219208 kb
Host smart-afeacc97-fe76-4056-9de7-cc48dfbd5594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292434014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.3292434014
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.2061803188
Short name T295
Test name
Test status
Simulation time 44314604 ps
CPU time 1.16 seconds
Started Jun 22 06:23:46 PM PDT 24
Finished Jun 22 06:23:48 PM PDT 24
Peak memory 218104 kb
Host smart-790386f3-46cc-4b1a-a456-0dd82a059370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061803188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2061803188
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.2888135371
Short name T991
Test name
Test status
Simulation time 119058933 ps
CPU time 1.29 seconds
Started Jun 22 06:23:49 PM PDT 24
Finished Jun 22 06:23:51 PM PDT 24
Peak memory 218568 kb
Host smart-2dc75e14-6ae1-498c-b3ce-5d4a52869055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888135371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2888135371
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.2005255409
Short name T853
Test name
Test status
Simulation time 164104280 ps
CPU time 2.25 seconds
Started Jun 22 06:23:46 PM PDT 24
Finished Jun 22 06:23:49 PM PDT 24
Peak memory 217896 kb
Host smart-7c1fac0d-bb6c-43c6-8a8f-ef9071ea02af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005255409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2005255409
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.1139913591
Short name T276
Test name
Test status
Simulation time 28486803 ps
CPU time 1.34 seconds
Started Jun 22 06:23:44 PM PDT 24
Finished Jun 22 06:23:46 PM PDT 24
Peak memory 218816 kb
Host smart-09364965-7893-4f7a-9bb6-bd1383000236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139913591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.1139913591
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.1074212481
Short name T871
Test name
Test status
Simulation time 44721439 ps
CPU time 1.3 seconds
Started Jun 22 06:23:43 PM PDT 24
Finished Jun 22 06:23:45 PM PDT 24
Peak memory 218920 kb
Host smart-8fcfcdb6-fc50-4139-aaf3-109958e1c5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074212481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1074212481
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.2861260882
Short name T58
Test name
Test status
Simulation time 31625352 ps
CPU time 1.3 seconds
Started Jun 22 06:23:48 PM PDT 24
Finished Jun 22 06:23:50 PM PDT 24
Peak memory 219876 kb
Host smart-24323b35-a293-4652-818f-fff992b2abe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861260882 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.2861260882
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.140019995
Short name T539
Test name
Test status
Simulation time 33766591 ps
CPU time 1.25 seconds
Started Jun 22 06:23:45 PM PDT 24
Finished Jun 22 06:23:47 PM PDT 24
Peak memory 217816 kb
Host smart-270105c5-6291-44b6-bb53-af01cc314e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140019995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.140019995
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.2215292234
Short name T645
Test name
Test status
Simulation time 24954719 ps
CPU time 1.18 seconds
Started Jun 22 06:23:46 PM PDT 24
Finished Jun 22 06:23:48 PM PDT 24
Peak memory 219104 kb
Host smart-baf9ac41-4e98-463b-b91b-6ad8cdc02cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215292234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2215292234
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.1883054646
Short name T477
Test name
Test status
Simulation time 36200216 ps
CPU time 1.41 seconds
Started Jun 22 06:23:44 PM PDT 24
Finished Jun 22 06:23:46 PM PDT 24
Peak memory 216496 kb
Host smart-8e68dd88-3dde-470c-8fa7-a5ed39c78ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883054646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1883054646
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.304427627
Short name T493
Test name
Test status
Simulation time 40964575 ps
CPU time 1.16 seconds
Started Jun 22 06:23:50 PM PDT 24
Finished Jun 22 06:23:51 PM PDT 24
Peak memory 219572 kb
Host smart-d8c90c9e-af25-40d6-9703-757790a9267e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304427627 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.304427627
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3602732252
Short name T901
Test name
Test status
Simulation time 75501454 ps
CPU time 1.12 seconds
Started Jun 22 06:23:44 PM PDT 24
Finished Jun 22 06:23:45 PM PDT 24
Peak memory 218000 kb
Host smart-0cdc93e1-fabe-4d82-92cc-6934c962c0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602732252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3602732252
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.2730113102
Short name T479
Test name
Test status
Simulation time 29583990 ps
CPU time 1.18 seconds
Started Jun 22 06:23:50 PM PDT 24
Finished Jun 22 06:23:52 PM PDT 24
Peak memory 219072 kb
Host smart-1a50b217-3251-4232-b82a-f10315c4be60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730113102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.2730113102
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.3604567056
Short name T763
Test name
Test status
Simulation time 105022933 ps
CPU time 1.32 seconds
Started Jun 22 06:23:51 PM PDT 24
Finished Jun 22 06:23:53 PM PDT 24
Peak memory 218956 kb
Host smart-620d0721-e28e-400f-ac80-e64aebde5ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604567056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3604567056
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.516681348
Short name T95
Test name
Test status
Simulation time 67449977 ps
CPU time 1.05 seconds
Started Jun 22 06:23:51 PM PDT 24
Finished Jun 22 06:23:52 PM PDT 24
Peak memory 217964 kb
Host smart-96d784ab-00f0-4e00-a0b5-da258a585074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516681348 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.516681348
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.1990489262
Short name T883
Test name
Test status
Simulation time 39283451 ps
CPU time 1.51 seconds
Started Jun 22 06:23:51 PM PDT 24
Finished Jun 22 06:23:53 PM PDT 24
Peak memory 216604 kb
Host smart-b8962e35-c4af-4162-b7ff-0e56bfc2cb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990489262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1990489262
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.439024511
Short name T943
Test name
Test status
Simulation time 44377236 ps
CPU time 1.16 seconds
Started Jun 22 06:23:54 PM PDT 24
Finished Jun 22 06:23:56 PM PDT 24
Peak memory 217200 kb
Host smart-8b65efa3-661a-4df3-b33b-05af8ab22878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439024511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.439024511
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.2540631938
Short name T708
Test name
Test status
Simulation time 102375390 ps
CPU time 1.26 seconds
Started Jun 22 06:23:49 PM PDT 24
Finished Jun 22 06:23:51 PM PDT 24
Peak memory 216664 kb
Host smart-213bbc0b-382b-48e4-ba73-39ab21833526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540631938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2540631938
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3910499572
Short name T615
Test name
Test status
Simulation time 25505050 ps
CPU time 1.22 seconds
Started Jun 22 06:19:13 PM PDT 24
Finished Jun 22 06:19:14 PM PDT 24
Peak memory 219136 kb
Host smart-aac6d70e-accf-4e4b-a57e-a40985e548d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910499572 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3910499572
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3528905000
Short name T743
Test name
Test status
Simulation time 20521100 ps
CPU time 0.84 seconds
Started Jun 22 06:19:13 PM PDT 24
Finished Jun 22 06:19:14 PM PDT 24
Peak memory 206076 kb
Host smart-bd6adabd-f482-4884-969f-76b73f5ba6ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528905000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3528905000
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.834686604
Short name T895
Test name
Test status
Simulation time 26390238 ps
CPU time 0.85 seconds
Started Jun 22 06:19:11 PM PDT 24
Finished Jun 22 06:19:13 PM PDT 24
Peak memory 215816 kb
Host smart-834e440a-ac78-4316-9e49-cdeb7a860f20
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834686604 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.834686604
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.2112151629
Short name T646
Test name
Test status
Simulation time 36977796 ps
CPU time 1.18 seconds
Started Jun 22 06:19:13 PM PDT 24
Finished Jun 22 06:19:15 PM PDT 24
Peak memory 223352 kb
Host smart-b266f293-65c3-4a02-b9b4-8884ff0011bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112151629 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2112151629
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.352949270
Short name T311
Test name
Test status
Simulation time 40511646 ps
CPU time 1.11 seconds
Started Jun 22 06:19:14 PM PDT 24
Finished Jun 22 06:19:15 PM PDT 24
Peak memory 216592 kb
Host smart-b8869370-5adc-43db-9dcd-cfd8d707695f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352949270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.352949270
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2540895613
Short name T660
Test name
Test status
Simulation time 23039905 ps
CPU time 0.96 seconds
Started Jun 22 06:19:13 PM PDT 24
Finished Jun 22 06:19:14 PM PDT 24
Peak memory 215076 kb
Host smart-38bfd091-f66f-4518-ad11-218cef43fc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540895613 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2540895613
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.780974818
Short name T950
Test name
Test status
Simulation time 86629439 ps
CPU time 1 seconds
Started Jun 22 06:19:13 PM PDT 24
Finished Jun 22 06:19:15 PM PDT 24
Peak memory 206444 kb
Host smart-adc9c991-c0c4-4956-9724-fce1a63337bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780974818 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.780974818
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.463104153
Short name T20
Test name
Test status
Simulation time 1083979347 ps
CPU time 8.47 seconds
Started Jun 22 06:19:14 PM PDT 24
Finished Jun 22 06:19:23 PM PDT 24
Peak memory 235744 kb
Host smart-6893971b-bbb0-4a76-8141-7ede6fea7f67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463104153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.463104153
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.896646993
Short name T371
Test name
Test status
Simulation time 19561835 ps
CPU time 1.05 seconds
Started Jun 22 06:19:07 PM PDT 24
Finished Jun 22 06:19:08 PM PDT 24
Peak memory 214728 kb
Host smart-f89e1b3e-406e-4952-bb8e-15ea3af22713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896646993 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.896646993
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.254332414
Short name T914
Test name
Test status
Simulation time 49569471 ps
CPU time 1.62 seconds
Started Jun 22 06:19:14 PM PDT 24
Finished Jun 22 06:19:16 PM PDT 24
Peak memory 214692 kb
Host smart-a20b268b-ab16-4b20-b2ea-0bc6105c33fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254332414 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.254332414
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.625182981
Short name T222
Test name
Test status
Simulation time 58440641335 ps
CPU time 365.81 seconds
Started Jun 22 06:19:14 PM PDT 24
Finished Jun 22 06:25:21 PM PDT 24
Peak memory 216468 kb
Host smart-cc97cf93-9793-41fb-8baa-643cb2d79c8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625182981 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.625182981
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.429996689
Short name T606
Test name
Test status
Simulation time 130242059 ps
CPU time 1.28 seconds
Started Jun 22 06:20:36 PM PDT 24
Finished Jun 22 06:20:38 PM PDT 24
Peak memory 217800 kb
Host smart-5529d7f4-b34d-4db3-ac25-de7b14362b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429996689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.429996689
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3875506521
Short name T408
Test name
Test status
Simulation time 40061395 ps
CPU time 1.32 seconds
Started Jun 22 06:20:47 PM PDT 24
Finished Jun 22 06:20:49 PM PDT 24
Peak memory 206276 kb
Host smart-d7fcdc7d-c9c4-4092-b5ab-6d5adaa2c9c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875506521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3875506521
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.2090968706
Short name T583
Test name
Test status
Simulation time 35016447 ps
CPU time 0.84 seconds
Started Jun 22 06:20:39 PM PDT 24
Finished Jun 22 06:20:40 PM PDT 24
Peak memory 215308 kb
Host smart-b3d376e5-ef2f-4206-abc1-1852ced67a62
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090968706 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2090968706
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.4076613397
Short name T574
Test name
Test status
Simulation time 58474496 ps
CPU time 1.18 seconds
Started Jun 22 06:20:36 PM PDT 24
Finished Jun 22 06:20:37 PM PDT 24
Peak memory 218508 kb
Host smart-0429bef6-b51d-4e1f-9e2a-2fc73e4f40e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076613397 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.4076613397
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1479462101
Short name T387
Test name
Test status
Simulation time 23327617 ps
CPU time 1.14 seconds
Started Jun 22 06:20:37 PM PDT 24
Finished Jun 22 06:20:39 PM PDT 24
Peak memory 218088 kb
Host smart-086d4463-326e-4ad8-be6a-4a2059420a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479462101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1479462101
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1676543058
Short name T239
Test name
Test status
Simulation time 34536162 ps
CPU time 1.32 seconds
Started Jun 22 06:20:38 PM PDT 24
Finished Jun 22 06:20:41 PM PDT 24
Peak memory 217672 kb
Host smart-58eb87c1-78d3-48f4-b345-5eb36a0a0ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676543058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1676543058
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.2238093466
Short name T71
Test name
Test status
Simulation time 27689437 ps
CPU time 0.93 seconds
Started Jun 22 06:20:40 PM PDT 24
Finished Jun 22 06:20:42 PM PDT 24
Peak memory 214988 kb
Host smart-b7362cf9-a6be-491c-97f3-f76953763189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238093466 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2238093466
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2585068397
Short name T338
Test name
Test status
Simulation time 34681332 ps
CPU time 0.88 seconds
Started Jun 22 06:20:39 PM PDT 24
Finished Jun 22 06:20:40 PM PDT 24
Peak memory 214628 kb
Host smart-b34311e6-d6e6-4b45-b8e6-700ac04e1987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585068397 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2585068397
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.4253024883
Short name T417
Test name
Test status
Simulation time 198863675 ps
CPU time 4.09 seconds
Started Jun 22 06:20:37 PM PDT 24
Finished Jun 22 06:20:42 PM PDT 24
Peak memory 216652 kb
Host smart-651d89c5-e65d-4cb2-b76b-b335b0ce1563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253024883 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.4253024883
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2449920310
Short name T910
Test name
Test status
Simulation time 176028329335 ps
CPU time 1626.01 seconds
Started Jun 22 06:20:38 PM PDT 24
Finished Jun 22 06:47:45 PM PDT 24
Peak memory 224192 kb
Host smart-2a9627c5-800b-46c4-a3e0-9b52db264442
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449920310 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2449920310
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1275306126
Short name T473
Test name
Test status
Simulation time 141950287 ps
CPU time 1.45 seconds
Started Jun 22 06:23:54 PM PDT 24
Finished Jun 22 06:23:56 PM PDT 24
Peak memory 218280 kb
Host smart-54e06fad-c6e2-4c9f-a6ef-17bcb424c3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275306126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1275306126
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1355526093
Short name T65
Test name
Test status
Simulation time 137754921 ps
CPU time 3.11 seconds
Started Jun 22 06:23:52 PM PDT 24
Finished Jun 22 06:23:56 PM PDT 24
Peak memory 219256 kb
Host smart-0d0d23ab-9982-4780-a49a-1b9d0d935a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355526093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1355526093
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2714037088
Short name T579
Test name
Test status
Simulation time 48440063 ps
CPU time 1.67 seconds
Started Jun 22 06:23:52 PM PDT 24
Finished Jun 22 06:23:54 PM PDT 24
Peak memory 217884 kb
Host smart-45ab7aa8-774e-4797-8213-4be83e14d4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714037088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2714037088
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2281842055
Short name T81
Test name
Test status
Simulation time 62434259 ps
CPU time 1.74 seconds
Started Jun 22 06:23:52 PM PDT 24
Finished Jun 22 06:23:54 PM PDT 24
Peak memory 217856 kb
Host smart-7cb60856-8682-41c6-b694-b1454e7a20f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281842055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2281842055
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1201132253
Short name T512
Test name
Test status
Simulation time 78201848 ps
CPU time 2.75 seconds
Started Jun 22 06:23:52 PM PDT 24
Finished Jun 22 06:23:55 PM PDT 24
Peak memory 216868 kb
Host smart-d9d496e2-ca74-45ea-940c-1f684bf6dd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201132253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1201132253
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.2883665958
Short name T372
Test name
Test status
Simulation time 41496191 ps
CPU time 1.36 seconds
Started Jun 22 06:23:52 PM PDT 24
Finished Jun 22 06:23:54 PM PDT 24
Peak memory 217968 kb
Host smart-b0eef944-782b-4261-a6aa-f5d3426f6b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883665958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.2883665958
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2866141057
Short name T284
Test name
Test status
Simulation time 76840567 ps
CPU time 1.11 seconds
Started Jun 22 06:23:52 PM PDT 24
Finished Jun 22 06:23:54 PM PDT 24
Peak memory 216708 kb
Host smart-b23061fa-c9f3-4430-891d-341798d3050a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866141057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2866141057
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2880205298
Short name T331
Test name
Test status
Simulation time 320287749 ps
CPU time 3.15 seconds
Started Jun 22 06:23:49 PM PDT 24
Finished Jun 22 06:23:52 PM PDT 24
Peak memory 217896 kb
Host smart-aa1ca290-7717-432e-8949-95722abd74c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880205298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2880205298
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2338433169
Short name T593
Test name
Test status
Simulation time 42466453 ps
CPU time 1.22 seconds
Started Jun 22 06:20:45 PM PDT 24
Finished Jun 22 06:20:47 PM PDT 24
Peak memory 218032 kb
Host smart-e81b865a-da4a-479f-896a-c7cb8f63bc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338433169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2338433169
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1104089620
Short name T648
Test name
Test status
Simulation time 25780659 ps
CPU time 1.15 seconds
Started Jun 22 06:20:46 PM PDT 24
Finished Jun 22 06:20:48 PM PDT 24
Peak memory 214368 kb
Host smart-03ea439e-7a20-42ee-9b5c-96a9028ba7e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104089620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1104089620
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.971886316
Short name T876
Test name
Test status
Simulation time 11145155 ps
CPU time 0.91 seconds
Started Jun 22 06:20:47 PM PDT 24
Finished Jun 22 06:20:49 PM PDT 24
Peak memory 215688 kb
Host smart-e384b4a8-f1d4-432b-8c15-66ab1d246835
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971886316 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.971886316
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3578224751
Short name T123
Test name
Test status
Simulation time 41039198 ps
CPU time 0.99 seconds
Started Jun 22 06:20:45 PM PDT 24
Finished Jun 22 06:20:47 PM PDT 24
Peak memory 216276 kb
Host smart-b455c841-34f3-4d06-92ea-2fdd1fffa4c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578224751 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3578224751
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.2758259204
Short name T154
Test name
Test status
Simulation time 20334714 ps
CPU time 1.18 seconds
Started Jun 22 06:20:45 PM PDT 24
Finished Jun 22 06:20:46 PM PDT 24
Peak memory 223372 kb
Host smart-a464e557-ac17-4706-b238-3dc2b9a8fddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758259204 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2758259204
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2086859613
Short name T789
Test name
Test status
Simulation time 38106457 ps
CPU time 1.45 seconds
Started Jun 22 06:20:46 PM PDT 24
Finished Jun 22 06:20:49 PM PDT 24
Peak memory 217864 kb
Host smart-a8a42b34-3112-4543-855b-2b5da9b9e6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086859613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2086859613
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3583320958
Short name T589
Test name
Test status
Simulation time 33244610 ps
CPU time 1.09 seconds
Started Jun 22 06:20:46 PM PDT 24
Finished Jun 22 06:20:48 PM PDT 24
Peak memory 223364 kb
Host smart-c1880636-f756-4ce3-94d0-32f13fbef69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583320958 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3583320958
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3645541045
Short name T815
Test name
Test status
Simulation time 16208872 ps
CPU time 1.02 seconds
Started Jun 22 06:20:46 PM PDT 24
Finished Jun 22 06:20:48 PM PDT 24
Peak memory 214832 kb
Host smart-12de3670-e17c-4343-b482-4577ed40bd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645541045 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3645541045
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.278671215
Short name T543
Test name
Test status
Simulation time 239874676 ps
CPU time 1.99 seconds
Started Jun 22 06:20:47 PM PDT 24
Finished Jun 22 06:20:50 PM PDT 24
Peak memory 216476 kb
Host smart-07908e2e-363b-445d-ba98-7aff23acd60d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278671215 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.278671215
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2560984345
Short name T74
Test name
Test status
Simulation time 134143535318 ps
CPU time 1563.61 seconds
Started Jun 22 06:20:46 PM PDT 24
Finished Jun 22 06:46:50 PM PDT 24
Peak memory 224244 kb
Host smart-d642b4b5-fe53-41c1-b29e-f89d5565ac3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560984345 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2560984345
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1426099721
Short name T489
Test name
Test status
Simulation time 52299318 ps
CPU time 1.2 seconds
Started Jun 22 06:23:53 PM PDT 24
Finished Jun 22 06:23:54 PM PDT 24
Peak memory 216568 kb
Host smart-cc1b6e14-0108-4741-a22b-465517a16178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426099721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1426099721
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2992669047
Short name T694
Test name
Test status
Simulation time 75713355 ps
CPU time 1.82 seconds
Started Jun 22 06:23:49 PM PDT 24
Finished Jun 22 06:23:52 PM PDT 24
Peak memory 217828 kb
Host smart-fcb457a1-ef11-4786-8b9d-b1c9591ab018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992669047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2992669047
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3184369678
Short name T744
Test name
Test status
Simulation time 36788050 ps
CPU time 1.32 seconds
Started Jun 22 06:23:52 PM PDT 24
Finished Jun 22 06:23:54 PM PDT 24
Peak memory 217812 kb
Host smart-9540e995-bd81-4531-bddc-ebc51308c8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184369678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3184369678
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.636131176
Short name T929
Test name
Test status
Simulation time 62855082 ps
CPU time 1.48 seconds
Started Jun 22 06:23:50 PM PDT 24
Finished Jun 22 06:23:52 PM PDT 24
Peak memory 217884 kb
Host smart-ad88375e-33fc-49ee-9daa-500bd5613ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636131176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.636131176
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1178629122
Short name T317
Test name
Test status
Simulation time 98162483 ps
CPU time 1.19 seconds
Started Jun 22 06:23:52 PM PDT 24
Finished Jun 22 06:23:54 PM PDT 24
Peak memory 216884 kb
Host smart-f4b2389b-d7ad-4f42-af2a-a2569f122b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178629122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1178629122
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1008534886
Short name T737
Test name
Test status
Simulation time 157875361 ps
CPU time 1.19 seconds
Started Jun 22 06:23:55 PM PDT 24
Finished Jun 22 06:23:56 PM PDT 24
Peak memory 216604 kb
Host smart-7fd87687-22aa-4344-bbd0-1aa47c68d282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008534886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1008534886
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.400408263
Short name T501
Test name
Test status
Simulation time 42998788 ps
CPU time 1.38 seconds
Started Jun 22 06:23:52 PM PDT 24
Finished Jun 22 06:23:54 PM PDT 24
Peak memory 217680 kb
Host smart-10e2e98a-95fc-41f5-b066-d952db7f12b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400408263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.400408263
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.347004169
Short name T324
Test name
Test status
Simulation time 25361751 ps
CPU time 1.16 seconds
Started Jun 22 06:23:54 PM PDT 24
Finished Jun 22 06:23:56 PM PDT 24
Peak memory 216572 kb
Host smart-a4abb021-78f0-422a-a92d-44691473190c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347004169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.347004169
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2171313008
Short name T785
Test name
Test status
Simulation time 93666778 ps
CPU time 1.17 seconds
Started Jun 22 06:23:50 PM PDT 24
Finished Jun 22 06:23:52 PM PDT 24
Peak memory 216652 kb
Host smart-9202cbce-e5c8-4e02-b4c5-8f4a1fe37cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171313008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2171313008
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1878292735
Short name T73
Test name
Test status
Simulation time 45891031 ps
CPU time 1.29 seconds
Started Jun 22 06:23:59 PM PDT 24
Finished Jun 22 06:24:01 PM PDT 24
Peak memory 218152 kb
Host smart-379e270d-a4d2-4e8e-94c9-e23cc6e09ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878292735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1878292735
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1829027311
Short name T133
Test name
Test status
Simulation time 28692178 ps
CPU time 1.3 seconds
Started Jun 22 06:20:48 PM PDT 24
Finished Jun 22 06:20:50 PM PDT 24
Peak memory 219744 kb
Host smart-1d06b0c6-7ce9-4ac2-83b4-2f1c1a156b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829027311 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1829027311
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1233845078
Short name T377
Test name
Test status
Simulation time 25216019 ps
CPU time 0.91 seconds
Started Jun 22 06:20:49 PM PDT 24
Finished Jun 22 06:20:50 PM PDT 24
Peak memory 206128 kb
Host smart-cca877e3-5ccc-4a2c-8dcb-f7c6b8de0d74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233845078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1233845078
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1796132031
Short name T171
Test name
Test status
Simulation time 22600512 ps
CPU time 0.83 seconds
Started Jun 22 06:20:47 PM PDT 24
Finished Jun 22 06:20:49 PM PDT 24
Peak memory 215688 kb
Host smart-0f606f9d-617e-471e-aae1-414dead2acf8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796132031 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1796132031
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_err.1182129982
Short name T526
Test name
Test status
Simulation time 32271333 ps
CPU time 1.01 seconds
Started Jun 22 06:20:47 PM PDT 24
Finished Jun 22 06:20:49 PM PDT 24
Peak memory 223200 kb
Host smart-211020c6-aa95-4d91-b6cb-f25d33d08a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182129982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1182129982
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3490322243
Short name T917
Test name
Test status
Simulation time 102298543 ps
CPU time 1.36 seconds
Started Jun 22 06:20:46 PM PDT 24
Finished Jun 22 06:20:48 PM PDT 24
Peak memory 218080 kb
Host smart-54d87a7f-17a8-4586-9071-52bdfbe28f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490322243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3490322243
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2244680277
Short name T740
Test name
Test status
Simulation time 39306819 ps
CPU time 1.02 seconds
Started Jun 22 06:20:46 PM PDT 24
Finished Jun 22 06:20:47 PM PDT 24
Peak memory 223400 kb
Host smart-0278f0b7-748b-40c9-9173-f28e7ce2d800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244680277 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2244680277
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2191523099
Short name T522
Test name
Test status
Simulation time 25927116 ps
CPU time 0.96 seconds
Started Jun 22 06:20:47 PM PDT 24
Finished Jun 22 06:20:49 PM PDT 24
Peak memory 214624 kb
Host smart-2101cacc-a2a7-4070-98e1-0a26261ffc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191523099 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2191523099
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.938212195
Short name T691
Test name
Test status
Simulation time 81494198 ps
CPU time 2.19 seconds
Started Jun 22 06:20:47 PM PDT 24
Finished Jun 22 06:20:50 PM PDT 24
Peak memory 214640 kb
Host smart-8c4dbf63-3d89-4d6a-9d6f-3d89a804cff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938212195 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.938212195
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1570526393
Short name T840
Test name
Test status
Simulation time 112126104278 ps
CPU time 694.46 seconds
Started Jun 22 06:20:45 PM PDT 24
Finished Jun 22 06:32:21 PM PDT 24
Peak memory 218880 kb
Host smart-9a6c8b21-a93b-4fbc-9ed5-e120714b165e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570526393 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1570526393
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1910583880
Short name T441
Test name
Test status
Simulation time 51340854 ps
CPU time 1.24 seconds
Started Jun 22 06:23:58 PM PDT 24
Finished Jun 22 06:23:59 PM PDT 24
Peak memory 216640 kb
Host smart-2bb6638a-effe-42e8-915d-b926927b11b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910583880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1910583880
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.898799914
Short name T330
Test name
Test status
Simulation time 49180220 ps
CPU time 1.24 seconds
Started Jun 22 06:23:59 PM PDT 24
Finished Jun 22 06:24:01 PM PDT 24
Peak memory 216664 kb
Host smart-67e1bd1a-aa77-4f17-b9d0-910ad1843ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898799914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.898799914
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2822087549
Short name T316
Test name
Test status
Simulation time 41130244 ps
CPU time 1.36 seconds
Started Jun 22 06:24:05 PM PDT 24
Finished Jun 22 06:24:08 PM PDT 24
Peak memory 216724 kb
Host smart-09ccde51-615f-48cf-92e9-bb0652575328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822087549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2822087549
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1356224622
Short name T75
Test name
Test status
Simulation time 43001789 ps
CPU time 1.65 seconds
Started Jun 22 06:24:04 PM PDT 24
Finished Jun 22 06:24:06 PM PDT 24
Peak memory 216772 kb
Host smart-47ec5d77-f438-4b95-9239-c646a2daa424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356224622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1356224622
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.976548351
Short name T826
Test name
Test status
Simulation time 92558562 ps
CPU time 1.16 seconds
Started Jun 22 06:23:57 PM PDT 24
Finished Jun 22 06:23:59 PM PDT 24
Peak memory 216544 kb
Host smart-7fd1ab5f-64bc-44b4-bd8a-5b78f4d27c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976548351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.976548351
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2342910046
Short name T802
Test name
Test status
Simulation time 59790060 ps
CPU time 1.12 seconds
Started Jun 22 06:23:58 PM PDT 24
Finished Jun 22 06:24:00 PM PDT 24
Peak memory 216684 kb
Host smart-63816f38-9c40-467b-a2cb-4ecbee609465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342910046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2342910046
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.4155446123
Short name T983
Test name
Test status
Simulation time 49040640 ps
CPU time 1.6 seconds
Started Jun 22 06:23:58 PM PDT 24
Finished Jun 22 06:24:00 PM PDT 24
Peak memory 219300 kb
Host smart-77237a66-7cf7-4b75-ae91-5d30a6585d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155446123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.4155446123
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.127594093
Short name T941
Test name
Test status
Simulation time 57865002 ps
CPU time 1.42 seconds
Started Jun 22 06:24:00 PM PDT 24
Finished Jun 22 06:24:02 PM PDT 24
Peak memory 218008 kb
Host smart-47ef2b24-c310-4c09-adaf-6d4b6818eb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127594093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.127594093
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.4057265045
Short name T503
Test name
Test status
Simulation time 33008852 ps
CPU time 1.35 seconds
Started Jun 22 06:23:57 PM PDT 24
Finished Jun 22 06:23:59 PM PDT 24
Peak memory 219108 kb
Host smart-04d1c556-e6d4-49fa-851d-cce66a92bfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057265045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.4057265045
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.134454015
Short name T656
Test name
Test status
Simulation time 52598160 ps
CPU time 1.25 seconds
Started Jun 22 06:23:56 PM PDT 24
Finished Jun 22 06:23:58 PM PDT 24
Peak memory 219252 kb
Host smart-f603e696-971f-4c60-95f6-e9d453375cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134454015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.134454015
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert_test.1160200673
Short name T111
Test name
Test status
Simulation time 27565427 ps
CPU time 0.91 seconds
Started Jun 22 06:20:46 PM PDT 24
Finished Jun 22 06:20:48 PM PDT 24
Peak memory 206092 kb
Host smart-01b36c78-ba8f-4c69-b285-24d8c6649339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160200673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1160200673
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3962072378
Short name T697
Test name
Test status
Simulation time 14509680 ps
CPU time 0.9 seconds
Started Jun 22 06:20:49 PM PDT 24
Finished Jun 22 06:20:51 PM PDT 24
Peak memory 215828 kb
Host smart-e358e8b8-54fd-4b62-b27f-a81cf555ea48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962072378 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3962072378
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.4168307085
Short name T788
Test name
Test status
Simulation time 98040068 ps
CPU time 1.09 seconds
Started Jun 22 06:20:47 PM PDT 24
Finished Jun 22 06:20:49 PM PDT 24
Peak memory 216288 kb
Host smart-9bc6e493-c68a-4538-ba21-cbbc11d25a17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168307085 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.4168307085
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.2962718430
Short name T52
Test name
Test status
Simulation time 19814454 ps
CPU time 1.17 seconds
Started Jun 22 06:20:47 PM PDT 24
Finished Jun 22 06:20:49 PM PDT 24
Peak memory 223396 kb
Host smart-87c61d11-887b-4156-9a6c-ba9a7c149f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962718430 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2962718430
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3495280484
Short name T530
Test name
Test status
Simulation time 49380357 ps
CPU time 1.15 seconds
Started Jun 22 06:20:45 PM PDT 24
Finished Jun 22 06:20:47 PM PDT 24
Peak memory 216624 kb
Host smart-55febe0c-8575-4898-90e2-aebf45cb8fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495280484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3495280484
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3633864920
Short name T104
Test name
Test status
Simulation time 20560259 ps
CPU time 1.09 seconds
Started Jun 22 06:20:46 PM PDT 24
Finished Jun 22 06:20:47 PM PDT 24
Peak memory 215036 kb
Host smart-8af4781e-3e22-479b-9c45-843d17506b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633864920 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3633864920
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.872970042
Short name T520
Test name
Test status
Simulation time 63024929 ps
CPU time 0.89 seconds
Started Jun 22 06:20:45 PM PDT 24
Finished Jun 22 06:20:47 PM PDT 24
Peak memory 214592 kb
Host smart-95916855-2c77-4a0b-9217-dc7e06b05243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872970042 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.872970042
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2788865153
Short name T969
Test name
Test status
Simulation time 176155170 ps
CPU time 2.26 seconds
Started Jun 22 06:20:48 PM PDT 24
Finished Jun 22 06:20:51 PM PDT 24
Peak memory 217836 kb
Host smart-828507d6-3242-43d0-b8a7-be5fa57bc50b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788865153 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2788865153
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1867072311
Short name T232
Test name
Test status
Simulation time 134686136625 ps
CPU time 597.54 seconds
Started Jun 22 06:20:46 PM PDT 24
Finished Jun 22 06:30:45 PM PDT 24
Peak memory 222976 kb
Host smart-720f92de-0095-47c6-90b8-66a7b17a893a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867072311 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1867072311
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.983764667
Short name T487
Test name
Test status
Simulation time 50508116 ps
CPU time 1.61 seconds
Started Jun 22 06:24:05 PM PDT 24
Finished Jun 22 06:24:08 PM PDT 24
Peak memory 217872 kb
Host smart-89a2de15-f244-4a03-bd06-e3e69a8ea537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983764667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.983764667
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3494056401
Short name T480
Test name
Test status
Simulation time 41894836 ps
CPU time 1.8 seconds
Started Jun 22 06:23:57 PM PDT 24
Finished Jun 22 06:23:59 PM PDT 24
Peak memory 218104 kb
Host smart-4c53162f-ef76-466e-8a60-b24e8b1390be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494056401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3494056401
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2604453237
Short name T528
Test name
Test status
Simulation time 103824718 ps
CPU time 1.96 seconds
Started Jun 22 06:23:57 PM PDT 24
Finished Jun 22 06:24:00 PM PDT 24
Peak memory 218352 kb
Host smart-d46e81fe-aa69-46e9-9c21-8802f68a0442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604453237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2604453237
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.427131821
Short name T344
Test name
Test status
Simulation time 25862279 ps
CPU time 1.19 seconds
Started Jun 22 06:23:58 PM PDT 24
Finished Jun 22 06:24:00 PM PDT 24
Peak memory 216508 kb
Host smart-f9c172ed-7c16-4a0e-91ed-d70d39e11e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427131821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.427131821
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.564905447
Short name T298
Test name
Test status
Simulation time 88463568 ps
CPU time 1.35 seconds
Started Jun 22 06:23:58 PM PDT 24
Finished Jun 22 06:24:01 PM PDT 24
Peak memory 216788 kb
Host smart-aede2729-2913-46b0-95a7-dfc262d08825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564905447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.564905447
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.472647816
Short name T781
Test name
Test status
Simulation time 61728454 ps
CPU time 1.46 seconds
Started Jun 22 06:24:05 PM PDT 24
Finished Jun 22 06:24:08 PM PDT 24
Peak memory 216704 kb
Host smart-a72af034-d7f9-4636-99c8-bdae86bfb614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472647816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.472647816
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2244554946
Short name T448
Test name
Test status
Simulation time 53550446 ps
CPU time 1.34 seconds
Started Jun 22 06:23:57 PM PDT 24
Finished Jun 22 06:23:59 PM PDT 24
Peak memory 219428 kb
Host smart-2191f60d-70a7-4f11-9c49-0110b7a9edea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244554946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2244554946
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.398217851
Short name T291
Test name
Test status
Simulation time 88385717 ps
CPU time 1.3 seconds
Started Jun 22 06:24:01 PM PDT 24
Finished Jun 22 06:24:03 PM PDT 24
Peak memory 219112 kb
Host smart-7971b9f2-5b00-4e02-aac5-e6708daded88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398217851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.398217851
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.949926821
Short name T762
Test name
Test status
Simulation time 27983844 ps
CPU time 1.27 seconds
Started Jun 22 06:24:08 PM PDT 24
Finished Jun 22 06:24:09 PM PDT 24
Peak memory 217852 kb
Host smart-5791cc40-6707-40f8-bad5-b8baab463560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949926821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.949926821
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.4167548937
Short name T764
Test name
Test status
Simulation time 59091628 ps
CPU time 1.41 seconds
Started Jun 22 06:24:04 PM PDT 24
Finished Jun 22 06:24:06 PM PDT 24
Peak memory 218008 kb
Host smart-8c56560f-3fb6-4ad3-ba1b-7fdf18780ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167548937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.4167548937
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert_test.4038326669
Short name T405
Test name
Test status
Simulation time 19198808 ps
CPU time 0.98 seconds
Started Jun 22 06:20:54 PM PDT 24
Finished Jun 22 06:20:55 PM PDT 24
Peak memory 206076 kb
Host smart-1b3299c1-950a-4721-8b08-5675de0d1233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038326669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.4038326669
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1892021986
Short name T755
Test name
Test status
Simulation time 37899707 ps
CPU time 1.16 seconds
Started Jun 22 06:20:53 PM PDT 24
Finished Jun 22 06:20:55 PM PDT 24
Peak memory 217760 kb
Host smart-6fad72cf-a5bd-4f89-a7fc-ec46ef982a11
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892021986 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1892021986
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3612646832
Short name T751
Test name
Test status
Simulation time 30418095 ps
CPU time 0.84 seconds
Started Jun 22 06:20:55 PM PDT 24
Finished Jun 22 06:20:56 PM PDT 24
Peak memory 214556 kb
Host smart-83e544ca-c461-4514-bd2b-50d5ccfa74d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612646832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3612646832
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.344842113
Short name T794
Test name
Test status
Simulation time 189438391 ps
CPU time 1.33 seconds
Started Jun 22 06:20:54 PM PDT 24
Finished Jun 22 06:20:56 PM PDT 24
Peak memory 218180 kb
Host smart-bb593990-0ce1-4027-b800-a9b3643acb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344842113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.344842113
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.1803892366
Short name T458
Test name
Test status
Simulation time 25027629 ps
CPU time 0.95 seconds
Started Jun 22 06:20:54 PM PDT 24
Finished Jun 22 06:20:55 PM PDT 24
Peak memory 215040 kb
Host smart-6d074b1a-d7e0-4f55-b69e-bb1064c0e270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803892366 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1803892366
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2380677915
Short name T495
Test name
Test status
Simulation time 23410013 ps
CPU time 0.99 seconds
Started Jun 22 06:20:45 PM PDT 24
Finished Jun 22 06:20:47 PM PDT 24
Peak memory 214616 kb
Host smart-02991e32-1b13-487b-b6d7-4e0115eb0dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380677915 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2380677915
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.4198968662
Short name T68
Test name
Test status
Simulation time 93741300 ps
CPU time 1.52 seconds
Started Jun 22 06:20:53 PM PDT 24
Finished Jun 22 06:20:55 PM PDT 24
Peak memory 219064 kb
Host smart-f6b16461-357a-4e94-93de-b47b34ee99d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198968662 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.4198968662
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3098040108
Short name T233
Test name
Test status
Simulation time 86649492243 ps
CPU time 469.6 seconds
Started Jun 22 06:20:52 PM PDT 24
Finished Jun 22 06:28:42 PM PDT 24
Peak memory 218460 kb
Host smart-dd5f47d2-7e13-49c7-9d20-d946337abe67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098040108 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3098040108
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3714240590
Short name T546
Test name
Test status
Simulation time 81356613 ps
CPU time 1.22 seconds
Started Jun 22 06:23:58 PM PDT 24
Finished Jun 22 06:24:00 PM PDT 24
Peak memory 216748 kb
Host smart-5e094a87-02ab-4e39-9745-6a3e9d9df245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714240590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3714240590
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2152406960
Short name T294
Test name
Test status
Simulation time 65590136 ps
CPU time 1.07 seconds
Started Jun 22 06:23:57 PM PDT 24
Finished Jun 22 06:23:58 PM PDT 24
Peak memory 214744 kb
Host smart-7001214e-7d07-4230-bac9-61a5c6398e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152406960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2152406960
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2017919538
Short name T292
Test name
Test status
Simulation time 30615614 ps
CPU time 1.2 seconds
Started Jun 22 06:23:57 PM PDT 24
Finished Jun 22 06:23:58 PM PDT 24
Peak memory 219216 kb
Host smart-35b4e2a7-28f9-4b1b-9e5b-c3142615d062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017919538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2017919538
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2792212136
Short name T369
Test name
Test status
Simulation time 45366240 ps
CPU time 1.25 seconds
Started Jun 22 06:23:58 PM PDT 24
Finished Jun 22 06:24:00 PM PDT 24
Peak memory 216744 kb
Host smart-9acd70f9-e3b9-405e-8c37-3689f777930b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792212136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2792212136
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.27766716
Short name T536
Test name
Test status
Simulation time 53581402 ps
CPU time 1.1 seconds
Started Jun 22 06:24:06 PM PDT 24
Finished Jun 22 06:24:07 PM PDT 24
Peak memory 218228 kb
Host smart-afc879ac-9c26-4960-b78d-73e75db126ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27766716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.27766716
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.380467699
Short name T349
Test name
Test status
Simulation time 40787241 ps
CPU time 1.58 seconds
Started Jun 22 06:23:56 PM PDT 24
Finished Jun 22 06:23:58 PM PDT 24
Peak memory 217840 kb
Host smart-3e04495e-a1ac-4d74-b951-fe68551d245d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380467699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.380467699
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1921090586
Short name T315
Test name
Test status
Simulation time 77534721 ps
CPU time 1.16 seconds
Started Jun 22 06:23:58 PM PDT 24
Finished Jun 22 06:24:00 PM PDT 24
Peak memory 216844 kb
Host smart-70240a53-ff21-49f3-a8d6-0e32046f5c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921090586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1921090586
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.628200866
Short name T83
Test name
Test status
Simulation time 58804391 ps
CPU time 1.48 seconds
Started Jun 22 06:23:56 PM PDT 24
Finished Jun 22 06:23:58 PM PDT 24
Peak memory 216680 kb
Host smart-73f90f99-17b5-4946-b15e-da5bccca8225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628200866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.628200866
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.425711534
Short name T382
Test name
Test status
Simulation time 75936153 ps
CPU time 1.21 seconds
Started Jun 22 06:24:03 PM PDT 24
Finished Jun 22 06:24:05 PM PDT 24
Peak memory 219596 kb
Host smart-d6097cf8-595e-44ad-a353-971082c1ceaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425711534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.425711534
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3535898780
Short name T287
Test name
Test status
Simulation time 41038981 ps
CPU time 1.47 seconds
Started Jun 22 06:24:15 PM PDT 24
Finished Jun 22 06:24:17 PM PDT 24
Peak memory 217804 kb
Host smart-90d8ea27-8bc9-4ec0-bae5-7d87762b5601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535898780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3535898780
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.4182062462
Short name T433
Test name
Test status
Simulation time 42386339 ps
CPU time 1.18 seconds
Started Jun 22 06:20:55 PM PDT 24
Finished Jun 22 06:20:56 PM PDT 24
Peak memory 219336 kb
Host smart-09a98ff0-62f1-458d-ac92-63fa965a21d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182062462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.4182062462
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.60715485
Short name T730
Test name
Test status
Simulation time 51750017 ps
CPU time 0.93 seconds
Started Jun 22 06:20:53 PM PDT 24
Finished Jun 22 06:20:55 PM PDT 24
Peak memory 214696 kb
Host smart-206b2ffd-1b5b-4cde-b703-07c76e397c85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60715485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.60715485
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3748641495
Short name T464
Test name
Test status
Simulation time 79851792 ps
CPU time 1.15 seconds
Started Jun 22 06:20:55 PM PDT 24
Finished Jun 22 06:20:57 PM PDT 24
Peak memory 218656 kb
Host smart-9c62a8b1-f3f6-4727-b3ac-82cde4c30e97
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748641495 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3748641495
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1294784188
Short name T9
Test name
Test status
Simulation time 28770508 ps
CPU time 1.26 seconds
Started Jun 22 06:20:53 PM PDT 24
Finished Jun 22 06:20:54 PM PDT 24
Peak memory 219108 kb
Host smart-dd7abff1-9c5c-4d8d-a11d-ba0b46c1182f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294784188 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1294784188
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.4218150078
Short name T385
Test name
Test status
Simulation time 38337288 ps
CPU time 1.37 seconds
Started Jun 22 06:20:58 PM PDT 24
Finished Jun 22 06:20:59 PM PDT 24
Peak memory 216744 kb
Host smart-41335911-8b3a-4ecc-91a3-f95f6531f99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218150078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.4218150078
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1532709132
Short name T587
Test name
Test status
Simulation time 36604303 ps
CPU time 0.93 seconds
Started Jun 22 06:20:54 PM PDT 24
Finished Jun 22 06:20:56 PM PDT 24
Peak memory 214696 kb
Host smart-98f54184-9f47-41af-abdf-384949515766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532709132 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1532709132
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2634968803
Short name T861
Test name
Test status
Simulation time 18830828 ps
CPU time 0.97 seconds
Started Jun 22 06:20:56 PM PDT 24
Finished Jun 22 06:20:57 PM PDT 24
Peak memory 214624 kb
Host smart-9a4e75ef-96a1-4611-8761-304fe5be3666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634968803 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2634968803
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2408705415
Short name T711
Test name
Test status
Simulation time 353352135 ps
CPU time 7.08 seconds
Started Jun 22 06:20:52 PM PDT 24
Finished Jun 22 06:21:00 PM PDT 24
Peak memory 214612 kb
Host smart-642487e6-a5cc-446b-b923-e6468c929328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408705415 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2408705415
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1218445175
Short name T500
Test name
Test status
Simulation time 61727022362 ps
CPU time 752.58 seconds
Started Jun 22 06:20:57 PM PDT 24
Finished Jun 22 06:33:30 PM PDT 24
Peak memory 217688 kb
Host smart-c0107559-9838-4713-89a8-1278a54ff5ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218445175 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1218445175
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3611148179
Short name T786
Test name
Test status
Simulation time 276838774 ps
CPU time 3.79 seconds
Started Jun 22 06:24:07 PM PDT 24
Finished Jun 22 06:24:11 PM PDT 24
Peak memory 219628 kb
Host smart-3c13e341-d064-4910-9b88-42a6a461d948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611148179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3611148179
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1482911477
Short name T851
Test name
Test status
Simulation time 59416934 ps
CPU time 1.35 seconds
Started Jun 22 06:24:15 PM PDT 24
Finished Jun 22 06:24:17 PM PDT 24
Peak memory 217680 kb
Host smart-a051933e-f0e8-46f7-a945-9aab661e2b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482911477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1482911477
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2760025489
Short name T651
Test name
Test status
Simulation time 72309598 ps
CPU time 1.12 seconds
Started Jun 22 06:24:05 PM PDT 24
Finished Jun 22 06:24:07 PM PDT 24
Peak memory 216768 kb
Host smart-e1a9182d-deb3-4212-87f7-b9195aab9bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760025489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2760025489
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1753618696
Short name T452
Test name
Test status
Simulation time 73468721 ps
CPU time 1.07 seconds
Started Jun 22 06:24:07 PM PDT 24
Finished Jun 22 06:24:09 PM PDT 24
Peak memory 216728 kb
Host smart-79c9eac6-f6ab-421f-85b1-8e00a3b919b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753618696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1753618696
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2803455070
Short name T310
Test name
Test status
Simulation time 36912930 ps
CPU time 1.22 seconds
Started Jun 22 06:24:15 PM PDT 24
Finished Jun 22 06:24:17 PM PDT 24
Peak memory 219368 kb
Host smart-221105ce-7c5f-4824-bf72-6b484b34b1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803455070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2803455070
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1549019288
Short name T14
Test name
Test status
Simulation time 48887860 ps
CPU time 1.24 seconds
Started Jun 22 06:24:05 PM PDT 24
Finished Jun 22 06:24:07 PM PDT 24
Peak memory 219028 kb
Host smart-1f30557f-5bae-46c7-8d0e-3d6e4f145657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549019288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1549019288
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.888785114
Short name T3
Test name
Test status
Simulation time 75328815 ps
CPU time 1.63 seconds
Started Jun 22 06:24:07 PM PDT 24
Finished Jun 22 06:24:09 PM PDT 24
Peak memory 214588 kb
Host smart-f80c7b94-3c66-4223-b661-84f75066ea70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888785114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.888785114
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1030973290
Short name T545
Test name
Test status
Simulation time 43995754 ps
CPU time 1.5 seconds
Started Jun 22 06:24:05 PM PDT 24
Finished Jun 22 06:24:08 PM PDT 24
Peak memory 218500 kb
Host smart-fee6b717-01f3-4f1f-8806-dd3396903145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030973290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1030973290
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3203490756
Short name T774
Test name
Test status
Simulation time 48115144 ps
CPU time 1.66 seconds
Started Jun 22 06:24:15 PM PDT 24
Finished Jun 22 06:24:17 PM PDT 24
Peak memory 217572 kb
Host smart-70f6f9b3-1b5b-4647-94a8-f4078b9a4a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203490756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3203490756
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.209133140
Short name T549
Test name
Test status
Simulation time 30051120 ps
CPU time 1.29 seconds
Started Jun 22 06:24:06 PM PDT 24
Finished Jun 22 06:24:08 PM PDT 24
Peak memory 216572 kb
Host smart-73483ae7-7f3b-4770-ae84-052312067724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209133140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.209133140
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3463616117
Short name T887
Test name
Test status
Simulation time 27643068 ps
CPU time 1.32 seconds
Started Jun 22 06:20:55 PM PDT 24
Finished Jun 22 06:20:57 PM PDT 24
Peak memory 217816 kb
Host smart-1d977ea2-8f15-4312-8e94-f3fe95020ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463616117 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3463616117
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2250921331
Short name T976
Test name
Test status
Simulation time 31670789 ps
CPU time 0.82 seconds
Started Jun 22 06:21:08 PM PDT 24
Finished Jun 22 06:21:09 PM PDT 24
Peak memory 204480 kb
Host smart-6e736d15-63bf-4a2d-b0fc-45dacd39464c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250921331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2250921331
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1654221161
Short name T185
Test name
Test status
Simulation time 26916926 ps
CPU time 0.86 seconds
Started Jun 22 06:20:58 PM PDT 24
Finished Jun 22 06:21:00 PM PDT 24
Peak memory 215668 kb
Host smart-acef23ea-0aaf-452b-88cc-be1134d6e90b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654221161 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1654221161
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3101821279
Short name T908
Test name
Test status
Simulation time 54192515 ps
CPU time 1.17 seconds
Started Jun 22 06:21:00 PM PDT 24
Finished Jun 22 06:21:02 PM PDT 24
Peak memory 218040 kb
Host smart-1efdd8d5-fe65-4098-834a-54e644621dea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101821279 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3101821279
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1202745670
Short name T598
Test name
Test status
Simulation time 91715631 ps
CPU time 1.13 seconds
Started Jun 22 06:20:54 PM PDT 24
Finished Jun 22 06:20:56 PM PDT 24
Peak memory 218952 kb
Host smart-8d61f801-86cf-4b5e-bb35-3594e19c94b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202745670 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1202745670
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1744200347
Short name T351
Test name
Test status
Simulation time 31440201 ps
CPU time 1.39 seconds
Started Jun 22 06:20:55 PM PDT 24
Finished Jun 22 06:20:57 PM PDT 24
Peak memory 217860 kb
Host smart-45ea1400-aa86-4a4c-877c-c5f0df282db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744200347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1744200347
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1425433936
Short name T34
Test name
Test status
Simulation time 25412264 ps
CPU time 1 seconds
Started Jun 22 06:20:54 PM PDT 24
Finished Jun 22 06:20:56 PM PDT 24
Peak memory 214980 kb
Host smart-23eeec31-2ce2-486a-9afd-ba5c6f8bb730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425433936 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1425433936
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.1347212502
Short name T449
Test name
Test status
Simulation time 69287033 ps
CPU time 0.94 seconds
Started Jun 22 06:20:54 PM PDT 24
Finished Jun 22 06:20:55 PM PDT 24
Peak memory 214636 kb
Host smart-09dffc17-ded2-4008-8dbb-728e39bc6440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347212502 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1347212502
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.533017223
Short name T684
Test name
Test status
Simulation time 86951108 ps
CPU time 2.15 seconds
Started Jun 22 06:20:58 PM PDT 24
Finished Jun 22 06:21:00 PM PDT 24
Peak memory 217808 kb
Host smart-a0bc1179-5146-40b4-9065-94d430192850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533017223 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.533017223
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2423069205
Short name T881
Test name
Test status
Simulation time 145972716783 ps
CPU time 1707.68 seconds
Started Jun 22 06:20:56 PM PDT 24
Finished Jun 22 06:49:24 PM PDT 24
Peak memory 224668 kb
Host smart-0ce414e7-fcd5-494a-99c5-7835fe93ef47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423069205 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2423069205
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1390569480
Short name T953
Test name
Test status
Simulation time 73465391 ps
CPU time 1.82 seconds
Started Jun 22 06:24:06 PM PDT 24
Finished Jun 22 06:24:08 PM PDT 24
Peak memory 219420 kb
Host smart-a97d69c1-092f-4e04-adc0-eff929edadd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390569480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1390569480
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2981884163
Short name T632
Test name
Test status
Simulation time 55141810 ps
CPU time 1.49 seconds
Started Jun 22 06:24:05 PM PDT 24
Finished Jun 22 06:24:07 PM PDT 24
Peak memory 217624 kb
Host smart-5999a03b-673e-458c-a5b8-36ce12079396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981884163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2981884163
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.4219022657
Short name T874
Test name
Test status
Simulation time 46199333 ps
CPU time 1.12 seconds
Started Jun 22 06:24:05 PM PDT 24
Finished Jun 22 06:24:07 PM PDT 24
Peak memory 216616 kb
Host smart-7a6142af-668f-471a-9202-abb52ffcee77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219022657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.4219022657
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.289976036
Short name T616
Test name
Test status
Simulation time 29204359 ps
CPU time 1.44 seconds
Started Jun 22 06:24:05 PM PDT 24
Finished Jun 22 06:24:07 PM PDT 24
Peak memory 216764 kb
Host smart-a313c7fb-7d1d-4236-8b35-31f9a7f1f9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289976036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.289976036
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2024968352
Short name T514
Test name
Test status
Simulation time 57449879 ps
CPU time 0.94 seconds
Started Jun 22 06:24:08 PM PDT 24
Finished Jun 22 06:24:09 PM PDT 24
Peak memory 216560 kb
Host smart-8d085215-ce4d-49f4-ab4f-a0154ccf4949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024968352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2024968352
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2818640246
Short name T649
Test name
Test status
Simulation time 41299399 ps
CPU time 1.15 seconds
Started Jun 22 06:24:05 PM PDT 24
Finished Jun 22 06:24:07 PM PDT 24
Peak memory 216624 kb
Host smart-8c5899f2-6490-4dba-a077-a6e42486b7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818640246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2818640246
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2419295304
Short name T741
Test name
Test status
Simulation time 30307926 ps
CPU time 1.38 seconds
Started Jun 22 06:24:06 PM PDT 24
Finished Jun 22 06:24:08 PM PDT 24
Peak memory 217896 kb
Host smart-1040c426-acdc-4b8d-9bcc-f078f0ff8922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419295304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2419295304
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1484028591
Short name T360
Test name
Test status
Simulation time 46296947 ps
CPU time 1.18 seconds
Started Jun 22 06:24:06 PM PDT 24
Finished Jun 22 06:24:08 PM PDT 24
Peak memory 216592 kb
Host smart-8f422639-4243-408b-a991-71c4eb4efa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484028591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1484028591
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.521439141
Short name T453
Test name
Test status
Simulation time 112508799 ps
CPU time 2.25 seconds
Started Jun 22 06:24:15 PM PDT 24
Finished Jun 22 06:24:18 PM PDT 24
Peak memory 217772 kb
Host smart-729eb135-9375-4c1c-a634-6ac3d891ccca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521439141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.521439141
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.205983806
Short name T241
Test name
Test status
Simulation time 102681480 ps
CPU time 1.36 seconds
Started Jun 22 06:21:01 PM PDT 24
Finished Jun 22 06:21:03 PM PDT 24
Peak memory 215068 kb
Host smart-ae41ddf9-dc45-46cd-a637-ca0789324757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205983806 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.205983806
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1834754323
Short name T728
Test name
Test status
Simulation time 29808852 ps
CPU time 0.89 seconds
Started Jun 22 06:21:00 PM PDT 24
Finished Jun 22 06:21:02 PM PDT 24
Peak memory 214160 kb
Host smart-d58fd2e5-351b-446e-9a5b-21a4d981ff31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834754323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1834754323
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.4205056533
Short name T155
Test name
Test status
Simulation time 21538361 ps
CPU time 0.89 seconds
Started Jun 22 06:21:00 PM PDT 24
Finished Jun 22 06:21:02 PM PDT 24
Peak memory 214844 kb
Host smart-33533154-819a-4d75-8780-0195d73f8520
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205056533 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.4205056533
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.376379675
Short name T144
Test name
Test status
Simulation time 29302067 ps
CPU time 1.24 seconds
Started Jun 22 06:21:02 PM PDT 24
Finished Jun 22 06:21:04 PM PDT 24
Peak memory 216256 kb
Host smart-a72755ee-034e-4fe5-a28c-f088340074c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376379675 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.376379675
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2842812373
Short name T343
Test name
Test status
Simulation time 92905300 ps
CPU time 1.32 seconds
Started Jun 22 06:21:01 PM PDT 24
Finished Jun 22 06:21:03 PM PDT 24
Peak memory 219244 kb
Host smart-b65ae26a-7bdf-4e8c-a2e9-5bb4ddd294b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842812373 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2842812373
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3716267206
Short name T367
Test name
Test status
Simulation time 246153869 ps
CPU time 1.59 seconds
Started Jun 22 06:21:01 PM PDT 24
Finished Jun 22 06:21:03 PM PDT 24
Peak memory 218272 kb
Host smart-c4bbc8f4-f3e3-421a-981a-c3bfc0313839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716267206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3716267206
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.957158563
Short name T696
Test name
Test status
Simulation time 40797717 ps
CPU time 0.9 seconds
Started Jun 22 06:20:59 PM PDT 24
Finished Jun 22 06:21:01 PM PDT 24
Peak memory 215044 kb
Host smart-7eac0641-0480-404e-afd0-b69d013b6878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957158563 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.957158563
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2121799679
Short name T822
Test name
Test status
Simulation time 16631756 ps
CPU time 1.06 seconds
Started Jun 22 06:21:00 PM PDT 24
Finished Jun 22 06:21:01 PM PDT 24
Peak memory 214644 kb
Host smart-d221f7f6-c316-42d4-9637-05d683d57c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121799679 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2121799679
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2492203724
Short name T547
Test name
Test status
Simulation time 134003855 ps
CPU time 1.46 seconds
Started Jun 22 06:21:00 PM PDT 24
Finished Jun 22 06:21:02 PM PDT 24
Peak memory 216716 kb
Host smart-c59f0dd1-3fcc-4307-80a0-568d7d183d09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492203724 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2492203724
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3410155561
Short name T231
Test name
Test status
Simulation time 15268179188 ps
CPU time 358.64 seconds
Started Jun 22 06:21:01 PM PDT 24
Finished Jun 22 06:27:01 PM PDT 24
Peak memory 216732 kb
Host smart-3e0a31f2-ec48-4d8f-bda9-d9800a7b79e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410155561 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3410155561
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.477966943
Short name T809
Test name
Test status
Simulation time 183867276 ps
CPU time 1.48 seconds
Started Jun 22 06:24:05 PM PDT 24
Finished Jun 22 06:24:07 PM PDT 24
Peak memory 217924 kb
Host smart-083023d6-8637-4e8c-a0ad-cfd28094080d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477966943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.477966943
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.40424073
Short name T988
Test name
Test status
Simulation time 119759532 ps
CPU time 1.47 seconds
Started Jun 22 06:24:12 PM PDT 24
Finished Jun 22 06:24:14 PM PDT 24
Peak memory 218224 kb
Host smart-093af45f-014f-4574-bd16-31abb1133b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40424073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.40424073
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.731053617
Short name T909
Test name
Test status
Simulation time 119475136 ps
CPU time 1.54 seconds
Started Jun 22 06:24:13 PM PDT 24
Finished Jun 22 06:24:15 PM PDT 24
Peak memory 218288 kb
Host smart-7a1c4220-4035-48c2-ad8d-3b9d5f530a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731053617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.731053617
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1958050043
Short name T978
Test name
Test status
Simulation time 47582696 ps
CPU time 1.52 seconds
Started Jun 22 06:24:12 PM PDT 24
Finished Jun 22 06:24:14 PM PDT 24
Peak memory 217980 kb
Host smart-18966f93-ef48-4223-97c8-0d04dd20bf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958050043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1958050043
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1893575221
Short name T46
Test name
Test status
Simulation time 41507903 ps
CPU time 1.5 seconds
Started Jun 22 06:24:13 PM PDT 24
Finished Jun 22 06:24:15 PM PDT 24
Peak memory 218084 kb
Host smart-f054421a-e403-4e54-a181-0542baaebb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893575221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1893575221
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3982789797
Short name T23
Test name
Test status
Simulation time 84445096 ps
CPU time 3.17 seconds
Started Jun 22 06:24:12 PM PDT 24
Finished Jun 22 06:24:16 PM PDT 24
Peak memory 219532 kb
Host smart-dd3d4941-e636-45aa-903d-89ed222a17c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982789797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3982789797
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2174295357
Short name T799
Test name
Test status
Simulation time 106750843 ps
CPU time 1.56 seconds
Started Jun 22 06:24:12 PM PDT 24
Finished Jun 22 06:24:14 PM PDT 24
Peak memory 217852 kb
Host smart-34f3a4ce-efd2-49dd-93b7-cc48a1ab7186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174295357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2174295357
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2115436741
Short name T362
Test name
Test status
Simulation time 52918980 ps
CPU time 1.34 seconds
Started Jun 22 06:24:12 PM PDT 24
Finished Jun 22 06:24:14 PM PDT 24
Peak memory 216696 kb
Host smart-23e358fc-76cb-46eb-9893-620d652a0494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115436741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2115436741
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2474481063
Short name T868
Test name
Test status
Simulation time 177764521 ps
CPU time 1.38 seconds
Started Jun 22 06:24:12 PM PDT 24
Finished Jun 22 06:24:14 PM PDT 24
Peak memory 218208 kb
Host smart-b4508b0e-a06d-4dae-b9ca-9753a0fe9465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474481063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2474481063
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.4270684108
Short name T302
Test name
Test status
Simulation time 51959281 ps
CPU time 1.69 seconds
Started Jun 22 06:24:11 PM PDT 24
Finished Jun 22 06:24:13 PM PDT 24
Peak memory 217760 kb
Host smart-61c6201d-8af2-4de9-888a-5fa369257433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270684108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.4270684108
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.562009747
Short name T967
Test name
Test status
Simulation time 26587465 ps
CPU time 1.16 seconds
Started Jun 22 06:21:11 PM PDT 24
Finished Jun 22 06:21:12 PM PDT 24
Peak memory 218032 kb
Host smart-dc7af95d-26fc-4c5c-9d44-08ee0504c7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562009747 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.562009747
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3360019822
Short name T510
Test name
Test status
Simulation time 22758794 ps
CPU time 0.96 seconds
Started Jun 22 06:21:10 PM PDT 24
Finished Jun 22 06:21:11 PM PDT 24
Peak memory 206092 kb
Host smart-1b967937-91e6-41a4-bc8b-a3ce704e136c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360019822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3360019822
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2399098684
Short name T801
Test name
Test status
Simulation time 10510323 ps
CPU time 0.85 seconds
Started Jun 22 06:21:11 PM PDT 24
Finished Jun 22 06:21:12 PM PDT 24
Peak memory 215324 kb
Host smart-a48e5af1-216c-43b0-b6b2-ace90a40e2e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399098684 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2399098684
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.4008016233
Short name T848
Test name
Test status
Simulation time 29811840 ps
CPU time 1.11 seconds
Started Jun 22 06:21:10 PM PDT 24
Finished Jun 22 06:21:11 PM PDT 24
Peak memory 217608 kb
Host smart-041b7ae0-e680-4d11-b62e-d8f1d933532b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008016233 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.4008016233
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.710231025
Short name T956
Test name
Test status
Simulation time 20559706 ps
CPU time 1.13 seconds
Started Jun 22 06:21:25 PM PDT 24
Finished Jun 22 06:21:27 PM PDT 24
Peak memory 219100 kb
Host smart-bdf5198e-c2ec-4164-943d-fa1445394cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710231025 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.710231025
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3058214212
Short name T293
Test name
Test status
Simulation time 40030387 ps
CPU time 1.43 seconds
Started Jun 22 06:21:01 PM PDT 24
Finished Jun 22 06:21:04 PM PDT 24
Peak memory 214616 kb
Host smart-c829e024-57e9-49fa-9763-bc6098da4e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058214212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3058214212
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3865482064
Short name T37
Test name
Test status
Simulation time 26903285 ps
CPU time 0.95 seconds
Started Jun 22 06:21:09 PM PDT 24
Finished Jun 22 06:21:11 PM PDT 24
Peak memory 215128 kb
Host smart-dec46264-56be-4746-b180-8b1148a270b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865482064 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3865482064
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3210242440
Short name T758
Test name
Test status
Simulation time 37943276 ps
CPU time 0.99 seconds
Started Jun 22 06:21:00 PM PDT 24
Finished Jun 22 06:21:02 PM PDT 24
Peak memory 214644 kb
Host smart-d9093191-2bfc-4828-becf-d586766d4e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210242440 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3210242440
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1777905030
Short name T235
Test name
Test status
Simulation time 789979342 ps
CPU time 6.1 seconds
Started Jun 22 06:21:01 PM PDT 24
Finished Jun 22 06:21:07 PM PDT 24
Peak memory 219360 kb
Host smart-785261aa-6d29-43c7-857b-e945b810083f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777905030 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1777905030
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1188579710
Short name T986
Test name
Test status
Simulation time 54791847985 ps
CPU time 651.7 seconds
Started Jun 22 06:21:11 PM PDT 24
Finished Jun 22 06:32:03 PM PDT 24
Peak memory 218296 kb
Host smart-20bb3476-e3e5-4d47-b192-6d4a8124f5ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188579710 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1188579710
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.710342239
Short name T715
Test name
Test status
Simulation time 181065011 ps
CPU time 1.24 seconds
Started Jun 22 06:24:13 PM PDT 24
Finished Jun 22 06:24:15 PM PDT 24
Peak memory 216744 kb
Host smart-e100edea-e3cb-4d11-9c81-21ba240875f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710342239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.710342239
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.203943527
Short name T577
Test name
Test status
Simulation time 113946175 ps
CPU time 1.04 seconds
Started Jun 22 06:24:12 PM PDT 24
Finished Jun 22 06:24:13 PM PDT 24
Peak memory 216708 kb
Host smart-01aa4c03-749a-4432-8221-a07a45ce142d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203943527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.203943527
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1934310951
Short name T951
Test name
Test status
Simulation time 64395049 ps
CPU time 1.42 seconds
Started Jun 22 06:24:12 PM PDT 24
Finished Jun 22 06:24:14 PM PDT 24
Peak memory 217972 kb
Host smart-382031a8-d157-46c9-a231-5861f931cef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934310951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1934310951
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2345169139
Short name T987
Test name
Test status
Simulation time 31005894 ps
CPU time 1.55 seconds
Started Jun 22 06:24:13 PM PDT 24
Finished Jun 22 06:24:15 PM PDT 24
Peak memory 217896 kb
Host smart-ec166b60-5725-4052-a55f-df23747bbebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345169139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2345169139
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3212939581
Short name T878
Test name
Test status
Simulation time 90868565 ps
CPU time 1.36 seconds
Started Jun 22 06:24:13 PM PDT 24
Finished Jun 22 06:24:15 PM PDT 24
Peak memory 217808 kb
Host smart-2a4acd94-01d5-4206-9de8-a3acb4613eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212939581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3212939581
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2081641477
Short name T657
Test name
Test status
Simulation time 47829886 ps
CPU time 1.35 seconds
Started Jun 22 06:24:13 PM PDT 24
Finished Jun 22 06:24:15 PM PDT 24
Peak memory 217952 kb
Host smart-fc8ddde0-8709-4b01-bad6-68ccfa35766d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081641477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2081641477
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2836708539
Short name T27
Test name
Test status
Simulation time 85574233 ps
CPU time 1.23 seconds
Started Jun 22 06:24:13 PM PDT 24
Finished Jun 22 06:24:14 PM PDT 24
Peak memory 216596 kb
Host smart-97e9ebf9-0d5b-4b15-a4f1-9c25b0a025db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836708539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2836708539
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1755846406
Short name T431
Test name
Test status
Simulation time 233076173 ps
CPU time 1.65 seconds
Started Jun 22 06:24:16 PM PDT 24
Finished Jun 22 06:24:18 PM PDT 24
Peak memory 218484 kb
Host smart-f95eef74-f5c3-4ec3-9261-8b00f548db65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755846406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1755846406
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.4125408903
Short name T328
Test name
Test status
Simulation time 90946359 ps
CPU time 1.18 seconds
Started Jun 22 06:24:21 PM PDT 24
Finished Jun 22 06:24:23 PM PDT 24
Peak memory 216680 kb
Host smart-ef872cc0-caea-433a-b0b2-3386b8710679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125408903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.4125408903
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2913402771
Short name T856
Test name
Test status
Simulation time 31380613 ps
CPU time 1.28 seconds
Started Jun 22 06:24:21 PM PDT 24
Finished Jun 22 06:24:24 PM PDT 24
Peak memory 216712 kb
Host smart-13759608-2359-4ff3-92ed-e7a51e2b5e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913402771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2913402771
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.3079603291
Short name T281
Test name
Test status
Simulation time 46424255 ps
CPU time 1.19 seconds
Started Jun 22 06:21:21 PM PDT 24
Finished Jun 22 06:21:22 PM PDT 24
Peak memory 218992 kb
Host smart-3733a5a6-4e97-4669-8f6b-e5a3c30af445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079603291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3079603291
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.195781363
Short name T627
Test name
Test status
Simulation time 18464569 ps
CPU time 1.03 seconds
Started Jun 22 06:21:12 PM PDT 24
Finished Jun 22 06:21:14 PM PDT 24
Peak memory 214600 kb
Host smart-a99fa1b3-de15-43d1-8677-f2a550505bc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195781363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.195781363
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2859167513
Short name T550
Test name
Test status
Simulation time 11994703 ps
CPU time 0.9 seconds
Started Jun 22 06:21:10 PM PDT 24
Finished Jun 22 06:21:11 PM PDT 24
Peak memory 215688 kb
Host smart-cb43a2cf-34a5-4cfa-95b4-980ee7d14ca2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859167513 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2859167513
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1190196188
Short name T12
Test name
Test status
Simulation time 59365766 ps
CPU time 1.24 seconds
Started Jun 22 06:21:11 PM PDT 24
Finished Jun 22 06:21:13 PM PDT 24
Peak memory 217644 kb
Host smart-6e87dabb-4916-48ad-9947-eb8f723ffaee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190196188 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1190196188
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_genbits.1926786346
Short name T701
Test name
Test status
Simulation time 169904360 ps
CPU time 1.15 seconds
Started Jun 22 06:21:13 PM PDT 24
Finished Jun 22 06:21:14 PM PDT 24
Peak memory 219144 kb
Host smart-292e02d9-801d-4444-9922-779e094348a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926786346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1926786346
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3397287821
Short name T773
Test name
Test status
Simulation time 23226983 ps
CPU time 1.24 seconds
Started Jun 22 06:21:12 PM PDT 24
Finished Jun 22 06:21:14 PM PDT 24
Peak memory 223396 kb
Host smart-e3a87d9f-7731-4784-81df-860e79f7499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397287821 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3397287821
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2053731428
Short name T863
Test name
Test status
Simulation time 17426917 ps
CPU time 1.02 seconds
Started Jun 22 06:21:12 PM PDT 24
Finished Jun 22 06:21:14 PM PDT 24
Peak memory 214632 kb
Host smart-b5b1a66a-0699-4422-808e-97c6aa66fd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053731428 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2053731428
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3362280458
Short name T354
Test name
Test status
Simulation time 2198734044 ps
CPU time 4.79 seconds
Started Jun 22 06:21:11 PM PDT 24
Finished Jun 22 06:21:17 PM PDT 24
Peak memory 214756 kb
Host smart-c08b8cb3-41f8-4b68-872a-2e4d4aaa7780
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362280458 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3362280458
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3865624437
Short name T614
Test name
Test status
Simulation time 90727479760 ps
CPU time 1137.38 seconds
Started Jun 22 06:21:12 PM PDT 24
Finished Jun 22 06:40:10 PM PDT 24
Peak memory 221460 kb
Host smart-9673ce88-e03e-45cf-812c-9df5b0cbdaeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865624437 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3865624437
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2911691744
Short name T682
Test name
Test status
Simulation time 42098674 ps
CPU time 1.33 seconds
Started Jun 22 06:24:22 PM PDT 24
Finished Jun 22 06:24:24 PM PDT 24
Peak memory 217820 kb
Host smart-c5545f21-1cf5-4dbf-ac62-b8d808b0dd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911691744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2911691744
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2803587314
Short name T363
Test name
Test status
Simulation time 44164105 ps
CPU time 1.3 seconds
Started Jun 22 06:24:20 PM PDT 24
Finished Jun 22 06:24:22 PM PDT 24
Peak memory 216548 kb
Host smart-9787b7dd-a893-451d-90a9-aca81de1a70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803587314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2803587314
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2934185823
Short name T688
Test name
Test status
Simulation time 27581270 ps
CPU time 1.3 seconds
Started Jun 22 06:24:21 PM PDT 24
Finished Jun 22 06:24:23 PM PDT 24
Peak memory 216772 kb
Host smart-e05e07f3-e922-406b-8ad0-56dfe34b7766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934185823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2934185823
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3377052438
Short name T457
Test name
Test status
Simulation time 44759531 ps
CPU time 1.19 seconds
Started Jun 22 06:24:19 PM PDT 24
Finished Jun 22 06:24:21 PM PDT 24
Peak memory 216704 kb
Host smart-e9bc85ad-20f2-4417-8d34-d29b67ac6056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377052438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3377052438
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.2063791485
Short name T427
Test name
Test status
Simulation time 30911347 ps
CPU time 1.32 seconds
Started Jun 22 06:24:20 PM PDT 24
Finished Jun 22 06:24:22 PM PDT 24
Peak memory 219292 kb
Host smart-5a796e9e-6d15-431b-97bb-5593c1f7636d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063791485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2063791485
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3620151526
Short name T445
Test name
Test status
Simulation time 2260969164 ps
CPU time 72.88 seconds
Started Jun 22 06:24:22 PM PDT 24
Finished Jun 22 06:25:36 PM PDT 24
Peak memory 219596 kb
Host smart-c373a230-7597-4b94-a714-2d050e1f9423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620151526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3620151526
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3839585281
Short name T664
Test name
Test status
Simulation time 49353892 ps
CPU time 1.28 seconds
Started Jun 22 06:24:21 PM PDT 24
Finished Jun 22 06:24:23 PM PDT 24
Peak memory 216820 kb
Host smart-a46c3573-5940-43df-88fe-cce5bfa4a3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839585281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3839585281
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2801820738
Short name T434
Test name
Test status
Simulation time 50139121 ps
CPU time 1.36 seconds
Started Jun 22 06:24:20 PM PDT 24
Finished Jun 22 06:24:22 PM PDT 24
Peak memory 217796 kb
Host smart-ecb8e229-376e-4cc7-81c5-5bd147868207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801820738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2801820738
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2437349118
Short name T308
Test name
Test status
Simulation time 45634555 ps
CPU time 1.24 seconds
Started Jun 22 06:24:19 PM PDT 24
Finished Jun 22 06:24:21 PM PDT 24
Peak memory 217876 kb
Host smart-40a6227e-c2d2-48da-a78c-572c3bd534ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437349118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2437349118
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3563924360
Short name T364
Test name
Test status
Simulation time 44849665 ps
CPU time 1.44 seconds
Started Jun 22 06:24:20 PM PDT 24
Finished Jun 22 06:24:22 PM PDT 24
Peak memory 219428 kb
Host smart-0f4505d3-45aa-45c7-b985-faf9dfaeb8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563924360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3563924360
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.111873433
Short name T829
Test name
Test status
Simulation time 47180289 ps
CPU time 1.18 seconds
Started Jun 22 06:19:23 PM PDT 24
Finished Jun 22 06:19:25 PM PDT 24
Peak memory 219160 kb
Host smart-3735d91b-b57d-4565-8003-f21623c6670b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111873433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.111873433
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2989680282
Short name T455
Test name
Test status
Simulation time 31242074 ps
CPU time 0.89 seconds
Started Jun 22 06:19:26 PM PDT 24
Finished Jun 22 06:19:28 PM PDT 24
Peak memory 214300 kb
Host smart-eaf32a06-ecb6-4cff-bb18-1ebe56b1349f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989680282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2989680282
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.4065930687
Short name T832
Test name
Test status
Simulation time 67545110 ps
CPU time 0.84 seconds
Started Jun 22 06:19:25 PM PDT 24
Finished Jun 22 06:19:27 PM PDT 24
Peak memory 215264 kb
Host smart-ab72cccc-0a6b-4fd9-8638-7b28dfee91f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065930687 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.4065930687
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3735760101
Short name T566
Test name
Test status
Simulation time 150466722 ps
CPU time 1.09 seconds
Started Jun 22 06:19:25 PM PDT 24
Finished Jun 22 06:19:27 PM PDT 24
Peak memory 217632 kb
Host smart-311a8135-8a95-4d4e-92cc-40bd1fe7dcda
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735760101 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3735760101
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1688705966
Short name T199
Test name
Test status
Simulation time 42645507 ps
CPU time 1.15 seconds
Started Jun 22 06:19:27 PM PDT 24
Finished Jun 22 06:19:28 PM PDT 24
Peak memory 218992 kb
Host smart-1f5bc860-024d-41d6-a2ac-7f6862112828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688705966 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1688705966
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.4039342529
Short name T723
Test name
Test status
Simulation time 46785406 ps
CPU time 1.44 seconds
Started Jun 22 06:19:25 PM PDT 24
Finished Jun 22 06:19:27 PM PDT 24
Peak memory 218312 kb
Host smart-3695892b-7e3d-431a-9f1e-46b890b1f9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039342529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.4039342529
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.303128496
Short name T564
Test name
Test status
Simulation time 48437797 ps
CPU time 0.88 seconds
Started Jun 22 06:19:26 PM PDT 24
Finished Jun 22 06:19:27 PM PDT 24
Peak memory 214924 kb
Host smart-c2f32905-48b1-4197-a579-c63b47e888be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303128496 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.303128496
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3437831726
Short name T63
Test name
Test status
Simulation time 569108519 ps
CPU time 8.49 seconds
Started Jun 22 06:19:25 PM PDT 24
Finished Jun 22 06:19:34 PM PDT 24
Peak memory 236668 kb
Host smart-3e482fdd-057c-492c-9009-0b0d855c14d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437831726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3437831726
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.372298293
Short name T662
Test name
Test status
Simulation time 16776326 ps
CPU time 1.07 seconds
Started Jun 22 06:19:27 PM PDT 24
Finished Jun 22 06:19:28 PM PDT 24
Peak memory 214844 kb
Host smart-2279babf-2c29-486d-9f72-3716f51bb56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372298293 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.372298293
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1335040755
Short name T736
Test name
Test status
Simulation time 165149298 ps
CPU time 2.11 seconds
Started Jun 22 06:19:27 PM PDT 24
Finished Jun 22 06:19:30 PM PDT 24
Peak memory 216536 kb
Host smart-678d86e6-65b5-42a1-afd0-bb14435c3575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335040755 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1335040755
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2031517506
Short name T979
Test name
Test status
Simulation time 160671023701 ps
CPU time 1597.35 seconds
Started Jun 22 06:19:25 PM PDT 24
Finished Jun 22 06:46:03 PM PDT 24
Peak memory 224924 kb
Host smart-de4f849f-3928-4b4c-873f-c3b4e81deb35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031517506 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2031517506
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2365365080
Short name T94
Test name
Test status
Simulation time 28577944 ps
CPU time 1.22 seconds
Started Jun 22 06:21:13 PM PDT 24
Finished Jun 22 06:21:15 PM PDT 24
Peak memory 219140 kb
Host smart-1130cec6-be76-4858-8bf9-a841b73cc0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365365080 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2365365080
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2046505224
Short name T412
Test name
Test status
Simulation time 27447120 ps
CPU time 0.86 seconds
Started Jun 22 06:21:26 PM PDT 24
Finished Jun 22 06:21:27 PM PDT 24
Peak memory 206036 kb
Host smart-ec15081b-7601-4c51-a3f7-f39b1753df12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046505224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2046505224
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.486578589
Short name T792
Test name
Test status
Simulation time 26513769 ps
CPU time 1.04 seconds
Started Jun 22 06:21:16 PM PDT 24
Finished Jun 22 06:21:17 PM PDT 24
Peak memory 219132 kb
Host smart-f2fc8ae4-cfab-4fdd-8736-8d2df0ad4dea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486578589 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.486578589
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3348750895
Short name T194
Test name
Test status
Simulation time 19070704 ps
CPU time 0.99 seconds
Started Jun 22 06:21:15 PM PDT 24
Finished Jun 22 06:21:17 PM PDT 24
Peak memory 217800 kb
Host smart-daea762b-e102-4a08-9d02-34702081420b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348750895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3348750895
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3100249430
Short name T685
Test name
Test status
Simulation time 42998780 ps
CPU time 1.58 seconds
Started Jun 22 06:21:12 PM PDT 24
Finished Jun 22 06:21:14 PM PDT 24
Peak memory 218384 kb
Host smart-e12bdd25-6a03-4847-88e4-2c49548d2284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100249430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3100249430
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.998700654
Short name T451
Test name
Test status
Simulation time 23605478 ps
CPU time 0.99 seconds
Started Jun 22 06:21:10 PM PDT 24
Finished Jun 22 06:21:12 PM PDT 24
Peak memory 215032 kb
Host smart-1641d2a6-87cd-4151-90fe-b3d5afd0ed3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998700654 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.998700654
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1148142706
Short name T605
Test name
Test status
Simulation time 47617715 ps
CPU time 0.87 seconds
Started Jun 22 06:21:09 PM PDT 24
Finished Jun 22 06:21:11 PM PDT 24
Peak memory 214640 kb
Host smart-670cea6d-e770-4f60-88d8-0d99a4330c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148142706 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1148142706
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2772613203
Short name T236
Test name
Test status
Simulation time 1675275353 ps
CPU time 5.07 seconds
Started Jun 22 06:21:11 PM PDT 24
Finished Jun 22 06:21:17 PM PDT 24
Peak memory 214640 kb
Host smart-9facc8df-4e5c-4aee-a19d-0d53d87e16a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772613203 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2772613203
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_alert.3793243780
Short name T214
Test name
Test status
Simulation time 24966928 ps
CPU time 1.25 seconds
Started Jun 22 06:21:16 PM PDT 24
Finished Jun 22 06:21:18 PM PDT 24
Peak memory 218072 kb
Host smart-6d487b3d-9069-42f4-b310-b22ab5593f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793243780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3793243780
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1708633505
Short name T384
Test name
Test status
Simulation time 104975747 ps
CPU time 0.85 seconds
Started Jun 22 06:21:15 PM PDT 24
Finished Jun 22 06:21:16 PM PDT 24
Peak memory 206256 kb
Host smart-0c983488-8f62-436a-abe7-bd14c2b63cd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708633505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1708633505
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1854265842
Short name T143
Test name
Test status
Simulation time 122364746 ps
CPU time 1.2 seconds
Started Jun 22 06:21:26 PM PDT 24
Finished Jun 22 06:21:27 PM PDT 24
Peak memory 216172 kb
Host smart-47749082-e885-4cb8-bf15-0e8a2430d882
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854265842 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1854265842
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.558822606
Short name T355
Test name
Test status
Simulation time 25660130 ps
CPU time 1.18 seconds
Started Jun 22 06:21:15 PM PDT 24
Finished Jun 22 06:21:17 PM PDT 24
Peak memory 217976 kb
Host smart-1d5c5927-72e6-4641-b742-e13559a95bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558822606 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.558822606
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3288386950
Short name T505
Test name
Test status
Simulation time 46925827 ps
CPU time 1.64 seconds
Started Jun 22 06:21:19 PM PDT 24
Finished Jun 22 06:21:21 PM PDT 24
Peak memory 217772 kb
Host smart-89f0ed8e-dfe6-44e2-b8a0-d1d4b10a0614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288386950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3288386950
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2935740681
Short name T610
Test name
Test status
Simulation time 29197332 ps
CPU time 0.97 seconds
Started Jun 22 06:21:18 PM PDT 24
Finished Jun 22 06:21:19 PM PDT 24
Peak memory 215008 kb
Host smart-65356368-f0ad-4912-897c-f6e64a3e65bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935740681 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2935740681
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.677099413
Short name T225
Test name
Test status
Simulation time 21602140 ps
CPU time 0.99 seconds
Started Jun 22 06:21:15 PM PDT 24
Finished Jun 22 06:21:17 PM PDT 24
Peak memory 214616 kb
Host smart-dcf341e1-bb8b-422f-a6cf-88855f46481c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677099413 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.677099413
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1616479892
Short name T735
Test name
Test status
Simulation time 266697588 ps
CPU time 5.14 seconds
Started Jun 22 06:21:16 PM PDT 24
Finished Jun 22 06:21:21 PM PDT 24
Peak memory 214632 kb
Host smart-e4d20fcd-6da4-4e4c-a0df-7231b6005606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616479892 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1616479892
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.4041304476
Short name T410
Test name
Test status
Simulation time 182664893265 ps
CPU time 2144.59 seconds
Started Jun 22 06:21:26 PM PDT 24
Finished Jun 22 06:57:11 PM PDT 24
Peak memory 226120 kb
Host smart-0e2be5e7-30c1-44d9-a23b-0f41f7264e40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041304476 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.4041304476
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.4289175426
Short name T819
Test name
Test status
Simulation time 71675557 ps
CPU time 1.13 seconds
Started Jun 22 06:21:23 PM PDT 24
Finished Jun 22 06:21:25 PM PDT 24
Peak memory 219888 kb
Host smart-94b90ceb-8077-4b55-9d59-8e885d1bc6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289175426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.4289175426
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3068635621
Short name T854
Test name
Test status
Simulation time 24528088 ps
CPU time 0.87 seconds
Started Jun 22 06:21:24 PM PDT 24
Finished Jun 22 06:21:25 PM PDT 24
Peak memory 206276 kb
Host smart-795074f0-1495-469b-bd47-e60f6bea7a31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068635621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3068635621
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2894887426
Short name T461
Test name
Test status
Simulation time 20965055 ps
CPU time 0.85 seconds
Started Jun 22 06:21:24 PM PDT 24
Finished Jun 22 06:21:25 PM PDT 24
Peak memory 215452 kb
Host smart-12980c59-4696-4d4b-b6af-00e93e9bf2e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894887426 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2894887426
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.741801882
Short name T595
Test name
Test status
Simulation time 36920320 ps
CPU time 1.15 seconds
Started Jun 22 06:21:22 PM PDT 24
Finished Jun 22 06:21:24 PM PDT 24
Peak memory 217732 kb
Host smart-a6bfbb6d-6c86-4a04-a735-5d7a46f37814
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741801882 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.741801882
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.4034133157
Short name T78
Test name
Test status
Simulation time 28105862 ps
CPU time 0.85 seconds
Started Jun 22 06:21:22 PM PDT 24
Finished Jun 22 06:21:23 PM PDT 24
Peak memory 217832 kb
Host smart-92f4e212-6495-4f34-9665-18747d7f63ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034133157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.4034133157
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2659484241
Short name T2
Test name
Test status
Simulation time 42396630 ps
CPU time 1.64 seconds
Started Jun 22 06:21:17 PM PDT 24
Finished Jun 22 06:21:19 PM PDT 24
Peak memory 218084 kb
Host smart-0a8b4cab-7c7a-428f-aabb-1c34cc0fdaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659484241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2659484241
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.214370550
Short name T924
Test name
Test status
Simulation time 22078447 ps
CPU time 1.26 seconds
Started Jun 22 06:21:23 PM PDT 24
Finished Jun 22 06:21:25 PM PDT 24
Peak memory 223392 kb
Host smart-6fb45fba-7972-4edc-85ed-79cb0c24fa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214370550 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.214370550
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3262931383
Short name T341
Test name
Test status
Simulation time 29243069 ps
CPU time 0.95 seconds
Started Jun 22 06:21:26 PM PDT 24
Finished Jun 22 06:21:27 PM PDT 24
Peak memory 214488 kb
Host smart-6ad82ba8-0ce7-4d59-9dc0-225ca5b448a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262931383 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3262931383
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.294448411
Short name T599
Test name
Test status
Simulation time 128415581 ps
CPU time 2.91 seconds
Started Jun 22 06:21:26 PM PDT 24
Finished Jun 22 06:21:29 PM PDT 24
Peak memory 216572 kb
Host smart-ddafa86d-80df-4988-872c-3b2a66d841ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294448411 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.294448411
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1582164816
Short name T904
Test name
Test status
Simulation time 26177897235 ps
CPU time 704 seconds
Started Jun 22 06:21:21 PM PDT 24
Finished Jun 22 06:33:06 PM PDT 24
Peak memory 222916 kb
Host smart-3ba9c47c-26c9-468a-87eb-bd2881185d88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582164816 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1582164816
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2804692492
Short name T671
Test name
Test status
Simulation time 43285408 ps
CPU time 1.24 seconds
Started Jun 22 06:21:24 PM PDT 24
Finished Jun 22 06:21:26 PM PDT 24
Peak memory 218148 kb
Host smart-b52f66f1-2e5e-40bb-a349-1f6129981882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804692492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2804692492
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2643053187
Short name T435
Test name
Test status
Simulation time 13139969 ps
CPU time 0.92 seconds
Started Jun 22 06:21:25 PM PDT 24
Finished Jun 22 06:21:26 PM PDT 24
Peak memory 206360 kb
Host smart-3f4c0818-b848-43f3-a0cb-54fc30d1d1cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643053187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2643053187
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.909752166
Short name T921
Test name
Test status
Simulation time 11102767 ps
CPU time 0.87 seconds
Started Jun 22 06:21:23 PM PDT 24
Finished Jun 22 06:21:24 PM PDT 24
Peak memory 215672 kb
Host smart-0718e4e1-1d37-45e7-a999-faa50f38f8dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909752166 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.909752166
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2568617063
Short name T419
Test name
Test status
Simulation time 43044107 ps
CPU time 1.35 seconds
Started Jun 22 06:21:24 PM PDT 24
Finished Jun 22 06:21:26 PM PDT 24
Peak memory 216292 kb
Host smart-966c1dec-0247-4a49-8156-61ee62ba78bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568617063 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2568617063
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2464735294
Short name T17
Test name
Test status
Simulation time 28763432 ps
CPU time 1.39 seconds
Started Jun 22 06:21:24 PM PDT 24
Finished Jun 22 06:21:26 PM PDT 24
Peak memory 224976 kb
Host smart-48761702-ccaa-4a1e-ab28-a667e388a04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464735294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2464735294
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1068367623
Short name T661
Test name
Test status
Simulation time 82172353 ps
CPU time 1.4 seconds
Started Jun 22 06:21:22 PM PDT 24
Finished Jun 22 06:21:24 PM PDT 24
Peak memory 218592 kb
Host smart-02a0fbca-baf2-4c7b-b78e-0a007b1bcd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068367623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1068367623
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3011913238
Short name T845
Test name
Test status
Simulation time 37321654 ps
CPU time 0.82 seconds
Started Jun 22 06:21:22 PM PDT 24
Finished Jun 22 06:21:23 PM PDT 24
Peak memory 214896 kb
Host smart-6a7f8fd2-48e3-49b0-99e0-29d47a056b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011913238 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3011913238
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.4190904123
Short name T747
Test name
Test status
Simulation time 37724140 ps
CPU time 0.86 seconds
Started Jun 22 06:21:24 PM PDT 24
Finished Jun 22 06:21:25 PM PDT 24
Peak memory 214472 kb
Host smart-d1786250-d703-483c-8d80-d97f3943bafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190904123 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.4190904123
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1879965667
Short name T327
Test name
Test status
Simulation time 173045976 ps
CPU time 0.98 seconds
Started Jun 22 06:21:22 PM PDT 24
Finished Jun 22 06:21:24 PM PDT 24
Peak memory 205832 kb
Host smart-e3262d14-aaa2-41a6-a3f2-d0c7e5586e72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879965667 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1879965667
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1000573285
Short name T221
Test name
Test status
Simulation time 61673186469 ps
CPU time 157.67 seconds
Started Jun 22 06:21:27 PM PDT 24
Finished Jun 22 06:24:05 PM PDT 24
Peak memory 222856 kb
Host smart-5ef2434f-82e8-4840-a7ae-f58368f974c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000573285 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1000573285
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert_test.1456768727
Short name T932
Test name
Test status
Simulation time 59903731 ps
CPU time 1.61 seconds
Started Jun 22 06:21:29 PM PDT 24
Finished Jun 22 06:21:31 PM PDT 24
Peak memory 214416 kb
Host smart-5c9a67f0-c084-4f73-a1bf-b6ce8e9d79b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456768727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1456768727
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1960652549
Short name T518
Test name
Test status
Simulation time 25554717 ps
CPU time 1.06 seconds
Started Jun 22 06:21:33 PM PDT 24
Finished Jun 22 06:21:35 PM PDT 24
Peak memory 216736 kb
Host smart-ec029e97-973f-46b2-afda-adae392df08b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960652549 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1960652549
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.721982772
Short name T208
Test name
Test status
Simulation time 20755061 ps
CPU time 0.92 seconds
Started Jun 22 06:21:31 PM PDT 24
Finished Jun 22 06:21:33 PM PDT 24
Peak memory 217752 kb
Host smart-a3c3972b-2fa5-4bf0-b175-2700cfe05799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721982772 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.721982772
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.420964481
Short name T456
Test name
Test status
Simulation time 68338452 ps
CPU time 2.57 seconds
Started Jun 22 06:21:24 PM PDT 24
Finished Jun 22 06:21:27 PM PDT 24
Peak memory 219416 kb
Host smart-362a0c2c-3d58-4403-ae53-7f081ae08c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420964481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.420964481
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.951492132
Short name T105
Test name
Test status
Simulation time 20377947 ps
CPU time 1.07 seconds
Started Jun 22 06:21:24 PM PDT 24
Finished Jun 22 06:21:26 PM PDT 24
Peak memory 215156 kb
Host smart-6fb24f9f-cb00-46da-ba9e-5e700d340e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951492132 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.951492132
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2407334151
Short name T323
Test name
Test status
Simulation time 74521822 ps
CPU time 0.9 seconds
Started Jun 22 06:21:23 PM PDT 24
Finished Jun 22 06:21:25 PM PDT 24
Peak memory 214620 kb
Host smart-fe0e4dd1-4ca6-4b58-ae76-5002e5e91f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407334151 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2407334151
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3414179664
Short name T811
Test name
Test status
Simulation time 258759617 ps
CPU time 2.95 seconds
Started Jun 22 06:21:26 PM PDT 24
Finished Jun 22 06:21:30 PM PDT 24
Peak memory 214576 kb
Host smart-fe15df6f-2c0f-430b-b621-1ad1dd9e74e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414179664 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3414179664
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1911421737
Short name T835
Test name
Test status
Simulation time 1058450665951 ps
CPU time 1767.6 seconds
Started Jun 22 06:21:23 PM PDT 24
Finished Jun 22 06:50:52 PM PDT 24
Peak memory 224064 kb
Host smart-e1fc1929-374e-4f45-a79f-386ad8b98726
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911421737 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1911421737
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1121265866
Short name T542
Test name
Test status
Simulation time 96824843 ps
CPU time 1.18 seconds
Started Jun 22 06:21:32 PM PDT 24
Finished Jun 22 06:21:34 PM PDT 24
Peak memory 218120 kb
Host smart-6842b82f-d3d1-4e82-bc11-c5c946bf4120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121265866 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1121265866
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3487956836
Short name T644
Test name
Test status
Simulation time 16430356 ps
CPU time 0.94 seconds
Started Jun 22 06:21:33 PM PDT 24
Finished Jun 22 06:21:35 PM PDT 24
Peak memory 206036 kb
Host smart-b1bf14e0-5017-41c2-9200-0492d79878e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487956836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3487956836
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1427246937
Short name T205
Test name
Test status
Simulation time 18350768 ps
CPU time 0.89 seconds
Started Jun 22 06:21:32 PM PDT 24
Finished Jun 22 06:21:33 PM PDT 24
Peak memory 216012 kb
Host smart-c0151915-9956-4592-b47d-2b88937db9a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427246937 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1427246937
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.774735553
Short name T515
Test name
Test status
Simulation time 29023477 ps
CPU time 1.02 seconds
Started Jun 22 06:21:32 PM PDT 24
Finished Jun 22 06:21:33 PM PDT 24
Peak memory 216256 kb
Host smart-a7bb4b84-890e-489b-ba2d-b1b0875b0ba9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774735553 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.774735553
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.4152071183
Short name T168
Test name
Test status
Simulation time 24878320 ps
CPU time 1.14 seconds
Started Jun 22 06:21:32 PM PDT 24
Finished Jun 22 06:21:34 PM PDT 24
Peak memory 217760 kb
Host smart-a960136d-6428-4b09-add1-c5be65e80c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152071183 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.4152071183
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_intr.3650864000
Short name T329
Test name
Test status
Simulation time 21825757 ps
CPU time 1.02 seconds
Started Jun 22 06:21:32 PM PDT 24
Finished Jun 22 06:21:34 PM PDT 24
Peak memory 214976 kb
Host smart-7167c2fd-2708-4814-836a-ec5b4fedd9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650864000 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3650864000
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3596086692
Short name T366
Test name
Test status
Simulation time 17042484 ps
CPU time 1.02 seconds
Started Jun 22 06:21:34 PM PDT 24
Finished Jun 22 06:21:35 PM PDT 24
Peak memory 214648 kb
Host smart-0f3f6770-86b3-4559-b129-1a3b1577f761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596086692 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3596086692
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.388769132
Short name T535
Test name
Test status
Simulation time 431209829 ps
CPU time 7.89 seconds
Started Jun 22 06:21:32 PM PDT 24
Finished Jun 22 06:21:41 PM PDT 24
Peak memory 216560 kb
Host smart-c47180fb-81f4-4c3d-b1bf-724e6b01a6c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388769132 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.388769132
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.320352176
Short name T592
Test name
Test status
Simulation time 34309336092 ps
CPU time 443.94 seconds
Started Jun 22 06:21:34 PM PDT 24
Finished Jun 22 06:28:59 PM PDT 24
Peak memory 216336 kb
Host smart-9b8401e6-c851-4993-87c9-d186efd613b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320352176 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.320352176
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.977028458
Short name T175
Test name
Test status
Simulation time 69608042 ps
CPU time 1.09 seconds
Started Jun 22 06:21:29 PM PDT 24
Finished Jun 22 06:21:31 PM PDT 24
Peak memory 218200 kb
Host smart-fb6c333d-824e-4bb0-bfb4-138d159e29ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977028458 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.977028458
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.304180081
Short name T844
Test name
Test status
Simulation time 24448830 ps
CPU time 0.89 seconds
Started Jun 22 06:21:30 PM PDT 24
Finished Jun 22 06:21:31 PM PDT 24
Peak memory 206136 kb
Host smart-5c642ad3-47a6-402f-b697-6e98d9065f79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304180081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.304180081
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1762965945
Short name T196
Test name
Test status
Simulation time 123104174 ps
CPU time 1.35 seconds
Started Jun 22 06:21:33 PM PDT 24
Finished Jun 22 06:21:35 PM PDT 24
Peak memory 216204 kb
Host smart-af1b5cbd-c02c-49ed-b3d9-0cedaac9a2c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762965945 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1762965945
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1143894382
Short name T553
Test name
Test status
Simulation time 33727086 ps
CPU time 1.13 seconds
Started Jun 22 06:21:32 PM PDT 24
Finished Jun 22 06:21:33 PM PDT 24
Peak memory 223448 kb
Host smart-c835e585-cf7b-45ad-ac9b-86daa9061acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143894382 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1143894382
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.4281369164
Short name T304
Test name
Test status
Simulation time 38027564 ps
CPU time 1.47 seconds
Started Jun 22 06:21:31 PM PDT 24
Finished Jun 22 06:21:33 PM PDT 24
Peak memory 219280 kb
Host smart-7a08bf57-b783-42e1-814b-8eeec8d268cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281369164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.4281369164
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2676257731
Short name T590
Test name
Test status
Simulation time 22045813 ps
CPU time 0.92 seconds
Started Jun 22 06:21:30 PM PDT 24
Finished Jun 22 06:21:32 PM PDT 24
Peak memory 215136 kb
Host smart-bd34d361-4d03-432d-8c76-6df2ca80ccb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676257731 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2676257731
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2182424061
Short name T397
Test name
Test status
Simulation time 52991057 ps
CPU time 0.95 seconds
Started Jun 22 06:21:31 PM PDT 24
Finished Jun 22 06:21:33 PM PDT 24
Peak memory 214636 kb
Host smart-46979a63-c36c-4e77-8025-32b24a73d662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182424061 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2182424061
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1466273704
Short name T865
Test name
Test status
Simulation time 273009341 ps
CPU time 3.2 seconds
Started Jun 22 06:21:30 PM PDT 24
Finished Jun 22 06:21:34 PM PDT 24
Peak memory 216696 kb
Host smart-633c3ff4-a584-41c8-8dd0-4e93d2909a99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466273704 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1466273704
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1861102310
Short name T556
Test name
Test status
Simulation time 407195025879 ps
CPU time 1286.18 seconds
Started Jun 22 06:21:38 PM PDT 24
Finished Jun 22 06:43:05 PM PDT 24
Peak memory 223028 kb
Host smart-64616ba8-e5bc-4965-9e54-f03044ecc08f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861102310 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1861102310
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3624679241
Short name T280
Test name
Test status
Simulation time 22842962 ps
CPU time 1.18 seconds
Started Jun 22 06:21:38 PM PDT 24
Finished Jun 22 06:21:40 PM PDT 24
Peak memory 218068 kb
Host smart-c16d050b-4d3e-400a-8a4d-69a6ff3b6b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624679241 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3624679241
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2923812650
Short name T936
Test name
Test status
Simulation time 44201335 ps
CPU time 0.89 seconds
Started Jun 22 06:21:38 PM PDT 24
Finished Jun 22 06:21:39 PM PDT 24
Peak memory 206132 kb
Host smart-bd173217-b23f-44c8-946e-198f782ae653
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923812650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2923812650
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2462455939
Short name T454
Test name
Test status
Simulation time 70923826 ps
CPU time 1.11 seconds
Started Jun 22 06:21:38 PM PDT 24
Finished Jun 22 06:21:40 PM PDT 24
Peak memory 216456 kb
Host smart-825e7c00-d376-447f-8c5a-c44ee0e9baae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462455939 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2462455939
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2774227203
Short name T202
Test name
Test status
Simulation time 47603543 ps
CPU time 0.87 seconds
Started Jun 22 06:21:42 PM PDT 24
Finished Jun 22 06:21:43 PM PDT 24
Peak memory 217812 kb
Host smart-762fd104-6882-49e9-beb4-379f2d6e6005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774227203 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2774227203
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3278822998
Short name T393
Test name
Test status
Simulation time 39614228 ps
CPU time 1.56 seconds
Started Jun 22 06:21:30 PM PDT 24
Finished Jun 22 06:21:32 PM PDT 24
Peak memory 217932 kb
Host smart-4c6305ab-85f0-4d91-b789-eec1aec857e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278822998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3278822998
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1435800323
Short name T778
Test name
Test status
Simulation time 28698442 ps
CPU time 1.13 seconds
Started Jun 22 06:21:33 PM PDT 24
Finished Jun 22 06:21:35 PM PDT 24
Peak memory 223360 kb
Host smart-96c15cd1-b42f-4fa4-aaeb-eba234302d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435800323 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1435800323
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.4001481307
Short name T334
Test name
Test status
Simulation time 18414517 ps
CPU time 1.04 seconds
Started Jun 22 06:21:32 PM PDT 24
Finished Jun 22 06:21:33 PM PDT 24
Peak memory 214640 kb
Host smart-9388d7bd-cec4-42a8-a757-4e05c746146d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001481307 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.4001481307
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.895210374
Short name T559
Test name
Test status
Simulation time 409256508 ps
CPU time 2.6 seconds
Started Jun 22 06:21:30 PM PDT 24
Finished Jun 22 06:21:32 PM PDT 24
Peak memory 216592 kb
Host smart-b1ec4ec2-9ea4-40d6-85ae-1989c2c6bf75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895210374 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.895210374
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.237629234
Short name T968
Test name
Test status
Simulation time 22527014183 ps
CPU time 303.15 seconds
Started Jun 22 06:21:31 PM PDT 24
Finished Jun 22 06:26:34 PM PDT 24
Peak memory 222876 kb
Host smart-a9ba2de7-0d34-4c93-94eb-73736499a33d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237629234 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.237629234
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.2255631678
Short name T624
Test name
Test status
Simulation time 88967228 ps
CPU time 1.26 seconds
Started Jun 22 06:21:39 PM PDT 24
Finished Jun 22 06:21:41 PM PDT 24
Peak memory 215084 kb
Host smart-320c42b4-240c-452e-9ab6-8ba7674aa7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255631678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2255631678
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.679494355
Short name T699
Test name
Test status
Simulation time 34703060 ps
CPU time 0.98 seconds
Started Jun 22 06:21:38 PM PDT 24
Finished Jun 22 06:21:39 PM PDT 24
Peak memory 206144 kb
Host smart-f4569c00-b868-4679-aef7-76d43ee83791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679494355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.679494355
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3844726750
Short name T508
Test name
Test status
Simulation time 31755908 ps
CPU time 0.83 seconds
Started Jun 22 06:21:40 PM PDT 24
Finished Jun 22 06:21:41 PM PDT 24
Peak memory 215308 kb
Host smart-b2318c20-2f12-46e8-b4d1-af723baa1273
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844726750 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3844726750
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.586927642
Short name T907
Test name
Test status
Simulation time 34016845 ps
CPU time 1.29 seconds
Started Jun 22 06:21:40 PM PDT 24
Finished Jun 22 06:21:42 PM PDT 24
Peak memory 216268 kb
Host smart-606679d6-6e50-4768-9d7d-cc74ff150bf2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586927642 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.586927642
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.327443778
Short name T54
Test name
Test status
Simulation time 40748319 ps
CPU time 1.14 seconds
Started Jun 22 06:21:42 PM PDT 24
Finished Jun 22 06:21:43 PM PDT 24
Peak memory 223356 kb
Host smart-bf72f16c-1df6-4bfb-842f-d46f76492a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327443778 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.327443778
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2666054722
Short name T353
Test name
Test status
Simulation time 46199036 ps
CPU time 1.74 seconds
Started Jun 22 06:21:41 PM PDT 24
Finished Jun 22 06:21:44 PM PDT 24
Peak memory 216968 kb
Host smart-1ce70046-f797-4279-aafd-db2e91f1cf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666054722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2666054722
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1193800542
Short name T98
Test name
Test status
Simulation time 37026259 ps
CPU time 0.89 seconds
Started Jun 22 06:21:41 PM PDT 24
Finished Jun 22 06:21:42 PM PDT 24
Peak memory 214892 kb
Host smart-8dc33d42-85c5-419d-985b-170c95751526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193800542 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1193800542
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3215323467
Short name T643
Test name
Test status
Simulation time 25422947 ps
CPU time 1 seconds
Started Jun 22 06:21:38 PM PDT 24
Finished Jun 22 06:21:40 PM PDT 24
Peak memory 214600 kb
Host smart-217c42d1-87c9-459d-9418-178eca9f82d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215323467 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3215323467
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3512528531
Short name T521
Test name
Test status
Simulation time 59235184 ps
CPU time 1.71 seconds
Started Jun 22 06:21:42 PM PDT 24
Finished Jun 22 06:21:44 PM PDT 24
Peak memory 217796 kb
Host smart-b1f251a3-64a6-4ab5-aca5-72dc6cf6755d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512528531 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3512528531
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.689993974
Short name T41
Test name
Test status
Simulation time 359245151216 ps
CPU time 785.01 seconds
Started Jun 22 06:21:39 PM PDT 24
Finished Jun 22 06:34:45 PM PDT 24
Peak memory 231212 kb
Host smart-2609da68-ac24-4a48-a517-e54c5b5d7a3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689993974 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.689993974
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3280741859
Short name T613
Test name
Test status
Simulation time 27506045 ps
CPU time 1.14 seconds
Started Jun 22 06:21:40 PM PDT 24
Finished Jun 22 06:21:41 PM PDT 24
Peak memory 218196 kb
Host smart-f3434d1f-38c1-4f5a-9d46-5d0b53d56b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280741859 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3280741859
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3604017061
Short name T790
Test name
Test status
Simulation time 45138298 ps
CPU time 0.85 seconds
Started Jun 22 06:21:41 PM PDT 24
Finished Jun 22 06:21:43 PM PDT 24
Peak memory 205916 kb
Host smart-2bc91184-be30-4707-b438-5e48b19491dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604017061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3604017061
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.605257491
Short name T157
Test name
Test status
Simulation time 35324717 ps
CPU time 0.9 seconds
Started Jun 22 06:21:38 PM PDT 24
Finished Jun 22 06:21:40 PM PDT 24
Peak memory 214852 kb
Host smart-094e1424-d949-47e3-a11c-e954f2b15afd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605257491 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.605257491
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3819792162
Short name T400
Test name
Test status
Simulation time 72949815 ps
CPU time 1.07 seconds
Started Jun 22 06:21:40 PM PDT 24
Finished Jun 22 06:21:42 PM PDT 24
Peak memory 217432 kb
Host smart-a77e221a-61f5-4fec-913b-3410b3235ce2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819792162 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3819792162
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1375349762
Short name T165
Test name
Test status
Simulation time 18708253 ps
CPU time 1.04 seconds
Started Jun 22 06:21:37 PM PDT 24
Finished Jun 22 06:21:39 PM PDT 24
Peak memory 217892 kb
Host smart-dbb8c3c5-e632-45d5-a3a6-c11c978a1d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375349762 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1375349762
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2749044157
Short name T750
Test name
Test status
Simulation time 127692328 ps
CPU time 1.11 seconds
Started Jun 22 06:21:38 PM PDT 24
Finished Jun 22 06:21:40 PM PDT 24
Peak memory 216756 kb
Host smart-b66a7089-9442-44c7-917e-abfc0802aafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749044157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2749044157
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_smoke.568146730
Short name T808
Test name
Test status
Simulation time 16825746 ps
CPU time 1 seconds
Started Jun 22 06:21:39 PM PDT 24
Finished Jun 22 06:21:41 PM PDT 24
Peak memory 214644 kb
Host smart-80719002-70fe-440d-8be3-b0e841389c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568146730 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.568146730
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1856967055
Short name T961
Test name
Test status
Simulation time 359420993 ps
CPU time 6.68 seconds
Started Jun 22 06:21:39 PM PDT 24
Finished Jun 22 06:21:47 PM PDT 24
Peak memory 216480 kb
Host smart-be5aa3f1-477c-40e2-b967-33bd49a3d7b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856967055 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1856967055
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2004086128
Short name T224
Test name
Test status
Simulation time 235956596879 ps
CPU time 1641.63 seconds
Started Jun 22 06:21:40 PM PDT 24
Finished Jun 22 06:49:02 PM PDT 24
Peak memory 226356 kb
Host smart-eb07507e-8216-439d-8103-1409bf8dd6ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004086128 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2004086128
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2507021830
Short name T406
Test name
Test status
Simulation time 92908310 ps
CPU time 1.22 seconds
Started Jun 22 06:19:29 PM PDT 24
Finished Jun 22 06:19:31 PM PDT 24
Peak memory 219612 kb
Host smart-00c8f232-89a7-4598-a5a0-9948962754ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507021830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2507021830
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1137658323
Short name T469
Test name
Test status
Simulation time 19135291 ps
CPU time 1.02 seconds
Started Jun 22 06:19:28 PM PDT 24
Finished Jun 22 06:19:30 PM PDT 24
Peak memory 206124 kb
Host smart-9d4b0b10-d899-4767-86d2-79bcea3ddd94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137658323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1137658323
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3067570128
Short name T398
Test name
Test status
Simulation time 36178087 ps
CPU time 0.88 seconds
Started Jun 22 06:19:28 PM PDT 24
Finished Jun 22 06:19:29 PM PDT 24
Peak memory 215816 kb
Host smart-f23edc24-403c-4912-86e0-d27c8158246b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067570128 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3067570128
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1408969282
Short name T140
Test name
Test status
Simulation time 17602250 ps
CPU time 1 seconds
Started Jun 22 06:19:31 PM PDT 24
Finished Jun 22 06:19:33 PM PDT 24
Peak memory 217668 kb
Host smart-0c50dbc7-42db-4aae-bf4b-ba4d2ddf10e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408969282 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1408969282
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.4115400520
Short name T463
Test name
Test status
Simulation time 43756605 ps
CPU time 0.85 seconds
Started Jun 22 06:19:28 PM PDT 24
Finished Jun 22 06:19:29 PM PDT 24
Peak memory 217792 kb
Host smart-d0505f20-c7ee-47c1-821a-6c1c136014e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115400520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.4115400520
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.4005036445
Short name T658
Test name
Test status
Simulation time 128138755 ps
CPU time 3.35 seconds
Started Jun 22 06:19:27 PM PDT 24
Finished Jun 22 06:19:31 PM PDT 24
Peak memory 219548 kb
Host smart-4ca83b34-b45c-4f6d-8bbd-524fac70d4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005036445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.4005036445
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1682358982
Short name T36
Test name
Test status
Simulation time 21973924 ps
CPU time 1.16 seconds
Started Jun 22 06:19:29 PM PDT 24
Finished Jun 22 06:19:31 PM PDT 24
Peak memory 215132 kb
Host smart-a51beab3-1529-451d-85a5-15cdbcb95eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682358982 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1682358982
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.576699284
Short name T906
Test name
Test status
Simulation time 31284779 ps
CPU time 0.9 seconds
Started Jun 22 06:19:28 PM PDT 24
Finished Jun 22 06:19:30 PM PDT 24
Peak memory 206528 kb
Host smart-1cd6ecb7-004e-412e-a54b-bbf400a381cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576699284 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.576699284
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.4252659657
Short name T64
Test name
Test status
Simulation time 405416891 ps
CPU time 6.49 seconds
Started Jun 22 06:19:30 PM PDT 24
Finished Jun 22 06:19:36 PM PDT 24
Peak memory 234732 kb
Host smart-ea48313d-f38a-4e57-aa12-be89e71a4bef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252659657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.4252659657
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.947272462
Short name T860
Test name
Test status
Simulation time 26626111 ps
CPU time 0.92 seconds
Started Jun 22 06:19:28 PM PDT 24
Finished Jun 22 06:19:30 PM PDT 24
Peak memory 214620 kb
Host smart-d24b116e-3d38-4e33-9097-6ed1f5e241a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947272462 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.947272462
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3174101306
Short name T49
Test name
Test status
Simulation time 807800417 ps
CPU time 5.24 seconds
Started Jun 22 06:19:27 PM PDT 24
Finished Jun 22 06:19:33 PM PDT 24
Peak memory 216628 kb
Host smart-2fb37f4f-8706-4a2e-885e-9cdad5ebae0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174101306 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3174101306
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2588058878
Short name T573
Test name
Test status
Simulation time 88932235214 ps
CPU time 1078.96 seconds
Started Jun 22 06:19:31 PM PDT 24
Finished Jun 22 06:37:31 PM PDT 24
Peak memory 222960 kb
Host smart-47823c62-63e2-4ea6-b75e-016d022ae3b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588058878 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2588058878
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.135800466
Short name T710
Test name
Test status
Simulation time 228052303 ps
CPU time 1.59 seconds
Started Jun 22 06:21:39 PM PDT 24
Finished Jun 22 06:21:41 PM PDT 24
Peak memory 220056 kb
Host smart-a257a0cb-513b-4988-b296-4566ef7423f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135800466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.135800466
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3842789495
Short name T623
Test name
Test status
Simulation time 240474588 ps
CPU time 0.9 seconds
Started Jun 22 06:21:47 PM PDT 24
Finished Jun 22 06:21:49 PM PDT 24
Peak memory 206100 kb
Host smart-f8e17a05-085b-42d6-a272-a820470abfd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842789495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3842789495
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3362297149
Short name T200
Test name
Test status
Simulation time 32554268 ps
CPU time 0.84 seconds
Started Jun 22 06:21:42 PM PDT 24
Finished Jun 22 06:21:43 PM PDT 24
Peak memory 215820 kb
Host smart-cc085122-67d7-4ec8-a626-4d25a4b5c020
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362297149 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3362297149
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2317598250
Short name T10
Test name
Test status
Simulation time 48495071 ps
CPU time 1.36 seconds
Started Jun 22 06:21:37 PM PDT 24
Finished Jun 22 06:21:39 PM PDT 24
Peak memory 216296 kb
Host smart-58639326-3faa-455f-8079-36850917c515
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317598250 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2317598250
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.988443094
Short name T102
Test name
Test status
Simulation time 26038776 ps
CPU time 1.21 seconds
Started Jun 22 06:21:39 PM PDT 24
Finished Jun 22 06:21:41 PM PDT 24
Peak memory 219164 kb
Host smart-dd247ce1-ddb9-4b6f-983e-13560dbb08f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988443094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.988443094
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.938958418
Short name T299
Test name
Test status
Simulation time 126970646 ps
CPU time 1.49 seconds
Started Jun 22 06:21:40 PM PDT 24
Finished Jun 22 06:21:42 PM PDT 24
Peak memory 217896 kb
Host smart-8728c043-e2b1-4985-878e-7a1aaf7b3f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938958418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.938958418
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2938834465
Short name T486
Test name
Test status
Simulation time 42255478 ps
CPU time 0.94 seconds
Started Jun 22 06:21:41 PM PDT 24
Finished Jun 22 06:21:43 PM PDT 24
Peak memory 214988 kb
Host smart-2f7ecd0a-234b-4e22-ad4e-89f7f502d958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938834465 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2938834465
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3063080356
Short name T492
Test name
Test status
Simulation time 14751554 ps
CPU time 0.98 seconds
Started Jun 22 06:21:41 PM PDT 24
Finished Jun 22 06:21:43 PM PDT 24
Peak memory 214624 kb
Host smart-9ec89936-a865-49b7-be52-7d731564a16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063080356 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3063080356
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3811027668
Short name T193
Test name
Test status
Simulation time 33194553 ps
CPU time 1.12 seconds
Started Jun 22 06:21:43 PM PDT 24
Finished Jun 22 06:21:45 PM PDT 24
Peak memory 214624 kb
Host smart-5ac7a7e6-648b-4d52-aebb-20533e221cbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811027668 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3811027668
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.4051919777
Short name T229
Test name
Test status
Simulation time 137585354970 ps
CPU time 1542.64 seconds
Started Jun 22 06:21:39 PM PDT 24
Finished Jun 22 06:47:23 PM PDT 24
Peak memory 222332 kb
Host smart-79e5057f-2c0b-4d0f-961e-202946200180
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051919777 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.4051919777
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3210635540
Short name T621
Test name
Test status
Simulation time 22717079 ps
CPU time 1.21 seconds
Started Jun 22 06:21:45 PM PDT 24
Finished Jun 22 06:21:47 PM PDT 24
Peak memory 215088 kb
Host smart-0011906c-93bb-40c2-b4ad-ac8ee0d0eacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210635540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3210635540
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1158935374
Short name T720
Test name
Test status
Simulation time 49832612 ps
CPU time 0.85 seconds
Started Jun 22 06:21:45 PM PDT 24
Finished Jun 22 06:21:46 PM PDT 24
Peak memory 206248 kb
Host smart-781a534a-fa06-4f08-80f1-ca62a54c4944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158935374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1158935374
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.4107283152
Short name T401
Test name
Test status
Simulation time 43804282 ps
CPU time 0.87 seconds
Started Jun 22 06:21:50 PM PDT 24
Finished Jun 22 06:21:51 PM PDT 24
Peak memory 215688 kb
Host smart-f1223286-cc86-4705-b060-1d6cbc0dc11e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107283152 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.4107283152
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2144135017
Short name T476
Test name
Test status
Simulation time 31964827 ps
CPU time 1.09 seconds
Started Jun 22 06:21:51 PM PDT 24
Finished Jun 22 06:21:52 PM PDT 24
Peak memory 218592 kb
Host smart-bbf2a2ec-d103-47a8-95f1-96151f37e146
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144135017 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2144135017
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3017451751
Short name T147
Test name
Test status
Simulation time 29797937 ps
CPU time 1.27 seconds
Started Jun 22 06:21:47 PM PDT 24
Finished Jun 22 06:21:49 PM PDT 24
Peak memory 216552 kb
Host smart-01011042-b5f4-434d-8327-a5aec95c8275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017451751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3017451751
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_intr.2028028217
Short name T35
Test name
Test status
Simulation time 32700259 ps
CPU time 0.91 seconds
Started Jun 22 06:21:45 PM PDT 24
Finished Jun 22 06:21:47 PM PDT 24
Peak memory 214980 kb
Host smart-ba499c87-3c98-401e-8ea1-3cb018d5e703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028028217 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2028028217
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2931136056
Short name T541
Test name
Test status
Simulation time 22915631 ps
CPU time 0.9 seconds
Started Jun 22 06:21:51 PM PDT 24
Finished Jun 22 06:21:52 PM PDT 24
Peak memory 214644 kb
Host smart-ccab4edd-ea43-47cd-b2cf-4615884429a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931136056 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2931136056
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1543303894
Short name T4
Test name
Test status
Simulation time 889555658 ps
CPU time 5.04 seconds
Started Jun 22 06:21:45 PM PDT 24
Finished Jun 22 06:21:51 PM PDT 24
Peak memory 214636 kb
Host smart-dee42d2b-7a44-4fd3-8d46-ebe54adee4ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543303894 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1543303894
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3446531468
Short name T466
Test name
Test status
Simulation time 311722553968 ps
CPU time 2162.05 seconds
Started Jun 22 06:21:52 PM PDT 24
Finished Jun 22 06:57:55 PM PDT 24
Peak memory 226668 kb
Host smart-e8ef17b1-32aa-4e34-b759-43dede269ded
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446531468 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3446531468
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3893997685
Short name T267
Test name
Test status
Simulation time 129946843 ps
CPU time 1.14 seconds
Started Jun 22 06:21:56 PM PDT 24
Finished Jun 22 06:21:58 PM PDT 24
Peak memory 219904 kb
Host smart-f223bfd6-a1cb-44ff-a5dd-bd0c6fd9d829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893997685 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3893997685
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3337890272
Short name T365
Test name
Test status
Simulation time 16558352 ps
CPU time 0.98 seconds
Started Jun 22 06:21:56 PM PDT 24
Finished Jun 22 06:21:58 PM PDT 24
Peak memory 206108 kb
Host smart-971a7fa8-e287-43d5-8808-e7884010a9e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337890272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3337890272
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3332828155
Short name T677
Test name
Test status
Simulation time 41366658 ps
CPU time 0.89 seconds
Started Jun 22 06:21:53 PM PDT 24
Finished Jun 22 06:21:54 PM PDT 24
Peak memory 215796 kb
Host smart-a11ae1b3-b87e-485c-bdca-f00f4c31d630
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332828155 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3332828155
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3109322418
Short name T745
Test name
Test status
Simulation time 300759133 ps
CPU time 1.31 seconds
Started Jun 22 06:21:53 PM PDT 24
Finished Jun 22 06:21:55 PM PDT 24
Peak memory 216272 kb
Host smart-28c25682-b44b-4c81-ae99-68125df70611
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109322418 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3109322418
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2078107748
Short name T666
Test name
Test status
Simulation time 18835305 ps
CPU time 1.19 seconds
Started Jun 22 06:21:55 PM PDT 24
Finished Jun 22 06:21:57 PM PDT 24
Peak memory 223364 kb
Host smart-6a467081-2d01-4aee-9c27-13df6e922f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078107748 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2078107748
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3519400963
Short name T45
Test name
Test status
Simulation time 76672123 ps
CPU time 2.95 seconds
Started Jun 22 06:21:53 PM PDT 24
Finished Jun 22 06:21:56 PM PDT 24
Peak memory 219608 kb
Host smart-a0ad56de-4018-4428-937d-dbfa89abd49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519400963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3519400963
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2352982571
Short name T569
Test name
Test status
Simulation time 20497085 ps
CPU time 1.1 seconds
Started Jun 22 06:21:54 PM PDT 24
Finished Jun 22 06:21:56 PM PDT 24
Peak memory 215068 kb
Host smart-b0ee597b-9f23-4869-8415-94f78bc7a5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352982571 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2352982571
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2419470446
Short name T404
Test name
Test status
Simulation time 31720495 ps
CPU time 1.03 seconds
Started Jun 22 06:21:47 PM PDT 24
Finished Jun 22 06:21:49 PM PDT 24
Peak memory 214620 kb
Host smart-66ed6923-a625-4922-9282-6a555833cf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419470446 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2419470446
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2844163414
Short name T357
Test name
Test status
Simulation time 315247175 ps
CPU time 6.62 seconds
Started Jun 22 06:21:47 PM PDT 24
Finished Jun 22 06:21:54 PM PDT 24
Peak memory 214704 kb
Host smart-8d5fc738-e83e-49da-bf9c-7282c51b76a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844163414 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2844163414
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3732092293
Short name T561
Test name
Test status
Simulation time 419270480624 ps
CPU time 2656.92 seconds
Started Jun 22 06:21:53 PM PDT 24
Finished Jun 22 07:06:11 PM PDT 24
Peak memory 227860 kb
Host smart-2ef90e42-df5f-4b32-96b2-a7ea6adc16f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732092293 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3732092293
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.3195851265
Short name T164
Test name
Test status
Simulation time 67223910 ps
CPU time 1.13 seconds
Started Jun 22 06:21:53 PM PDT 24
Finished Jun 22 06:21:55 PM PDT 24
Peak memory 220572 kb
Host smart-f20a26f5-709c-4637-a3ff-0f2c4527ea68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195851265 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3195851265
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1241863022
Short name T852
Test name
Test status
Simulation time 23321027 ps
CPU time 0.88 seconds
Started Jun 22 06:21:53 PM PDT 24
Finished Jun 22 06:21:55 PM PDT 24
Peak memory 206112 kb
Host smart-5d92d65d-96e4-4385-9920-8fc92f010d79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241863022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1241863022
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2774135246
Short name T209
Test name
Test status
Simulation time 37153556 ps
CPU time 0.82 seconds
Started Jun 22 06:21:52 PM PDT 24
Finished Jun 22 06:21:54 PM PDT 24
Peak memory 215624 kb
Host smart-c019fe19-c04b-47ce-8445-85921bb57491
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774135246 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2774135246
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.4012034965
Short name T866
Test name
Test status
Simulation time 39876405 ps
CPU time 1.2 seconds
Started Jun 22 06:21:55 PM PDT 24
Finished Jun 22 06:21:57 PM PDT 24
Peak memory 216332 kb
Host smart-a8c526d5-95d3-468b-8d0b-8929eb69ea09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012034965 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.4012034965
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.392328189
Short name T79
Test name
Test status
Simulation time 31010790 ps
CPU time 0.92 seconds
Started Jun 22 06:21:56 PM PDT 24
Finished Jun 22 06:21:58 PM PDT 24
Peak memory 217844 kb
Host smart-d864cc29-c78b-49a0-8a88-df9d75aa10cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392328189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.392328189
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2929624111
Short name T517
Test name
Test status
Simulation time 37289506 ps
CPU time 1.09 seconds
Started Jun 22 06:21:54 PM PDT 24
Finished Jun 22 06:21:56 PM PDT 24
Peak memory 217888 kb
Host smart-89e57912-6de1-4ba9-bc35-f5d3684cb5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929624111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2929624111
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3027314993
Short name T567
Test name
Test status
Simulation time 19541473 ps
CPU time 1.11 seconds
Started Jun 22 06:21:54 PM PDT 24
Finished Jun 22 06:21:56 PM PDT 24
Peak memory 215044 kb
Host smart-350d95e5-4b2c-4caf-afd8-ff55b2656617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027314993 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3027314993
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2728691357
Short name T838
Test name
Test status
Simulation time 17537538 ps
CPU time 1.02 seconds
Started Jun 22 06:21:53 PM PDT 24
Finished Jun 22 06:21:55 PM PDT 24
Peak memory 214628 kb
Host smart-902f7b59-3399-41c0-8d84-de77b0eb5bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728691357 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2728691357
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2288035449
Short name T289
Test name
Test status
Simulation time 349813894 ps
CPU time 2.21 seconds
Started Jun 22 06:21:54 PM PDT 24
Finished Jun 22 06:21:57 PM PDT 24
Peak memory 216384 kb
Host smart-e350f97c-fe59-465a-b459-4ae0123d4a6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288035449 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2288035449
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3242458255
Short name T396
Test name
Test status
Simulation time 359947344447 ps
CPU time 878.67 seconds
Started Jun 22 06:21:52 PM PDT 24
Finished Jun 22 06:36:32 PM PDT 24
Peak memory 219892 kb
Host smart-818c1526-543e-4e93-9716-db6e1f2dfdf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242458255 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3242458255
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.75995661
Short name T89
Test name
Test status
Simulation time 31859101 ps
CPU time 1.18 seconds
Started Jun 22 06:21:53 PM PDT 24
Finished Jun 22 06:21:56 PM PDT 24
Peak memory 220564 kb
Host smart-ce4a7c39-a6dd-46fb-9c48-ca19a4a5aa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75995661 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.75995661
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1833960324
Short name T57
Test name
Test status
Simulation time 33862225 ps
CPU time 0.91 seconds
Started Jun 22 06:21:54 PM PDT 24
Finished Jun 22 06:21:56 PM PDT 24
Peak memory 206092 kb
Host smart-8825503f-43a3-494b-a210-ead6ae10161b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833960324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1833960324
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3187010978
Short name T218
Test name
Test status
Simulation time 10509285 ps
CPU time 0.88 seconds
Started Jun 22 06:21:54 PM PDT 24
Finished Jun 22 06:21:55 PM PDT 24
Peak memory 215688 kb
Host smart-54f2afe1-c880-432b-9527-b8cc9eac707e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187010978 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3187010978
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.4039542364
Short name T242
Test name
Test status
Simulation time 72089832 ps
CPU time 1.11 seconds
Started Jun 22 06:21:55 PM PDT 24
Finished Jun 22 06:21:57 PM PDT 24
Peak memory 219116 kb
Host smart-c971092e-6cc3-497e-a104-08fb89f96353
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039542364 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.4039542364
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.606132655
Short name T612
Test name
Test status
Simulation time 19259095 ps
CPU time 1.06 seconds
Started Jun 22 06:21:56 PM PDT 24
Finished Jun 22 06:21:57 PM PDT 24
Peak memory 218132 kb
Host smart-1a9542e4-f02c-4d3e-853f-371512eade3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606132655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.606132655
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3744294150
Short name T394
Test name
Test status
Simulation time 86374429 ps
CPU time 1.4 seconds
Started Jun 22 06:21:53 PM PDT 24
Finished Jun 22 06:21:55 PM PDT 24
Peak memory 219316 kb
Host smart-dd8ac9ad-2bfc-43d4-a5c4-6c1426404675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744294150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3744294150
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2946389473
Short name T772
Test name
Test status
Simulation time 49056998 ps
CPU time 0.93 seconds
Started Jun 22 06:21:52 PM PDT 24
Finished Jun 22 06:21:54 PM PDT 24
Peak memory 214716 kb
Host smart-595aa835-2074-40b2-8c49-d0611be5c025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946389473 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2946389473
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1220129924
Short name T761
Test name
Test status
Simulation time 21991119 ps
CPU time 1.05 seconds
Started Jun 22 06:21:53 PM PDT 24
Finished Jun 22 06:21:54 PM PDT 24
Peak memory 214608 kb
Host smart-1b7098de-c116-480d-bd1a-f9c402b5beb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220129924 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1220129924
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3995359643
Short name T237
Test name
Test status
Simulation time 169957792 ps
CPU time 1.75 seconds
Started Jun 22 06:21:53 PM PDT 24
Finished Jun 22 06:21:55 PM PDT 24
Peak memory 216540 kb
Host smart-f788d911-03bd-4e56-b284-4d8725cf588f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995359643 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3995359643
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_alert.2035768980
Short name T719
Test name
Test status
Simulation time 105627130 ps
CPU time 1.34 seconds
Started Jun 22 06:22:03 PM PDT 24
Finished Jun 22 06:22:05 PM PDT 24
Peak memory 218340 kb
Host smart-560bcc04-6bc9-4ba9-9716-7ce6458339de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035768980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2035768980
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.4186957223
Short name T414
Test name
Test status
Simulation time 46939885 ps
CPU time 0.96 seconds
Started Jun 22 06:22:00 PM PDT 24
Finished Jun 22 06:22:01 PM PDT 24
Peak memory 214392 kb
Host smart-33b8800e-1fca-4353-b683-a3ed7d5e290f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186957223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.4186957223
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3120519185
Short name T149
Test name
Test status
Simulation time 76942489 ps
CPU time 1.04 seconds
Started Jun 22 06:22:00 PM PDT 24
Finished Jun 22 06:22:02 PM PDT 24
Peak memory 216388 kb
Host smart-30bb076c-edfa-49d5-b71d-a09e48be9380
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120519185 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3120519185
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2270249586
Short name T964
Test name
Test status
Simulation time 19852317 ps
CPU time 1.19 seconds
Started Jun 22 06:22:02 PM PDT 24
Finished Jun 22 06:22:04 PM PDT 24
Peak memory 223372 kb
Host smart-7709a821-ddfe-43ff-92d7-be0d0fa537f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270249586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2270249586
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1639092263
Short name T509
Test name
Test status
Simulation time 525953501 ps
CPU time 4.85 seconds
Started Jun 22 06:21:59 PM PDT 24
Finished Jun 22 06:22:05 PM PDT 24
Peak memory 219636 kb
Host smart-3f2bf28f-aba2-4b2d-8152-89111387f61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639092263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1639092263
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1195290045
Short name T465
Test name
Test status
Simulation time 26145120 ps
CPU time 1.06 seconds
Started Jun 22 06:22:00 PM PDT 24
Finished Jun 22 06:22:01 PM PDT 24
Peak memory 223396 kb
Host smart-19d44f20-7dde-4bc0-8f77-1fa5585d5731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195290045 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1195290045
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2028719209
Short name T653
Test name
Test status
Simulation time 46344657 ps
CPU time 0.86 seconds
Started Jun 22 06:21:59 PM PDT 24
Finished Jun 22 06:22:00 PM PDT 24
Peak memory 214560 kb
Host smart-fcf8ea4b-a30e-4151-bc79-76dfad2f2fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028719209 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2028719209
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3696105297
Short name T824
Test name
Test status
Simulation time 101803020 ps
CPU time 2.42 seconds
Started Jun 22 06:21:58 PM PDT 24
Finished Jun 22 06:22:01 PM PDT 24
Peak memory 217844 kb
Host smart-f2284673-f28c-406a-8d84-cf98f0ebb505
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696105297 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3696105297
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1014368851
Short name T227
Test name
Test status
Simulation time 82826006587 ps
CPU time 936.14 seconds
Started Jun 22 06:22:00 PM PDT 24
Finished Jun 22 06:37:36 PM PDT 24
Peak memory 221200 kb
Host smart-68342d1d-c447-451e-8091-dcb91dd7cd2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014368851 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1014368851
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3198531792
Short name T146
Test name
Test status
Simulation time 28292863 ps
CPU time 1.19 seconds
Started Jun 22 06:22:07 PM PDT 24
Finished Jun 22 06:22:09 PM PDT 24
Peak memory 218160 kb
Host smart-32f44a33-9400-4064-851a-b1aa42187ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198531792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3198531792
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2945777466
Short name T525
Test name
Test status
Simulation time 25104856 ps
CPU time 0.9 seconds
Started Jun 22 06:22:09 PM PDT 24
Finished Jun 22 06:22:10 PM PDT 24
Peak memory 214172 kb
Host smart-06220c88-adf3-4e10-b849-22cf47c24765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945777466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2945777466
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2603402191
Short name T210
Test name
Test status
Simulation time 38473857 ps
CPU time 0.89 seconds
Started Jun 22 06:22:09 PM PDT 24
Finished Jun 22 06:22:10 PM PDT 24
Peak memory 215816 kb
Host smart-19148a6a-da6f-4672-ae27-1ac74c0f5fb8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603402191 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2603402191
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.4138328313
Short name T151
Test name
Test status
Simulation time 161250799 ps
CPU time 1.18 seconds
Started Jun 22 06:22:09 PM PDT 24
Finished Jun 22 06:22:10 PM PDT 24
Peak memory 216356 kb
Host smart-545ea759-a929-426c-a65d-283fe87b97b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138328313 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.4138328313
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1771753499
Short name T504
Test name
Test status
Simulation time 25324006 ps
CPU time 1.12 seconds
Started Jun 22 06:22:09 PM PDT 24
Finished Jun 22 06:22:10 PM PDT 24
Peak memory 223572 kb
Host smart-acfbb519-fb00-4c0d-87e9-0d0cd0f22066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771753499 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1771753499
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.495755821
Short name T459
Test name
Test status
Simulation time 80049306 ps
CPU time 1.54 seconds
Started Jun 22 06:21:59 PM PDT 24
Finished Jun 22 06:22:01 PM PDT 24
Peak memory 218368 kb
Host smart-94055265-05d4-4821-b1a1-1df5737b523e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495755821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.495755821
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.718554014
Short name T603
Test name
Test status
Simulation time 39414914 ps
CPU time 1.04 seconds
Started Jun 22 06:21:58 PM PDT 24
Finished Jun 22 06:21:59 PM PDT 24
Peak memory 223352 kb
Host smart-0c2c5c3d-c412-441a-bf3a-da69523289fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718554014 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.718554014
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3252551800
Short name T784
Test name
Test status
Simulation time 18617936 ps
CPU time 1.02 seconds
Started Jun 22 06:21:59 PM PDT 24
Finished Jun 22 06:22:00 PM PDT 24
Peak memory 214644 kb
Host smart-82dba3bf-8180-4f38-808b-76fde2a259f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252551800 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3252551800
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3578741338
Short name T890
Test name
Test status
Simulation time 258568413 ps
CPU time 1.48 seconds
Started Jun 22 06:22:02 PM PDT 24
Finished Jun 22 06:22:04 PM PDT 24
Peak memory 214640 kb
Host smart-78493118-cc2d-48ff-b816-1f723d965d6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578741338 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3578741338
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3771041945
Short name T230
Test name
Test status
Simulation time 207479197447 ps
CPU time 896.12 seconds
Started Jun 22 06:21:59 PM PDT 24
Finished Jun 22 06:36:55 PM PDT 24
Peak memory 219860 kb
Host smart-3a41479d-24b8-4c55-b03d-71669d71215e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771041945 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3771041945
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2641689648
Short name T817
Test name
Test status
Simulation time 37655342 ps
CPU time 1.14 seconds
Started Jun 22 06:22:09 PM PDT 24
Finished Jun 22 06:22:11 PM PDT 24
Peak memory 217936 kb
Host smart-44eb64ef-e7b0-405f-a252-6fa06e3431a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641689648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2641689648
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.4044993655
Short name T490
Test name
Test status
Simulation time 24453122 ps
CPU time 1.05 seconds
Started Jun 22 06:22:09 PM PDT 24
Finished Jun 22 06:22:10 PM PDT 24
Peak memory 206316 kb
Host smart-707907cf-675b-4cd5-9671-6dedcc1f6ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044993655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.4044993655
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.563116954
Short name T197
Test name
Test status
Simulation time 49933021 ps
CPU time 0.86 seconds
Started Jun 22 06:22:07 PM PDT 24
Finished Jun 22 06:22:09 PM PDT 24
Peak memory 215820 kb
Host smart-987072d1-1125-4a72-9492-5470aebbe5a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563116954 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.563116954
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2255487985
Short name T702
Test name
Test status
Simulation time 21156358 ps
CPU time 1.35 seconds
Started Jun 22 06:22:07 PM PDT 24
Finished Jun 22 06:22:09 PM PDT 24
Peak memory 216148 kb
Host smart-131e467a-c115-405d-a9bd-9bf8f0f2750b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255487985 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2255487985
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1762281395
Short name T103
Test name
Test status
Simulation time 30889285 ps
CPU time 0.94 seconds
Started Jun 22 06:22:07 PM PDT 24
Finished Jun 22 06:22:08 PM PDT 24
Peak memory 218904 kb
Host smart-1ccf16f5-fd7b-4daa-a77d-f19cd8bbdd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762281395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1762281395
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3487991287
Short name T820
Test name
Test status
Simulation time 85312529 ps
CPU time 1.27 seconds
Started Jun 22 06:22:07 PM PDT 24
Finished Jun 22 06:22:08 PM PDT 24
Peak memory 219464 kb
Host smart-7a371efa-20a7-4e78-b58e-500b1231f233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487991287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3487991287
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.666204123
Short name T705
Test name
Test status
Simulation time 34950669 ps
CPU time 0.93 seconds
Started Jun 22 06:22:08 PM PDT 24
Finished Jun 22 06:22:10 PM PDT 24
Peak memory 214888 kb
Host smart-9d9913a2-ca36-45ed-a63e-9c7b4451ced3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666204123 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.666204123
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1284464105
Short name T326
Test name
Test status
Simulation time 18880546 ps
CPU time 0.99 seconds
Started Jun 22 06:22:08 PM PDT 24
Finished Jun 22 06:22:10 PM PDT 24
Peak memory 214624 kb
Host smart-f0e29d7b-b053-44a0-9d78-fff00b96a742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284464105 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1284464105
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1844065510
Short name T340
Test name
Test status
Simulation time 281674331 ps
CPU time 5.82 seconds
Started Jun 22 06:22:11 PM PDT 24
Finished Jun 22 06:22:17 PM PDT 24
Peak memory 214740 kb
Host smart-4d874b66-9e29-4605-881f-ab9ae19440f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844065510 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1844065510
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2460823616
Short name T872
Test name
Test status
Simulation time 85344241205 ps
CPU time 1947.45 seconds
Started Jun 22 06:22:11 PM PDT 24
Finished Jun 22 06:54:39 PM PDT 24
Peak memory 227904 kb
Host smart-6816f6a8-28a2-4318-8e8b-243ddc2bb070
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460823616 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2460823616
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert_test.3322598421
Short name T703
Test name
Test status
Simulation time 49760768 ps
CPU time 0.92 seconds
Started Jun 22 06:22:09 PM PDT 24
Finished Jun 22 06:22:10 PM PDT 24
Peak memory 206116 kb
Host smart-4f7f520d-e179-49cc-a4b4-f9e1f1b66ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322598421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3322598421
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3275619361
Short name T594
Test name
Test status
Simulation time 41005463 ps
CPU time 1.33 seconds
Started Jun 22 06:22:07 PM PDT 24
Finished Jun 22 06:22:09 PM PDT 24
Peak memory 215084 kb
Host smart-ea8ad49f-d5fe-4282-87a2-108027eb509f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275619361 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3275619361
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1415323189
Short name T201
Test name
Test status
Simulation time 27536915 ps
CPU time 1.02 seconds
Started Jun 22 06:22:07 PM PDT 24
Finished Jun 22 06:22:09 PM PDT 24
Peak memory 219112 kb
Host smart-b9c92ce0-a718-4694-ac4c-04c415ec9ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415323189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1415323189
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1371105199
Short name T814
Test name
Test status
Simulation time 322783967 ps
CPU time 3.71 seconds
Started Jun 22 06:22:06 PM PDT 24
Finished Jun 22 06:22:11 PM PDT 24
Peak memory 219460 kb
Host smart-ac44230e-9a31-46a4-924a-2fd5e4d7fe65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371105199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1371105199
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.962633667
Short name T980
Test name
Test status
Simulation time 33523032 ps
CPU time 0.9 seconds
Started Jun 22 06:22:08 PM PDT 24
Finished Jun 22 06:22:09 PM PDT 24
Peak memory 214764 kb
Host smart-a36036cf-7fc8-4ae2-90e1-86bf85cf426c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962633667 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.962633667
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3625152578
Short name T368
Test name
Test status
Simulation time 36885835 ps
CPU time 0.91 seconds
Started Jun 22 06:22:07 PM PDT 24
Finished Jun 22 06:22:09 PM PDT 24
Peak memory 214648 kb
Host smart-34961065-9f95-43f7-8bb8-ab5dc241e943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625152578 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3625152578
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3215626561
Short name T428
Test name
Test status
Simulation time 375609081 ps
CPU time 1.66 seconds
Started Jun 22 06:22:06 PM PDT 24
Finished Jun 22 06:22:08 PM PDT 24
Peak memory 214604 kb
Host smart-380a19d8-2f8e-411b-ba80-dfb052253b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215626561 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3215626561
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2888989387
Short name T228
Test name
Test status
Simulation time 400440698873 ps
CPU time 692.82 seconds
Started Jun 22 06:22:07 PM PDT 24
Finished Jun 22 06:33:41 PM PDT 24
Peak memory 219016 kb
Host smart-486009cd-8f9c-45b3-b52c-c4fccbb30fb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888989387 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2888989387
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2628306978
Short name T240
Test name
Test status
Simulation time 99243349 ps
CPU time 1.21 seconds
Started Jun 22 06:22:21 PM PDT 24
Finished Jun 22 06:22:23 PM PDT 24
Peak memory 219108 kb
Host smart-278d882a-ce5f-4f0f-b188-1fa66e8099c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628306978 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2628306978
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2216381304
Short name T391
Test name
Test status
Simulation time 27548412 ps
CPU time 0.91 seconds
Started Jun 22 06:22:14 PM PDT 24
Finished Jun 22 06:22:16 PM PDT 24
Peak memory 206032 kb
Host smart-a24900c9-36ec-4663-8e46-292836601f44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216381304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2216381304
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3167647282
Short name T626
Test name
Test status
Simulation time 73827427 ps
CPU time 0.79 seconds
Started Jun 22 06:22:15 PM PDT 24
Finished Jun 22 06:22:16 PM PDT 24
Peak memory 215324 kb
Host smart-d8367cc8-834d-4695-bfef-7e47a9f6adef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167647282 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3167647282
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2032548169
Short name T775
Test name
Test status
Simulation time 21416008 ps
CPU time 0.97 seconds
Started Jun 22 06:22:21 PM PDT 24
Finished Jun 22 06:22:22 PM PDT 24
Peak memory 217616 kb
Host smart-65e6dcff-b3cb-409d-859a-828385a2a72a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032548169 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2032548169
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3173419686
Short name T944
Test name
Test status
Simulation time 30217656 ps
CPU time 1.07 seconds
Started Jun 22 06:22:18 PM PDT 24
Finished Jun 22 06:22:19 PM PDT 24
Peak memory 219324 kb
Host smart-c77ba9fd-c1ba-4316-aa08-50d242a48426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173419686 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3173419686
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_intr.3085053755
Short name T53
Test name
Test status
Simulation time 35109491 ps
CPU time 1.01 seconds
Started Jun 22 06:22:16 PM PDT 24
Finished Jun 22 06:22:17 PM PDT 24
Peak memory 223392 kb
Host smart-4f8fed20-27a0-43d1-aeba-29adeec8fe60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085053755 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3085053755
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3894847093
Short name T673
Test name
Test status
Simulation time 29110030 ps
CPU time 0.89 seconds
Started Jun 22 06:22:14 PM PDT 24
Finished Jun 22 06:22:16 PM PDT 24
Peak memory 214616 kb
Host smart-09bf668a-4b99-4ebf-b3b8-01dbd6b50973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894847093 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3894847093
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.324913201
Short name T333
Test name
Test status
Simulation time 261395148 ps
CPU time 3.41 seconds
Started Jun 22 06:22:15 PM PDT 24
Finished Jun 22 06:22:19 PM PDT 24
Peak memory 214572 kb
Host smart-5469ca27-f00f-434c-9a84-830b350d0d3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324913201 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.324913201
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2699286130
Short name T732
Test name
Test status
Simulation time 104467108737 ps
CPU time 1015.38 seconds
Started Jun 22 06:22:14 PM PDT 24
Finished Jun 22 06:39:09 PM PDT 24
Peak memory 222800 kb
Host smart-3532edfc-faaa-44fd-89e2-6d5aea59962c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699286130 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2699286130
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1453170108
Short name T474
Test name
Test status
Simulation time 51693170 ps
CPU time 1.18 seconds
Started Jun 22 06:19:38 PM PDT 24
Finished Jun 22 06:19:39 PM PDT 24
Peak memory 219000 kb
Host smart-fcfec03a-4f65-4b8a-9e0b-d2491b80542f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453170108 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1453170108
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2297726198
Short name T337
Test name
Test status
Simulation time 57010557 ps
CPU time 0.84 seconds
Started Jun 22 06:19:36 PM PDT 24
Finished Jun 22 06:19:37 PM PDT 24
Peak memory 205820 kb
Host smart-32e067ba-6d5e-4420-8bf3-03150d34de1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297726198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2297726198
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1619808148
Short name T724
Test name
Test status
Simulation time 15453860 ps
CPU time 0.86 seconds
Started Jun 22 06:19:37 PM PDT 24
Finished Jun 22 06:19:38 PM PDT 24
Peak memory 215324 kb
Host smart-e8eed52d-fa03-4cee-b3f7-06a406c50356
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619808148 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1619808148
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_err.815573377
Short name T611
Test name
Test status
Simulation time 44253813 ps
CPU time 0.89 seconds
Started Jun 22 06:19:37 PM PDT 24
Finished Jun 22 06:19:39 PM PDT 24
Peak memory 217968 kb
Host smart-a4981446-3148-472d-94a6-7b1e644d30b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815573377 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.815573377
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_intr.305525743
Short name T727
Test name
Test status
Simulation time 21691264 ps
CPU time 1.19 seconds
Started Jun 22 06:19:36 PM PDT 24
Finished Jun 22 06:19:38 PM PDT 24
Peak memory 223384 kb
Host smart-a2d71639-b108-4bf7-9a7d-0840bba68719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305525743 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.305525743
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1764890464
Short name T787
Test name
Test status
Simulation time 92750522 ps
CPU time 0.97 seconds
Started Jun 22 06:19:27 PM PDT 24
Finished Jun 22 06:19:29 PM PDT 24
Peak memory 206432 kb
Host smart-e348c338-530c-411d-b333-5fe426bfcdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764890464 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1764890464
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2349827260
Short name T825
Test name
Test status
Simulation time 35962209 ps
CPU time 0.89 seconds
Started Jun 22 06:19:30 PM PDT 24
Finished Jun 22 06:19:31 PM PDT 24
Peak memory 214624 kb
Host smart-d98ab4a5-9ed9-4d1f-867f-4d50e6bbf4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349827260 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2349827260
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1318299757
Short name T903
Test name
Test status
Simulation time 322718247 ps
CPU time 5.84 seconds
Started Jun 22 06:19:34 PM PDT 24
Finished Jun 22 06:19:40 PM PDT 24
Peak memory 217916 kb
Host smart-23db0370-ed29-48de-93d2-cdc9b2fb934e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318299757 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1318299757
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/50.edn_alert.3158278456
Short name T769
Test name
Test status
Simulation time 278340669 ps
CPU time 1.37 seconds
Started Jun 22 06:22:14 PM PDT 24
Finished Jun 22 06:22:16 PM PDT 24
Peak memory 219936 kb
Host smart-497b1bbd-137d-42c8-9db3-8e7f33c31991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158278456 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.3158278456
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.582952027
Short name T69
Test name
Test status
Simulation time 203762461 ps
CPU time 1.09 seconds
Started Jun 22 06:22:14 PM PDT 24
Finished Jun 22 06:22:16 PM PDT 24
Peak memory 229124 kb
Host smart-fa0d9790-86b3-4725-a007-5f3cff0491e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582952027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.582952027
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.4200193341
Short name T544
Test name
Test status
Simulation time 64254364 ps
CPU time 1.28 seconds
Started Jun 22 06:22:16 PM PDT 24
Finished Jun 22 06:22:18 PM PDT 24
Peak memory 217676 kb
Host smart-8fe263d6-06d7-49cb-8286-6f024a64258d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200193341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.4200193341
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.4201162390
Short name T217
Test name
Test status
Simulation time 150066327 ps
CPU time 1.18 seconds
Started Jun 22 06:22:15 PM PDT 24
Finished Jun 22 06:22:17 PM PDT 24
Peak memory 218516 kb
Host smart-e4bee350-ba35-4fd5-b198-134fc3ed4449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201162390 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.4201162390
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.1192420872
Short name T163
Test name
Test status
Simulation time 22912118 ps
CPU time 1.08 seconds
Started Jun 22 06:22:14 PM PDT 24
Finished Jun 22 06:22:15 PM PDT 24
Peak memory 223316 kb
Host smart-c61643eb-bca9-4e43-aa37-940b2436f9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192420872 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1192420872
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2014049629
Short name T296
Test name
Test status
Simulation time 115371824 ps
CPU time 1.73 seconds
Started Jun 22 06:22:21 PM PDT 24
Finished Jun 22 06:22:23 PM PDT 24
Peak memory 218176 kb
Host smart-93ffe703-8da7-44c2-bc95-a3638ba68c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014049629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2014049629
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.4011591536
Short name T891
Test name
Test status
Simulation time 51367832 ps
CPU time 1.3 seconds
Started Jun 22 06:22:14 PM PDT 24
Finished Jun 22 06:22:17 PM PDT 24
Peak memory 220840 kb
Host smart-803b51e8-6a32-447e-bed3-54ae2e80427c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011591536 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.4011591536
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.326219043
Short name T176
Test name
Test status
Simulation time 39704936 ps
CPU time 1.02 seconds
Started Jun 22 06:22:23 PM PDT 24
Finished Jun 22 06:22:25 PM PDT 24
Peak memory 223224 kb
Host smart-82bd05a4-65de-4b2f-9e86-9e3282d8a973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326219043 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.326219043
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.4128128531
Short name T862
Test name
Test status
Simulation time 35534190 ps
CPU time 1.41 seconds
Started Jun 22 06:22:21 PM PDT 24
Finished Jun 22 06:22:23 PM PDT 24
Peak memory 219304 kb
Host smart-82b75c03-0aa1-4c38-a5e2-1e91c5623c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128128531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.4128128531
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.2082808572
Short name T346
Test name
Test status
Simulation time 67267038 ps
CPU time 1.09 seconds
Started Jun 22 06:22:14 PM PDT 24
Finished Jun 22 06:22:16 PM PDT 24
Peak memory 217836 kb
Host smart-388957ad-2ddc-492f-9af2-fccadcb47419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082808572 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.2082808572
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.1333584457
Short name T138
Test name
Test status
Simulation time 32373814 ps
CPU time 1.16 seconds
Started Jun 22 06:22:13 PM PDT 24
Finished Jun 22 06:22:14 PM PDT 24
Peak memory 229012 kb
Host smart-21cb8e9e-7e23-447e-9148-f23aa6788efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333584457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1333584457
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3378188021
Short name T388
Test name
Test status
Simulation time 49026530 ps
CPU time 1.8 seconds
Started Jun 22 06:22:16 PM PDT 24
Finished Jun 22 06:22:19 PM PDT 24
Peak memory 217892 kb
Host smart-6467889a-a217-4364-9a8a-d8672b065e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378188021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3378188021
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.3745686913
Short name T879
Test name
Test status
Simulation time 70364984 ps
CPU time 1.18 seconds
Started Jun 22 06:22:17 PM PDT 24
Finished Jun 22 06:22:19 PM PDT 24
Peak memory 218020 kb
Host smart-5ff71b20-93a3-47d5-9a09-afeadb97b4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745686913 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3745686913
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2310766368
Short name T534
Test name
Test status
Simulation time 31805203 ps
CPU time 0.9 seconds
Started Jun 22 06:22:16 PM PDT 24
Finished Jun 22 06:22:18 PM PDT 24
Peak memory 218544 kb
Host smart-852000b7-84a2-4383-9981-adc546768f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310766368 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2310766368
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.673402468
Short name T496
Test name
Test status
Simulation time 30825928 ps
CPU time 1.46 seconds
Started Jun 22 06:22:17 PM PDT 24
Finished Jun 22 06:22:19 PM PDT 24
Peak memory 216716 kb
Host smart-d1765620-fa61-4501-9b3c-614ba606ff81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673402468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.673402468
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.1191273005
Short name T572
Test name
Test status
Simulation time 24483129 ps
CPU time 1.24 seconds
Started Jun 22 06:22:14 PM PDT 24
Finished Jun 22 06:22:17 PM PDT 24
Peak memory 218524 kb
Host smart-04f00c32-fee4-49de-a397-0fba3901f389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191273005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.1191273005
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.4174398228
Short name T50
Test name
Test status
Simulation time 18425660 ps
CPU time 1.19 seconds
Started Jun 22 06:22:19 PM PDT 24
Finished Jun 22 06:22:21 PM PDT 24
Peak memory 223336 kb
Host smart-9035bc76-b1dc-4191-9852-a45a842bed0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174398228 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.4174398228
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2038089458
Short name T889
Test name
Test status
Simulation time 39680176 ps
CPU time 1.28 seconds
Started Jun 22 06:22:15 PM PDT 24
Finished Jun 22 06:22:17 PM PDT 24
Peak memory 219220 kb
Host smart-28b5ae7e-6ca2-4918-bbb9-8a5295620de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038089458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2038089458
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.2110606484
Short name T420
Test name
Test status
Simulation time 27921805 ps
CPU time 1.17 seconds
Started Jun 22 06:22:22 PM PDT 24
Finished Jun 22 06:22:24 PM PDT 24
Peak memory 219248 kb
Host smart-a83c6134-1bf2-48bf-9e2a-58bf461fef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110606484 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.2110606484
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.2044522759
Short name T795
Test name
Test status
Simulation time 19554841 ps
CPU time 1.12 seconds
Started Jun 22 06:22:23 PM PDT 24
Finished Jun 22 06:22:25 PM PDT 24
Peak memory 217964 kb
Host smart-788f2c78-91f7-4a77-8fbc-985812ea7c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044522759 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2044522759
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.794562920
Short name T683
Test name
Test status
Simulation time 43446201 ps
CPU time 1.76 seconds
Started Jun 22 06:22:16 PM PDT 24
Finished Jun 22 06:22:19 PM PDT 24
Peak memory 218044 kb
Host smart-6b8919f0-edbe-468f-ace4-23893cfdeaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794562920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.794562920
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.4001364974
Short name T187
Test name
Test status
Simulation time 73884540 ps
CPU time 1.1 seconds
Started Jun 22 06:22:21 PM PDT 24
Finished Jun 22 06:22:23 PM PDT 24
Peak memory 219352 kb
Host smart-9f0a083d-7e61-4fb4-a46c-81b147839937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001364974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.4001364974
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.2324644627
Short name T191
Test name
Test status
Simulation time 26484608 ps
CPU time 0.86 seconds
Started Jun 22 06:22:43 PM PDT 24
Finished Jun 22 06:22:45 PM PDT 24
Peak memory 218524 kb
Host smart-91a16fbd-846b-4fb6-9a9c-140e57de757a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324644627 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2324644627
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2052453796
Short name T989
Test name
Test status
Simulation time 46899917 ps
CPU time 1.15 seconds
Started Jun 22 06:22:20 PM PDT 24
Finished Jun 22 06:22:22 PM PDT 24
Peak memory 216660 kb
Host smart-20262dfb-7cf4-489c-831f-ed7de50222c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052453796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2052453796
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.3827911932
Short name T898
Test name
Test status
Simulation time 26426277 ps
CPU time 1.16 seconds
Started Jun 22 06:22:22 PM PDT 24
Finished Jun 22 06:22:24 PM PDT 24
Peak memory 215080 kb
Host smart-e2f2776e-04e7-4b88-be11-1470de97f319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827911932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.3827911932
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_genbits.322493475
Short name T847
Test name
Test status
Simulation time 46287640 ps
CPU time 1.13 seconds
Started Jun 22 06:22:23 PM PDT 24
Finished Jun 22 06:22:25 PM PDT 24
Peak memory 219256 kb
Host smart-0d691f8d-13bd-4d6f-8fd0-8ee424f5b3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322493475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.322493475
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.2563713741
Short name T709
Test name
Test status
Simulation time 56694307 ps
CPU time 1.28 seconds
Started Jun 22 06:22:27 PM PDT 24
Finished Jun 22 06:22:28 PM PDT 24
Peak memory 215088 kb
Host smart-36cb60ca-969a-4a37-9206-61eec78f34af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563713741 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.2563713741
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.3555322526
Short name T169
Test name
Test status
Simulation time 19301407 ps
CPU time 1.16 seconds
Started Jun 22 06:22:20 PM PDT 24
Finished Jun 22 06:22:21 PM PDT 24
Peak memory 223328 kb
Host smart-33f4aa5a-6644-45d6-8f50-b1f157f1fac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555322526 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3555322526
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3162921017
Short name T70
Test name
Test status
Simulation time 51932822 ps
CPU time 1.22 seconds
Started Jun 22 06:22:23 PM PDT 24
Finished Jun 22 06:22:25 PM PDT 24
Peak memory 219212 kb
Host smart-ea7faaa5-fcce-4be4-9b94-806e90c6f434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162921017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3162921017
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2589451435
Short name T607
Test name
Test status
Simulation time 80607368 ps
CPU time 1.32 seconds
Started Jun 22 06:19:34 PM PDT 24
Finished Jun 22 06:19:36 PM PDT 24
Peak memory 219156 kb
Host smart-c1f9a168-5966-43b7-8709-dede372b7fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589451435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2589451435
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2580265684
Short name T342
Test name
Test status
Simulation time 15481573 ps
CPU time 0.93 seconds
Started Jun 22 06:19:46 PM PDT 24
Finished Jun 22 06:19:48 PM PDT 24
Peak memory 206108 kb
Host smart-af4dec26-85f0-4ea6-8081-7906c429507b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580265684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2580265684
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1596527851
Short name T128
Test name
Test status
Simulation time 77948326 ps
CPU time 1.31 seconds
Started Jun 22 06:19:43 PM PDT 24
Finished Jun 22 06:19:45 PM PDT 24
Peak memory 216180 kb
Host smart-f6e9b36c-6a31-4c79-b4b7-1cd478c8b8eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596527851 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1596527851
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1331888750
Short name T162
Test name
Test status
Simulation time 18069442 ps
CPU time 1.07 seconds
Started Jun 22 06:19:44 PM PDT 24
Finished Jun 22 06:19:45 PM PDT 24
Peak memory 217744 kb
Host smart-6561342c-ca7f-424b-a6e7-1fbda457c015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331888750 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1331888750
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3492671116
Short name T804
Test name
Test status
Simulation time 40726662 ps
CPU time 1.04 seconds
Started Jun 22 06:19:35 PM PDT 24
Finished Jun 22 06:19:37 PM PDT 24
Peak memory 217936 kb
Host smart-29936930-fd6d-482f-9d98-1d9bcaf97420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492671116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3492671116
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.888740287
Short name T681
Test name
Test status
Simulation time 28780178 ps
CPU time 1.11 seconds
Started Jun 22 06:19:36 PM PDT 24
Finished Jun 22 06:19:38 PM PDT 24
Peak memory 223392 kb
Host smart-c351498f-b2a9-4339-930e-e4b1368cfbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888740287 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.888740287
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.394037551
Short name T28
Test name
Test status
Simulation time 31749003 ps
CPU time 0.99 seconds
Started Jun 22 06:19:35 PM PDT 24
Finished Jun 22 06:19:36 PM PDT 24
Peak memory 206448 kb
Host smart-eeb0748c-f021-4b49-b57e-7a2991dbe1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394037551 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.394037551
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.4076667109
Short name T345
Test name
Test status
Simulation time 18861638 ps
CPU time 0.99 seconds
Started Jun 22 06:19:34 PM PDT 24
Finished Jun 22 06:19:36 PM PDT 24
Peak memory 214624 kb
Host smart-6575eb69-8cb3-4786-b93e-5995da6ea1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076667109 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.4076667109
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3858048166
Short name T873
Test name
Test status
Simulation time 1642453983 ps
CPU time 5.23 seconds
Started Jun 22 06:19:35 PM PDT 24
Finished Jun 22 06:19:41 PM PDT 24
Peak memory 214640 kb
Host smart-10d8a9b9-2e8e-488d-b92e-f37a2f90fab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858048166 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3858048166
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.666266765
Short name T223
Test name
Test status
Simulation time 277623477586 ps
CPU time 1824.53 seconds
Started Jun 22 06:19:35 PM PDT 24
Finished Jun 22 06:50:00 PM PDT 24
Peak memory 227444 kb
Host smart-b8c03691-93c5-492e-9b90-2a91c9c5a87c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666266765 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.666266765
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.1637627345
Short name T491
Test name
Test status
Simulation time 40575747 ps
CPU time 1.11 seconds
Started Jun 22 06:22:22 PM PDT 24
Finished Jun 22 06:22:25 PM PDT 24
Peak memory 218252 kb
Host smart-0e2b82bf-dcf8-4a68-9c1e-4be82d905c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637627345 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1637627345
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.3403784316
Short name T132
Test name
Test status
Simulation time 26302943 ps
CPU time 1.23 seconds
Started Jun 22 06:22:22 PM PDT 24
Finished Jun 22 06:22:25 PM PDT 24
Peak memory 219832 kb
Host smart-e3564bc5-0009-4773-990c-80cf5e0ca403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403784316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3403784316
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3092648170
Short name T90
Test name
Test status
Simulation time 76754421 ps
CPU time 1.6 seconds
Started Jun 22 06:22:21 PM PDT 24
Finished Jun 22 06:22:23 PM PDT 24
Peak memory 218044 kb
Host smart-600555a4-b96b-418e-b8f2-de7a141dc825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092648170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3092648170
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1209134654
Short name T687
Test name
Test status
Simulation time 91449659 ps
CPU time 1.2 seconds
Started Jun 22 06:22:23 PM PDT 24
Finished Jun 22 06:22:25 PM PDT 24
Peak memory 217924 kb
Host smart-665d8285-654e-415d-b78e-6625758311bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209134654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1209134654
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.4151476335
Short name T597
Test name
Test status
Simulation time 43022855 ps
CPU time 1.12 seconds
Started Jun 22 06:22:21 PM PDT 24
Finished Jun 22 06:22:23 PM PDT 24
Peak memory 219468 kb
Host smart-6d52eb87-8a55-47a5-9cce-5de3abcadeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151476335 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.4151476335
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.725546420
Short name T760
Test name
Test status
Simulation time 67309520 ps
CPU time 1.17 seconds
Started Jun 22 06:22:23 PM PDT 24
Finished Jun 22 06:22:25 PM PDT 24
Peak memory 217724 kb
Host smart-6519609c-404e-407d-ba47-6b78a81e7c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725546420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.725546420
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.2492984914
Short name T679
Test name
Test status
Simulation time 100591250 ps
CPU time 1.11 seconds
Started Jun 22 06:22:22 PM PDT 24
Finished Jun 22 06:22:25 PM PDT 24
Peak memory 219956 kb
Host smart-5d789c90-2956-4286-8a17-ce643500d576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492984914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.2492984914
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.245102810
Short name T765
Test name
Test status
Simulation time 63676720 ps
CPU time 0.99 seconds
Started Jun 22 06:22:22 PM PDT 24
Finished Jun 22 06:22:24 PM PDT 24
Peak memory 223212 kb
Host smart-011ecf85-391e-4e03-b223-fa0fde6e52f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245102810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.245102810
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2497561161
Short name T483
Test name
Test status
Simulation time 96659451 ps
CPU time 1.7 seconds
Started Jun 22 06:22:22 PM PDT 24
Finished Jun 22 06:22:24 PM PDT 24
Peak memory 218224 kb
Host smart-568ec3ea-b2f3-4f8f-a9b5-d538fb5fa089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497561161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2497561161
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.2430654398
Short name T620
Test name
Test status
Simulation time 41787621 ps
CPU time 1.13 seconds
Started Jun 22 06:22:22 PM PDT 24
Finished Jun 22 06:22:23 PM PDT 24
Peak memory 218916 kb
Host smart-895a4040-2892-4594-a3e6-ae402c0da16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430654398 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2430654398
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.1375839236
Short name T716
Test name
Test status
Simulation time 29024098 ps
CPU time 0.88 seconds
Started Jun 22 06:22:23 PM PDT 24
Finished Jun 22 06:22:25 PM PDT 24
Peak memory 217844 kb
Host smart-50bad1f2-5dc9-4fe0-be52-a428c84c0a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375839236 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1375839236
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.988118581
Short name T440
Test name
Test status
Simulation time 39353311 ps
CPU time 1.93 seconds
Started Jun 22 06:22:22 PM PDT 24
Finished Jun 22 06:22:24 PM PDT 24
Peak memory 219652 kb
Host smart-4a33525f-0b92-4c2d-8080-f28416146e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988118581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.988118581
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.475517593
Short name T601
Test name
Test status
Simulation time 91269925 ps
CPU time 1.34 seconds
Started Jun 22 06:22:21 PM PDT 24
Finished Jun 22 06:22:23 PM PDT 24
Peak memory 217916 kb
Host smart-c884f1f9-60a1-4ea8-ab94-78ed2675246e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475517593 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.475517593
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.4077378994
Short name T136
Test name
Test status
Simulation time 27660046 ps
CPU time 1.37 seconds
Started Jun 22 06:22:26 PM PDT 24
Finished Jun 22 06:22:28 PM PDT 24
Peak memory 229048 kb
Host smart-71fe781b-3a5b-4aa2-80ae-4379b3b919da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077378994 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.4077378994
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3220331661
Short name T379
Test name
Test status
Simulation time 25800693 ps
CPU time 1.22 seconds
Started Jun 22 06:22:25 PM PDT 24
Finished Jun 22 06:22:26 PM PDT 24
Peak memory 219076 kb
Host smart-507e41d8-1a9c-443b-bc56-17e6e944369d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220331661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3220331661
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.555358991
Short name T31
Test name
Test status
Simulation time 50845653 ps
CPU time 1.2 seconds
Started Jun 22 06:22:25 PM PDT 24
Finished Jun 22 06:22:26 PM PDT 24
Peak memory 218896 kb
Host smart-a7678079-41be-48c0-bbae-6c98e9a11353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555358991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.555358991
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.1487187207
Short name T700
Test name
Test status
Simulation time 29964020 ps
CPU time 1.35 seconds
Started Jun 22 06:22:22 PM PDT 24
Finished Jun 22 06:22:25 PM PDT 24
Peak memory 219368 kb
Host smart-dfd6ed4b-bdb5-4a72-8abe-4a94281d2a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487187207 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1487187207
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3939991673
Short name T226
Test name
Test status
Simulation time 24996027 ps
CPU time 1.21 seconds
Started Jun 22 06:22:23 PM PDT 24
Finished Jun 22 06:22:25 PM PDT 24
Peak memory 217964 kb
Host smart-601d21d9-2fe7-454c-8b53-6d487087aab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939991673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3939991673
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.109422647
Short name T850
Test name
Test status
Simulation time 26803233 ps
CPU time 1.26 seconds
Started Jun 22 06:22:23 PM PDT 24
Finished Jun 22 06:22:25 PM PDT 24
Peak memory 218064 kb
Host smart-6bab9ac2-de4d-42a8-a367-9467150e924d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109422647 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.109422647
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1035666765
Short name T170
Test name
Test status
Simulation time 64690862 ps
CPU time 0.89 seconds
Started Jun 22 06:22:29 PM PDT 24
Finished Jun 22 06:22:30 PM PDT 24
Peak memory 217588 kb
Host smart-d0b5cb11-a8b4-454e-bf07-7e5c146e279b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035666765 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1035666765
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3789488965
Short name T356
Test name
Test status
Simulation time 42514206 ps
CPU time 1.59 seconds
Started Jun 22 06:22:25 PM PDT 24
Finished Jun 22 06:22:27 PM PDT 24
Peak memory 217928 kb
Host smart-4e4e4fcf-5fe3-41cf-9a8d-9810be632f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789488965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3789488965
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.1813748044
Short name T186
Test name
Test status
Simulation time 22299626 ps
CPU time 1.18 seconds
Started Jun 22 06:22:30 PM PDT 24
Finished Jun 22 06:22:31 PM PDT 24
Peak memory 219152 kb
Host smart-589c14b3-acc2-412b-a6b1-e15b8ebb38b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813748044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.1813748044
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1184031375
Short name T375
Test name
Test status
Simulation time 37301554 ps
CPU time 0.86 seconds
Started Jun 22 06:22:29 PM PDT 24
Finished Jun 22 06:22:31 PM PDT 24
Peak memory 217972 kb
Host smart-2ecb0797-1e2b-4e43-8494-2e01741ede44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184031375 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1184031375
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3336458003
Short name T374
Test name
Test status
Simulation time 111307045 ps
CPU time 1.46 seconds
Started Jun 22 06:22:30 PM PDT 24
Finished Jun 22 06:22:32 PM PDT 24
Peak memory 218848 kb
Host smart-59b49f6f-6d55-4641-9bda-6e4beee68336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336458003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3336458003
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.929561565
Short name T115
Test name
Test status
Simulation time 35767695 ps
CPU time 1.13 seconds
Started Jun 22 06:22:30 PM PDT 24
Finished Jun 22 06:22:31 PM PDT 24
Peak memory 218036 kb
Host smart-3d8a3601-6fc1-4af0-bdb4-8be1df4ed083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929561565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.929561565
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.3458690847
Short name T654
Test name
Test status
Simulation time 52667155 ps
CPU time 1.13 seconds
Started Jun 22 06:22:34 PM PDT 24
Finished Jun 22 06:22:36 PM PDT 24
Peak memory 216948 kb
Host smart-77f6829d-0128-41c2-8b7c-ba7d3ce7181b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458690847 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3458690847
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.594925281
Short name T312
Test name
Test status
Simulation time 70223684 ps
CPU time 1.69 seconds
Started Jun 22 06:22:34 PM PDT 24
Finished Jun 22 06:22:36 PM PDT 24
Peak memory 218060 kb
Host smart-2f54cd11-4313-4d0b-bf8d-7ca5be445b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594925281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.594925281
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.2448534112
Short name T106
Test name
Test status
Simulation time 40516195 ps
CPU time 1.11 seconds
Started Jun 22 06:22:29 PM PDT 24
Finished Jun 22 06:22:31 PM PDT 24
Peak memory 217956 kb
Host smart-54463d90-13c0-4043-84f3-3549dfc479fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448534112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.2448534112
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2209258128
Short name T118
Test name
Test status
Simulation time 60583791 ps
CPU time 1.14 seconds
Started Jun 22 06:22:32 PM PDT 24
Finished Jun 22 06:22:33 PM PDT 24
Peak memory 219760 kb
Host smart-1980402b-7bcd-48f8-923e-af4e58c3af9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209258128 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2209258128
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.80623674
Short name T321
Test name
Test status
Simulation time 73286015 ps
CPU time 2.73 seconds
Started Jun 22 06:22:30 PM PDT 24
Finished Jun 22 06:22:33 PM PDT 24
Peak memory 217904 kb
Host smart-cbde751c-78dc-4601-8e4b-9ba8c94b9150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80623674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.80623674
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.309884747
Short name T647
Test name
Test status
Simulation time 199067498 ps
CPU time 1.18 seconds
Started Jun 22 06:19:47 PM PDT 24
Finished Jun 22 06:19:48 PM PDT 24
Peak memory 219092 kb
Host smart-61c9f77c-c12a-434e-9869-5f894bf60321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309884747 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.309884747
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.338875358
Short name T110
Test name
Test status
Simulation time 16650821 ps
CPU time 0.97 seconds
Started Jun 22 06:19:43 PM PDT 24
Finished Jun 22 06:19:44 PM PDT 24
Peak memory 206124 kb
Host smart-be859c00-d8bb-440b-8f79-936390cce9f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338875358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.338875358
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.4225457860
Short name T172
Test name
Test status
Simulation time 11996584 ps
CPU time 0.91 seconds
Started Jun 22 06:19:42 PM PDT 24
Finished Jun 22 06:19:44 PM PDT 24
Peak memory 215840 kb
Host smart-9b0fe0f1-3dfb-4338-8f3d-ebe0be3519d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225457860 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.4225457860
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1844801188
Short name T777
Test name
Test status
Simulation time 55718544 ps
CPU time 0.99 seconds
Started Jun 22 06:19:46 PM PDT 24
Finished Jun 22 06:19:47 PM PDT 24
Peak memory 219152 kb
Host smart-4b76ff25-986d-491d-9615-9f348e3a7062
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844801188 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1844801188
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3636583531
Short name T882
Test name
Test status
Simulation time 19148287 ps
CPU time 1.13 seconds
Started Jun 22 06:19:46 PM PDT 24
Finished Jun 22 06:19:48 PM PDT 24
Peak memory 223324 kb
Host smart-58ffdba5-571f-47bb-b4c0-22feb655a847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636583531 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3636583531
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3039363590
Short name T373
Test name
Test status
Simulation time 54587644 ps
CPU time 1.31 seconds
Started Jun 22 06:19:43 PM PDT 24
Finished Jun 22 06:19:45 PM PDT 24
Peak memory 218960 kb
Host smart-3f186daa-33ee-4085-8664-7561a2ab25aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039363590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3039363590
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.619937664
Short name T16
Test name
Test status
Simulation time 22121083 ps
CPU time 1.24 seconds
Started Jun 22 06:19:42 PM PDT 24
Finished Jun 22 06:19:44 PM PDT 24
Peak memory 223388 kb
Host smart-b915d090-59b3-4bbc-b123-54478467cb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619937664 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.619937664
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.1513784857
Short name T402
Test name
Test status
Simulation time 16749209 ps
CPU time 1.04 seconds
Started Jun 22 06:19:46 PM PDT 24
Finished Jun 22 06:19:48 PM PDT 24
Peak memory 206420 kb
Host smart-1ecbd0f3-418c-4c0e-b5bd-a20c34867a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513784857 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1513784857
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2361931420
Short name T634
Test name
Test status
Simulation time 37989889 ps
CPU time 0.98 seconds
Started Jun 22 06:19:44 PM PDT 24
Finished Jun 22 06:19:45 PM PDT 24
Peak memory 214620 kb
Host smart-ad0ed6d5-ada8-42a5-ae1b-e760915b6705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361931420 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2361931420
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.656363788
Short name T411
Test name
Test status
Simulation time 559707410 ps
CPU time 3.38 seconds
Started Jun 22 06:19:44 PM PDT 24
Finished Jun 22 06:19:48 PM PDT 24
Peak memory 216720 kb
Host smart-1518c2ee-b15d-44a6-bdfb-53347bc3a156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656363788 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.656363788
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2371383389
Short name T971
Test name
Test status
Simulation time 56976810418 ps
CPU time 1250.43 seconds
Started Jun 22 06:19:47 PM PDT 24
Finished Jun 22 06:40:38 PM PDT 24
Peak memory 222952 kb
Host smart-548c798c-9831-46af-9fee-dc42509b4b53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371383389 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2371383389
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.1962931375
Short name T959
Test name
Test status
Simulation time 26392715 ps
CPU time 1.21 seconds
Started Jun 22 06:22:34 PM PDT 24
Finished Jun 22 06:22:35 PM PDT 24
Peak memory 218784 kb
Host smart-e3a08cdb-7748-40e7-925a-29a3cf71e806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962931375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.1962931375
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.2894648023
Short name T676
Test name
Test status
Simulation time 29344291 ps
CPU time 1.02 seconds
Started Jun 22 06:22:32 PM PDT 24
Finished Jun 22 06:22:33 PM PDT 24
Peak memory 223508 kb
Host smart-3c7a3bc6-8cc5-4b5d-9e4f-9a3b5a9a9c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894648023 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2894648023
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3371509398
Short name T416
Test name
Test status
Simulation time 285117497 ps
CPU time 1.37 seconds
Started Jun 22 06:22:32 PM PDT 24
Finished Jun 22 06:22:34 PM PDT 24
Peak memory 217936 kb
Host smart-ea4fb120-d079-4eea-890c-df6ff72d91b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371509398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3371509398
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.1742377833
Short name T174
Test name
Test status
Simulation time 97522682 ps
CPU time 1.26 seconds
Started Jun 22 06:22:33 PM PDT 24
Finished Jun 22 06:22:34 PM PDT 24
Peak memory 215084 kb
Host smart-eb596635-45c6-431d-88ff-86e45394b004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742377833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.1742377833
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.618978788
Short name T680
Test name
Test status
Simulation time 24526511 ps
CPU time 1.27 seconds
Started Jun 22 06:22:31 PM PDT 24
Finished Jun 22 06:22:33 PM PDT 24
Peak memory 220244 kb
Host smart-3a90f90c-5fe1-4d54-be38-0ed4fbec6a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618978788 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.618978788
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2604664943
Short name T314
Test name
Test status
Simulation time 40914999 ps
CPU time 1.61 seconds
Started Jun 22 06:22:30 PM PDT 24
Finished Jun 22 06:22:32 PM PDT 24
Peak memory 218152 kb
Host smart-3df7c256-b482-4dee-805d-8340fc6b3fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604664943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2604664943
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.2508581711
Short name T843
Test name
Test status
Simulation time 47766365 ps
CPU time 1.25 seconds
Started Jun 22 06:22:38 PM PDT 24
Finished Jun 22 06:22:40 PM PDT 24
Peak memory 219668 kb
Host smart-ff1ff18d-bf25-4c0b-b120-695f1cee7e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508581711 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.2508581711
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3748497728
Short name T166
Test name
Test status
Simulation time 19561415 ps
CPU time 0.98 seconds
Started Jun 22 06:22:37 PM PDT 24
Finished Jun 22 06:22:39 PM PDT 24
Peak memory 217772 kb
Host smart-11bd49df-6bd7-4b97-b347-38fbc3dbab76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748497728 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3748497728
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.598881152
Short name T618
Test name
Test status
Simulation time 70944141 ps
CPU time 2.7 seconds
Started Jun 22 06:22:36 PM PDT 24
Finished Jun 22 06:22:40 PM PDT 24
Peak memory 214644 kb
Host smart-9cb5d7c7-aeb8-4b86-9e8f-b76c629dba41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598881152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.598881152
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.1376983942
Short name T470
Test name
Test status
Simulation time 52840592 ps
CPU time 1.16 seconds
Started Jun 22 06:22:36 PM PDT 24
Finished Jun 22 06:22:39 PM PDT 24
Peak memory 217996 kb
Host smart-110ac1cc-d9a7-4718-86bf-b9f9d2b37e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376983942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.1376983942
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.2779493751
Short name T161
Test name
Test status
Simulation time 19779573 ps
CPU time 1.06 seconds
Started Jun 22 06:22:42 PM PDT 24
Finished Jun 22 06:22:44 PM PDT 24
Peak memory 217688 kb
Host smart-82111021-6fa9-47c3-905b-f3051310fa48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779493751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2779493751
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2399322935
Short name T938
Test name
Test status
Simulation time 48503888 ps
CPU time 1.36 seconds
Started Jun 22 06:22:37 PM PDT 24
Finished Jun 22 06:22:39 PM PDT 24
Peak memory 219292 kb
Host smart-70ef4ef0-ef02-4092-a782-a7d7766800e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399322935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2399322935
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.191835583
Short name T756
Test name
Test status
Simulation time 201119671 ps
CPU time 1.2 seconds
Started Jun 22 06:22:36 PM PDT 24
Finished Jun 22 06:22:39 PM PDT 24
Peak memory 219436 kb
Host smart-1ae3f6ad-0d41-4692-b91d-9f2d59865309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191835583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.191835583
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2855538699
Short name T485
Test name
Test status
Simulation time 74764714 ps
CPU time 1.12 seconds
Started Jun 22 06:22:35 PM PDT 24
Finished Jun 22 06:22:37 PM PDT 24
Peak memory 219112 kb
Host smart-baecc8c8-f1b6-4978-9dee-779170ec8a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855538699 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2855538699
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1694463355
Short name T693
Test name
Test status
Simulation time 116701587 ps
CPU time 1.45 seconds
Started Jun 22 06:22:37 PM PDT 24
Finished Jun 22 06:22:40 PM PDT 24
Peak memory 219228 kb
Host smart-b4b292ae-3a14-4f77-b806-83b17eeb9c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694463355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1694463355
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.511757069
Short name T600
Test name
Test status
Simulation time 78550531 ps
CPU time 1.18 seconds
Started Jun 22 06:22:38 PM PDT 24
Finished Jun 22 06:22:41 PM PDT 24
Peak memory 220004 kb
Host smart-4bb5e317-c937-42fd-8053-464ddadf3228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511757069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.511757069
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.104479881
Short name T119
Test name
Test status
Simulation time 20384565 ps
CPU time 1.15 seconds
Started Jun 22 06:22:39 PM PDT 24
Finished Jun 22 06:22:41 PM PDT 24
Peak memory 219084 kb
Host smart-39e203f0-f1a3-4fc4-9aaf-3af527f1f495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104479881 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.104479881
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.4204685547
Short name T44
Test name
Test status
Simulation time 55793179 ps
CPU time 1.22 seconds
Started Jun 22 06:22:36 PM PDT 24
Finished Jun 22 06:22:39 PM PDT 24
Peak memory 216672 kb
Host smart-a55b876a-1a70-4972-b179-db147ab0196f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204685547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.4204685547
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.535435032
Short name T922
Test name
Test status
Simulation time 45880897 ps
CPU time 1.12 seconds
Started Jun 22 06:22:37 PM PDT 24
Finished Jun 22 06:22:39 PM PDT 24
Peak memory 217956 kb
Host smart-e00bfe21-ca4e-411b-881c-787363c413c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535435032 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.535435032
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.3845149367
Short name T204
Test name
Test status
Simulation time 76238112 ps
CPU time 1.12 seconds
Started Jun 22 06:22:40 PM PDT 24
Finished Jun 22 06:22:42 PM PDT 24
Peak memory 219136 kb
Host smart-dae827df-197d-40af-96f0-ecef056279fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845149367 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3845149367
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.23617899
Short name T320
Test name
Test status
Simulation time 64816657 ps
CPU time 1.27 seconds
Started Jun 22 06:22:38 PM PDT 24
Finished Jun 22 06:22:40 PM PDT 24
Peak memory 218208 kb
Host smart-88777d69-a98c-437a-91ff-b29fe3df6844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23617899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.23617899
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.854314213
Short name T167
Test name
Test status
Simulation time 46012653 ps
CPU time 1.22 seconds
Started Jun 22 06:22:37 PM PDT 24
Finished Jun 22 06:22:40 PM PDT 24
Peak memory 215092 kb
Host smart-80ce485c-c240-4821-b9e2-0fc522088273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854314213 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.854314213
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.2699944866
Short name T533
Test name
Test status
Simulation time 44497737 ps
CPU time 1.17 seconds
Started Jun 22 06:22:42 PM PDT 24
Finished Jun 22 06:22:44 PM PDT 24
Peak memory 219044 kb
Host smart-fb07bd8a-77b2-4995-8366-877e09b98d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699944866 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2699944866
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2966895729
Short name T665
Test name
Test status
Simulation time 56448697 ps
CPU time 2.16 seconds
Started Jun 22 06:22:38 PM PDT 24
Finished Jun 22 06:22:41 PM PDT 24
Peak memory 216808 kb
Host smart-d34f5b1a-f75c-4e19-8cd8-bac2a9ac00c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966895729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2966895729
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.790075025
Short name T502
Test name
Test status
Simulation time 40134176 ps
CPU time 1.16 seconds
Started Jun 22 06:22:36 PM PDT 24
Finished Jun 22 06:22:38 PM PDT 24
Peak memory 218196 kb
Host smart-d0efe6d8-d33c-4d8d-9f67-816cb57d8c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790075025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.790075025
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.544590150
Short name T126
Test name
Test status
Simulation time 85262914 ps
CPU time 0.96 seconds
Started Jun 22 06:22:35 PM PDT 24
Finished Jun 22 06:22:36 PM PDT 24
Peak memory 228808 kb
Host smart-9673bae7-0ac8-4899-8dcb-5d8507d2302a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544590150 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.544590150
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1308599574
Short name T386
Test name
Test status
Simulation time 44341095 ps
CPU time 1.78 seconds
Started Jun 22 06:22:34 PM PDT 24
Finished Jun 22 06:22:36 PM PDT 24
Peak memory 216784 kb
Host smart-e0cc3dd6-e9b8-4f00-857b-4a39c967210d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308599574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1308599574
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.511610080
Short name T636
Test name
Test status
Simulation time 49983344 ps
CPU time 1.16 seconds
Started Jun 22 06:22:42 PM PDT 24
Finished Jun 22 06:22:44 PM PDT 24
Peak memory 220136 kb
Host smart-488a7645-a1aa-48b6-9c01-fee8a18bd27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511610080 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.511610080
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.127066065
Short name T137
Test name
Test status
Simulation time 59150148 ps
CPU time 1.11 seconds
Started Jun 22 06:22:36 PM PDT 24
Finished Jun 22 06:22:38 PM PDT 24
Peak memory 229132 kb
Host smart-4b186693-32fe-424d-aa3a-a910cafb22f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127066065 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.127066065
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.690204535
Short name T828
Test name
Test status
Simulation time 162520251 ps
CPU time 3.68 seconds
Started Jun 22 06:22:36 PM PDT 24
Finished Jun 22 06:22:41 PM PDT 24
Peak memory 219616 kb
Host smart-d65d877b-6919-4175-935e-a380ffaef3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690204535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.690204535
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2003158600
Short name T243
Test name
Test status
Simulation time 27416763 ps
CPU time 1.3 seconds
Started Jun 22 06:19:50 PM PDT 24
Finished Jun 22 06:19:52 PM PDT 24
Peak memory 217900 kb
Host smart-9bb46f84-7a37-480d-b10c-475f1db2144b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003158600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2003158600
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.888181590
Short name T985
Test name
Test status
Simulation time 15521210 ps
CPU time 0.95 seconds
Started Jun 22 06:19:50 PM PDT 24
Finished Jun 22 06:19:52 PM PDT 24
Peak memory 206128 kb
Host smart-9a0da018-4af8-4289-994c-7d844ee6c41f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888181590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.888181590
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.244304898
Short name T963
Test name
Test status
Simulation time 27997040 ps
CPU time 0.84 seconds
Started Jun 22 06:19:51 PM PDT 24
Finished Jun 22 06:19:53 PM PDT 24
Peak memory 214840 kb
Host smart-ee793044-57f9-43fc-9a5e-1f1c66b6760d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244304898 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.244304898
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.556561430
Short name T957
Test name
Test status
Simulation time 76948141 ps
CPU time 1.04 seconds
Started Jun 22 06:19:50 PM PDT 24
Finished Jun 22 06:19:52 PM PDT 24
Peak memory 219032 kb
Host smart-cf9017b0-57c8-4e97-911b-919f86134ca2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556561430 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.556561430
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2422864537
Short name T443
Test name
Test status
Simulation time 18482327 ps
CPU time 1.14 seconds
Started Jun 22 06:19:51 PM PDT 24
Finished Jun 22 06:19:52 PM PDT 24
Peak memory 232208 kb
Host smart-5057bf89-0a4f-4b51-8463-0df4a33464fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422864537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2422864537
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1544946139
Short name T916
Test name
Test status
Simulation time 44021522 ps
CPU time 1.47 seconds
Started Jun 22 06:19:43 PM PDT 24
Finished Jun 22 06:19:45 PM PDT 24
Peak memory 217768 kb
Host smart-74401caa-91c4-46d4-88dd-02e5f1ca2bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544946139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1544946139
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.964354772
Short name T33
Test name
Test status
Simulation time 35117780 ps
CPU time 0.85 seconds
Started Jun 22 06:19:50 PM PDT 24
Finished Jun 22 06:19:51 PM PDT 24
Peak memory 214824 kb
Host smart-93c512f9-9bd6-41f5-bc25-e10e6e8fb2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964354772 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.964354772
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1855393896
Short name T725
Test name
Test status
Simulation time 46344594 ps
CPU time 0.93 seconds
Started Jun 22 06:19:44 PM PDT 24
Finished Jun 22 06:19:45 PM PDT 24
Peak memory 206440 kb
Host smart-a99199ad-85e9-4acc-8aef-729de15e6610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855393896 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1855393896
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3464310577
Short name T585
Test name
Test status
Simulation time 28588379 ps
CPU time 0.95 seconds
Started Jun 22 06:19:43 PM PDT 24
Finished Jun 22 06:19:45 PM PDT 24
Peak memory 214624 kb
Host smart-d048a0a4-0a94-4164-b79a-91b0cd1d958a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464310577 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3464310577
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3987668752
Short name T776
Test name
Test status
Simulation time 27711915469 ps
CPU time 330.03 seconds
Started Jun 22 06:19:48 PM PDT 24
Finished Jun 22 06:25:19 PM PDT 24
Peak memory 219896 kb
Host smart-bc04d174-3c92-4191-acb8-4159008b8f20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987668752 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3987668752
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.3005907251
Short name T215
Test name
Test status
Simulation time 25803754 ps
CPU time 1.3 seconds
Started Jun 22 06:22:37 PM PDT 24
Finished Jun 22 06:22:40 PM PDT 24
Peak memory 218080 kb
Host smart-0692647d-bd4e-4e81-aa3b-13b83e4a2e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005907251 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.3005907251
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.2046046190
Short name T460
Test name
Test status
Simulation time 50979684 ps
CPU time 0.99 seconds
Started Jun 22 06:22:48 PM PDT 24
Finished Jun 22 06:22:50 PM PDT 24
Peak memory 219000 kb
Host smart-607a9a44-3991-4cd1-bd11-41cf8494c1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046046190 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2046046190
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.394160899
Short name T655
Test name
Test status
Simulation time 133817623 ps
CPU time 1.13 seconds
Started Jun 22 06:22:39 PM PDT 24
Finished Jun 22 06:22:41 PM PDT 24
Peak memory 216556 kb
Host smart-0e3e4cae-c14a-41c9-95da-3266b009c736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394160899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.394160899
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1227734504
Short name T96
Test name
Test status
Simulation time 71604835 ps
CPU time 1.19 seconds
Started Jun 22 06:22:39 PM PDT 24
Finished Jun 22 06:22:41 PM PDT 24
Peak memory 219132 kb
Host smart-5ccff868-1c4d-42b9-b2fd-38cd72845f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227734504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1227734504
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.907040844
Short name T121
Test name
Test status
Simulation time 51434599 ps
CPU time 0.98 seconds
Started Jun 22 06:22:36 PM PDT 24
Finished Jun 22 06:22:39 PM PDT 24
Peak memory 219828 kb
Host smart-e45991fc-ddc5-495c-9fdf-befc122575d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907040844 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.907040844
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.4092950494
Short name T538
Test name
Test status
Simulation time 55787952 ps
CPU time 1.36 seconds
Started Jun 22 06:22:36 PM PDT 24
Finished Jun 22 06:22:39 PM PDT 24
Peak memory 218076 kb
Host smart-ab0471df-dcd4-4e5f-b166-77933aa26ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092950494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.4092950494
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.526174485
Short name T839
Test name
Test status
Simulation time 80528770 ps
CPU time 1.2 seconds
Started Jun 22 06:22:48 PM PDT 24
Finished Jun 22 06:22:50 PM PDT 24
Peak memory 218540 kb
Host smart-5082109e-9a7e-4015-95e3-aa97701b569d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526174485 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.526174485
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.3654466052
Short name T900
Test name
Test status
Simulation time 26860620 ps
CPU time 0.91 seconds
Started Jun 22 06:22:47 PM PDT 24
Finished Jun 22 06:22:49 PM PDT 24
Peak memory 217664 kb
Host smart-677ee3ff-523d-4b7a-8b9d-35426e8ed62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654466052 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3654466052
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3300429866
Short name T389
Test name
Test status
Simulation time 58844742 ps
CPU time 1.3 seconds
Started Jun 22 06:22:35 PM PDT 24
Finished Jun 22 06:22:37 PM PDT 24
Peak memory 216980 kb
Host smart-7385207d-da15-41e1-bbb4-f48963dfd326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300429866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3300429866
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.1432517674
Short name T275
Test name
Test status
Simulation time 91117710 ps
CPU time 1.27 seconds
Started Jun 22 06:22:47 PM PDT 24
Finished Jun 22 06:22:48 PM PDT 24
Peak memory 215088 kb
Host smart-893d19c9-c3a4-4429-971c-4aedeab586bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432517674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.1432517674
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.1436018397
Short name T352
Test name
Test status
Simulation time 29878743 ps
CPU time 0.88 seconds
Started Jun 22 06:22:49 PM PDT 24
Finished Jun 22 06:22:50 PM PDT 24
Peak memory 217784 kb
Host smart-ef07f963-6255-44c2-9376-f5128fb10c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436018397 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1436018397
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1408532375
Short name T576
Test name
Test status
Simulation time 25479468 ps
CPU time 1.23 seconds
Started Jun 22 06:22:48 PM PDT 24
Finished Jun 22 06:22:50 PM PDT 24
Peak memory 216700 kb
Host smart-68306103-e07d-4021-9aef-948f2de1ad0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408532375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1408532375
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.1587053295
Short name T216
Test name
Test status
Simulation time 77234876 ps
CPU time 1.16 seconds
Started Jun 22 06:22:49 PM PDT 24
Finished Jun 22 06:22:51 PM PDT 24
Peak memory 219172 kb
Host smart-8e40554b-b3f0-4459-84c6-075d6805d844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587053295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.1587053295
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.40659484
Short name T831
Test name
Test status
Simulation time 27091705 ps
CPU time 0.89 seconds
Started Jun 22 06:22:47 PM PDT 24
Finished Jun 22 06:22:49 PM PDT 24
Peak memory 217436 kb
Host smart-73dcd9d6-19f8-4a16-b1eb-52e9c8d3397a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40659484 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.40659484
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1612229460
Short name T766
Test name
Test status
Simulation time 222804146 ps
CPU time 3.69 seconds
Started Jun 22 06:22:48 PM PDT 24
Finished Jun 22 06:22:52 PM PDT 24
Peak memory 217036 kb
Host smart-4a962aac-7331-4cee-b3ce-c7affb62cd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612229460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1612229460
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.3327792479
Short name T633
Test name
Test status
Simulation time 34588626 ps
CPU time 1.2 seconds
Started Jun 22 06:22:47 PM PDT 24
Finished Jun 22 06:22:48 PM PDT 24
Peak memory 219012 kb
Host smart-ecb7eaf4-7f22-4466-ab20-4888e6fc7963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327792479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.3327792479
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.2925579052
Short name T125
Test name
Test status
Simulation time 26112209 ps
CPU time 1.19 seconds
Started Jun 22 06:22:46 PM PDT 24
Finished Jun 22 06:22:48 PM PDT 24
Peak memory 216544 kb
Host smart-a04cce0a-e08d-4b91-bd32-cfdf572a89ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925579052 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2925579052
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2820352292
Short name T884
Test name
Test status
Simulation time 48262304 ps
CPU time 1.32 seconds
Started Jun 22 06:22:46 PM PDT 24
Finished Jun 22 06:22:48 PM PDT 24
Peak memory 216608 kb
Host smart-7fb3c183-2b29-4f31-a443-cf62cf7284a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820352292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2820352292
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.186667014
Short name T552
Test name
Test status
Simulation time 33129139 ps
CPU time 1.19 seconds
Started Jun 22 06:22:57 PM PDT 24
Finished Jun 22 06:22:59 PM PDT 24
Peak memory 219912 kb
Host smart-d2641874-b5d1-465e-a84b-579db774a843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186667014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.186667014
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2026072137
Short name T926
Test name
Test status
Simulation time 31152235 ps
CPU time 1.07 seconds
Started Jun 22 06:22:56 PM PDT 24
Finished Jun 22 06:22:58 PM PDT 24
Peak memory 223188 kb
Host smart-d9e7cd14-c4a4-4a4f-bc00-da1a1f376522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026072137 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2026072137
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.228669377
Short name T413
Test name
Test status
Simulation time 103769466 ps
CPU time 1.17 seconds
Started Jun 22 06:22:55 PM PDT 24
Finished Jun 22 06:22:57 PM PDT 24
Peak memory 218132 kb
Host smart-a5448f05-75b5-491e-ad8c-cf00fad1385a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228669377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.228669377
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.3773182858
Short name T678
Test name
Test status
Simulation time 110861966 ps
CPU time 1.17 seconds
Started Jun 22 06:22:55 PM PDT 24
Finished Jun 22 06:22:57 PM PDT 24
Peak memory 218228 kb
Host smart-011fb402-99ef-42eb-b1a5-cf7d7df2aab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773182858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.3773182858
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.2460060306
Short name T484
Test name
Test status
Simulation time 31289388 ps
CPU time 1.08 seconds
Started Jun 22 06:22:55 PM PDT 24
Finished Jun 22 06:22:57 PM PDT 24
Peak memory 218064 kb
Host smart-f921d399-ca7e-4378-8028-ace560c844bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460060306 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2460060306
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.682287227
Short name T482
Test name
Test status
Simulation time 82632449 ps
CPU time 1.13 seconds
Started Jun 22 06:22:58 PM PDT 24
Finished Jun 22 06:23:00 PM PDT 24
Peak memory 216632 kb
Host smart-f85d0dd5-3383-458e-8ac9-f804b436818b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682287227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.682287227
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.571945735
Short name T625
Test name
Test status
Simulation time 25785269 ps
CPU time 1.19 seconds
Started Jun 22 06:22:55 PM PDT 24
Finished Jun 22 06:22:57 PM PDT 24
Peak memory 220280 kb
Host smart-8099c5f4-bcd6-4aee-b35f-0291c3082cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571945735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.571945735
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.3167691607
Short name T946
Test name
Test status
Simulation time 19381657 ps
CPU time 1.04 seconds
Started Jun 22 06:22:56 PM PDT 24
Finished Jun 22 06:22:58 PM PDT 24
Peak memory 217524 kb
Host smart-a65b25dc-8b31-48ea-b429-f3fe0a1bd720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167691607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3167691607
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2428432530
Short name T707
Test name
Test status
Simulation time 62696306 ps
CPU time 1.34 seconds
Started Jun 22 06:22:55 PM PDT 24
Finished Jun 22 06:22:57 PM PDT 24
Peak memory 216488 kb
Host smart-6e2559f5-10bd-471e-950a-673c24300e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428432530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2428432530
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.3514706506
Short name T642
Test name
Test status
Simulation time 30576502 ps
CPU time 1.36 seconds
Started Jun 22 06:22:54 PM PDT 24
Finished Jun 22 06:22:55 PM PDT 24
Peak memory 215072 kb
Host smart-5dabe5d2-bcfe-4cff-8955-e7e4e96ce63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514706506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.3514706506
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.3502763473
Short name T56
Test name
Test status
Simulation time 20375354 ps
CPU time 1.27 seconds
Started Jun 22 06:22:55 PM PDT 24
Finished Jun 22 06:22:57 PM PDT 24
Peak memory 228984 kb
Host smart-01cd4ba3-49f1-4177-bac3-538cb8e1f5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502763473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3502763473
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3944984221
Short name T395
Test name
Test status
Simulation time 32411836 ps
CPU time 1.27 seconds
Started Jun 22 06:22:54 PM PDT 24
Finished Jun 22 06:22:56 PM PDT 24
Peak memory 216812 kb
Host smart-23e81e31-c770-4681-948d-81ef9987cb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944984221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3944984221
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1979152133
Short name T429
Test name
Test status
Simulation time 29025690 ps
CPU time 1.28 seconds
Started Jun 22 06:19:50 PM PDT 24
Finished Jun 22 06:19:52 PM PDT 24
Peak memory 217916 kb
Host smart-cc61e517-f911-4745-adf2-0c6a3f64a622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979152133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1979152133
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1813417449
Short name T813
Test name
Test status
Simulation time 49121998 ps
CPU time 0.87 seconds
Started Jun 22 06:19:57 PM PDT 24
Finished Jun 22 06:19:59 PM PDT 24
Peak memory 205924 kb
Host smart-77ed1291-b8b2-4d23-8bd2-b7438dc70e03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813417449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1813417449
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3902869632
Short name T212
Test name
Test status
Simulation time 33610143 ps
CPU time 0.87 seconds
Started Jun 22 06:19:49 PM PDT 24
Finished Jun 22 06:19:50 PM PDT 24
Peak memory 215684 kb
Host smart-a5b9b9b8-a864-4039-b301-f1d949dd73cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902869632 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3902869632
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.2629538658
Short name T139
Test name
Test status
Simulation time 133589315 ps
CPU time 1.25 seconds
Started Jun 22 06:19:57 PM PDT 24
Finished Jun 22 06:19:59 PM PDT 24
Peak memory 218852 kb
Host smart-6e7fc426-d3a7-47bd-a2b1-8221d697e19f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629538658 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.2629538658
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1422547295
Short name T837
Test name
Test status
Simulation time 24829727 ps
CPU time 1.17 seconds
Started Jun 22 06:19:51 PM PDT 24
Finished Jun 22 06:19:52 PM PDT 24
Peak memory 218148 kb
Host smart-6eaacb7f-4ac5-422e-a58c-1cb0a7f84979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422547295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1422547295
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.107421323
Short name T319
Test name
Test status
Simulation time 99625163 ps
CPU time 1.26 seconds
Started Jun 22 06:19:50 PM PDT 24
Finished Jun 22 06:19:52 PM PDT 24
Peak memory 219404 kb
Host smart-453f3efe-82f2-4e9b-b9c6-f507b25523c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107421323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.107421323
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2766099490
Short name T100
Test name
Test status
Simulation time 32153765 ps
CPU time 0.94 seconds
Started Jun 22 06:19:49 PM PDT 24
Finished Jun 22 06:19:51 PM PDT 24
Peak memory 214888 kb
Host smart-8cb0aa18-8eae-4b8e-bc3d-2e801f3dcd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766099490 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2766099490
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2841786297
Short name T858
Test name
Test status
Simulation time 15202438 ps
CPU time 0.96 seconds
Started Jun 22 06:19:51 PM PDT 24
Finished Jun 22 06:19:52 PM PDT 24
Peak memory 206444 kb
Host smart-1bc80f10-01c3-480e-9a88-bd3d77a9a635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841786297 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2841786297
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.4172665840
Short name T554
Test name
Test status
Simulation time 90156533 ps
CPU time 0.95 seconds
Started Jun 22 06:19:50 PM PDT 24
Finished Jun 22 06:19:51 PM PDT 24
Peak memory 214628 kb
Host smart-1d85fabb-c2ca-47fa-a171-39debc2111f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172665840 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.4172665840
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2156508352
Short name T958
Test name
Test status
Simulation time 84807800 ps
CPU time 1.1 seconds
Started Jun 22 06:19:51 PM PDT 24
Finished Jun 22 06:19:52 PM PDT 24
Peak memory 206384 kb
Host smart-0037a11e-d5e7-401e-827f-0d4ee04b6a49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156508352 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2156508352
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.202836804
Short name T40
Test name
Test status
Simulation time 68840913887 ps
CPU time 1450.79 seconds
Started Jun 22 06:19:51 PM PDT 24
Finished Jun 22 06:44:02 PM PDT 24
Peak memory 223760 kb
Host smart-a4b7a063-464d-40b8-bc48-d8d8f400cf2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202836804 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.202836804
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.1832727259
Short name T59
Test name
Test status
Simulation time 70704095 ps
CPU time 1.15 seconds
Started Jun 22 06:22:56 PM PDT 24
Finished Jun 22 06:22:59 PM PDT 24
Peak memory 219180 kb
Host smart-5b7b7db4-f605-468a-8af7-ee5af6fb5f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832727259 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.1832727259
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.3645872168
Short name T488
Test name
Test status
Simulation time 23680738 ps
CPU time 1.3 seconds
Started Jun 22 06:22:54 PM PDT 24
Finished Jun 22 06:22:56 PM PDT 24
Peak memory 223360 kb
Host smart-36a31ac5-8aa1-4a51-8978-d3ea196fbe6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645872168 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3645872168
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.4214587816
Short name T332
Test name
Test status
Simulation time 69947466 ps
CPU time 1.13 seconds
Started Jun 22 06:22:56 PM PDT 24
Finished Jun 22 06:22:58 PM PDT 24
Peak memory 216444 kb
Host smart-fb755847-d75f-41f2-91b0-59013cb1b482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214587816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.4214587816
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.3521994644
Short name T108
Test name
Test status
Simulation time 31515615 ps
CPU time 1.29 seconds
Started Jun 22 06:22:56 PM PDT 24
Finished Jun 22 06:22:59 PM PDT 24
Peak memory 218956 kb
Host smart-5fbe2430-5c6a-4b1a-9836-0023301d2f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521994644 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.3521994644
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.1187959417
Short name T51
Test name
Test status
Simulation time 25240496 ps
CPU time 1.32 seconds
Started Jun 22 06:22:55 PM PDT 24
Finished Jun 22 06:22:57 PM PDT 24
Peak memory 231604 kb
Host smart-088a3854-73f9-4b3d-901a-06c1793cdb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187959417 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1187959417
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2985778227
Short name T608
Test name
Test status
Simulation time 135301292 ps
CPU time 1.12 seconds
Started Jun 22 06:22:55 PM PDT 24
Finished Jun 22 06:22:57 PM PDT 24
Peak memory 216584 kb
Host smart-c9e6ca73-398b-409c-9aa5-789c11938fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985778227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2985778227
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.2147841565
Short name T130
Test name
Test status
Simulation time 102163819 ps
CPU time 1.32 seconds
Started Jun 22 06:22:55 PM PDT 24
Finished Jun 22 06:22:58 PM PDT 24
Peak memory 219100 kb
Host smart-dc92814f-0af7-4a3f-9e34-03cec65b8e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147841565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.2147841565
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.2001385363
Short name T390
Test name
Test status
Simulation time 35765657 ps
CPU time 0.9 seconds
Started Jun 22 06:22:55 PM PDT 24
Finished Jun 22 06:22:57 PM PDT 24
Peak memory 218784 kb
Host smart-0654380b-072f-445b-8f4e-716621ab1069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001385363 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2001385363
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1429396432
Short name T859
Test name
Test status
Simulation time 33163592 ps
CPU time 1.44 seconds
Started Jun 22 06:22:55 PM PDT 24
Finished Jun 22 06:22:57 PM PDT 24
Peak memory 217864 kb
Host smart-db09f008-18e8-4abc-a97a-656331aa0a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429396432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1429396432
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.2629998084
Short name T195
Test name
Test status
Simulation time 30096357 ps
CPU time 1.3 seconds
Started Jun 22 06:22:55 PM PDT 24
Finished Jun 22 06:22:57 PM PDT 24
Peak memory 219320 kb
Host smart-9c7098cb-acc6-4e93-9ebe-15584aa0bec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629998084 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2629998084
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.446587601
Short name T392
Test name
Test status
Simulation time 88156232 ps
CPU time 1.37 seconds
Started Jun 22 06:22:59 PM PDT 24
Finished Jun 22 06:23:01 PM PDT 24
Peak memory 219288 kb
Host smart-b6f3d45a-a0ef-4fbe-a4c6-2ed605b7fd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446587601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.446587601
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1921169519
Short name T771
Test name
Test status
Simulation time 70175235 ps
CPU time 1.16 seconds
Started Jun 22 06:22:56 PM PDT 24
Finished Jun 22 06:22:59 PM PDT 24
Peak memory 219184 kb
Host smart-a5d486ef-d4bd-4f67-abd1-c9b07fb3a1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921169519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1921169519
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1827657794
Short name T113
Test name
Test status
Simulation time 67342544 ps
CPU time 0.94 seconds
Started Jun 22 06:22:57 PM PDT 24
Finished Jun 22 06:22:59 PM PDT 24
Peak memory 219280 kb
Host smart-a660f78a-553c-4592-b954-0b2a65f112e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827657794 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1827657794
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2029871569
Short name T870
Test name
Test status
Simulation time 71657491 ps
CPU time 1.28 seconds
Started Jun 22 06:22:54 PM PDT 24
Finished Jun 22 06:22:56 PM PDT 24
Peak memory 218220 kb
Host smart-458cbf05-5d58-42f2-9816-bb1a8d32840b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029871569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2029871569
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.13897031
Short name T129
Test name
Test status
Simulation time 43742449 ps
CPU time 1.22 seconds
Started Jun 22 06:22:58 PM PDT 24
Finished Jun 22 06:23:00 PM PDT 24
Peak memory 218384 kb
Host smart-0dc6ebf6-f28b-4265-a9f5-80305e7803e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13897031 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.13897031
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1941726132
Short name T537
Test name
Test status
Simulation time 78351572 ps
CPU time 1 seconds
Started Jun 22 06:22:57 PM PDT 24
Finished Jun 22 06:22:59 PM PDT 24
Peak memory 217728 kb
Host smart-ecac9cf5-4ef7-45c5-8668-d4585ffaf124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941726132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1941726132
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1241043505
Short name T698
Test name
Test status
Simulation time 77968417 ps
CPU time 1.48 seconds
Started Jun 22 06:22:56 PM PDT 24
Finished Jun 22 06:22:59 PM PDT 24
Peak memory 219452 kb
Host smart-281bf548-2082-4efd-8037-958b15879d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241043505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1241043505
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1767757177
Short name T188
Test name
Test status
Simulation time 99877707 ps
CPU time 1.16 seconds
Started Jun 22 06:22:54 PM PDT 24
Finished Jun 22 06:22:55 PM PDT 24
Peak memory 219628 kb
Host smart-0dab34f6-5578-4e14-8921-7f1763e8bdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767757177 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1767757177
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.1001518898
Short name T915
Test name
Test status
Simulation time 24277351 ps
CPU time 1.19 seconds
Started Jun 22 06:22:58 PM PDT 24
Finished Jun 22 06:23:00 PM PDT 24
Peak memory 219240 kb
Host smart-726349ff-7919-4be7-b638-57a8652e928b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001518898 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1001518898
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/97.edn_alert.1397138194
Short name T841
Test name
Test status
Simulation time 85790981 ps
CPU time 1.24 seconds
Started Jun 22 06:22:57 PM PDT 24
Finished Jun 22 06:22:59 PM PDT 24
Peak memory 218068 kb
Host smart-18724937-eff1-48aa-9403-e6b1882e6ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397138194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.1397138194
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.1389035755
Short name T954
Test name
Test status
Simulation time 23809241 ps
CPU time 1.02 seconds
Started Jun 22 06:22:55 PM PDT 24
Finished Jun 22 06:22:56 PM PDT 24
Peak memory 217932 kb
Host smart-4ad681e1-ce7e-4d01-96a1-519a38f8a1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389035755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1389035755
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3852869489
Short name T984
Test name
Test status
Simulation time 74860524 ps
CPU time 2.71 seconds
Started Jun 22 06:22:54 PM PDT 24
Finished Jun 22 06:22:57 PM PDT 24
Peak memory 218404 kb
Host smart-0de33c7f-34be-4fe8-a5ca-ea02f82794e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852869489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3852869489
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.3718716971
Short name T116
Test name
Test status
Simulation time 53252410 ps
CPU time 1.33 seconds
Started Jun 22 06:22:55 PM PDT 24
Finished Jun 22 06:22:57 PM PDT 24
Peak memory 215296 kb
Host smart-14f3c3d1-d965-4aeb-a1ce-b0e39c24606d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718716971 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.3718716971
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.2173118603
Short name T940
Test name
Test status
Simulation time 30909319 ps
CPU time 0.94 seconds
Started Jun 22 06:22:56 PM PDT 24
Finished Jun 22 06:22:58 PM PDT 24
Peak memory 218052 kb
Host smart-e38e3157-19c7-4b6d-98c8-3e31852fcecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173118603 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2173118603
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2011428642
Short name T973
Test name
Test status
Simulation time 60596211 ps
CPU time 1.35 seconds
Started Jun 22 06:22:56 PM PDT 24
Finished Jun 22 06:22:58 PM PDT 24
Peak memory 216568 kb
Host smart-68b66d96-2937-4148-a30e-911ef589eb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011428642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2011428642
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.2609365394
Short name T548
Test name
Test status
Simulation time 27545763 ps
CPU time 1.2 seconds
Started Jun 22 06:22:56 PM PDT 24
Finished Jun 22 06:22:59 PM PDT 24
Peak memory 219124 kb
Host smart-7fe481d3-e4f7-45bd-a239-a0d0c4597b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609365394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.2609365394
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.1417198258
Short name T177
Test name
Test status
Simulation time 31968814 ps
CPU time 1.04 seconds
Started Jun 22 06:23:02 PM PDT 24
Finished Jun 22 06:23:04 PM PDT 24
Peak memory 223208 kb
Host smart-ecab5999-ee62-46e2-880a-6ea4aac79e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417198258 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1417198258
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3698177101
Short name T318
Test name
Test status
Simulation time 49474236 ps
CPU time 1.69 seconds
Started Jun 22 06:22:55 PM PDT 24
Finished Jun 22 06:22:57 PM PDT 24
Peak memory 217876 kb
Host smart-b3efef67-483e-4bc1-90d6-c0a07dc4334d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698177101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3698177101
Directory /workspace/99.edn_genbits/latest
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