Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.53 98.25 93.91 97.02 91.28 96.37 99.77 92.08


Total test records in report: 1130
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T273 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2286079926 Jun 23 05:49:25 PM PDT 24 Jun 23 05:49:26 PM PDT 24 42676833 ps
T259 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1348417505 Jun 23 05:49:21 PM PDT 24 Jun 23 05:49:22 PM PDT 24 39863929 ps
T289 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.4195854750 Jun 23 05:49:24 PM PDT 24 Jun 23 05:49:26 PM PDT 24 90242976 ps
T1021 /workspace/coverage/cover_reg_top/10.edn_intr_test.1024345572 Jun 23 05:49:14 PM PDT 24 Jun 23 05:49:15 PM PDT 24 12002896 ps
T1022 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2575534541 Jun 23 05:49:05 PM PDT 24 Jun 23 05:49:06 PM PDT 24 49078187 ps
T1023 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3097445878 Jun 23 05:49:09 PM PDT 24 Jun 23 05:49:10 PM PDT 24 54188848 ps
T274 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3343983203 Jun 23 05:49:08 PM PDT 24 Jun 23 05:49:10 PM PDT 24 118332203 ps
T260 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2087497695 Jun 23 05:49:06 PM PDT 24 Jun 23 05:49:07 PM PDT 24 28242153 ps
T1024 /workspace/coverage/cover_reg_top/25.edn_intr_test.1196028638 Jun 23 05:49:28 PM PDT 24 Jun 23 05:49:29 PM PDT 24 20073822 ps
T275 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2639867821 Jun 23 05:49:11 PM PDT 24 Jun 23 05:49:13 PM PDT 24 23894611 ps
T1025 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1091943097 Jun 23 05:49:03 PM PDT 24 Jun 23 05:49:08 PM PDT 24 940963681 ps
T1026 /workspace/coverage/cover_reg_top/4.edn_intr_test.2917417028 Jun 23 05:49:09 PM PDT 24 Jun 23 05:49:11 PM PDT 24 13227376 ps
T261 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2118477877 Jun 23 05:49:05 PM PDT 24 Jun 23 05:49:07 PM PDT 24 22275090 ps
T1027 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3568114172 Jun 23 05:49:04 PM PDT 24 Jun 23 05:49:05 PM PDT 24 78412038 ps
T1028 /workspace/coverage/cover_reg_top/7.edn_intr_test.4213183015 Jun 23 05:49:14 PM PDT 24 Jun 23 05:49:16 PM PDT 24 49305450 ps
T1029 /workspace/coverage/cover_reg_top/14.edn_intr_test.986008713 Jun 23 05:49:25 PM PDT 24 Jun 23 05:49:26 PM PDT 24 15626941 ps
T1030 /workspace/coverage/cover_reg_top/8.edn_intr_test.2855495283 Jun 23 05:49:12 PM PDT 24 Jun 23 05:49:13 PM PDT 24 13956090 ps
T1031 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3697941287 Jun 23 05:49:11 PM PDT 24 Jun 23 05:49:14 PM PDT 24 223525496 ps
T1032 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1008436097 Jun 23 05:49:24 PM PDT 24 Jun 23 05:49:26 PM PDT 24 61378084 ps
T1033 /workspace/coverage/cover_reg_top/12.edn_intr_test.1222766511 Jun 23 05:49:19 PM PDT 24 Jun 23 05:49:20 PM PDT 24 108636785 ps
T276 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3106148747 Jun 23 05:49:06 PM PDT 24 Jun 23 05:49:08 PM PDT 24 130841391 ps
T1034 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2131388585 Jun 23 05:49:09 PM PDT 24 Jun 23 05:49:11 PM PDT 24 35712007 ps
T1035 /workspace/coverage/cover_reg_top/48.edn_intr_test.522373894 Jun 23 05:49:31 PM PDT 24 Jun 23 05:49:32 PM PDT 24 14568325 ps
T1036 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3228562337 Jun 23 05:49:02 PM PDT 24 Jun 23 05:49:03 PM PDT 24 23576233 ps
T1037 /workspace/coverage/cover_reg_top/14.edn_tl_errors.4010994476 Jun 23 05:49:24 PM PDT 24 Jun 23 05:49:27 PM PDT 24 60743081 ps
T1038 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3626604915 Jun 23 05:49:19 PM PDT 24 Jun 23 05:49:22 PM PDT 24 173494111 ps
T1039 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1496290739 Jun 23 05:49:14 PM PDT 24 Jun 23 05:49:15 PM PDT 24 19649106 ps
T1040 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2066819222 Jun 23 05:49:08 PM PDT 24 Jun 23 05:49:10 PM PDT 24 42468365 ps
T1041 /workspace/coverage/cover_reg_top/18.edn_intr_test.737351586 Jun 23 05:49:23 PM PDT 24 Jun 23 05:49:24 PM PDT 24 21587528 ps
T1042 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3387500177 Jun 23 05:49:03 PM PDT 24 Jun 23 05:49:05 PM PDT 24 42727613 ps
T1043 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1259800501 Jun 23 05:49:05 PM PDT 24 Jun 23 05:49:09 PM PDT 24 126115303 ps
T1044 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3241785883 Jun 23 05:49:13 PM PDT 24 Jun 23 05:49:15 PM PDT 24 31540060 ps
T1045 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1636414729 Jun 23 05:49:21 PM PDT 24 Jun 23 05:49:23 PM PDT 24 44875408 ps
T1046 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4013876672 Jun 23 05:49:26 PM PDT 24 Jun 23 05:49:28 PM PDT 24 69052376 ps
T1047 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2249916169 Jun 23 05:49:18 PM PDT 24 Jun 23 05:49:19 PM PDT 24 36846860 ps
T1048 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.934427855 Jun 23 05:49:06 PM PDT 24 Jun 23 05:49:08 PM PDT 24 25064351 ps
T286 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3531132361 Jun 23 05:49:10 PM PDT 24 Jun 23 05:49:12 PM PDT 24 47655361 ps
T262 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.98045761 Jun 23 05:49:05 PM PDT 24 Jun 23 05:49:08 PM PDT 24 129402351 ps
T287 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.675769726 Jun 23 05:49:08 PM PDT 24 Jun 23 05:49:11 PM PDT 24 131640495 ps
T263 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2794376351 Jun 23 05:49:12 PM PDT 24 Jun 23 05:49:13 PM PDT 24 14856958 ps
T1049 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1314043066 Jun 23 05:49:21 PM PDT 24 Jun 23 05:49:22 PM PDT 24 117703306 ps
T1050 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.441949939 Jun 23 05:49:21 PM PDT 24 Jun 23 05:49:23 PM PDT 24 80872686 ps
T1051 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.946879681 Jun 23 05:49:03 PM PDT 24 Jun 23 05:49:05 PM PDT 24 238142778 ps
T1052 /workspace/coverage/cover_reg_top/42.edn_intr_test.3916144447 Jun 23 05:49:32 PM PDT 24 Jun 23 05:49:33 PM PDT 24 54254785 ps
T1053 /workspace/coverage/cover_reg_top/44.edn_intr_test.2685359991 Jun 23 05:49:30 PM PDT 24 Jun 23 05:49:31 PM PDT 24 42578138 ps
T1054 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1264772606 Jun 23 05:49:07 PM PDT 24 Jun 23 05:49:08 PM PDT 24 121838870 ps
T1055 /workspace/coverage/cover_reg_top/19.edn_csr_rw.404937820 Jun 23 05:49:23 PM PDT 24 Jun 23 05:49:24 PM PDT 24 97892848 ps
T267 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4194848818 Jun 23 05:49:13 PM PDT 24 Jun 23 05:49:17 PM PDT 24 64040090 ps
T1056 /workspace/coverage/cover_reg_top/28.edn_intr_test.412846583 Jun 23 05:49:29 PM PDT 24 Jun 23 05:49:31 PM PDT 24 48807345 ps
T1057 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1051983443 Jun 23 05:49:24 PM PDT 24 Jun 23 05:49:26 PM PDT 24 63448719 ps
T1058 /workspace/coverage/cover_reg_top/9.edn_intr_test.3747442759 Jun 23 05:49:14 PM PDT 24 Jun 23 05:49:16 PM PDT 24 13501300 ps
T1059 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.867812395 Jun 23 05:49:23 PM PDT 24 Jun 23 05:49:25 PM PDT 24 26254870 ps
T1060 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1954375825 Jun 23 05:49:24 PM PDT 24 Jun 23 05:49:26 PM PDT 24 47831292 ps
T1061 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1204309770 Jun 23 05:49:10 PM PDT 24 Jun 23 05:49:15 PM PDT 24 211916768 ps
T1062 /workspace/coverage/cover_reg_top/47.edn_intr_test.2611238328 Jun 23 05:49:30 PM PDT 24 Jun 23 05:49:31 PM PDT 24 44241504 ps
T1063 /workspace/coverage/cover_reg_top/6.edn_intr_test.3070505798 Jun 23 05:49:11 PM PDT 24 Jun 23 05:49:12 PM PDT 24 15342880 ps
T1064 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3663757086 Jun 23 05:49:14 PM PDT 24 Jun 23 05:49:16 PM PDT 24 20076659 ps
T1065 /workspace/coverage/cover_reg_top/23.edn_intr_test.1284218225 Jun 23 05:49:28 PM PDT 24 Jun 23 05:49:29 PM PDT 24 18663302 ps
T1066 /workspace/coverage/cover_reg_top/31.edn_intr_test.910754410 Jun 23 05:49:30 PM PDT 24 Jun 23 05:49:31 PM PDT 24 26382458 ps
T1067 /workspace/coverage/cover_reg_top/27.edn_intr_test.125267048 Jun 23 05:49:31 PM PDT 24 Jun 23 05:49:33 PM PDT 24 15904083 ps
T1068 /workspace/coverage/cover_reg_top/3.edn_intr_test.196203855 Jun 23 05:49:02 PM PDT 24 Jun 23 05:49:04 PM PDT 24 26524705 ps
T1069 /workspace/coverage/cover_reg_top/40.edn_intr_test.2626382310 Jun 23 05:49:30 PM PDT 24 Jun 23 05:49:32 PM PDT 24 51818585 ps
T264 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2472405577 Jun 23 05:49:14 PM PDT 24 Jun 23 05:49:15 PM PDT 24 19778532 ps
T1070 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1568107962 Jun 23 05:49:07 PM PDT 24 Jun 23 05:49:09 PM PDT 24 239142464 ps
T1071 /workspace/coverage/cover_reg_top/5.edn_intr_test.2131557583 Jun 23 05:49:12 PM PDT 24 Jun 23 05:49:13 PM PDT 24 37224988 ps
T1072 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.266475330 Jun 23 05:49:23 PM PDT 24 Jun 23 05:49:24 PM PDT 24 30582501 ps
T1073 /workspace/coverage/cover_reg_top/15.edn_intr_test.2302123548 Jun 23 05:49:19 PM PDT 24 Jun 23 05:49:21 PM PDT 24 15086621 ps
T1074 /workspace/coverage/cover_reg_top/34.edn_intr_test.3644160220 Jun 23 05:49:28 PM PDT 24 Jun 23 05:49:29 PM PDT 24 16296595 ps
T1075 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.471044666 Jun 23 05:49:18 PM PDT 24 Jun 23 05:49:20 PM PDT 24 643440597 ps
T290 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2153811956 Jun 23 05:49:25 PM PDT 24 Jun 23 05:49:27 PM PDT 24 50493696 ps
T1076 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3138859401 Jun 23 05:49:13 PM PDT 24 Jun 23 05:49:15 PM PDT 24 60184197 ps
T1077 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3539029612 Jun 23 05:49:21 PM PDT 24 Jun 23 05:49:22 PM PDT 24 43018951 ps
T265 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2934330086 Jun 23 05:49:04 PM PDT 24 Jun 23 05:49:05 PM PDT 24 17420437 ps
T1078 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.344819659 Jun 23 05:49:24 PM PDT 24 Jun 23 05:49:26 PM PDT 24 131822685 ps
T1079 /workspace/coverage/cover_reg_top/36.edn_intr_test.3493638126 Jun 23 05:49:36 PM PDT 24 Jun 23 05:49:37 PM PDT 24 52906136 ps
T1080 /workspace/coverage/cover_reg_top/13.edn_tl_errors.100013250 Jun 23 05:49:18 PM PDT 24 Jun 23 05:49:20 PM PDT 24 24325930 ps
T1081 /workspace/coverage/cover_reg_top/18.edn_tl_errors.624282243 Jun 23 05:49:23 PM PDT 24 Jun 23 05:49:26 PM PDT 24 122551788 ps
T266 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1700199442 Jun 23 05:49:16 PM PDT 24 Jun 23 05:49:17 PM PDT 24 13002671 ps
T1082 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1223418509 Jun 23 05:49:23 PM PDT 24 Jun 23 05:49:24 PM PDT 24 49961743 ps
T1083 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1659643883 Jun 23 05:49:10 PM PDT 24 Jun 23 05:49:13 PM PDT 24 65194185 ps
T1084 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3764056542 Jun 23 05:49:12 PM PDT 24 Jun 23 05:49:16 PM PDT 24 92738092 ps
T1085 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1283476871 Jun 23 05:49:09 PM PDT 24 Jun 23 05:49:13 PM PDT 24 557387108 ps
T1086 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.4011156615 Jun 23 05:49:14 PM PDT 24 Jun 23 05:49:17 PM PDT 24 236010172 ps
T1087 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1720075559 Jun 23 05:49:14 PM PDT 24 Jun 23 05:49:15 PM PDT 24 14807443 ps
T1088 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.228631064 Jun 23 05:49:11 PM PDT 24 Jun 23 05:49:13 PM PDT 24 35126339 ps
T1089 /workspace/coverage/cover_reg_top/8.edn_csr_rw.533077255 Jun 23 05:49:12 PM PDT 24 Jun 23 05:49:14 PM PDT 24 63706995 ps
T1090 /workspace/coverage/cover_reg_top/24.edn_intr_test.2257273650 Jun 23 05:49:31 PM PDT 24 Jun 23 05:49:33 PM PDT 24 12376434 ps
T1091 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2585810652 Jun 23 05:49:07 PM PDT 24 Jun 23 05:49:13 PM PDT 24 348683667 ps
T1092 /workspace/coverage/cover_reg_top/37.edn_intr_test.1298369482 Jun 23 05:49:32 PM PDT 24 Jun 23 05:49:33 PM PDT 24 63910169 ps
T1093 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3326493569 Jun 23 05:49:14 PM PDT 24 Jun 23 05:49:17 PM PDT 24 127665716 ps
T1094 /workspace/coverage/cover_reg_top/41.edn_intr_test.820078208 Jun 23 05:49:30 PM PDT 24 Jun 23 05:49:31 PM PDT 24 50024160 ps
T1095 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.629913656 Jun 23 05:49:19 PM PDT 24 Jun 23 05:49:22 PM PDT 24 89057689 ps
T1096 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.436861000 Jun 23 05:49:21 PM PDT 24 Jun 23 05:49:23 PM PDT 24 70776180 ps
T1097 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3218140656 Jun 23 05:49:15 PM PDT 24 Jun 23 05:49:18 PM PDT 24 31431248 ps
T1098 /workspace/coverage/cover_reg_top/22.edn_intr_test.3332544417 Jun 23 05:49:24 PM PDT 24 Jun 23 05:49:25 PM PDT 24 23056027 ps
T1099 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3625578350 Jun 23 05:49:07 PM PDT 24 Jun 23 05:49:11 PM PDT 24 475403122 ps
T1100 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3636350821 Jun 23 05:49:12 PM PDT 24 Jun 23 05:49:14 PM PDT 24 25912913 ps
T1101 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2964291466 Jun 23 05:49:14 PM PDT 24 Jun 23 05:49:15 PM PDT 24 77380278 ps
T1102 /workspace/coverage/cover_reg_top/16.edn_intr_test.791351853 Jun 23 05:49:18 PM PDT 24 Jun 23 05:49:20 PM PDT 24 32392121 ps
T1103 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2914245935 Jun 23 05:49:06 PM PDT 24 Jun 23 05:49:10 PM PDT 24 517954801 ps
T1104 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3537378963 Jun 23 05:49:10 PM PDT 24 Jun 23 05:49:12 PM PDT 24 19792438 ps
T1105 /workspace/coverage/cover_reg_top/29.edn_intr_test.2185754827 Jun 23 05:49:32 PM PDT 24 Jun 23 05:49:34 PM PDT 24 21262843 ps
T1106 /workspace/coverage/cover_reg_top/32.edn_intr_test.2552691030 Jun 23 05:49:30 PM PDT 24 Jun 23 05:49:31 PM PDT 24 65754255 ps
T1107 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2605285933 Jun 23 05:49:14 PM PDT 24 Jun 23 05:49:19 PM PDT 24 181469022 ps
T291 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3639010266 Jun 23 05:49:05 PM PDT 24 Jun 23 05:49:08 PM PDT 24 156365950 ps
T1108 /workspace/coverage/cover_reg_top/26.edn_intr_test.1696112389 Jun 23 05:49:28 PM PDT 24 Jun 23 05:49:29 PM PDT 24 22379357 ps
T268 /workspace/coverage/cover_reg_top/12.edn_csr_rw.3633334043 Jun 23 05:49:25 PM PDT 24 Jun 23 05:49:27 PM PDT 24 17455193 ps
T1109 /workspace/coverage/cover_reg_top/11.edn_intr_test.4259673785 Jun 23 05:49:15 PM PDT 24 Jun 23 05:49:16 PM PDT 24 13199875 ps
T1110 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1858341716 Jun 23 05:49:04 PM PDT 24 Jun 23 05:49:08 PM PDT 24 188103386 ps
T1111 /workspace/coverage/cover_reg_top/35.edn_intr_test.2220562202 Jun 23 05:49:33 PM PDT 24 Jun 23 05:49:34 PM PDT 24 36836558 ps
T1112 /workspace/coverage/cover_reg_top/46.edn_intr_test.2482763730 Jun 23 05:49:31 PM PDT 24 Jun 23 05:49:32 PM PDT 24 17821787 ps
T1113 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.729222591 Jun 23 05:49:13 PM PDT 24 Jun 23 05:49:15 PM PDT 24 37176737 ps
T1114 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1077774387 Jun 23 05:49:13 PM PDT 24 Jun 23 05:49:18 PM PDT 24 112296470 ps
T1115 /workspace/coverage/cover_reg_top/45.edn_intr_test.2047913749 Jun 23 05:49:30 PM PDT 24 Jun 23 05:49:32 PM PDT 24 20348335 ps
T1116 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1281295251 Jun 23 05:49:09 PM PDT 24 Jun 23 05:49:11 PM PDT 24 46262154 ps
T1117 /workspace/coverage/cover_reg_top/17.edn_intr_test.1555130898 Jun 23 05:49:25 PM PDT 24 Jun 23 05:49:27 PM PDT 24 18713243 ps
T1118 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1943091287 Jun 23 05:49:14 PM PDT 24 Jun 23 05:49:16 PM PDT 24 46658015 ps
T1119 /workspace/coverage/cover_reg_top/30.edn_intr_test.4211162838 Jun 23 05:49:29 PM PDT 24 Jun 23 05:49:30 PM PDT 24 28503806 ps
T1120 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.936191612 Jun 23 05:49:14 PM PDT 24 Jun 23 05:49:16 PM PDT 24 22189169 ps
T1121 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3375522537 Jun 23 05:49:26 PM PDT 24 Jun 23 05:49:28 PM PDT 24 14671809 ps
T1122 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2847256084 Jun 23 05:49:01 PM PDT 24 Jun 23 05:49:05 PM PDT 24 109061718 ps
T1123 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2428995531 Jun 23 05:49:24 PM PDT 24 Jun 23 05:49:25 PM PDT 24 54096088 ps
T1124 /workspace/coverage/cover_reg_top/13.edn_csr_rw.945871193 Jun 23 05:49:20 PM PDT 24 Jun 23 05:49:21 PM PDT 24 41902112 ps
T1125 /workspace/coverage/cover_reg_top/13.edn_intr_test.3352285881 Jun 23 05:49:18 PM PDT 24 Jun 23 05:49:20 PM PDT 24 25698090 ps
T1126 /workspace/coverage/cover_reg_top/19.edn_intr_test.3731043316 Jun 23 05:49:26 PM PDT 24 Jun 23 05:49:27 PM PDT 24 29043789 ps
T1127 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3771459474 Jun 23 05:49:11 PM PDT 24 Jun 23 05:49:12 PM PDT 24 34256926 ps
T269 /workspace/coverage/cover_reg_top/1.edn_csr_rw.1611274123 Jun 23 05:49:07 PM PDT 24 Jun 23 05:49:08 PM PDT 24 110030039 ps
T1128 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3820859850 Jun 23 05:49:20 PM PDT 24 Jun 23 05:49:23 PM PDT 24 960011896 ps
T1129 /workspace/coverage/cover_reg_top/20.edn_intr_test.3663002272 Jun 23 05:49:22 PM PDT 24 Jun 23 05:49:23 PM PDT 24 88802776 ps
T1130 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3601979542 Jun 23 05:49:06 PM PDT 24 Jun 23 05:49:08 PM PDT 24 61658974 ps

Test location /workspace/coverage/default/253.edn_genbits.178407029
Short name T8
Test name
Test status
Simulation time 70034115 ps
CPU time 1.16 seconds
Started Jun 23 05:37:02 PM PDT 24
Finished Jun 23 05:37:03 PM PDT 24
Peak memory 219052 kb
Host smart-08e3822c-0ce6-4ef3-9a4d-bbd32afab1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178407029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.178407029
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.178281145
Short name T39
Test name
Test status
Simulation time 518938277695 ps
CPU time 1056.85 seconds
Started Jun 23 05:33:55 PM PDT 24
Finished Jun 23 05:51:32 PM PDT 24
Peak memory 220832 kb
Host smart-747a6289-337a-467c-8c21-f1e85fdcd7f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178281145 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.178281145
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.3688010279
Short name T2
Test name
Test status
Simulation time 33417737 ps
CPU time 1.21 seconds
Started Jun 23 05:36:38 PM PDT 24
Finished Jun 23 05:36:40 PM PDT 24
Peak memory 219172 kb
Host smart-c1c5ed10-80c0-4742-a1da-f24ee798dbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688010279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3688010279
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3060217516
Short name T17
Test name
Test status
Simulation time 1033777340 ps
CPU time 4.4 seconds
Started Jun 23 05:33:51 PM PDT 24
Finished Jun 23 05:33:56 PM PDT 24
Peak memory 241452 kb
Host smart-2837119c-b519-45c8-9e67-1e6ba9712268
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060217516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3060217516
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/54.edn_err.3007403821
Short name T29
Test name
Test status
Simulation time 31439535 ps
CPU time 0.87 seconds
Started Jun 23 05:35:49 PM PDT 24
Finished Jun 23 05:35:51 PM PDT 24
Peak memory 218136 kb
Host smart-33d57c2a-dde5-446f-9e72-e57973b6bf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007403821 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3007403821
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1808830042
Short name T12
Test name
Test status
Simulation time 61678359 ps
CPU time 1.07 seconds
Started Jun 23 05:34:52 PM PDT 24
Finished Jun 23 05:34:54 PM PDT 24
Peak memory 219104 kb
Host smart-1b097da2-23b0-416e-974e-ab2e35d195f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808830042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1808830042
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.235263819
Short name T9
Test name
Test status
Simulation time 60284237 ps
CPU time 1.16 seconds
Started Jun 23 05:34:56 PM PDT 24
Finished Jun 23 05:34:57 PM PDT 24
Peak memory 217516 kb
Host smart-1bd53a80-f4c2-4fac-8351-3eed554db4c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235263819 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.235263819
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/174.edn_alert.340410067
Short name T95
Test name
Test status
Simulation time 25740773 ps
CPU time 1.19 seconds
Started Jun 23 05:36:42 PM PDT 24
Finished Jun 23 05:36:44 PM PDT 24
Peak memory 219156 kb
Host smart-760cb642-fd67-4095-8e09-2a3552d8ebd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340410067 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.340410067
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/61.edn_alert.1976520126
Short name T123
Test name
Test status
Simulation time 33438525 ps
CPU time 1.16 seconds
Started Jun 23 05:35:55 PM PDT 24
Finished Jun 23 05:35:57 PM PDT 24
Peak memory 217976 kb
Host smart-1243de0f-168e-40cd-ac34-20c4d45ec4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976520126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1976520126
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3063213323
Short name T230
Test name
Test status
Simulation time 27754079161 ps
CPU time 627.53 seconds
Started Jun 23 05:35:27 PM PDT 24
Finished Jun 23 05:45:55 PM PDT 24
Peak memory 218880 kb
Host smart-6e30a9d2-1c3a-4304-a94a-b90ccf02bc23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063213323 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3063213323
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.edn_regwen.3373115643
Short name T25
Test name
Test status
Simulation time 24468000 ps
CPU time 0.95 seconds
Started Jun 23 05:34:09 PM PDT 24
Finished Jun 23 05:34:11 PM PDT 24
Peak memory 206448 kb
Host smart-f30fb1b4-02e9-41fa-b5c8-85da350849ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373115643 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3373115643
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/17.edn_disable.506248279
Short name T100
Test name
Test status
Simulation time 42399863 ps
CPU time 0.87 seconds
Started Jun 23 05:34:35 PM PDT 24
Finished Jun 23 05:34:36 PM PDT 24
Peak memory 214848 kb
Host smart-b3ed25e1-5c00-4b5a-9652-ccdd407e493e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506248279 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.506248279
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/101.edn_alert.279953833
Short name T121
Test name
Test status
Simulation time 54740712 ps
CPU time 1.26 seconds
Started Jun 23 05:36:18 PM PDT 24
Finished Jun 23 05:36:21 PM PDT 24
Peak memory 219332 kb
Host smart-e86154d6-3eec-4e4f-9590-b70829de2947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279953833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.279953833
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.819064893
Short name T166
Test name
Test status
Simulation time 61345736 ps
CPU time 1.11 seconds
Started Jun 23 05:34:22 PM PDT 24
Finished Jun 23 05:34:23 PM PDT 24
Peak memory 218904 kb
Host smart-a287f8cf-6fbc-4991-97f9-458f655333e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819064893 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.819064893
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/132.edn_alert.2317809641
Short name T168
Test name
Test status
Simulation time 26719273 ps
CPU time 1.29 seconds
Started Jun 23 05:36:34 PM PDT 24
Finished Jun 23 05:36:36 PM PDT 24
Peak memory 218620 kb
Host smart-18439f23-fb3f-416c-8307-0ded9ee083ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317809641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.2317809641
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.392079595
Short name T282
Test name
Test status
Simulation time 243125465 ps
CPU time 2.37 seconds
Started Jun 23 05:49:26 PM PDT 24
Finished Jun 23 05:49:29 PM PDT 24
Peak memory 206368 kb
Host smart-91c37343-74af-4970-80b0-a7cbc7744ee8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392079595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.392079595
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/default/6.edn_disable.897136447
Short name T87
Test name
Test status
Simulation time 34783635 ps
CPU time 0.85 seconds
Started Jun 23 05:34:02 PM PDT 24
Finished Jun 23 05:34:03 PM PDT 24
Peak memory 215836 kb
Host smart-c451a46c-2db0-44a3-bba6-4cdee08357bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897136447 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.897136447
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable.3049686236
Short name T90
Test name
Test status
Simulation time 34662022 ps
CPU time 0.82 seconds
Started Jun 23 05:35:09 PM PDT 24
Finished Jun 23 05:35:10 PM PDT 24
Peak memory 215696 kb
Host smart-e3bbaffd-517b-40ca-b07f-2ae8c6d4ed76
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049686236 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3049686236
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3842365410
Short name T842
Test name
Test status
Simulation time 66093001 ps
CPU time 1.3 seconds
Started Jun 23 05:34:14 PM PDT 24
Finished Jun 23 05:34:16 PM PDT 24
Peak memory 216332 kb
Host smart-fa9e6bc5-b453-487e-abf0-070702f02449
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842365410 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3842365410
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3807077273
Short name T847
Test name
Test status
Simulation time 61005454 ps
CPU time 1.28 seconds
Started Jun 23 05:34:22 PM PDT 24
Finished Jun 23 05:34:24 PM PDT 24
Peak memory 216164 kb
Host smart-ca5b2367-5550-4b92-a91d-0df8debf5d32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807077273 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3807077273
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3090622669
Short name T196
Test name
Test status
Simulation time 26614390 ps
CPU time 0.93 seconds
Started Jun 23 05:34:29 PM PDT 24
Finished Jun 23 05:34:30 PM PDT 24
Peak memory 217636 kb
Host smart-c21ed46e-73a9-44b2-a2e1-49c220f2ebf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090622669 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3090622669
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/106.edn_alert.2219832003
Short name T221
Test name
Test status
Simulation time 25096486 ps
CPU time 1.18 seconds
Started Jun 23 05:36:23 PM PDT 24
Finished Jun 23 05:36:25 PM PDT 24
Peak memory 219424 kb
Host smart-b7e10d15-2ad1-4777-ad0a-f0c30c50410d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219832003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2219832003
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1348417505
Short name T259
Test name
Test status
Simulation time 39863929 ps
CPU time 0.82 seconds
Started Jun 23 05:49:21 PM PDT 24
Finished Jun 23 05:49:22 PM PDT 24
Peak memory 206264 kb
Host smart-37fcabf8-4d1f-4f26-8381-e966161ff56b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348417505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1348417505
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.777850827
Short name T41
Test name
Test status
Simulation time 208090191523 ps
CPU time 884.53 seconds
Started Jun 23 05:34:54 PM PDT 24
Finished Jun 23 05:49:39 PM PDT 24
Peak memory 239340 kb
Host smart-7251f0e3-5b5d-490b-9d00-5a61b74e7d0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777850827 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.777850827
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/236.edn_genbits.4114589857
Short name T89
Test name
Test status
Simulation time 99325251 ps
CPU time 1.61 seconds
Started Jun 23 05:37:03 PM PDT 24
Finished Jun 23 05:37:05 PM PDT 24
Peak memory 218100 kb
Host smart-2f6d9b7a-b988-4614-a3c5-5a85883aa33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114589857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.4114589857
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1402661709
Short name T145
Test name
Test status
Simulation time 29113011 ps
CPU time 1.32 seconds
Started Jun 23 05:34:19 PM PDT 24
Finished Jun 23 05:34:20 PM PDT 24
Peak memory 217844 kb
Host smart-0ff8a8ed-c3ec-4197-99e6-643d01002cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402661709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1402661709
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/105.edn_alert.1978198989
Short name T158
Test name
Test status
Simulation time 80460535 ps
CPU time 1.09 seconds
Started Jun 23 05:36:21 PM PDT 24
Finished Jun 23 05:36:23 PM PDT 24
Peak memory 219924 kb
Host smart-e1713a39-ea5b-4b40-b639-d3a16de22580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978198989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.1978198989
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/108.edn_alert.3958774888
Short name T538
Test name
Test status
Simulation time 160881658 ps
CPU time 1.25 seconds
Started Jun 23 05:36:21 PM PDT 24
Finished Jun 23 05:36:23 PM PDT 24
Peak memory 217828 kb
Host smart-42fe7f93-f8c0-4ed8-a308-e5334ca4f076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958774888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.3958774888
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/137.edn_alert.3733404865
Short name T174
Test name
Test status
Simulation time 67585385 ps
CPU time 1.17 seconds
Started Jun 23 05:36:30 PM PDT 24
Finished Jun 23 05:36:32 PM PDT 24
Peak memory 220140 kb
Host smart-174dc4f3-2fd4-44aa-a5c0-c04ca01b7337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733404865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.3733404865
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/193.edn_alert.4291286722
Short name T494
Test name
Test status
Simulation time 107168947 ps
CPU time 1.37 seconds
Started Jun 23 05:36:55 PM PDT 24
Finished Jun 23 05:36:57 PM PDT 24
Peak memory 215092 kb
Host smart-e19b09c8-59ad-4d4e-a065-bbf20d2e66a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291286722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.4291286722
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/27.edn_intr.1335312975
Short name T1
Test name
Test status
Simulation time 34482310 ps
CPU time 0.86 seconds
Started Jun 23 05:34:53 PM PDT 24
Finished Jun 23 05:34:54 PM PDT 24
Peak memory 214872 kb
Host smart-6ed18022-bf29-44b1-9dc2-fe6fdda278b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335312975 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1335312975
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/186.edn_genbits.3336027991
Short name T304
Test name
Test status
Simulation time 29041382 ps
CPU time 1.33 seconds
Started Jun 23 05:36:47 PM PDT 24
Finished Jun 23 05:36:49 PM PDT 24
Peak memory 216620 kb
Host smart-c9379769-13ba-4e69-88df-cd48ebf5cbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336027991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3336027991
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.217370020
Short name T744
Test name
Test status
Simulation time 30453287 ps
CPU time 1.24 seconds
Started Jun 23 05:36:47 PM PDT 24
Finished Jun 23 05:36:49 PM PDT 24
Peak memory 220108 kb
Host smart-6dabc40c-489e-4a90-9ff0-6775d00de458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217370020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.217370020
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/19.edn_intr.4155733507
Short name T35
Test name
Test status
Simulation time 24927990 ps
CPU time 0.9 seconds
Started Jun 23 05:34:40 PM PDT 24
Finished Jun 23 05:34:42 PM PDT 24
Peak memory 215084 kb
Host smart-3bde392e-2fe6-421b-8dce-61c9d7fbb331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155733507 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.4155733507
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1430451293
Short name T10
Test name
Test status
Simulation time 80434625 ps
CPU time 1.06 seconds
Started Jun 23 05:34:34 PM PDT 24
Finished Jun 23 05:34:36 PM PDT 24
Peak memory 216172 kb
Host smart-fb4f2cba-626b-4966-9046-f83671032bea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430451293 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1430451293
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_disable.586697046
Short name T214
Test name
Test status
Simulation time 22952531 ps
CPU time 0.89 seconds
Started Jun 23 05:35:08 PM PDT 24
Finished Jun 23 05:35:10 PM PDT 24
Peak memory 215472 kb
Host smart-9e0de6e6-b1ec-4388-9970-63c8d84821c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586697046 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.586697046
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2095397928
Short name T91
Test name
Test status
Simulation time 22140279 ps
CPU time 1.16 seconds
Started Jun 23 05:33:47 PM PDT 24
Finished Jun 23 05:33:49 PM PDT 24
Peak memory 216332 kb
Host smart-aaad6823-4c58-432d-97df-a89eea6471b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095397928 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2095397928
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/121.edn_alert.2840941247
Short name T189
Test name
Test status
Simulation time 26741709 ps
CPU time 1.23 seconds
Started Jun 23 05:36:25 PM PDT 24
Finished Jun 23 05:36:27 PM PDT 24
Peak memory 219256 kb
Host smart-9c404cda-7100-4eba-852b-8c1679ed3f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840941247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.2840941247
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/126.edn_alert.2059971532
Short name T182
Test name
Test status
Simulation time 40531452 ps
CPU time 1.08 seconds
Started Jun 23 05:36:25 PM PDT 24
Finished Jun 23 05:36:26 PM PDT 24
Peak memory 218044 kb
Host smart-d5d84a3c-35d9-47e0-b006-63546b43fd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059971532 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.2059971532
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert.3225425381
Short name T846
Test name
Test status
Simulation time 80070483 ps
CPU time 1.19 seconds
Started Jun 23 05:34:22 PM PDT 24
Finished Jun 23 05:34:24 PM PDT 24
Peak memory 217928 kb
Host smart-9d478034-0b47-4ee7-8a47-44454cea93e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225425381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3225425381
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/138.edn_alert.231820332
Short name T186
Test name
Test status
Simulation time 25298435 ps
CPU time 1.16 seconds
Started Jun 23 05:36:34 PM PDT 24
Finished Jun 23 05:36:35 PM PDT 24
Peak memory 219036 kb
Host smart-02d3122e-9df5-455c-be5e-d07e21af65dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231820332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.231820332
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.4051079571
Short name T160
Test name
Test status
Simulation time 97745090 ps
CPU time 1.17 seconds
Started Jun 23 05:34:24 PM PDT 24
Finished Jun 23 05:34:26 PM PDT 24
Peak memory 216196 kb
Host smart-6554c154-2ad0-490f-a62d-dfcbc2861237
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051079571 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.4051079571
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_disable.815436017
Short name T185
Test name
Test status
Simulation time 10370676 ps
CPU time 0.84 seconds
Started Jun 23 05:33:51 PM PDT 24
Finished Jun 23 05:33:52 PM PDT 24
Peak memory 215696 kb
Host smart-ba9b191e-5dd4-491b-b860-c740cebe1cf3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815436017 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.815436017
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/41.edn_err.2351604032
Short name T202
Test name
Test status
Simulation time 20349663 ps
CPU time 1.13 seconds
Started Jun 23 05:35:26 PM PDT 24
Finished Jun 23 05:35:28 PM PDT 24
Peak memory 228964 kb
Host smart-c71ab61f-a253-4f8a-93a9-112f3d50c09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351604032 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2351604032
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/183.edn_genbits.2043530529
Short name T308
Test name
Test status
Simulation time 31527266 ps
CPU time 1.34 seconds
Started Jun 23 05:36:46 PM PDT 24
Finished Jun 23 05:36:48 PM PDT 24
Peak memory 219440 kb
Host smart-75ccb70a-5019-4704-bec0-fb61ef266490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043530529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2043530529
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert_test.2941914766
Short name T76
Test name
Test status
Simulation time 31245370 ps
CPU time 1 seconds
Started Jun 23 05:33:44 PM PDT 24
Finished Jun 23 05:33:45 PM PDT 24
Peak memory 214604 kb
Host smart-183f5ea2-7daf-4bf6-9ec3-caa7945715c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941914766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2941914766
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/168.edn_genbits.1835009380
Short name T97
Test name
Test status
Simulation time 62544503 ps
CPU time 1.57 seconds
Started Jun 23 05:36:44 PM PDT 24
Finished Jun 23 05:36:46 PM PDT 24
Peak memory 217824 kb
Host smart-27fbc996-7abb-46d1-94ef-043b4b324e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835009380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1835009380
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_genbits.2503729651
Short name T98
Test name
Test status
Simulation time 31638069 ps
CPU time 1.24 seconds
Started Jun 23 05:34:15 PM PDT 24
Finished Jun 23 05:34:16 PM PDT 24
Peak memory 216736 kb
Host smart-9a77934f-8655-46be-a094-9a66347e2f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503729651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2503729651
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.781202692
Short name T102
Test name
Test status
Simulation time 29915036 ps
CPU time 0.93 seconds
Started Jun 23 05:33:46 PM PDT 24
Finished Jun 23 05:33:47 PM PDT 24
Peak memory 215144 kb
Host smart-8560a82e-cdb6-4689-b351-652ae6107e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781202692 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.781202692
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/102.edn_alert.372872012
Short name T94
Test name
Test status
Simulation time 28210339 ps
CPU time 1.23 seconds
Started Jun 23 05:36:19 PM PDT 24
Finished Jun 23 05:36:21 PM PDT 24
Peak memory 219344 kb
Host smart-5b0a6798-a38d-435e-b23b-c5ee690c6c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372872012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.372872012
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.3319041616
Short name T328
Test name
Test status
Simulation time 59232987 ps
CPU time 1.34 seconds
Started Jun 23 05:36:50 PM PDT 24
Finished Jun 23 05:36:51 PM PDT 24
Peak memory 217912 kb
Host smart-ff873e29-5a02-49b4-ab3e-95ef48b63b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319041616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3319041616
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3923844354
Short name T434
Test name
Test status
Simulation time 110942761 ps
CPU time 1.74 seconds
Started Jun 23 05:36:58 PM PDT 24
Finished Jun 23 05:37:00 PM PDT 24
Peak memory 218320 kb
Host smart-22de425a-d8ad-406b-b20f-157996a6e230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923844354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3923844354
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_err.1477093978
Short name T152
Test name
Test status
Simulation time 33318648 ps
CPU time 1.01 seconds
Started Jun 23 05:34:53 PM PDT 24
Finished Jun 23 05:34:54 PM PDT 24
Peak memory 229032 kb
Host smart-bfb69a20-6fa0-4ac3-ab1c-8e47b8ab05e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477093978 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1477093978
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2934330086
Short name T265
Test name
Test status
Simulation time 17420437 ps
CPU time 0.84 seconds
Started Jun 23 05:49:04 PM PDT 24
Finished Jun 23 05:49:05 PM PDT 24
Peak memory 206180 kb
Host smart-78d64bd6-9452-41da-b365-856dc48d437a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934330086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2934330086
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3639010266
Short name T291
Test name
Test status
Simulation time 156365950 ps
CPU time 2.36 seconds
Started Jun 23 05:49:05 PM PDT 24
Finished Jun 23 05:49:08 PM PDT 24
Peak memory 206684 kb
Host smart-52b7e964-8cd8-49e0-8b83-231f1ee10c70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639010266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3639010266
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/101.edn_genbits.2649525632
Short name T311
Test name
Test status
Simulation time 146076690 ps
CPU time 1.23 seconds
Started Jun 23 05:36:25 PM PDT 24
Finished Jun 23 05:36:26 PM PDT 24
Peak memory 218188 kb
Host smart-2da4323d-e091-410d-9365-6e78ca60def0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649525632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2649525632
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.552096889
Short name T317
Test name
Test status
Simulation time 89041028 ps
CPU time 2.74 seconds
Started Jun 23 05:36:21 PM PDT 24
Finished Jun 23 05:36:25 PM PDT 24
Peak memory 216872 kb
Host smart-f01e09f6-7142-4dc7-a35c-f91ec587f632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552096889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.552096889
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3512108654
Short name T499
Test name
Test status
Simulation time 42430698 ps
CPU time 1.24 seconds
Started Jun 23 05:36:22 PM PDT 24
Finished Jun 23 05:36:24 PM PDT 24
Peak memory 220644 kb
Host smart-45e03ec6-3bc9-4b33-b249-66364c3c9d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512108654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3512108654
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/120.edn_alert.1509614254
Short name T169
Test name
Test status
Simulation time 185310656 ps
CPU time 1.43 seconds
Started Jun 23 05:36:28 PM PDT 24
Finished Jun 23 05:36:30 PM PDT 24
Peak memory 218036 kb
Host smart-0222bb9d-e8e4-4eac-8635-0fb09151b4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509614254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.1509614254
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.2739432131
Short name T11
Test name
Test status
Simulation time 35609770 ps
CPU time 1.46 seconds
Started Jun 23 05:36:26 PM PDT 24
Finished Jun 23 05:36:28 PM PDT 24
Peak memory 219520 kb
Host smart-32def2cd-faa3-4600-baa3-f6cddebca14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739432131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2739432131
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3999243936
Short name T314
Test name
Test status
Simulation time 60466374 ps
CPU time 1.07 seconds
Started Jun 23 05:36:30 PM PDT 24
Finished Jun 23 05:36:32 PM PDT 24
Peak memory 218100 kb
Host smart-40d25e30-7e72-4039-9471-4564a760227a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999243936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3999243936
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1488822169
Short name T331
Test name
Test status
Simulation time 53430296 ps
CPU time 1.26 seconds
Started Jun 23 05:36:35 PM PDT 24
Finished Jun 23 05:36:37 PM PDT 24
Peak memory 214508 kb
Host smart-d18af6db-cba3-4170-bf46-f1722d077f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488822169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1488822169
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_stress_all.3571603592
Short name T785
Test name
Test status
Simulation time 827416960 ps
CPU time 3.97 seconds
Started Jun 23 05:34:25 PM PDT 24
Finished Jun 23 05:34:29 PM PDT 24
Peak memory 214644 kb
Host smart-91804538-5c8e-4859-ba54-e8e71568fccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571603592 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3571603592
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/150.edn_genbits.1920919131
Short name T634
Test name
Test status
Simulation time 190624559 ps
CPU time 1.33 seconds
Started Jun 23 05:36:36 PM PDT 24
Finished Jun 23 05:36:38 PM PDT 24
Peak memory 218448 kb
Host smart-45171272-940f-4b2a-9a09-227b0b9c41f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920919131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1920919131
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.3820966820
Short name T306
Test name
Test status
Simulation time 70948070 ps
CPU time 1.34 seconds
Started Jun 23 05:36:45 PM PDT 24
Finished Jun 23 05:36:47 PM PDT 24
Peak memory 218336 kb
Host smart-258ca88e-e229-4105-b96a-6f2bc530b811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820966820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3820966820
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_genbits.3537872465
Short name T320
Test name
Test status
Simulation time 60758858 ps
CPU time 1.72 seconds
Started Jun 23 05:36:11 PM PDT 24
Finished Jun 23 05:36:13 PM PDT 24
Peak memory 217984 kb
Host smart-eec76eea-cc04-42c2-9943-dc8ccb693271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537872465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3537872465
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1437448048
Short name T107
Test name
Test status
Simulation time 27771345 ps
CPU time 0.89 seconds
Started Jun 23 05:34:09 PM PDT 24
Finished Jun 23 05:34:11 PM PDT 24
Peak memory 214940 kb
Host smart-19b54508-29c4-4b99-92c2-d87ce763f6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437448048 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1437448048
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/178.edn_alert.510880526
Short name T125
Test name
Test status
Simulation time 25111738 ps
CPU time 1.19 seconds
Started Jun 23 05:36:45 PM PDT 24
Finished Jun 23 05:36:47 PM PDT 24
Peak memory 218740 kb
Host smart-93a0d9a4-b847-4547-8a8e-0b1943c8c9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510880526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.510880526
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/224.edn_genbits.1670187139
Short name T567
Test name
Test status
Simulation time 90311240 ps
CPU time 1.51 seconds
Started Jun 23 05:36:59 PM PDT 24
Finished Jun 23 05:37:01 PM PDT 24
Peak memory 216980 kb
Host smart-1b8107eb-81aa-4568-82ad-5f348b4d48fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670187139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1670187139
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1568107962
Short name T1070
Test name
Test status
Simulation time 239142464 ps
CPU time 1.47 seconds
Started Jun 23 05:49:07 PM PDT 24
Finished Jun 23 05:49:09 PM PDT 24
Peak memory 206328 kb
Host smart-fad9af90-5fdf-48fe-b418-1c6cacf0c8e8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568107962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1568107962
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2585810652
Short name T1091
Test name
Test status
Simulation time 348683667 ps
CPU time 4.9 seconds
Started Jun 23 05:49:07 PM PDT 24
Finished Jun 23 05:49:13 PM PDT 24
Peak memory 206560 kb
Host smart-4c733aa7-a1d9-4940-9864-b6a07cef60c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585810652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2585810652
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3228562337
Short name T1036
Test name
Test status
Simulation time 23576233 ps
CPU time 0.96 seconds
Started Jun 23 05:49:02 PM PDT 24
Finished Jun 23 05:49:03 PM PDT 24
Peak memory 206304 kb
Host smart-1fb952ab-096e-47cc-89c8-5ab2898ed88e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228562337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3228562337
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.934427855
Short name T1048
Test name
Test status
Simulation time 25064351 ps
CPU time 1.39 seconds
Started Jun 23 05:49:06 PM PDT 24
Finished Jun 23 05:49:08 PM PDT 24
Peak memory 214796 kb
Host smart-1ed5a437-a3f5-4eb6-b2a1-741af86f4f14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934427855 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.934427855
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1449085136
Short name T1012
Test name
Test status
Simulation time 42190106 ps
CPU time 0.82 seconds
Started Jun 23 05:48:59 PM PDT 24
Finished Jun 23 05:49:01 PM PDT 24
Peak memory 206236 kb
Host smart-b19334d6-8cb1-409b-a535-b0a52360d819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449085136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1449085136
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1264772606
Short name T1054
Test name
Test status
Simulation time 121838870 ps
CPU time 1.16 seconds
Started Jun 23 05:49:07 PM PDT 24
Finished Jun 23 05:49:08 PM PDT 24
Peak memory 206364 kb
Host smart-9dc3e08e-6301-4290-bd50-d53ccad9327b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264772606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1264772606
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2847256084
Short name T1122
Test name
Test status
Simulation time 109061718 ps
CPU time 3.39 seconds
Started Jun 23 05:49:01 PM PDT 24
Finished Jun 23 05:49:05 PM PDT 24
Peak memory 214636 kb
Host smart-fa44bac7-cc8b-40f0-91a7-acddc6eebc91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847256084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2847256084
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1070532009
Short name T1016
Test name
Test status
Simulation time 19963764 ps
CPU time 1.29 seconds
Started Jun 23 05:49:03 PM PDT 24
Finished Jun 23 05:49:05 PM PDT 24
Peak memory 206240 kb
Host smart-9ef4b43f-7f94-430f-91e5-edb1ad524582
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070532009 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1070532009
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2914245935
Short name T1103
Test name
Test status
Simulation time 517954801 ps
CPU time 3.61 seconds
Started Jun 23 05:49:06 PM PDT 24
Finished Jun 23 05:49:10 PM PDT 24
Peak memory 206244 kb
Host smart-bce8b80b-aaa8-4909-909e-a3dcb8b60317
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914245935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2914245935
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.773544372
Short name T1015
Test name
Test status
Simulation time 22709984 ps
CPU time 0.87 seconds
Started Jun 23 05:49:06 PM PDT 24
Finished Jun 23 05:49:07 PM PDT 24
Peak memory 206288 kb
Host smart-70a61cab-9596-49d0-bdd8-a686cb7cef68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773544372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.773544372
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2439565996
Short name T998
Test name
Test status
Simulation time 33555081 ps
CPU time 1.31 seconds
Started Jun 23 05:49:05 PM PDT 24
Finished Jun 23 05:49:07 PM PDT 24
Peak memory 214776 kb
Host smart-a6d0a3d7-2f6c-45d5-a3e5-8ddda4f6bb13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439565996 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2439565996
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1611274123
Short name T269
Test name
Test status
Simulation time 110030039 ps
CPU time 0.76 seconds
Started Jun 23 05:49:07 PM PDT 24
Finished Jun 23 05:49:08 PM PDT 24
Peak memory 206204 kb
Host smart-a32b9035-5c22-4147-b320-7041ad300617
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611274123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1611274123
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2344505464
Short name T1011
Test name
Test status
Simulation time 43012794 ps
CPU time 0.77 seconds
Started Jun 23 05:49:00 PM PDT 24
Finished Jun 23 05:49:01 PM PDT 24
Peak memory 206140 kb
Host smart-2b490dc2-ae58-44a1-b789-f708ff5767d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344505464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2344505464
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.859872739
Short name T258
Test name
Test status
Simulation time 75698211 ps
CPU time 1.11 seconds
Started Jun 23 05:49:05 PM PDT 24
Finished Jun 23 05:49:07 PM PDT 24
Peak memory 206324 kb
Host smart-d524bec2-ea19-4bfc-8bad-f628dc68bb9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859872739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.859872739
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1091943097
Short name T1025
Test name
Test status
Simulation time 940963681 ps
CPU time 4.71 seconds
Started Jun 23 05:49:03 PM PDT 24
Finished Jun 23 05:49:08 PM PDT 24
Peak memory 214624 kb
Host smart-e326d048-5a41-4925-a865-65fe65216a32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091943097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1091943097
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.946879681
Short name T1051
Test name
Test status
Simulation time 238142778 ps
CPU time 1.53 seconds
Started Jun 23 05:49:03 PM PDT 24
Finished Jun 23 05:49:05 PM PDT 24
Peak memory 206328 kb
Host smart-fc800dd8-f179-41f3-8d29-3646d47558bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946879681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.946879681
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2964291466
Short name T1101
Test name
Test status
Simulation time 77380278 ps
CPU time 1.15 seconds
Started Jun 23 05:49:14 PM PDT 24
Finished Jun 23 05:49:15 PM PDT 24
Peak memory 222808 kb
Host smart-efccba6b-cd84-4d3e-b81e-6556813cf66c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964291466 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2964291466
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3537378963
Short name T1104
Test name
Test status
Simulation time 19792438 ps
CPU time 0.81 seconds
Started Jun 23 05:49:10 PM PDT 24
Finished Jun 23 05:49:12 PM PDT 24
Peak memory 206172 kb
Host smart-cc28a652-ce8d-4b34-8567-aa516e89d8b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537378963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3537378963
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1024345572
Short name T1021
Test name
Test status
Simulation time 12002896 ps
CPU time 0.86 seconds
Started Jun 23 05:49:14 PM PDT 24
Finished Jun 23 05:49:15 PM PDT 24
Peak memory 206280 kb
Host smart-644e305f-4aa0-46da-9965-34d4d5037e3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024345572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1024345572
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.445184686
Short name T272
Test name
Test status
Simulation time 134808516 ps
CPU time 0.92 seconds
Started Jun 23 05:49:13 PM PDT 24
Finished Jun 23 05:49:14 PM PDT 24
Peak memory 206292 kb
Host smart-8acbce15-40da-481d-801b-c2a00d777c10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445184686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.445184686
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1659643883
Short name T1083
Test name
Test status
Simulation time 65194185 ps
CPU time 2.27 seconds
Started Jun 23 05:49:10 PM PDT 24
Finished Jun 23 05:49:13 PM PDT 24
Peak memory 214636 kb
Host smart-c33325a4-1513-4622-9359-6baa5ee249ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659643883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1659643883
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.200605477
Short name T288
Test name
Test status
Simulation time 76746267 ps
CPU time 1.56 seconds
Started Jun 23 05:49:14 PM PDT 24
Finished Jun 23 05:49:16 PM PDT 24
Peak memory 206424 kb
Host smart-fe0062b3-1fc6-4ac7-817f-c5c4bc32f92b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200605477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.200605477
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1497838467
Short name T1017
Test name
Test status
Simulation time 178733941 ps
CPU time 1.82 seconds
Started Jun 23 05:49:16 PM PDT 24
Finished Jun 23 05:49:18 PM PDT 24
Peak memory 214632 kb
Host smart-d232d69b-e27a-48d3-b9b3-4a11261f8354
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497838467 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1497838467
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1720075559
Short name T1087
Test name
Test status
Simulation time 14807443 ps
CPU time 0.92 seconds
Started Jun 23 05:49:14 PM PDT 24
Finished Jun 23 05:49:15 PM PDT 24
Peak memory 206252 kb
Host smart-b36fe2f2-513a-4c49-b177-a4a081ddc729
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720075559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1720075559
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.4259673785
Short name T1109
Test name
Test status
Simulation time 13199875 ps
CPU time 0.93 seconds
Started Jun 23 05:49:15 PM PDT 24
Finished Jun 23 05:49:16 PM PDT 24
Peak memory 206308 kb
Host smart-a2989071-de7e-4f68-a793-3133c7aec3fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259673785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.4259673785
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3138859401
Short name T1076
Test name
Test status
Simulation time 60184197 ps
CPU time 1.15 seconds
Started Jun 23 05:49:13 PM PDT 24
Finished Jun 23 05:49:15 PM PDT 24
Peak memory 206384 kb
Host smart-391b36e2-239a-4523-96b1-32fe5288a5e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138859401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3138859401
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3218140656
Short name T1097
Test name
Test status
Simulation time 31431248 ps
CPU time 2.17 seconds
Started Jun 23 05:49:15 PM PDT 24
Finished Jun 23 05:49:18 PM PDT 24
Peak memory 214672 kb
Host smart-d3290b51-a148-408a-a487-385eb21d08b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218140656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3218140656
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.4011156615
Short name T1086
Test name
Test status
Simulation time 236010172 ps
CPU time 1.69 seconds
Started Jun 23 05:49:14 PM PDT 24
Finished Jun 23 05:49:17 PM PDT 24
Peak memory 206632 kb
Host smart-a102ead3-cdd3-4985-872e-0f678282fc1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011156615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.4011156615
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1008436097
Short name T1032
Test name
Test status
Simulation time 61378084 ps
CPU time 1.41 seconds
Started Jun 23 05:49:24 PM PDT 24
Finished Jun 23 05:49:26 PM PDT 24
Peak memory 214608 kb
Host smart-ec328fd9-2f04-4f23-899e-c7eb648a204e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008436097 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1008436097
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3633334043
Short name T268
Test name
Test status
Simulation time 17455193 ps
CPU time 1 seconds
Started Jun 23 05:49:25 PM PDT 24
Finished Jun 23 05:49:27 PM PDT 24
Peak memory 206248 kb
Host smart-d165837b-cb2c-46b7-b0ce-56af623a0dcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633334043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3633334043
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1222766511
Short name T1033
Test name
Test status
Simulation time 108636785 ps
CPU time 0.81 seconds
Started Jun 23 05:49:19 PM PDT 24
Finished Jun 23 05:49:20 PM PDT 24
Peak memory 206168 kb
Host smart-d0362af8-b526-4f8f-9a9c-968d0bf1d209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222766511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1222766511
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4013876672
Short name T1046
Test name
Test status
Simulation time 69052376 ps
CPU time 1.56 seconds
Started Jun 23 05:49:26 PM PDT 24
Finished Jun 23 05:49:28 PM PDT 24
Peak memory 206308 kb
Host smart-3059868a-7c7b-450c-acfa-999e99808c75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013876672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.4013876672
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3331139078
Short name T1007
Test name
Test status
Simulation time 98050760 ps
CPU time 2.09 seconds
Started Jun 23 05:49:19 PM PDT 24
Finished Jun 23 05:49:21 PM PDT 24
Peak memory 214620 kb
Host smart-98da78c1-70ca-4846-913d-0f4d84111c4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331139078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3331139078
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.344819659
Short name T1078
Test name
Test status
Simulation time 131822685 ps
CPU time 1.56 seconds
Started Jun 23 05:49:24 PM PDT 24
Finished Jun 23 05:49:26 PM PDT 24
Peak memory 206380 kb
Host smart-ec12f5f1-5ae3-4707-ae0e-fce25d42dc50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344819659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.344819659
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2428995531
Short name T1123
Test name
Test status
Simulation time 54096088 ps
CPU time 0.96 seconds
Started Jun 23 05:49:24 PM PDT 24
Finished Jun 23 05:49:25 PM PDT 24
Peak memory 206440 kb
Host smart-cc538458-7d9d-4e28-83a1-2394a653f6dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428995531 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2428995531
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.945871193
Short name T1124
Test name
Test status
Simulation time 41902112 ps
CPU time 0.87 seconds
Started Jun 23 05:49:20 PM PDT 24
Finished Jun 23 05:49:21 PM PDT 24
Peak memory 206196 kb
Host smart-017cffc2-e174-4a77-9179-9bc91cea3c9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945871193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.945871193
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3352285881
Short name T1125
Test name
Test status
Simulation time 25698090 ps
CPU time 0.88 seconds
Started Jun 23 05:49:18 PM PDT 24
Finished Jun 23 05:49:20 PM PDT 24
Peak memory 206300 kb
Host smart-90c94197-df49-4c05-a9fd-a2cb0ab2b278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352285881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3352285881
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2286079926
Short name T273
Test name
Test status
Simulation time 42676833 ps
CPU time 0.98 seconds
Started Jun 23 05:49:25 PM PDT 24
Finished Jun 23 05:49:26 PM PDT 24
Peak memory 206340 kb
Host smart-dc9b233c-dd8b-4b2f-a268-6e8ebf53b1dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286079926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2286079926
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.100013250
Short name T1080
Test name
Test status
Simulation time 24325930 ps
CPU time 1.66 seconds
Started Jun 23 05:49:18 PM PDT 24
Finished Jun 23 05:49:20 PM PDT 24
Peak memory 214784 kb
Host smart-1e68a4f0-e281-42c0-a3bc-a4c9f2b7765b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100013250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.100013250
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.629913656
Short name T1095
Test name
Test status
Simulation time 89057689 ps
CPU time 2.65 seconds
Started Jun 23 05:49:19 PM PDT 24
Finished Jun 23 05:49:22 PM PDT 24
Peak memory 214680 kb
Host smart-2f60fdd7-18a1-42fd-ac48-9ba15a3b65e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629913656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.629913656
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1047488390
Short name T1004
Test name
Test status
Simulation time 27603057 ps
CPU time 1.33 seconds
Started Jun 23 05:49:20 PM PDT 24
Finished Jun 23 05:49:22 PM PDT 24
Peak memory 214632 kb
Host smart-6ad3c65a-759c-45b6-be7d-6cfca671a222
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047488390 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1047488390
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3539029612
Short name T1077
Test name
Test status
Simulation time 43018951 ps
CPU time 0.88 seconds
Started Jun 23 05:49:21 PM PDT 24
Finished Jun 23 05:49:22 PM PDT 24
Peak memory 206220 kb
Host smart-1db4fefe-1b2b-4eeb-a9cb-0dcee446a921
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539029612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3539029612
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.986008713
Short name T1029
Test name
Test status
Simulation time 15626941 ps
CPU time 0.95 seconds
Started Jun 23 05:49:25 PM PDT 24
Finished Jun 23 05:49:26 PM PDT 24
Peak memory 206252 kb
Host smart-ce023ad9-08df-4f87-ac2d-c000fa4b1796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986008713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.986008713
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.266475330
Short name T1072
Test name
Test status
Simulation time 30582501 ps
CPU time 1.06 seconds
Started Jun 23 05:49:23 PM PDT 24
Finished Jun 23 05:49:24 PM PDT 24
Peak memory 206368 kb
Host smart-ef1e7bb2-9af7-4259-bd1b-2c949d54e440
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266475330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.266475330
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.4010994476
Short name T1037
Test name
Test status
Simulation time 60743081 ps
CPU time 2.45 seconds
Started Jun 23 05:49:24 PM PDT 24
Finished Jun 23 05:49:27 PM PDT 24
Peak memory 214636 kb
Host smart-41232281-40e3-44d9-b06d-8c22d78f04bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010994476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.4010994476
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.4195854750
Short name T289
Test name
Test status
Simulation time 90242976 ps
CPU time 1.62 seconds
Started Jun 23 05:49:24 PM PDT 24
Finished Jun 23 05:49:26 PM PDT 24
Peak memory 214512 kb
Host smart-81a89b2f-b5be-49a3-8e2c-1e7b5966b90d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195854750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.4195854750
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1223418509
Short name T1082
Test name
Test status
Simulation time 49961743 ps
CPU time 1.33 seconds
Started Jun 23 05:49:23 PM PDT 24
Finished Jun 23 05:49:24 PM PDT 24
Peak memory 214628 kb
Host smart-4cdf4843-03d6-463c-af10-f213a6461ce1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223418509 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1223418509
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1700199442
Short name T266
Test name
Test status
Simulation time 13002671 ps
CPU time 0.87 seconds
Started Jun 23 05:49:16 PM PDT 24
Finished Jun 23 05:49:17 PM PDT 24
Peak memory 206176 kb
Host smart-f9669ea9-f412-4861-8a49-0e2337226138
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700199442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1700199442
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2302123548
Short name T1073
Test name
Test status
Simulation time 15086621 ps
CPU time 0.9 seconds
Started Jun 23 05:49:19 PM PDT 24
Finished Jun 23 05:49:21 PM PDT 24
Peak memory 206300 kb
Host smart-c0d99134-5b7b-4b1d-b45d-6c796e7aaf67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302123548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2302123548
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.471044666
Short name T1075
Test name
Test status
Simulation time 643440597 ps
CPU time 1.81 seconds
Started Jun 23 05:49:18 PM PDT 24
Finished Jun 23 05:49:20 PM PDT 24
Peak memory 206296 kb
Host smart-e941661e-e3bb-4b0f-8e49-2f0db1dda02e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471044666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.471044666
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1954375825
Short name T1060
Test name
Test status
Simulation time 47831292 ps
CPU time 2 seconds
Started Jun 23 05:49:24 PM PDT 24
Finished Jun 23 05:49:26 PM PDT 24
Peak memory 214640 kb
Host smart-b8baf1b3-dd1e-496a-9ee8-5ff043ad9f40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954375825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1954375825
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3820859850
Short name T1128
Test name
Test status
Simulation time 960011896 ps
CPU time 2.27 seconds
Started Jun 23 05:49:20 PM PDT 24
Finished Jun 23 05:49:23 PM PDT 24
Peak memory 206360 kb
Host smart-e010a0f6-c8c8-4060-bc22-bd84e56a7bfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820859850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3820859850
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2249916169
Short name T1047
Test name
Test status
Simulation time 36846860 ps
CPU time 1.11 seconds
Started Jun 23 05:49:18 PM PDT 24
Finished Jun 23 05:49:19 PM PDT 24
Peak memory 214628 kb
Host smart-186aeeb0-bca2-4330-abfe-14fe50e29e24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249916169 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2249916169
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.791351853
Short name T1102
Test name
Test status
Simulation time 32392121 ps
CPU time 0.77 seconds
Started Jun 23 05:49:18 PM PDT 24
Finished Jun 23 05:49:20 PM PDT 24
Peak memory 206376 kb
Host smart-98c4eff3-1fbd-4dd0-9bb0-863c4095034d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791351853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.791351853
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1314043066
Short name T1049
Test name
Test status
Simulation time 117703306 ps
CPU time 1.45 seconds
Started Jun 23 05:49:21 PM PDT 24
Finished Jun 23 05:49:22 PM PDT 24
Peak memory 206384 kb
Host smart-6f8194d8-81a6-4730-88af-cdafad985e79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314043066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1314043066
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3267094646
Short name T1000
Test name
Test status
Simulation time 137064044 ps
CPU time 2.79 seconds
Started Jun 23 05:49:17 PM PDT 24
Finished Jun 23 05:49:20 PM PDT 24
Peak memory 214744 kb
Host smart-0cb11c96-061b-4f48-a1b0-ca45ea3aaaea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267094646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3267094646
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3626604915
Short name T1038
Test name
Test status
Simulation time 173494111 ps
CPU time 2.29 seconds
Started Jun 23 05:49:19 PM PDT 24
Finished Jun 23 05:49:22 PM PDT 24
Peak memory 206456 kb
Host smart-00138c7a-0eb1-48c7-aaa8-8c366fb9ed93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626604915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3626604915
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.867812395
Short name T1059
Test name
Test status
Simulation time 26254870 ps
CPU time 1.03 seconds
Started Jun 23 05:49:23 PM PDT 24
Finished Jun 23 05:49:25 PM PDT 24
Peak memory 214636 kb
Host smart-4f49d3d7-63e1-43b0-b632-cc1925651093
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867812395 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.867812395
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3375522537
Short name T1121
Test name
Test status
Simulation time 14671809 ps
CPU time 0.94 seconds
Started Jun 23 05:49:26 PM PDT 24
Finished Jun 23 05:49:28 PM PDT 24
Peak memory 206292 kb
Host smart-1771e288-6c7e-4d4a-8a2b-dee363d6faa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375522537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3375522537
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1555130898
Short name T1117
Test name
Test status
Simulation time 18713243 ps
CPU time 0.93 seconds
Started Jun 23 05:49:25 PM PDT 24
Finished Jun 23 05:49:27 PM PDT 24
Peak memory 206300 kb
Host smart-e494d9da-57c5-4258-b04a-7861fae7b9ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555130898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1555130898
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.913293841
Short name T270
Test name
Test status
Simulation time 140096288 ps
CPU time 1.12 seconds
Started Jun 23 05:49:22 PM PDT 24
Finished Jun 23 05:49:24 PM PDT 24
Peak memory 206376 kb
Host smart-3dd485db-cf9c-4961-8c7a-f533342ddbc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913293841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.913293841
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.4279556550
Short name T1008
Test name
Test status
Simulation time 388133038 ps
CPU time 2.65 seconds
Started Jun 23 05:49:20 PM PDT 24
Finished Jun 23 05:49:23 PM PDT 24
Peak memory 214628 kb
Host smart-0b63923a-b7e5-4617-bbd5-79b974b555b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279556550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.4279556550
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1051983443
Short name T1057
Test name
Test status
Simulation time 63448719 ps
CPU time 1.22 seconds
Started Jun 23 05:49:24 PM PDT 24
Finished Jun 23 05:49:26 PM PDT 24
Peak memory 214696 kb
Host smart-bf5a6b5d-7ce6-4b7f-8803-a417ab8cd4e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051983443 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1051983443
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.635355131
Short name T254
Test name
Test status
Simulation time 45459698 ps
CPU time 0.85 seconds
Started Jun 23 05:49:25 PM PDT 24
Finished Jun 23 05:49:26 PM PDT 24
Peak memory 206288 kb
Host smart-998d64ba-1b18-458e-bfc7-d1a0d46d890e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635355131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.635355131
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.737351586
Short name T1041
Test name
Test status
Simulation time 21587528 ps
CPU time 0.82 seconds
Started Jun 23 05:49:23 PM PDT 24
Finished Jun 23 05:49:24 PM PDT 24
Peak memory 206468 kb
Host smart-3304d195-98b6-4297-8a36-f2dd5ef1bc86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737351586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.737351586
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3310573892
Short name T257
Test name
Test status
Simulation time 89215737 ps
CPU time 1.02 seconds
Started Jun 23 05:49:22 PM PDT 24
Finished Jun 23 05:49:24 PM PDT 24
Peak memory 206508 kb
Host smart-4f45d0aa-8aa2-4d19-978d-aeb51dbdff1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310573892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3310573892
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.624282243
Short name T1081
Test name
Test status
Simulation time 122551788 ps
CPU time 2.42 seconds
Started Jun 23 05:49:23 PM PDT 24
Finished Jun 23 05:49:26 PM PDT 24
Peak memory 214544 kb
Host smart-78108dec-cdaa-4fa3-9a24-e93398466a17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624282243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.624282243
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2153811956
Short name T290
Test name
Test status
Simulation time 50493696 ps
CPU time 1.75 seconds
Started Jun 23 05:49:25 PM PDT 24
Finished Jun 23 05:49:27 PM PDT 24
Peak memory 214728 kb
Host smart-0a992cbe-de30-4b91-9c0f-5da144206d38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153811956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2153811956
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.436861000
Short name T1096
Test name
Test status
Simulation time 70776180 ps
CPU time 1.32 seconds
Started Jun 23 05:49:21 PM PDT 24
Finished Jun 23 05:49:23 PM PDT 24
Peak memory 214604 kb
Host smart-9d2b58d9-3549-47da-bf7f-7fb516edccc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436861000 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.436861000
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.404937820
Short name T1055
Test name
Test status
Simulation time 97892848 ps
CPU time 0.9 seconds
Started Jun 23 05:49:23 PM PDT 24
Finished Jun 23 05:49:24 PM PDT 24
Peak memory 206212 kb
Host smart-4658c774-13bb-4d79-a881-484710a2b55c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404937820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.404937820
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3731043316
Short name T1126
Test name
Test status
Simulation time 29043789 ps
CPU time 0.81 seconds
Started Jun 23 05:49:26 PM PDT 24
Finished Jun 23 05:49:27 PM PDT 24
Peak memory 206212 kb
Host smart-b27d3ec8-27fa-43c8-b478-c5da374c4ce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731043316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3731043316
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1636414729
Short name T1045
Test name
Test status
Simulation time 44875408 ps
CPU time 1.16 seconds
Started Jun 23 05:49:21 PM PDT 24
Finished Jun 23 05:49:23 PM PDT 24
Peak memory 206296 kb
Host smart-9a7acc0c-36da-4b5d-b679-a32a5ca3f73d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636414729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1636414729
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1195196011
Short name T1020
Test name
Test status
Simulation time 57311966 ps
CPU time 2.26 seconds
Started Jun 23 05:49:27 PM PDT 24
Finished Jun 23 05:49:30 PM PDT 24
Peak memory 214520 kb
Host smart-b3db8870-e76f-4b85-9c94-d1acbc26e360
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195196011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1195196011
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.441949939
Short name T1050
Test name
Test status
Simulation time 80872686 ps
CPU time 1.54 seconds
Started Jun 23 05:49:21 PM PDT 24
Finished Jun 23 05:49:23 PM PDT 24
Peak memory 206420 kb
Host smart-4d4c23fb-85db-41da-b409-5ec582bdb66f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441949939 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.441949939
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2118477877
Short name T261
Test name
Test status
Simulation time 22275090 ps
CPU time 1.26 seconds
Started Jun 23 05:49:05 PM PDT 24
Finished Jun 23 05:49:07 PM PDT 24
Peak memory 206316 kb
Host smart-848ab6fc-9f7f-4792-b491-e151b6a9a22b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118477877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2118477877
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.98045761
Short name T262
Test name
Test status
Simulation time 129402351 ps
CPU time 2.07 seconds
Started Jun 23 05:49:05 PM PDT 24
Finished Jun 23 05:49:08 PM PDT 24
Peak memory 206400 kb
Host smart-d90fe33a-01b6-410c-8e7b-81f2ef9ece07
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98045761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.98045761
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2575534541
Short name T1022
Test name
Test status
Simulation time 49078187 ps
CPU time 0.87 seconds
Started Jun 23 05:49:05 PM PDT 24
Finished Jun 23 05:49:06 PM PDT 24
Peak memory 206308 kb
Host smart-5c12faf1-f8e1-44ca-a4de-400545484ea3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575534541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2575534541
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3387500177
Short name T1042
Test name
Test status
Simulation time 42727613 ps
CPU time 1.19 seconds
Started Jun 23 05:49:03 PM PDT 24
Finished Jun 23 05:49:05 PM PDT 24
Peak memory 214604 kb
Host smart-30981242-6a0e-4147-9b25-05bc11946bd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387500177 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3387500177
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3601979542
Short name T1130
Test name
Test status
Simulation time 61658974 ps
CPU time 0.95 seconds
Started Jun 23 05:49:06 PM PDT 24
Finished Jun 23 05:49:08 PM PDT 24
Peak memory 206300 kb
Host smart-10c46250-7b8e-4c21-b399-412143f147eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601979542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3601979542
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2304544819
Short name T1002
Test name
Test status
Simulation time 22445764 ps
CPU time 0.91 seconds
Started Jun 23 05:49:05 PM PDT 24
Finished Jun 23 05:49:06 PM PDT 24
Peak memory 206232 kb
Host smart-c4d22e0e-522f-4749-8d1e-8983d053edaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304544819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2304544819
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3106148747
Short name T276
Test name
Test status
Simulation time 130841391 ps
CPU time 1.4 seconds
Started Jun 23 05:49:06 PM PDT 24
Finished Jun 23 05:49:08 PM PDT 24
Peak memory 206336 kb
Host smart-55f93af5-5fd1-46cf-945b-a3368da0d56c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106148747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3106148747
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.945442239
Short name T1009
Test name
Test status
Simulation time 129329694 ps
CPU time 4.28 seconds
Started Jun 23 05:49:07 PM PDT 24
Finished Jun 23 05:49:12 PM PDT 24
Peak memory 214588 kb
Host smart-b7f92872-1be7-4cd4-9c76-185f465f74fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945442239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.945442239
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3568114172
Short name T1027
Test name
Test status
Simulation time 78412038 ps
CPU time 1.65 seconds
Started Jun 23 05:49:04 PM PDT 24
Finished Jun 23 05:49:05 PM PDT 24
Peak memory 206352 kb
Host smart-bd0c7f71-7691-41c8-b103-d91f5e0c9a29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568114172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3568114172
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3663002272
Short name T1129
Test name
Test status
Simulation time 88802776 ps
CPU time 0.82 seconds
Started Jun 23 05:49:22 PM PDT 24
Finished Jun 23 05:49:23 PM PDT 24
Peak memory 206092 kb
Host smart-66f5d865-3b36-4a71-ac8d-9dedc5b82541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663002272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3663002272
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2564484185
Short name T1019
Test name
Test status
Simulation time 103075472 ps
CPU time 0.81 seconds
Started Jun 23 05:49:25 PM PDT 24
Finished Jun 23 05:49:26 PM PDT 24
Peak memory 206292 kb
Host smart-2890ba31-413f-47af-962e-14ed14906d24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564484185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2564484185
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3332544417
Short name T1098
Test name
Test status
Simulation time 23056027 ps
CPU time 0.86 seconds
Started Jun 23 05:49:24 PM PDT 24
Finished Jun 23 05:49:25 PM PDT 24
Peak memory 206268 kb
Host smart-1f2a9377-ba57-48f1-be82-3b3d288ba489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332544417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3332544417
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1284218225
Short name T1065
Test name
Test status
Simulation time 18663302 ps
CPU time 0.99 seconds
Started Jun 23 05:49:28 PM PDT 24
Finished Jun 23 05:49:29 PM PDT 24
Peak memory 206304 kb
Host smart-21d93e21-ac0a-4b1e-b4ac-8be211868378
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284218225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1284218225
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2257273650
Short name T1090
Test name
Test status
Simulation time 12376434 ps
CPU time 0.81 seconds
Started Jun 23 05:49:31 PM PDT 24
Finished Jun 23 05:49:33 PM PDT 24
Peak memory 206288 kb
Host smart-fca8912d-ffb3-428f-a6e1-19196a4c377e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257273650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2257273650
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1196028638
Short name T1024
Test name
Test status
Simulation time 20073822 ps
CPU time 0.95 seconds
Started Jun 23 05:49:28 PM PDT 24
Finished Jun 23 05:49:29 PM PDT 24
Peak memory 206308 kb
Host smart-958d0eb3-ab5c-4f68-8b5b-0ba66ae6f6ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196028638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1196028638
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1696112389
Short name T1108
Test name
Test status
Simulation time 22379357 ps
CPU time 0.93 seconds
Started Jun 23 05:49:28 PM PDT 24
Finished Jun 23 05:49:29 PM PDT 24
Peak memory 206304 kb
Host smart-f901ee78-9c74-4347-8040-39c4eabd9313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696112389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1696112389
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.125267048
Short name T1067
Test name
Test status
Simulation time 15904083 ps
CPU time 0.9 seconds
Started Jun 23 05:49:31 PM PDT 24
Finished Jun 23 05:49:33 PM PDT 24
Peak memory 206284 kb
Host smart-ebe425b5-56dc-4fc5-85a7-7733a16b4b9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125267048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.125267048
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.412846583
Short name T1056
Test name
Test status
Simulation time 48807345 ps
CPU time 0.86 seconds
Started Jun 23 05:49:29 PM PDT 24
Finished Jun 23 05:49:31 PM PDT 24
Peak memory 206300 kb
Host smart-5bf21453-d4ec-4f82-924d-bebb8685ae69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412846583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.412846583
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2185754827
Short name T1105
Test name
Test status
Simulation time 21262843 ps
CPU time 0.84 seconds
Started Jun 23 05:49:32 PM PDT 24
Finished Jun 23 05:49:34 PM PDT 24
Peak memory 206304 kb
Host smart-0c300390-0047-40dd-aae8-ff8473f5e821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185754827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2185754827
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3457578114
Short name T255
Test name
Test status
Simulation time 225867465 ps
CPU time 1.2 seconds
Started Jun 23 05:49:14 PM PDT 24
Finished Jun 23 05:49:16 PM PDT 24
Peak memory 206300 kb
Host smart-bb1dc4c4-8591-4a9a-8746-64ab25b7c6bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457578114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3457578114
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3625578350
Short name T1099
Test name
Test status
Simulation time 475403122 ps
CPU time 3.25 seconds
Started Jun 23 05:49:07 PM PDT 24
Finished Jun 23 05:49:11 PM PDT 24
Peak memory 206212 kb
Host smart-5e708cf1-0f56-4de2-81c9-05cf56a2049e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625578350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3625578350
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2087497695
Short name T260
Test name
Test status
Simulation time 28242153 ps
CPU time 0.93 seconds
Started Jun 23 05:49:06 PM PDT 24
Finished Jun 23 05:49:07 PM PDT 24
Peak memory 206272 kb
Host smart-afc077b2-8dc8-4c8f-a5e0-9e18bcc159df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087497695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2087497695
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3097445878
Short name T1023
Test name
Test status
Simulation time 54188848 ps
CPU time 1.13 seconds
Started Jun 23 05:49:09 PM PDT 24
Finished Jun 23 05:49:10 PM PDT 24
Peak memory 214604 kb
Host smart-209f4975-11b3-4210-b68c-e195cec85f71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097445878 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3097445878
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.130270639
Short name T256
Test name
Test status
Simulation time 41158751 ps
CPU time 0.82 seconds
Started Jun 23 05:49:06 PM PDT 24
Finished Jun 23 05:49:07 PM PDT 24
Peak memory 206248 kb
Host smart-9cacbc78-4bd2-4e46-bbac-7df17946796f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130270639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.130270639
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.196203855
Short name T1068
Test name
Test status
Simulation time 26524705 ps
CPU time 0.92 seconds
Started Jun 23 05:49:02 PM PDT 24
Finished Jun 23 05:49:04 PM PDT 24
Peak memory 206272 kb
Host smart-a8523833-225d-4c7c-93fa-d70421018088
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196203855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.196203855
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3343983203
Short name T274
Test name
Test status
Simulation time 118332203 ps
CPU time 1.17 seconds
Started Jun 23 05:49:08 PM PDT 24
Finished Jun 23 05:49:10 PM PDT 24
Peak memory 206388 kb
Host smart-0e585977-319f-4bbe-b30c-3e872a5dbe74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343983203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3343983203
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1259800501
Short name T1043
Test name
Test status
Simulation time 126115303 ps
CPU time 2.61 seconds
Started Jun 23 05:49:05 PM PDT 24
Finished Jun 23 05:49:09 PM PDT 24
Peak memory 214660 kb
Host smart-ac1aaad9-4359-4a27-8ed4-d9d3d201da58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259800501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1259800501
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1858341716
Short name T1110
Test name
Test status
Simulation time 188103386 ps
CPU time 3.58 seconds
Started Jun 23 05:49:04 PM PDT 24
Finished Jun 23 05:49:08 PM PDT 24
Peak memory 206420 kb
Host smart-7f81793a-be60-4070-b030-12ccc79b5a70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858341716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1858341716
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.4211162838
Short name T1119
Test name
Test status
Simulation time 28503806 ps
CPU time 0.81 seconds
Started Jun 23 05:49:29 PM PDT 24
Finished Jun 23 05:49:30 PM PDT 24
Peak memory 206300 kb
Host smart-e79fe4fd-3aa2-4c04-bc72-e102f900f8fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211162838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.4211162838
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.910754410
Short name T1066
Test name
Test status
Simulation time 26382458 ps
CPU time 0.83 seconds
Started Jun 23 05:49:30 PM PDT 24
Finished Jun 23 05:49:31 PM PDT 24
Peak memory 206304 kb
Host smart-cc841fcd-7a73-4836-b16f-1ee537660d13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910754410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.910754410
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2552691030
Short name T1106
Test name
Test status
Simulation time 65754255 ps
CPU time 0.8 seconds
Started Jun 23 05:49:30 PM PDT 24
Finished Jun 23 05:49:31 PM PDT 24
Peak memory 206208 kb
Host smart-ebf114c1-c000-4aa6-996a-44526b12f069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552691030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2552691030
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.182873274
Short name T1005
Test name
Test status
Simulation time 40519041 ps
CPU time 0.78 seconds
Started Jun 23 05:49:29 PM PDT 24
Finished Jun 23 05:49:30 PM PDT 24
Peak memory 206164 kb
Host smart-6dfc4fca-803b-49ac-8743-d4c4f210b065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182873274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.182873274
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3644160220
Short name T1074
Test name
Test status
Simulation time 16296595 ps
CPU time 0.78 seconds
Started Jun 23 05:49:28 PM PDT 24
Finished Jun 23 05:49:29 PM PDT 24
Peak memory 206088 kb
Host smart-3441dd17-5281-4fd0-942e-1bde1109fe31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644160220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3644160220
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2220562202
Short name T1111
Test name
Test status
Simulation time 36836558 ps
CPU time 0.83 seconds
Started Jun 23 05:49:33 PM PDT 24
Finished Jun 23 05:49:34 PM PDT 24
Peak memory 206180 kb
Host smart-feccad9d-1216-4e74-bd5f-f91cb68ca670
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220562202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2220562202
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3493638126
Short name T1079
Test name
Test status
Simulation time 52906136 ps
CPU time 0.84 seconds
Started Jun 23 05:49:36 PM PDT 24
Finished Jun 23 05:49:37 PM PDT 24
Peak memory 206208 kb
Host smart-b66f9ca6-d5d2-454c-abb1-7a73fa7b2f18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493638126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3493638126
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1298369482
Short name T1092
Test name
Test status
Simulation time 63910169 ps
CPU time 0.9 seconds
Started Jun 23 05:49:32 PM PDT 24
Finished Jun 23 05:49:33 PM PDT 24
Peak memory 206224 kb
Host smart-3058c3bb-08a7-4b7f-b193-c7f33ee3df8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298369482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1298369482
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1378269059
Short name T1018
Test name
Test status
Simulation time 38955745 ps
CPU time 0.81 seconds
Started Jun 23 05:49:31 PM PDT 24
Finished Jun 23 05:49:33 PM PDT 24
Peak memory 206212 kb
Host smart-ea4acb98-5182-4393-8de4-ff7817534c65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378269059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1378269059
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3317826751
Short name T1003
Test name
Test status
Simulation time 84755874 ps
CPU time 0.89 seconds
Started Jun 23 05:49:29 PM PDT 24
Finished Jun 23 05:49:30 PM PDT 24
Peak memory 206280 kb
Host smart-c1163069-0a0f-4f78-afc4-14f4de79e16a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317826751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3317826751
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2565689552
Short name T1010
Test name
Test status
Simulation time 27753991 ps
CPU time 1.24 seconds
Started Jun 23 05:49:11 PM PDT 24
Finished Jun 23 05:49:13 PM PDT 24
Peak memory 206300 kb
Host smart-d6a5c00d-1738-4301-a1e6-6455a21887ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565689552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2565689552
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4194848818
Short name T267
Test name
Test status
Simulation time 64040090 ps
CPU time 3.25 seconds
Started Jun 23 05:49:13 PM PDT 24
Finished Jun 23 05:49:17 PM PDT 24
Peak memory 206252 kb
Host smart-8037d340-f368-4766-8d07-f21da6a29fbf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194848818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.4194848818
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2472405577
Short name T264
Test name
Test status
Simulation time 19778532 ps
CPU time 0.99 seconds
Started Jun 23 05:49:14 PM PDT 24
Finished Jun 23 05:49:15 PM PDT 24
Peak memory 206276 kb
Host smart-716ade66-f8b6-4b9d-b65b-5740d2258bcc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472405577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2472405577
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3241785883
Short name T1044
Test name
Test status
Simulation time 31540060 ps
CPU time 1.46 seconds
Started Jun 23 05:49:13 PM PDT 24
Finished Jun 23 05:49:15 PM PDT 24
Peak memory 217508 kb
Host smart-3ce40890-ad0f-444c-917c-4d8bd2b66732
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241785883 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3241785883
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2066819222
Short name T1040
Test name
Test status
Simulation time 42468365 ps
CPU time 0.83 seconds
Started Jun 23 05:49:08 PM PDT 24
Finished Jun 23 05:49:10 PM PDT 24
Peak memory 206356 kb
Host smart-59bf99a1-04ab-4d0e-8d83-7026361072be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066819222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2066819222
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2917417028
Short name T1026
Test name
Test status
Simulation time 13227376 ps
CPU time 0.81 seconds
Started Jun 23 05:49:09 PM PDT 24
Finished Jun 23 05:49:11 PM PDT 24
Peak memory 206272 kb
Host smart-ded0176b-8842-41c0-994e-aa8817d786b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917417028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2917417028
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.228631064
Short name T1088
Test name
Test status
Simulation time 35126339 ps
CPU time 1.46 seconds
Started Jun 23 05:49:11 PM PDT 24
Finished Jun 23 05:49:13 PM PDT 24
Peak memory 206312 kb
Host smart-fbbaac5a-732f-4363-b65d-1dce44469673
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228631064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.228631064
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1281295251
Short name T1116
Test name
Test status
Simulation time 46262154 ps
CPU time 1.96 seconds
Started Jun 23 05:49:09 PM PDT 24
Finished Jun 23 05:49:11 PM PDT 24
Peak memory 214668 kb
Host smart-62cf989b-3c61-49f3-91aa-c2154151e433
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281295251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1281295251
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.675769726
Short name T287
Test name
Test status
Simulation time 131640495 ps
CPU time 1.54 seconds
Started Jun 23 05:49:08 PM PDT 24
Finished Jun 23 05:49:11 PM PDT 24
Peak memory 206444 kb
Host smart-18b7d654-adf5-446d-b5f8-9509bf836df4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675769726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.675769726
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2626382310
Short name T1069
Test name
Test status
Simulation time 51818585 ps
CPU time 0.84 seconds
Started Jun 23 05:49:30 PM PDT 24
Finished Jun 23 05:49:32 PM PDT 24
Peak memory 206304 kb
Host smart-b3a6dff8-2af3-4762-a680-365b43925002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626382310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2626382310
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.820078208
Short name T1094
Test name
Test status
Simulation time 50024160 ps
CPU time 0.93 seconds
Started Jun 23 05:49:30 PM PDT 24
Finished Jun 23 05:49:31 PM PDT 24
Peak memory 206288 kb
Host smart-a5c60a16-0e82-4d13-a2da-95b5f9ea5486
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820078208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.820078208
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3916144447
Short name T1052
Test name
Test status
Simulation time 54254785 ps
CPU time 0.83 seconds
Started Jun 23 05:49:32 PM PDT 24
Finished Jun 23 05:49:33 PM PDT 24
Peak memory 206184 kb
Host smart-47f5ef01-9476-4908-b821-2ff27ce1ea14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916144447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3916144447
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.84048179
Short name T1006
Test name
Test status
Simulation time 30943597 ps
CPU time 0.93 seconds
Started Jun 23 05:49:30 PM PDT 24
Finished Jun 23 05:49:32 PM PDT 24
Peak memory 206292 kb
Host smart-f6ae6b50-bad4-412f-846c-6c0160e32e05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84048179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.84048179
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2685359991
Short name T1053
Test name
Test status
Simulation time 42578138 ps
CPU time 0.83 seconds
Started Jun 23 05:49:30 PM PDT 24
Finished Jun 23 05:49:31 PM PDT 24
Peak memory 206208 kb
Host smart-203d4509-6fa1-4d51-8778-9d79de9a8470
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685359991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2685359991
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2047913749
Short name T1115
Test name
Test status
Simulation time 20348335 ps
CPU time 0.93 seconds
Started Jun 23 05:49:30 PM PDT 24
Finished Jun 23 05:49:32 PM PDT 24
Peak memory 206308 kb
Host smart-8599e137-4aa8-4277-af4f-3eed790f3806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047913749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2047913749
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2482763730
Short name T1112
Test name
Test status
Simulation time 17821787 ps
CPU time 0.98 seconds
Started Jun 23 05:49:31 PM PDT 24
Finished Jun 23 05:49:32 PM PDT 24
Peak memory 206188 kb
Host smart-d07734bf-f1e5-43ba-b409-e25d41549278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482763730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2482763730
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2611238328
Short name T1062
Test name
Test status
Simulation time 44241504 ps
CPU time 0.9 seconds
Started Jun 23 05:49:30 PM PDT 24
Finished Jun 23 05:49:31 PM PDT 24
Peak memory 206272 kb
Host smart-cf20579b-f68a-4f89-89a7-f4461acccdaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611238328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2611238328
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.522373894
Short name T1035
Test name
Test status
Simulation time 14568325 ps
CPU time 0.91 seconds
Started Jun 23 05:49:31 PM PDT 24
Finished Jun 23 05:49:32 PM PDT 24
Peak memory 206184 kb
Host smart-65f4fb30-eed8-48af-bb53-9510e87fc17c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522373894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.522373894
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.421474778
Short name T1001
Test name
Test status
Simulation time 44210863 ps
CPU time 0.81 seconds
Started Jun 23 05:49:32 PM PDT 24
Finished Jun 23 05:49:33 PM PDT 24
Peak memory 206224 kb
Host smart-14575d6c-dde1-4cc6-9b1d-bbdd3f44324b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421474778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.421474778
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.770016560
Short name T1014
Test name
Test status
Simulation time 84131201 ps
CPU time 1.02 seconds
Started Jun 23 05:49:11 PM PDT 24
Finished Jun 23 05:49:12 PM PDT 24
Peak memory 206404 kb
Host smart-524d37d7-68b0-4845-88c8-716123de5cb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770016560 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.770016560
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2639867821
Short name T275
Test name
Test status
Simulation time 23894611 ps
CPU time 0.88 seconds
Started Jun 23 05:49:11 PM PDT 24
Finished Jun 23 05:49:13 PM PDT 24
Peak memory 206296 kb
Host smart-113781bb-90ba-4119-8474-b13dc6ced9a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639867821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2639867821
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2131557583
Short name T1071
Test name
Test status
Simulation time 37224988 ps
CPU time 0.83 seconds
Started Jun 23 05:49:12 PM PDT 24
Finished Jun 23 05:49:13 PM PDT 24
Peak memory 206212 kb
Host smart-67564929-96c0-47f9-8f47-1bdcfb077d85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131557583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2131557583
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.468486575
Short name T271
Test name
Test status
Simulation time 25909172 ps
CPU time 1.12 seconds
Started Jun 23 05:49:07 PM PDT 24
Finished Jun 23 05:49:09 PM PDT 24
Peak memory 206344 kb
Host smart-81d324fb-7e89-4531-9aae-1e45e3b9277c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468486575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.468486575
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3764056542
Short name T1084
Test name
Test status
Simulation time 92738092 ps
CPU time 2.89 seconds
Started Jun 23 05:49:12 PM PDT 24
Finished Jun 23 05:49:16 PM PDT 24
Peak memory 214648 kb
Host smart-305c2f38-b140-436f-98e2-1f3d3eda357e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764056542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3764056542
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2605285933
Short name T1107
Test name
Test status
Simulation time 181469022 ps
CPU time 3.88 seconds
Started Jun 23 05:49:14 PM PDT 24
Finished Jun 23 05:49:19 PM PDT 24
Peak memory 206576 kb
Host smart-85eeecaa-b0a8-465c-aa9d-9a655c0b4974
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605285933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2605285933
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.936191612
Short name T1120
Test name
Test status
Simulation time 22189169 ps
CPU time 1.19 seconds
Started Jun 23 05:49:14 PM PDT 24
Finished Jun 23 05:49:16 PM PDT 24
Peak memory 216464 kb
Host smart-342d5516-bd6e-48df-bd80-3e2da716405d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936191612 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.936191612
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2794376351
Short name T263
Test name
Test status
Simulation time 14856958 ps
CPU time 0.98 seconds
Started Jun 23 05:49:12 PM PDT 24
Finished Jun 23 05:49:13 PM PDT 24
Peak memory 206300 kb
Host smart-f987b282-5c4d-4853-bc76-7c2d3f93b589
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794376351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2794376351
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3070505798
Short name T1063
Test name
Test status
Simulation time 15342880 ps
CPU time 0.93 seconds
Started Jun 23 05:49:11 PM PDT 24
Finished Jun 23 05:49:12 PM PDT 24
Peak memory 206300 kb
Host smart-c30cbe75-9cc5-4f65-b0ab-d069d91831fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070505798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3070505798
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2131388585
Short name T1034
Test name
Test status
Simulation time 35712007 ps
CPU time 1.12 seconds
Started Jun 23 05:49:09 PM PDT 24
Finished Jun 23 05:49:11 PM PDT 24
Peak memory 206452 kb
Host smart-b513313e-8414-4d04-9f1c-c4e9aeaab771
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131388585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2131388585
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3326493569
Short name T1093
Test name
Test status
Simulation time 127665716 ps
CPU time 2.02 seconds
Started Jun 23 05:49:14 PM PDT 24
Finished Jun 23 05:49:17 PM PDT 24
Peak memory 214708 kb
Host smart-4b6e59fe-7f0b-4ef5-9715-2c3fab717484
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326493569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3326493569
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3531132361
Short name T286
Test name
Test status
Simulation time 47655361 ps
CPU time 1.63 seconds
Started Jun 23 05:49:10 PM PDT 24
Finished Jun 23 05:49:12 PM PDT 24
Peak memory 206504 kb
Host smart-551c3fbc-c2fd-4f3b-bc87-602caf929f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531132361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3531132361
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3481833870
Short name T1013
Test name
Test status
Simulation time 120581791 ps
CPU time 1.15 seconds
Started Jun 23 05:49:08 PM PDT 24
Finished Jun 23 05:49:10 PM PDT 24
Peak memory 214552 kb
Host smart-00f5bef6-587f-4bab-980c-bf698e32d014
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481833870 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3481833870
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1496290739
Short name T1039
Test name
Test status
Simulation time 19649106 ps
CPU time 0.97 seconds
Started Jun 23 05:49:14 PM PDT 24
Finished Jun 23 05:49:15 PM PDT 24
Peak memory 206268 kb
Host smart-9a482af1-50c9-4a02-8d06-0e6f608473d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496290739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1496290739
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.4213183015
Short name T1028
Test name
Test status
Simulation time 49305450 ps
CPU time 0.82 seconds
Started Jun 23 05:49:14 PM PDT 24
Finished Jun 23 05:49:16 PM PDT 24
Peak memory 206204 kb
Host smart-78f162f3-5049-44ef-a0ae-d88ce74a8f18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213183015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.4213183015
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3771459474
Short name T1127
Test name
Test status
Simulation time 34256926 ps
CPU time 1.45 seconds
Started Jun 23 05:49:11 PM PDT 24
Finished Jun 23 05:49:12 PM PDT 24
Peak memory 206360 kb
Host smart-27614c95-c4d8-404c-841f-c8906b1ea9b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771459474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3771459474
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1283476871
Short name T1085
Test name
Test status
Simulation time 557387108 ps
CPU time 3.43 seconds
Started Jun 23 05:49:09 PM PDT 24
Finished Jun 23 05:49:13 PM PDT 24
Peak memory 214648 kb
Host smart-b9f6406a-9eb1-4b45-b7ea-cb9c032f622a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283476871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1283476871
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1204309770
Short name T1061
Test name
Test status
Simulation time 211916768 ps
CPU time 4.46 seconds
Started Jun 23 05:49:10 PM PDT 24
Finished Jun 23 05:49:15 PM PDT 24
Peak memory 206368 kb
Host smart-fe65500a-f53f-4eed-8245-9ddb3a990289
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204309770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1204309770
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3636350821
Short name T1100
Test name
Test status
Simulation time 25912913 ps
CPU time 1.22 seconds
Started Jun 23 05:49:12 PM PDT 24
Finished Jun 23 05:49:14 PM PDT 24
Peak memory 214664 kb
Host smart-c31e56a2-de2b-4ee7-ba9b-bfd3997a8d8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636350821 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3636350821
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.533077255
Short name T1089
Test name
Test status
Simulation time 63706995 ps
CPU time 0.85 seconds
Started Jun 23 05:49:12 PM PDT 24
Finished Jun 23 05:49:14 PM PDT 24
Peak memory 206292 kb
Host smart-587e91c9-6b10-4026-8436-abf4890fa193
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533077255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.533077255
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2855495283
Short name T1030
Test name
Test status
Simulation time 13956090 ps
CPU time 0.91 seconds
Started Jun 23 05:49:12 PM PDT 24
Finished Jun 23 05:49:13 PM PDT 24
Peak memory 206300 kb
Host smart-9e6f4742-a2cb-4c44-b0e8-ea19637ef60c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855495283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2855495283
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1943091287
Short name T1118
Test name
Test status
Simulation time 46658015 ps
CPU time 0.98 seconds
Started Jun 23 05:49:14 PM PDT 24
Finished Jun 23 05:49:16 PM PDT 24
Peak memory 206560 kb
Host smart-53b73165-460d-4204-8ca4-e225de3e9120
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943091287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1943091287
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3697941287
Short name T1031
Test name
Test status
Simulation time 223525496 ps
CPU time 2.24 seconds
Started Jun 23 05:49:11 PM PDT 24
Finished Jun 23 05:49:14 PM PDT 24
Peak memory 214892 kb
Host smart-f5c2d37c-7f85-4088-b7b5-6f10047d8c65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697941287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3697941287
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2734809657
Short name T283
Test name
Test status
Simulation time 317923007 ps
CPU time 1.69 seconds
Started Jun 23 05:49:10 PM PDT 24
Finished Jun 23 05:49:12 PM PDT 24
Peak memory 214552 kb
Host smart-4a4b4587-00a8-47bb-8fb4-f049316fccac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734809657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2734809657
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3663757086
Short name T1064
Test name
Test status
Simulation time 20076659 ps
CPU time 1.15 seconds
Started Jun 23 05:49:14 PM PDT 24
Finished Jun 23 05:49:16 PM PDT 24
Peak memory 214556 kb
Host smart-0720448e-e408-464b-a30f-f5e7da46ad31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663757086 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3663757086
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1118509865
Short name T999
Test name
Test status
Simulation time 66179408 ps
CPU time 0.9 seconds
Started Jun 23 05:49:15 PM PDT 24
Finished Jun 23 05:49:16 PM PDT 24
Peak memory 206292 kb
Host smart-637b7e1f-a56a-4dfe-83c5-6aaa0ef15dda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118509865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1118509865
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3747442759
Short name T1058
Test name
Test status
Simulation time 13501300 ps
CPU time 0.9 seconds
Started Jun 23 05:49:14 PM PDT 24
Finished Jun 23 05:49:16 PM PDT 24
Peak memory 206296 kb
Host smart-d981ef93-b4f1-41db-9174-9e4fde8dfd34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747442759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3747442759
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.729222591
Short name T1113
Test name
Test status
Simulation time 37176737 ps
CPU time 0.94 seconds
Started Jun 23 05:49:13 PM PDT 24
Finished Jun 23 05:49:15 PM PDT 24
Peak memory 206356 kb
Host smart-6117fb2d-96e0-4d49-b175-cbba393b5ec4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729222591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.729222591
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1077774387
Short name T1114
Test name
Test status
Simulation time 112296470 ps
CPU time 3.82 seconds
Started Jun 23 05:49:13 PM PDT 24
Finished Jun 23 05:49:18 PM PDT 24
Peak memory 214624 kb
Host smart-13f1f500-2ebe-413f-8fb7-ea45426641fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077774387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1077774387
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1994175829
Short name T281
Test name
Test status
Simulation time 46171281 ps
CPU time 1.67 seconds
Started Jun 23 05:49:13 PM PDT 24
Finished Jun 23 05:49:15 PM PDT 24
Peak memory 214816 kb
Host smart-6c97fd46-f8d2-4626-8451-849eaac9ccd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994175829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1994175829
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.4130931980
Short name T292
Test name
Test status
Simulation time 73265584 ps
CPU time 1.26 seconds
Started Jun 23 05:33:41 PM PDT 24
Finished Jun 23 05:33:43 PM PDT 24
Peak memory 218040 kb
Host smart-c2cc8b75-26b4-4272-a2a7-03951d846d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130931980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.4130931980
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable.915188590
Short name T208
Test name
Test status
Simulation time 13598986 ps
CPU time 0.88 seconds
Started Jun 23 05:33:42 PM PDT 24
Finished Jun 23 05:33:43 PM PDT 24
Peak memory 215824 kb
Host smart-97950c24-a28a-45e8-9d98-2e7c8ea8532d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915188590 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.915188590
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1662455179
Short name T135
Test name
Test status
Simulation time 49410613 ps
CPU time 1.07 seconds
Started Jun 23 05:33:43 PM PDT 24
Finished Jun 23 05:33:44 PM PDT 24
Peak memory 216240 kb
Host smart-932a2791-93c6-494b-896a-05af8b05a979
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662455179 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1662455179
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1738359549
Short name T177
Test name
Test status
Simulation time 32871218 ps
CPU time 0.89 seconds
Started Jun 23 05:33:42 PM PDT 24
Finished Jun 23 05:33:43 PM PDT 24
Peak memory 217756 kb
Host smart-1022600e-5e0d-427f-b114-3170a4365f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738359549 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1738359549
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.184468054
Short name T798
Test name
Test status
Simulation time 76664231 ps
CPU time 1.17 seconds
Started Jun 23 05:33:41 PM PDT 24
Finished Jun 23 05:33:42 PM PDT 24
Peak memory 219340 kb
Host smart-a6df6ea5-eb96-46bf-b718-c43847bd6025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184468054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.184468054
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.2353913008
Short name T454
Test name
Test status
Simulation time 27141891 ps
CPU time 1.04 seconds
Started Jun 23 05:33:45 PM PDT 24
Finished Jun 23 05:33:46 PM PDT 24
Peak memory 223372 kb
Host smart-60ad6e2d-3e3c-4664-8362-3fb83490946d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353913008 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2353913008
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.2760906022
Short name T891
Test name
Test status
Simulation time 81150467 ps
CPU time 0.89 seconds
Started Jun 23 05:33:43 PM PDT 24
Finished Jun 23 05:33:44 PM PDT 24
Peak memory 206444 kb
Host smart-addeb00c-ebad-4ee9-a3b1-1fbafe0a82d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760906022 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2760906022
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2542682670
Short name T19
Test name
Test status
Simulation time 946864826 ps
CPU time 8.07 seconds
Started Jun 23 05:33:40 PM PDT 24
Finished Jun 23 05:33:48 PM PDT 24
Peak memory 236624 kb
Host smart-e1a48ad7-b096-46db-b1d2-9314d0f97036
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542682670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2542682670
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.1572565935
Short name T643
Test name
Test status
Simulation time 34481034 ps
CPU time 0.88 seconds
Started Jun 23 05:33:42 PM PDT 24
Finished Jun 23 05:33:43 PM PDT 24
Peak memory 214640 kb
Host smart-e9b83814-fbff-44b8-a926-e64fa5d19b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572565935 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1572565935
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1110228128
Short name T973
Test name
Test status
Simulation time 118094718 ps
CPU time 2.77 seconds
Started Jun 23 05:33:41 PM PDT 24
Finished Jun 23 05:33:44 PM PDT 24
Peak memory 216516 kb
Host smart-3d6e3310-2cff-489a-8ec5-9f64c8e84297
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110228128 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1110228128
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.103383148
Short name T430
Test name
Test status
Simulation time 83362968363 ps
CPU time 963.02 seconds
Started Jun 23 05:33:40 PM PDT 24
Finished Jun 23 05:49:44 PM PDT 24
Peak memory 221672 kb
Host smart-0ea7e036-4828-41e5-8b2a-8da052ee49d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103383148 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.103383148
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.106916930
Short name T521
Test name
Test status
Simulation time 45843059 ps
CPU time 1.15 seconds
Started Jun 23 05:33:46 PM PDT 24
Finished Jun 23 05:33:47 PM PDT 24
Peak memory 219112 kb
Host smart-faec6d24-1239-4910-89e1-387fe3c3fbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106916930 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.106916930
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.2415845976
Short name T637
Test name
Test status
Simulation time 53534246 ps
CPU time 0.91 seconds
Started Jun 23 05:33:49 PM PDT 24
Finished Jun 23 05:33:51 PM PDT 24
Peak memory 206148 kb
Host smart-2003f570-f5b0-42a0-bd28-ee149f171f6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415845976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2415845976
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.2992508129
Short name T217
Test name
Test status
Simulation time 21827865 ps
CPU time 0.88 seconds
Started Jun 23 05:33:44 PM PDT 24
Finished Jun 23 05:33:45 PM PDT 24
Peak memory 215664 kb
Host smart-42954516-8f26-475e-962e-1a9c6555b368
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992508129 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2992508129
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.1234873078
Short name T472
Test name
Test status
Simulation time 20493385 ps
CPU time 1.12 seconds
Started Jun 23 05:33:48 PM PDT 24
Finished Jun 23 05:33:49 PM PDT 24
Peak memory 219412 kb
Host smart-ecc6fd29-f623-4394-b71f-785285556954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234873078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1234873078
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.4121642131
Short name T665
Test name
Test status
Simulation time 40608776 ps
CPU time 1.43 seconds
Started Jun 23 05:33:51 PM PDT 24
Finished Jun 23 05:33:53 PM PDT 24
Peak memory 217960 kb
Host smart-23c87f35-930e-43fe-9644-7984965ba15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121642131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.4121642131
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.704583478
Short name T27
Test name
Test status
Simulation time 51082948 ps
CPU time 0.85 seconds
Started Jun 23 05:33:52 PM PDT 24
Finished Jun 23 05:33:53 PM PDT 24
Peak memory 206432 kb
Host smart-9a465ff3-bf5e-46ce-9e85-dd64f98125a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704583478 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.704583478
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1303922987
Short name T66
Test name
Test status
Simulation time 604791529 ps
CPU time 9.21 seconds
Started Jun 23 05:33:46 PM PDT 24
Finished Jun 23 05:33:55 PM PDT 24
Peak memory 235688 kb
Host smart-f4f57d9d-7bcf-4af7-b9fa-7cfd18ee29bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303922987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1303922987
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1037772501
Short name T510
Test name
Test status
Simulation time 19828215 ps
CPU time 0.93 seconds
Started Jun 23 05:33:41 PM PDT 24
Finished Jun 23 05:33:43 PM PDT 24
Peak memory 214572 kb
Host smart-1c7a8803-4c14-4cf3-a52a-7099c32d6f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037772501 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1037772501
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1745962066
Short name T871
Test name
Test status
Simulation time 857655786 ps
CPU time 4.97 seconds
Started Jun 23 05:33:49 PM PDT 24
Finished Jun 23 05:33:54 PM PDT 24
Peak memory 214660 kb
Host smart-1f64ad1d-d185-4c4f-8d63-77a216b7b389
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745962066 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1745962066
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1670110096
Short name T862
Test name
Test status
Simulation time 71383211144 ps
CPU time 1777.55 seconds
Started Jun 23 05:33:46 PM PDT 24
Finished Jun 23 06:03:24 PM PDT 24
Peak memory 226440 kb
Host smart-025442d8-c06a-4dc9-82ef-6c700b47c721
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670110096 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1670110096
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3278065419
Short name T63
Test name
Test status
Simulation time 32794180 ps
CPU time 1.28 seconds
Started Jun 23 05:34:08 PM PDT 24
Finished Jun 23 05:34:10 PM PDT 24
Peak memory 215100 kb
Host smart-5b9fea46-7e1f-4075-b6c2-635b31326545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278065419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3278065419
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.1489674648
Short name T766
Test name
Test status
Simulation time 24622208 ps
CPU time 0.82 seconds
Started Jun 23 05:34:16 PM PDT 24
Finished Jun 23 05:34:17 PM PDT 24
Peak memory 205648 kb
Host smart-87c52332-d795-4a76-9862-02f15d89c213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489674648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1489674648
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.906908331
Short name T714
Test name
Test status
Simulation time 31292388 ps
CPU time 0.9 seconds
Started Jun 23 05:34:09 PM PDT 24
Finished Jun 23 05:34:11 PM PDT 24
Peak memory 215692 kb
Host smart-9e33bafc-910b-4005-87fc-cebf0dc6b7be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906908331 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.906908331
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3111391554
Short name T838
Test name
Test status
Simulation time 222477159 ps
CPU time 1.15 seconds
Started Jun 23 05:34:09 PM PDT 24
Finished Jun 23 05:34:11 PM PDT 24
Peak memory 216328 kb
Host smart-cf913484-2d1e-41a7-81e4-2b8a45ad2e69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111391554 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3111391554
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.334013395
Short name T130
Test name
Test status
Simulation time 20906743 ps
CPU time 1.17 seconds
Started Jun 23 05:34:09 PM PDT 24
Finished Jun 23 05:34:11 PM PDT 24
Peak memory 218924 kb
Host smart-7b084644-16c8-4c5b-b256-aa3099d2fb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334013395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.334013395
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2800582878
Short name T705
Test name
Test status
Simulation time 93428257 ps
CPU time 1.24 seconds
Started Jun 23 05:34:13 PM PDT 24
Finished Jun 23 05:34:15 PM PDT 24
Peak memory 213352 kb
Host smart-ae71e8d7-da68-4490-9f8f-cf970380361e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800582878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2800582878
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.1522849509
Short name T866
Test name
Test status
Simulation time 14711634 ps
CPU time 0.95 seconds
Started Jun 23 05:34:09 PM PDT 24
Finished Jun 23 05:34:11 PM PDT 24
Peak memory 214628 kb
Host smart-7f532066-ef4b-41fc-a57b-a2d48cf5eeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522849509 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1522849509
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1792060388
Short name T651
Test name
Test status
Simulation time 856512444 ps
CPU time 3.09 seconds
Started Jun 23 05:34:10 PM PDT 24
Finished Jun 23 05:34:14 PM PDT 24
Peak memory 216328 kb
Host smart-6aef8ddd-714d-4f65-baa1-e56d6354fe3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792060388 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1792060388
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1971210909
Short name T119
Test name
Test status
Simulation time 34212693593 ps
CPU time 240.69 seconds
Started Jun 23 05:34:11 PM PDT 24
Finished Jun 23 05:38:12 PM PDT 24
Peak memory 219560 kb
Host smart-9eee4d6e-f2b8-4605-aea8-ed0326352052
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971210909 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1971210909
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.3235216866
Short name T887
Test name
Test status
Simulation time 156566610 ps
CPU time 1.27 seconds
Started Jun 23 05:36:17 PM PDT 24
Finished Jun 23 05:36:18 PM PDT 24
Peak memory 218960 kb
Host smart-5fad6325-7e3b-422b-8249-653b325eaa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235216866 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.3235216866
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.2315691739
Short name T44
Test name
Test status
Simulation time 125603230 ps
CPU time 1.07 seconds
Started Jun 23 05:36:14 PM PDT 24
Finished Jun 23 05:36:15 PM PDT 24
Peak memory 216584 kb
Host smart-ecf3f643-a689-44bf-843a-ca150447a45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315691739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2315691739
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.307575225
Short name T438
Test name
Test status
Simulation time 93987714 ps
CPU time 1.52 seconds
Started Jun 23 05:36:19 PM PDT 24
Finished Jun 23 05:36:21 PM PDT 24
Peak memory 218256 kb
Host smart-6c1bdd51-eeb6-4dd8-b6e6-c64d982e28cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307575225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.307575225
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.599976096
Short name T199
Test name
Test status
Simulation time 78703686 ps
CPU time 1.13 seconds
Started Jun 23 05:36:19 PM PDT 24
Finished Jun 23 05:36:21 PM PDT 24
Peak memory 218844 kb
Host smart-f0ae9ade-c6b4-4d58-81c0-1593ecd9ae8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599976096 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.599976096
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.3942560406
Short name T243
Test name
Test status
Simulation time 91945580 ps
CPU time 1.22 seconds
Started Jun 23 05:36:16 PM PDT 24
Finished Jun 23 05:36:18 PM PDT 24
Peak memory 218332 kb
Host smart-24a065e0-2812-41bb-b422-939312ca5539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942560406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3942560406
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.2618549255
Short name T522
Test name
Test status
Simulation time 96931501 ps
CPU time 1.25 seconds
Started Jun 23 05:36:19 PM PDT 24
Finished Jun 23 05:36:22 PM PDT 24
Peak memory 217844 kb
Host smart-726c7940-8124-417e-91a2-69bdff3b794e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618549255 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.2618549255
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.1037211148
Short name T609
Test name
Test status
Simulation time 33531758 ps
CPU time 1.33 seconds
Started Jun 23 05:36:20 PM PDT 24
Finished Jun 23 05:36:22 PM PDT 24
Peak memory 216604 kb
Host smart-828ca263-7ed1-4f17-a29d-8a34791bcbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037211148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1037211148
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.2855763987
Short name T624
Test name
Test status
Simulation time 41796166 ps
CPU time 1.76 seconds
Started Jun 23 05:36:22 PM PDT 24
Finished Jun 23 05:36:25 PM PDT 24
Peak memory 217964 kb
Host smart-55666954-bde8-48eb-9c96-1c325bd0be89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855763987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2855763987
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.76325232
Short name T948
Test name
Test status
Simulation time 79855657 ps
CPU time 1.15 seconds
Started Jun 23 05:36:18 PM PDT 24
Finished Jun 23 05:36:19 PM PDT 24
Peak memory 220208 kb
Host smart-7de9012b-8585-45e5-aaae-9f5791812fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76325232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.76325232
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.1300525104
Short name T564
Test name
Test status
Simulation time 117167168 ps
CPU time 1.33 seconds
Started Jun 23 05:36:19 PM PDT 24
Finished Jun 23 05:36:21 PM PDT 24
Peak memory 217984 kb
Host smart-bfd7c1ab-a1db-441b-aae4-7d1a8ef48403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300525104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1300525104
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2219270857
Short name T572
Test name
Test status
Simulation time 96925082 ps
CPU time 1.07 seconds
Started Jun 23 05:36:23 PM PDT 24
Finished Jun 23 05:36:25 PM PDT 24
Peak memory 216732 kb
Host smart-38032330-ae47-4cda-929e-c55a422b82ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219270857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2219270857
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.2617532844
Short name T582
Test name
Test status
Simulation time 21328656 ps
CPU time 1.16 seconds
Started Jun 23 05:36:22 PM PDT 24
Finished Jun 23 05:36:24 PM PDT 24
Peak memory 220176 kb
Host smart-d9dec31e-1605-4c59-b0f1-4d915eb9d6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617532844 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.2617532844
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.2084907281
Short name T944
Test name
Test status
Simulation time 23416625 ps
CPU time 1.2 seconds
Started Jun 23 05:36:19 PM PDT 24
Finished Jun 23 05:36:21 PM PDT 24
Peak memory 217908 kb
Host smart-52870bbc-db8a-417d-b774-fe42f877c287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084907281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2084907281
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.1526927980
Short name T653
Test name
Test status
Simulation time 11262817 ps
CPU time 0.86 seconds
Started Jun 23 05:34:17 PM PDT 24
Finished Jun 23 05:34:18 PM PDT 24
Peak memory 206268 kb
Host smart-de741314-0799-4830-9ed7-61a81a3a0e9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526927980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1526927980
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.93715039
Short name T557
Test name
Test status
Simulation time 12625316 ps
CPU time 0.91 seconds
Started Jun 23 05:34:14 PM PDT 24
Finished Jun 23 05:34:15 PM PDT 24
Peak memory 215708 kb
Host smart-c0111359-b214-4545-99c4-9b6391fa9f6b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93715039 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.93715039
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.3463723772
Short name T176
Test name
Test status
Simulation time 36209492 ps
CPU time 1.12 seconds
Started Jun 23 05:34:15 PM PDT 24
Finished Jun 23 05:34:17 PM PDT 24
Peak memory 223352 kb
Host smart-e1a74674-5903-4477-a1c2-f0aa9f70f2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463723772 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3463723772
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1733530844
Short name T635
Test name
Test status
Simulation time 81192287 ps
CPU time 1.54 seconds
Started Jun 23 05:34:10 PM PDT 24
Finished Jun 23 05:34:12 PM PDT 24
Peak memory 218128 kb
Host smart-dd795d97-f61a-4838-96bd-c9176ed97ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733530844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1733530844
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.902729984
Short name T490
Test name
Test status
Simulation time 29588378 ps
CPU time 0.92 seconds
Started Jun 23 05:34:15 PM PDT 24
Finished Jun 23 05:34:17 PM PDT 24
Peak memory 214984 kb
Host smart-0d5d9512-56ae-4749-ae2d-bf64998e5b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902729984 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.902729984
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.501468263
Short name T830
Test name
Test status
Simulation time 30608286 ps
CPU time 0.87 seconds
Started Jun 23 05:34:13 PM PDT 24
Finished Jun 23 05:34:14 PM PDT 24
Peak memory 213436 kb
Host smart-7e64c1b7-360d-471f-a726-133943bb8fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501468263 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.501468263
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1609128387
Short name T117
Test name
Test status
Simulation time 185249357 ps
CPU time 1.54 seconds
Started Jun 23 05:34:16 PM PDT 24
Finished Jun 23 05:34:18 PM PDT 24
Peak memory 216464 kb
Host smart-2faa0eef-6b56-48bb-8862-7759755b84ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609128387 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1609128387
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.45891520
Short name T924
Test name
Test status
Simulation time 81102462721 ps
CPU time 2085.1 seconds
Started Jun 23 05:34:15 PM PDT 24
Finished Jun 23 06:09:01 PM PDT 24
Peak memory 228836 kb
Host smart-1d07bd0c-6a8b-4bb9-9586-443c4a11fad5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45891520 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.45891520
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.4269922071
Short name T988
Test name
Test status
Simulation time 21380152 ps
CPU time 1.12 seconds
Started Jun 23 05:36:20 PM PDT 24
Finished Jun 23 05:36:23 PM PDT 24
Peak memory 220132 kb
Host smart-ce6cbcaa-7935-4989-af51-f239725e5e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269922071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.4269922071
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.2168128397
Short name T347
Test name
Test status
Simulation time 34849142 ps
CPU time 1.37 seconds
Started Jun 23 05:36:21 PM PDT 24
Finished Jun 23 05:36:24 PM PDT 24
Peak memory 217752 kb
Host smart-537da978-1edb-4aad-92be-efdbd6c83213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168128397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2168128397
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.2129422688
Short name T746
Test name
Test status
Simulation time 66148957 ps
CPU time 1.13 seconds
Started Jun 23 05:36:22 PM PDT 24
Finished Jun 23 05:36:24 PM PDT 24
Peak memory 219760 kb
Host smart-e86a0fa8-5c40-4720-b9bb-025e01b13010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129422688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.2129422688
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.2374432639
Short name T359
Test name
Test status
Simulation time 39944261 ps
CPU time 1.19 seconds
Started Jun 23 05:36:19 PM PDT 24
Finished Jun 23 05:36:22 PM PDT 24
Peak memory 216888 kb
Host smart-48023a34-ffb4-433a-a84f-6c07844a965d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374432639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2374432639
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1550126704
Short name T379
Test name
Test status
Simulation time 52494742 ps
CPU time 1.6 seconds
Started Jun 23 05:36:19 PM PDT 24
Finished Jun 23 05:36:22 PM PDT 24
Peak memory 218016 kb
Host smart-482089e1-153a-49c2-ab52-ae2ae7a11cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550126704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1550126704
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.2623410109
Short name T147
Test name
Test status
Simulation time 25654954 ps
CPU time 1.28 seconds
Started Jun 23 05:36:21 PM PDT 24
Finished Jun 23 05:36:24 PM PDT 24
Peak memory 219212 kb
Host smart-9c461a92-e212-4287-a13e-eae1c7154ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623410109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2623410109
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.2276292391
Short name T365
Test name
Test status
Simulation time 20737889 ps
CPU time 1.12 seconds
Started Jun 23 05:36:21 PM PDT 24
Finished Jun 23 05:36:23 PM PDT 24
Peak memory 216592 kb
Host smart-21f3d900-4416-45dc-9f6b-60be90f6055b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276292391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2276292391
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.699754207
Short name T692
Test name
Test status
Simulation time 48902895 ps
CPU time 1.25 seconds
Started Jun 23 05:36:20 PM PDT 24
Finished Jun 23 05:36:22 PM PDT 24
Peak memory 215100 kb
Host smart-3fb2242e-593f-48ed-86e3-8b6f7e1e20d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699754207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.699754207
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.1943096115
Short name T792
Test name
Test status
Simulation time 56743252 ps
CPU time 1.97 seconds
Started Jun 23 05:36:20 PM PDT 24
Finished Jun 23 05:36:24 PM PDT 24
Peak memory 218248 kb
Host smart-125e5364-7486-4331-a320-1cadb763698e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943096115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1943096115
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.518377992
Short name T390
Test name
Test status
Simulation time 51531437 ps
CPU time 1.29 seconds
Started Jun 23 05:36:24 PM PDT 24
Finished Jun 23 05:36:26 PM PDT 24
Peak memory 218812 kb
Host smart-248c1134-c086-48b8-92b4-0c9879258135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518377992 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.518377992
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.3549979842
Short name T822
Test name
Test status
Simulation time 64909066 ps
CPU time 1.46 seconds
Started Jun 23 05:36:29 PM PDT 24
Finished Jun 23 05:36:32 PM PDT 24
Peak memory 219252 kb
Host smart-b3f1c41a-2b44-44ac-b3a9-efb7e2232bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549979842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3549979842
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.3001302975
Short name T939
Test name
Test status
Simulation time 200773208 ps
CPU time 1.13 seconds
Started Jun 23 05:36:33 PM PDT 24
Finished Jun 23 05:36:35 PM PDT 24
Peak memory 219164 kb
Host smart-9653c8eb-a430-4b64-a731-f52ca1629b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001302975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.3001302975
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.3429844499
Short name T761
Test name
Test status
Simulation time 87164961 ps
CPU time 1.43 seconds
Started Jun 23 05:36:25 PM PDT 24
Finished Jun 23 05:36:27 PM PDT 24
Peak memory 218036 kb
Host smart-eb22e8b6-54a4-4e34-992e-5b67d7fa34f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429844499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3429844499
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.3920510738
Short name T738
Test name
Test status
Simulation time 118346725 ps
CPU time 1.19 seconds
Started Jun 23 05:36:33 PM PDT 24
Finished Jun 23 05:36:35 PM PDT 24
Peak memory 217796 kb
Host smart-e900a450-8b0e-4dd3-8aae-b65fbb84564f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920510738 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.3920510738
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.3547989824
Short name T780
Test name
Test status
Simulation time 80381892 ps
CPU time 1.02 seconds
Started Jun 23 05:36:26 PM PDT 24
Finished Jun 23 05:36:28 PM PDT 24
Peak memory 216624 kb
Host smart-3dd1c9ba-b0b5-41c9-92f9-3e97759ae2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547989824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3547989824
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.4103250335
Short name T126
Test name
Test status
Simulation time 52822739 ps
CPU time 1.2 seconds
Started Jun 23 05:36:28 PM PDT 24
Finished Jun 23 05:36:30 PM PDT 24
Peak memory 218476 kb
Host smart-c9771227-c405-4ecb-9587-dfff2569f6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103250335 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.4103250335
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.3628394987
Short name T663
Test name
Test status
Simulation time 34585415 ps
CPU time 1.43 seconds
Started Jun 23 05:36:29 PM PDT 24
Finished Jun 23 05:36:32 PM PDT 24
Peak memory 218180 kb
Host smart-45b39be9-46ad-4563-90c7-2851eb2b720d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628394987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3628394987
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.667445738
Short name T517
Test name
Test status
Simulation time 45230163 ps
CPU time 1.15 seconds
Started Jun 23 05:36:28 PM PDT 24
Finished Jun 23 05:36:30 PM PDT 24
Peak memory 218396 kb
Host smart-bcd1b2dd-6ac6-47df-9319-a8fff6fc074a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667445738 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.667445738
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.1492165520
Short name T397
Test name
Test status
Simulation time 24563628 ps
CPU time 1.2 seconds
Started Jun 23 05:36:27 PM PDT 24
Finished Jun 23 05:36:28 PM PDT 24
Peak memory 216520 kb
Host smart-b6cef96f-5f4e-4355-ae85-89b61b9b2dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492165520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1492165520
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1875055412
Short name T832
Test name
Test status
Simulation time 76620486 ps
CPU time 1.19 seconds
Started Jun 23 05:34:21 PM PDT 24
Finished Jun 23 05:34:23 PM PDT 24
Peak memory 220896 kb
Host smart-5fc98119-277d-4ffe-aab9-8ba69273c0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875055412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1875055412
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.254232969
Short name T399
Test name
Test status
Simulation time 68327107 ps
CPU time 0.92 seconds
Started Jun 23 05:34:22 PM PDT 24
Finished Jun 23 05:34:23 PM PDT 24
Peak memory 206132 kb
Host smart-d4dd2cd2-aab5-49c0-85e8-12098e165949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254232969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.254232969
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.4192301604
Short name T52
Test name
Test status
Simulation time 114022939 ps
CPU time 0.89 seconds
Started Jun 23 05:34:22 PM PDT 24
Finished Jun 23 05:34:24 PM PDT 24
Peak memory 215664 kb
Host smart-b90090a9-6f6e-4aee-9797-60d1438c95f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192301604 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.4192301604
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.99475611
Short name T193
Test name
Test status
Simulation time 21645581 ps
CPU time 0.95 seconds
Started Jun 23 05:34:22 PM PDT 24
Finished Jun 23 05:34:24 PM PDT 24
Peak memory 218000 kb
Host smart-89e809f4-329d-4926-bdbf-331368851ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99475611 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.99475611
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_intr.923516606
Short name T608
Test name
Test status
Simulation time 27541942 ps
CPU time 1.07 seconds
Started Jun 23 05:34:23 PM PDT 24
Finished Jun 23 05:34:24 PM PDT 24
Peak memory 223380 kb
Host smart-bb685136-3f91-4cf5-bfb0-2a3c198e94e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923516606 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.923516606
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.965483781
Short name T353
Test name
Test status
Simulation time 19208080 ps
CPU time 0.97 seconds
Started Jun 23 05:34:14 PM PDT 24
Finished Jun 23 05:34:15 PM PDT 24
Peak memory 214596 kb
Host smart-92415dd5-8011-41ad-98d1-3113e07c77c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965483781 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.965483781
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3829637004
Short name T895
Test name
Test status
Simulation time 60454161 ps
CPU time 0.91 seconds
Started Jun 23 05:34:15 PM PDT 24
Finished Jun 23 05:34:16 PM PDT 24
Peak memory 205744 kb
Host smart-b1f116a7-dc45-42a4-9557-a781b783f920
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829637004 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3829637004
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2592212270
Short name T228
Test name
Test status
Simulation time 7536316545 ps
CPU time 170.66 seconds
Started Jun 23 05:34:18 PM PDT 24
Finished Jun 23 05:37:09 PM PDT 24
Peak memory 216652 kb
Host smart-e9b2eef5-1f83-47d2-ae27-fa53d350b729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592212270 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2592212270
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.3063255434
Short name T800
Test name
Test status
Simulation time 62112359 ps
CPU time 1.38 seconds
Started Jun 23 05:36:24 PM PDT 24
Finished Jun 23 05:36:26 PM PDT 24
Peak memory 216812 kb
Host smart-e91d6963-e2ad-4765-bbd7-36c41e4e0b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063255434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3063255434
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.3204610479
Short name T701
Test name
Test status
Simulation time 37741421 ps
CPU time 1.63 seconds
Started Jun 23 05:36:34 PM PDT 24
Finished Jun 23 05:36:36 PM PDT 24
Peak memory 216696 kb
Host smart-4f85ff14-18b5-4d9f-8a44-bd20ce8476ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204610479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3204610479
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.1114776273
Short name T146
Test name
Test status
Simulation time 34823222 ps
CPU time 1.48 seconds
Started Jun 23 05:36:26 PM PDT 24
Finished Jun 23 05:36:28 PM PDT 24
Peak memory 215088 kb
Host smart-90c774d1-31fd-4fe7-9dd1-c76e65be6549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114776273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.1114776273
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.366985900
Short name T649
Test name
Test status
Simulation time 38397867 ps
CPU time 1.44 seconds
Started Jun 23 05:36:24 PM PDT 24
Finished Jun 23 05:36:26 PM PDT 24
Peak memory 217944 kb
Host smart-a0aa53e6-86ff-4f53-a22b-5e7555b94b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366985900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.366985900
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.2052226418
Short name T104
Test name
Test status
Simulation time 31541981 ps
CPU time 1.16 seconds
Started Jun 23 05:36:34 PM PDT 24
Finished Jun 23 05:36:36 PM PDT 24
Peak memory 219592 kb
Host smart-3ce6140c-6b02-4dc7-9a98-35613ad6dfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052226418 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2052226418
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.2524418863
Short name T84
Test name
Test status
Simulation time 33335761 ps
CPU time 1.27 seconds
Started Jun 23 05:36:24 PM PDT 24
Finished Jun 23 05:36:26 PM PDT 24
Peak memory 217748 kb
Host smart-3bdea1ab-b5bd-496e-8ad1-e14c90d779d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524418863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2524418863
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.2184487341
Short name T610
Test name
Test status
Simulation time 30415612 ps
CPU time 1.17 seconds
Started Jun 23 05:36:29 PM PDT 24
Finished Jun 23 05:36:30 PM PDT 24
Peak memory 218864 kb
Host smart-80893281-f994-467f-bed3-f5e19378e067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184487341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.2184487341
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.1291617309
Short name T666
Test name
Test status
Simulation time 36370458 ps
CPU time 1.55 seconds
Started Jun 23 05:36:26 PM PDT 24
Finished Jun 23 05:36:28 PM PDT 24
Peak memory 216740 kb
Host smart-0a14d209-db40-43db-9150-891f76ce9b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291617309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1291617309
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.2133481148
Short name T403
Test name
Test status
Simulation time 98060774 ps
CPU time 1.24 seconds
Started Jun 23 05:36:24 PM PDT 24
Finished Jun 23 05:36:25 PM PDT 24
Peak memory 215036 kb
Host smart-74d0f5e0-34c6-4337-a4e4-4674478f879e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133481148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.2133481148
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.159811052
Short name T316
Test name
Test status
Simulation time 310275871 ps
CPU time 3.66 seconds
Started Jun 23 05:36:29 PM PDT 24
Finished Jun 23 05:36:33 PM PDT 24
Peak memory 219548 kb
Host smart-76bc989e-9c8c-4b83-b8bd-779d276214e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159811052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.159811052
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1517575681
Short name T386
Test name
Test status
Simulation time 80625446 ps
CPU time 1.4 seconds
Started Jun 23 05:36:28 PM PDT 24
Finished Jun 23 05:36:30 PM PDT 24
Peak memory 217976 kb
Host smart-6060da65-582d-417d-8205-5f65bdf8e201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517575681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1517575681
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.4090114819
Short name T892
Test name
Test status
Simulation time 45412315 ps
CPU time 1.13 seconds
Started Jun 23 05:36:28 PM PDT 24
Finished Jun 23 05:36:30 PM PDT 24
Peak memory 218936 kb
Host smart-eea6e528-e268-450c-a128-ef19360ec036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090114819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.4090114819
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/128.edn_alert.660462707
Short name T617
Test name
Test status
Simulation time 29461487 ps
CPU time 1.39 seconds
Started Jun 23 05:36:25 PM PDT 24
Finished Jun 23 05:36:27 PM PDT 24
Peak memory 219988 kb
Host smart-fe7ef339-82bd-4679-953f-c1bc831f8af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660462707 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.660462707
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.459431549
Short name T455
Test name
Test status
Simulation time 106787034 ps
CPU time 1.22 seconds
Started Jun 23 05:36:27 PM PDT 24
Finished Jun 23 05:36:28 PM PDT 24
Peak memory 217860 kb
Host smart-88cbdc2f-620c-4d2f-a5a0-1de9c85a265b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459431549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.459431549
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.333796812
Short name T912
Test name
Test status
Simulation time 129667233 ps
CPU time 1.2 seconds
Started Jun 23 05:36:29 PM PDT 24
Finished Jun 23 05:36:31 PM PDT 24
Peak memory 219780 kb
Host smart-4ccc25b3-6419-474c-ba18-54e6258862a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333796812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.333796812
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.1176324911
Short name T694
Test name
Test status
Simulation time 25140072 ps
CPU time 1.23 seconds
Started Jun 23 05:36:34 PM PDT 24
Finished Jun 23 05:36:35 PM PDT 24
Peak memory 219244 kb
Host smart-b4ac6dfc-049f-4c22-8087-505fa8d6a740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176324911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1176324911
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.2207478049
Short name T589
Test name
Test status
Simulation time 15707371 ps
CPU time 0.86 seconds
Started Jun 23 05:34:21 PM PDT 24
Finished Jun 23 05:34:23 PM PDT 24
Peak memory 206224 kb
Host smart-e480f83a-63c3-4055-a56a-efd6cb789df0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207478049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2207478049
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3610887563
Short name T180
Test name
Test status
Simulation time 11965201 ps
CPU time 0.89 seconds
Started Jun 23 05:34:19 PM PDT 24
Finished Jun 23 05:34:20 PM PDT 24
Peak memory 215804 kb
Host smart-a50fc27c-ee18-4acd-8c62-2af0f22b41c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610887563 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3610887563
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.1271211219
Short name T763
Test name
Test status
Simulation time 21403884 ps
CPU time 1.04 seconds
Started Jun 23 05:34:21 PM PDT 24
Finished Jun 23 05:34:23 PM PDT 24
Peak memory 217972 kb
Host smart-5c957088-d0b8-48f3-b8e9-a28305362df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271211219 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1271211219
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1575860604
Short name T329
Test name
Test status
Simulation time 92577033 ps
CPU time 1.24 seconds
Started Jun 23 05:34:21 PM PDT 24
Finished Jun 23 05:34:23 PM PDT 24
Peak memory 216512 kb
Host smart-f402f5df-ecd0-4e19-b35d-8227c07acf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575860604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1575860604
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2354256352
Short name T442
Test name
Test status
Simulation time 24238673 ps
CPU time 1.01 seconds
Started Jun 23 05:34:20 PM PDT 24
Finished Jun 23 05:34:21 PM PDT 24
Peak memory 214748 kb
Host smart-b5aa7bbf-03e7-435f-a9f9-d02ddfe19b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354256352 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2354256352
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2155380815
Short name T501
Test name
Test status
Simulation time 45154377 ps
CPU time 0.92 seconds
Started Jun 23 05:34:21 PM PDT 24
Finished Jun 23 05:34:23 PM PDT 24
Peak memory 214632 kb
Host smart-1bf2c04e-a637-45ac-9a65-dfcd112d643c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155380815 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2155380815
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1954627272
Short name T968
Test name
Test status
Simulation time 400008952 ps
CPU time 2.61 seconds
Started Jun 23 05:34:23 PM PDT 24
Finished Jun 23 05:34:26 PM PDT 24
Peak memory 216740 kb
Host smart-a725d18e-524d-48da-8cf2-251f96bbccb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954627272 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1954627272
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1026090622
Short name T40
Test name
Test status
Simulation time 97583650259 ps
CPU time 1244.53 seconds
Started Jun 23 05:34:19 PM PDT 24
Finished Jun 23 05:55:04 PM PDT 24
Peak memory 224652 kb
Host smart-1be20b5f-bd52-4a32-bc93-56952325c085
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026090622 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1026090622
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.1903830554
Short name T858
Test name
Test status
Simulation time 30753476 ps
CPU time 1.23 seconds
Started Jun 23 05:36:33 PM PDT 24
Finished Jun 23 05:36:35 PM PDT 24
Peak memory 219192 kb
Host smart-29fb2562-5efa-472c-9f39-c6114c944133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903830554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.1903830554
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.2839838949
Short name T409
Test name
Test status
Simulation time 34589121 ps
CPU time 1.45 seconds
Started Jun 23 05:36:30 PM PDT 24
Finished Jun 23 05:36:32 PM PDT 24
Peak memory 216768 kb
Host smart-ba191464-4ff8-4082-a4b0-24c4020ffc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839838949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2839838949
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.1235111274
Short name T151
Test name
Test status
Simulation time 41119724 ps
CPU time 1.26 seconds
Started Jun 23 05:36:28 PM PDT 24
Finished Jun 23 05:36:30 PM PDT 24
Peak memory 219920 kb
Host smart-d5de8ace-cf94-4c9e-9422-be51bc1d8480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235111274 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.1235111274
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.1011131565
Short name T802
Test name
Test status
Simulation time 178663367 ps
CPU time 1.25 seconds
Started Jun 23 05:36:29 PM PDT 24
Finished Jun 23 05:36:31 PM PDT 24
Peak memory 216728 kb
Host smart-3acf9edf-c1aa-495f-ba84-a8e50baaf181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011131565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1011131565
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1280716599
Short name T554
Test name
Test status
Simulation time 34477384 ps
CPU time 1.39 seconds
Started Jun 23 05:36:24 PM PDT 24
Finished Jun 23 05:36:26 PM PDT 24
Peak memory 219132 kb
Host smart-39eb0818-388c-42ab-af44-de68e9dd3bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280716599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1280716599
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.35874599
Short name T966
Test name
Test status
Simulation time 40314954 ps
CPU time 1.22 seconds
Started Jun 23 05:36:28 PM PDT 24
Finished Jun 23 05:36:30 PM PDT 24
Peak memory 217988 kb
Host smart-345a19c5-d3e1-490c-ade0-5875c089cca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35874599 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.35874599
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.3732610564
Short name T922
Test name
Test status
Simulation time 85074299 ps
CPU time 1.43 seconds
Started Jun 23 05:36:29 PM PDT 24
Finished Jun 23 05:36:31 PM PDT 24
Peak memory 218332 kb
Host smart-d6665912-dbf1-43ef-9fb8-2155fb6f9f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732610564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3732610564
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.3548701481
Short name T407
Test name
Test status
Simulation time 79218509 ps
CPU time 1.1 seconds
Started Jun 23 05:36:28 PM PDT 24
Finished Jun 23 05:36:30 PM PDT 24
Peak memory 219236 kb
Host smart-ccba45ea-9fc5-45ca-bdc1-6f2520834fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548701481 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.3548701481
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/135.edn_alert.3661832728
Short name T32
Test name
Test status
Simulation time 34455888 ps
CPU time 1.18 seconds
Started Jun 23 05:36:29 PM PDT 24
Finished Jun 23 05:36:30 PM PDT 24
Peak memory 219016 kb
Host smart-23c715d1-fc32-42bd-a677-7b8bdc1dddd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661832728 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.3661832728
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.2399482698
Short name T691
Test name
Test status
Simulation time 54808171 ps
CPU time 1.11 seconds
Started Jun 23 05:36:30 PM PDT 24
Finished Jun 23 05:36:32 PM PDT 24
Peak memory 216860 kb
Host smart-a60c8f3a-e292-437f-8e8c-a672deda9ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399482698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2399482698
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.535878382
Short name T602
Test name
Test status
Simulation time 222135387 ps
CPU time 1.39 seconds
Started Jun 23 05:36:32 PM PDT 24
Finished Jun 23 05:36:33 PM PDT 24
Peak memory 220044 kb
Host smart-0205aef9-bb3f-435d-ac0c-df77cfa52e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535878382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.535878382
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.1730148966
Short name T927
Test name
Test status
Simulation time 43349471 ps
CPU time 1.5 seconds
Started Jun 23 05:36:33 PM PDT 24
Finished Jun 23 05:36:35 PM PDT 24
Peak memory 218760 kb
Host smart-bd505c2d-4250-4a84-a73b-55f3a796ddc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730148966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1730148966
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.2148744276
Short name T764
Test name
Test status
Simulation time 149800299 ps
CPU time 3.39 seconds
Started Jun 23 05:36:31 PM PDT 24
Finished Jun 23 05:36:35 PM PDT 24
Peak memory 217880 kb
Host smart-bbf35875-6ddb-4972-9204-794280ba2f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148744276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2148744276
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2759425229
Short name T462
Test name
Test status
Simulation time 50899420 ps
CPU time 1.57 seconds
Started Jun 23 05:36:29 PM PDT 24
Finished Jun 23 05:36:32 PM PDT 24
Peak memory 217792 kb
Host smart-234171e9-d857-4433-974c-4b6eaa7d8ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759425229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2759425229
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.3471568569
Short name T183
Test name
Test status
Simulation time 112702480 ps
CPU time 1.19 seconds
Started Jun 23 05:36:28 PM PDT 24
Finished Jun 23 05:36:30 PM PDT 24
Peak memory 218256 kb
Host smart-c01eebcf-6f85-4430-8f7b-3fde00ca4dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471568569 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.3471568569
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.1744911982
Short name T350
Test name
Test status
Simulation time 44825392 ps
CPU time 1.08 seconds
Started Jun 23 05:36:32 PM PDT 24
Finished Jun 23 05:36:33 PM PDT 24
Peak memory 216684 kb
Host smart-fbbeac99-e5ef-4a46-82cc-f87026cf9f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744911982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1744911982
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1252112940
Short name T840
Test name
Test status
Simulation time 25329590 ps
CPU time 1.16 seconds
Started Jun 23 05:34:23 PM PDT 24
Finished Jun 23 05:34:24 PM PDT 24
Peak memory 219168 kb
Host smart-287a49f9-56d0-4096-adeb-79c5da2c1894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252112940 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1252112940
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1856891126
Short name T23
Test name
Test status
Simulation time 50559670 ps
CPU time 0.92 seconds
Started Jun 23 05:34:25 PM PDT 24
Finished Jun 23 05:34:26 PM PDT 24
Peak memory 206092 kb
Host smart-f33e5a4f-604e-40bc-b09a-91a25872f208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856891126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1856891126
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.3493412523
Short name T713
Test name
Test status
Simulation time 35171114 ps
CPU time 0.84 seconds
Started Jun 23 05:34:26 PM PDT 24
Finished Jun 23 05:34:27 PM PDT 24
Peak memory 214796 kb
Host smart-038c9357-92ca-4bc2-ab20-df6441fe6a60
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493412523 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3493412523
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.795414733
Short name T389
Test name
Test status
Simulation time 62550222 ps
CPU time 1.1 seconds
Started Jun 23 05:34:27 PM PDT 24
Finished Jun 23 05:34:28 PM PDT 24
Peak memory 219280 kb
Host smart-0fb3663a-cd74-4ffb-997d-ec0870724313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795414733 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.795414733
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1420290381
Short name T799
Test name
Test status
Simulation time 204661543 ps
CPU time 1.58 seconds
Started Jun 23 05:34:21 PM PDT 24
Finished Jun 23 05:34:24 PM PDT 24
Peak memory 217944 kb
Host smart-08280591-2589-4e78-9cd4-1736ba2125c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420290381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1420290381
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1647710840
Short name T106
Test name
Test status
Simulation time 21263112 ps
CPU time 1.08 seconds
Started Jun 23 05:34:21 PM PDT 24
Finished Jun 23 05:34:22 PM PDT 24
Peak memory 215180 kb
Host smart-479df9a5-e88e-41ff-a82a-895fc1f6dd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647710840 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1647710840
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2234605474
Short name T962
Test name
Test status
Simulation time 38581474 ps
CPU time 0.94 seconds
Started Jun 23 05:34:21 PM PDT 24
Finished Jun 23 05:34:22 PM PDT 24
Peak memory 214584 kb
Host smart-e53f0c2d-abfb-485e-9f1e-bd5025d9b9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234605474 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2234605474
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2991341930
Short name T585
Test name
Test status
Simulation time 348267504 ps
CPU time 2.42 seconds
Started Jun 23 05:34:19 PM PDT 24
Finished Jun 23 05:34:21 PM PDT 24
Peak memory 216644 kb
Host smart-d2687a35-8fc9-4db5-8801-84fe6027cd52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991341930 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2991341930
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1770681280
Short name T238
Test name
Test status
Simulation time 87940805908 ps
CPU time 1034.45 seconds
Started Jun 23 05:34:21 PM PDT 24
Finished Jun 23 05:51:36 PM PDT 24
Peak memory 220776 kb
Host smart-87ad3bfb-090f-4df0-b335-187424c4c940
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770681280 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1770681280
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.3047344856
Short name T852
Test name
Test status
Simulation time 250836567 ps
CPU time 1.07 seconds
Started Jun 23 05:36:31 PM PDT 24
Finished Jun 23 05:36:33 PM PDT 24
Peak memory 219388 kb
Host smart-2f5ae860-1a14-4777-a56f-49eccec59a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047344856 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.3047344856
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.23937441
Short name T373
Test name
Test status
Simulation time 57396339 ps
CPU time 1.27 seconds
Started Jun 23 05:36:29 PM PDT 24
Finished Jun 23 05:36:31 PM PDT 24
Peak memory 216652 kb
Host smart-a35fc327-bc3b-4ae5-81e3-451654a0fcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23937441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.23937441
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.2957274590
Short name T670
Test name
Test status
Simulation time 77133782 ps
CPU time 1.19 seconds
Started Jun 23 05:36:29 PM PDT 24
Finished Jun 23 05:36:31 PM PDT 24
Peak memory 217940 kb
Host smart-37edd3d9-929b-4032-af3f-a7bbbf623b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957274590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2957274590
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.413719438
Short name T992
Test name
Test status
Simulation time 98554527 ps
CPU time 1.17 seconds
Started Jun 23 05:36:30 PM PDT 24
Finished Jun 23 05:36:31 PM PDT 24
Peak memory 217672 kb
Host smart-a79c58bd-c791-4bc3-a988-164b54d2fbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413719438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.413719438
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.3761440957
Short name T607
Test name
Test status
Simulation time 27955076 ps
CPU time 1.26 seconds
Started Jun 23 05:36:34 PM PDT 24
Finished Jun 23 05:36:35 PM PDT 24
Peak memory 217944 kb
Host smart-a7c4a9e4-fe2e-4fc3-9a16-5207606763c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761440957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3761440957
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.3640984273
Short name T77
Test name
Test status
Simulation time 46274666 ps
CPU time 1.2 seconds
Started Jun 23 05:36:32 PM PDT 24
Finished Jun 23 05:36:34 PM PDT 24
Peak memory 216676 kb
Host smart-7f28b11c-d3b3-4b15-854c-488aab93f18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640984273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3640984273
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.3120537217
Short name T300
Test name
Test status
Simulation time 25184591 ps
CPU time 1.24 seconds
Started Jun 23 05:36:38 PM PDT 24
Finished Jun 23 05:36:40 PM PDT 24
Peak memory 219072 kb
Host smart-e213472d-bfe0-4737-8201-717f3195dfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120537217 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.3120537217
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.4278112624
Short name T43
Test name
Test status
Simulation time 35032590 ps
CPU time 1.59 seconds
Started Jun 23 05:36:36 PM PDT 24
Finished Jun 23 05:36:38 PM PDT 24
Peak memory 217912 kb
Host smart-a2cb579e-50d1-448e-94e0-2942f1b41545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278112624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.4278112624
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.363059895
Short name T471
Test name
Test status
Simulation time 85121097 ps
CPU time 1.12 seconds
Started Jun 23 05:36:33 PM PDT 24
Finished Jun 23 05:36:35 PM PDT 24
Peak memory 219028 kb
Host smart-e8daf375-373b-4196-b6ac-bb15370798a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363059895 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.363059895
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/145.edn_alert.1276473347
Short name T474
Test name
Test status
Simulation time 31979957 ps
CPU time 1.08 seconds
Started Jun 23 05:36:33 PM PDT 24
Finished Jun 23 05:36:34 PM PDT 24
Peak memory 218040 kb
Host smart-0f4dca7a-1626-4e62-b20d-750c5b424a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276473347 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.1276473347
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.1896865408
Short name T621
Test name
Test status
Simulation time 60600849 ps
CPU time 1.26 seconds
Started Jun 23 05:36:35 PM PDT 24
Finished Jun 23 05:36:37 PM PDT 24
Peak memory 214644 kb
Host smart-7a46e827-c39d-4574-b336-1f26c856ab15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896865408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1896865408
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.1207135715
Short name T972
Test name
Test status
Simulation time 73332214 ps
CPU time 1.12 seconds
Started Jun 23 05:36:35 PM PDT 24
Finished Jun 23 05:36:37 PM PDT 24
Peak memory 220584 kb
Host smart-3a5f321b-3105-4534-836d-2795ad9ffb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207135715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.1207135715
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.821125555
Short name T473
Test name
Test status
Simulation time 110970534 ps
CPU time 3.13 seconds
Started Jun 23 05:36:34 PM PDT 24
Finished Jun 23 05:36:38 PM PDT 24
Peak memory 218144 kb
Host smart-ab9e4229-03f6-4ea6-802f-2e1e600b2099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821125555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.821125555
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.150139392
Short name T81
Test name
Test status
Simulation time 42301466 ps
CPU time 1.11 seconds
Started Jun 23 05:36:34 PM PDT 24
Finished Jun 23 05:36:36 PM PDT 24
Peak memory 217904 kb
Host smart-10dae249-340e-4b0c-8d17-8f6c8c2cd2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150139392 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.150139392
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3094093740
Short name T464
Test name
Test status
Simulation time 150868120 ps
CPU time 1.04 seconds
Started Jun 23 05:36:35 PM PDT 24
Finished Jun 23 05:36:37 PM PDT 24
Peak memory 216684 kb
Host smart-0dce0c5c-6de8-428c-827b-f965ee54c5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094093740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3094093740
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.4093294811
Short name T779
Test name
Test status
Simulation time 91294997 ps
CPU time 1.1 seconds
Started Jun 23 05:36:35 PM PDT 24
Finished Jun 23 05:36:36 PM PDT 24
Peak memory 218980 kb
Host smart-447c2e4a-3433-4f56-a112-f39c01562de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093294811 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.4093294811
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.3202891461
Short name T327
Test name
Test status
Simulation time 72955804 ps
CPU time 2.7 seconds
Started Jun 23 05:36:34 PM PDT 24
Finished Jun 23 05:36:38 PM PDT 24
Peak memory 216776 kb
Host smart-978dbfe4-2490-44f6-b9ff-4ada1878fdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202891461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3202891461
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.428389306
Short name T194
Test name
Test status
Simulation time 27510007 ps
CPU time 1.27 seconds
Started Jun 23 05:36:35 PM PDT 24
Finished Jun 23 05:36:36 PM PDT 24
Peak memory 219572 kb
Host smart-1014fc4a-e50c-4c01-83c0-919d3d70789d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428389306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.428389306
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.1099371138
Short name T698
Test name
Test status
Simulation time 117413261 ps
CPU time 1.11 seconds
Started Jun 23 05:36:38 PM PDT 24
Finished Jun 23 05:36:40 PM PDT 24
Peak memory 216704 kb
Host smart-defb82bd-a5a3-407a-863f-1d927570192f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099371138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1099371138
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3944320860
Short name T581
Test name
Test status
Simulation time 37712486 ps
CPU time 1.17 seconds
Started Jun 23 05:34:23 PM PDT 24
Finished Jun 23 05:34:25 PM PDT 24
Peak memory 217960 kb
Host smart-c86e0bef-c016-4dbd-b3ac-ee4a9587ff08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944320860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3944320860
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2399106096
Short name T867
Test name
Test status
Simulation time 46374323 ps
CPU time 0.93 seconds
Started Jun 23 05:34:31 PM PDT 24
Finished Jun 23 05:34:32 PM PDT 24
Peak memory 214352 kb
Host smart-44148421-c6aa-41a2-b7b1-36d627480359
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399106096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2399106096
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2483836573
Short name T172
Test name
Test status
Simulation time 45672186 ps
CPU time 0.88 seconds
Started Jun 23 05:34:24 PM PDT 24
Finished Jun 23 05:34:25 PM PDT 24
Peak memory 214844 kb
Host smart-2c8e30d5-f96b-47d2-9d33-d2f3024950db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483836573 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2483836573
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2507801958
Short name T786
Test name
Test status
Simulation time 52649814 ps
CPU time 1.11 seconds
Started Jun 23 05:34:34 PM PDT 24
Finished Jun 23 05:34:35 PM PDT 24
Peak memory 217596 kb
Host smart-0e98e4f4-39d6-4f2e-a041-008bd24bac47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507801958 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2507801958
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1102120302
Short name T730
Test name
Test status
Simulation time 19482741 ps
CPU time 1.06 seconds
Started Jun 23 05:34:26 PM PDT 24
Finished Jun 23 05:34:27 PM PDT 24
Peak memory 217968 kb
Host smart-b0860c92-238d-4126-88c1-36b106f58f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102120302 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1102120302
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3764182949
Short name T994
Test name
Test status
Simulation time 99076903 ps
CPU time 1.14 seconds
Started Jun 23 05:34:25 PM PDT 24
Finished Jun 23 05:34:27 PM PDT 24
Peak memory 216632 kb
Host smart-9ab9f046-6dc7-415f-be5e-12aa414dc413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764182949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3764182949
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.3732771461
Short name T496
Test name
Test status
Simulation time 36539003 ps
CPU time 0.8 seconds
Started Jun 23 05:34:25 PM PDT 24
Finished Jun 23 05:34:26 PM PDT 24
Peak memory 214768 kb
Host smart-289fecae-b53e-432d-a215-dfe69b9198b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732771461 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3732771461
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1829951965
Short name T242
Test name
Test status
Simulation time 58090562 ps
CPU time 0.92 seconds
Started Jun 23 05:34:25 PM PDT 24
Finished Jun 23 05:34:26 PM PDT 24
Peak memory 214632 kb
Host smart-3e81461e-2c54-4f48-9d38-68058fe7d6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829951965 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1829951965
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3599650138
Short name T516
Test name
Test status
Simulation time 117314984958 ps
CPU time 1286.28 seconds
Started Jun 23 05:34:25 PM PDT 24
Finished Jun 23 05:55:52 PM PDT 24
Peak memory 223432 kb
Host smart-e4d49350-0565-43d9-b483-868832b5b2c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599650138 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3599650138
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.112000348
Short name T297
Test name
Test status
Simulation time 42882782 ps
CPU time 1.31 seconds
Started Jun 23 05:36:33 PM PDT 24
Finished Jun 23 05:36:35 PM PDT 24
Peak memory 218408 kb
Host smart-8cd9d1f6-58a1-465e-9239-ff09e8a54e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112000348 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.112000348
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/151.edn_alert.2684084486
Short name T758
Test name
Test status
Simulation time 87295003 ps
CPU time 1.13 seconds
Started Jun 23 05:36:33 PM PDT 24
Finished Jun 23 05:36:34 PM PDT 24
Peak memory 215000 kb
Host smart-a9b54be5-2255-42d4-af55-28f8855b6dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684084486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.2684084486
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.3575612972
Short name T923
Test name
Test status
Simulation time 54239441 ps
CPU time 1.04 seconds
Started Jun 23 05:36:38 PM PDT 24
Finished Jun 23 05:36:40 PM PDT 24
Peak memory 216928 kb
Host smart-24f9981f-90cc-4375-844b-38303c78ce4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575612972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3575612972
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.1150029293
Short name T301
Test name
Test status
Simulation time 23632490 ps
CPU time 1.21 seconds
Started Jun 23 05:36:39 PM PDT 24
Finished Jun 23 05:36:41 PM PDT 24
Peak memory 219700 kb
Host smart-6279a7fc-33f9-415c-8258-bb6a3d261731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150029293 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.1150029293
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.2041984959
Short name T312
Test name
Test status
Simulation time 90279775 ps
CPU time 1.35 seconds
Started Jun 23 05:36:37 PM PDT 24
Finished Jun 23 05:36:39 PM PDT 24
Peak memory 218008 kb
Host smart-9eaa2484-9fdf-4681-8636-06aacd29fd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041984959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2041984959
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.4171079747
Short name T54
Test name
Test status
Simulation time 106884441 ps
CPU time 1.26 seconds
Started Jun 23 05:36:41 PM PDT 24
Finished Jun 23 05:36:43 PM PDT 24
Peak memory 219304 kb
Host smart-37c12e5f-2fbc-41dd-aafe-51e6354cad32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171079747 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.4171079747
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.3334008784
Short name T381
Test name
Test status
Simulation time 93698979 ps
CPU time 1.5 seconds
Started Jun 23 05:36:36 PM PDT 24
Finished Jun 23 05:36:38 PM PDT 24
Peak memory 218088 kb
Host smart-7ee75f0a-95fb-4802-8bd7-44ea69466414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334008784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3334008784
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.3414851462
Short name T813
Test name
Test status
Simulation time 42626123 ps
CPU time 1.14 seconds
Started Jun 23 05:36:41 PM PDT 24
Finished Jun 23 05:36:42 PM PDT 24
Peak memory 218912 kb
Host smart-2fd0af3f-19ea-4c1c-bb95-af6b3ffff9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414851462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.3414851462
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.131414271
Short name T321
Test name
Test status
Simulation time 98351900 ps
CPU time 1.31 seconds
Started Jun 23 05:36:41 PM PDT 24
Finished Jun 23 05:36:43 PM PDT 24
Peak memory 216876 kb
Host smart-82063b22-fe97-464e-949b-5c1b50a06e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131414271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.131414271
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.430317734
Short name T979
Test name
Test status
Simulation time 24091848 ps
CPU time 1.15 seconds
Started Jun 23 05:36:39 PM PDT 24
Finished Jun 23 05:36:41 PM PDT 24
Peak memory 219880 kb
Host smart-96ae01d5-3971-49fd-a797-e0c264a8fbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430317734 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.430317734
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.3557495679
Short name T628
Test name
Test status
Simulation time 116377289 ps
CPU time 1.15 seconds
Started Jun 23 05:36:38 PM PDT 24
Finished Jun 23 05:36:40 PM PDT 24
Peak memory 216592 kb
Host smart-fbe13ccc-2903-4e96-bb7d-9affbee64fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557495679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3557495679
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.2455825573
Short name T225
Test name
Test status
Simulation time 349281556 ps
CPU time 1.22 seconds
Started Jun 23 05:36:42 PM PDT 24
Finished Jun 23 05:36:44 PM PDT 24
Peak memory 220172 kb
Host smart-6150fd08-d547-4138-95eb-74f8a019330a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455825573 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.2455825573
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.3698363382
Short name T805
Test name
Test status
Simulation time 65547794 ps
CPU time 1.72 seconds
Started Jun 23 05:36:39 PM PDT 24
Finished Jun 23 05:36:41 PM PDT 24
Peak memory 218052 kb
Host smart-286323dd-dbbe-449f-b1a4-f5158f3c1692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698363382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3698363382
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.744884580
Short name T175
Test name
Test status
Simulation time 45075026 ps
CPU time 1.13 seconds
Started Jun 23 05:36:45 PM PDT 24
Finished Jun 23 05:36:47 PM PDT 24
Peak memory 217792 kb
Host smart-c8731e46-20ff-4718-9bab-4e320a35bb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744884580 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.744884580
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.2049747090
Short name T899
Test name
Test status
Simulation time 79584717 ps
CPU time 1.09 seconds
Started Jun 23 05:36:39 PM PDT 24
Finished Jun 23 05:36:41 PM PDT 24
Peak memory 218856 kb
Host smart-494f263d-0e92-469c-845c-0cac05e66c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049747090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2049747090
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.1661401394
Short name T122
Test name
Test status
Simulation time 189178706 ps
CPU time 1.08 seconds
Started Jun 23 05:36:40 PM PDT 24
Finished Jun 23 05:36:42 PM PDT 24
Peak memory 218044 kb
Host smart-6eced508-fb32-4a4d-a779-5d5598766197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661401394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.1661401394
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.386250976
Short name T451
Test name
Test status
Simulation time 69534695 ps
CPU time 1.68 seconds
Started Jun 23 05:36:42 PM PDT 24
Finished Jun 23 05:36:44 PM PDT 24
Peak memory 218060 kb
Host smart-4df57220-db7b-4a2f-84cc-2880dd2fb766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386250976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.386250976
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.1432130057
Short name T417
Test name
Test status
Simulation time 187651105 ps
CPU time 1.25 seconds
Started Jun 23 05:36:41 PM PDT 24
Finished Jun 23 05:36:43 PM PDT 24
Peak memory 220092 kb
Host smart-675953a2-5e04-4b92-84ba-9324c1c7b66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432130057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.1432130057
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.3372473855
Short name T674
Test name
Test status
Simulation time 44377442 ps
CPU time 1.58 seconds
Started Jun 23 05:36:39 PM PDT 24
Finished Jun 23 05:36:41 PM PDT 24
Peak memory 217856 kb
Host smart-96c5f52c-8dc0-462a-a8d3-803d32371295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372473855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3372473855
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2568155699
Short name T771
Test name
Test status
Simulation time 54029079 ps
CPU time 1.22 seconds
Started Jun 23 05:34:31 PM PDT 24
Finished Jun 23 05:34:32 PM PDT 24
Peak memory 220280 kb
Host smart-c8d7cddb-e379-4a55-ab5d-8f109e423d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568155699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2568155699
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3893930048
Short name T431
Test name
Test status
Simulation time 57260358 ps
CPU time 0.97 seconds
Started Jun 23 05:34:33 PM PDT 24
Finished Jun 23 05:34:35 PM PDT 24
Peak memory 214380 kb
Host smart-05ed13d7-583d-4189-ab5f-a0e3ad029ac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893930048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3893930048
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.1584280412
Short name T726
Test name
Test status
Simulation time 12584165 ps
CPU time 0.94 seconds
Started Jun 23 05:34:28 PM PDT 24
Finished Jun 23 05:34:29 PM PDT 24
Peak memory 215784 kb
Host smart-fb21e5ff-175c-48dd-880a-0a61e72902f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584280412 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1584280412
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1392117716
Short name T819
Test name
Test status
Simulation time 144084466 ps
CPU time 1.12 seconds
Started Jun 23 05:34:31 PM PDT 24
Finished Jun 23 05:34:33 PM PDT 24
Peak memory 216248 kb
Host smart-30457f03-4018-4eaf-8460-216b5bedfc5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392117716 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1392117716
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_genbits.1769456705
Short name T721
Test name
Test status
Simulation time 25525214 ps
CPU time 1.14 seconds
Started Jun 23 05:34:31 PM PDT 24
Finished Jun 23 05:34:33 PM PDT 24
Peak memory 216508 kb
Host smart-14a5e910-1895-447f-bc76-1305e78c912a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769456705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1769456705
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.999194604
Short name T108
Test name
Test status
Simulation time 35674231 ps
CPU time 0.95 seconds
Started Jun 23 05:34:29 PM PDT 24
Finished Jun 23 05:34:30 PM PDT 24
Peak memory 214992 kb
Host smart-867bded6-7277-4669-9160-98bd3ea895de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999194604 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.999194604
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1122339308
Short name T949
Test name
Test status
Simulation time 32210151 ps
CPU time 0.97 seconds
Started Jun 23 05:34:31 PM PDT 24
Finished Jun 23 05:34:33 PM PDT 24
Peak memory 214632 kb
Host smart-878145f1-bce0-4d29-a882-32ac9383d60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122339308 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1122339308
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3011868183
Short name T445
Test name
Test status
Simulation time 85746180 ps
CPU time 2.25 seconds
Started Jun 23 05:34:33 PM PDT 24
Finished Jun 23 05:34:35 PM PDT 24
Peak memory 214476 kb
Host smart-a822cd44-65fa-4779-a071-7fce4928077f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011868183 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3011868183
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1694994041
Short name T398
Test name
Test status
Simulation time 49576351260 ps
CPU time 615.96 seconds
Started Jun 23 05:34:29 PM PDT 24
Finished Jun 23 05:44:46 PM PDT 24
Peak memory 223024 kb
Host smart-d5a981c8-6c32-4856-aae2-95c69a18ade8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694994041 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1694994041
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.2498939292
Short name T560
Test name
Test status
Simulation time 87790506 ps
CPU time 1.46 seconds
Started Jun 23 05:36:43 PM PDT 24
Finished Jun 23 05:36:45 PM PDT 24
Peak memory 218204 kb
Host smart-51423287-31bc-49d0-a655-3423a18c6b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498939292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2498939292
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.3788069323
Short name T137
Test name
Test status
Simulation time 28270958 ps
CPU time 1.3 seconds
Started Jun 23 05:36:37 PM PDT 24
Finished Jun 23 05:36:39 PM PDT 24
Peak memory 219168 kb
Host smart-7587c18c-e9bc-4f45-a211-65d7c944fd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788069323 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.3788069323
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.478225915
Short name T536
Test name
Test status
Simulation time 116617283 ps
CPU time 1.34 seconds
Started Jun 23 05:36:40 PM PDT 24
Finished Jun 23 05:36:42 PM PDT 24
Peak memory 216620 kb
Host smart-b7efe03b-e484-4466-8b35-a05936a5c222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478225915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.478225915
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.3610827635
Short name T64
Test name
Test status
Simulation time 99491832 ps
CPU time 1.21 seconds
Started Jun 23 05:36:43 PM PDT 24
Finished Jun 23 05:36:44 PM PDT 24
Peak memory 219276 kb
Host smart-500cde5f-dc6d-4310-b3d1-f4f395e29f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610827635 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.3610827635
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.188071647
Short name T941
Test name
Test status
Simulation time 102685503 ps
CPU time 1.24 seconds
Started Jun 23 05:36:38 PM PDT 24
Finished Jun 23 05:36:40 PM PDT 24
Peak memory 217812 kb
Host smart-e4a16a5c-3e7d-4407-8c13-f9610518aed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188071647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.188071647
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.3384049560
Short name T280
Test name
Test status
Simulation time 282090096 ps
CPU time 1.23 seconds
Started Jun 23 05:36:41 PM PDT 24
Finished Jun 23 05:36:43 PM PDT 24
Peak memory 219172 kb
Host smart-9999ec5b-481a-4f57-85ee-38758625f54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384049560 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.3384049560
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.3546648506
Short name T310
Test name
Test status
Simulation time 62309441 ps
CPU time 1.76 seconds
Started Jun 23 05:36:41 PM PDT 24
Finished Jun 23 05:36:44 PM PDT 24
Peak memory 218032 kb
Host smart-bac59478-8ff1-470e-82a7-457688c5a7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546648506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3546648506
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.4130866951
Short name T31
Test name
Test status
Simulation time 63359091 ps
CPU time 1.09 seconds
Started Jun 23 05:36:40 PM PDT 24
Finished Jun 23 05:36:42 PM PDT 24
Peak memory 218824 kb
Host smart-215a29e5-c411-44b4-9417-0ff158bf93b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130866951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.4130866951
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.3086573147
Short name T333
Test name
Test status
Simulation time 55076076 ps
CPU time 1.19 seconds
Started Jun 23 05:36:40 PM PDT 24
Finished Jun 23 05:36:42 PM PDT 24
Peak memory 216656 kb
Host smart-e7b305d8-302c-44bc-8c54-2a8122bb6773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086573147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3086573147
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.845185205
Short name T85
Test name
Test status
Simulation time 84234365 ps
CPU time 1.13 seconds
Started Jun 23 05:36:43 PM PDT 24
Finished Jun 23 05:36:45 PM PDT 24
Peak memory 219684 kb
Host smart-18bb77b0-f63c-40d5-82bc-1bd6f41b02f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845185205 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.845185205
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.621709368
Short name T583
Test name
Test status
Simulation time 38425621 ps
CPU time 1.47 seconds
Started Jun 23 05:36:42 PM PDT 24
Finished Jun 23 05:36:44 PM PDT 24
Peak memory 217944 kb
Host smart-39da98e5-235c-4025-9496-c81cafb0569e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621709368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.621709368
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.3880898332
Short name T226
Test name
Test status
Simulation time 93562187 ps
CPU time 1.12 seconds
Started Jun 23 05:36:43 PM PDT 24
Finished Jun 23 05:36:45 PM PDT 24
Peak memory 218460 kb
Host smart-1d7d617b-4b2f-46a6-bca6-7eeb518003d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880898332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.3880898332
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.4252582821
Short name T615
Test name
Test status
Simulation time 45394745 ps
CPU time 1.56 seconds
Started Jun 23 05:36:43 PM PDT 24
Finished Jun 23 05:36:46 PM PDT 24
Peak memory 216552 kb
Host smart-9b6228a7-50f0-4666-8963-71f1378165f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252582821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.4252582821
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.2072264450
Short name T593
Test name
Test status
Simulation time 54707653 ps
CPU time 2.11 seconds
Started Jun 23 05:36:42 PM PDT 24
Finished Jun 23 05:36:45 PM PDT 24
Peak memory 219504 kb
Host smart-d351c3a4-80d8-45eb-b8f7-88be4a218b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072264450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2072264450
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.3671143099
Short name T765
Test name
Test status
Simulation time 60055468 ps
CPU time 1.26 seconds
Started Jun 23 05:36:44 PM PDT 24
Finished Jun 23 05:36:47 PM PDT 24
Peak memory 219580 kb
Host smart-165f3ce5-2a4c-4628-9078-1895d138b923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671143099 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.3671143099
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/169.edn_alert.951444023
Short name T816
Test name
Test status
Simulation time 83899622 ps
CPU time 1.18 seconds
Started Jun 23 05:36:43 PM PDT 24
Finished Jun 23 05:36:45 PM PDT 24
Peak memory 215072 kb
Host smart-568ef7d7-d9a2-4908-a0f5-d84b48373f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951444023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.951444023
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.2641229595
Short name T917
Test name
Test status
Simulation time 78417376 ps
CPU time 1.63 seconds
Started Jun 23 05:36:45 PM PDT 24
Finished Jun 23 05:36:48 PM PDT 24
Peak memory 219412 kb
Host smart-98a44def-804d-4ac4-a563-059e355c4027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641229595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2641229595
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2706095614
Short name T224
Test name
Test status
Simulation time 25088455 ps
CPU time 1.24 seconds
Started Jun 23 05:34:29 PM PDT 24
Finished Jun 23 05:34:30 PM PDT 24
Peak memory 219196 kb
Host smart-37d8b1f0-6c64-43f3-a063-8da0a594a442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706095614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2706095614
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3910390720
Short name T755
Test name
Test status
Simulation time 57058189 ps
CPU time 0.89 seconds
Started Jun 23 05:34:35 PM PDT 24
Finished Jun 23 05:34:36 PM PDT 24
Peak memory 206104 kb
Host smart-61fa7287-b14b-4ecd-9307-d4260e90e167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910390720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3910390720
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1060405679
Short name T739
Test name
Test status
Simulation time 23864125 ps
CPU time 1.03 seconds
Started Jun 23 05:34:32 PM PDT 24
Finished Jun 23 05:34:34 PM PDT 24
Peak memory 216312 kb
Host smart-a926981a-e0a8-4253-903d-582051e0a83f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060405679 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1060405679
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1917148250
Short name T362
Test name
Test status
Simulation time 19036982 ps
CPU time 1.01 seconds
Started Jun 23 05:34:42 PM PDT 24
Finished Jun 23 05:34:44 PM PDT 24
Peak memory 217628 kb
Host smart-5a43b495-2ca0-469e-8a72-34243dbcb0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917148250 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1917148250
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.419057434
Short name T712
Test name
Test status
Simulation time 90059189 ps
CPU time 1.99 seconds
Started Jun 23 05:34:33 PM PDT 24
Finished Jun 23 05:34:35 PM PDT 24
Peak memory 214560 kb
Host smart-1b78b481-d284-45d3-922c-99baf73a9270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419057434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.419057434
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.2514981324
Short name T507
Test name
Test status
Simulation time 91681187 ps
CPU time 0.87 seconds
Started Jun 23 05:34:32 PM PDT 24
Finished Jun 23 05:34:34 PM PDT 24
Peak memory 214608 kb
Host smart-0d9d0fd1-b0cb-45eb-840e-5570213297ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514981324 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2514981324
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2026712436
Short name T829
Test name
Test status
Simulation time 17025520 ps
CPU time 1.01 seconds
Started Jun 23 05:34:31 PM PDT 24
Finished Jun 23 05:34:33 PM PDT 24
Peak memory 214628 kb
Host smart-58c0b141-ccb4-4916-bf9e-2573298e2172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026712436 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2026712436
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1024725628
Short name T601
Test name
Test status
Simulation time 192854002 ps
CPU time 1.47 seconds
Started Jun 23 05:34:30 PM PDT 24
Finished Jun 23 05:34:32 PM PDT 24
Peak memory 217792 kb
Host smart-5e4d226a-5d59-486c-8517-f9ece035d8fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024725628 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1024725628
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2156401088
Short name T450
Test name
Test status
Simulation time 61146024055 ps
CPU time 1461.78 seconds
Started Jun 23 05:34:29 PM PDT 24
Finished Jun 23 05:58:51 PM PDT 24
Peak memory 223020 kb
Host smart-a9c63704-04de-444b-8c1c-8ed313404600
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156401088 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2156401088
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.3581135861
Short name T700
Test name
Test status
Simulation time 80990003 ps
CPU time 1.16 seconds
Started Jun 23 05:36:44 PM PDT 24
Finished Jun 23 05:36:45 PM PDT 24
Peak memory 218260 kb
Host smart-729d1c6b-3f77-4638-8a0d-663b0e08b1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581135861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.3581135861
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.4024295672
Short name T396
Test name
Test status
Simulation time 74207000 ps
CPU time 1.07 seconds
Started Jun 23 05:36:43 PM PDT 24
Finished Jun 23 05:36:45 PM PDT 24
Peak memory 216696 kb
Host smart-98847ed6-5f1c-40c7-92f2-642c8c7f29e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024295672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.4024295672
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.1061689903
Short name T657
Test name
Test status
Simulation time 47387279 ps
CPU time 1.2 seconds
Started Jun 23 05:36:52 PM PDT 24
Finished Jun 23 05:36:53 PM PDT 24
Peak memory 218120 kb
Host smart-61812d02-c1da-4783-98fc-c2e3ff6ce505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061689903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.1061689903
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.1588872994
Short name T933
Test name
Test status
Simulation time 36967434 ps
CPU time 1.28 seconds
Started Jun 23 05:36:42 PM PDT 24
Finished Jun 23 05:36:44 PM PDT 24
Peak memory 218188 kb
Host smart-9c578e48-30b6-41fc-88c3-a1707a24cde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588872994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1588872994
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1057392702
Short name T650
Test name
Test status
Simulation time 25627763 ps
CPU time 1.23 seconds
Started Jun 23 05:36:46 PM PDT 24
Finished Jun 23 05:36:48 PM PDT 24
Peak memory 218208 kb
Host smart-557194d2-7a50-40a0-9931-4756c63a74c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057392702 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1057392702
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.3789626371
Short name T889
Test name
Test status
Simulation time 42895148 ps
CPU time 1.53 seconds
Started Jun 23 05:36:46 PM PDT 24
Finished Jun 23 05:36:48 PM PDT 24
Peak memory 216516 kb
Host smart-499bf262-2c82-48e3-a7c5-ebb5477d9d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789626371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3789626371
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.375304095
Short name T155
Test name
Test status
Simulation time 28237102 ps
CPU time 1.22 seconds
Started Jun 23 05:36:46 PM PDT 24
Finished Jun 23 05:36:48 PM PDT 24
Peak memory 219012 kb
Host smart-d531c083-1f2e-4e80-bbf5-f9a00fc907a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375304095 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.375304095
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.1666897254
Short name T955
Test name
Test status
Simulation time 178069886 ps
CPU time 3.57 seconds
Started Jun 23 05:36:43 PM PDT 24
Finished Jun 23 05:36:47 PM PDT 24
Peak memory 219108 kb
Host smart-0495387b-0d1e-47d5-9058-7b2e52929df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666897254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1666897254
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.4248465181
Short name T518
Test name
Test status
Simulation time 75967367 ps
CPU time 1.15 seconds
Started Jun 23 05:36:43 PM PDT 24
Finished Jun 23 05:36:45 PM PDT 24
Peak memory 219364 kb
Host smart-57614f66-d9eb-4354-96f4-798533851990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248465181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.4248465181
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.2942912782
Short name T595
Test name
Test status
Simulation time 75719381 ps
CPU time 1.18 seconds
Started Jun 23 05:36:46 PM PDT 24
Finished Jun 23 05:36:49 PM PDT 24
Peak memory 217988 kb
Host smart-17b629b2-7de3-46fd-9fe4-f63e477b6925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942912782 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.2942912782
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.3439666644
Short name T13
Test name
Test status
Simulation time 149574127 ps
CPU time 1.29 seconds
Started Jun 23 05:36:43 PM PDT 24
Finished Jun 23 05:36:45 PM PDT 24
Peak memory 219000 kb
Host smart-d0e2197b-a25f-4a92-b606-94916ec22086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439666644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3439666644
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.2568098283
Short name T425
Test name
Test status
Simulation time 59915802 ps
CPU time 1.13 seconds
Started Jun 23 05:36:46 PM PDT 24
Finished Jun 23 05:36:48 PM PDT 24
Peak memory 220032 kb
Host smart-12b068a2-7b87-4041-bb10-8c2ba3e783eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568098283 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2568098283
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.3338995710
Short name T556
Test name
Test status
Simulation time 142564440 ps
CPU time 3.03 seconds
Started Jun 23 05:36:44 PM PDT 24
Finished Jun 23 05:36:48 PM PDT 24
Peak memory 217904 kb
Host smart-7c2ab5b6-6c77-493d-b8c3-8f56c66020d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338995710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3338995710
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.1255668244
Short name T444
Test name
Test status
Simulation time 77100053 ps
CPU time 1.16 seconds
Started Jun 23 05:36:44 PM PDT 24
Finished Jun 23 05:36:46 PM PDT 24
Peak memory 220200 kb
Host smart-204aec34-1ee8-4e4c-9990-e42d23ad052a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255668244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.1255668244
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.2884683593
Short name T562
Test name
Test status
Simulation time 174659359 ps
CPU time 2.4 seconds
Started Jun 23 05:36:49 PM PDT 24
Finished Jun 23 05:36:52 PM PDT 24
Peak memory 219340 kb
Host smart-542c6c0e-f767-4886-a779-6be68781c44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884683593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2884683593
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.3364009348
Short name T372
Test name
Test status
Simulation time 67344392 ps
CPU time 0.95 seconds
Started Jun 23 05:36:44 PM PDT 24
Finished Jun 23 05:36:46 PM PDT 24
Peak memory 214736 kb
Host smart-ceb0b6f5-9f3b-4230-a6e0-b81c2700509d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364009348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3364009348
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.236253677
Short name T441
Test name
Test status
Simulation time 78952501 ps
CPU time 1.15 seconds
Started Jun 23 05:36:47 PM PDT 24
Finished Jun 23 05:36:49 PM PDT 24
Peak memory 217760 kb
Host smart-d2574e08-2e6a-42d4-ad1e-5d446066a067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236253677 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.236253677
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.1050071116
Short name T855
Test name
Test status
Simulation time 148064487 ps
CPU time 3 seconds
Started Jun 23 05:36:43 PM PDT 24
Finished Jun 23 05:36:47 PM PDT 24
Peak memory 217844 kb
Host smart-461a12a9-8234-4192-8bde-5eeaf0b80db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050071116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1050071116
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.321695401
Short name T416
Test name
Test status
Simulation time 33067986 ps
CPU time 1.41 seconds
Started Jun 23 05:34:35 PM PDT 24
Finished Jun 23 05:34:37 PM PDT 24
Peak memory 215100 kb
Host smart-f9df7184-742f-41e0-afd1-4c2196f55ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321695401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.321695401
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1795027419
Short name T574
Test name
Test status
Simulation time 20656951 ps
CPU time 0.92 seconds
Started Jun 23 05:34:33 PM PDT 24
Finished Jun 23 05:34:35 PM PDT 24
Peak memory 206148 kb
Host smart-b8f9bdd0-faae-495e-9348-6efe977cf747
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795027419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1795027419
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.324447110
Short name T215
Test name
Test status
Simulation time 11273212 ps
CPU time 0.91 seconds
Started Jun 23 05:34:34 PM PDT 24
Finished Jun 23 05:34:35 PM PDT 24
Peak memory 215792 kb
Host smart-10c95524-4499-4a5c-9d61-8aa01e029d3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324447110 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.324447110
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.2565753065
Short name T385
Test name
Test status
Simulation time 47275970 ps
CPU time 0.83 seconds
Started Jun 23 05:34:33 PM PDT 24
Finished Jun 23 05:34:34 PM PDT 24
Peak memory 217748 kb
Host smart-e9dbff22-145d-4a08-87c3-fb5d31e88e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565753065 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2565753065
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1196205371
Short name T773
Test name
Test status
Simulation time 90947306 ps
CPU time 1.4 seconds
Started Jun 23 05:34:36 PM PDT 24
Finished Jun 23 05:34:38 PM PDT 24
Peak memory 216900 kb
Host smart-49b5c50f-7929-4672-bdb6-09c9c97eea5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196205371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1196205371
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.380979316
Short name T539
Test name
Test status
Simulation time 40586017 ps
CPU time 1.05 seconds
Started Jun 23 05:34:35 PM PDT 24
Finished Jun 23 05:34:37 PM PDT 24
Peak memory 223184 kb
Host smart-373762cb-4d84-4d45-ad99-6ff9a06f0421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380979316 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.380979316
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3281106266
Short name T340
Test name
Test status
Simulation time 15666572 ps
CPU time 0.97 seconds
Started Jun 23 05:34:35 PM PDT 24
Finished Jun 23 05:34:37 PM PDT 24
Peak memory 206436 kb
Host smart-800d3ddf-6213-47d8-97e3-c56d283ed560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281106266 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3281106266
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2223046697
Short name T249
Test name
Test status
Simulation time 968346576 ps
CPU time 5.21 seconds
Started Jun 23 05:34:34 PM PDT 24
Finished Jun 23 05:34:40 PM PDT 24
Peak memory 214656 kb
Host smart-b027fb81-8c12-4d6d-88e8-60d467f7720c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223046697 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2223046697
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2667639368
Short name T235
Test name
Test status
Simulation time 161967826531 ps
CPU time 1572.9 seconds
Started Jun 23 05:34:34 PM PDT 24
Finished Jun 23 06:00:48 PM PDT 24
Peak memory 223840 kb
Host smart-d4469936-ee1b-4bd8-8627-e82c70c78cf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667639368 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2667639368
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.2890131384
Short name T299
Test name
Test status
Simulation time 61016580 ps
CPU time 1.32 seconds
Started Jun 23 05:36:52 PM PDT 24
Finished Jun 23 05:36:54 PM PDT 24
Peak memory 215100 kb
Host smart-e32fbe87-f3db-4252-b5f0-871d29398aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890131384 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.2890131384
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.4122063782
Short name T782
Test name
Test status
Simulation time 44530032 ps
CPU time 1.12 seconds
Started Jun 23 05:36:53 PM PDT 24
Finished Jun 23 05:36:55 PM PDT 24
Peak memory 216636 kb
Host smart-9d50fbb6-d2b5-4b71-819e-5f6e3f9a3442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122063782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.4122063782
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.2744233831
Short name T835
Test name
Test status
Simulation time 41112747 ps
CPU time 1.14 seconds
Started Jun 23 05:36:53 PM PDT 24
Finished Jun 23 05:36:54 PM PDT 24
Peak memory 218188 kb
Host smart-ba97066a-e0f8-42a3-9051-8c48e826f586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744233831 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.2744233831
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.4036035246
Short name T402
Test name
Test status
Simulation time 92928891 ps
CPU time 1.5 seconds
Started Jun 23 05:36:53 PM PDT 24
Finished Jun 23 05:36:55 PM PDT 24
Peak memory 218056 kb
Host smart-489f27a8-0add-409e-a683-ba014b731309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036035246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.4036035246
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.2980515648
Short name T970
Test name
Test status
Simulation time 29161064 ps
CPU time 1.06 seconds
Started Jun 23 05:36:45 PM PDT 24
Finished Jun 23 05:36:47 PM PDT 24
Peak memory 219000 kb
Host smart-129b4a8b-4dfd-49a2-839c-4c3c81ae8378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980515648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2980515648
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/183.edn_alert.188025012
Short name T68
Test name
Test status
Simulation time 225721359 ps
CPU time 1.22 seconds
Started Jun 23 05:36:46 PM PDT 24
Finished Jun 23 05:36:48 PM PDT 24
Peak memory 219936 kb
Host smart-8d189de6-b3e1-4921-86a2-f7a96604e63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188025012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.188025012
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/184.edn_alert.1903302863
Short name T997
Test name
Test status
Simulation time 93716356 ps
CPU time 1.18 seconds
Started Jun 23 05:36:50 PM PDT 24
Finished Jun 23 05:36:51 PM PDT 24
Peak memory 218004 kb
Host smart-79a148f3-df37-44d4-bdbe-bcb6e359225b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903302863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.1903302863
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.2743074321
Short name T375
Test name
Test status
Simulation time 27745113 ps
CPU time 1.31 seconds
Started Jun 23 05:36:49 PM PDT 24
Finished Jun 23 05:36:51 PM PDT 24
Peak memory 217992 kb
Host smart-b729088d-e6e5-4c48-b5ea-11ece05ac9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743074321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2743074321
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.2712400936
Short name T943
Test name
Test status
Simulation time 206971264 ps
CPU time 1.24 seconds
Started Jun 23 05:36:49 PM PDT 24
Finished Jun 23 05:36:51 PM PDT 24
Peak memory 215092 kb
Host smart-3de95c81-fa15-4a84-b145-e4666bc58443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712400936 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.2712400936
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.1612288179
Short name T47
Test name
Test status
Simulation time 91567835 ps
CPU time 1.63 seconds
Started Jun 23 05:36:48 PM PDT 24
Finished Jun 23 05:36:51 PM PDT 24
Peak memory 217944 kb
Host smart-f7397d61-d045-4a21-a32f-1b325c90283a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612288179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1612288179
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.1965838600
Short name T198
Test name
Test status
Simulation time 118337836 ps
CPU time 1.26 seconds
Started Jun 23 05:36:49 PM PDT 24
Finished Jun 23 05:36:51 PM PDT 24
Peak memory 220196 kb
Host smart-ccbc0b39-ef10-46ab-9d8a-f65354e3a60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965838600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.1965838600
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/187.edn_alert.550012499
Short name T170
Test name
Test status
Simulation time 51189181 ps
CPU time 1.33 seconds
Started Jun 23 05:36:52 PM PDT 24
Finished Jun 23 05:36:53 PM PDT 24
Peak memory 218148 kb
Host smart-09e5925b-2ce2-4e7d-89ab-bd63d8b792b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550012499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.550012499
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.4068876737
Short name T395
Test name
Test status
Simulation time 33375926 ps
CPU time 1.31 seconds
Started Jun 23 05:36:48 PM PDT 24
Finished Jun 23 05:36:50 PM PDT 24
Peak memory 217788 kb
Host smart-534d5739-079d-4010-834f-4c8a20c31d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068876737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.4068876737
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.1453430089
Short name T616
Test name
Test status
Simulation time 86004244 ps
CPU time 1.09 seconds
Started Jun 23 05:36:52 PM PDT 24
Finished Jun 23 05:36:53 PM PDT 24
Peak memory 219212 kb
Host smart-10fdb699-2470-4cdc-b0e7-7a8c9c61c3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453430089 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.1453430089
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/189.edn_alert.285721755
Short name T977
Test name
Test status
Simulation time 59437399 ps
CPU time 1.27 seconds
Started Jun 23 05:36:48 PM PDT 24
Finished Jun 23 05:36:50 PM PDT 24
Peak memory 220528 kb
Host smart-5a04f829-b7f5-4055-8946-32bb598dc027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285721755 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.285721755
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.4227994871
Short name T741
Test name
Test status
Simulation time 39458560 ps
CPU time 1.51 seconds
Started Jun 23 05:36:51 PM PDT 24
Finished Jun 23 05:36:53 PM PDT 24
Peak memory 219176 kb
Host smart-cec16b35-3f9b-4ce0-8fab-5eb9f5510aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227994871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.4227994871
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.4275982002
Short name T534
Test name
Test status
Simulation time 38754301 ps
CPU time 1.19 seconds
Started Jun 23 05:34:36 PM PDT 24
Finished Jun 23 05:34:38 PM PDT 24
Peak memory 219136 kb
Host smart-bf8c34a2-63f2-4e8c-97f6-ff6d9016f504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275982002 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.4275982002
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1558145824
Short name T459
Test name
Test status
Simulation time 20900472 ps
CPU time 0.96 seconds
Started Jun 23 05:34:41 PM PDT 24
Finished Jun 23 05:34:43 PM PDT 24
Peak memory 214620 kb
Host smart-d0b5e754-551c-4274-a637-553c393aa4e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558145824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1558145824
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1643768887
Short name T477
Test name
Test status
Simulation time 50182115 ps
CPU time 0.89 seconds
Started Jun 23 05:34:34 PM PDT 24
Finished Jun 23 05:34:36 PM PDT 24
Peak memory 215780 kb
Host smart-3e5184ce-9bc1-48fa-940a-4ce4e9037c4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643768887 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1643768887
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.788333082
Short name T165
Test name
Test status
Simulation time 228056425 ps
CPU time 1.13 seconds
Started Jun 23 05:34:51 PM PDT 24
Finished Jun 23 05:34:53 PM PDT 24
Peak memory 216228 kb
Host smart-87a763a8-57b0-4fc9-a24e-46b615ced8c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788333082 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.788333082
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1523507820
Short name T15
Test name
Test status
Simulation time 193133919 ps
CPU time 1.15 seconds
Started Jun 23 05:34:35 PM PDT 24
Finished Jun 23 05:34:37 PM PDT 24
Peak memory 224976 kb
Host smart-32473053-866e-4f43-a591-38b31a4fd60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523507820 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1523507820
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1021287572
Short name T681
Test name
Test status
Simulation time 259452893 ps
CPU time 2.98 seconds
Started Jun 23 05:34:41 PM PDT 24
Finished Jun 23 05:34:45 PM PDT 24
Peak memory 218016 kb
Host smart-ed24cde2-dca8-40e8-82b9-db013c833fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021287572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1021287572
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_smoke.137372805
Short name T354
Test name
Test status
Simulation time 26996068 ps
CPU time 0.92 seconds
Started Jun 23 05:34:40 PM PDT 24
Finished Jun 23 05:34:42 PM PDT 24
Peak memory 214656 kb
Host smart-0c2412f6-2943-4a4b-a366-2a04a0f76038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137372805 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.137372805
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2155810783
Short name T422
Test name
Test status
Simulation time 519164005 ps
CPU time 5.44 seconds
Started Jun 23 05:34:34 PM PDT 24
Finished Jun 23 05:34:40 PM PDT 24
Peak memory 214660 kb
Host smart-2d3464f0-1b96-489f-95aa-0c011324d0e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155810783 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2155810783
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2655101761
Short name T859
Test name
Test status
Simulation time 291475992055 ps
CPU time 1054.49 seconds
Started Jun 23 05:34:41 PM PDT 24
Finished Jun 23 05:52:17 PM PDT 24
Peak memory 222996 kb
Host smart-763bbbf0-6b73-42a4-96d4-4035945388cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655101761 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2655101761
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.537169641
Short name T642
Test name
Test status
Simulation time 95973814 ps
CPU time 1.25 seconds
Started Jun 23 05:36:47 PM PDT 24
Finished Jun 23 05:36:49 PM PDT 24
Peak memory 219996 kb
Host smart-5077d4d3-0d3a-43b0-9367-dd4aa770906f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537169641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.537169641
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3847715368
Short name T570
Test name
Test status
Simulation time 96470237 ps
CPU time 1.27 seconds
Started Jun 23 05:36:47 PM PDT 24
Finished Jun 23 05:36:49 PM PDT 24
Peak memory 217808 kb
Host smart-3106306a-acb7-40e4-8df7-3382fc693069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847715368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3847715368
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.780033544
Short name T848
Test name
Test status
Simulation time 111401258 ps
CPU time 1.16 seconds
Started Jun 23 05:36:54 PM PDT 24
Finished Jun 23 05:36:55 PM PDT 24
Peak memory 217748 kb
Host smart-d9b49fc8-01cb-4f96-9fe3-e0d8cf8bc1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780033544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.780033544
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.66156865
Short name T364
Test name
Test status
Simulation time 143721003 ps
CPU time 1.4 seconds
Started Jun 23 05:36:51 PM PDT 24
Finished Jun 23 05:36:53 PM PDT 24
Peak memory 218048 kb
Host smart-0e05b743-be4a-4d73-bb93-0913b58372c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66156865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.66156865
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.3582411173
Short name T815
Test name
Test status
Simulation time 103970987 ps
CPU time 1.19 seconds
Started Jun 23 05:36:54 PM PDT 24
Finished Jun 23 05:36:56 PM PDT 24
Peak memory 220256 kb
Host smart-4c62d926-6eca-4c63-9749-b654344b4ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582411173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3582411173
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.2981634381
Short name T481
Test name
Test status
Simulation time 69157188 ps
CPU time 2.52 seconds
Started Jun 23 05:36:56 PM PDT 24
Finished Jun 23 05:36:59 PM PDT 24
Peak memory 216908 kb
Host smart-838776f8-5c60-412a-9609-0a2c00c0cc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981634381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2981634381
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.2978131246
Short name T684
Test name
Test status
Simulation time 36973185 ps
CPU time 1.11 seconds
Started Jun 23 05:36:54 PM PDT 24
Finished Jun 23 05:36:55 PM PDT 24
Peak memory 216612 kb
Host smart-8f6b339c-9504-466d-9b82-22c78f2ec32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978131246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2978131246
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.3760220873
Short name T880
Test name
Test status
Simulation time 22309358 ps
CPU time 1.11 seconds
Started Jun 23 05:36:52 PM PDT 24
Finished Jun 23 05:36:53 PM PDT 24
Peak memory 217848 kb
Host smart-9f2f0cc4-8284-43b6-80d1-cac4c387e853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760220873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.3760220873
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.741621312
Short name T794
Test name
Test status
Simulation time 72350547 ps
CPU time 1.08 seconds
Started Jun 23 05:36:56 PM PDT 24
Finished Jun 23 05:36:57 PM PDT 24
Peak memory 216644 kb
Host smart-d9cae236-db1d-48de-a5a5-2a6d74650481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741621312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.741621312
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.4182531150
Short name T711
Test name
Test status
Simulation time 185258981 ps
CPU time 1.45 seconds
Started Jun 23 05:36:55 PM PDT 24
Finished Jun 23 05:36:57 PM PDT 24
Peak memory 218036 kb
Host smart-28dd793b-9679-49d6-87e5-5a7a1545695e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182531150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.4182531150
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.27813315
Short name T514
Test name
Test status
Simulation time 32917818 ps
CPU time 1.29 seconds
Started Jun 23 05:36:56 PM PDT 24
Finished Jun 23 05:36:58 PM PDT 24
Peak memory 217888 kb
Host smart-bc39758e-dfd4-4bbd-8e35-16ca7d4aedc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27813315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.27813315
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.1413464980
Short name T62
Test name
Test status
Simulation time 52995520 ps
CPU time 1.31 seconds
Started Jun 23 05:36:50 PM PDT 24
Finished Jun 23 05:36:52 PM PDT 24
Peak memory 215088 kb
Host smart-ceeb098d-9bb3-4598-a10f-c8bb1f626c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413464980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.1413464980
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.620745805
Short name T724
Test name
Test status
Simulation time 56693385 ps
CPU time 1.27 seconds
Started Jun 23 05:36:56 PM PDT 24
Finished Jun 23 05:36:58 PM PDT 24
Peak memory 216660 kb
Host smart-9ad21273-104e-4ed7-909e-b2f63863b0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620745805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.620745805
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.4740967
Short name T854
Test name
Test status
Simulation time 230712108 ps
CPU time 1.32 seconds
Started Jun 23 05:36:55 PM PDT 24
Finished Jun 23 05:36:56 PM PDT 24
Peak memory 218680 kb
Host smart-23337888-7739-4b70-82bf-f4215c1d748f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4740967 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.4740967
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.457791729
Short name T544
Test name
Test status
Simulation time 151674806 ps
CPU time 1.76 seconds
Started Jun 23 05:36:55 PM PDT 24
Finished Jun 23 05:36:57 PM PDT 24
Peak memory 219356 kb
Host smart-909415e7-6027-4495-8690-91db9eb33af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457791729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.457791729
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.1197781991
Short name T138
Test name
Test status
Simulation time 38053012 ps
CPU time 1.18 seconds
Started Jun 23 05:36:53 PM PDT 24
Finished Jun 23 05:36:54 PM PDT 24
Peak memory 219712 kb
Host smart-bacc35c5-08b7-4b24-a231-604e0df4ae25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197781991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.1197781991
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.1982558359
Short name T636
Test name
Test status
Simulation time 56217353 ps
CPU time 1.42 seconds
Started Jun 23 05:36:52 PM PDT 24
Finished Jun 23 05:36:54 PM PDT 24
Peak memory 218068 kb
Host smart-94f6c376-d712-4c91-ba44-f775b98457b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982558359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1982558359
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.1795504444
Short name T380
Test name
Test status
Simulation time 182477233 ps
CPU time 1.23 seconds
Started Jun 23 05:36:55 PM PDT 24
Finished Jun 23 05:36:57 PM PDT 24
Peak memory 217780 kb
Host smart-d99b0fe0-4de0-498b-8717-ca56bfb822e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795504444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.1795504444
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.3160693378
Short name T659
Test name
Test status
Simulation time 49860611 ps
CPU time 1.79 seconds
Started Jun 23 05:36:51 PM PDT 24
Finished Jun 23 05:36:54 PM PDT 24
Peak memory 217896 kb
Host smart-4e05c83b-fc99-4ae2-8a93-67253a2e5b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160693378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3160693378
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1659297295
Short name T190
Test name
Test status
Simulation time 384757072 ps
CPU time 1.39 seconds
Started Jun 23 05:33:53 PM PDT 24
Finished Jun 23 05:33:54 PM PDT 24
Peak memory 219008 kb
Host smart-29037dcd-f511-4d20-9a98-e37c6ce49906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659297295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1659297295
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3721007736
Short name T605
Test name
Test status
Simulation time 45640189 ps
CPU time 0.97 seconds
Started Jun 23 05:33:53 PM PDT 24
Finished Jun 23 05:33:54 PM PDT 24
Peak memory 206156 kb
Host smart-42598003-f7de-4d9a-88af-255003173903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721007736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3721007736
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.742569519
Short name T750
Test name
Test status
Simulation time 37053314 ps
CPU time 1.05 seconds
Started Jun 23 05:33:54 PM PDT 24
Finished Jun 23 05:33:55 PM PDT 24
Peak memory 218956 kb
Host smart-b0ed622d-00ab-418a-ad1e-9bca19cfed35
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742569519 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.742569519
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3710792527
Short name T457
Test name
Test status
Simulation time 22781438 ps
CPU time 0.99 seconds
Started Jun 23 05:33:56 PM PDT 24
Finished Jun 23 05:33:57 PM PDT 24
Peak memory 218240 kb
Host smart-3ccb4756-1800-4b3b-9f00-7bcf33ad0c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710792527 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3710792527
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.2107033834
Short name T793
Test name
Test status
Simulation time 34241667 ps
CPU time 1.23 seconds
Started Jun 23 05:33:49 PM PDT 24
Finished Jun 23 05:33:50 PM PDT 24
Peak memory 216632 kb
Host smart-ba58aa7a-208b-4b2e-b20b-a00ba3c6636b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107033834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2107033834
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2543930168
Short name T3
Test name
Test status
Simulation time 64179024 ps
CPU time 0.83 seconds
Started Jun 23 05:34:06 PM PDT 24
Finished Jun 23 05:34:07 PM PDT 24
Peak memory 214808 kb
Host smart-96082331-f875-4875-8acd-4b6b907c9ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543930168 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2543930168
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2304764209
Short name T533
Test name
Test status
Simulation time 18470374 ps
CPU time 1 seconds
Started Jun 23 05:33:54 PM PDT 24
Finished Jun 23 05:33:56 PM PDT 24
Peak memory 206544 kb
Host smart-aae9bba6-a5f9-4551-a393-225bb33b5a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304764209 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2304764209
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.3144678593
Short name T735
Test name
Test status
Simulation time 18358677 ps
CPU time 1.09 seconds
Started Jun 23 05:34:00 PM PDT 24
Finished Jun 23 05:34:02 PM PDT 24
Peak memory 214596 kb
Host smart-72e1a88b-dfb5-447d-a4db-9fd3aa28e8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144678593 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3144678593
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3048319666
Short name T745
Test name
Test status
Simulation time 323769534 ps
CPU time 2.49 seconds
Started Jun 23 05:34:00 PM PDT 24
Finished Jun 23 05:34:04 PM PDT 24
Peak memory 216652 kb
Host smart-bde5e70c-43ae-4579-b23a-7eb734d943aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048319666 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3048319666
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.385309722
Short name T925
Test name
Test status
Simulation time 53392573283 ps
CPU time 1223.76 seconds
Started Jun 23 05:33:51 PM PDT 24
Finished Jun 23 05:54:15 PM PDT 24
Peak memory 220764 kb
Host smart-d60ee47b-a923-4389-a538-6eded60f709f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385309722 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.385309722
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3577857213
Short name T976
Test name
Test status
Simulation time 25097442 ps
CPU time 1.22 seconds
Started Jun 23 05:34:39 PM PDT 24
Finished Jun 23 05:34:41 PM PDT 24
Peak memory 219036 kb
Host smart-6b4dc216-bc75-4c72-a375-674d1139c322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577857213 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3577857213
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3590895943
Short name T928
Test name
Test status
Simulation time 34987386 ps
CPU time 0.87 seconds
Started Jun 23 05:34:42 PM PDT 24
Finished Jun 23 05:34:43 PM PDT 24
Peak memory 206100 kb
Host smart-abde5014-e4b9-4dff-9f72-9d6656c6a899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590895943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3590895943
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3804888730
Short name T70
Test name
Test status
Simulation time 11247852 ps
CPU time 0.88 seconds
Started Jun 23 05:34:42 PM PDT 24
Finished Jun 23 05:34:44 PM PDT 24
Peak memory 215568 kb
Host smart-c767b48e-6065-4da7-9116-aa51196d7d2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804888730 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3804888730
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2517194262
Short name T161
Test name
Test status
Simulation time 255883491 ps
CPU time 1.26 seconds
Started Jun 23 05:34:43 PM PDT 24
Finished Jun 23 05:34:44 PM PDT 24
Peak memory 216244 kb
Host smart-0f5c0a6a-8954-4936-b4c9-3f590ceee541
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517194262 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2517194262
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2211952856
Short name T164
Test name
Test status
Simulation time 40934794 ps
CPU time 1.14 seconds
Started Jun 23 05:34:38 PM PDT 24
Finished Jun 23 05:34:40 PM PDT 24
Peak memory 219836 kb
Host smart-7504fff0-9930-4cee-b2a1-ed86960e3f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211952856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2211952856
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2650373446
Short name T241
Test name
Test status
Simulation time 93548657 ps
CPU time 1.12 seconds
Started Jun 23 05:34:37 PM PDT 24
Finished Jun 23 05:34:38 PM PDT 24
Peak memory 217944 kb
Host smart-370a3833-cdea-4670-910a-c6e05891ba52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650373446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2650373446
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1640340841
Short name T690
Test name
Test status
Simulation time 35012009 ps
CPU time 1 seconds
Started Jun 23 05:34:43 PM PDT 24
Finished Jun 23 05:34:44 PM PDT 24
Peak memory 223380 kb
Host smart-02b78605-2072-443c-8557-497e25d33a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640340841 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1640340841
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3805119732
Short name T550
Test name
Test status
Simulation time 17327539 ps
CPU time 0.98 seconds
Started Jun 23 05:34:38 PM PDT 24
Finished Jun 23 05:34:40 PM PDT 24
Peak memory 214604 kb
Host smart-a3c873a8-c0e9-4350-aaa3-727b5ed0c41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805119732 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3805119732
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.539352721
Short name T529
Test name
Test status
Simulation time 207523589 ps
CPU time 4.24 seconds
Started Jun 23 05:34:40 PM PDT 24
Finished Jun 23 05:34:44 PM PDT 24
Peak memory 216524 kb
Host smart-0427235b-338d-4ca6-8854-5b41e113f5ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539352721 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.539352721
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3483062990
Short name T446
Test name
Test status
Simulation time 120412822944 ps
CPU time 1486.95 seconds
Started Jun 23 05:34:51 PM PDT 24
Finished Jun 23 05:59:39 PM PDT 24
Peak memory 226024 kb
Host smart-8b8296bf-4074-4073-9f0b-a4664f659c7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483062990 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3483062990
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3109102098
Short name T749
Test name
Test status
Simulation time 183286121 ps
CPU time 1.23 seconds
Started Jun 23 05:36:54 PM PDT 24
Finished Jun 23 05:36:56 PM PDT 24
Peak memory 216572 kb
Host smart-6b16a09b-4433-4454-8d96-cc25dac2a813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109102098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3109102098
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2467276045
Short name T49
Test name
Test status
Simulation time 34353784 ps
CPU time 1.09 seconds
Started Jun 23 05:36:53 PM PDT 24
Finished Jun 23 05:36:55 PM PDT 24
Peak memory 216596 kb
Host smart-e18d4c76-8e51-4745-a5fc-74023cdd216a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467276045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2467276045
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2931585986
Short name T357
Test name
Test status
Simulation time 83331625 ps
CPU time 1.54 seconds
Started Jun 23 05:36:55 PM PDT 24
Finished Jun 23 05:36:57 PM PDT 24
Peak memory 217968 kb
Host smart-e73c16e3-c06d-44f8-b227-91d0eb8334ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931585986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2931585986
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.985257595
Short name T820
Test name
Test status
Simulation time 48817974 ps
CPU time 1.36 seconds
Started Jun 23 05:36:59 PM PDT 24
Finished Jun 23 05:37:01 PM PDT 24
Peak memory 218032 kb
Host smart-f55516af-4caf-4e24-8701-1e98440a8411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985257595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.985257595
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1976539471
Short name T622
Test name
Test status
Simulation time 38348525 ps
CPU time 1.51 seconds
Started Jun 23 05:37:01 PM PDT 24
Finished Jun 23 05:37:03 PM PDT 24
Peak memory 217828 kb
Host smart-40e8c021-5c4d-48f4-af7d-e1a255257714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976539471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1976539471
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3368050691
Short name T604
Test name
Test status
Simulation time 48990018 ps
CPU time 1.48 seconds
Started Jun 23 05:37:00 PM PDT 24
Finished Jun 23 05:37:02 PM PDT 24
Peak memory 218068 kb
Host smart-19f84bff-d716-409e-9899-4c0c1304f55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368050691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3368050691
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1474547202
Short name T42
Test name
Test status
Simulation time 36447983 ps
CPU time 1.58 seconds
Started Jun 23 05:37:02 PM PDT 24
Finished Jun 23 05:37:04 PM PDT 24
Peak memory 214620 kb
Host smart-bca54bd9-3c5a-4d72-9339-dc8fbb2b79ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474547202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1474547202
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3243922206
Short name T488
Test name
Test status
Simulation time 77576842 ps
CPU time 1.22 seconds
Started Jun 23 05:37:02 PM PDT 24
Finished Jun 23 05:37:04 PM PDT 24
Peak memory 216728 kb
Host smart-60ca7a56-a481-4b18-b5dc-5d48fc49fa00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243922206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3243922206
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.265168239
Short name T935
Test name
Test status
Simulation time 97329367 ps
CPU time 1.54 seconds
Started Jun 23 05:36:57 PM PDT 24
Finished Jun 23 05:36:59 PM PDT 24
Peak memory 218204 kb
Host smart-18ba2cbd-40b3-432d-90bb-e24e925074c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265168239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.265168239
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.4170707993
Short name T324
Test name
Test status
Simulation time 61317017 ps
CPU time 1.45 seconds
Started Jun 23 05:36:57 PM PDT 24
Finished Jun 23 05:36:59 PM PDT 24
Peak memory 218024 kb
Host smart-ca45ca20-5a11-4cf8-b0e4-13b3901a97f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170707993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.4170707993
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2048906085
Short name T579
Test name
Test status
Simulation time 39351057 ps
CPU time 1.03 seconds
Started Jun 23 05:34:41 PM PDT 24
Finished Jun 23 05:34:43 PM PDT 24
Peak memory 217844 kb
Host smart-a17aeb35-9b57-424f-8ded-75021b5be4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048906085 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2048906085
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3245847724
Short name T845
Test name
Test status
Simulation time 20433706 ps
CPU time 0.84 seconds
Started Jun 23 05:34:51 PM PDT 24
Finished Jun 23 05:34:52 PM PDT 24
Peak memory 205992 kb
Host smart-13e40733-e9a3-4bdb-94a7-e4b793a54599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245847724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3245847724
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.689204825
Short name T982
Test name
Test status
Simulation time 15182488 ps
CPU time 0.94 seconds
Started Jun 23 05:34:42 PM PDT 24
Finished Jun 23 05:34:43 PM PDT 24
Peak memory 215960 kb
Host smart-7c2ff6e5-dcbd-4c19-9ee4-f836c743ab6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689204825 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.689204825
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1884401434
Short name T463
Test name
Test status
Simulation time 78465023 ps
CPU time 0.99 seconds
Started Jun 23 05:34:42 PM PDT 24
Finished Jun 23 05:34:43 PM PDT 24
Peak memory 217820 kb
Host smart-3a043298-45e5-419f-8729-f1724ff2ef57
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884401434 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1884401434
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.2616416866
Short name T715
Test name
Test status
Simulation time 40594005 ps
CPU time 1.11 seconds
Started Jun 23 05:34:40 PM PDT 24
Finished Jun 23 05:34:42 PM PDT 24
Peak memory 219328 kb
Host smart-c26a645f-e5f2-4cf1-9fd8-e95b93ff2a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616416866 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2616416866
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3757436012
Short name T374
Test name
Test status
Simulation time 137222367 ps
CPU time 2.66 seconds
Started Jun 23 05:34:40 PM PDT 24
Finished Jun 23 05:34:43 PM PDT 24
Peak memory 219468 kb
Host smart-449119cd-7c5c-4a76-88c6-4d949351129a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757436012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3757436012
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.996922815
Short name T500
Test name
Test status
Simulation time 24465429 ps
CPU time 0.93 seconds
Started Jun 23 05:34:41 PM PDT 24
Finished Jun 23 05:34:43 PM PDT 24
Peak memory 214976 kb
Host smart-b6f05176-75db-4bf0-bf7d-c555a87a3250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996922815 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.996922815
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2405500100
Short name T641
Test name
Test status
Simulation time 18243095 ps
CPU time 0.98 seconds
Started Jun 23 05:34:39 PM PDT 24
Finished Jun 23 05:34:40 PM PDT 24
Peak memory 214656 kb
Host smart-12154c71-d937-48a9-88fc-10fc0a078834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405500100 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2405500100
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.4168435691
Short name T592
Test name
Test status
Simulation time 169227428 ps
CPU time 3.33 seconds
Started Jun 23 05:34:51 PM PDT 24
Finished Jun 23 05:34:55 PM PDT 24
Peak memory 214656 kb
Host smart-ebd06c85-6177-4842-a132-5aa474146a9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168435691 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.4168435691
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2722228848
Short name T234
Test name
Test status
Simulation time 826458727334 ps
CPU time 2952.64 seconds
Started Jun 23 05:34:51 PM PDT 24
Finished Jun 23 06:24:04 PM PDT 24
Peak memory 237732 kb
Host smart-ba508711-274d-4ef4-a8c7-5826bb7bcab9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722228848 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2722228848
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2565051113
Short name T412
Test name
Test status
Simulation time 36072061 ps
CPU time 1.48 seconds
Started Jun 23 05:36:57 PM PDT 24
Finished Jun 23 05:36:59 PM PDT 24
Peak memory 218080 kb
Host smart-85f7562f-5aa7-4934-b302-b8449f6ff37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565051113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2565051113
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2805623635
Short name T844
Test name
Test status
Simulation time 269636666 ps
CPU time 1.2 seconds
Started Jun 23 05:37:01 PM PDT 24
Finished Jun 23 05:37:02 PM PDT 24
Peak memory 216516 kb
Host smart-e2b1f0ba-8c0a-4551-b3a1-97cebd282500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805623635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2805623635
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3381951911
Short name T485
Test name
Test status
Simulation time 118936206 ps
CPU time 1.53 seconds
Started Jun 23 05:36:57 PM PDT 24
Finished Jun 23 05:36:59 PM PDT 24
Peak memory 218100 kb
Host smart-7ff71dee-b1eb-46d5-becb-3b7ca0a673ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381951911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3381951911
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.546884540
Short name T676
Test name
Test status
Simulation time 72329175 ps
CPU time 1.14 seconds
Started Jun 23 05:36:59 PM PDT 24
Finished Jun 23 05:37:00 PM PDT 24
Peak memory 216608 kb
Host smart-f8855989-17d4-4fdb-b07f-985b972f84b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546884540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.546884540
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2943099522
Short name T619
Test name
Test status
Simulation time 131671759 ps
CPU time 1.13 seconds
Started Jun 23 05:36:57 PM PDT 24
Finished Jun 23 05:36:59 PM PDT 24
Peak memory 216688 kb
Host smart-69bace4d-5a2b-47e1-890f-408f313c8210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943099522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2943099522
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1085762230
Short name T942
Test name
Test status
Simulation time 44824109 ps
CPU time 1.29 seconds
Started Jun 23 05:36:58 PM PDT 24
Finished Jun 23 05:37:00 PM PDT 24
Peak memory 216744 kb
Host smart-0b0aeaed-62e5-4dba-b66f-e595e9164f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085762230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1085762230
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.4043977918
Short name T974
Test name
Test status
Simulation time 52219049 ps
CPU time 1.41 seconds
Started Jun 23 05:37:03 PM PDT 24
Finished Jun 23 05:37:05 PM PDT 24
Peak memory 217952 kb
Host smart-e66f43fe-043b-4e26-941f-a6a04ceb0731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043977918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.4043977918
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2938586143
Short name T675
Test name
Test status
Simulation time 88647151 ps
CPU time 1.1 seconds
Started Jun 23 05:37:00 PM PDT 24
Finished Jun 23 05:37:02 PM PDT 24
Peak memory 216716 kb
Host smart-af82a927-c0bc-4e4a-9cbc-6897f38819da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938586143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2938586143
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3602632620
Short name T30
Test name
Test status
Simulation time 39019917 ps
CPU time 1.35 seconds
Started Jun 23 05:37:00 PM PDT 24
Finished Jun 23 05:37:02 PM PDT 24
Peak memory 217860 kb
Host smart-8f78e823-34ed-4574-8c35-da0d3cc7484d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602632620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3602632620
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.874156154
Short name T93
Test name
Test status
Simulation time 200012671 ps
CPU time 1.16 seconds
Started Jun 23 05:34:46 PM PDT 24
Finished Jun 23 05:34:48 PM PDT 24
Peak memory 218904 kb
Host smart-ddf961b3-45db-4e73-85e5-9d7931864925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874156154 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.874156154
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2764701010
Short name T341
Test name
Test status
Simulation time 67737374 ps
CPU time 0.94 seconds
Started Jun 23 05:34:43 PM PDT 24
Finished Jun 23 05:34:45 PM PDT 24
Peak memory 214328 kb
Host smart-822bd8a2-7e52-492d-972a-e3192cf4ae0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764701010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2764701010
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3253423274
Short name T206
Test name
Test status
Simulation time 34884269 ps
CPU time 0.83 seconds
Started Jun 23 05:34:45 PM PDT 24
Finished Jun 23 05:34:47 PM PDT 24
Peak memory 215692 kb
Host smart-b8eacf6e-8ee4-4f4d-9a56-b734c9f4d89b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253423274 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3253423274
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.4126623067
Short name T827
Test name
Test status
Simulation time 68562060 ps
CPU time 1.28 seconds
Started Jun 23 05:34:48 PM PDT 24
Finished Jun 23 05:34:50 PM PDT 24
Peak memory 216300 kb
Host smart-5a7e5aa8-22ea-4db3-bc59-a21ca4e81d4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126623067 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.4126623067
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2107514653
Short name T424
Test name
Test status
Simulation time 23697456 ps
CPU time 0.98 seconds
Started Jun 23 05:34:44 PM PDT 24
Finished Jun 23 05:34:46 PM PDT 24
Peak memory 218104 kb
Host smart-46bc4f3c-04fc-49e1-8eb3-49b7a3e729ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107514653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2107514653
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3771424588
Short name T465
Test name
Test status
Simulation time 50561258 ps
CPU time 1.81 seconds
Started Jun 23 05:34:41 PM PDT 24
Finished Jun 23 05:34:43 PM PDT 24
Peak memory 218004 kb
Host smart-bfecf234-e5ef-418e-8e18-ce12f350aee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771424588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3771424588
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3332711632
Short name T548
Test name
Test status
Simulation time 21659106 ps
CPU time 1.08 seconds
Started Jun 23 05:34:47 PM PDT 24
Finished Jun 23 05:34:48 PM PDT 24
Peak memory 215096 kb
Host smart-80cfd7b3-c534-4633-892e-0553f855a446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332711632 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3332711632
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1554226553
Short name T851
Test name
Test status
Simulation time 19510246 ps
CPU time 1.03 seconds
Started Jun 23 05:34:51 PM PDT 24
Finished Jun 23 05:34:53 PM PDT 24
Peak memory 214632 kb
Host smart-52b4063c-09db-40bb-9d51-555d645b91a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554226553 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1554226553
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.539095547
Short name T247
Test name
Test status
Simulation time 400406763 ps
CPU time 2.82 seconds
Started Jun 23 05:34:41 PM PDT 24
Finished Jun 23 05:34:44 PM PDT 24
Peak memory 216576 kb
Host smart-c371e64e-6943-4f79-ba6e-d0c2f1d04ee7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539095547 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.539095547
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.376134658
Short name T319
Test name
Test status
Simulation time 127041762063 ps
CPU time 585.47 seconds
Started Jun 23 05:34:53 PM PDT 24
Finished Jun 23 05:44:38 PM PDT 24
Peak memory 218940 kb
Host smart-840c9508-d5bc-40ed-bd33-05edff284ece
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376134658 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.376134658
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2071780061
Short name T919
Test name
Test status
Simulation time 119765777 ps
CPU time 1.32 seconds
Started Jun 23 05:36:58 PM PDT 24
Finished Jun 23 05:37:00 PM PDT 24
Peak memory 216732 kb
Host smart-f1c3cde3-e730-4835-9270-357a14b91e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071780061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2071780061
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2398176250
Short name T752
Test name
Test status
Simulation time 35453164 ps
CPU time 1.47 seconds
Started Jun 23 05:36:57 PM PDT 24
Finished Jun 23 05:36:59 PM PDT 24
Peak memory 217884 kb
Host smart-93de7863-9a68-4a5e-979d-5c5a8f83129e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398176250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2398176250
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.5941515
Short name T527
Test name
Test status
Simulation time 46042376 ps
CPU time 1.57 seconds
Started Jun 23 05:36:58 PM PDT 24
Finished Jun 23 05:37:01 PM PDT 24
Peak memory 216648 kb
Host smart-d12f0765-8a96-4c73-8c4a-58ea23a5c1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5941515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.5941515
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2973064711
Short name T984
Test name
Test status
Simulation time 189594054 ps
CPU time 1.79 seconds
Started Jun 23 05:36:58 PM PDT 24
Finished Jun 23 05:37:01 PM PDT 24
Peak memory 217908 kb
Host smart-a0e8b3a2-c412-4aee-aacf-100047703992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973064711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2973064711
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2662760090
Short name T203
Test name
Test status
Simulation time 39513470 ps
CPU time 1.61 seconds
Started Jun 23 05:36:58 PM PDT 24
Finished Jun 23 05:37:00 PM PDT 24
Peak memory 217884 kb
Host smart-dc216ae5-0736-41de-9588-8a4185d48bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662760090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2662760090
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1827093893
Short name T596
Test name
Test status
Simulation time 47286314 ps
CPU time 1.8 seconds
Started Jun 23 05:37:01 PM PDT 24
Finished Jun 23 05:37:03 PM PDT 24
Peak memory 217764 kb
Host smart-bc1a6613-a852-469b-a2a8-fbfbf9e07c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827093893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1827093893
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.339044250
Short name T483
Test name
Test status
Simulation time 22262387 ps
CPU time 1.04 seconds
Started Jun 23 05:36:59 PM PDT 24
Finished Jun 23 05:37:00 PM PDT 24
Peak memory 216512 kb
Host smart-6025dfde-54eb-469a-9ab5-e41d18234fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339044250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.339044250
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.245508519
Short name T882
Test name
Test status
Simulation time 40504408 ps
CPU time 1.7 seconds
Started Jun 23 05:37:03 PM PDT 24
Finished Jun 23 05:37:05 PM PDT 24
Peak memory 217884 kb
Host smart-02aca185-6f45-4278-abbf-3c683bef168b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245508519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.245508519
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3807603396
Short name T699
Test name
Test status
Simulation time 58205875 ps
CPU time 2.18 seconds
Started Jun 23 05:36:58 PM PDT 24
Finished Jun 23 05:37:01 PM PDT 24
Peak memory 219412 kb
Host smart-578054cf-0fcf-484d-b142-60a8a79a9d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807603396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3807603396
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.163369654
Short name T363
Test name
Test status
Simulation time 27008972 ps
CPU time 1.18 seconds
Started Jun 23 05:34:46 PM PDT 24
Finished Jun 23 05:34:47 PM PDT 24
Peak memory 218932 kb
Host smart-aee5a85e-7f95-4fb4-bed0-c10aec8ba6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163369654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.163369654
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.894895040
Short name T344
Test name
Test status
Simulation time 28771829 ps
CPU time 0.92 seconds
Started Jun 23 05:34:51 PM PDT 24
Finished Jun 23 05:34:52 PM PDT 24
Peak memory 214164 kb
Host smart-a2ff9469-a2da-44e3-8cda-93800bb41a58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894895040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.894895040
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.503509067
Short name T210
Test name
Test status
Simulation time 18068850 ps
CPU time 0.85 seconds
Started Jun 23 05:34:44 PM PDT 24
Finished Jun 23 05:34:46 PM PDT 24
Peak memory 214828 kb
Host smart-011603d3-d93a-4fc1-930c-f8d8ec2d2f23
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503509067 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.503509067
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3672328046
Short name T969
Test name
Test status
Simulation time 49140692 ps
CPU time 1.08 seconds
Started Jun 23 05:34:48 PM PDT 24
Finished Jun 23 05:34:50 PM PDT 24
Peak memory 216240 kb
Host smart-faf59c2a-3792-4c9b-8841-9a420a20af0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672328046 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3672328046
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.2053778701
Short name T58
Test name
Test status
Simulation time 23230203 ps
CPU time 1.16 seconds
Started Jun 23 05:34:46 PM PDT 24
Finished Jun 23 05:34:48 PM PDT 24
Peak memory 223428 kb
Host smart-a5ed1ca8-4d99-4c45-9c63-82122b4fd689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053778701 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2053778701
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1081090882
Short name T767
Test name
Test status
Simulation time 263469818 ps
CPU time 3.74 seconds
Started Jun 23 05:34:53 PM PDT 24
Finished Jun 23 05:34:57 PM PDT 24
Peak memory 217888 kb
Host smart-fc6099e1-180a-4e76-83fa-bcd5888cc357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081090882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1081090882
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.4277821498
Short name T14
Test name
Test status
Simulation time 22283006 ps
CPU time 1.2 seconds
Started Jun 23 05:34:51 PM PDT 24
Finished Jun 23 05:34:52 PM PDT 24
Peak memory 223352 kb
Host smart-2632fc25-dd21-4b37-b886-3d8d85ee7e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277821498 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.4277821498
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.252425208
Short name T339
Test name
Test status
Simulation time 16791639 ps
CPU time 0.98 seconds
Started Jun 23 05:34:47 PM PDT 24
Finished Jun 23 05:34:48 PM PDT 24
Peak memory 214656 kb
Host smart-90c37d60-0f11-4687-a36c-daff0812cf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252425208 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.252425208
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3561600579
Short name T118
Test name
Test status
Simulation time 137802696 ps
CPU time 2.26 seconds
Started Jun 23 05:34:44 PM PDT 24
Finished Jun 23 05:34:47 PM PDT 24
Peak memory 216564 kb
Host smart-603cfe83-7ac8-4ff8-9769-25b0b1c315fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561600579 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3561600579
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1443869075
Short name T443
Test name
Test status
Simulation time 12401121200 ps
CPU time 276 seconds
Started Jun 23 05:34:47 PM PDT 24
Finished Jun 23 05:39:24 PM PDT 24
Peak memory 217688 kb
Host smart-9a8d6eb2-5963-401a-a8a6-6b87877d860f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443869075 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1443869075
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.339205302
Short name T50
Test name
Test status
Simulation time 77480820 ps
CPU time 1.17 seconds
Started Jun 23 05:37:00 PM PDT 24
Finished Jun 23 05:37:02 PM PDT 24
Peak memory 218172 kb
Host smart-e3ce328a-044b-4072-b8f3-cfad1b0a2914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339205302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.339205302
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1317336644
Short name T950
Test name
Test status
Simulation time 32168491 ps
CPU time 1.4 seconds
Started Jun 23 05:36:57 PM PDT 24
Finished Jun 23 05:36:59 PM PDT 24
Peak memory 217944 kb
Host smart-ba38e83a-ac18-4422-b96b-d9b3c3b38a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317336644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1317336644
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.148094358
Short name T673
Test name
Test status
Simulation time 44120119 ps
CPU time 1.15 seconds
Started Jun 23 05:36:56 PM PDT 24
Finished Jun 23 05:36:58 PM PDT 24
Peak memory 216540 kb
Host smart-ee6019ea-6891-4669-aad9-cc19d5686189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148094358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.148094358
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2495708457
Short name T888
Test name
Test status
Simulation time 92571616 ps
CPU time 1.19 seconds
Started Jun 23 05:36:57 PM PDT 24
Finished Jun 23 05:36:59 PM PDT 24
Peak memory 219100 kb
Host smart-136a55db-918b-4613-940a-5d4bed34dcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495708457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2495708457
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.561383071
Short name T725
Test name
Test status
Simulation time 54325825 ps
CPU time 1.39 seconds
Started Jun 23 05:37:04 PM PDT 24
Finished Jun 23 05:37:06 PM PDT 24
Peak memory 219300 kb
Host smart-d1dd56f5-4bc5-4b62-8231-fe189f74ce5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561383071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.561383071
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3748209647
Short name T512
Test name
Test status
Simulation time 41870720 ps
CPU time 1.55 seconds
Started Jun 23 05:37:04 PM PDT 24
Finished Jun 23 05:37:07 PM PDT 24
Peak memory 217744 kb
Host smart-7bd8a945-32fb-4b93-bf2e-48e729ab5cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748209647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3748209647
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.502237648
Short name T747
Test name
Test status
Simulation time 86972040 ps
CPU time 1.18 seconds
Started Jun 23 05:37:04 PM PDT 24
Finished Jun 23 05:37:06 PM PDT 24
Peak memory 218376 kb
Host smart-723b0c0b-f8f2-4575-abcf-4278013579ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502237648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.502237648
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.579225275
Short name T931
Test name
Test status
Simulation time 57705331 ps
CPU time 1.3 seconds
Started Jun 23 05:37:04 PM PDT 24
Finished Jun 23 05:37:06 PM PDT 24
Peak memory 219628 kb
Host smart-3d8ea101-c5fc-4509-923b-d0c9dc53cac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579225275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.579225275
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.4186338411
Short name T638
Test name
Test status
Simulation time 60210948 ps
CPU time 2.15 seconds
Started Jun 23 05:37:08 PM PDT 24
Finished Jun 23 05:37:10 PM PDT 24
Peak memory 218640 kb
Host smart-a0363fb6-049f-400d-9479-b41374f7a9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186338411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.4186338411
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.4152622106
Short name T821
Test name
Test status
Simulation time 25384312 ps
CPU time 1.19 seconds
Started Jun 23 05:34:43 PM PDT 24
Finished Jun 23 05:34:45 PM PDT 24
Peak memory 220020 kb
Host smart-10a8c63e-bae2-47e9-9cfb-84e6afc8f8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152622106 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.4152622106
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.15780541
Short name T696
Test name
Test status
Simulation time 59080488 ps
CPU time 0.95 seconds
Started Jun 23 05:34:44 PM PDT 24
Finished Jun 23 05:34:45 PM PDT 24
Peak memory 206136 kb
Host smart-2e13a7d5-315b-4479-a04d-078a2e01d984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15780541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.15780541
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2389919270
Short name T781
Test name
Test status
Simulation time 14186507 ps
CPU time 0.93 seconds
Started Jun 23 05:34:46 PM PDT 24
Finished Jun 23 05:34:48 PM PDT 24
Peak memory 215840 kb
Host smart-269d9258-ccc2-40db-8fa7-36c8b698e28d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389919270 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2389919270
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1989204616
Short name T487
Test name
Test status
Simulation time 38196195 ps
CPU time 1.31 seconds
Started Jun 23 05:34:44 PM PDT 24
Finished Jun 23 05:34:46 PM PDT 24
Peak memory 216252 kb
Host smart-405ffd0c-0b87-41f4-b49b-ae9a55c3e3fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989204616 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1989204616
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2978133651
Short name T937
Test name
Test status
Simulation time 28432555 ps
CPU time 0.91 seconds
Started Jun 23 05:34:44 PM PDT 24
Finished Jun 23 05:34:46 PM PDT 24
Peak memory 217432 kb
Host smart-1b47b229-1dc7-4a7e-bebf-5f9db43cacba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978133651 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2978133651
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1675686233
Short name T965
Test name
Test status
Simulation time 34158730 ps
CPU time 1.3 seconds
Started Jun 23 05:34:47 PM PDT 24
Finished Jun 23 05:34:49 PM PDT 24
Peak memory 216732 kb
Host smart-55cd0029-3dcd-4065-9a08-a13bc7eac79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675686233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1675686233
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.1113689306
Short name T810
Test name
Test status
Simulation time 22708610 ps
CPU time 1.21 seconds
Started Jun 23 05:34:43 PM PDT 24
Finished Jun 23 05:34:44 PM PDT 24
Peak memory 223412 kb
Host smart-c1182770-8b07-44ab-8a48-d0139961c114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113689306 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1113689306
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.4017011861
Short name T370
Test name
Test status
Simulation time 55519723 ps
CPU time 0.96 seconds
Started Jun 23 05:34:47 PM PDT 24
Finished Jun 23 05:34:48 PM PDT 24
Peak memory 214632 kb
Host smart-26261beb-21ca-4007-9fe8-186f54774aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017011861 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.4017011861
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1332034385
Short name T343
Test name
Test status
Simulation time 316596337 ps
CPU time 2.18 seconds
Started Jun 23 05:34:46 PM PDT 24
Finished Jun 23 05:34:48 PM PDT 24
Peak memory 216696 kb
Host smart-06c0f470-ad2e-4abd-ae33-8f1c55eb02d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332034385 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1332034385
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.166356587
Short name T777
Test name
Test status
Simulation time 856291280633 ps
CPU time 2170.43 seconds
Started Jun 23 05:34:43 PM PDT 24
Finished Jun 23 06:10:55 PM PDT 24
Peak memory 226564 kb
Host smart-8805dbb8-70ab-4c41-ae81-2d7296dc52a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166356587 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.166356587
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3661935465
Short name T784
Test name
Test status
Simulation time 98012090 ps
CPU time 1.32 seconds
Started Jun 23 05:37:03 PM PDT 24
Finished Jun 23 05:37:05 PM PDT 24
Peak memory 218196 kb
Host smart-4c0fb78f-c868-4255-8e4b-cf3c023bb425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661935465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3661935465
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1296108457
Short name T836
Test name
Test status
Simulation time 56528788 ps
CPU time 1.68 seconds
Started Jun 23 05:37:03 PM PDT 24
Finished Jun 23 05:37:06 PM PDT 24
Peak memory 216696 kb
Host smart-5f08106e-9a61-4fe3-af49-fa10bd705688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296108457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1296108457
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3755844689
Short name T546
Test name
Test status
Simulation time 112602346 ps
CPU time 1.44 seconds
Started Jun 23 05:37:04 PM PDT 24
Finished Jun 23 05:37:06 PM PDT 24
Peak memory 218224 kb
Host smart-8ed8e290-52e9-45c4-8465-ee5352a7f930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755844689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3755844689
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3698077591
Short name T387
Test name
Test status
Simulation time 72058139 ps
CPU time 1.47 seconds
Started Jun 23 05:37:02 PM PDT 24
Finished Jun 23 05:37:04 PM PDT 24
Peak memory 216680 kb
Host smart-4d2aae91-b060-4a67-9847-17beda0d27f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698077591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3698077591
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1690250540
Short name T330
Test name
Test status
Simulation time 146647884 ps
CPU time 1.71 seconds
Started Jun 23 05:37:03 PM PDT 24
Finished Jun 23 05:37:05 PM PDT 24
Peak memory 218040 kb
Host smart-f21acf60-2c12-4664-8e00-5a05b61eb2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690250540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1690250540
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3631298667
Short name T803
Test name
Test status
Simulation time 197692637 ps
CPU time 3.04 seconds
Started Jun 23 05:37:02 PM PDT 24
Finished Jun 23 05:37:05 PM PDT 24
Peak memory 219468 kb
Host smart-8f3f3ec2-400d-438f-a6b4-a916c7f75e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631298667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3631298667
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.522267550
Short name T864
Test name
Test status
Simulation time 87474982 ps
CPU time 1.25 seconds
Started Jun 23 05:37:03 PM PDT 24
Finished Jun 23 05:37:05 PM PDT 24
Peak memory 219220 kb
Host smart-0871e3f8-6a2d-453e-bfd9-0c3fcd454cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522267550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.522267550
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1243769729
Short name T323
Test name
Test status
Simulation time 81115439 ps
CPU time 1.15 seconds
Started Jun 23 05:37:03 PM PDT 24
Finished Jun 23 05:37:05 PM PDT 24
Peak memory 216808 kb
Host smart-1b8198f0-3b42-4fc5-bfc0-759680f3dc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243769729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1243769729
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.908002734
Short name T470
Test name
Test status
Simulation time 39026346 ps
CPU time 1.47 seconds
Started Jun 23 05:37:03 PM PDT 24
Finished Jun 23 05:37:05 PM PDT 24
Peak memory 219320 kb
Host smart-b0f039a6-ad18-4a7a-9c7f-0e21fb46c5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908002734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.908002734
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1762102325
Short name T952
Test name
Test status
Simulation time 75462446 ps
CPU time 1.24 seconds
Started Jun 23 05:37:05 PM PDT 24
Finished Jun 23 05:37:06 PM PDT 24
Peak memory 216792 kb
Host smart-f180d869-b842-4c70-8780-1d6e5cfd659f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762102325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1762102325
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3868534375
Short name T504
Test name
Test status
Simulation time 24853953 ps
CPU time 1.17 seconds
Started Jun 23 05:34:51 PM PDT 24
Finished Jun 23 05:34:52 PM PDT 24
Peak memory 217960 kb
Host smart-ecf07415-ad48-480d-b242-817425457bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868534375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3868534375
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.935306421
Short name T478
Test name
Test status
Simulation time 23768759 ps
CPU time 1.05 seconds
Started Jun 23 05:34:48 PM PDT 24
Finished Jun 23 05:34:49 PM PDT 24
Peak memory 214212 kb
Host smart-dcdc797c-4d59-4eea-857c-6db57d97705a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935306421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.935306421
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.1886706483
Short name T913
Test name
Test status
Simulation time 13009990 ps
CPU time 0.94 seconds
Started Jun 23 05:34:49 PM PDT 24
Finished Jun 23 05:34:51 PM PDT 24
Peak memory 215844 kb
Host smart-7477080c-07d5-466c-a50a-e988c10f7b6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886706483 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1886706483
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.28156454
Short name T754
Test name
Test status
Simulation time 81928895 ps
CPU time 1.19 seconds
Started Jun 23 05:34:49 PM PDT 24
Finished Jun 23 05:34:51 PM PDT 24
Peak memory 216348 kb
Host smart-48e24d11-7887-4be1-859c-045a230e15e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28156454 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_dis
able_auto_req_mode.28156454
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.169216398
Short name T801
Test name
Test status
Simulation time 33147964 ps
CPU time 1 seconds
Started Jun 23 05:34:44 PM PDT 24
Finished Jun 23 05:34:46 PM PDT 24
Peak memory 223216 kb
Host smart-df37a1fb-717d-47d3-bcd3-96201c5d3502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169216398 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.169216398
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.789940619
Short name T67
Test name
Test status
Simulation time 80496659 ps
CPU time 1.26 seconds
Started Jun 23 05:34:46 PM PDT 24
Finished Jun 23 05:34:47 PM PDT 24
Peak memory 217976 kb
Host smart-39266aa6-3049-445b-b365-85772bc3ad5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789940619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.789940619
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.393738482
Short name T508
Test name
Test status
Simulation time 33248863 ps
CPU time 0.89 seconds
Started Jun 23 05:34:46 PM PDT 24
Finished Jun 23 05:34:48 PM PDT 24
Peak memory 214856 kb
Host smart-250c2957-3e39-4172-94f7-fd7e657b07c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393738482 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.393738482
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.11480476
Short name T376
Test name
Test status
Simulation time 15360580 ps
CPU time 1.01 seconds
Started Jun 23 05:34:46 PM PDT 24
Finished Jun 23 05:34:47 PM PDT 24
Peak memory 214628 kb
Host smart-cce00168-e348-4a36-86cb-adc875748825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11480476 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.11480476
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3617177582
Short name T837
Test name
Test status
Simulation time 172355566 ps
CPU time 1.5 seconds
Started Jun 23 05:34:46 PM PDT 24
Finished Jun 23 05:34:48 PM PDT 24
Peak memory 216556 kb
Host smart-80d6b285-7db2-48b2-8e82-368be057b2db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617177582 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3617177582
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.259533202
Short name T561
Test name
Test status
Simulation time 237136091090 ps
CPU time 1353.98 seconds
Started Jun 23 05:34:46 PM PDT 24
Finished Jun 23 05:57:21 PM PDT 24
Peak memory 225032 kb
Host smart-5ffe39d3-c1c2-40cf-af58-e2ed3f9077ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259533202 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.259533202
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2781953473
Short name T523
Test name
Test status
Simulation time 41137505 ps
CPU time 1.43 seconds
Started Jun 23 05:37:04 PM PDT 24
Finished Jun 23 05:37:06 PM PDT 24
Peak memory 217908 kb
Host smart-4646bcfc-45cf-42ea-bcd9-2e34bbee915b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781953473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2781953473
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2222931171
Short name T824
Test name
Test status
Simulation time 148526698 ps
CPU time 1.68 seconds
Started Jun 23 05:37:02 PM PDT 24
Finished Jun 23 05:37:04 PM PDT 24
Peak memory 216760 kb
Host smart-028f221d-9e0d-41be-be61-503e76609edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222931171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2222931171
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.874382115
Short name T757
Test name
Test status
Simulation time 104636221 ps
CPU time 1.63 seconds
Started Jun 23 05:37:03 PM PDT 24
Finished Jun 23 05:37:05 PM PDT 24
Peak memory 218136 kb
Host smart-24421d53-6757-41e0-92c4-077aeb876eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874382115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.874382115
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3278122960
Short name T588
Test name
Test status
Simulation time 141495089 ps
CPU time 1.56 seconds
Started Jun 23 05:37:03 PM PDT 24
Finished Jun 23 05:37:05 PM PDT 24
Peak memory 218112 kb
Host smart-12aa1f7a-3290-4a56-92c6-f03455ea4651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278122960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3278122960
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.260886860
Short name T981
Test name
Test status
Simulation time 28276179 ps
CPU time 1.25 seconds
Started Jun 23 05:37:04 PM PDT 24
Finished Jun 23 05:37:06 PM PDT 24
Peak memory 218112 kb
Host smart-b13a4b2d-6348-4571-bf64-9e4dcfd8336c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260886860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.260886860
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2562085844
Short name T680
Test name
Test status
Simulation time 39693066 ps
CPU time 1.45 seconds
Started Jun 23 05:37:03 PM PDT 24
Finished Jun 23 05:37:05 PM PDT 24
Peak memory 218020 kb
Host smart-276777eb-688a-4905-a2ea-b46f404d7e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562085844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2562085844
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.4049631294
Short name T902
Test name
Test status
Simulation time 110613201 ps
CPU time 2.45 seconds
Started Jun 23 05:37:04 PM PDT 24
Finished Jun 23 05:37:07 PM PDT 24
Peak memory 219244 kb
Host smart-e110b535-a831-4ad9-9d35-d0777b8f2523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049631294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.4049631294
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2121108493
Short name T427
Test name
Test status
Simulation time 63766776 ps
CPU time 2.18 seconds
Started Jun 23 05:37:15 PM PDT 24
Finished Jun 23 05:37:18 PM PDT 24
Peak memory 219280 kb
Host smart-3559002c-41ef-4e52-bc3f-a3ac683eb588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121108493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2121108493
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.797897526
Short name T342
Test name
Test status
Simulation time 58611984 ps
CPU time 1.28 seconds
Started Jun 23 05:37:11 PM PDT 24
Finished Jun 23 05:37:13 PM PDT 24
Peak memory 217892 kb
Host smart-2f7c083e-d3da-464e-b7c3-e12bd4b9abf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797897526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.797897526
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2323751207
Short name T909
Test name
Test status
Simulation time 41541462 ps
CPU time 1.09 seconds
Started Jun 23 05:34:50 PM PDT 24
Finished Jun 23 05:34:52 PM PDT 24
Peak memory 219068 kb
Host smart-1b21c9c0-3b3f-4427-88cd-e2fa713e3f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323751207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2323751207
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2819248203
Short name T348
Test name
Test status
Simulation time 30219480 ps
CPU time 0.97 seconds
Started Jun 23 05:34:50 PM PDT 24
Finished Jun 23 05:34:51 PM PDT 24
Peak memory 206288 kb
Host smart-79e9dd1f-c271-4a05-8bdc-135a3ea58afd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819248203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2819248203
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.423826324
Short name T658
Test name
Test status
Simulation time 17442511 ps
CPU time 0.83 seconds
Started Jun 23 05:34:48 PM PDT 24
Finished Jun 23 05:34:50 PM PDT 24
Peak memory 215696 kb
Host smart-639a0d36-43a4-4f0c-b6a7-c8a94c1749f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423826324 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.423826324
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3547003767
Short name T905
Test name
Test status
Simulation time 74867567 ps
CPU time 1.04 seconds
Started Jun 23 05:34:49 PM PDT 24
Finished Jun 23 05:34:50 PM PDT 24
Peak memory 216284 kb
Host smart-e6ac2e13-90ab-4a00-8d4d-202e58a069b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547003767 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3547003767
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1900571299
Short name T841
Test name
Test status
Simulation time 33098753 ps
CPU time 0.94 seconds
Started Jun 23 05:34:49 PM PDT 24
Finished Jun 23 05:34:51 PM PDT 24
Peak memory 219200 kb
Host smart-74ebb785-92a2-4350-94c9-bb3bcbf41de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900571299 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1900571299
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.4041092358
Short name T652
Test name
Test status
Simulation time 58317875 ps
CPU time 1.41 seconds
Started Jun 23 05:34:48 PM PDT 24
Finished Jun 23 05:34:50 PM PDT 24
Peak memory 218168 kb
Host smart-e0fe7db4-eb34-440b-8180-fb7e3ea99940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041092358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.4041092358
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2291519003
Short name T606
Test name
Test status
Simulation time 45658735 ps
CPU time 0.98 seconds
Started Jun 23 05:34:54 PM PDT 24
Finished Jun 23 05:34:55 PM PDT 24
Peak memory 223196 kb
Host smart-07138a42-8f3d-445f-ac15-e11bca17fcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291519003 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2291519003
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3488105630
Short name T382
Test name
Test status
Simulation time 72948812 ps
CPU time 0.89 seconds
Started Jun 23 05:34:51 PM PDT 24
Finished Jun 23 05:34:53 PM PDT 24
Peak memory 214504 kb
Host smart-c3918283-dc04-4679-b6dc-53d75aa0d257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488105630 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3488105630
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.326141735
Short name T577
Test name
Test status
Simulation time 114115086 ps
CPU time 2.74 seconds
Started Jun 23 05:34:49 PM PDT 24
Finished Jun 23 05:34:53 PM PDT 24
Peak memory 219024 kb
Host smart-ded45736-bd55-42fb-8dca-0e36c1e944c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326141735 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.326141735
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2290889806
Short name T671
Test name
Test status
Simulation time 143895784717 ps
CPU time 2110.93 seconds
Started Jun 23 05:34:48 PM PDT 24
Finished Jun 23 06:10:00 PM PDT 24
Peak memory 229560 kb
Host smart-cf3c3552-fbb4-4397-857c-c446eb49c0bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290889806 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2290889806
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3855705531
Short name T433
Test name
Test status
Simulation time 75541023 ps
CPU time 1.18 seconds
Started Jun 23 05:37:13 PM PDT 24
Finished Jun 23 05:37:14 PM PDT 24
Peak memory 219328 kb
Host smart-260fe944-089c-4f58-be3c-803ef4854807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855705531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3855705531
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1502196427
Short name T728
Test name
Test status
Simulation time 45613593 ps
CPU time 1.82 seconds
Started Jun 23 05:37:14 PM PDT 24
Finished Jun 23 05:37:17 PM PDT 24
Peak memory 217924 kb
Host smart-3d09e4ee-2b9e-4dc3-82ed-ec120392bf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502196427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1502196427
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2033018895
Short name T797
Test name
Test status
Simulation time 48093838 ps
CPU time 1.27 seconds
Started Jun 23 05:37:12 PM PDT 24
Finished Jun 23 05:37:14 PM PDT 24
Peak memory 218024 kb
Host smart-f012e49b-c0bd-4cb8-b7c4-7cd797b96eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033018895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2033018895
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1940429302
Short name T904
Test name
Test status
Simulation time 93689681 ps
CPU time 1.19 seconds
Started Jun 23 05:37:16 PM PDT 24
Finished Jun 23 05:37:18 PM PDT 24
Peak memory 216780 kb
Host smart-5e268ece-c7da-47cf-a230-9143af5a55b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940429302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1940429302
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1434455876
Short name T439
Test name
Test status
Simulation time 61371826 ps
CPU time 1.06 seconds
Started Jun 23 05:37:13 PM PDT 24
Finished Jun 23 05:37:14 PM PDT 24
Peak memory 216784 kb
Host smart-75dfe8b7-8476-4a3e-a9f8-0acf25162c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434455876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1434455876
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3663540212
Short name T576
Test name
Test status
Simulation time 38817641 ps
CPU time 1.38 seconds
Started Jun 23 05:37:14 PM PDT 24
Finished Jun 23 05:37:16 PM PDT 24
Peak memory 217968 kb
Host smart-5bc038a1-b955-4f2c-a0bb-b4fd956b1974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663540212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3663540212
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3500789315
Short name T598
Test name
Test status
Simulation time 52268667 ps
CPU time 1.91 seconds
Started Jun 23 05:37:14 PM PDT 24
Finished Jun 23 05:37:17 PM PDT 24
Peak memory 217828 kb
Host smart-bec784b4-8780-4b9d-9a51-4100d61a572f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500789315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3500789315
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3070309542
Short name T877
Test name
Test status
Simulation time 44555402 ps
CPU time 1.53 seconds
Started Jun 23 05:37:20 PM PDT 24
Finished Jun 23 05:37:22 PM PDT 24
Peak memory 217732 kb
Host smart-1a27d3b9-e6e7-4b5f-a2c3-9fd878829429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070309542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3070309542
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.3708993818
Short name T549
Test name
Test status
Simulation time 122676638 ps
CPU time 1.25 seconds
Started Jun 23 05:37:14 PM PDT 24
Finished Jun 23 05:37:16 PM PDT 24
Peak memory 217860 kb
Host smart-4eecdef3-e01c-4e8c-b0e2-abfe071fe8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708993818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.3708993818
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2524261125
Short name T911
Test name
Test status
Simulation time 33161012 ps
CPU time 1.3 seconds
Started Jun 23 05:37:20 PM PDT 24
Finished Jun 23 05:37:22 PM PDT 24
Peak memory 217816 kb
Host smart-8e84cfd8-da47-4e41-9fb9-c3d99ed70726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524261125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2524261125
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3093820195
Short name T669
Test name
Test status
Simulation time 28953974 ps
CPU time 1.23 seconds
Started Jun 23 05:34:55 PM PDT 24
Finished Jun 23 05:34:56 PM PDT 24
Peak memory 218080 kb
Host smart-7cfc901d-78db-4b80-a6bb-fd875294a75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093820195 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3093820195
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2978110809
Short name T677
Test name
Test status
Simulation time 32273584 ps
CPU time 0.86 seconds
Started Jun 23 05:34:57 PM PDT 24
Finished Jun 23 05:34:58 PM PDT 24
Peak memory 205772 kb
Host smart-e5628736-a5f6-47ce-9400-8085c96ce5e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978110809 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2978110809
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3491912566
Short name T667
Test name
Test status
Simulation time 13786020 ps
CPU time 0.9 seconds
Started Jun 23 05:34:53 PM PDT 24
Finished Jun 23 05:34:54 PM PDT 24
Peak memory 215448 kb
Host smart-5994f06e-1b09-4cc8-a520-dfdff4f47b13
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491912566 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3491912566
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_genbits.1781261600
Short name T632
Test name
Test status
Simulation time 77223347 ps
CPU time 1.31 seconds
Started Jun 23 05:34:47 PM PDT 24
Finished Jun 23 05:34:49 PM PDT 24
Peak memory 217968 kb
Host smart-72b85216-67a8-4075-a603-b910acb2aff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781261600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1781261600
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_smoke.725218747
Short name T640
Test name
Test status
Simulation time 23251628 ps
CPU time 0.94 seconds
Started Jun 23 05:34:48 PM PDT 24
Finished Jun 23 05:34:50 PM PDT 24
Peak memory 214692 kb
Host smart-583403a5-750a-4bc4-a776-fadcda50d3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725218747 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.725218747
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2375484106
Short name T4
Test name
Test status
Simulation time 384438339 ps
CPU time 4.28 seconds
Started Jun 23 05:34:49 PM PDT 24
Finished Jun 23 05:34:54 PM PDT 24
Peak memory 214652 kb
Host smart-c855b087-6503-4593-b706-35f284390afe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375484106 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2375484106
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1924006067
Short name T881
Test name
Test status
Simulation time 297229809423 ps
CPU time 1703.8 seconds
Started Jun 23 05:34:48 PM PDT 24
Finished Jun 23 06:03:13 PM PDT 24
Peak memory 223896 kb
Host smart-95b1c13d-c98e-47ac-9a9b-586c86ab1eaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924006067 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1924006067
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2263246735
Short name T535
Test name
Test status
Simulation time 37844995 ps
CPU time 1.51 seconds
Started Jun 23 05:37:15 PM PDT 24
Finished Jun 23 05:37:17 PM PDT 24
Peak memory 216628 kb
Host smart-eca71c25-2e6e-4e0c-9c92-ce39e8846f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263246735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2263246735
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3873764707
Short name T559
Test name
Test status
Simulation time 41828735 ps
CPU time 1.64 seconds
Started Jun 23 05:37:16 PM PDT 24
Finished Jun 23 05:37:19 PM PDT 24
Peak memory 217816 kb
Host smart-e1f44e63-4921-43aa-9e11-e33776c53e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873764707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3873764707
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1084548838
Short name T702
Test name
Test status
Simulation time 48430098 ps
CPU time 1.49 seconds
Started Jun 23 05:37:19 PM PDT 24
Finished Jun 23 05:37:22 PM PDT 24
Peak memory 217924 kb
Host smart-3b458076-cd75-445b-be31-fa704eaed259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084548838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1084548838
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1488332238
Short name T876
Test name
Test status
Simulation time 63466977 ps
CPU time 1.22 seconds
Started Jun 23 05:37:14 PM PDT 24
Finished Jun 23 05:37:16 PM PDT 24
Peak memory 218164 kb
Host smart-81639eff-75a5-4ffc-82c2-0ced56f396d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488332238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1488332238
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.97077445
Short name T818
Test name
Test status
Simulation time 48733011 ps
CPU time 1.17 seconds
Started Jun 23 05:37:13 PM PDT 24
Finished Jun 23 05:37:14 PM PDT 24
Peak memory 216692 kb
Host smart-ed956850-8e76-4787-9718-cbfa2816717a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97077445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.97077445
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2915544654
Short name T453
Test name
Test status
Simulation time 141917894 ps
CPU time 1.2 seconds
Started Jun 23 05:37:17 PM PDT 24
Finished Jun 23 05:37:20 PM PDT 24
Peak memory 216588 kb
Host smart-9d6955e4-87dc-4a97-b24e-27cef41239e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915544654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2915544654
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1692409625
Short name T250
Test name
Test status
Simulation time 46808999 ps
CPU time 1.12 seconds
Started Jun 23 05:37:13 PM PDT 24
Finished Jun 23 05:37:15 PM PDT 24
Peak memory 216704 kb
Host smart-6dcca37b-eac6-4430-afc2-16f8d5cdac1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692409625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1692409625
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.271822574
Short name T338
Test name
Test status
Simulation time 128613527 ps
CPU time 2.59 seconds
Started Jun 23 05:37:14 PM PDT 24
Finished Jun 23 05:37:17 PM PDT 24
Peak memory 219268 kb
Host smart-bfc35cfd-8e29-4774-b464-3883421ed90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271822574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.271822574
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2414633529
Short name T461
Test name
Test status
Simulation time 119684158 ps
CPU time 1.15 seconds
Started Jun 23 05:37:13 PM PDT 24
Finished Jun 23 05:37:15 PM PDT 24
Peak memory 216660 kb
Host smart-413f0dd0-8049-4c74-a60e-98c5c7faf80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414633529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2414633529
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3975856427
Short name T46
Test name
Test status
Simulation time 194914205 ps
CPU time 1.56 seconds
Started Jun 23 05:37:16 PM PDT 24
Finished Jun 23 05:37:18 PM PDT 24
Peak memory 218136 kb
Host smart-7858c7ce-73d8-49c3-92c4-f00eac469191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975856427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3975856427
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.851435250
Short name T127
Test name
Test status
Simulation time 76889768 ps
CPU time 1.12 seconds
Started Jun 23 05:34:53 PM PDT 24
Finished Jun 23 05:34:54 PM PDT 24
Peak memory 218916 kb
Host smart-8d45e6c3-ce58-42ec-b32a-8dac98684815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851435250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.851435250
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.16184301
Short name T566
Test name
Test status
Simulation time 49833236 ps
CPU time 1.02 seconds
Started Jun 23 05:34:59 PM PDT 24
Finished Jun 23 05:35:00 PM PDT 24
Peak memory 214408 kb
Host smart-65090b7f-9b79-4005-b1b3-32c499ae57b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16184301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.16184301
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3071091446
Short name T74
Test name
Test status
Simulation time 62318149 ps
CPU time 1.41 seconds
Started Jun 23 05:35:01 PM PDT 24
Finished Jun 23 05:35:03 PM PDT 24
Peak memory 216372 kb
Host smart-edbbefb4-b253-468f-90e9-c895bbed7978
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071091446 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3071091446
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.32020940
Short name T148
Test name
Test status
Simulation time 150893251 ps
CPU time 1.14 seconds
Started Jun 23 05:35:08 PM PDT 24
Finished Jun 23 05:35:10 PM PDT 24
Peak memory 228904 kb
Host smart-bb1f5b7d-aacc-4b25-90b0-e31aa796e662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32020940 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.32020940
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_intr.3647322809
Short name T776
Test name
Test status
Simulation time 38740976 ps
CPU time 1.02 seconds
Started Jun 23 05:34:56 PM PDT 24
Finished Jun 23 05:34:57 PM PDT 24
Peak memory 223356 kb
Host smart-3abb4b42-4405-47e1-b51c-6ff6bc90c8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647322809 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3647322809
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2324550980
Short name T452
Test name
Test status
Simulation time 20292949 ps
CPU time 1.03 seconds
Started Jun 23 05:34:55 PM PDT 24
Finished Jun 23 05:34:56 PM PDT 24
Peak memory 214636 kb
Host smart-8984591e-71c4-4b97-9852-e464ec128860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324550980 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2324550980
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2753988082
Short name T860
Test name
Test status
Simulation time 724125152 ps
CPU time 5.05 seconds
Started Jun 23 05:34:53 PM PDT 24
Finished Jun 23 05:34:59 PM PDT 24
Peak memory 216492 kb
Host smart-a689d49b-500d-47c7-92e8-b06eebe09f1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753988082 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2753988082
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/280.edn_genbits.803704949
Short name T885
Test name
Test status
Simulation time 35261676 ps
CPU time 1.31 seconds
Started Jun 23 05:37:14 PM PDT 24
Finished Jun 23 05:37:16 PM PDT 24
Peak memory 217852 kb
Host smart-b50592a7-07e3-46d8-9957-b67ba61a27de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803704949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.803704949
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.762012963
Short name T894
Test name
Test status
Simulation time 123345391 ps
CPU time 1.14 seconds
Started Jun 23 05:37:13 PM PDT 24
Finished Jun 23 05:37:14 PM PDT 24
Peak memory 216580 kb
Host smart-67520312-fa1b-4a2f-9a23-feaad04f1509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762012963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.762012963
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2850929344
Short name T528
Test name
Test status
Simulation time 267659088 ps
CPU time 1.48 seconds
Started Jun 23 05:37:19 PM PDT 24
Finished Jun 23 05:37:22 PM PDT 24
Peak memory 218360 kb
Host smart-f0fa2bcc-636d-40cf-8ab1-02b015f5d2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850929344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2850929344
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1680178113
Short name T683
Test name
Test status
Simulation time 356364722 ps
CPU time 4.38 seconds
Started Jun 23 05:37:18 PM PDT 24
Finished Jun 23 05:37:23 PM PDT 24
Peak memory 219332 kb
Host smart-07cf8088-6be1-4242-a12c-13ac675b76ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680178113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1680178113
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2764795644
Short name T870
Test name
Test status
Simulation time 160513602 ps
CPU time 1.37 seconds
Started Jun 23 05:37:14 PM PDT 24
Finished Jun 23 05:37:17 PM PDT 24
Peak memory 216772 kb
Host smart-6252692b-ffa8-4a53-8725-492942aaca0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764795644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2764795644
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3211808407
Short name T355
Test name
Test status
Simulation time 40569373 ps
CPU time 1.16 seconds
Started Jun 23 05:37:15 PM PDT 24
Finished Jun 23 05:37:17 PM PDT 24
Peak memory 216464 kb
Host smart-eb531cce-a817-4f6f-b5c5-b9a49490a2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211808407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3211808407
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3705189966
Short name T24
Test name
Test status
Simulation time 123726292 ps
CPU time 1.07 seconds
Started Jun 23 05:37:11 PM PDT 24
Finished Jun 23 05:37:13 PM PDT 24
Peak memory 216688 kb
Host smart-92fec62e-1ff1-45df-8963-e7ec2f42505b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705189966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3705189966
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3333222828
Short name T337
Test name
Test status
Simulation time 52270345 ps
CPU time 1.79 seconds
Started Jun 23 05:37:16 PM PDT 24
Finished Jun 23 05:37:19 PM PDT 24
Peak memory 217912 kb
Host smart-296eef07-c08e-4c9d-ba0f-d86c08f9b371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333222828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3333222828
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3741815659
Short name T639
Test name
Test status
Simulation time 33677108 ps
CPU time 1.11 seconds
Started Jun 23 05:37:14 PM PDT 24
Finished Jun 23 05:37:16 PM PDT 24
Peak memory 216652 kb
Host smart-7b7e48d0-8d92-4064-9908-06dc29b7c799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741815659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3741815659
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.106215943
Short name T808
Test name
Test status
Simulation time 46482295 ps
CPU time 1.46 seconds
Started Jun 23 05:37:17 PM PDT 24
Finished Jun 23 05:37:20 PM PDT 24
Peak memory 217696 kb
Host smart-cf680079-4da8-4924-a1c9-d55f7826eb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106215943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.106215943
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.3639111237
Short name T718
Test name
Test status
Simulation time 30024605 ps
CPU time 1.4 seconds
Started Jun 23 05:34:58 PM PDT 24
Finished Jun 23 05:35:00 PM PDT 24
Peak memory 220228 kb
Host smart-347d323f-1f77-476d-992f-f2dd4c519c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639111237 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3639111237
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.4142752479
Short name T903
Test name
Test status
Simulation time 52723856 ps
CPU time 0.92 seconds
Started Jun 23 05:35:00 PM PDT 24
Finished Jun 23 05:35:01 PM PDT 24
Peak memory 206072 kb
Host smart-03434b01-f198-42d8-ad67-eb4b133993e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142752479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.4142752479
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3233409841
Short name T812
Test name
Test status
Simulation time 16061194 ps
CPU time 0.83 seconds
Started Jun 23 05:35:08 PM PDT 24
Finished Jun 23 05:35:10 PM PDT 24
Peak memory 215672 kb
Host smart-95555d50-c3fe-4eab-aeeb-d88c07095eaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233409841 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3233409841
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1377121472
Short name T154
Test name
Test status
Simulation time 57171759 ps
CPU time 1.14 seconds
Started Jun 23 05:35:00 PM PDT 24
Finished Jun 23 05:35:02 PM PDT 24
Peak memory 217852 kb
Host smart-52438045-1897-4a12-a4e1-0c5ddf84c78b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377121472 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1377121472
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.269468344
Short name T16
Test name
Test status
Simulation time 18934207 ps
CPU time 1.18 seconds
Started Jun 23 05:35:08 PM PDT 24
Finished Jun 23 05:35:10 PM PDT 24
Peak memory 223268 kb
Host smart-5bcf955d-9892-44a9-aa3e-1937d0cae172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269468344 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.269468344
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3897025829
Short name T645
Test name
Test status
Simulation time 55046717 ps
CPU time 2.05 seconds
Started Jun 23 05:35:00 PM PDT 24
Finished Jun 23 05:35:02 PM PDT 24
Peak memory 216776 kb
Host smart-e2fb67dc-05aa-4bf0-89ef-5e1544a3e84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897025829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3897025829
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2372554477
Short name T849
Test name
Test status
Simulation time 32029311 ps
CPU time 0.82 seconds
Started Jun 23 05:34:59 PM PDT 24
Finished Jun 23 05:35:00 PM PDT 24
Peak memory 214904 kb
Host smart-673d1980-8606-44fd-8dee-6280a8633984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372554477 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2372554477
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3015778463
Short name T906
Test name
Test status
Simulation time 25356512 ps
CPU time 0.93 seconds
Started Jun 23 05:34:59 PM PDT 24
Finished Jun 23 05:35:00 PM PDT 24
Peak memory 214584 kb
Host smart-33d60571-47ca-4e3d-ac95-909279e178e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015778463 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3015778463
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1201115575
Short name T569
Test name
Test status
Simulation time 371154144 ps
CPU time 3.84 seconds
Started Jun 23 05:35:00 PM PDT 24
Finished Jun 23 05:35:05 PM PDT 24
Peak memory 214664 kb
Host smart-b7651881-c9a2-4c4d-b2cc-1499025fb0b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201115575 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1201115575
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3654794968
Short name T710
Test name
Test status
Simulation time 42338007389 ps
CPU time 291.03 seconds
Started Jun 23 05:34:58 PM PDT 24
Finished Jun 23 05:39:49 PM PDT 24
Peak memory 217112 kb
Host smart-8dc7d8a0-a9e4-454f-bdc5-82da35e1d5b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654794968 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3654794968
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2036969090
Short name T326
Test name
Test status
Simulation time 48898419 ps
CPU time 1.26 seconds
Started Jun 23 05:37:13 PM PDT 24
Finished Jun 23 05:37:16 PM PDT 24
Peak memory 219460 kb
Host smart-682c1664-c9b5-42e9-85fb-d0de4653bc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036969090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2036969090
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2456834772
Short name T993
Test name
Test status
Simulation time 37765845 ps
CPU time 1.63 seconds
Started Jun 23 05:37:13 PM PDT 24
Finished Jun 23 05:37:16 PM PDT 24
Peak memory 219352 kb
Host smart-c77f8b91-4c2a-430c-ac30-ac0f7bc66452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456834772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2456834772
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.740411380
Short name T612
Test name
Test status
Simulation time 220318400 ps
CPU time 2.8 seconds
Started Jun 23 05:37:14 PM PDT 24
Finished Jun 23 05:37:18 PM PDT 24
Peak memory 219080 kb
Host smart-7d41e894-727c-403d-b47d-889dc05be4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740411380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.740411380
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1603018442
Short name T479
Test name
Test status
Simulation time 81626664 ps
CPU time 1.19 seconds
Started Jun 23 05:37:14 PM PDT 24
Finished Jun 23 05:37:16 PM PDT 24
Peak memory 219200 kb
Host smart-a0e56b22-eb40-41c0-8e94-0eaafd98c006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603018442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1603018442
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3611075838
Short name T603
Test name
Test status
Simulation time 50808190 ps
CPU time 1.34 seconds
Started Jun 23 05:37:13 PM PDT 24
Finished Jun 23 05:37:15 PM PDT 24
Peak memory 217896 kb
Host smart-624a0fb2-7e29-49d6-8672-d9c615d2c780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611075838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3611075838
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3043503149
Short name T631
Test name
Test status
Simulation time 32744286 ps
CPU time 1.32 seconds
Started Jun 23 05:37:13 PM PDT 24
Finished Jun 23 05:37:15 PM PDT 24
Peak memory 216572 kb
Host smart-01bd4601-f887-44f0-9323-a65283517091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043503149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3043503149
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.341866431
Short name T369
Test name
Test status
Simulation time 59263118 ps
CPU time 1.58 seconds
Started Jun 23 05:37:14 PM PDT 24
Finished Jun 23 05:37:16 PM PDT 24
Peak memory 218012 kb
Host smart-54268094-c405-43ba-ba97-a7584e5d7d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341866431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.341866431
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2533098203
Short name T956
Test name
Test status
Simulation time 77425467 ps
CPU time 1.13 seconds
Started Jun 23 05:37:18 PM PDT 24
Finished Jun 23 05:37:20 PM PDT 24
Peak memory 216696 kb
Host smart-9446036a-59f5-43ad-8522-583bc743a5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533098203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2533098203
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3944979187
Short name T480
Test name
Test status
Simulation time 79261000 ps
CPU time 1.52 seconds
Started Jun 23 05:37:13 PM PDT 24
Finished Jun 23 05:37:16 PM PDT 24
Peak memory 219200 kb
Host smart-bf9a84e3-5f72-4f27-b22b-6cea9b18fa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944979187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3944979187
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3247662580
Short name T345
Test name
Test status
Simulation time 32476126 ps
CPU time 1.19 seconds
Started Jun 23 05:37:16 PM PDT 24
Finished Jun 23 05:37:18 PM PDT 24
Peak memory 217948 kb
Host smart-21183799-62c3-458f-8f9d-164e56824bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247662580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3247662580
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2603762028
Short name T644
Test name
Test status
Simulation time 75194105 ps
CPU time 1.21 seconds
Started Jun 23 05:34:06 PM PDT 24
Finished Jun 23 05:34:07 PM PDT 24
Peak memory 219792 kb
Host smart-be9dc249-34ea-4889-987d-ebb55f125896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603762028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2603762028
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.587638162
Short name T502
Test name
Test status
Simulation time 52162254 ps
CPU time 0.95 seconds
Started Jun 23 05:33:57 PM PDT 24
Finished Jun 23 05:33:58 PM PDT 24
Peak memory 214536 kb
Host smart-af5c7d18-0377-4c37-bcc8-266a3d688312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587638162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.587638162
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2016031216
Short name T204
Test name
Test status
Simulation time 33584459 ps
CPU time 0.98 seconds
Started Jun 23 05:33:59 PM PDT 24
Finished Jun 23 05:34:01 PM PDT 24
Peak memory 215800 kb
Host smart-046d06d3-5ccf-49ae-bbd9-7acdb4666622
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016031216 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2016031216
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.490810506
Short name T458
Test name
Test status
Simulation time 94322662 ps
CPU time 1.09 seconds
Started Jun 23 05:34:00 PM PDT 24
Finished Jun 23 05:34:02 PM PDT 24
Peak memory 216164 kb
Host smart-5fa4acfe-2538-466f-84cf-2f9001545ec0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490810506 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.490810506
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3913785626
Short name T401
Test name
Test status
Simulation time 39227396 ps
CPU time 0.93 seconds
Started Jun 23 05:33:51 PM PDT 24
Finished Jun 23 05:33:52 PM PDT 24
Peak memory 219312 kb
Host smart-00cfaa76-849b-4045-b8f0-e31ee21bfae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913785626 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3913785626
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3567552282
Short name T558
Test name
Test status
Simulation time 54125643 ps
CPU time 1 seconds
Started Jun 23 05:33:49 PM PDT 24
Finished Jun 23 05:33:50 PM PDT 24
Peak memory 216600 kb
Host smart-65bbdd1e-db1d-4c6a-aced-3094e8c3e7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567552282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3567552282
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2914618921
Short name T672
Test name
Test status
Simulation time 21939968 ps
CPU time 1.08 seconds
Started Jun 23 05:33:52 PM PDT 24
Finished Jun 23 05:33:53 PM PDT 24
Peak memory 215024 kb
Host smart-e0ed8d4b-0cf1-426f-a462-093c126453f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914618921 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2914618921
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.2626451120
Short name T648
Test name
Test status
Simulation time 18426271 ps
CPU time 0.99 seconds
Started Jun 23 05:34:04 PM PDT 24
Finished Jun 23 05:34:05 PM PDT 24
Peak memory 206408 kb
Host smart-2a4dec67-c679-4248-97a1-01d4e4fcd382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626451120 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2626451120
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.4175813833
Short name T18
Test name
Test status
Simulation time 2122193875 ps
CPU time 8.2 seconds
Started Jun 23 05:33:54 PM PDT 24
Finished Jun 23 05:34:03 PM PDT 24
Peak memory 235260 kb
Host smart-39203067-3563-44d2-9464-22da7520fe93
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175813833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.4175813833
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.216505824
Short name T953
Test name
Test status
Simulation time 49219142 ps
CPU time 0.91 seconds
Started Jun 23 05:33:56 PM PDT 24
Finished Jun 23 05:33:57 PM PDT 24
Peak memory 214628 kb
Host smart-7acf25d8-2672-4a9c-9928-8165f630b119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216505824 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.216505824
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.356460258
Short name T732
Test name
Test status
Simulation time 849507965 ps
CPU time 1.86 seconds
Started Jun 23 05:33:52 PM PDT 24
Finished Jun 23 05:33:54 PM PDT 24
Peak memory 214648 kb
Host smart-47fd3795-85db-48e0-adab-2ec1959c5409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356460258 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.356460258
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.563599274
Short name T239
Test name
Test status
Simulation time 107399884776 ps
CPU time 630.83 seconds
Started Jun 23 05:33:52 PM PDT 24
Finished Jun 23 05:44:23 PM PDT 24
Peak memory 218892 kb
Host smart-15be74ed-e05a-401b-926d-e1eeb7c4f45c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563599274 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.563599274
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.4089078085
Short name T530
Test name
Test status
Simulation time 42011129 ps
CPU time 1.09 seconds
Started Jun 23 05:34:59 PM PDT 24
Finished Jun 23 05:35:00 PM PDT 24
Peak memory 219076 kb
Host smart-0d9a4eac-ae84-4ead-af68-1cc3214e2d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089078085 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.4089078085
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3315458483
Short name T951
Test name
Test status
Simulation time 18598304 ps
CPU time 0.97 seconds
Started Jun 23 05:35:07 PM PDT 24
Finished Jun 23 05:35:08 PM PDT 24
Peak memory 214608 kb
Host smart-0e9e9069-1d70-4140-8933-55afef5bffb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315458483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3315458483
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1984516125
Short name T129
Test name
Test status
Simulation time 21895456 ps
CPU time 0.86 seconds
Started Jun 23 05:35:00 PM PDT 24
Finished Jun 23 05:35:01 PM PDT 24
Peak memory 215824 kb
Host smart-ced674f0-1d61-41bf-8b45-4cc42a83e7ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984516125 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1984516125
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2910394541
Short name T440
Test name
Test status
Simulation time 184838368 ps
CPU time 1.18 seconds
Started Jun 23 05:35:00 PM PDT 24
Finished Jun 23 05:35:02 PM PDT 24
Peak memory 217600 kb
Host smart-d8be8106-99af-4ba5-b8e9-c38d9db84402
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910394541 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2910394541
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.2668073531
Short name T140
Test name
Test status
Simulation time 37081078 ps
CPU time 0.98 seconds
Started Jun 23 05:34:59 PM PDT 24
Finished Jun 23 05:35:00 PM PDT 24
Peak memory 219168 kb
Host smart-7fecf11b-d944-410b-bc68-69e06e1a912e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668073531 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2668073531
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.365580235
Short name T356
Test name
Test status
Simulation time 126788713 ps
CPU time 1.13 seconds
Started Jun 23 05:35:01 PM PDT 24
Finished Jun 23 05:35:03 PM PDT 24
Peak memory 216556 kb
Host smart-f183a822-3468-4054-b5f8-7eef74c1ac6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365580235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.365580235
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.359358993
Short name T36
Test name
Test status
Simulation time 19745359 ps
CPU time 1.16 seconds
Started Jun 23 05:35:01 PM PDT 24
Finished Jun 23 05:35:03 PM PDT 24
Peak memory 215184 kb
Host smart-d4ee61e2-2ad1-43f6-985c-87d5363ea3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359358993 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.359358993
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3652942892
Short name T901
Test name
Test status
Simulation time 85658746 ps
CPU time 0.92 seconds
Started Jun 23 05:35:01 PM PDT 24
Finished Jun 23 05:35:03 PM PDT 24
Peak memory 214572 kb
Host smart-e5a0f545-e8be-41b3-b95f-27891eae0e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652942892 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3652942892
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.802097422
Short name T244
Test name
Test status
Simulation time 240968594 ps
CPU time 4.9 seconds
Started Jun 23 05:34:58 PM PDT 24
Finished Jun 23 05:35:04 PM PDT 24
Peak memory 214620 kb
Host smart-a029f30e-45c3-4bde-a28c-f70f7d24e917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802097422 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.802097422
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3720897738
Short name T584
Test name
Test status
Simulation time 387450886144 ps
CPU time 1088.41 seconds
Started Jun 23 05:35:08 PM PDT 24
Finished Jun 23 05:53:17 PM PDT 24
Peak memory 222800 kb
Host smart-eec4b056-5ffd-43f4-959a-c3bf9fc14217
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720897738 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3720897738
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3748543002
Short name T163
Test name
Test status
Simulation time 85752585 ps
CPU time 1.24 seconds
Started Jun 23 05:35:06 PM PDT 24
Finished Jun 23 05:35:08 PM PDT 24
Peak memory 218012 kb
Host smart-f1854f04-d4a7-4677-bd74-c509fe3b5ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748543002 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3748543002
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3155133473
Short name T360
Test name
Test status
Simulation time 56798275 ps
CPU time 0.91 seconds
Started Jun 23 05:35:04 PM PDT 24
Finished Jun 23 05:35:05 PM PDT 24
Peak memory 205920 kb
Host smart-76c4b867-2be7-4768-9ad3-2d240f9250b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155133473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3155133473
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.1529479445
Short name T184
Test name
Test status
Simulation time 68256307 ps
CPU time 0.81 seconds
Started Jun 23 05:35:08 PM PDT 24
Finished Jun 23 05:35:09 PM PDT 24
Peak memory 215820 kb
Host smart-28a3e662-ae48-41b9-b458-f3ee0d04317e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529479445 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1529479445
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3655870151
Short name T105
Test name
Test status
Simulation time 38242662 ps
CPU time 1.31 seconds
Started Jun 23 05:35:04 PM PDT 24
Finished Jun 23 05:35:06 PM PDT 24
Peak memory 216320 kb
Host smart-d4a66c90-0252-4d81-a1d0-0b47737710ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655870151 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3655870151
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1678541573
Short name T920
Test name
Test status
Simulation time 65941751 ps
CPU time 1.03 seconds
Started Jun 23 05:35:07 PM PDT 24
Finished Jun 23 05:35:09 PM PDT 24
Peak memory 219292 kb
Host smart-dcd3b200-9d16-40c9-8cef-e30d5c1e7211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678541573 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1678541573
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.737680410
Short name T987
Test name
Test status
Simulation time 43617533 ps
CPU time 1.42 seconds
Started Jun 23 05:35:05 PM PDT 24
Finished Jun 23 05:35:07 PM PDT 24
Peak memory 217800 kb
Host smart-1878ccef-d42d-468c-b2b0-4982b3d5a2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737680410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.737680410
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.728432833
Short name T740
Test name
Test status
Simulation time 22490041 ps
CPU time 1.12 seconds
Started Jun 23 05:35:04 PM PDT 24
Finished Jun 23 05:35:05 PM PDT 24
Peak memory 215012 kb
Host smart-1efd2257-e0f9-47dd-86ad-2afdc337a3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728432833 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.728432833
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1502182659
Short name T72
Test name
Test status
Simulation time 18238327 ps
CPU time 0.97 seconds
Started Jun 23 05:35:07 PM PDT 24
Finished Jun 23 05:35:09 PM PDT 24
Peak memory 214636 kb
Host smart-66fa77b3-85a0-478a-bec1-1e95e29e9ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502182659 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1502182659
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3309262385
Short name T120
Test name
Test status
Simulation time 337380172 ps
CPU time 3.24 seconds
Started Jun 23 05:35:05 PM PDT 24
Finished Jun 23 05:35:09 PM PDT 24
Peak memory 219344 kb
Host smart-8a5f1a4d-24d9-472d-b101-3ae65ec142c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309262385 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3309262385
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.560423030
Short name T394
Test name
Test status
Simulation time 305307694388 ps
CPU time 1822.24 seconds
Started Jun 23 05:35:06 PM PDT 24
Finished Jun 23 06:05:29 PM PDT 24
Peak memory 227580 kb
Host smart-6a5261b2-ddd5-4a6b-b6e9-3609b9221ef9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560423030 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.560423030
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3127431865
Short name T707
Test name
Test status
Simulation time 63497898 ps
CPU time 1.04 seconds
Started Jun 23 05:35:09 PM PDT 24
Finished Jun 23 05:35:11 PM PDT 24
Peak memory 218120 kb
Host smart-1fa7278e-cc83-4c6a-a21d-e335bada3710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127431865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3127431865
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.4148264753
Short name T476
Test name
Test status
Simulation time 147202384 ps
CPU time 1 seconds
Started Jun 23 05:35:09 PM PDT 24
Finished Jun 23 05:35:10 PM PDT 24
Peak memory 206148 kb
Host smart-f7b2414e-712f-49ec-976e-c4bd2e986487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148264753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.4148264753
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1844256738
Short name T930
Test name
Test status
Simulation time 25797390 ps
CPU time 0.79 seconds
Started Jun 23 05:35:12 PM PDT 24
Finished Jun 23 05:35:13 PM PDT 24
Peak memory 215760 kb
Host smart-69259818-d243-4615-8002-71a776b8bde2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844256738 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1844256738
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2144310825
Short name T934
Test name
Test status
Simulation time 76975711 ps
CPU time 1.02 seconds
Started Jun 23 05:35:09 PM PDT 24
Finished Jun 23 05:35:11 PM PDT 24
Peak memory 216188 kb
Host smart-042f2ff5-9f0a-4d56-ab6f-8a03911a4d5c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144310825 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2144310825
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2689748845
Short name T173
Test name
Test status
Simulation time 39907098 ps
CPU time 0.86 seconds
Started Jun 23 05:35:09 PM PDT 24
Finished Jun 23 05:35:11 PM PDT 24
Peak memory 217620 kb
Host smart-8a43ee3c-d812-46e8-a75e-b37fbe18441a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689748845 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2689748845
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2497652788
Short name T573
Test name
Test status
Simulation time 35471008 ps
CPU time 1.26 seconds
Started Jun 23 05:35:05 PM PDT 24
Finished Jun 23 05:35:06 PM PDT 24
Peak memory 217640 kb
Host smart-86db91c9-7271-4fca-865f-25de22451cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497652788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2497652788
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3586776477
Short name T543
Test name
Test status
Simulation time 23094641 ps
CPU time 1.12 seconds
Started Jun 23 05:35:07 PM PDT 24
Finished Jun 23 05:35:09 PM PDT 24
Peak memory 215008 kb
Host smart-0ccf72f2-fdb4-47f6-a481-cf5f392d7b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586776477 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3586776477
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.407301583
Short name T916
Test name
Test status
Simulation time 44808860 ps
CPU time 0.84 seconds
Started Jun 23 05:35:06 PM PDT 24
Finished Jun 23 05:35:07 PM PDT 24
Peak memory 214004 kb
Host smart-f6dc2915-2fd9-4799-a469-1e7777a7da67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407301583 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.407301583
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1519108648
Short name T552
Test name
Test status
Simulation time 483670539 ps
CPU time 5.02 seconds
Started Jun 23 05:35:04 PM PDT 24
Finished Jun 23 05:35:10 PM PDT 24
Peak memory 214616 kb
Host smart-5dd20214-8fb5-489c-a034-74b6ad8212b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519108648 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1519108648
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3489146602
Short name T229
Test name
Test status
Simulation time 1273280294086 ps
CPU time 1949.97 seconds
Started Jun 23 05:35:09 PM PDT 24
Finished Jun 23 06:07:39 PM PDT 24
Peak memory 223800 kb
Host smart-92632af6-1b8e-4055-a996-fdfd32d3fd08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489146602 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3489146602
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3593137020
Short name T731
Test name
Test status
Simulation time 51860940 ps
CPU time 1.09 seconds
Started Jun 23 05:35:10 PM PDT 24
Finished Jun 23 05:35:12 PM PDT 24
Peak memory 217988 kb
Host smart-567fab9b-8211-4bf9-aa90-b81c654256c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593137020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3593137020
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.352793693
Short name T482
Test name
Test status
Simulation time 130213734 ps
CPU time 0.91 seconds
Started Jun 23 05:35:10 PM PDT 24
Finished Jun 23 05:35:12 PM PDT 24
Peak memory 214288 kb
Host smart-f3db7725-3eb0-44c3-840e-66e5e29cf1a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352793693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.352793693
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1510196081
Short name T467
Test name
Test status
Simulation time 61347771 ps
CPU time 1.04 seconds
Started Jun 23 05:35:10 PM PDT 24
Finished Jun 23 05:35:11 PM PDT 24
Peak memory 219216 kb
Host smart-b0775158-4224-45cd-88ec-5cd9b07ebba9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510196081 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1510196081
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.930339702
Short name T547
Test name
Test status
Simulation time 28596191 ps
CPU time 1.12 seconds
Started Jun 23 05:35:10 PM PDT 24
Finished Jun 23 05:35:12 PM PDT 24
Peak memory 223348 kb
Host smart-6b4d3c1c-cd55-4165-864c-1322e1a1a14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930339702 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.930339702
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2489687571
Short name T630
Test name
Test status
Simulation time 122585673 ps
CPU time 1.15 seconds
Started Jun 23 05:35:08 PM PDT 24
Finished Jun 23 05:35:10 PM PDT 24
Peak memory 218652 kb
Host smart-3e9555d8-3179-4e07-8434-e0fd85951007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489687571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2489687571
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2599443472
Short name T388
Test name
Test status
Simulation time 22418813 ps
CPU time 1.2 seconds
Started Jun 23 05:35:10 PM PDT 24
Finished Jun 23 05:35:12 PM PDT 24
Peak memory 215008 kb
Host smart-57fcbbe5-5e6e-4fcc-b5cd-cff494d81624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599443472 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2599443472
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2037862712
Short name T418
Test name
Test status
Simulation time 50217874 ps
CPU time 0.93 seconds
Started Jun 23 05:35:10 PM PDT 24
Finished Jun 23 05:35:12 PM PDT 24
Peak memory 214628 kb
Host smart-2b310abd-3078-4184-9daf-424982826c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037862712 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2037862712
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2731379939
Short name T55
Test name
Test status
Simulation time 755538925 ps
CPU time 4.65 seconds
Started Jun 23 05:35:10 PM PDT 24
Finished Jun 23 05:35:16 PM PDT 24
Peak memory 216604 kb
Host smart-f0756db2-8444-469a-86ec-e4571cd9191a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731379939 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2731379939
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.298295515
Short name T991
Test name
Test status
Simulation time 56659642154 ps
CPU time 364.97 seconds
Started Jun 23 05:35:11 PM PDT 24
Finished Jun 23 05:41:17 PM PDT 24
Peak memory 216632 kb
Host smart-796af53e-917d-46f8-b29e-54d214eebfe3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298295515 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.298295515
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3174415751
Short name T162
Test name
Test status
Simulation time 38019759 ps
CPU time 1.14 seconds
Started Jun 23 05:35:10 PM PDT 24
Finished Jun 23 05:35:11 PM PDT 24
Peak memory 218148 kb
Host smart-af735cb5-58cd-4c95-b44a-7937177c91e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174415751 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3174415751
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3690011242
Short name T869
Test name
Test status
Simulation time 35690475 ps
CPU time 0.9 seconds
Started Jun 23 05:35:10 PM PDT 24
Finished Jun 23 05:35:11 PM PDT 24
Peak memory 205924 kb
Host smart-40f6e6fe-6088-4e2b-a4fa-7ce6dc439937
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690011242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3690011242
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3176408268
Short name T772
Test name
Test status
Simulation time 11933859 ps
CPU time 0.89 seconds
Started Jun 23 05:35:10 PM PDT 24
Finished Jun 23 05:35:12 PM PDT 24
Peak memory 215976 kb
Host smart-8d075e94-926b-4d91-98df-e7a02a727cbd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176408268 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3176408268
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.45611447
Short name T278
Test name
Test status
Simulation time 48117542 ps
CPU time 1.1 seconds
Started Jun 23 05:35:10 PM PDT 24
Finished Jun 23 05:35:12 PM PDT 24
Peak memory 216304 kb
Host smart-68a6eed3-afb4-44e2-8956-6df25778d060
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45611447 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_dis
able_auto_req_mode.45611447
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.1745944857
Short name T156
Test name
Test status
Simulation time 34857791 ps
CPU time 1.07 seconds
Started Jun 23 05:35:09 PM PDT 24
Finished Jun 23 05:35:11 PM PDT 24
Peak memory 223464 kb
Host smart-8c392aaa-b0a6-4406-9c03-75eb37097299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745944857 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1745944857
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2882305948
Short name T685
Test name
Test status
Simulation time 108160664 ps
CPU time 1.53 seconds
Started Jun 23 05:35:13 PM PDT 24
Finished Jun 23 05:35:15 PM PDT 24
Peak memory 218124 kb
Host smart-cd159c47-a8e3-4e0e-84a0-33490905fa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882305948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2882305948
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2688857046
Short name T833
Test name
Test status
Simulation time 53029640 ps
CPU time 0.91 seconds
Started Jun 23 05:35:11 PM PDT 24
Finished Jun 23 05:35:12 PM PDT 24
Peak memory 214892 kb
Host smart-f49b4557-cd0c-4612-96b4-8bec5ad25311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688857046 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2688857046
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.4091158668
Short name T697
Test name
Test status
Simulation time 20629199 ps
CPU time 0.93 seconds
Started Jun 23 05:35:11 PM PDT 24
Finished Jun 23 05:35:12 PM PDT 24
Peak memory 214596 kb
Host smart-d429d289-3d46-4930-987f-c5f41425dad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091158668 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.4091158668
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.4022729747
Short name T879
Test name
Test status
Simulation time 452377642 ps
CPU time 1.81 seconds
Started Jun 23 05:35:11 PM PDT 24
Finished Jun 23 05:35:13 PM PDT 24
Peak memory 216636 kb
Host smart-beb01b14-c43b-4aea-9c6e-01c8c6f2bbc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022729747 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.4022729747
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3022356994
Short name T435
Test name
Test status
Simulation time 233761943561 ps
CPU time 844.62 seconds
Started Jun 23 05:35:08 PM PDT 24
Finished Jun 23 05:49:13 PM PDT 24
Peak memory 222888 kb
Host smart-95ceccb2-f5ce-4d09-bd1d-c59d9698874c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022356994 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3022356994
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2643700008
Short name T294
Test name
Test status
Simulation time 69251328 ps
CPU time 1.08 seconds
Started Jun 23 05:35:13 PM PDT 24
Finished Jun 23 05:35:15 PM PDT 24
Peak memory 219712 kb
Host smart-2e579e0e-43da-4b8c-a888-007cccdf1038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643700008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2643700008
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1486927775
Short name T406
Test name
Test status
Simulation time 67273660 ps
CPU time 0.9 seconds
Started Jun 23 05:35:13 PM PDT 24
Finished Jun 23 05:35:15 PM PDT 24
Peak memory 206104 kb
Host smart-52fbb01e-8dca-46fb-830b-2252c54aa327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486927775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1486927775
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1963870791
Short name T682
Test name
Test status
Simulation time 16188081 ps
CPU time 0.85 seconds
Started Jun 23 05:35:12 PM PDT 24
Finished Jun 23 05:35:13 PM PDT 24
Peak memory 215652 kb
Host smart-1f2a4bab-874a-449f-a812-2e1fa5477c63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963870791 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1963870791
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2704842378
Short name T796
Test name
Test status
Simulation time 20975793 ps
CPU time 1.02 seconds
Started Jun 23 05:35:13 PM PDT 24
Finished Jun 23 05:35:15 PM PDT 24
Peak memory 217712 kb
Host smart-4622f336-1c87-4306-808b-07d63372bca1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704842378 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2704842378
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1134813112
Short name T875
Test name
Test status
Simulation time 44829592 ps
CPU time 1.25 seconds
Started Jun 23 05:35:14 PM PDT 24
Finished Jun 23 05:35:15 PM PDT 24
Peak memory 225228 kb
Host smart-d016697a-0a70-4c2b-b552-c9054cb40aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134813112 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1134813112
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3976683666
Short name T736
Test name
Test status
Simulation time 45025256 ps
CPU time 1.13 seconds
Started Jun 23 05:35:14 PM PDT 24
Finished Jun 23 05:35:16 PM PDT 24
Peak memory 216628 kb
Host smart-ea30eba6-49eb-4abd-bb5d-3db8f81b4c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976683666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3976683666
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1676893010
Short name T817
Test name
Test status
Simulation time 21500188 ps
CPU time 1.24 seconds
Started Jun 23 05:35:15 PM PDT 24
Finished Jun 23 05:35:17 PM PDT 24
Peak memory 223364 kb
Host smart-d854719d-9626-420d-8dad-4f670d4e9f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676893010 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1676893010
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.719308307
Short name T996
Test name
Test status
Simulation time 19138120 ps
CPU time 1.01 seconds
Started Jun 23 05:35:13 PM PDT 24
Finished Jun 23 05:35:14 PM PDT 24
Peak memory 214588 kb
Host smart-385747c3-8d30-4fe9-8765-e99e74e04fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719308307 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.719308307
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1081907627
Short name T826
Test name
Test status
Simulation time 137408715 ps
CPU time 1.17 seconds
Started Jun 23 05:35:19 PM PDT 24
Finished Jun 23 05:35:21 PM PDT 24
Peak memory 205960 kb
Host smart-caa269f6-703f-4d36-aba0-2abfbdc6fd01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081907627 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1081907627
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1330675758
Short name T938
Test name
Test status
Simulation time 97265742644 ps
CPU time 536.3 seconds
Started Jun 23 05:35:13 PM PDT 24
Finished Jun 23 05:44:10 PM PDT 24
Peak memory 222892 kb
Host smart-fc4ab0ac-c0a2-4ab5-8df6-242334ad8df2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330675758 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1330675758
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1801474614
Short name T850
Test name
Test status
Simulation time 26018457 ps
CPU time 1.15 seconds
Started Jun 23 05:35:19 PM PDT 24
Finished Jun 23 05:35:21 PM PDT 24
Peak memory 217680 kb
Host smart-590f97c2-af72-4cbd-9c93-69f0def4610b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801474614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1801474614
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2387375023
Short name T963
Test name
Test status
Simulation time 64565172 ps
CPU time 0.88 seconds
Started Jun 23 05:35:21 PM PDT 24
Finished Jun 23 05:35:22 PM PDT 24
Peak memory 206144 kb
Host smart-099d80ff-1381-497e-8da5-6797ea029748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387375023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2387375023
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1587608483
Short name T219
Test name
Test status
Simulation time 37736330 ps
CPU time 0.83 seconds
Started Jun 23 05:35:19 PM PDT 24
Finished Jun 23 05:35:20 PM PDT 24
Peak memory 215632 kb
Host smart-0b10fcd7-15fb-419a-bceb-a13d5bed9652
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587608483 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1587608483
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1732853696
Short name T959
Test name
Test status
Simulation time 196889706 ps
CPU time 0.97 seconds
Started Jun 23 05:35:19 PM PDT 24
Finished Jun 23 05:35:20 PM PDT 24
Peak memory 216892 kb
Host smart-beb828c2-f00b-427b-888e-0c1c46492008
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732853696 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1732853696
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2242884900
Short name T918
Test name
Test status
Simulation time 21023653 ps
CPU time 1.15 seconds
Started Jun 23 05:35:19 PM PDT 24
Finished Jun 23 05:35:21 PM PDT 24
Peak memory 217948 kb
Host smart-0a724cc1-2a8a-4501-9abe-c0bdaa826998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242884900 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2242884900
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.41468961
Short name T791
Test name
Test status
Simulation time 146390611 ps
CPU time 1.06 seconds
Started Jun 23 05:35:18 PM PDT 24
Finished Jun 23 05:35:19 PM PDT 24
Peak memory 216668 kb
Host smart-fc746df0-8e2a-4061-aaa7-a1d0ecb69828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41468961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.41468961
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.286436268
Short name T625
Test name
Test status
Simulation time 33643124 ps
CPU time 0.84 seconds
Started Jun 23 05:35:17 PM PDT 24
Finished Jun 23 05:35:19 PM PDT 24
Peak memory 214620 kb
Host smart-e8926676-222b-4174-8a89-bdcdc4dbd3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286436268 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.286436268
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3961246881
Short name T351
Test name
Test status
Simulation time 121636204 ps
CPU time 0.96 seconds
Started Jun 23 05:35:12 PM PDT 24
Finished Jun 23 05:35:13 PM PDT 24
Peak memory 214632 kb
Host smart-e189dec2-fe0b-4eaf-bc9a-99e7bb11ee92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961246881 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3961246881
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3343045374
Short name T727
Test name
Test status
Simulation time 238477884 ps
CPU time 4.62 seconds
Started Jun 23 05:35:14 PM PDT 24
Finished Jun 23 05:35:19 PM PDT 24
Peak memory 217836 kb
Host smart-76333808-d22b-4ab1-a92e-702efc041d1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343045374 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3343045374
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3746602081
Short name T366
Test name
Test status
Simulation time 74901740302 ps
CPU time 1799.43 seconds
Started Jun 23 05:35:12 PM PDT 24
Finished Jun 23 06:05:12 PM PDT 24
Peak memory 227228 kb
Host smart-dd562ef1-5b4b-4532-9a78-b172833af4f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746602081 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3746602081
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2379812428
Short name T873
Test name
Test status
Simulation time 41946760 ps
CPU time 1.13 seconds
Started Jun 23 05:35:20 PM PDT 24
Finished Jun 23 05:35:21 PM PDT 24
Peak memory 220128 kb
Host smart-6106b330-82b1-4bbb-b3a6-772050926847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379812428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2379812428
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2120299280
Short name T946
Test name
Test status
Simulation time 15908252 ps
CPU time 0.9 seconds
Started Jun 23 05:35:21 PM PDT 24
Finished Jun 23 05:35:22 PM PDT 24
Peak memory 206092 kb
Host smart-bd8e0c3a-5c87-43ec-8605-f31a6a4f0645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120299280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2120299280
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3539244025
Short name T92
Test name
Test status
Simulation time 45918379 ps
CPU time 0.88 seconds
Started Jun 23 05:35:21 PM PDT 24
Finished Jun 23 05:35:22 PM PDT 24
Peak memory 215700 kb
Host smart-c1bc1a67-f679-4b3d-828c-2a1cc01e87f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539244025 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3539244025
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2927305632
Short name T144
Test name
Test status
Simulation time 39900880 ps
CPU time 1.45 seconds
Started Jun 23 05:35:25 PM PDT 24
Finished Jun 23 05:35:28 PM PDT 24
Peak memory 216404 kb
Host smart-64c00180-99be-4643-b923-f4f6dc03dab1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927305632 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2927305632
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2479215839
Short name T985
Test name
Test status
Simulation time 36993458 ps
CPU time 1.03 seconds
Started Jun 23 05:35:21 PM PDT 24
Finished Jun 23 05:35:23 PM PDT 24
Peak memory 223240 kb
Host smart-1775ab2c-c467-4276-9d99-c2194c48a995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479215839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2479215839
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2736840112
Short name T828
Test name
Test status
Simulation time 71839269 ps
CPU time 1.19 seconds
Started Jun 23 05:35:23 PM PDT 24
Finished Jun 23 05:35:24 PM PDT 24
Peak memory 216808 kb
Host smart-8766c506-7d64-4feb-af98-f3209962cc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736840112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2736840112
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2079378327
Short name T664
Test name
Test status
Simulation time 19773696 ps
CPU time 1.05 seconds
Started Jun 23 05:35:18 PM PDT 24
Finished Jun 23 05:35:20 PM PDT 24
Peak memory 215064 kb
Host smart-571c74ba-bf4c-495b-9f56-492833e895a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079378327 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2079378327
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3115234756
Short name T437
Test name
Test status
Simulation time 40439742 ps
CPU time 0.97 seconds
Started Jun 23 05:35:20 PM PDT 24
Finished Jun 23 05:35:21 PM PDT 24
Peak memory 214656 kb
Host smart-ba44be22-ec0b-456b-989f-9bc190c29a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115234756 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3115234756
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.290459341
Short name T69
Test name
Test status
Simulation time 591374132 ps
CPU time 3.31 seconds
Started Jun 23 05:35:19 PM PDT 24
Finished Jun 23 05:35:23 PM PDT 24
Peak memory 216644 kb
Host smart-2798cecb-b451-49e3-a381-d9c93b94519e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290459341 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.290459341
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3700486867
Short name T391
Test name
Test status
Simulation time 45252825208 ps
CPU time 1136.41 seconds
Started Jun 23 05:35:22 PM PDT 24
Finished Jun 23 05:54:19 PM PDT 24
Peak memory 222936 kb
Host smart-5b0a36a3-8b6c-4463-b8d1-893fa9325a5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700486867 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3700486867
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1011549920
Short name T686
Test name
Test status
Simulation time 69693311 ps
CPU time 1.04 seconds
Started Jun 23 05:35:20 PM PDT 24
Finished Jun 23 05:35:22 PM PDT 24
Peak memory 219248 kb
Host smart-1da0a112-cf1e-4d48-9218-b9d64c56a9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011549920 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1011549920
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1863305704
Short name T759
Test name
Test status
Simulation time 21875244 ps
CPU time 0.86 seconds
Started Jun 23 05:35:25 PM PDT 24
Finished Jun 23 05:35:26 PM PDT 24
Peak memory 206136 kb
Host smart-2a894537-3b35-497c-b55a-122c0b2071bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863305704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1863305704
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.166217092
Short name T96
Test name
Test status
Simulation time 10633860 ps
CPU time 0.89 seconds
Started Jun 23 05:35:21 PM PDT 24
Finished Jun 23 05:35:22 PM PDT 24
Peak memory 215332 kb
Host smart-0491d41c-c863-46f2-8f18-cb6f15ea4af6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166217092 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.166217092
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.883944602
Short name T647
Test name
Test status
Simulation time 126792463 ps
CPU time 1.14 seconds
Started Jun 23 05:35:24 PM PDT 24
Finished Jun 23 05:35:26 PM PDT 24
Peak memory 217884 kb
Host smart-fd12098a-707e-4893-bf77-7677761405e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883944602 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.883944602
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.2632909277
Short name T157
Test name
Test status
Simulation time 39408545 ps
CPU time 1.1 seconds
Started Jun 23 05:35:22 PM PDT 24
Finished Jun 23 05:35:23 PM PDT 24
Peak memory 217880 kb
Host smart-1f15389e-2300-4de5-901a-d5fd6ff502b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632909277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2632909277
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1679935250
Short name T410
Test name
Test status
Simulation time 36009937 ps
CPU time 1.44 seconds
Started Jun 23 05:35:20 PM PDT 24
Finished Jun 23 05:35:22 PM PDT 24
Peak memory 216800 kb
Host smart-a60f81ba-531b-432e-9a5a-63d822ad9858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679935250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1679935250
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1971437959
Short name T113
Test name
Test status
Simulation time 29573059 ps
CPU time 0.9 seconds
Started Jun 23 05:35:24 PM PDT 24
Finished Jun 23 05:35:25 PM PDT 24
Peak memory 215152 kb
Host smart-b14f34c4-e921-4c11-8c95-6b084567cbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971437959 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1971437959
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3687426183
Short name T733
Test name
Test status
Simulation time 53194521 ps
CPU time 0.91 seconds
Started Jun 23 05:35:24 PM PDT 24
Finished Jun 23 05:35:25 PM PDT 24
Peak memory 214640 kb
Host smart-2c81425e-fa43-4698-b55d-1f48bc124c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687426183 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3687426183
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.596410277
Short name T116
Test name
Test status
Simulation time 202745626 ps
CPU time 1.37 seconds
Started Jun 23 05:35:21 PM PDT 24
Finished Jun 23 05:35:23 PM PDT 24
Peak memory 217764 kb
Host smart-f0280f0a-770b-4ac5-801e-df7a3aeaa8bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596410277 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.596410277
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1189077693
Short name T545
Test name
Test status
Simulation time 68119349994 ps
CPU time 831.16 seconds
Started Jun 23 05:35:25 PM PDT 24
Finished Jun 23 05:49:17 PM PDT 24
Peak memory 222160 kb
Host smart-380d8db5-e051-4414-b5ec-f08f6538fdb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189077693 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1189077693
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2031295696
Short name T708
Test name
Test status
Simulation time 79467500 ps
CPU time 1.22 seconds
Started Jun 23 05:35:24 PM PDT 24
Finished Jun 23 05:35:25 PM PDT 24
Peak memory 218060 kb
Host smart-6dd27aa4-561c-48a5-b801-96e9266ec8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031295696 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2031295696
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3029612824
Short name T509
Test name
Test status
Simulation time 20677577 ps
CPU time 0.87 seconds
Started Jun 23 05:35:26 PM PDT 24
Finished Jun 23 05:35:28 PM PDT 24
Peak memory 214320 kb
Host smart-9fd0959a-a7da-407c-8399-2c25d7c7af53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029612824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3029612824
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2780840464
Short name T893
Test name
Test status
Simulation time 61641633 ps
CPU time 0.94 seconds
Started Jun 23 05:35:27 PM PDT 24
Finished Jun 23 05:35:28 PM PDT 24
Peak memory 215828 kb
Host smart-5ab9abae-967d-482e-87a0-2c51c53210a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780840464 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2780840464
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1075426087
Short name T143
Test name
Test status
Simulation time 81428490 ps
CPU time 1.07 seconds
Started Jun 23 05:35:26 PM PDT 24
Finished Jun 23 05:35:28 PM PDT 24
Peak memory 216312 kb
Host smart-06ca9e2d-eed5-4e9f-8265-339e5c16e5f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075426087 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1075426087
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2662297264
Short name T594
Test name
Test status
Simulation time 29245982 ps
CPU time 1.24 seconds
Started Jun 23 05:35:22 PM PDT 24
Finished Jun 23 05:35:24 PM PDT 24
Peak memory 219028 kb
Host smart-d775caa8-ab6f-430b-9d6a-9624f978817f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662297264 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2662297264
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3617373302
Short name T307
Test name
Test status
Simulation time 79281026 ps
CPU time 2.36 seconds
Started Jun 23 05:35:24 PM PDT 24
Finished Jun 23 05:35:27 PM PDT 24
Peak memory 219304 kb
Host smart-8e634673-23b2-45d0-8ac4-af194c5bf273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617373302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3617373302
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2533570323
Short name T491
Test name
Test status
Simulation time 31172119 ps
CPU time 0.89 seconds
Started Jun 23 05:35:25 PM PDT 24
Finished Jun 23 05:35:26 PM PDT 24
Peak memory 215052 kb
Host smart-680645da-3dbc-4e5c-b4eb-0a2a8689e1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533570323 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2533570323
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.151699959
Short name T352
Test name
Test status
Simulation time 65166344 ps
CPU time 1.02 seconds
Started Jun 23 05:35:25 PM PDT 24
Finished Jun 23 05:35:27 PM PDT 24
Peak memory 213864 kb
Host smart-21738676-8463-4fc3-8452-bcc945f5a122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151699959 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.151699959
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2710754881
Short name T614
Test name
Test status
Simulation time 241755050 ps
CPU time 1.71 seconds
Started Jun 23 05:35:23 PM PDT 24
Finished Jun 23 05:35:26 PM PDT 24
Peak memory 214604 kb
Host smart-52b5d322-d504-47e3-967e-178514530ff4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710754881 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2710754881
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3620003405
Short name T878
Test name
Test status
Simulation time 41490405757 ps
CPU time 505.21 seconds
Started Jun 23 05:35:23 PM PDT 24
Finished Jun 23 05:43:48 PM PDT 24
Peak memory 217336 kb
Host smart-74d62774-69a9-4758-add9-59995be90b3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620003405 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3620003405
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3980481426
Short name T693
Test name
Test status
Simulation time 47258028 ps
CPU time 1.21 seconds
Started Jun 23 05:33:58 PM PDT 24
Finished Jun 23 05:33:59 PM PDT 24
Peak memory 220632 kb
Host smart-6864a565-08ac-46f6-aee0-6f28b420a5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980481426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3980481426
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3278868979
Short name T542
Test name
Test status
Simulation time 29786983 ps
CPU time 1.15 seconds
Started Jun 23 05:33:55 PM PDT 24
Finished Jun 23 05:33:57 PM PDT 24
Peak memory 206264 kb
Host smart-a79bca1b-4535-4d6e-b403-0c0f0016bf6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278868979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3278868979
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2675129625
Short name T207
Test name
Test status
Simulation time 15687998 ps
CPU time 0.83 seconds
Started Jun 23 05:34:00 PM PDT 24
Finished Jun 23 05:34:01 PM PDT 24
Peak memory 215680 kb
Host smart-e58e71ef-727d-4db5-8517-1ef08f6c7751
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675129625 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2675129625
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3418862665
Short name T447
Test name
Test status
Simulation time 126542748 ps
CPU time 1.09 seconds
Started Jun 23 05:33:54 PM PDT 24
Finished Jun 23 05:33:55 PM PDT 24
Peak memory 217588 kb
Host smart-2412f791-be6f-4cee-bf43-a8531f352e6b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418862665 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3418862665
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2482967935
Short name T220
Test name
Test status
Simulation time 160123015 ps
CPU time 1.04 seconds
Started Jun 23 05:34:00 PM PDT 24
Finished Jun 23 05:34:01 PM PDT 24
Peak memory 219132 kb
Host smart-f19dc50d-d400-4508-ba08-f949c6b11445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482967935 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2482967935
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1553625009
Short name T456
Test name
Test status
Simulation time 105701980 ps
CPU time 1.71 seconds
Started Jun 23 05:33:59 PM PDT 24
Finished Jun 23 05:34:01 PM PDT 24
Peak memory 218292 kb
Host smart-bbd93bb6-d551-42a5-b100-d10db91f1557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553625009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1553625009
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3011358463
Short name T51
Test name
Test status
Simulation time 23408357 ps
CPU time 1.03 seconds
Started Jun 23 05:33:55 PM PDT 24
Finished Jun 23 05:33:57 PM PDT 24
Peak memory 214760 kb
Host smart-ce51c3ab-1b35-4fee-bd06-6d1b8e29f372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011358463 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3011358463
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.666032888
Short name T660
Test name
Test status
Simulation time 17835966 ps
CPU time 1.02 seconds
Started Jun 23 05:33:56 PM PDT 24
Finished Jun 23 05:33:57 PM PDT 24
Peak memory 206484 kb
Host smart-7b383da9-5e00-40a6-831e-e1001001710b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666032888 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.666032888
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3194587421
Short name T65
Test name
Test status
Simulation time 443075246 ps
CPU time 7.5 seconds
Started Jun 23 05:33:55 PM PDT 24
Finished Jun 23 05:34:03 PM PDT 24
Peak memory 235828 kb
Host smart-41dc784f-9d84-4363-9f1c-23670829b404
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194587421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3194587421
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.4131153827
Short name T857
Test name
Test status
Simulation time 19120863 ps
CPU time 0.99 seconds
Started Jun 23 05:33:56 PM PDT 24
Finished Jun 23 05:33:57 PM PDT 24
Peak memory 206412 kb
Host smart-50a35e41-736a-43f4-96af-e1986c815609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131153827 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.4131153827
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.878049170
Short name T687
Test name
Test status
Simulation time 267834266 ps
CPU time 2.93 seconds
Started Jun 23 05:33:55 PM PDT 24
Finished Jun 23 05:33:58 PM PDT 24
Peak memory 214636 kb
Host smart-1fdd2d60-44d3-4d84-a990-e80c40e750c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878049170 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.878049170
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_alert.1772036680
Short name T73
Test name
Test status
Simulation time 139387567 ps
CPU time 1.34 seconds
Started Jun 23 05:35:23 PM PDT 24
Finished Jun 23 05:35:25 PM PDT 24
Peak memory 218332 kb
Host smart-a7f8f8ba-cc5c-4254-b83a-7277fec396f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772036680 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1772036680
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3439424083
Short name T719
Test name
Test status
Simulation time 62620084 ps
CPU time 0.97 seconds
Started Jun 23 05:35:25 PM PDT 24
Finished Jun 23 05:35:26 PM PDT 24
Peak memory 206144 kb
Host smart-6e48b405-5727-4a57-8bc6-71f41da7e21e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439424083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3439424083
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3676002739
Short name T729
Test name
Test status
Simulation time 165149753 ps
CPU time 0.85 seconds
Started Jun 23 05:35:23 PM PDT 24
Finished Jun 23 05:35:24 PM PDT 24
Peak memory 215696 kb
Host smart-7fdd3b0f-b7d1-4cd6-8495-2209b3d8017e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676002739 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3676002739
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1838695158
Short name T20
Test name
Test status
Simulation time 328253981 ps
CPU time 1.03 seconds
Started Jun 23 05:35:29 PM PDT 24
Finished Jun 23 05:35:31 PM PDT 24
Peak memory 216292 kb
Host smart-c249c413-806b-4746-9a13-a822883aa9eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838695158 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1838695158
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2576791661
Short name T484
Test name
Test status
Simulation time 27485100 ps
CPU time 0.95 seconds
Started Jun 23 05:35:23 PM PDT 24
Finished Jun 23 05:35:24 PM PDT 24
Peak memory 219064 kb
Host smart-8d27046d-241d-4e80-b930-24a773f929db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576791661 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2576791661
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1958286790
Short name T689
Test name
Test status
Simulation time 256756617 ps
CPU time 3.32 seconds
Started Jun 23 05:35:23 PM PDT 24
Finished Jun 23 05:35:27 PM PDT 24
Peak memory 219428 kb
Host smart-76caf54b-7998-4009-87b2-50191ce7c8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958286790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1958286790
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1569481905
Short name T109
Test name
Test status
Simulation time 111523834 ps
CPU time 0.82 seconds
Started Jun 23 05:35:25 PM PDT 24
Finished Jun 23 05:35:27 PM PDT 24
Peak memory 214836 kb
Host smart-f42a82bf-504d-4ddf-acd1-99681b3ba78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569481905 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1569481905
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.758738049
Short name T811
Test name
Test status
Simulation time 27683762 ps
CPU time 0.99 seconds
Started Jun 23 05:35:24 PM PDT 24
Finished Jun 23 05:35:25 PM PDT 24
Peak memory 214648 kb
Host smart-ff27faec-868a-4861-a7b5-4d8f3f3b905a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758738049 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.758738049
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1779528466
Short name T886
Test name
Test status
Simulation time 484589231 ps
CPU time 3.12 seconds
Started Jun 23 05:35:28 PM PDT 24
Finished Jun 23 05:35:32 PM PDT 24
Peak memory 219584 kb
Host smart-38aee9ae-9025-47b9-8b17-afbe18a6f304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779528466 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1779528466
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.607926613
Short name T404
Test name
Test status
Simulation time 136433682003 ps
CPU time 806.46 seconds
Started Jun 23 05:35:25 PM PDT 24
Finished Jun 23 05:48:53 PM PDT 24
Peak memory 220976 kb
Host smart-e8190f12-e8f5-469b-9934-f81d26a679e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607926613 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.607926613
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3013894564
Short name T150
Test name
Test status
Simulation time 62881413 ps
CPU time 1.11 seconds
Started Jun 23 05:35:25 PM PDT 24
Finished Jun 23 05:35:26 PM PDT 24
Peak memory 219200 kb
Host smart-d93ad3c5-7669-403d-b8ab-05174ac27fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013894564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3013894564
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2963218177
Short name T704
Test name
Test status
Simulation time 27381245 ps
CPU time 1.01 seconds
Started Jun 23 05:35:28 PM PDT 24
Finished Jun 23 05:35:30 PM PDT 24
Peak memory 206088 kb
Host smart-e6ac50ac-35d4-4c5a-9ad7-84e548dfbca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963218177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2963218177
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3824274258
Short name T706
Test name
Test status
Simulation time 27885025 ps
CPU time 0.92 seconds
Started Jun 23 05:35:23 PM PDT 24
Finished Jun 23 05:35:24 PM PDT 24
Peak memory 215848 kb
Host smart-ea192bfe-9dad-41f2-bb4a-b57a9b6d5231
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824274258 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3824274258
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2138551675
Short name T75
Test name
Test status
Simulation time 72869927 ps
CPU time 1.01 seconds
Started Jun 23 05:35:28 PM PDT 24
Finished Jun 23 05:35:29 PM PDT 24
Peak memory 216232 kb
Host smart-5dc0ea8b-f8f8-424d-a4c4-c51f2d5dc9bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138551675 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2138551675
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_genbits.1515193506
Short name T679
Test name
Test status
Simulation time 185946042 ps
CPU time 1.3 seconds
Started Jun 23 05:35:25 PM PDT 24
Finished Jun 23 05:35:27 PM PDT 24
Peak memory 216692 kb
Host smart-585fe8da-c88a-4315-b753-42e5bd619256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515193506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1515193506
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1002662927
Short name T498
Test name
Test status
Simulation time 25310315 ps
CPU time 1.03 seconds
Started Jun 23 05:35:26 PM PDT 24
Finished Jun 23 05:35:28 PM PDT 24
Peak memory 223384 kb
Host smart-9df2dc33-50bd-483b-9847-0332ec64d688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002662927 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1002662927
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2081449577
Short name T423
Test name
Test status
Simulation time 69949125 ps
CPU time 0.93 seconds
Started Jun 23 05:35:25 PM PDT 24
Finished Jun 23 05:35:26 PM PDT 24
Peak memory 214704 kb
Host smart-ff202a26-9fa5-4cd6-8842-f583922daf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081449577 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2081449577
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.128953108
Short name T245
Test name
Test status
Simulation time 408981215 ps
CPU time 2.28 seconds
Started Jun 23 05:35:23 PM PDT 24
Finished Jun 23 05:35:26 PM PDT 24
Peak memory 216740 kb
Host smart-6cb00732-5236-4d32-ab1d-f093439a67ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128953108 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.128953108
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_alert.3434567310
Short name T86
Test name
Test status
Simulation time 145878534 ps
CPU time 1.29 seconds
Started Jun 23 05:35:26 PM PDT 24
Finished Jun 23 05:35:28 PM PDT 24
Peak memory 218104 kb
Host smart-7cacd052-b6e7-42ea-a7c1-73906ffc6dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434567310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3434567310
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.873931159
Short name T788
Test name
Test status
Simulation time 22666835 ps
CPU time 1.04 seconds
Started Jun 23 05:35:37 PM PDT 24
Finished Jun 23 05:35:39 PM PDT 24
Peak memory 214404 kb
Host smart-4a886dfe-c33b-4ff2-91b3-22af6da8ff64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873931159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.873931159
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1922526437
Short name T823
Test name
Test status
Simulation time 120822012 ps
CPU time 0.84 seconds
Started Jun 23 05:35:30 PM PDT 24
Finished Jun 23 05:35:32 PM PDT 24
Peak memory 214844 kb
Host smart-d834f7d3-9502-4b2e-996f-c1bfb29a4d27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922526437 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1922526437
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.363192817
Short name T134
Test name
Test status
Simulation time 37261189 ps
CPU time 1.27 seconds
Started Jun 23 05:35:28 PM PDT 24
Finished Jun 23 05:35:30 PM PDT 24
Peak memory 216240 kb
Host smart-71b42e95-7dfc-4f4d-84ef-82f9b7afc03e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363192817 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.363192817
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3288507718
Short name T56
Test name
Test status
Simulation time 31348553 ps
CPU time 0.99 seconds
Started Jun 23 05:35:26 PM PDT 24
Finished Jun 23 05:35:28 PM PDT 24
Peak memory 223260 kb
Host smart-74cf76c8-3dd0-410e-b37b-0454371a73bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288507718 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3288507718
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3277575090
Short name T384
Test name
Test status
Simulation time 34549918 ps
CPU time 1.4 seconds
Started Jun 23 05:35:26 PM PDT 24
Finished Jun 23 05:35:28 PM PDT 24
Peak memory 219268 kb
Host smart-74ee70a6-bff7-4f40-ad33-8e859226b972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277575090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3277575090
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.995339810
Short name T709
Test name
Test status
Simulation time 23080791 ps
CPU time 1.17 seconds
Started Jun 23 05:35:25 PM PDT 24
Finished Jun 23 05:35:27 PM PDT 24
Peak memory 223384 kb
Host smart-b04d8cef-0371-4fa7-81d0-b61f5a1dcd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995339810 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.995339810
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3178709266
Short name T626
Test name
Test status
Simulation time 50957831 ps
CPU time 0.93 seconds
Started Jun 23 05:35:25 PM PDT 24
Finished Jun 23 05:35:27 PM PDT 24
Peak memory 214628 kb
Host smart-c3188fee-99fe-499b-b6d5-969f44a74e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178709266 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3178709266
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.633619926
Short name T723
Test name
Test status
Simulation time 181819540 ps
CPU time 3.79 seconds
Started Jun 23 05:35:23 PM PDT 24
Finished Jun 23 05:35:27 PM PDT 24
Peak memory 216588 kb
Host smart-be15be28-c6a3-43a6-a0d4-fb292ee85132
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633619926 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.633619926
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3690814267
Short name T809
Test name
Test status
Simulation time 204184307652 ps
CPU time 1314 seconds
Started Jun 23 05:35:24 PM PDT 24
Finished Jun 23 05:57:19 PM PDT 24
Peak memory 225024 kb
Host smart-b256c78a-bda2-457a-92f5-283dc4038daa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690814267 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3690814267
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.392145089
Short name T717
Test name
Test status
Simulation time 28854341 ps
CPU time 1.33 seconds
Started Jun 23 05:35:31 PM PDT 24
Finished Jun 23 05:35:33 PM PDT 24
Peak memory 220024 kb
Host smart-e82a9dc3-0b78-48dc-8949-328b54333491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392145089 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.392145089
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1205671656
Short name T915
Test name
Test status
Simulation time 32252510 ps
CPU time 0.96 seconds
Started Jun 23 05:35:37 PM PDT 24
Finished Jun 23 05:35:38 PM PDT 24
Peak memory 206064 kb
Host smart-0bd8e5e5-f7d8-4a1e-ab0e-bb9aa9e60726
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205671656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1205671656
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2467052094
Short name T768
Test name
Test status
Simulation time 14679280 ps
CPU time 0.91 seconds
Started Jun 23 05:35:32 PM PDT 24
Finished Jun 23 05:35:33 PM PDT 24
Peak memory 215420 kb
Host smart-35e1613f-8fdd-4ec1-abff-aea12cba58be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467052094 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2467052094
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3190727636
Short name T167
Test name
Test status
Simulation time 54939562 ps
CPU time 1.25 seconds
Started Jun 23 05:35:29 PM PDT 24
Finished Jun 23 05:35:31 PM PDT 24
Peak memory 216132 kb
Host smart-73d6bb23-8d78-451e-a0ef-5c0b5d074816
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190727636 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3190727636
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.4175800020
Short name T774
Test name
Test status
Simulation time 90112344 ps
CPU time 0.85 seconds
Started Jun 23 05:35:37 PM PDT 24
Finished Jun 23 05:35:39 PM PDT 24
Peak memory 217936 kb
Host smart-2c30aaac-09f6-466c-ada3-daa65acc9dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175800020 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.4175800020
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1490596599
Short name T853
Test name
Test status
Simulation time 40728916 ps
CPU time 1.73 seconds
Started Jun 23 05:35:28 PM PDT 24
Finished Jun 23 05:35:31 PM PDT 24
Peak memory 218128 kb
Host smart-afd6588a-48cc-47df-be7c-4efb2bbbdea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490596599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1490596599
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2333729693
Short name T37
Test name
Test status
Simulation time 27903279 ps
CPU time 0.92 seconds
Started Jun 23 05:35:37 PM PDT 24
Finished Jun 23 05:35:38 PM PDT 24
Peak memory 215052 kb
Host smart-4e57c27c-5990-4fbf-822c-1b533490a8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333729693 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2333729693
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1192672252
Short name T503
Test name
Test status
Simulation time 49642962 ps
CPU time 1 seconds
Started Jun 23 05:35:29 PM PDT 24
Finished Jun 23 05:35:30 PM PDT 24
Peak memory 214668 kb
Host smart-11789ad0-a6dd-416d-8f6c-0dae8b58a64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192672252 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1192672252
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1413126556
Short name T246
Test name
Test status
Simulation time 116018576 ps
CPU time 1.47 seconds
Started Jun 23 05:35:38 PM PDT 24
Finished Jun 23 05:35:40 PM PDT 24
Peak memory 206516 kb
Host smart-9ac97613-aa96-4b1d-8a13-22228b1518b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413126556 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1413126556
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2793648983
Short name T898
Test name
Test status
Simulation time 69433404643 ps
CPU time 879.21 seconds
Started Jun 23 05:35:30 PM PDT 24
Finished Jun 23 05:50:10 PM PDT 24
Peak memory 222928 kb
Host smart-ec917f9d-d256-4c0d-8c39-3acdd40c6a73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793648983 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2793648983
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3772287916
Short name T856
Test name
Test status
Simulation time 39529714 ps
CPU time 1.11 seconds
Started Jun 23 05:35:36 PM PDT 24
Finished Jun 23 05:35:37 PM PDT 24
Peak memory 219940 kb
Host smart-a7d1a1a0-fa74-4f88-bf18-9c0b2238a275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772287916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3772287916
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.635000949
Short name T720
Test name
Test status
Simulation time 12609347 ps
CPU time 0.84 seconds
Started Jun 23 05:35:27 PM PDT 24
Finished Jun 23 05:35:29 PM PDT 24
Peak memory 206228 kb
Host smart-23e54933-aead-4879-b5c0-8fadbe152bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635000949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.635000949
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.832684093
Short name T179
Test name
Test status
Simulation time 18002837 ps
CPU time 0.84 seconds
Started Jun 23 05:35:36 PM PDT 24
Finished Jun 23 05:35:37 PM PDT 24
Peak memory 215556 kb
Host smart-bfc23430-b855-45f1-8098-02ccc1837146
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832684093 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.832684093
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2792315238
Short name T277
Test name
Test status
Simulation time 32236238 ps
CPU time 1.22 seconds
Started Jun 23 05:35:29 PM PDT 24
Finished Jun 23 05:35:31 PM PDT 24
Peak memory 217620 kb
Host smart-55bc799c-58bf-4197-abed-c42af9312462
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792315238 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2792315238
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3623004495
Short name T78
Test name
Test status
Simulation time 31537769 ps
CPU time 0.84 seconds
Started Jun 23 05:35:29 PM PDT 24
Finished Jun 23 05:35:30 PM PDT 24
Peak memory 217448 kb
Host smart-c65b1e2b-8a45-4a2f-b021-ad5a778c6c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623004495 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3623004495
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2554307034
Short name T428
Test name
Test status
Simulation time 97902454 ps
CPU time 1.22 seconds
Started Jun 23 05:35:31 PM PDT 24
Finished Jun 23 05:35:33 PM PDT 24
Peak memory 216844 kb
Host smart-87b60584-c2c6-4e3a-af5f-76965b1e1f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554307034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2554307034
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.690921039
Short name T128
Test name
Test status
Simulation time 30952369 ps
CPU time 0.92 seconds
Started Jun 23 05:35:34 PM PDT 24
Finished Jun 23 05:35:35 PM PDT 24
Peak memory 215088 kb
Host smart-10db2533-539d-4899-8833-c33effdf89a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690921039 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.690921039
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3694680495
Short name T519
Test name
Test status
Simulation time 49122611 ps
CPU time 0.92 seconds
Started Jun 23 05:35:38 PM PDT 24
Finished Jun 23 05:35:39 PM PDT 24
Peak memory 214632 kb
Host smart-50da5740-72a4-457b-963b-6abf52c0fda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694680495 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3694680495
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.438419046
Short name T734
Test name
Test status
Simulation time 367895290 ps
CPU time 6.9 seconds
Started Jun 23 05:35:37 PM PDT 24
Finished Jun 23 05:35:44 PM PDT 24
Peak memory 217964 kb
Host smart-168ed3f5-0265-4fa0-94f7-2c7bf5fced8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438419046 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.438419046
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2942765639
Short name T231
Test name
Test status
Simulation time 32072399032 ps
CPU time 357.33 seconds
Started Jun 23 05:35:30 PM PDT 24
Finished Jun 23 05:41:28 PM PDT 24
Peak memory 222916 kb
Host smart-5cc3d2f4-3d21-4e07-bf6f-fe1bd523212c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942765639 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2942765639
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1382084379
Short name T296
Test name
Test status
Simulation time 89121695 ps
CPU time 1.25 seconds
Started Jun 23 05:35:37 PM PDT 24
Finished Jun 23 05:35:39 PM PDT 24
Peak memory 218368 kb
Host smart-ce3e44c6-761a-4593-87a7-9cc41396249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382084379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1382084379
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3433822518
Short name T22
Test name
Test status
Simulation time 24208362 ps
CPU time 1.08 seconds
Started Jun 23 05:35:36 PM PDT 24
Finished Jun 23 05:35:37 PM PDT 24
Peak memory 214540 kb
Host smart-84496412-d308-40eb-b86a-4285ae1ce250
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433822518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3433822518
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3430437524
Short name T756
Test name
Test status
Simulation time 14523094 ps
CPU time 0.94 seconds
Started Jun 23 05:35:32 PM PDT 24
Finished Jun 23 05:35:33 PM PDT 24
Peak memory 215944 kb
Host smart-c4816695-bd90-4d8d-a25c-38c9adac48ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430437524 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3430437524
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1097764041
Short name T493
Test name
Test status
Simulation time 45183322 ps
CPU time 1.51 seconds
Started Jun 23 05:35:39 PM PDT 24
Finished Jun 23 05:35:41 PM PDT 24
Peak memory 216372 kb
Host smart-19798dfd-dc9e-4c58-a8df-ef8a85281a60
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097764041 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1097764041
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1588286744
Short name T908
Test name
Test status
Simulation time 34053672 ps
CPU time 1.26 seconds
Started Jun 23 05:35:34 PM PDT 24
Finished Jun 23 05:35:36 PM PDT 24
Peak memory 219248 kb
Host smart-b22b4ae3-cd3b-4a04-a2d1-ac8169104a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588286744 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1588286744
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2035278170
Short name T532
Test name
Test status
Simulation time 51573225 ps
CPU time 1.39 seconds
Started Jun 23 05:35:40 PM PDT 24
Finished Jun 23 05:35:42 PM PDT 24
Peak memory 216608 kb
Host smart-977676be-de97-4d66-8103-fda22f3d505f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035278170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2035278170
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1203518490
Short name T429
Test name
Test status
Simulation time 22730964 ps
CPU time 1.2 seconds
Started Jun 23 05:35:38 PM PDT 24
Finished Jun 23 05:35:39 PM PDT 24
Peak memory 223380 kb
Host smart-63dd2de0-fdd0-4f48-9790-58a47a96d88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203518490 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1203518490
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2064100284
Short name T611
Test name
Test status
Simulation time 71786321 ps
CPU time 0.93 seconds
Started Jun 23 05:35:35 PM PDT 24
Finished Jun 23 05:35:36 PM PDT 24
Peak memory 214628 kb
Host smart-c807e05c-ea94-4877-a615-a30282633d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064100284 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2064100284
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1848268448
Short name T795
Test name
Test status
Simulation time 24349585 ps
CPU time 1.11 seconds
Started Jun 23 05:35:32 PM PDT 24
Finished Jun 23 05:35:33 PM PDT 24
Peak memory 214596 kb
Host smart-0f8a89be-3183-4ebd-afb5-c68d61d7ff33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848268448 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1848268448
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2768831308
Short name T236
Test name
Test status
Simulation time 52952352335 ps
CPU time 1181.83 seconds
Started Jun 23 05:35:39 PM PDT 24
Finished Jun 23 05:55:21 PM PDT 24
Peak memory 222244 kb
Host smart-e81a8a9f-f64a-4389-b9b4-f7e97da78105
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768831308 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2768831308
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.693255673
Short name T565
Test name
Test status
Simulation time 71167033 ps
CPU time 1.1 seconds
Started Jun 23 05:35:43 PM PDT 24
Finished Jun 23 05:35:44 PM PDT 24
Peak memory 217916 kb
Host smart-f88f1630-d33b-4ffd-9b0d-63485be30ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693255673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.693255673
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4055518629
Short name T967
Test name
Test status
Simulation time 13965773 ps
CPU time 0.89 seconds
Started Jun 23 05:35:43 PM PDT 24
Finished Jun 23 05:35:45 PM PDT 24
Peak memory 206056 kb
Host smart-73cad19e-1949-4402-bbbe-e183ffc8fd48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055518629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4055518629
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.58899459
Short name T466
Test name
Test status
Simulation time 70606162 ps
CPU time 0.88 seconds
Started Jun 23 05:35:38 PM PDT 24
Finished Jun 23 05:35:39 PM PDT 24
Peak memory 215668 kb
Host smart-ce4f6606-dddd-414e-9b3f-adeb01ce9bf5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58899459 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.58899459
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1739929422
Short name T136
Test name
Test status
Simulation time 44720923 ps
CPU time 1.19 seconds
Started Jun 23 05:35:40 PM PDT 24
Finished Jun 23 05:35:42 PM PDT 24
Peak memory 216340 kb
Host smart-130514ea-dcb0-4ce1-91f7-280ba4a86a4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739929422 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1739929422
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1527566063
Short name T201
Test name
Test status
Simulation time 24440532 ps
CPU time 0.96 seconds
Started Jun 23 05:35:40 PM PDT 24
Finished Jun 23 05:35:41 PM PDT 24
Peak memory 218680 kb
Host smart-799c29a1-8073-440c-81ab-b29223462434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527566063 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1527566063
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1895266761
Short name T590
Test name
Test status
Simulation time 36293180 ps
CPU time 1.43 seconds
Started Jun 23 05:35:30 PM PDT 24
Finished Jun 23 05:35:32 PM PDT 24
Peak memory 218876 kb
Host smart-b9bfed41-e080-400b-a24e-8f4abd4be948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895266761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1895266761
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3310629405
Short name T995
Test name
Test status
Simulation time 21434147 ps
CPU time 1.05 seconds
Started Jun 23 05:35:36 PM PDT 24
Finished Jun 23 05:35:38 PM PDT 24
Peak memory 214880 kb
Host smart-05912269-ce1d-47ae-8841-6c3bdb3f23d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310629405 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3310629405
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.759370571
Short name T762
Test name
Test status
Simulation time 16069388 ps
CPU time 1 seconds
Started Jun 23 05:35:39 PM PDT 24
Finished Jun 23 05:35:40 PM PDT 24
Peak memory 213916 kb
Host smart-16bb804b-e804-4cff-a807-1a2f223d4e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759370571 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.759370571
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2526981269
Short name T115
Test name
Test status
Simulation time 476848532 ps
CPU time 4.7 seconds
Started Jun 23 05:35:36 PM PDT 24
Finished Jun 23 05:35:41 PM PDT 24
Peak memory 216504 kb
Host smart-df2cd311-f96a-4d71-83b1-476b9106c7c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526981269 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2526981269
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.657479603
Short name T868
Test name
Test status
Simulation time 100635786673 ps
CPU time 1349.38 seconds
Started Jun 23 05:35:38 PM PDT 24
Finished Jun 23 05:58:08 PM PDT 24
Peak memory 224532 kb
Host smart-f156a591-7f48-4dbf-ae4a-19d9fbb56288
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657479603 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.657479603
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1187557520
Short name T983
Test name
Test status
Simulation time 25116193 ps
CPU time 1.12 seconds
Started Jun 23 05:35:37 PM PDT 24
Finished Jun 23 05:35:39 PM PDT 24
Peak memory 219964 kb
Host smart-1c3737b8-ed73-4544-a10c-ea89383d6f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187557520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1187557520
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2677578892
Short name T600
Test name
Test status
Simulation time 40054128 ps
CPU time 0.94 seconds
Started Jun 23 05:35:39 PM PDT 24
Finished Jun 23 05:35:41 PM PDT 24
Peak memory 214608 kb
Host smart-05361b19-a38a-4f27-aa3e-4f38bea05558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677578892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2677578892
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.4196233752
Short name T48
Test name
Test status
Simulation time 12554758 ps
CPU time 0.9 seconds
Started Jun 23 05:35:38 PM PDT 24
Finished Jun 23 05:35:39 PM PDT 24
Peak memory 214980 kb
Host smart-a6df50c3-12cf-4ef5-8be4-00aaaebe6647
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196233752 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.4196233752
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3107340579
Short name T989
Test name
Test status
Simulation time 101753950 ps
CPU time 1.08 seconds
Started Jun 23 05:35:45 PM PDT 24
Finished Jun 23 05:35:46 PM PDT 24
Peak memory 216172 kb
Host smart-e30e4541-eb36-46f6-b608-1c8914729a49
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107340579 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3107340579
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.912041874
Short name T133
Test name
Test status
Simulation time 24610462 ps
CPU time 1.01 seconds
Started Jun 23 05:35:40 PM PDT 24
Finished Jun 23 05:35:41 PM PDT 24
Peak memory 219108 kb
Host smart-55cb7e9f-b739-491a-a3a7-e42f5a7af4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912041874 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.912041874
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.4091964349
Short name T335
Test name
Test status
Simulation time 31177651 ps
CPU time 1.31 seconds
Started Jun 23 05:35:39 PM PDT 24
Finished Jun 23 05:35:41 PM PDT 24
Peak memory 219152 kb
Host smart-9810209f-b505-4806-8b1f-e10fc3030026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091964349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.4091964349
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1392929702
Short name T790
Test name
Test status
Simulation time 24696133 ps
CPU time 1.22 seconds
Started Jun 23 05:35:37 PM PDT 24
Finished Jun 23 05:35:39 PM PDT 24
Peak memory 223376 kb
Host smart-3fd10c6f-4f3f-4d32-b085-96c019d33146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392929702 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1392929702
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2357271471
Short name T505
Test name
Test status
Simulation time 43957547 ps
CPU time 0.89 seconds
Started Jun 23 05:35:39 PM PDT 24
Finished Jun 23 05:35:40 PM PDT 24
Peak memory 214636 kb
Host smart-7d6a46c9-3f7f-435a-bbf8-a040c23f3e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357271471 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2357271471
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1169766900
Short name T248
Test name
Test status
Simulation time 297522455 ps
CPU time 3.42 seconds
Started Jun 23 05:35:44 PM PDT 24
Finished Jun 23 05:35:48 PM PDT 24
Peak memory 214604 kb
Host smart-7ab934bb-30cf-42fb-9b09-41a9e04ae0c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169766900 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1169766900
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.338232847
Short name T760
Test name
Test status
Simulation time 25470054735 ps
CPU time 657.48 seconds
Started Jun 23 05:35:39 PM PDT 24
Finished Jun 23 05:46:37 PM PDT 24
Peak memory 217868 kb
Host smart-8866c849-df50-4325-9659-24525bd1f14f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338232847 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.338232847
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2367626513
Short name T181
Test name
Test status
Simulation time 59262852 ps
CPU time 1.17 seconds
Started Jun 23 05:35:44 PM PDT 24
Finished Jun 23 05:35:46 PM PDT 24
Peak memory 218932 kb
Host smart-40807344-5a73-439d-a61c-50672b9053de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367626513 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2367626513
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.4131613638
Short name T770
Test name
Test status
Simulation time 65894370 ps
CPU time 0.99 seconds
Started Jun 23 05:35:48 PM PDT 24
Finished Jun 23 05:35:50 PM PDT 24
Peak memory 206224 kb
Host smart-4762a824-335c-4904-94e0-454b51fc571e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131613638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.4131613638
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3332188229
Short name T28
Test name
Test status
Simulation time 120664436 ps
CPU time 0.91 seconds
Started Jun 23 05:35:45 PM PDT 24
Finished Jun 23 05:35:46 PM PDT 24
Peak memory 215328 kb
Host smart-752af845-2559-4d78-92c6-e3c3f2153665
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332188229 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3332188229
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.920580413
Short name T587
Test name
Test status
Simulation time 38470766 ps
CPU time 1.21 seconds
Started Jun 23 05:35:44 PM PDT 24
Finished Jun 23 05:35:45 PM PDT 24
Peak memory 217632 kb
Host smart-d06cf589-647a-4645-9161-242089d9b920
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920580413 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.920580413
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.794210122
Short name T141
Test name
Test status
Simulation time 56571129 ps
CPU time 1.04 seconds
Started Jun 23 05:35:48 PM PDT 24
Finished Jun 23 05:35:49 PM PDT 24
Peak memory 219964 kb
Host smart-da29e1e4-a06a-4e4c-9ff9-79ec7bb14382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794210122 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.794210122
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.4186834297
Short name T336
Test name
Test status
Simulation time 74824514 ps
CPU time 1.61 seconds
Started Jun 23 05:35:40 PM PDT 24
Finished Jun 23 05:35:42 PM PDT 24
Peak memory 219620 kb
Host smart-952c8050-86f7-4231-af49-aa7da3e9e5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186834297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.4186834297
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1011214490
Short name T38
Test name
Test status
Simulation time 20498847 ps
CPU time 1.12 seconds
Started Jun 23 05:35:44 PM PDT 24
Finished Jun 23 05:35:45 PM PDT 24
Peak memory 215144 kb
Host smart-9259e4c4-cdf1-4472-841d-7b2bad9ef532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011214490 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1011214490
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.512246718
Short name T420
Test name
Test status
Simulation time 85562441 ps
CPU time 0.98 seconds
Started Jun 23 05:35:38 PM PDT 24
Finished Jun 23 05:35:39 PM PDT 24
Peak memory 214584 kb
Host smart-b37b4342-57d8-4902-b10f-1e640aec85b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512246718 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.512246718
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.4114467400
Short name T511
Test name
Test status
Simulation time 230545636 ps
CPU time 2.43 seconds
Started Jun 23 05:35:42 PM PDT 24
Finished Jun 23 05:35:45 PM PDT 24
Peak memory 216644 kb
Host smart-3402b7bf-3f9f-417d-b6cb-d28ccd26e9d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114467400 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.4114467400
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.4010721580
Short name T961
Test name
Test status
Simulation time 26852552209 ps
CPU time 687.79 seconds
Started Jun 23 05:35:38 PM PDT 24
Finished Jun 23 05:47:07 PM PDT 24
Peak memory 222928 kb
Host smart-0745d98b-0ebf-4fcc-8633-4a1536c6567b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010721580 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.4010721580
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.111597371
Short name T377
Test name
Test status
Simulation time 50510310 ps
CPU time 1.19 seconds
Started Jun 23 05:35:42 PM PDT 24
Finished Jun 23 05:35:44 PM PDT 24
Peak memory 219224 kb
Host smart-7d26b084-04b9-4eb6-89f0-d4393d064fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111597371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.111597371
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.812647125
Short name T524
Test name
Test status
Simulation time 16550675 ps
CPU time 0.85 seconds
Started Jun 23 05:35:43 PM PDT 24
Finished Jun 23 05:35:44 PM PDT 24
Peak memory 206084 kb
Host smart-6d322614-4f27-4459-8b60-50179f15e39b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812647125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.812647125
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3557599459
Short name T211
Test name
Test status
Simulation time 11241534 ps
CPU time 0.87 seconds
Started Jun 23 05:35:45 PM PDT 24
Finished Jun 23 05:35:46 PM PDT 24
Peak memory 215972 kb
Host smart-0471c6ec-5ab4-46bb-8c48-2da212d5a5c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557599459 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3557599459
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.4087587341
Short name T88
Test name
Test status
Simulation time 320859657 ps
CPU time 1.09 seconds
Started Jun 23 05:35:49 PM PDT 24
Finished Jun 23 05:35:51 PM PDT 24
Peak memory 216308 kb
Host smart-7720817a-f856-49fe-a330-405860976217
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087587341 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.4087587341
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1603852937
Short name T191
Test name
Test status
Simulation time 20098076 ps
CPU time 0.98 seconds
Started Jun 23 05:35:42 PM PDT 24
Finished Jun 23 05:35:43 PM PDT 24
Peak memory 217792 kb
Host smart-4643924e-5043-43ba-89b8-0a3825340c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603852937 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1603852937
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.523660431
Short name T537
Test name
Test status
Simulation time 84928659 ps
CPU time 1.24 seconds
Started Jun 23 05:35:42 PM PDT 24
Finished Jun 23 05:35:43 PM PDT 24
Peak memory 216800 kb
Host smart-f9de1e87-5c95-4525-9461-4bf891fefaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523660431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.523660431
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2987863821
Short name T34
Test name
Test status
Simulation time 19536046 ps
CPU time 1.08 seconds
Started Jun 23 05:35:43 PM PDT 24
Finished Jun 23 05:35:44 PM PDT 24
Peak memory 215128 kb
Host smart-a4e7f2c3-cdef-47a0-ba8e-4f26ee6c2403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987863821 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2987863821
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3205608016
Short name T571
Test name
Test status
Simulation time 43089465 ps
CPU time 0.91 seconds
Started Jun 23 05:35:43 PM PDT 24
Finished Jun 23 05:35:44 PM PDT 24
Peak memory 214652 kb
Host smart-ab4d7198-e21d-4d93-b16b-5751585a1f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205608016 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3205608016
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3401913761
Short name T361
Test name
Test status
Simulation time 221750784 ps
CPU time 2.5 seconds
Started Jun 23 05:35:48 PM PDT 24
Finished Jun 23 05:35:51 PM PDT 24
Peak memory 216548 kb
Host smart-7fe997d4-7172-4516-b76e-5507d84972f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401913761 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3401913761
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3772104251
Short name T240
Test name
Test status
Simulation time 133688487633 ps
CPU time 1492.61 seconds
Started Jun 23 05:35:43 PM PDT 24
Finished Jun 23 06:00:37 PM PDT 24
Peak memory 223268 kb
Host smart-2246d733-0cde-4ac4-b377-166ac37a59dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772104251 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3772104251
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.16471194
Short name T222
Test name
Test status
Simulation time 96756139 ps
CPU time 1.26 seconds
Started Jun 23 05:34:03 PM PDT 24
Finished Jun 23 05:34:04 PM PDT 24
Peak memory 217996 kb
Host smart-5934c5db-7811-4efd-b7a2-525edcbc7caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16471194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.16471194
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.4192852432
Short name T743
Test name
Test status
Simulation time 172539838 ps
CPU time 0.97 seconds
Started Jun 23 05:34:13 PM PDT 24
Finished Jun 23 05:34:14 PM PDT 24
Peak memory 205996 kb
Host smart-a86bd4dd-b00c-4c3d-becd-443f5d806633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192852432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.4192852432
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3968890266
Short name T945
Test name
Test status
Simulation time 11077988 ps
CPU time 0.89 seconds
Started Jun 23 05:34:02 PM PDT 24
Finished Jun 23 05:34:03 PM PDT 24
Peak memory 215460 kb
Host smart-2db00df4-4933-42e7-929b-84112973f799
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968890266 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3968890266
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3031330189
Short name T825
Test name
Test status
Simulation time 157983785 ps
CPU time 0.99 seconds
Started Jun 23 05:34:03 PM PDT 24
Finished Jun 23 05:34:04 PM PDT 24
Peak memory 219304 kb
Host smart-ecf3147c-2394-4fe5-8e80-bd83b4d487dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031330189 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3031330189
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1794729134
Short name T958
Test name
Test status
Simulation time 29597340 ps
CPU time 1.01 seconds
Started Jun 23 05:34:06 PM PDT 24
Finished Jun 23 05:34:08 PM PDT 24
Peak memory 223240 kb
Host smart-85afe4e3-b432-4c83-9119-ed6452563a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794729134 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1794729134
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1423993338
Short name T415
Test name
Test status
Simulation time 182721348 ps
CPU time 1.29 seconds
Started Jun 23 05:33:56 PM PDT 24
Finished Jun 23 05:33:57 PM PDT 24
Peak memory 217812 kb
Host smart-319650b2-4437-4726-be3c-58cfd7004729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423993338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1423993338
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3337273934
Short name T400
Test name
Test status
Simulation time 23843352 ps
CPU time 1.19 seconds
Started Jun 23 05:34:00 PM PDT 24
Finished Jun 23 05:34:02 PM PDT 24
Peak memory 223380 kb
Host smart-4cfe9a71-bb08-4b8f-a1f1-5d8044de41cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337273934 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3337273934
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2574805029
Short name T978
Test name
Test status
Simulation time 17454378 ps
CPU time 0.98 seconds
Started Jun 23 05:33:55 PM PDT 24
Finished Jun 23 05:33:57 PM PDT 24
Peak memory 206448 kb
Host smart-15e19215-1146-4be3-87d2-4109458d50fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574805029 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2574805029
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1752075140
Short name T986
Test name
Test status
Simulation time 19398320 ps
CPU time 1.07 seconds
Started Jun 23 05:33:57 PM PDT 24
Finished Jun 23 05:33:58 PM PDT 24
Peak memory 214492 kb
Host smart-b9670ca2-58e2-4133-bf13-bab92f0669e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752075140 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1752075140
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.20111691
Short name T936
Test name
Test status
Simulation time 713924932 ps
CPU time 4.14 seconds
Started Jun 23 05:33:54 PM PDT 24
Finished Jun 23 05:33:59 PM PDT 24
Peak memory 216712 kb
Host smart-69dae099-efae-4f35-a3d0-ed3fdfe8d9bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20111691 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.20111691
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1053873170
Short name T233
Test name
Test status
Simulation time 944264592326 ps
CPU time 2752.63 seconds
Started Jun 23 05:33:57 PM PDT 24
Finished Jun 23 06:19:50 PM PDT 24
Peak memory 227752 kb
Host smart-7693735b-db90-4a1b-8f3f-b506a744427c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053873170 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1053873170
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.2679122494
Short name T980
Test name
Test status
Simulation time 65885264 ps
CPU time 1.06 seconds
Started Jun 23 05:35:48 PM PDT 24
Finished Jun 23 05:35:50 PM PDT 24
Peak memory 219996 kb
Host smart-d79e5955-0b6c-45d3-9427-20cf3d1cfa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679122494 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2679122494
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.3782008284
Short name T460
Test name
Test status
Simulation time 26729983 ps
CPU time 0.97 seconds
Started Jun 23 05:35:48 PM PDT 24
Finished Jun 23 05:35:50 PM PDT 24
Peak memory 223252 kb
Host smart-cfc90816-95cd-49ad-84a4-cd2c68793c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782008284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3782008284
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3734986806
Short name T313
Test name
Test status
Simulation time 187163480 ps
CPU time 3.19 seconds
Started Jun 23 05:35:50 PM PDT 24
Finished Jun 23 05:35:53 PM PDT 24
Peak memory 217916 kb
Host smart-6bce9975-641d-4fd4-93a9-e2be04ac1b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734986806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3734986806
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.3435998955
Short name T668
Test name
Test status
Simulation time 45351803 ps
CPU time 1.2 seconds
Started Jun 23 05:35:48 PM PDT 24
Finished Jun 23 05:35:50 PM PDT 24
Peak memory 219152 kb
Host smart-260b2a45-f3e5-49e9-a10f-ce9696d8d5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435998955 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.3435998955
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.749624822
Short name T178
Test name
Test status
Simulation time 28825670 ps
CPU time 0.93 seconds
Started Jun 23 05:35:53 PM PDT 24
Finished Jun 23 05:35:54 PM PDT 24
Peak memory 217644 kb
Host smart-c70538d7-f17b-4b6f-8150-c253c4f452c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749624822 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.749624822
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.100066987
Short name T492
Test name
Test status
Simulation time 112376833 ps
CPU time 2.13 seconds
Started Jun 23 05:35:49 PM PDT 24
Finished Jun 23 05:35:51 PM PDT 24
Peak memory 217900 kb
Host smart-15a6a223-dec5-4b7b-b89f-7c9f264f2ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100066987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.100066987
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.2538033816
Short name T432
Test name
Test status
Simulation time 93164706 ps
CPU time 1.22 seconds
Started Jun 23 05:35:49 PM PDT 24
Finished Jun 23 05:35:51 PM PDT 24
Peak memory 217908 kb
Host smart-89582726-0803-417e-a269-be4868df8b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538033816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.2538033816
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.440665331
Short name T716
Test name
Test status
Simulation time 20961447 ps
CPU time 1.04 seconds
Started Jun 23 05:35:48 PM PDT 24
Finished Jun 23 05:35:50 PM PDT 24
Peak memory 217832 kb
Host smart-99238189-8605-4177-bc12-c19822fd3b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440665331 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.440665331
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3207907223
Short name T563
Test name
Test status
Simulation time 31650132 ps
CPU time 1.28 seconds
Started Jun 23 05:35:48 PM PDT 24
Finished Jun 23 05:35:50 PM PDT 24
Peak memory 216540 kb
Host smart-c6d6e3e8-c1b9-40f6-92a2-cce27883449d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207907223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3207907223
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.2851491790
Short name T597
Test name
Test status
Simulation time 26350702 ps
CPU time 1.29 seconds
Started Jun 23 05:35:48 PM PDT 24
Finished Jun 23 05:35:50 PM PDT 24
Peak memory 219352 kb
Host smart-c8e02bea-da05-410c-954c-fae11e578c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851491790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.2851491790
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.3660358345
Short name T926
Test name
Test status
Simulation time 70731745 ps
CPU time 1.18 seconds
Started Jun 23 05:35:48 PM PDT 24
Finished Jun 23 05:35:50 PM PDT 24
Peak memory 224988 kb
Host smart-014e110f-55a4-4452-a9fa-f364dfb714aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660358345 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3660358345
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1020793211
Short name T787
Test name
Test status
Simulation time 62577460 ps
CPU time 1.28 seconds
Started Jun 23 05:35:51 PM PDT 24
Finished Jun 23 05:35:53 PM PDT 24
Peak memory 216480 kb
Host smart-9f82eb13-8182-48c3-b345-a83cbdb0a113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020793211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1020793211
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.2330485269
Short name T695
Test name
Test status
Simulation time 209872238 ps
CPU time 1.24 seconds
Started Jun 23 05:35:53 PM PDT 24
Finished Jun 23 05:35:54 PM PDT 24
Peak memory 219084 kb
Host smart-0586d90c-43ce-4826-aa1a-df0b0d916459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330485269 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.2330485269
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_genbits.2644642990
Short name T520
Test name
Test status
Simulation time 49009949 ps
CPU time 1.16 seconds
Started Jun 23 05:35:48 PM PDT 24
Finished Jun 23 05:35:50 PM PDT 24
Peak memory 216568 kb
Host smart-6c9a837d-25ff-4147-bc3c-a1c4bff62091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644642990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2644642990
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.1126838650
Short name T971
Test name
Test status
Simulation time 74090424 ps
CPU time 1.06 seconds
Started Jun 23 05:35:48 PM PDT 24
Finished Jun 23 05:35:50 PM PDT 24
Peak memory 217972 kb
Host smart-f8bf24ff-2149-4735-898c-cb89128f68fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126838650 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.1126838650
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.3504928923
Short name T346
Test name
Test status
Simulation time 28400036 ps
CPU time 0.9 seconds
Started Jun 23 05:35:48 PM PDT 24
Finished Jun 23 05:35:49 PM PDT 24
Peak memory 217768 kb
Host smart-3dac63d3-4620-435d-a053-f4427a8632da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504928923 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3504928923
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.30238371
Short name T332
Test name
Test status
Simulation time 45465172 ps
CPU time 1.68 seconds
Started Jun 23 05:35:48 PM PDT 24
Finished Jun 23 05:35:50 PM PDT 24
Peak memory 219572 kb
Host smart-df98d6f8-f905-433e-bb4c-ea6917993c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30238371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.30238371
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.1487557166
Short name T253
Test name
Test status
Simulation time 83353407 ps
CPU time 1.21 seconds
Started Jun 23 05:35:49 PM PDT 24
Finished Jun 23 05:35:51 PM PDT 24
Peak memory 219724 kb
Host smart-29bf60cf-9525-4b66-be01-d251c07499d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487557166 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.1487557166
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.347010879
Short name T957
Test name
Test status
Simulation time 25719363 ps
CPU time 0.93 seconds
Started Jun 23 05:35:50 PM PDT 24
Finished Jun 23 05:35:51 PM PDT 24
Peak memory 217620 kb
Host smart-6f1275fd-deb1-4cca-b20a-775a687d043b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347010879 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.347010879
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1018482224
Short name T325
Test name
Test status
Simulation time 114242261 ps
CPU time 1.47 seconds
Started Jun 23 05:35:48 PM PDT 24
Finished Jun 23 05:35:50 PM PDT 24
Peak memory 217744 kb
Host smart-bef6b23f-83df-4c8d-8f02-35fda4bcd4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018482224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1018482224
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.3001401725
Short name T954
Test name
Test status
Simulation time 29152111 ps
CPU time 1.31 seconds
Started Jun 23 05:35:50 PM PDT 24
Finished Jun 23 05:35:52 PM PDT 24
Peak memory 219824 kb
Host smart-383195fa-5851-4b6e-99ce-9278105e405b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001401725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.3001401725
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.270090585
Short name T192
Test name
Test status
Simulation time 28206497 ps
CPU time 1.07 seconds
Started Jun 23 05:35:51 PM PDT 24
Finished Jun 23 05:35:52 PM PDT 24
Peak memory 223348 kb
Host smart-f3f1fd69-36f4-481d-a766-c2b10f36d8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270090585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.270090585
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.355660360
Short name T775
Test name
Test status
Simulation time 97200009 ps
CPU time 1.21 seconds
Started Jun 23 05:35:50 PM PDT 24
Finished Jun 23 05:35:52 PM PDT 24
Peak memory 217840 kb
Host smart-8547067e-bb9a-4a5d-977e-8ab41518dffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355660360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.355660360
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.474222077
Short name T839
Test name
Test status
Simulation time 27744596 ps
CPU time 1.31 seconds
Started Jun 23 05:35:53 PM PDT 24
Finished Jun 23 05:35:55 PM PDT 24
Peak memory 219028 kb
Host smart-5f8a29fd-a62d-432d-ad57-54d9f9bf8cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474222077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.474222077
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.2558326882
Short name T153
Test name
Test status
Simulation time 34803909 ps
CPU time 1.08 seconds
Started Jun 23 05:35:47 PM PDT 24
Finished Jun 23 05:35:48 PM PDT 24
Peak memory 220108 kb
Host smart-d4754f4e-05da-49e0-8482-c5975ec5c08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558326882 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2558326882
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3910521308
Short name T914
Test name
Test status
Simulation time 49045590 ps
CPU time 1.66 seconds
Started Jun 23 05:35:46 PM PDT 24
Finished Jun 23 05:35:48 PM PDT 24
Peak memory 217920 kb
Host smart-3fe0fc01-61e2-49f8-8be3-54907ebd60db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910521308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3910521308
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.1433067760
Short name T834
Test name
Test status
Simulation time 89250374 ps
CPU time 1.2 seconds
Started Jun 23 05:35:49 PM PDT 24
Finished Jun 23 05:35:51 PM PDT 24
Peak memory 219796 kb
Host smart-3f03bd36-74aa-45f6-8944-550ff4f1120a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433067760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.1433067760
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.2807962978
Short name T111
Test name
Test status
Simulation time 27799688 ps
CPU time 0.89 seconds
Started Jun 23 05:35:51 PM PDT 24
Finished Jun 23 05:35:52 PM PDT 24
Peak memory 218032 kb
Host smart-4fd537a0-152f-44b2-9517-ab1d0f14b1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807962978 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2807962978
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.1128086192
Short name T722
Test name
Test status
Simulation time 46167549 ps
CPU time 1.79 seconds
Started Jun 23 05:35:48 PM PDT 24
Finished Jun 23 05:35:51 PM PDT 24
Peak memory 217976 kb
Host smart-be16a6e4-89ed-4241-b1ba-df2d36b5ff8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128086192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1128086192
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2865835732
Short name T279
Test name
Test status
Simulation time 46510132 ps
CPU time 1.22 seconds
Started Jun 23 05:34:03 PM PDT 24
Finished Jun 23 05:34:05 PM PDT 24
Peak memory 219928 kb
Host smart-f58d6364-a69b-4ec3-94bb-f71d482a4458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865835732 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2865835732
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3566999485
Short name T419
Test name
Test status
Simulation time 55975481 ps
CPU time 0.98 seconds
Started Jun 23 05:34:01 PM PDT 24
Finished Jun 23 05:34:02 PM PDT 24
Peak memory 206100 kb
Host smart-0ab068c7-2f16-4686-bcef-846f685b2246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566999485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3566999485
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2739851490
Short name T960
Test name
Test status
Simulation time 66505682 ps
CPU time 1.27 seconds
Started Jun 23 05:33:59 PM PDT 24
Finished Jun 23 05:34:01 PM PDT 24
Peak memory 216148 kb
Host smart-f884a5c0-9a7a-44dd-bca8-02fad3e1e14b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739851490 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2739851490
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1482538867
Short name T990
Test name
Test status
Simulation time 43678290 ps
CPU time 1.09 seconds
Started Jun 23 05:33:59 PM PDT 24
Finished Jun 23 05:34:01 PM PDT 24
Peak memory 219116 kb
Host smart-13788721-2b34-4126-8ab6-770989a20162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482538867 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1482538867
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3082873059
Short name T315
Test name
Test status
Simulation time 65870787 ps
CPU time 1.43 seconds
Started Jun 23 05:34:02 PM PDT 24
Finished Jun 23 05:34:04 PM PDT 24
Peak memory 217928 kb
Host smart-a579fcd5-6ca3-4744-8d3b-a83108a26c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082873059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3082873059
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1349205185
Short name T33
Test name
Test status
Simulation time 19913452 ps
CPU time 1.09 seconds
Started Jun 23 05:34:03 PM PDT 24
Finished Jun 23 05:34:05 PM PDT 24
Peak memory 215168 kb
Host smart-adec56bf-3045-46c9-8550-acbba58c423e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349205185 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1349205185
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.369770396
Short name T789
Test name
Test status
Simulation time 66266691 ps
CPU time 0.91 seconds
Started Jun 23 05:34:03 PM PDT 24
Finished Jun 23 05:34:04 PM PDT 24
Peak memory 206456 kb
Host smart-b62730f0-2f7f-4c85-9a10-ab2d63fe138c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369770396 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.369770396
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3415225937
Short name T627
Test name
Test status
Simulation time 19584125 ps
CPU time 1.05 seconds
Started Jun 23 05:34:01 PM PDT 24
Finished Jun 23 05:34:02 PM PDT 24
Peak memory 214628 kb
Host smart-488d9fad-8e6d-483c-ae12-f6e166f0ca2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415225937 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3415225937
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1532768622
Short name T586
Test name
Test status
Simulation time 112242200 ps
CPU time 2.62 seconds
Started Jun 23 05:34:00 PM PDT 24
Finished Jun 23 05:34:04 PM PDT 24
Peak memory 214640 kb
Host smart-f0f73df2-502d-466e-a17f-f54659353cf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532768622 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1532768622
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.977677786
Short name T568
Test name
Test status
Simulation time 94665385234 ps
CPU time 532.96 seconds
Started Jun 23 05:34:01 PM PDT 24
Finished Jun 23 05:42:55 PM PDT 24
Peak memory 219680 kb
Host smart-e9eff812-237c-463a-9b6c-2b78ad8529a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977677786 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.977677786
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.25722326
Short name T633
Test name
Test status
Simulation time 27924719 ps
CPU time 1.28 seconds
Started Jun 23 05:35:53 PM PDT 24
Finished Jun 23 05:35:54 PM PDT 24
Peak memory 218000 kb
Host smart-cdab18c5-1dc7-4236-bab5-dc655a259ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25722326 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.25722326
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.3828257920
Short name T618
Test name
Test status
Simulation time 77886745 ps
CPU time 0.93 seconds
Started Jun 23 05:35:49 PM PDT 24
Finished Jun 23 05:35:50 PM PDT 24
Peak memory 223252 kb
Host smart-746637f2-ecb0-4950-be76-6c2077ec5949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828257920 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3828257920
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1138234870
Short name T541
Test name
Test status
Simulation time 70005528 ps
CPU time 1.26 seconds
Started Jun 23 05:35:53 PM PDT 24
Finished Jun 23 05:35:55 PM PDT 24
Peak memory 216448 kb
Host smart-795a6a3d-6585-4f0d-9241-a1ddfc555095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138234870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1138234870
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.306386021
Short name T688
Test name
Test status
Simulation time 22457789 ps
CPU time 1.02 seconds
Started Jun 23 05:35:55 PM PDT 24
Finished Jun 23 05:35:56 PM PDT 24
Peak memory 223208 kb
Host smart-d4a7d737-3925-4e27-96b9-8afcb6544019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306386021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.306386021
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.645719627
Short name T599
Test name
Test status
Simulation time 81777119 ps
CPU time 1.1 seconds
Started Jun 23 05:35:50 PM PDT 24
Finished Jun 23 05:35:52 PM PDT 24
Peak memory 216772 kb
Host smart-56cc20ee-9353-46b6-a4ae-38d29847d1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645719627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.645719627
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.103478411
Short name T408
Test name
Test status
Simulation time 49913154 ps
CPU time 1.29 seconds
Started Jun 23 05:35:53 PM PDT 24
Finished Jun 23 05:35:54 PM PDT 24
Peak memory 219024 kb
Host smart-f3c0fcb3-8bec-4836-944c-31a972abaf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103478411 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.103478411
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.1037735082
Short name T5
Test name
Test status
Simulation time 23406478 ps
CPU time 1.16 seconds
Started Jun 23 05:35:52 PM PDT 24
Finished Jun 23 05:35:54 PM PDT 24
Peak memory 219320 kb
Host smart-96396668-32b9-4776-b2b3-6c2f881cdf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037735082 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1037735082
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3885085792
Short name T392
Test name
Test status
Simulation time 47555390 ps
CPU time 1.21 seconds
Started Jun 23 05:35:51 PM PDT 24
Finished Jun 23 05:35:53 PM PDT 24
Peak memory 216784 kb
Host smart-32abfdd1-896a-4e94-a9ea-c0d2fa55038c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885085792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3885085792
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.749124651
Short name T139
Test name
Test status
Simulation time 52918025 ps
CPU time 1.16 seconds
Started Jun 23 05:35:51 PM PDT 24
Finished Jun 23 05:35:53 PM PDT 24
Peak memory 217996 kb
Host smart-31954fa5-bc77-471e-af75-5d8b4f664cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749124651 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.749124651
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.1049599427
Short name T426
Test name
Test status
Simulation time 28928185 ps
CPU time 0.97 seconds
Started Jun 23 05:35:50 PM PDT 24
Finished Jun 23 05:35:52 PM PDT 24
Peak memory 223244 kb
Host smart-3f9120ec-7f24-4eae-9111-fc6a4010db3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049599427 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1049599427
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3366461015
Short name T83
Test name
Test status
Simulation time 77339315 ps
CPU time 1.37 seconds
Started Jun 23 05:35:51 PM PDT 24
Finished Jun 23 05:35:52 PM PDT 24
Peak memory 214656 kb
Host smart-330aab63-9e2d-4051-995b-433755d33f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366461015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3366461015
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.1206045888
Short name T807
Test name
Test status
Simulation time 59553417 ps
CPU time 1.15 seconds
Started Jun 23 05:35:52 PM PDT 24
Finished Jun 23 05:35:54 PM PDT 24
Peak memory 219048 kb
Host smart-7a8753c5-6738-438a-ac9e-2ec75ddbfd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206045888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.1206045888
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.2268741634
Short name T515
Test name
Test status
Simulation time 44181708 ps
CPU time 1.12 seconds
Started Jun 23 05:35:57 PM PDT 24
Finished Jun 23 05:35:59 PM PDT 24
Peak memory 219168 kb
Host smart-473c7b8d-1c98-4ca3-b970-041b5cccda35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268741634 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2268741634
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1037740808
Short name T900
Test name
Test status
Simulation time 142828131 ps
CPU time 1.19 seconds
Started Jun 23 05:35:54 PM PDT 24
Finished Jun 23 05:35:55 PM PDT 24
Peak memory 218168 kb
Host smart-046d1726-d964-4904-b78a-4c5f2fd53a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037740808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1037740808
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.1649699124
Short name T883
Test name
Test status
Simulation time 36690563 ps
CPU time 1.08 seconds
Started Jun 23 05:36:09 PM PDT 24
Finished Jun 23 05:36:11 PM PDT 24
Peak memory 218068 kb
Host smart-d07fb40b-3d19-4c47-a8d9-92913f37efe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649699124 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.1649699124
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.2766015977
Short name T947
Test name
Test status
Simulation time 35456661 ps
CPU time 0.88 seconds
Started Jun 23 05:35:57 PM PDT 24
Finished Jun 23 05:35:58 PM PDT 24
Peak memory 218972 kb
Host smart-b65cf220-0a20-42d2-9aa6-164b43d08afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766015977 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2766015977
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.4229035438
Short name T383
Test name
Test status
Simulation time 64681366 ps
CPU time 1.1 seconds
Started Jun 23 05:36:08 PM PDT 24
Finished Jun 23 05:36:10 PM PDT 24
Peak memory 216552 kb
Host smart-a7b9202e-bc6f-4a1a-8bd9-1ca752a17d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229035438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.4229035438
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.3284850572
Short name T293
Test name
Test status
Simulation time 28592872 ps
CPU time 1.21 seconds
Started Jun 23 05:35:57 PM PDT 24
Finished Jun 23 05:35:59 PM PDT 24
Peak memory 219068 kb
Host smart-73c2aad3-70f9-4370-91e6-4b9e07412ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284850572 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.3284850572
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.2174779537
Short name T553
Test name
Test status
Simulation time 41814728 ps
CPU time 1.07 seconds
Started Jun 23 05:36:06 PM PDT 24
Finished Jun 23 05:36:08 PM PDT 24
Peak memory 219032 kb
Host smart-0e72558f-6da7-4989-8148-39f8c5bfdc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174779537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2174779537
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.231128442
Short name T910
Test name
Test status
Simulation time 50618537 ps
CPU time 1.81 seconds
Started Jun 23 05:35:58 PM PDT 24
Finished Jun 23 05:36:00 PM PDT 24
Peak memory 216888 kb
Host smart-577df69e-35f8-4092-b817-996180c9035d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231128442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.231128442
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.869381860
Short name T551
Test name
Test status
Simulation time 23212178 ps
CPU time 1.12 seconds
Started Jun 23 05:35:58 PM PDT 24
Finished Jun 23 05:36:00 PM PDT 24
Peak memory 219332 kb
Host smart-f296e5b0-7a20-43d5-bca8-c477281afed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869381860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.869381860
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1524862999
Short name T124
Test name
Test status
Simulation time 49521797 ps
CPU time 0.97 seconds
Started Jun 23 05:35:56 PM PDT 24
Finished Jun 23 05:35:58 PM PDT 24
Peak memory 219800 kb
Host smart-5a93d817-1a6e-4edc-a984-9a684e3f9781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524862999 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1524862999
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1921893641
Short name T591
Test name
Test status
Simulation time 101077294 ps
CPU time 1.59 seconds
Started Jun 23 05:36:07 PM PDT 24
Finished Jun 23 05:36:10 PM PDT 24
Peak memory 217760 kb
Host smart-6117215b-70a6-4746-abc8-ff79be01aa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921893641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1921893641
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.485292950
Short name T890
Test name
Test status
Simulation time 115065695 ps
CPU time 1.22 seconds
Started Jun 23 05:35:59 PM PDT 24
Finished Jun 23 05:36:00 PM PDT 24
Peak memory 219204 kb
Host smart-78fb8ba5-d62e-4e9c-9c4a-6df4343ea9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485292950 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.485292950
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.4020296904
Short name T200
Test name
Test status
Simulation time 22894684 ps
CPU time 1.19 seconds
Started Jun 23 05:36:07 PM PDT 24
Finished Jun 23 05:36:09 PM PDT 24
Peak memory 228900 kb
Host smart-517b2d99-dd3e-4123-ac7a-f95fc9702b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020296904 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.4020296904
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3485494792
Short name T305
Test name
Test status
Simulation time 119571304 ps
CPU time 1.51 seconds
Started Jun 23 05:35:56 PM PDT 24
Finished Jun 23 05:35:58 PM PDT 24
Peak memory 217948 kb
Host smart-e6bbc7da-836d-4bf2-8710-e39f1b39c871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485494792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3485494792
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.3064508155
Short name T489
Test name
Test status
Simulation time 107787652 ps
CPU time 1.23 seconds
Started Jun 23 05:36:07 PM PDT 24
Finished Jun 23 05:36:09 PM PDT 24
Peak memory 218316 kb
Host smart-e1bbb0fc-e2ad-44f5-a4df-a17deca09978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064508155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.3064508155
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2754541978
Short name T778
Test name
Test status
Simulation time 31254446 ps
CPU time 1.01 seconds
Started Jun 23 05:35:58 PM PDT 24
Finished Jun 23 05:35:59 PM PDT 24
Peak memory 217896 kb
Host smart-10f31d47-2014-494e-aa83-0c1445df3809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754541978 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2754541978
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1359346724
Short name T101
Test name
Test status
Simulation time 79316439 ps
CPU time 1.36 seconds
Started Jun 23 05:35:58 PM PDT 24
Finished Jun 23 05:36:00 PM PDT 24
Peak memory 218380 kb
Host smart-a92facc8-926c-4707-b75c-86284b7fbfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359346724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1359346724
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3526358914
Short name T358
Test name
Test status
Simulation time 77499868 ps
CPU time 1.18 seconds
Started Jun 23 05:34:06 PM PDT 24
Finished Jun 23 05:34:07 PM PDT 24
Peak memory 219280 kb
Host smart-919e03bc-e1ed-4c05-a420-f024ff3b2bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526358914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3526358914
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3130097726
Short name T678
Test name
Test status
Simulation time 25076485 ps
CPU time 0.92 seconds
Started Jun 23 05:34:03 PM PDT 24
Finished Jun 23 05:34:04 PM PDT 24
Peak memory 214316 kb
Host smart-8a32b63c-f751-4235-af1c-fe56db8a60ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130097726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3130097726
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1119408670
Short name T368
Test name
Test status
Simulation time 10678014 ps
CPU time 0.88 seconds
Started Jun 23 05:34:07 PM PDT 24
Finished Jun 23 05:34:09 PM PDT 24
Peak memory 215460 kb
Host smart-46317df0-eb95-48ab-a65c-8fb7c9c0ff91
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119408670 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1119408670
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1983808376
Short name T349
Test name
Test status
Simulation time 107701009 ps
CPU time 1.08 seconds
Started Jun 23 05:34:06 PM PDT 24
Finished Jun 23 05:34:07 PM PDT 24
Peak memory 216276 kb
Host smart-78f199af-a797-472e-993b-d69114518a7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983808376 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1983808376
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1740870171
Short name T209
Test name
Test status
Simulation time 35151199 ps
CPU time 0.94 seconds
Started Jun 23 05:34:06 PM PDT 24
Finished Jun 23 05:34:07 PM PDT 24
Peak memory 219332 kb
Host smart-078b6399-8a47-47e9-9b73-2c431ab01fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740870171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1740870171
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1675722316
Short name T309
Test name
Test status
Simulation time 195699666 ps
CPU time 1.89 seconds
Started Jun 23 05:34:05 PM PDT 24
Finished Jun 23 05:34:07 PM PDT 24
Peak memory 218016 kb
Host smart-16149656-36e9-4e7f-9a23-a90a3255d874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675722316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1675722316
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1635494222
Short name T103
Test name
Test status
Simulation time 26854371 ps
CPU time 0.98 seconds
Started Jun 23 05:34:08 PM PDT 24
Finished Jun 23 05:34:09 PM PDT 24
Peak memory 214988 kb
Host smart-aa9a15a1-d989-4e34-a526-d025b7d660b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635494222 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1635494222
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.9421604
Short name T26
Test name
Test status
Simulation time 19462434 ps
CPU time 1.04 seconds
Started Jun 23 05:34:08 PM PDT 24
Finished Jun 23 05:34:09 PM PDT 24
Peak memory 206432 kb
Host smart-603cff77-79e8-4b2b-a293-f5248444877c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9421604 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.9421604
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1035395519
Short name T661
Test name
Test status
Simulation time 38083192 ps
CPU time 0.91 seconds
Started Jun 23 05:34:01 PM PDT 24
Finished Jun 23 05:34:03 PM PDT 24
Peak memory 214592 kb
Host smart-5b7847a6-7873-41db-a2b6-b7f7cb170b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035395519 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1035395519
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.400062772
Short name T703
Test name
Test status
Simulation time 91313915 ps
CPU time 2.24 seconds
Started Jun 23 05:34:06 PM PDT 24
Finished Jun 23 05:34:08 PM PDT 24
Peak memory 216616 kb
Host smart-fae56bfc-9573-4c49-a90c-9386229532bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400062772 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.400062772
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.268513175
Short name T232
Test name
Test status
Simulation time 13005673939 ps
CPU time 290.31 seconds
Started Jun 23 05:34:08 PM PDT 24
Finished Jun 23 05:38:59 PM PDT 24
Peak memory 217992 kb
Host smart-1eef3857-4465-4686-be05-e92af20ffdca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268513175 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.268513175
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.2517048360
Short name T421
Test name
Test status
Simulation time 75622673 ps
CPU time 1.15 seconds
Started Jun 23 05:35:57 PM PDT 24
Finished Jun 23 05:35:59 PM PDT 24
Peak memory 219168 kb
Host smart-8554f130-3f66-492b-9c0b-5c6c3e56cc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517048360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.2517048360
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.2245961818
Short name T159
Test name
Test status
Simulation time 55258108 ps
CPU time 0.93 seconds
Started Jun 23 05:35:59 PM PDT 24
Finished Jun 23 05:36:00 PM PDT 24
Peak memory 218884 kb
Host smart-b7b255fb-9785-4ec1-8de1-8fc63f1219ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245961818 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2245961818
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1637884801
Short name T495
Test name
Test status
Simulation time 297594487 ps
CPU time 1.1 seconds
Started Jun 23 05:35:58 PM PDT 24
Finished Jun 23 05:36:00 PM PDT 24
Peak memory 216740 kb
Host smart-46be9751-814b-4e82-a4e8-9b8f2e239a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637884801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1637884801
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.1399743678
Short name T223
Test name
Test status
Simulation time 167183334 ps
CPU time 1.2 seconds
Started Jun 23 05:35:58 PM PDT 24
Finished Jun 23 05:36:00 PM PDT 24
Peak memory 218692 kb
Host smart-6b9e97b0-802e-42bd-9b62-21f0fee8e82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399743678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.1399743678
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.1897425222
Short name T112
Test name
Test status
Simulation time 22963563 ps
CPU time 0.94 seconds
Started Jun 23 05:35:57 PM PDT 24
Finished Jun 23 05:35:59 PM PDT 24
Peak memory 218092 kb
Host smart-84afb1e9-8458-478d-a3dd-b815cab251ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897425222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1897425222
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2764655124
Short name T114
Test name
Test status
Simulation time 54963967 ps
CPU time 1.21 seconds
Started Jun 23 05:35:59 PM PDT 24
Finished Jun 23 05:36:01 PM PDT 24
Peak memory 218032 kb
Host smart-c3ae7340-1ff0-4389-a254-b2274a0c86ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764655124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2764655124
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.6642033
Short name T646
Test name
Test status
Simulation time 27473255 ps
CPU time 1.29 seconds
Started Jun 23 05:36:09 PM PDT 24
Finished Jun 23 05:36:11 PM PDT 24
Peak memory 220504 kb
Host smart-3878284f-6efa-4edd-bb5e-a69e40545346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6642033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.6642033
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.694363613
Short name T212
Test name
Test status
Simulation time 20351446 ps
CPU time 1.23 seconds
Started Jun 23 05:35:57 PM PDT 24
Finished Jun 23 05:35:58 PM PDT 24
Peak memory 223400 kb
Host smart-39fc9c3a-89eb-4f8f-b66d-970dd8d81ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694363613 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.694363613
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1840854872
Short name T654
Test name
Test status
Simulation time 44883140 ps
CPU time 1.48 seconds
Started Jun 23 05:36:00 PM PDT 24
Finished Jun 23 05:36:02 PM PDT 24
Peak memory 217820 kb
Host smart-096ca6b9-c625-4bb6-b247-613323b552ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840854872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1840854872
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.3108969584
Short name T468
Test name
Test status
Simulation time 86639997 ps
CPU time 1.3 seconds
Started Jun 23 05:36:03 PM PDT 24
Finished Jun 23 05:36:05 PM PDT 24
Peak memory 217796 kb
Host smart-63c6c563-4fb7-40a4-9a29-51110c59f9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108969584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.3108969584
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.2754186630
Short name T131
Test name
Test status
Simulation time 28257799 ps
CPU time 1.24 seconds
Started Jun 23 05:36:02 PM PDT 24
Finished Jun 23 05:36:04 PM PDT 24
Peak memory 229036 kb
Host smart-655075c1-1824-47f1-9b20-ef1083ef9f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754186630 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2754186630
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3845136334
Short name T861
Test name
Test status
Simulation time 34942653 ps
CPU time 1.38 seconds
Started Jun 23 05:36:04 PM PDT 24
Finished Jun 23 05:36:06 PM PDT 24
Peak memory 217956 kb
Host smart-f3419d15-5c11-4e11-8e95-643481cb8f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845136334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3845136334
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.1989172840
Short name T149
Test name
Test status
Simulation time 27555352 ps
CPU time 1.25 seconds
Started Jun 23 05:36:01 PM PDT 24
Finished Jun 23 05:36:03 PM PDT 24
Peak memory 218004 kb
Host smart-e819d19b-4a8d-4ee8-b7e5-c2af971317b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989172840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.1989172840
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.141997138
Short name T831
Test name
Test status
Simulation time 32406629 ps
CPU time 0.93 seconds
Started Jun 23 05:36:00 PM PDT 24
Finished Jun 23 05:36:02 PM PDT 24
Peak memory 218056 kb
Host smart-02c598ef-a505-4721-ae58-8f12e3da4297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141997138 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.141997138
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.367345623
Short name T629
Test name
Test status
Simulation time 34972267 ps
CPU time 1.03 seconds
Started Jun 23 05:36:05 PM PDT 24
Finished Jun 23 05:36:07 PM PDT 24
Peak memory 219256 kb
Host smart-945748e4-f61a-4c7f-9b6c-cba90db72f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367345623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.367345623
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.4166826974
Short name T393
Test name
Test status
Simulation time 32084777 ps
CPU time 1.3 seconds
Started Jun 23 05:36:04 PM PDT 24
Finished Jun 23 05:36:06 PM PDT 24
Peak memory 218968 kb
Host smart-8df698dd-be8c-4542-9c3d-c79018779b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166826974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.4166826974
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.1636654379
Short name T218
Test name
Test status
Simulation time 20937456 ps
CPU time 1.02 seconds
Started Jun 23 05:36:05 PM PDT 24
Finished Jun 23 05:36:06 PM PDT 24
Peak memory 218128 kb
Host smart-d4d77083-1ddc-4c72-aa45-a0622f0963e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636654379 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1636654379
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2610767042
Short name T896
Test name
Test status
Simulation time 215259748 ps
CPU time 3.51 seconds
Started Jun 23 05:36:02 PM PDT 24
Finished Jun 23 05:36:06 PM PDT 24
Peak memory 219500 kb
Host smart-3591b2d1-9426-488b-a8b0-5b6cf5760a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610767042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2610767042
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.39505699
Short name T540
Test name
Test status
Simulation time 22931252 ps
CPU time 1.15 seconds
Started Jun 23 05:36:04 PM PDT 24
Finished Jun 23 05:36:06 PM PDT 24
Peak memory 218264 kb
Host smart-36f6c848-3fbd-41e0-898c-6b2d37b764e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39505699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.39505699
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.4276088892
Short name T197
Test name
Test status
Simulation time 23949240 ps
CPU time 1 seconds
Started Jun 23 05:36:03 PM PDT 24
Finished Jun 23 05:36:04 PM PDT 24
Peak memory 217872 kb
Host smart-50319eac-4ba0-4ab2-9364-530ba830cd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276088892 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.4276088892
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3239880670
Short name T302
Test name
Test status
Simulation time 137807974 ps
CPU time 1.1 seconds
Started Jun 23 05:36:04 PM PDT 24
Finished Jun 23 05:36:05 PM PDT 24
Peak memory 216608 kb
Host smart-8038301c-b50d-467f-8521-948cd988ab39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239880670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3239880670
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.79739431
Short name T378
Test name
Test status
Simulation time 139084647 ps
CPU time 1.25 seconds
Started Jun 23 05:36:03 PM PDT 24
Finished Jun 23 05:36:05 PM PDT 24
Peak memory 219608 kb
Host smart-72879b39-e5f1-4283-b342-87d0d1108fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79739431 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.79739431
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.3413338730
Short name T578
Test name
Test status
Simulation time 20997102 ps
CPU time 0.99 seconds
Started Jun 23 05:36:01 PM PDT 24
Finished Jun 23 05:36:03 PM PDT 24
Peak memory 218140 kb
Host smart-eea2b4e9-3492-4f0d-b220-e3f800e82d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413338730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3413338730
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.400573667
Short name T413
Test name
Test status
Simulation time 46050605 ps
CPU time 1.15 seconds
Started Jun 23 05:36:06 PM PDT 24
Finished Jun 23 05:36:07 PM PDT 24
Peak memory 219040 kb
Host smart-8fc82cdf-63bd-4f01-807d-78a9eacfb0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400573667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.400573667
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.4073345832
Short name T195
Test name
Test status
Simulation time 45555663 ps
CPU time 1.25 seconds
Started Jun 23 05:36:01 PM PDT 24
Finished Jun 23 05:36:03 PM PDT 24
Peak memory 218180 kb
Host smart-0b6eecf5-4337-4d9a-acfd-5c0559cbe64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073345832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.4073345832
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.2175499006
Short name T872
Test name
Test status
Simulation time 23332641 ps
CPU time 0.92 seconds
Started Jun 23 05:36:03 PM PDT 24
Finished Jun 23 05:36:05 PM PDT 24
Peak memory 217580 kb
Host smart-e2e6bbac-3575-4f10-8175-671236ef82a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175499006 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2175499006
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2855119758
Short name T655
Test name
Test status
Simulation time 293625152 ps
CPU time 1.62 seconds
Started Jun 23 05:36:05 PM PDT 24
Finished Jun 23 05:36:07 PM PDT 24
Peak memory 218088 kb
Host smart-0200aa3d-f750-4ad7-8063-45e84900c2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855119758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2855119758
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.43906257
Short name T82
Test name
Test status
Simulation time 49232689 ps
CPU time 1.09 seconds
Started Jun 23 05:36:01 PM PDT 24
Finished Jun 23 05:36:03 PM PDT 24
Peak memory 218192 kb
Host smart-d030eb78-7a60-43b9-838c-201ad4d59200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43906257 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.43906257
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.3257401868
Short name T60
Test name
Test status
Simulation time 36424884 ps
CPU time 0.99 seconds
Started Jun 23 05:36:04 PM PDT 24
Finished Jun 23 05:36:06 PM PDT 24
Peak memory 223240 kb
Host smart-dbe26a08-dc2d-46e9-818b-4214a53a4c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257401868 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3257401868
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.4275379175
Short name T334
Test name
Test status
Simulation time 51583933 ps
CPU time 1.76 seconds
Started Jun 23 05:36:03 PM PDT 24
Finished Jun 23 05:36:05 PM PDT 24
Peak memory 217956 kb
Host smart-92cfd6b1-24f1-422c-83f6-528bb711f9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275379175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.4275379175
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1692822675
Short name T53
Test name
Test status
Simulation time 31051697 ps
CPU time 1.32 seconds
Started Jun 23 05:34:05 PM PDT 24
Finished Jun 23 05:34:07 PM PDT 24
Peak memory 219140 kb
Host smart-8915aca2-0b41-4bd6-8d9a-286168cb5a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692822675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1692822675
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2013214011
Short name T964
Test name
Test status
Simulation time 21331021 ps
CPU time 1.04 seconds
Started Jun 23 05:34:06 PM PDT 24
Finished Jun 23 05:34:08 PM PDT 24
Peak memory 214408 kb
Host smart-a235998f-33ff-492d-aa34-b8c610ce47f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013214011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2013214011
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.975693449
Short name T863
Test name
Test status
Simulation time 31346725 ps
CPU time 0.89 seconds
Started Jun 23 05:34:07 PM PDT 24
Finished Jun 23 05:34:09 PM PDT 24
Peak memory 215332 kb
Host smart-ef393fb6-d654-45da-bf02-d53efe27fdd9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975693449 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.975693449
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1798022957
Short name T469
Test name
Test status
Simulation time 83755326 ps
CPU time 1.23 seconds
Started Jun 23 05:34:10 PM PDT 24
Finished Jun 23 05:34:11 PM PDT 24
Peak memory 217868 kb
Host smart-962e8870-8cbe-4086-92b0-0d0647a3b956
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798022957 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1798022957
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2017662044
Short name T110
Test name
Test status
Simulation time 21320029 ps
CPU time 0.97 seconds
Started Jun 23 05:34:05 PM PDT 24
Finished Jun 23 05:34:06 PM PDT 24
Peak memory 217588 kb
Host smart-e769d2ad-39f3-4df2-b53b-a8925f47260c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017662044 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2017662044
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.194223332
Short name T497
Test name
Test status
Simulation time 39904126 ps
CPU time 1.46 seconds
Started Jun 23 05:34:08 PM PDT 24
Finished Jun 23 05:34:10 PM PDT 24
Peak memory 217844 kb
Host smart-446e1916-4c2e-40c4-8587-864786081281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194223332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.194223332
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3968535527
Short name T806
Test name
Test status
Simulation time 22466089 ps
CPU time 1.16 seconds
Started Jun 23 05:34:07 PM PDT 24
Finished Jun 23 05:34:09 PM PDT 24
Peak memory 214916 kb
Host smart-b712091f-7f54-4468-bc70-c07d85d7876a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968535527 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3968535527
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_smoke.1288032195
Short name T71
Test name
Test status
Simulation time 80159642 ps
CPU time 0.97 seconds
Started Jun 23 05:34:04 PM PDT 24
Finished Jun 23 05:34:05 PM PDT 24
Peak memory 214656 kb
Host smart-b92a671c-4abb-44ce-9464-cb04ec6aa3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288032195 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1288032195
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.586852195
Short name T448
Test name
Test status
Simulation time 250065960 ps
CPU time 3.11 seconds
Started Jun 23 05:34:06 PM PDT 24
Finished Jun 23 05:34:09 PM PDT 24
Peak memory 219628 kb
Host smart-d7af60d7-8c55-43ec-8b51-729cd8e330b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586852195 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.586852195
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3676542082
Short name T303
Test name
Test status
Simulation time 60072358148 ps
CPU time 961.83 seconds
Started Jun 23 05:34:04 PM PDT 24
Finished Jun 23 05:50:07 PM PDT 24
Peak memory 223016 kb
Host smart-b100e39b-3596-4f64-bc17-a89fcbe58f7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676542082 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3676542082
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.2684981071
Short name T252
Test name
Test status
Simulation time 80539243 ps
CPU time 1.3 seconds
Started Jun 23 05:36:02 PM PDT 24
Finished Jun 23 05:36:03 PM PDT 24
Peak memory 220152 kb
Host smart-0df56da9-02d5-4e2a-a672-5638018275c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684981071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2684981071
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.2369335870
Short name T921
Test name
Test status
Simulation time 28662370 ps
CPU time 0.88 seconds
Started Jun 23 05:36:06 PM PDT 24
Finished Jun 23 05:36:07 PM PDT 24
Peak memory 217720 kb
Host smart-a2a20721-c003-4a1d-a67a-a42ec0bfa8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369335870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2369335870
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3616878280
Short name T932
Test name
Test status
Simulation time 108474465 ps
CPU time 1.29 seconds
Started Jun 23 05:36:02 PM PDT 24
Finished Jun 23 05:36:04 PM PDT 24
Peak memory 216656 kb
Host smart-18fa315f-b016-42a6-bbc8-a80ee93c52cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616878280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3616878280
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.186223318
Short name T80
Test name
Test status
Simulation time 28153828 ps
CPU time 1.21 seconds
Started Jun 23 05:36:05 PM PDT 24
Finished Jun 23 05:36:06 PM PDT 24
Peak memory 217876 kb
Host smart-249a41cd-b336-4fe4-89f2-fd1298532764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186223318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.186223318
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.4056779112
Short name T61
Test name
Test status
Simulation time 69102421 ps
CPU time 1.11 seconds
Started Jun 23 05:36:04 PM PDT 24
Finished Jun 23 05:36:05 PM PDT 24
Peak memory 223380 kb
Host smart-0851906e-c508-4195-9df3-bd17083146db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056779112 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.4056779112
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1706821748
Short name T620
Test name
Test status
Simulation time 38302157 ps
CPU time 1.34 seconds
Started Jun 23 05:36:05 PM PDT 24
Finished Jun 23 05:36:07 PM PDT 24
Peak memory 217644 kb
Host smart-909ec077-87a0-4d1f-930c-2a56eee16b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706821748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1706821748
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.3362143002
Short name T284
Test name
Test status
Simulation time 26649583 ps
CPU time 1.29 seconds
Started Jun 23 05:36:02 PM PDT 24
Finished Jun 23 05:36:04 PM PDT 24
Peak memory 217992 kb
Host smart-c908e543-08b8-4238-bbf7-6224b01a0c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362143002 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.3362143002
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.3260154892
Short name T753
Test name
Test status
Simulation time 33721694 ps
CPU time 0.88 seconds
Started Jun 23 05:36:01 PM PDT 24
Finished Jun 23 05:36:02 PM PDT 24
Peak memory 218832 kb
Host smart-1bed7288-23dd-435e-a409-e6021c13e641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260154892 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3260154892
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1486472020
Short name T884
Test name
Test status
Simulation time 58340077 ps
CPU time 0.98 seconds
Started Jun 23 05:36:04 PM PDT 24
Finished Jun 23 05:36:06 PM PDT 24
Peak memory 216732 kb
Host smart-b796b46b-debd-4117-93dd-68aa7a6dd3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486472020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1486472020
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.1702643912
Short name T897
Test name
Test status
Simulation time 77878487 ps
CPU time 1.12 seconds
Started Jun 23 05:36:05 PM PDT 24
Finished Jun 23 05:36:06 PM PDT 24
Peak memory 218632 kb
Host smart-cc8e3de1-53ce-4424-ad64-56a3b5301ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702643912 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.1702643912
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.2762611691
Short name T742
Test name
Test status
Simulation time 19241491 ps
CPU time 1.03 seconds
Started Jun 23 05:36:04 PM PDT 24
Finished Jun 23 05:36:05 PM PDT 24
Peak memory 217856 kb
Host smart-600e2778-ebb3-42fa-a160-edeb32f66117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762611691 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2762611691
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3132605913
Short name T975
Test name
Test status
Simulation time 28549398 ps
CPU time 1.26 seconds
Started Jun 23 05:35:59 PM PDT 24
Finished Jun 23 05:36:01 PM PDT 24
Peak memory 217040 kb
Host smart-0fcb9687-aa00-4ca3-9c74-f453a2ffe0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132605913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3132605913
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.2273753781
Short name T251
Test name
Test status
Simulation time 29340541 ps
CPU time 1.35 seconds
Started Jun 23 05:36:07 PM PDT 24
Finished Jun 23 05:36:10 PM PDT 24
Peak memory 219712 kb
Host smart-2d8eb799-09bb-41c5-b26b-5a1066596543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273753781 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2273753781
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.1993951457
Short name T79
Test name
Test status
Simulation time 18184286 ps
CPU time 1.06 seconds
Started Jun 23 05:36:06 PM PDT 24
Finished Jun 23 05:36:08 PM PDT 24
Peak memory 217644 kb
Host smart-1448ba42-ff2a-4e50-b797-be28b2363347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993951457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1993951457
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2450278609
Short name T613
Test name
Test status
Simulation time 40742286 ps
CPU time 1.46 seconds
Started Jun 23 05:36:06 PM PDT 24
Finished Jun 23 05:36:09 PM PDT 24
Peak memory 219156 kb
Host smart-429783dc-a7af-4ead-906a-6b6f6051a957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450278609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2450278609
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.9869956
Short name T298
Test name
Test status
Simulation time 79156211 ps
CPU time 1.21 seconds
Started Jun 23 05:36:10 PM PDT 24
Finished Jun 23 05:36:11 PM PDT 24
Peak memory 215044 kb
Host smart-deae9ceb-113f-43fd-8b9d-0eddc21fbeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9869956 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.9869956
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.939443806
Short name T6
Test name
Test status
Simulation time 24617719 ps
CPU time 0.99 seconds
Started Jun 23 05:36:07 PM PDT 24
Finished Jun 23 05:36:09 PM PDT 24
Peak memory 219088 kb
Host smart-84ceb15e-3c2c-4d47-a88b-dc0a22b624a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939443806 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.939443806
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3564323501
Short name T322
Test name
Test status
Simulation time 41703490 ps
CPU time 1.15 seconds
Started Jun 23 05:36:07 PM PDT 24
Finished Jun 23 05:36:09 PM PDT 24
Peak memory 216740 kb
Host smart-cfe07d02-9915-4462-81bd-97254809b5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564323501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3564323501
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.3885594570
Short name T783
Test name
Test status
Simulation time 80062229 ps
CPU time 1.15 seconds
Started Jun 23 05:36:06 PM PDT 24
Finished Jun 23 05:36:07 PM PDT 24
Peak memory 218420 kb
Host smart-3ee447a8-6ee9-4289-ac67-9896516abeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885594570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.3885594570
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.3404382531
Short name T171
Test name
Test status
Simulation time 117732482 ps
CPU time 1.17 seconds
Started Jun 23 05:36:06 PM PDT 24
Finished Jun 23 05:36:08 PM PDT 24
Peak memory 225032 kb
Host smart-6a58d6d4-3540-43b0-8907-0b51d43eff06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404382531 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3404382531
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2010979435
Short name T21
Test name
Test status
Simulation time 38607634 ps
CPU time 1.51 seconds
Started Jun 23 05:36:08 PM PDT 24
Finished Jun 23 05:36:10 PM PDT 24
Peak memory 214748 kb
Host smart-98ad4e66-43b9-4b28-a76a-1ca5daa64388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010979435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2010979435
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.3756624460
Short name T580
Test name
Test status
Simulation time 24169987 ps
CPU time 1.19 seconds
Started Jun 23 05:36:06 PM PDT 24
Finished Jun 23 05:36:08 PM PDT 24
Peak memory 219948 kb
Host smart-a081162a-bd15-4a70-b3fd-68d45a586531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756624460 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.3756624460
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.157647424
Short name T656
Test name
Test status
Simulation time 21416673 ps
CPU time 1.13 seconds
Started Jun 23 05:36:07 PM PDT 24
Finished Jun 23 05:36:09 PM PDT 24
Peak memory 218884 kb
Host smart-fa67fac8-a2ab-4076-a9b3-85c7070fef0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157647424 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.157647424
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.1157317029
Short name T45
Test name
Test status
Simulation time 75830800 ps
CPU time 1.56 seconds
Started Jun 23 05:36:07 PM PDT 24
Finished Jun 23 05:36:09 PM PDT 24
Peak memory 216852 kb
Host smart-58841da3-c2c3-422b-8ff4-cade3d0ba49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157317029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1157317029
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.2313867910
Short name T513
Test name
Test status
Simulation time 108373902 ps
CPU time 1.25 seconds
Started Jun 23 05:36:07 PM PDT 24
Finished Jun 23 05:36:09 PM PDT 24
Peak memory 220100 kb
Host smart-02c712d6-faf0-40a9-b0ad-88bd91f620b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313867910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.2313867910
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.936331095
Short name T205
Test name
Test status
Simulation time 33127172 ps
CPU time 0.9 seconds
Started Jun 23 05:36:07 PM PDT 24
Finished Jun 23 05:36:08 PM PDT 24
Peak memory 217800 kb
Host smart-2f44b4b9-893d-4724-b062-1695ba2e146b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936331095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.936331095
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.609069613
Short name T769
Test name
Test status
Simulation time 213557479 ps
CPU time 1.52 seconds
Started Jun 23 05:36:06 PM PDT 24
Finished Jun 23 05:36:09 PM PDT 24
Peak memory 218164 kb
Host smart-625908e4-6096-433b-a54f-a9ce2cda7b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609069613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.609069613
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.3988584347
Short name T227
Test name
Test status
Simulation time 137006095 ps
CPU time 1.18 seconds
Started Jun 23 05:36:06 PM PDT 24
Finished Jun 23 05:36:08 PM PDT 24
Peak memory 218928 kb
Host smart-0472c09a-539e-4c70-abb3-1d8879716585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988584347 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.3988584347
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.4146615718
Short name T142
Test name
Test status
Simulation time 25500166 ps
CPU time 1.27 seconds
Started Jun 23 05:36:06 PM PDT 24
Finished Jun 23 05:36:08 PM PDT 24
Peak memory 229060 kb
Host smart-d047c6d1-d0be-4a01-a5a9-2c4582ea458c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146615718 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.4146615718
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.4115946602
Short name T285
Test name
Test status
Simulation time 84065563 ps
CPU time 1.19 seconds
Started Jun 23 05:36:06 PM PDT 24
Finished Jun 23 05:36:08 PM PDT 24
Peak memory 216632 kb
Host smart-5e0ea68c-0a55-4d6d-b878-49471e2ddb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115946602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.4115946602
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3795633092
Short name T99
Test name
Test status
Simulation time 51070560 ps
CPU time 1.43 seconds
Started Jun 23 05:34:11 PM PDT 24
Finished Jun 23 05:34:12 PM PDT 24
Peak memory 215104 kb
Host smart-76a0edb6-b1f7-471a-b581-86d801892278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795633092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3795633092
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.131096239
Short name T531
Test name
Test status
Simulation time 40056332 ps
CPU time 0.86 seconds
Started Jun 23 05:34:09 PM PDT 24
Finished Jun 23 05:34:11 PM PDT 24
Peak memory 205924 kb
Host smart-8a11c18f-9b92-40b6-a207-9073f68daf56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131096239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.131096239
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1868947062
Short name T843
Test name
Test status
Simulation time 11213488 ps
CPU time 0.92 seconds
Started Jun 23 05:34:09 PM PDT 24
Finished Jun 23 05:34:10 PM PDT 24
Peak memory 215668 kb
Host smart-63870e72-1dc7-41f2-9cf9-96a794be88c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868947062 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1868947062
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1146066682
Short name T367
Test name
Test status
Simulation time 234304880 ps
CPU time 1.01 seconds
Started Jun 23 05:34:11 PM PDT 24
Finished Jun 23 05:34:13 PM PDT 24
Peak memory 217564 kb
Host smart-779645cf-3dbf-4ca1-97a9-9cb15305f1bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146066682 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1146066682
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.2175135865
Short name T216
Test name
Test status
Simulation time 25955484 ps
CPU time 0.96 seconds
Started Jun 23 05:34:09 PM PDT 24
Finished Jun 23 05:34:11 PM PDT 24
Peak memory 219276 kb
Host smart-73e8868a-a342-4839-9b6a-c7cfee0676b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175135865 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2175135865
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.4077854778
Short name T475
Test name
Test status
Simulation time 38474174 ps
CPU time 1.6 seconds
Started Jun 23 05:34:09 PM PDT 24
Finished Jun 23 05:34:12 PM PDT 24
Peak memory 216632 kb
Host smart-a3392406-27d3-4274-963b-55c2623b1875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077854778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.4077854778
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1508066956
Short name T929
Test name
Test status
Simulation time 27518472 ps
CPU time 1.03 seconds
Started Jun 23 05:34:07 PM PDT 24
Finished Jun 23 05:34:09 PM PDT 24
Peak memory 223248 kb
Host smart-40049f1b-1bdf-4985-bb6b-689c967e0085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508066956 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1508066956
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2308377800
Short name T295
Test name
Test status
Simulation time 41179518 ps
CPU time 0.87 seconds
Started Jun 23 05:34:06 PM PDT 24
Finished Jun 23 05:34:07 PM PDT 24
Peak memory 206432 kb
Host smart-39dd9551-0da2-4ea2-a2b7-a4d14f6ea571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308377800 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2308377800
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2894308816
Short name T405
Test name
Test status
Simulation time 15937513 ps
CPU time 0.97 seconds
Started Jun 23 05:34:07 PM PDT 24
Finished Jun 23 05:34:08 PM PDT 24
Peak memory 214656 kb
Host smart-12280479-c8c6-4669-8c46-bc864346bd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894308816 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2894308816
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2710672536
Short name T318
Test name
Test status
Simulation time 114853530 ps
CPU time 2.66 seconds
Started Jun 23 05:34:07 PM PDT 24
Finished Jun 23 05:34:11 PM PDT 24
Peak memory 219052 kb
Host smart-8d37d1a5-b2ac-4dfe-b0b0-76bc25abc3b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710672536 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2710672536
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.420842117
Short name T237
Test name
Test status
Simulation time 44889236195 ps
CPU time 1036.87 seconds
Started Jun 23 05:34:07 PM PDT 24
Finished Jun 23 05:51:25 PM PDT 24
Peak memory 218756 kb
Host smart-75c171d6-d2ff-4213-b202-fdef9b052a46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420842117 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.420842117
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.477107644
Short name T436
Test name
Test status
Simulation time 24728578 ps
CPU time 1.31 seconds
Started Jun 23 05:36:13 PM PDT 24
Finished Jun 23 05:36:14 PM PDT 24
Peak memory 218800 kb
Host smart-82d90f64-a12b-4aa7-83c4-39b7d14bdef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477107644 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.477107644
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.680496151
Short name T751
Test name
Test status
Simulation time 36429086 ps
CPU time 0.84 seconds
Started Jun 23 05:36:13 PM PDT 24
Finished Jun 23 05:36:14 PM PDT 24
Peak memory 217652 kb
Host smart-dfe7de8e-b05a-4a23-9d61-cc095e7d3f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680496151 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.680496151
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3223793779
Short name T371
Test name
Test status
Simulation time 30348283 ps
CPU time 1.3 seconds
Started Jun 23 05:36:12 PM PDT 24
Finished Jun 23 05:36:14 PM PDT 24
Peak memory 217820 kb
Host smart-26ce4239-7409-4a1a-9592-ab27b98b9d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223793779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3223793779
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.2547102093
Short name T865
Test name
Test status
Simulation time 77898370 ps
CPU time 1.11 seconds
Started Jun 23 05:36:13 PM PDT 24
Finished Jun 23 05:36:14 PM PDT 24
Peak memory 220120 kb
Host smart-a139fa64-360f-409e-ae61-2c209dfc5438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547102093 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.2547102093
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.1726491023
Short name T575
Test name
Test status
Simulation time 32057049 ps
CPU time 0.99 seconds
Started Jun 23 05:36:13 PM PDT 24
Finished Jun 23 05:36:14 PM PDT 24
Peak memory 223240 kb
Host smart-2831b555-516f-441a-8504-d11b98b88981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726491023 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1726491023
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3039987341
Short name T814
Test name
Test status
Simulation time 104966590 ps
CPU time 2.32 seconds
Started Jun 23 05:36:11 PM PDT 24
Finished Jun 23 05:36:13 PM PDT 24
Peak memory 214612 kb
Host smart-5c7e1977-a07c-451a-9eb1-998b530e2c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039987341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3039987341
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.3396394178
Short name T623
Test name
Test status
Simulation time 28039803 ps
CPU time 1.24 seconds
Started Jun 23 05:36:12 PM PDT 24
Finished Jun 23 05:36:13 PM PDT 24
Peak memory 218232 kb
Host smart-e1709afb-831d-4559-9faa-c8ef4e846833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396394178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.3396394178
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.2559102748
Short name T57
Test name
Test status
Simulation time 23023918 ps
CPU time 0.99 seconds
Started Jun 23 05:36:11 PM PDT 24
Finished Jun 23 05:36:13 PM PDT 24
Peak memory 223400 kb
Host smart-5df7df16-3108-4374-ac69-dc2841d8c036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559102748 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2559102748
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3009977498
Short name T804
Test name
Test status
Simulation time 66443406 ps
CPU time 1.58 seconds
Started Jun 23 05:36:12 PM PDT 24
Finished Jun 23 05:36:14 PM PDT 24
Peak memory 216856 kb
Host smart-f718a1ef-1f33-400d-858f-a71c2704ac34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009977498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3009977498
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.1624724887
Short name T187
Test name
Test status
Simulation time 91392249 ps
CPU time 1.27 seconds
Started Jun 23 05:36:13 PM PDT 24
Finished Jun 23 05:36:14 PM PDT 24
Peak memory 219224 kb
Host smart-2bb0d6c6-3ff0-4f5e-a83b-51fc2b6fdd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624724887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.1624724887
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.890279021
Short name T132
Test name
Test status
Simulation time 26533677 ps
CPU time 0.99 seconds
Started Jun 23 05:36:16 PM PDT 24
Finished Jun 23 05:36:18 PM PDT 24
Peak memory 218944 kb
Host smart-cb0f21db-1cc5-4a97-816d-cab532e7509d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890279021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.890279021
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/94.edn_alert.297885879
Short name T188
Test name
Test status
Simulation time 193005764 ps
CPU time 1.04 seconds
Started Jun 23 05:36:15 PM PDT 24
Finished Jun 23 05:36:16 PM PDT 24
Peak memory 218936 kb
Host smart-ba5a3ac5-cf69-4d96-afa3-226098ec7140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297885879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.297885879
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.2443237522
Short name T737
Test name
Test status
Simulation time 35315481 ps
CPU time 1.08 seconds
Started Jun 23 05:36:16 PM PDT 24
Finished Jun 23 05:36:17 PM PDT 24
Peak memory 220096 kb
Host smart-a08aaf32-11c5-449b-9d87-276c83e834bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443237522 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2443237522
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2656901971
Short name T525
Test name
Test status
Simulation time 44061915 ps
CPU time 1.11 seconds
Started Jun 23 05:36:14 PM PDT 24
Finished Jun 23 05:36:16 PM PDT 24
Peak memory 216692 kb
Host smart-e41149e6-dec5-4cb9-967e-0b506eb684e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656901971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2656901971
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.414639359
Short name T506
Test name
Test status
Simulation time 24856968 ps
CPU time 1.17 seconds
Started Jun 23 05:36:19 PM PDT 24
Finished Jun 23 05:36:22 PM PDT 24
Peak memory 218012 kb
Host smart-b9fde7b6-825c-4731-ace1-f35fcfe4f721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414639359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.414639359
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.3998967686
Short name T411
Test name
Test status
Simulation time 39525002 ps
CPU time 0.83 seconds
Started Jun 23 05:36:16 PM PDT 24
Finished Jun 23 05:36:17 PM PDT 24
Peak memory 217612 kb
Host smart-7090e869-b8be-4fa6-852e-53d43e973014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998967686 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3998967686
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.438034218
Short name T874
Test name
Test status
Simulation time 219766052 ps
CPU time 1.41 seconds
Started Jun 23 05:36:19 PM PDT 24
Finished Jun 23 05:36:22 PM PDT 24
Peak memory 219572 kb
Host smart-6e2a7dd4-e05b-4b2d-b53f-452dbee56d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438034218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.438034218
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.627162744
Short name T555
Test name
Test status
Simulation time 57075536 ps
CPU time 1.28 seconds
Started Jun 23 05:36:21 PM PDT 24
Finished Jun 23 05:36:24 PM PDT 24
Peak memory 215084 kb
Host smart-b528274e-1804-49b3-8e2d-333f98169d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627162744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.627162744
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.1147882065
Short name T213
Test name
Test status
Simulation time 42102494 ps
CPU time 0.89 seconds
Started Jun 23 05:36:17 PM PDT 24
Finished Jun 23 05:36:18 PM PDT 24
Peak memory 218160 kb
Host smart-82678e08-3b5a-4e3e-9193-6271e48a3148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147882065 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1147882065
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.491328179
Short name T486
Test name
Test status
Simulation time 153661427 ps
CPU time 1.47 seconds
Started Jun 23 05:36:15 PM PDT 24
Finished Jun 23 05:36:18 PM PDT 24
Peak memory 219516 kb
Host smart-63548536-077c-4b3c-812c-0f2912f7d0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491328179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.491328179
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.2539163401
Short name T449
Test name
Test status
Simulation time 25993674 ps
CPU time 1.2 seconds
Started Jun 23 05:36:19 PM PDT 24
Finished Jun 23 05:36:22 PM PDT 24
Peak memory 219020 kb
Host smart-7409bb05-f003-44c6-8e1d-1a82d2c24d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539163401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.2539163401
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.907369651
Short name T59
Test name
Test status
Simulation time 21202614 ps
CPU time 1.03 seconds
Started Jun 23 05:36:16 PM PDT 24
Finished Jun 23 05:36:17 PM PDT 24
Peak memory 223320 kb
Host smart-08ceda9a-eaf1-4d0b-a3c7-7beb48618bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907369651 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.907369651
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3056820140
Short name T907
Test name
Test status
Simulation time 95542648 ps
CPU time 2.17 seconds
Started Jun 23 05:36:14 PM PDT 24
Finished Jun 23 05:36:17 PM PDT 24
Peak memory 217028 kb
Host smart-3b9de128-0492-4738-adb5-b46454307092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056820140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3056820140
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.121675917
Short name T526
Test name
Test status
Simulation time 28125583 ps
CPU time 1.22 seconds
Started Jun 23 05:36:19 PM PDT 24
Finished Jun 23 05:36:21 PM PDT 24
Peak memory 215104 kb
Host smart-e0e5cc0d-8ad0-4765-a364-e36adc5001d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121675917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.121675917
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.1119021319
Short name T7
Test name
Test status
Simulation time 24814386 ps
CPU time 1.19 seconds
Started Jun 23 05:36:18 PM PDT 24
Finished Jun 23 05:36:20 PM PDT 24
Peak memory 218012 kb
Host smart-7bad82ab-2782-4bea-8015-e81f2cbbbf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119021319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1119021319
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2481149622
Short name T414
Test name
Test status
Simulation time 1047841175 ps
CPU time 8.34 seconds
Started Jun 23 05:36:16 PM PDT 24
Finished Jun 23 05:36:25 PM PDT 24
Peak memory 219524 kb
Host smart-48fc0347-459b-4051-8fba-f95dc85ed437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481149622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2481149622
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.2629697829
Short name T940
Test name
Test status
Simulation time 36785459 ps
CPU time 1.17 seconds
Started Jun 23 05:36:16 PM PDT 24
Finished Jun 23 05:36:17 PM PDT 24
Peak memory 218392 kb
Host smart-e76c83c2-0966-4ef0-8e1e-910c1df3b957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629697829 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.2629697829
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.3512497749
Short name T662
Test name
Test status
Simulation time 32243563 ps
CPU time 1.03 seconds
Started Jun 23 05:36:20 PM PDT 24
Finished Jun 23 05:36:23 PM PDT 24
Peak memory 223396 kb
Host smart-e6a1a0ad-8345-4506-8ad6-318fe457c7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512497749 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3512497749
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.184272398
Short name T748
Test name
Test status
Simulation time 163271426 ps
CPU time 1.36 seconds
Started Jun 23 05:36:20 PM PDT 24
Finished Jun 23 05:36:22 PM PDT 24
Peak memory 219572 kb
Host smart-6369ae13-91a2-4fdf-a596-0f3efed1b01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184272398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.184272398
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%