Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.60 98.25 93.67 97.02 91.86 96.37 99.77 92.28


Total test records in report: 1128
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1018 /workspace/coverage/cover_reg_top/44.edn_intr_test.1447720144 Jun 25 05:45:49 PM PDT 24 Jun 25 05:45:51 PM PDT 24 98109059 ps
T1019 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.4078879298 Jun 25 05:45:33 PM PDT 24 Jun 25 05:45:36 PM PDT 24 39910418 ps
T284 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2015557729 Jun 25 05:44:53 PM PDT 24 Jun 25 05:44:55 PM PDT 24 66575944 ps
T270 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2403192778 Jun 25 05:45:28 PM PDT 24 Jun 25 05:45:30 PM PDT 24 73646227 ps
T1020 /workspace/coverage/cover_reg_top/1.edn_csr_rw.1253351466 Jun 25 05:44:39 PM PDT 24 Jun 25 05:44:40 PM PDT 24 46357812 ps
T1021 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.351915052 Jun 25 05:44:39 PM PDT 24 Jun 25 05:44:41 PM PDT 24 76085174 ps
T1022 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1931580219 Jun 25 05:45:16 PM PDT 24 Jun 25 05:45:18 PM PDT 24 22429972 ps
T271 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3555224984 Jun 25 05:44:37 PM PDT 24 Jun 25 05:44:39 PM PDT 24 29410125 ps
T1023 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3407564914 Jun 25 05:44:55 PM PDT 24 Jun 25 05:44:58 PM PDT 24 50389426 ps
T1024 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1288436074 Jun 25 05:44:47 PM PDT 24 Jun 25 05:44:49 PM PDT 24 50331324 ps
T272 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3244975160 Jun 25 05:44:39 PM PDT 24 Jun 25 05:44:41 PM PDT 24 17712997 ps
T1025 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2507550961 Jun 25 05:45:24 PM PDT 24 Jun 25 05:45:26 PM PDT 24 120880117 ps
T1026 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2461524350 Jun 25 05:45:17 PM PDT 24 Jun 25 05:45:20 PM PDT 24 18484333 ps
T1027 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1060623548 Jun 25 05:44:48 PM PDT 24 Jun 25 05:44:49 PM PDT 24 40097624 ps
T1028 /workspace/coverage/cover_reg_top/3.edn_csr_rw.4138394416 Jun 25 05:44:45 PM PDT 24 Jun 25 05:44:47 PM PDT 24 37763439 ps
T1029 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3356447668 Jun 25 05:45:25 PM PDT 24 Jun 25 05:45:30 PM PDT 24 104679345 ps
T1030 /workspace/coverage/cover_reg_top/10.edn_intr_test.3220797989 Jun 25 05:45:18 PM PDT 24 Jun 25 05:45:20 PM PDT 24 56378349 ps
T1031 /workspace/coverage/cover_reg_top/28.edn_intr_test.4221331577 Jun 25 05:45:44 PM PDT 24 Jun 25 05:45:46 PM PDT 24 16035682 ps
T307 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.4161914942 Jun 25 05:44:45 PM PDT 24 Jun 25 05:44:47 PM PDT 24 54379773 ps
T1032 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3046597377 Jun 25 05:44:54 PM PDT 24 Jun 25 05:44:56 PM PDT 24 88635425 ps
T303 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1662504936 Jun 25 05:45:20 PM PDT 24 Jun 25 05:45:23 PM PDT 24 245988992 ps
T1033 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2743418582 Jun 25 05:45:17 PM PDT 24 Jun 25 05:45:19 PM PDT 24 27956072 ps
T1034 /workspace/coverage/cover_reg_top/2.edn_tl_errors.304347322 Jun 25 05:44:38 PM PDT 24 Jun 25 05:44:41 PM PDT 24 28432336 ps
T1035 /workspace/coverage/cover_reg_top/40.edn_intr_test.1094761338 Jun 25 05:45:45 PM PDT 24 Jun 25 05:45:47 PM PDT 24 13068638 ps
T1036 /workspace/coverage/cover_reg_top/35.edn_intr_test.1495985016 Jun 25 05:45:42 PM PDT 24 Jun 25 05:45:44 PM PDT 24 14387814 ps
T273 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3088562268 Jun 25 05:44:52 PM PDT 24 Jun 25 05:44:54 PM PDT 24 78367245 ps
T1037 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3057245610 Jun 25 05:45:17 PM PDT 24 Jun 25 05:45:20 PM PDT 24 35177478 ps
T1038 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3583498230 Jun 25 05:45:18 PM PDT 24 Jun 25 05:45:22 PM PDT 24 89834551 ps
T285 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2625732958 Jun 25 05:45:35 PM PDT 24 Jun 25 05:45:37 PM PDT 24 52751602 ps
T1039 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2778561288 Jun 25 05:44:47 PM PDT 24 Jun 25 05:44:49 PM PDT 24 30181927 ps
T1040 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2550890839 Jun 25 05:45:19 PM PDT 24 Jun 25 05:45:22 PM PDT 24 281364147 ps
T1041 /workspace/coverage/cover_reg_top/34.edn_intr_test.1841696975 Jun 25 05:45:45 PM PDT 24 Jun 25 05:45:47 PM PDT 24 35245859 ps
T1042 /workspace/coverage/cover_reg_top/9.edn_intr_test.4098892980 Jun 25 05:45:18 PM PDT 24 Jun 25 05:45:20 PM PDT 24 34179106 ps
T1043 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3692919330 Jun 25 05:44:38 PM PDT 24 Jun 25 05:44:42 PM PDT 24 345005224 ps
T286 /workspace/coverage/cover_reg_top/4.edn_csr_rw.402137893 Jun 25 05:44:53 PM PDT 24 Jun 25 05:44:54 PM PDT 24 30741445 ps
T1044 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1564413879 Jun 25 05:45:25 PM PDT 24 Jun 25 05:45:28 PM PDT 24 27335800 ps
T1045 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3429688342 Jun 25 05:44:29 PM PDT 24 Jun 25 05:44:31 PM PDT 24 75942965 ps
T1046 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2555582046 Jun 25 05:45:02 PM PDT 24 Jun 25 05:45:03 PM PDT 24 14745942 ps
T279 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1431211161 Jun 25 05:44:39 PM PDT 24 Jun 25 05:44:43 PM PDT 24 457941629 ps
T1047 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3053116002 Jun 25 05:44:29 PM PDT 24 Jun 25 05:44:30 PM PDT 24 12433346 ps
T1048 /workspace/coverage/cover_reg_top/15.edn_csr_rw.761887711 Jun 25 05:45:25 PM PDT 24 Jun 25 05:45:27 PM PDT 24 14854222 ps
T1049 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1028627361 Jun 25 05:45:27 PM PDT 24 Jun 25 05:45:29 PM PDT 24 62853970 ps
T1050 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2089676965 Jun 25 05:44:37 PM PDT 24 Jun 25 05:44:40 PM PDT 24 170403742 ps
T1051 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3514134154 Jun 25 05:45:01 PM PDT 24 Jun 25 05:45:03 PM PDT 24 356235303 ps
T1052 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1011142079 Jun 25 05:45:17 PM PDT 24 Jun 25 05:45:19 PM PDT 24 23873167 ps
T1053 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3992805567 Jun 25 05:45:34 PM PDT 24 Jun 25 05:45:37 PM PDT 24 24102645 ps
T1054 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2081895230 Jun 25 05:45:16 PM PDT 24 Jun 25 05:45:18 PM PDT 24 71151192 ps
T1055 /workspace/coverage/cover_reg_top/42.edn_intr_test.3246277989 Jun 25 05:45:46 PM PDT 24 Jun 25 05:45:48 PM PDT 24 70506370 ps
T1056 /workspace/coverage/cover_reg_top/27.edn_intr_test.3534613851 Jun 25 05:45:43 PM PDT 24 Jun 25 05:45:44 PM PDT 24 43579578 ps
T1057 /workspace/coverage/cover_reg_top/15.edn_intr_test.1733971528 Jun 25 05:45:26 PM PDT 24 Jun 25 05:45:29 PM PDT 24 14317776 ps
T1058 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2044661592 Jun 25 05:45:19 PM PDT 24 Jun 25 05:45:21 PM PDT 24 207647823 ps
T1059 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3840306806 Jun 25 05:45:25 PM PDT 24 Jun 25 05:45:28 PM PDT 24 33971691 ps
T1060 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2478763296 Jun 25 05:45:25 PM PDT 24 Jun 25 05:45:28 PM PDT 24 23002923 ps
T1061 /workspace/coverage/cover_reg_top/11.edn_intr_test.1070686549 Jun 25 05:45:19 PM PDT 24 Jun 25 05:45:20 PM PDT 24 21855151 ps
T274 /workspace/coverage/cover_reg_top/16.edn_csr_rw.344468684 Jun 25 05:45:26 PM PDT 24 Jun 25 05:45:28 PM PDT 24 13549461 ps
T1062 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.339528770 Jun 25 05:45:18 PM PDT 24 Jun 25 05:45:21 PM PDT 24 198749694 ps
T1063 /workspace/coverage/cover_reg_top/8.edn_intr_test.1872814161 Jun 25 05:45:16 PM PDT 24 Jun 25 05:45:18 PM PDT 24 151024467 ps
T1064 /workspace/coverage/cover_reg_top/38.edn_intr_test.136781292 Jun 25 05:45:41 PM PDT 24 Jun 25 05:45:43 PM PDT 24 34263219 ps
T1065 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3406843594 Jun 25 05:44:38 PM PDT 24 Jun 25 05:44:41 PM PDT 24 170980500 ps
T1066 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3329322693 Jun 25 05:45:18 PM PDT 24 Jun 25 05:45:21 PM PDT 24 88296968 ps
T1067 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1127728868 Jun 25 05:45:17 PM PDT 24 Jun 25 05:45:19 PM PDT 24 82914253 ps
T1068 /workspace/coverage/cover_reg_top/39.edn_intr_test.1851727757 Jun 25 05:45:43 PM PDT 24 Jun 25 05:45:44 PM PDT 24 14736309 ps
T1069 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2987997377 Jun 25 05:45:34 PM PDT 24 Jun 25 05:45:37 PM PDT 24 190226342 ps
T1070 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3819044923 Jun 25 05:45:20 PM PDT 24 Jun 25 05:45:24 PM PDT 24 262140411 ps
T1071 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4236463101 Jun 25 05:44:46 PM PDT 24 Jun 25 05:44:48 PM PDT 24 306691195 ps
T1072 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3026511903 Jun 25 05:44:39 PM PDT 24 Jun 25 05:44:41 PM PDT 24 110373269 ps
T1073 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1178604546 Jun 25 05:45:34 PM PDT 24 Jun 25 05:45:36 PM PDT 24 23047018 ps
T1074 /workspace/coverage/cover_reg_top/25.edn_intr_test.3866307153 Jun 25 05:45:46 PM PDT 24 Jun 25 05:45:48 PM PDT 24 12844485 ps
T1075 /workspace/coverage/cover_reg_top/19.edn_intr_test.3598188920 Jun 25 05:45:32 PM PDT 24 Jun 25 05:45:34 PM PDT 24 47091673 ps
T1076 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2993625230 Jun 25 05:45:18 PM PDT 24 Jun 25 05:45:22 PM PDT 24 97059522 ps
T1077 /workspace/coverage/cover_reg_top/29.edn_intr_test.3680042567 Jun 25 05:45:41 PM PDT 24 Jun 25 05:45:43 PM PDT 24 56848617 ps
T1078 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1872639584 Jun 25 05:44:44 PM PDT 24 Jun 25 05:44:46 PM PDT 24 43214904 ps
T1079 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2196185587 Jun 25 05:45:03 PM PDT 24 Jun 25 05:45:04 PM PDT 24 55331150 ps
T280 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2295141248 Jun 25 05:44:53 PM PDT 24 Jun 25 05:45:00 PM PDT 24 266563890 ps
T1080 /workspace/coverage/cover_reg_top/21.edn_intr_test.4161962275 Jun 25 05:45:33 PM PDT 24 Jun 25 05:45:34 PM PDT 24 29785123 ps
T1081 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3258479796 Jun 25 05:44:47 PM PDT 24 Jun 25 05:44:49 PM PDT 24 134493172 ps
T1082 /workspace/coverage/cover_reg_top/45.edn_intr_test.3429719772 Jun 25 05:45:52 PM PDT 24 Jun 25 05:45:54 PM PDT 24 15331790 ps
T1083 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1847663595 Jun 25 05:45:26 PM PDT 24 Jun 25 05:45:29 PM PDT 24 42289081 ps
T1084 /workspace/coverage/cover_reg_top/5.edn_tl_errors.4076804145 Jun 25 05:44:52 PM PDT 24 Jun 25 05:44:55 PM PDT 24 230801597 ps
T1085 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2210108386 Jun 25 05:45:18 PM PDT 24 Jun 25 05:45:20 PM PDT 24 20161507 ps
T1086 /workspace/coverage/cover_reg_top/2.edn_intr_test.4228729347 Jun 25 05:44:37 PM PDT 24 Jun 25 05:44:39 PM PDT 24 35083824 ps
T1087 /workspace/coverage/cover_reg_top/17.edn_intr_test.3290670832 Jun 25 05:45:24 PM PDT 24 Jun 25 05:45:26 PM PDT 24 70399434 ps
T1088 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1103680380 Jun 25 05:45:15 PM PDT 24 Jun 25 05:45:18 PM PDT 24 59200504 ps
T275 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1529621368 Jun 25 05:44:46 PM PDT 24 Jun 25 05:44:48 PM PDT 24 52586244 ps
T1089 /workspace/coverage/cover_reg_top/6.edn_intr_test.3551490775 Jun 25 05:45:03 PM PDT 24 Jun 25 05:45:04 PM PDT 24 19457831 ps
T1090 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.171625394 Jun 25 05:45:17 PM PDT 24 Jun 25 05:45:21 PM PDT 24 128852028 ps
T276 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3782618615 Jun 25 05:44:47 PM PDT 24 Jun 25 05:44:49 PM PDT 24 58187674 ps
T1091 /workspace/coverage/cover_reg_top/0.edn_csr_rw.518415858 Jun 25 05:44:30 PM PDT 24 Jun 25 05:44:32 PM PDT 24 14908040 ps
T1092 /workspace/coverage/cover_reg_top/5.edn_intr_test.3758444338 Jun 25 05:45:00 PM PDT 24 Jun 25 05:45:01 PM PDT 24 52227690 ps
T1093 /workspace/coverage/cover_reg_top/24.edn_intr_test.3176158944 Jun 25 05:45:35 PM PDT 24 Jun 25 05:45:37 PM PDT 24 13594548 ps
T1094 /workspace/coverage/cover_reg_top/7.edn_intr_test.3237112762 Jun 25 05:45:16 PM PDT 24 Jun 25 05:45:18 PM PDT 24 16719049 ps
T1095 /workspace/coverage/cover_reg_top/32.edn_intr_test.2310065198 Jun 25 05:45:42 PM PDT 24 Jun 25 05:45:43 PM PDT 24 41224584 ps
T1096 /workspace/coverage/cover_reg_top/49.edn_intr_test.2103595171 Jun 25 05:45:50 PM PDT 24 Jun 25 05:45:52 PM PDT 24 16598124 ps
T1097 /workspace/coverage/cover_reg_top/22.edn_intr_test.3241840270 Jun 25 05:45:34 PM PDT 24 Jun 25 05:45:36 PM PDT 24 13669153 ps
T1098 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2837550502 Jun 25 05:44:46 PM PDT 24 Jun 25 05:44:47 PM PDT 24 23165060 ps
T1099 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1278402360 Jun 25 05:44:39 PM PDT 24 Jun 25 05:44:41 PM PDT 24 178585345 ps
T1100 /workspace/coverage/cover_reg_top/3.edn_tl_errors.780554066 Jun 25 05:44:48 PM PDT 24 Jun 25 05:44:52 PM PDT 24 314695090 ps
T277 /workspace/coverage/cover_reg_top/18.edn_csr_rw.3175887807 Jun 25 05:45:33 PM PDT 24 Jun 25 05:45:35 PM PDT 24 12221648 ps
T1101 /workspace/coverage/cover_reg_top/12.edn_intr_test.210622919 Jun 25 05:45:21 PM PDT 24 Jun 25 05:45:22 PM PDT 24 32917557 ps
T1102 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2817654104 Jun 25 05:45:35 PM PDT 24 Jun 25 05:45:37 PM PDT 24 51966685 ps
T1103 /workspace/coverage/cover_reg_top/47.edn_intr_test.2064691471 Jun 25 05:45:51 PM PDT 24 Jun 25 05:45:53 PM PDT 24 23666764 ps
T304 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3526831970 Jun 25 05:45:27 PM PDT 24 Jun 25 05:45:30 PM PDT 24 78504387 ps
T1104 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2778234206 Jun 25 05:45:26 PM PDT 24 Jun 25 05:45:30 PM PDT 24 357591681 ps
T1105 /workspace/coverage/cover_reg_top/3.edn_intr_test.1557782711 Jun 25 05:44:45 PM PDT 24 Jun 25 05:44:46 PM PDT 24 15468506 ps
T1106 /workspace/coverage/cover_reg_top/14.edn_intr_test.1976631877 Jun 25 05:45:27 PM PDT 24 Jun 25 05:45:29 PM PDT 24 22803978 ps
T1107 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3427079072 Jun 25 05:44:46 PM PDT 24 Jun 25 05:44:51 PM PDT 24 644959512 ps
T1108 /workspace/coverage/cover_reg_top/18.edn_tl_errors.180442734 Jun 25 05:45:36 PM PDT 24 Jun 25 05:45:38 PM PDT 24 642299939 ps
T1109 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3376759688 Jun 25 05:44:40 PM PDT 24 Jun 25 05:44:41 PM PDT 24 19393074 ps
T1110 /workspace/coverage/cover_reg_top/13.edn_intr_test.3262861611 Jun 25 05:45:25 PM PDT 24 Jun 25 05:45:27 PM PDT 24 14338820 ps
T1111 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.404129061 Jun 25 05:45:26 PM PDT 24 Jun 25 05:45:28 PM PDT 24 67984269 ps
T1112 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3641207019 Jun 25 05:45:01 PM PDT 24 Jun 25 05:45:05 PM PDT 24 153790257 ps
T1113 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1012546245 Jun 25 05:45:18 PM PDT 24 Jun 25 05:45:22 PM PDT 24 356509862 ps
T1114 /workspace/coverage/cover_reg_top/30.edn_intr_test.380807822 Jun 25 05:45:45 PM PDT 24 Jun 25 05:45:47 PM PDT 24 150874678 ps
T1115 /workspace/coverage/cover_reg_top/36.edn_intr_test.54149149 Jun 25 05:45:46 PM PDT 24 Jun 25 05:45:48 PM PDT 24 16701695 ps
T1116 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3368838092 Jun 25 05:44:28 PM PDT 24 Jun 25 05:44:31 PM PDT 24 63448669 ps
T1117 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2748991677 Jun 25 05:45:32 PM PDT 24 Jun 25 05:45:37 PM PDT 24 2419369427 ps
T1118 /workspace/coverage/cover_reg_top/31.edn_intr_test.3648359839 Jun 25 05:45:45 PM PDT 24 Jun 25 05:45:47 PM PDT 24 25280805 ps
T1119 /workspace/coverage/cover_reg_top/0.edn_intr_test.811556235 Jun 25 05:44:30 PM PDT 24 Jun 25 05:44:31 PM PDT 24 45067553 ps
T1120 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2413339056 Jun 25 05:45:27 PM PDT 24 Jun 25 05:45:29 PM PDT 24 48584205 ps
T1121 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2740435866 Jun 25 05:45:32 PM PDT 24 Jun 25 05:45:34 PM PDT 24 28870809 ps
T1122 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2480138210 Jun 25 05:45:20 PM PDT 24 Jun 25 05:45:22 PM PDT 24 40683859 ps
T1123 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1731338520 Jun 25 05:45:25 PM PDT 24 Jun 25 05:45:28 PM PDT 24 55685695 ps
T278 /workspace/coverage/cover_reg_top/12.edn_csr_rw.3463082681 Jun 25 05:45:20 PM PDT 24 Jun 25 05:45:22 PM PDT 24 28051749 ps
T1124 /workspace/coverage/cover_reg_top/10.edn_tl_errors.977979631 Jun 25 05:45:17 PM PDT 24 Jun 25 05:45:22 PM PDT 24 48465176 ps
T1125 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1762226732 Jun 25 05:44:38 PM PDT 24 Jun 25 05:44:42 PM PDT 24 452268773 ps
T1126 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.464613962 Jun 25 05:44:38 PM PDT 24 Jun 25 05:44:40 PM PDT 24 47249218 ps
T1127 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3625717518 Jun 25 05:45:25 PM PDT 24 Jun 25 05:45:30 PM PDT 24 239899699 ps
T1128 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1301631291 Jun 25 05:45:25 PM PDT 24 Jun 25 05:45:28 PM PDT 24 56524913 ps

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3195176877
Short name T10
Test name
Test status
Simulation time 28830515 ps
CPU time 1.04 seconds
Started Jun 25 05:49:23 PM PDT 24
Finished Jun 25 05:49:27 PM PDT 24
Peak memory 218608 kb
Host smart-fa9dab8c-e497-4c23-92aa-dff4631a590c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195176877 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3195176877
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3203786416
Short name T6
Test name
Test status
Simulation time 95601710562 ps
CPU time 516.92 seconds
Started Jun 25 05:49:13 PM PDT 24
Finished Jun 25 05:57:52 PM PDT 24
Peak memory 222972 kb
Host smart-e3662783-2974-4c53-9aac-685eae8f9c1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203786416 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3203786416
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_genbits.4122370745
Short name T34
Test name
Test status
Simulation time 119036913 ps
CPU time 1.51 seconds
Started Jun 25 05:49:29 PM PDT 24
Finished Jun 25 05:49:32 PM PDT 24
Peak memory 219128 kb
Host smart-0cf20dc2-97fb-4a31-a7d6-d02a1a4e55e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122370745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.4122370745
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_sec_cm.2612963478
Short name T18
Test name
Test status
Simulation time 332018066 ps
CPU time 4.73 seconds
Started Jun 25 05:48:13 PM PDT 24
Finished Jun 25 05:48:20 PM PDT 24
Peak memory 235964 kb
Host smart-a6fcb124-9933-4c67-9881-18ee5d85d4f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612963478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2612963478
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/75.edn_alert.3905777599
Short name T32
Test name
Test status
Simulation time 94902867 ps
CPU time 1.27 seconds
Started Jun 25 05:50:12 PM PDT 24
Finished Jun 25 05:50:15 PM PDT 24
Peak memory 221184 kb
Host smart-2e5016f6-a10e-4fe3-9809-9753860fea13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905777599 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.3905777599
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.996770886
Short name T78
Test name
Test status
Simulation time 34518726 ps
CPU time 0.92 seconds
Started Jun 25 05:50:11 PM PDT 24
Finished Jun 25 05:50:13 PM PDT 24
Peak memory 218788 kb
Host smart-d4f7d968-76ef-4234-9ccc-76c1eb36efcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996770886 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.996770886
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/3.edn_disable.1436997587
Short name T186
Test name
Test status
Simulation time 22707475 ps
CPU time 0.91 seconds
Started Jun 25 05:48:13 PM PDT 24
Finished Jun 25 05:48:15 PM PDT 24
Peak memory 216592 kb
Host smart-b64048eb-61be-494d-9080-8bd61622e5cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436997587 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1436997587
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/40.edn_genbits.1672917681
Short name T52
Test name
Test status
Simulation time 35093273 ps
CPU time 1.42 seconds
Started Jun 25 05:49:38 PM PDT 24
Finished Jun 25 05:49:41 PM PDT 24
Peak memory 217796 kb
Host smart-6cf3d997-3968-4121-8127-33bdf2c0028f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672917681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1672917681
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.3148912743
Short name T89
Test name
Test status
Simulation time 88883972 ps
CPU time 1.26 seconds
Started Jun 25 05:50:46 PM PDT 24
Finished Jun 25 05:50:49 PM PDT 24
Peak memory 218864 kb
Host smart-f9171ffd-88a2-42f1-bcde-0736e3b28198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148912743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.3148912743
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3544386226
Short name T234
Test name
Test status
Simulation time 123546349608 ps
CPU time 781.97 seconds
Started Jun 25 05:49:23 PM PDT 24
Finished Jun 25 06:02:27 PM PDT 24
Peak memory 223012 kb
Host smart-947797ad-742f-4ef4-ab80-1c022be22b46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544386226 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3544386226
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_regwen.3061294003
Short name T535
Test name
Test status
Simulation time 54556756 ps
CPU time 0.98 seconds
Started Jun 25 05:48:05 PM PDT 24
Finished Jun 25 05:48:07 PM PDT 24
Peak memory 207444 kb
Host smart-17eb0fa9-38d5-45a7-bdb6-ec957f6c78a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061294003 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3061294003
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3770210211
Short name T67
Test name
Test status
Simulation time 38940399 ps
CPU time 1.3 seconds
Started Jun 25 05:49:49 PM PDT 24
Finished Jun 25 05:49:52 PM PDT 24
Peak memory 219816 kb
Host smart-46539a83-6412-46e6-98d7-d8c5b996840c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770210211 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3770210211
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/63.edn_alert.759227129
Short name T102
Test name
Test status
Simulation time 43724114 ps
CPU time 1.21 seconds
Started Jun 25 05:50:02 PM PDT 24
Finished Jun 25 05:50:05 PM PDT 24
Peak memory 219048 kb
Host smart-14e38049-c953-4997-875f-a3e6fe76a2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759227129 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.759227129
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1662504936
Short name T303
Test name
Test status
Simulation time 245988992 ps
CPU time 2.28 seconds
Started Jun 25 05:45:20 PM PDT 24
Finished Jun 25 05:45:23 PM PDT 24
Peak memory 207028 kb
Host smart-e73b25b1-eb1d-4399-9d2c-51b70b640459
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662504936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1662504936
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/33.edn_disable.3469148256
Short name T81
Test name
Test status
Simulation time 20654214 ps
CPU time 0.88 seconds
Started Jun 25 05:49:23 PM PDT 24
Finished Jun 25 05:49:26 PM PDT 24
Peak memory 216676 kb
Host smart-0ff0fdd5-b303-4fdc-a23a-9b75c01b32b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469148256 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3469148256
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/86.edn_alert.4249318155
Short name T317
Test name
Test status
Simulation time 24831673 ps
CPU time 1.29 seconds
Started Jun 25 05:50:21 PM PDT 24
Finished Jun 25 05:50:23 PM PDT 24
Peak memory 220900 kb
Host smart-1a01579c-0c9f-4806-a160-9d448f00f1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249318155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.4249318155
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.2120740273
Short name T5
Test name
Test status
Simulation time 29824462 ps
CPU time 0.93 seconds
Started Jun 25 05:50:00 PM PDT 24
Finished Jun 25 05:50:02 PM PDT 24
Peak memory 218568 kb
Host smart-bca2810d-df95-41c0-b730-4e8fbb97f5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120740273 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2120740273
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/12.edn_disable.2501783336
Short name T211
Test name
Test status
Simulation time 12679073 ps
CPU time 0.92 seconds
Started Jun 25 05:48:38 PM PDT 24
Finished Jun 25 05:48:40 PM PDT 24
Peak memory 216748 kb
Host smart-5e979052-6bbf-4252-ae99-3f351ff68ff1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501783336 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2501783336
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable.3649157536
Short name T203
Test name
Test status
Simulation time 14541509 ps
CPU time 0.9 seconds
Started Jun 25 05:48:38 PM PDT 24
Finished Jun 25 05:48:40 PM PDT 24
Peak memory 216512 kb
Host smart-dd9d5a55-dd38-4a05-be44-1dbde281251d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649157536 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3649157536
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.147953708
Short name T110
Test name
Test status
Simulation time 54824656 ps
CPU time 1.11 seconds
Started Jun 25 05:48:12 PM PDT 24
Finished Jun 25 05:48:14 PM PDT 24
Peak memory 217316 kb
Host smart-f82d597c-ceff-4e9e-ad8e-a622a6607ff1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147953708 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.147953708
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/161.edn_alert.2764796867
Short name T287
Test name
Test status
Simulation time 91129317 ps
CPU time 1.25 seconds
Started Jun 25 05:50:47 PM PDT 24
Finished Jun 25 05:50:50 PM PDT 24
Peak memory 220188 kb
Host smart-6c15ebda-7839-4a6f-ab6b-3cbe3b7f44ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764796867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.2764796867
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1529621368
Short name T275
Test name
Test status
Simulation time 52586244 ps
CPU time 0.91 seconds
Started Jun 25 05:44:46 PM PDT 24
Finished Jun 25 05:44:48 PM PDT 24
Peak memory 206960 kb
Host smart-3b0491cd-0a5c-4d8c-b871-9b1ab034ce59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529621368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1529621368
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/default/3.edn_genbits.655289099
Short name T49
Test name
Test status
Simulation time 51556870 ps
CPU time 1.23 seconds
Started Jun 25 05:48:15 PM PDT 24
Finished Jun 25 05:48:18 PM PDT 24
Peak memory 219252 kb
Host smart-7ccf5455-be76-4c34-af0c-efba27cd0b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655289099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.655289099
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.811588678
Short name T30
Test name
Test status
Simulation time 44959563 ps
CPU time 1.29 seconds
Started Jun 25 05:50:37 PM PDT 24
Finished Jun 25 05:50:40 PM PDT 24
Peak memory 221260 kb
Host smart-04ddfed0-6a21-446f-8abf-bc4b8182b0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811588678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.811588678
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/167.edn_alert.167931533
Short name T117
Test name
Test status
Simulation time 107168465 ps
CPU time 1.38 seconds
Started Jun 25 05:50:54 PM PDT 24
Finished Jun 25 05:50:57 PM PDT 24
Peak memory 219980 kb
Host smart-e5546b1e-5dfa-43d8-ae5a-15e1aaeec39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167931533 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.167931533
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.821389100
Short name T322
Test name
Test status
Simulation time 49422805 ps
CPU time 1.67 seconds
Started Jun 25 05:50:42 PM PDT 24
Finished Jun 25 05:50:45 PM PDT 24
Peak memory 218768 kb
Host smart-132af012-c659-47ed-9939-730177ad6621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821389100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.821389100
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_alert.1637479136
Short name T263
Test name
Test status
Simulation time 33031257 ps
CPU time 1.23 seconds
Started Jun 25 05:49:20 PM PDT 24
Finished Jun 25 05:49:23 PM PDT 24
Peak memory 219004 kb
Host smart-55a933fb-6e83-4d2d-bb6c-d59136d692e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637479136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1637479136
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/122.edn_alert.1840652096
Short name T199
Test name
Test status
Simulation time 22586112 ps
CPU time 1.12 seconds
Started Jun 25 05:50:31 PM PDT 24
Finished Jun 25 05:50:35 PM PDT 24
Peak memory 220264 kb
Host smart-0164818f-aa10-4b10-b02d-b084af6ff517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840652096 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.1840652096
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/123.edn_alert.110056011
Short name T486
Test name
Test status
Simulation time 22890125 ps
CPU time 1.16 seconds
Started Jun 25 05:50:31 PM PDT 24
Finished Jun 25 05:50:35 PM PDT 24
Peak memory 220140 kb
Host smart-f4aa74a6-0d96-4b27-84b8-928596f5336d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110056011 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.110056011
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/132.edn_alert.4247406652
Short name T801
Test name
Test status
Simulation time 45773928 ps
CPU time 1.18 seconds
Started Jun 25 05:50:43 PM PDT 24
Finished Jun 25 05:50:45 PM PDT 24
Peak memory 220020 kb
Host smart-d9895f0f-7c1f-43fa-b999-e706a34c5b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247406652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.4247406652
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.2510874508
Short name T60
Test name
Test status
Simulation time 31184230 ps
CPU time 1.02 seconds
Started Jun 25 05:49:56 PM PDT 24
Finished Jun 25 05:49:59 PM PDT 24
Peak memory 229680 kb
Host smart-f68e0753-1883-4bc7-a7e8-999ccaa3f39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510874508 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2510874508
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1355902044
Short name T663
Test name
Test status
Simulation time 32219193942 ps
CPU time 742.66 seconds
Started Jun 25 05:48:32 PM PDT 24
Finished Jun 25 06:00:56 PM PDT 24
Peak memory 224044 kb
Host smart-28507c9f-28fd-4a09-a901-bc65962970fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355902044 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1355902044
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.1825612430
Short name T874
Test name
Test status
Simulation time 27675965 ps
CPU time 1.28 seconds
Started Jun 25 05:50:27 PM PDT 24
Finished Jun 25 05:50:29 PM PDT 24
Peak memory 219736 kb
Host smart-25bcc73b-5e20-4b5b-a4b0-e0902e235d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825612430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.1825612430
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/42.edn_genbits.760242956
Short name T56
Test name
Test status
Simulation time 77949702 ps
CPU time 1.35 seconds
Started Jun 25 05:49:40 PM PDT 24
Finished Jun 25 05:49:42 PM PDT 24
Peak memory 218732 kb
Host smart-1d812b54-4152-4b2b-91ec-14cd301cba79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760242956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.760242956
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.678029687
Short name T45
Test name
Test status
Simulation time 21322489 ps
CPU time 1.06 seconds
Started Jun 25 05:49:46 PM PDT 24
Finished Jun 25 05:49:49 PM PDT 24
Peak memory 216096 kb
Host smart-320daac3-8328-4537-854d-9bdcb92d36b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678029687 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.678029687
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/18.edn_alert.3200173258
Short name T229
Test name
Test status
Simulation time 34162341 ps
CPU time 1.18 seconds
Started Jun 25 05:48:46 PM PDT 24
Finished Jun 25 05:48:48 PM PDT 24
Peak memory 219004 kb
Host smart-5acb7eb6-bc3f-4b59-ac50-bde65ebe5e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200173258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3200173258
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/13.edn_intr.3746073015
Short name T4
Test name
Test status
Simulation time 22226752 ps
CPU time 1.14 seconds
Started Jun 25 05:48:40 PM PDT 24
Finished Jun 25 05:48:42 PM PDT 24
Peak memory 216164 kb
Host smart-a62b4920-5182-425d-9c65-6c6ad8e55257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746073015 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3746073015
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/10.edn_disable.666035661
Short name T220
Test name
Test status
Simulation time 38051542 ps
CPU time 0.84 seconds
Started Jun 25 05:48:31 PM PDT 24
Finished Jun 25 05:48:34 PM PDT 24
Peak memory 215768 kb
Host smart-0836bead-daaa-4ae1-8ad6-e6503fc295d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666035661 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.666035661
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1846784128
Short name T21
Test name
Test status
Simulation time 32033631 ps
CPU time 1.21 seconds
Started Jun 25 05:48:31 PM PDT 24
Finished Jun 25 05:48:34 PM PDT 24
Peak memory 216984 kb
Host smart-bde8b4df-0568-4685-a7b3-9432c7b26a2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846784128 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1846784128
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/108.edn_alert.3925431994
Short name T119
Test name
Test status
Simulation time 29506678 ps
CPU time 1.35 seconds
Started Jun 25 05:50:29 PM PDT 24
Finished Jun 25 05:50:32 PM PDT 24
Peak memory 219056 kb
Host smart-c1c2ed90-0e82-40dc-8c76-1fa71ff87c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925431994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.3925431994
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/133.edn_alert.3119775503
Short name T114
Test name
Test status
Simulation time 52995622 ps
CPU time 1.21 seconds
Started Jun 25 05:50:44 PM PDT 24
Finished Jun 25 05:50:46 PM PDT 24
Peak memory 216012 kb
Host smart-518e2149-7b92-44b0-b95f-930f073f4364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119775503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.3119775503
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/139.edn_alert.2796730895
Short name T385
Test name
Test status
Simulation time 75249806 ps
CPU time 0.98 seconds
Started Jun 25 05:50:38 PM PDT 24
Finished Jun 25 05:50:40 PM PDT 24
Peak memory 218656 kb
Host smart-7924a937-0633-4805-87d0-96b8afafea56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796730895 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.2796730895
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/156.edn_alert.26570235
Short name T188
Test name
Test status
Simulation time 50790945 ps
CPU time 1.13 seconds
Started Jun 25 05:50:46 PM PDT 24
Finished Jun 25 05:50:49 PM PDT 24
Peak memory 218716 kb
Host smart-a8aa44eb-33fe-4e4f-8984-29a82d384da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26570235 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.26570235
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1052382650
Short name T221
Test name
Test status
Simulation time 107632248 ps
CPU time 1.11 seconds
Started Jun 25 05:48:46 PM PDT 24
Finished Jun 25 05:48:48 PM PDT 24
Peak memory 217228 kb
Host smart-ed0c81f6-f788-43db-b48f-7f6a0b8a738a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052382650 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1052382650
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_disable.2491939252
Short name T204
Test name
Test status
Simulation time 14517901 ps
CPU time 0.97 seconds
Started Jun 25 05:48:48 PM PDT 24
Finished Jun 25 05:48:51 PM PDT 24
Peak memory 216752 kb
Host smart-c7c3e5db-0f2a-4919-8e0a-f2bb3fd8a3f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491939252 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2491939252
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1396066089
Short name T12
Test name
Test status
Simulation time 98316021 ps
CPU time 1.17 seconds
Started Jun 25 05:48:46 PM PDT 24
Finished Jun 25 05:48:48 PM PDT 24
Peak memory 217332 kb
Host smart-a5eb8318-a06b-4c7b-9601-1f5a76edc623
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396066089 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1396066089
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3602777697
Short name T134
Test name
Test status
Simulation time 36349751 ps
CPU time 1.03 seconds
Started Jun 25 05:48:55 PM PDT 24
Finished Jun 25 05:48:58 PM PDT 24
Peak memory 217228 kb
Host smart-c16d14aa-cbd9-4668-842e-e6a0cdb76e9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602777697 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3602777697
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3983084840
Short name T191
Test name
Test status
Simulation time 19420054 ps
CPU time 1.16 seconds
Started Jun 25 05:49:11 PM PDT 24
Finished Jun 25 05:49:14 PM PDT 24
Peak memory 224300 kb
Host smart-d80be1e2-aa3c-4859-8ae6-aabbe2886c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983084840 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3983084840
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/44.edn_disable.1535407659
Short name T195
Test name
Test status
Simulation time 17704012 ps
CPU time 0.86 seconds
Started Jun 25 05:49:43 PM PDT 24
Finished Jun 25 05:49:45 PM PDT 24
Peak memory 216652 kb
Host smart-22ed482f-9825-4b17-ae0f-541e9c10542e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535407659 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1535407659
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/88.edn_genbits.2965715534
Short name T324
Test name
Test status
Simulation time 53195990 ps
CPU time 1.52 seconds
Started Jun 25 05:50:26 PM PDT 24
Finished Jun 25 05:50:29 PM PDT 24
Peak memory 218912 kb
Host smart-d7d8295d-2203-4849-9021-84d44ae3d549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965715534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2965715534
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.371598297
Short name T311
Test name
Test status
Simulation time 68471099 ps
CPU time 1.14 seconds
Started Jun 25 05:51:01 PM PDT 24
Finished Jun 25 05:51:03 PM PDT 24
Peak memory 220332 kb
Host smart-10470cdd-8c9a-4ff2-88b9-557b12ba1c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371598297 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.371598297
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3436124004
Short name T424
Test name
Test status
Simulation time 21246844 ps
CPU time 1.02 seconds
Started Jun 25 05:48:41 PM PDT 24
Finished Jun 25 05:48:43 PM PDT 24
Peak memory 215212 kb
Host smart-7cc637a3-50d7-4b82-8f87-73c68af621f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436124004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3436124004
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/164.edn_genbits.3689550688
Short name T352
Test name
Test status
Simulation time 53267800 ps
CPU time 1.25 seconds
Started Jun 25 05:51:01 PM PDT 24
Finished Jun 25 05:51:04 PM PDT 24
Peak memory 220240 kb
Host smart-a5b188a6-1431-4f31-ba78-1c8b8b0f94f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689550688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3689550688
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_genbits.376229748
Short name T732
Test name
Test status
Simulation time 134320323 ps
CPU time 1.63 seconds
Started Jun 25 05:48:06 PM PDT 24
Finished Jun 25 05:48:09 PM PDT 24
Peak memory 219012 kb
Host smart-d8282ca4-e405-4cc4-b96d-8c74647f9b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376229748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.376229748
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.4174179964
Short name T335
Test name
Test status
Simulation time 65850881 ps
CPU time 1.67 seconds
Started Jun 25 05:50:45 PM PDT 24
Finished Jun 25 05:50:49 PM PDT 24
Peak memory 218776 kb
Host smart-c7819841-6760-4e61-ba1b-b1e684293fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174179964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.4174179964
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_genbits.349848018
Short name T355
Test name
Test status
Simulation time 135184508 ps
CPU time 1.66 seconds
Started Jun 25 05:48:56 PM PDT 24
Finished Jun 25 05:49:00 PM PDT 24
Peak memory 220280 kb
Host smart-cfda7dbf-df75-42dc-a2fe-dba89b1425a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349848018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.349848018
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1310121525
Short name T268
Test name
Test status
Simulation time 26600755 ps
CPU time 0.89 seconds
Started Jun 25 05:45:19 PM PDT 24
Finished Jun 25 05:45:21 PM PDT 24
Peak memory 206948 kb
Host smart-fae15ec3-64ea-4169-9579-8839461f07e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310121525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1310121525
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/default/0.edn_stress_all.3467602905
Short name T885
Test name
Test status
Simulation time 359816269 ps
CPU time 3.95 seconds
Started Jun 25 05:48:03 PM PDT 24
Finished Jun 25 05:48:09 PM PDT 24
Peak memory 215644 kb
Host smart-ef7839aa-9276-4bdd-a4ce-e12e90139463
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467602905 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3467602905
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_genbits.438780614
Short name T339
Test name
Test status
Simulation time 248213213 ps
CPU time 3.28 seconds
Started Jun 25 05:48:05 PM PDT 24
Finished Jun 25 05:48:10 PM PDT 24
Peak memory 220212 kb
Host smart-27e58c77-83b4-47a0-8a59-936d86edebb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438780614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.438780614
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3137432710
Short name T349
Test name
Test status
Simulation time 121937358 ps
CPU time 1.63 seconds
Started Jun 25 05:50:32 PM PDT 24
Finished Jun 25 05:50:36 PM PDT 24
Peak memory 218992 kb
Host smart-c0116cc7-680b-443e-ae84-ea96ce129b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137432710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3137432710
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.1112532086
Short name T646
Test name
Test status
Simulation time 43780820 ps
CPU time 1.44 seconds
Started Jun 25 05:50:33 PM PDT 24
Finished Jun 25 05:50:37 PM PDT 24
Peak memory 218848 kb
Host smart-26f23bf9-2f0c-47b0-b91c-3fd92764d164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112532086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1112532086
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.2791426331
Short name T629
Test name
Test status
Simulation time 208008283 ps
CPU time 1.1 seconds
Started Jun 25 05:50:31 PM PDT 24
Finished Jun 25 05:50:35 PM PDT 24
Peak memory 217604 kb
Host smart-2c20cbb5-6d1a-4520-8e31-97f5d3298d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791426331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2791426331
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.4005597415
Short name T987
Test name
Test status
Simulation time 63114486 ps
CPU time 2.29 seconds
Started Jun 25 05:50:41 PM PDT 24
Finished Jun 25 05:50:44 PM PDT 24
Peak memory 218840 kb
Host smart-f9fc04a5-310e-4366-8a63-1462c3a4bccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005597415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.4005597415
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.3866557410
Short name T328
Test name
Test status
Simulation time 91669777 ps
CPU time 1.46 seconds
Started Jun 25 05:50:43 PM PDT 24
Finished Jun 25 05:50:46 PM PDT 24
Peak memory 219064 kb
Host smart-d679a76f-1ae9-4be4-9a37-ab197960b829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866557410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3866557410
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/160.edn_alert.953865962
Short name T300
Test name
Test status
Simulation time 136374884 ps
CPU time 1.24 seconds
Started Jun 25 05:50:45 PM PDT 24
Finished Jun 25 05:50:48 PM PDT 24
Peak memory 218756 kb
Host smart-5015c8a9-8d86-4e53-b6c8-8b197b31b6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953865962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.953865962
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/17.edn_genbits.4199306533
Short name T591
Test name
Test status
Simulation time 65790477 ps
CPU time 1.1 seconds
Started Jun 25 05:48:50 PM PDT 24
Finished Jun 25 05:48:53 PM PDT 24
Peak memory 220480 kb
Host smart-7ec6accb-310c-4d41-8b78-021ca7682689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199306533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.4199306533
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.936989064
Short name T337
Test name
Test status
Simulation time 70721261 ps
CPU time 1.25 seconds
Started Jun 25 05:51:17 PM PDT 24
Finished Jun 25 05:51:20 PM PDT 24
Peak memory 220332 kb
Host smart-f9e84512-0f30-444d-bf9a-d614f8ff97de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936989064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.936989064
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2665022455
Short name T265
Test name
Test status
Simulation time 28003251 ps
CPU time 1.28 seconds
Started Jun 25 05:49:38 PM PDT 24
Finished Jun 25 05:49:41 PM PDT 24
Peak memory 217344 kb
Host smart-2a3992d8-1b51-411e-a764-8cf73b1f376d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665022455 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2665022455
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_intr.1740102030
Short name T852
Test name
Test status
Simulation time 33866593 ps
CPU time 0.88 seconds
Started Jun 25 05:48:48 PM PDT 24
Finished Jun 25 05:48:51 PM PDT 24
Peak memory 215920 kb
Host smart-84150779-5f45-4594-a58a-a36514ac02a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740102030 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1740102030
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/10.edn_intr.3627258912
Short name T43
Test name
Test status
Simulation time 44234261 ps
CPU time 0.89 seconds
Started Jun 25 05:48:30 PM PDT 24
Finished Jun 25 05:48:32 PM PDT 24
Peak memory 216104 kb
Host smart-a95fb2bb-f4d9-4306-a436-6aedd755dfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627258912 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3627258912
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/120.edn_alert.1050362350
Short name T813
Test name
Test status
Simulation time 78716329 ps
CPU time 1.28 seconds
Started Jun 25 05:50:28 PM PDT 24
Finished Jun 25 05:50:31 PM PDT 24
Peak memory 220200 kb
Host smart-1842d221-ec53-4734-b734-3cf4487b0c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050362350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.1050362350
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/1.edn_err.177012773
Short name T7
Test name
Test status
Simulation time 55378121 ps
CPU time 1.16 seconds
Started Jun 25 05:48:15 PM PDT 24
Finished Jun 25 05:48:18 PM PDT 24
Peak memory 230020 kb
Host smart-3086c39b-69b4-4259-9a1e-e918f982a509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177012773 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.177012773
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.464613962
Short name T1126
Test name
Test status
Simulation time 47249218 ps
CPU time 1.02 seconds
Started Jun 25 05:44:38 PM PDT 24
Finished Jun 25 05:44:40 PM PDT 24
Peak memory 207016 kb
Host smart-2748a9a1-5880-4e24-aaba-9aaef1f093cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464613962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.464613962
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1762226732
Short name T1125
Test name
Test status
Simulation time 452268773 ps
CPU time 3.3 seconds
Started Jun 25 05:44:38 PM PDT 24
Finished Jun 25 05:44:42 PM PDT 24
Peak memory 206936 kb
Host smart-4f8a5f0f-9569-43c4-ad5c-643032458265
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762226732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1762226732
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3053116002
Short name T1047
Test name
Test status
Simulation time 12433346 ps
CPU time 0.86 seconds
Started Jun 25 05:44:29 PM PDT 24
Finished Jun 25 05:44:30 PM PDT 24
Peak memory 206960 kb
Host smart-8ea89583-e5c4-4b62-9f81-f66cec8d2c3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053116002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3053116002
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.351915052
Short name T1021
Test name
Test status
Simulation time 76085174 ps
CPU time 1.2 seconds
Started Jun 25 05:44:39 PM PDT 24
Finished Jun 25 05:44:41 PM PDT 24
Peak memory 215232 kb
Host smart-258dcf76-74c0-40b5-ae9f-fed8199a40b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351915052 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.351915052
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.518415858
Short name T1091
Test name
Test status
Simulation time 14908040 ps
CPU time 0.98 seconds
Started Jun 25 05:44:30 PM PDT 24
Finished Jun 25 05:44:32 PM PDT 24
Peak memory 206884 kb
Host smart-5b28d915-dbc1-40e6-b9fd-8bddbd64fea3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518415858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.518415858
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.811556235
Short name T1119
Test name
Test status
Simulation time 45067553 ps
CPU time 0.83 seconds
Started Jun 25 05:44:30 PM PDT 24
Finished Jun 25 05:44:31 PM PDT 24
Peak memory 206884 kb
Host smart-4afe375b-ef29-42d7-b49f-6248cf55d356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811556235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.811556235
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3376759688
Short name T1109
Test name
Test status
Simulation time 19393074 ps
CPU time 1.02 seconds
Started Jun 25 05:44:40 PM PDT 24
Finished Jun 25 05:44:41 PM PDT 24
Peak memory 206956 kb
Host smart-a6c389f8-920e-4fe0-9d4e-69d328635af8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376759688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3376759688
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3368838092
Short name T1116
Test name
Test status
Simulation time 63448669 ps
CPU time 2.45 seconds
Started Jun 25 05:44:28 PM PDT 24
Finished Jun 25 05:44:31 PM PDT 24
Peak memory 215140 kb
Host smart-2525e114-e173-4cac-a694-a510025f73e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368838092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3368838092
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3429688342
Short name T1045
Test name
Test status
Simulation time 75942965 ps
CPU time 1.55 seconds
Started Jun 25 05:44:29 PM PDT 24
Finished Jun 25 05:44:31 PM PDT 24
Peak memory 207048 kb
Host smart-06845447-6d3b-4c3f-a9ee-50365f8cbfa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429688342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3429688342
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3244975160
Short name T272
Test name
Test status
Simulation time 17712997 ps
CPU time 1.23 seconds
Started Jun 25 05:44:39 PM PDT 24
Finished Jun 25 05:44:41 PM PDT 24
Peak memory 207148 kb
Host smart-c19a5f33-548b-43bf-9ee2-10e902ee09f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244975160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3244975160
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1431211161
Short name T279
Test name
Test status
Simulation time 457941629 ps
CPU time 3.32 seconds
Started Jun 25 05:44:39 PM PDT 24
Finished Jun 25 05:44:43 PM PDT 24
Peak memory 207024 kb
Host smart-1b5e2a30-30d5-41c8-8a3b-7f2968e2eae2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431211161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1431211161
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3555224984
Short name T271
Test name
Test status
Simulation time 29410125 ps
CPU time 0.97 seconds
Started Jun 25 05:44:37 PM PDT 24
Finished Jun 25 05:44:39 PM PDT 24
Peak memory 206936 kb
Host smart-2b769ac7-b8b1-4c3b-883c-3e049f82240b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555224984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3555224984
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3026511903
Short name T1072
Test name
Test status
Simulation time 110373269 ps
CPU time 1.37 seconds
Started Jun 25 05:44:39 PM PDT 24
Finished Jun 25 05:44:41 PM PDT 24
Peak memory 215216 kb
Host smart-89d556cc-2fe6-47b5-9219-174cd369a105
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026511903 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3026511903
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1253351466
Short name T1020
Test name
Test status
Simulation time 46357812 ps
CPU time 0.91 seconds
Started Jun 25 05:44:39 PM PDT 24
Finished Jun 25 05:44:40 PM PDT 24
Peak memory 206956 kb
Host smart-8309eec2-54a5-446a-aea7-ae5b5baf79ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253351466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1253351466
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2603504361
Short name T994
Test name
Test status
Simulation time 30026770 ps
CPU time 0.78 seconds
Started Jun 25 05:44:38 PM PDT 24
Finished Jun 25 05:44:39 PM PDT 24
Peak memory 206740 kb
Host smart-3ab751a3-9e4b-4e61-b9ca-12d29e54c35b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603504361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2603504361
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1278402360
Short name T1099
Test name
Test status
Simulation time 178585345 ps
CPU time 1.44 seconds
Started Jun 25 05:44:39 PM PDT 24
Finished Jun 25 05:44:41 PM PDT 24
Peak memory 206940 kb
Host smart-6176a0ca-f390-4cd8-8308-5f3d8fc09ff3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278402360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1278402360
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3692919330
Short name T1043
Test name
Test status
Simulation time 345005224 ps
CPU time 3.72 seconds
Started Jun 25 05:44:38 PM PDT 24
Finished Jun 25 05:44:42 PM PDT 24
Peak memory 215216 kb
Host smart-756b3db7-f4d0-4c9f-85c2-d5762f1c5ba4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692919330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3692919330
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2089676965
Short name T1050
Test name
Test status
Simulation time 170403742 ps
CPU time 1.5 seconds
Started Jun 25 05:44:37 PM PDT 24
Finished Jun 25 05:44:40 PM PDT 24
Peak memory 215144 kb
Host smart-9adf4ff5-319c-408f-9d71-890a1ad2230a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089676965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2089676965
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3329322693
Short name T1066
Test name
Test status
Simulation time 88296968 ps
CPU time 1.08 seconds
Started Jun 25 05:45:18 PM PDT 24
Finished Jun 25 05:45:21 PM PDT 24
Peak memory 216876 kb
Host smart-ebb4dc19-c908-4fad-b91f-b77ce378f044
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329322693 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3329322693
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3220797989
Short name T1030
Test name
Test status
Simulation time 56378349 ps
CPU time 0.97 seconds
Started Jun 25 05:45:18 PM PDT 24
Finished Jun 25 05:45:20 PM PDT 24
Peak memory 206884 kb
Host smart-417380ca-ba35-4b08-8f84-1e00d9a40459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220797989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3220797989
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1405136268
Short name T267
Test name
Test status
Simulation time 18984690 ps
CPU time 1.18 seconds
Started Jun 25 05:45:20 PM PDT 24
Finished Jun 25 05:45:22 PM PDT 24
Peak memory 207016 kb
Host smart-f2f087da-baf0-4013-aacd-83b0ba8b9550
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405136268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1405136268
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.977979631
Short name T1124
Test name
Test status
Simulation time 48465176 ps
CPU time 3.23 seconds
Started Jun 25 05:45:17 PM PDT 24
Finished Jun 25 05:45:22 PM PDT 24
Peak memory 215324 kb
Host smart-d262c359-746c-4cb7-bfe6-19000eeb7143
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977979631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.977979631
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2550890839
Short name T1040
Test name
Test status
Simulation time 281364147 ps
CPU time 2.17 seconds
Started Jun 25 05:45:19 PM PDT 24
Finished Jun 25 05:45:22 PM PDT 24
Peak memory 206908 kb
Host smart-eb9216ff-f715-4643-92c6-12de4cc9d85a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550890839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2550890839
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2743418582
Short name T1033
Test name
Test status
Simulation time 27956072 ps
CPU time 1.32 seconds
Started Jun 25 05:45:17 PM PDT 24
Finished Jun 25 05:45:19 PM PDT 24
Peak memory 223408 kb
Host smart-787d1705-a029-4a95-a375-60c81ea8f980
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743418582 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2743418582
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2210108386
Short name T1085
Test name
Test status
Simulation time 20161507 ps
CPU time 0.78 seconds
Started Jun 25 05:45:18 PM PDT 24
Finished Jun 25 05:45:20 PM PDT 24
Peak memory 206772 kb
Host smart-21182508-b886-4fa4-82f7-d0eb6f589565
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210108386 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2210108386
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1070686549
Short name T1061
Test name
Test status
Simulation time 21855151 ps
CPU time 0.82 seconds
Started Jun 25 05:45:19 PM PDT 24
Finished Jun 25 05:45:20 PM PDT 24
Peak memory 206916 kb
Host smart-5844d50b-1052-4640-86be-b0f6babad012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070686549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1070686549
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1127728868
Short name T1067
Test name
Test status
Simulation time 82914253 ps
CPU time 0.95 seconds
Started Jun 25 05:45:17 PM PDT 24
Finished Jun 25 05:45:19 PM PDT 24
Peak memory 206964 kb
Host smart-d112469f-6d22-4695-900a-48b7f2b6fceb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127728868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1127728868
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1103680380
Short name T1088
Test name
Test status
Simulation time 59200504 ps
CPU time 1.56 seconds
Started Jun 25 05:45:15 PM PDT 24
Finished Jun 25 05:45:18 PM PDT 24
Peak memory 215296 kb
Host smart-3e228fe8-9f5e-4d35-8160-a1150028bc5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103680380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1103680380
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1012546245
Short name T1113
Test name
Test status
Simulation time 356509862 ps
CPU time 2.34 seconds
Started Jun 25 05:45:18 PM PDT 24
Finished Jun 25 05:45:22 PM PDT 24
Peak memory 215168 kb
Host smart-10742210-241d-4cf9-9a82-e72939b7d4be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012546245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1012546245
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1301631291
Short name T1128
Test name
Test status
Simulation time 56524913 ps
CPU time 1 seconds
Started Jun 25 05:45:25 PM PDT 24
Finished Jun 25 05:45:28 PM PDT 24
Peak memory 207016 kb
Host smart-419777c1-63ae-4b34-b26c-df9f848861e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301631291 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1301631291
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3463082681
Short name T278
Test name
Test status
Simulation time 28051749 ps
CPU time 0.9 seconds
Started Jun 25 05:45:20 PM PDT 24
Finished Jun 25 05:45:22 PM PDT 24
Peak memory 206972 kb
Host smart-2af17140-5f73-454a-b133-8d24c768da0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463082681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3463082681
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.210622919
Short name T1101
Test name
Test status
Simulation time 32917557 ps
CPU time 0.86 seconds
Started Jun 25 05:45:21 PM PDT 24
Finished Jun 25 05:45:22 PM PDT 24
Peak memory 206908 kb
Host smart-c4779b69-199f-489a-8c7c-acf53233517b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210622919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.210622919
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2190549052
Short name T269
Test name
Test status
Simulation time 65552926 ps
CPU time 1.38 seconds
Started Jun 25 05:45:26 PM PDT 24
Finished Jun 25 05:45:29 PM PDT 24
Peak memory 206952 kb
Host smart-d85d14e6-2a54-4438-8fee-e9ff14b6d54e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190549052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2190549052
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3819044923
Short name T1070
Test name
Test status
Simulation time 262140411 ps
CPU time 2.61 seconds
Started Jun 25 05:45:20 PM PDT 24
Finished Jun 25 05:45:24 PM PDT 24
Peak memory 215236 kb
Host smart-38fc94a3-b860-424c-a70a-346d2008017e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819044923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3819044923
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3583498230
Short name T1038
Test name
Test status
Simulation time 89834551 ps
CPU time 2.5 seconds
Started Jun 25 05:45:18 PM PDT 24
Finished Jun 25 05:45:22 PM PDT 24
Peak memory 215216 kb
Host smart-3ee2cc6c-4808-42ab-8fe8-c2d5a361a9d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583498230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3583498230
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1564413879
Short name T1044
Test name
Test status
Simulation time 27335800 ps
CPU time 0.96 seconds
Started Jun 25 05:45:25 PM PDT 24
Finished Jun 25 05:45:28 PM PDT 24
Peak memory 207020 kb
Host smart-4dacd23c-015c-4c22-be8b-f831b6674448
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564413879 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1564413879
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1847663595
Short name T1083
Test name
Test status
Simulation time 42289081 ps
CPU time 0.92 seconds
Started Jun 25 05:45:26 PM PDT 24
Finished Jun 25 05:45:29 PM PDT 24
Peak memory 206932 kb
Host smart-c60b5e3e-cb57-4a35-9fff-bc0344c2103d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847663595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1847663595
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3262861611
Short name T1110
Test name
Test status
Simulation time 14338820 ps
CPU time 0.87 seconds
Started Jun 25 05:45:25 PM PDT 24
Finished Jun 25 05:45:27 PM PDT 24
Peak memory 206708 kb
Host smart-d078e3f5-dadb-4aa8-b163-f867f765e61a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262861611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3262861611
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2403192778
Short name T270
Test name
Test status
Simulation time 73646227 ps
CPU time 1.17 seconds
Started Jun 25 05:45:28 PM PDT 24
Finished Jun 25 05:45:30 PM PDT 24
Peak memory 206720 kb
Host smart-ed3951ec-8f02-4127-b689-1518c0f50947
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403192778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2403192778
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3356447668
Short name T1029
Test name
Test status
Simulation time 104679345 ps
CPU time 3.67 seconds
Started Jun 25 05:45:25 PM PDT 24
Finished Jun 25 05:45:30 PM PDT 24
Peak memory 215236 kb
Host smart-227144ae-b0d9-4136-a1cd-21e40f519675
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356447668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3356447668
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3526831970
Short name T304
Test name
Test status
Simulation time 78504387 ps
CPU time 2.29 seconds
Started Jun 25 05:45:27 PM PDT 24
Finished Jun 25 05:45:30 PM PDT 24
Peak memory 206956 kb
Host smart-7c0e7641-f8dc-4060-b335-fc758753fb7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526831970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3526831970
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2507550961
Short name T1025
Test name
Test status
Simulation time 120880117 ps
CPU time 1.17 seconds
Started Jun 25 05:45:24 PM PDT 24
Finished Jun 25 05:45:26 PM PDT 24
Peak memory 216720 kb
Host smart-0917c3d2-fafe-47e2-a20a-174bc8efcb25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507550961 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2507550961
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1028627361
Short name T1049
Test name
Test status
Simulation time 62853970 ps
CPU time 0.86 seconds
Started Jun 25 05:45:27 PM PDT 24
Finished Jun 25 05:45:29 PM PDT 24
Peak memory 206960 kb
Host smart-43043838-502f-4aac-9e8f-52ce4f855407
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028627361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1028627361
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1976631877
Short name T1106
Test name
Test status
Simulation time 22803978 ps
CPU time 0.85 seconds
Started Jun 25 05:45:27 PM PDT 24
Finished Jun 25 05:45:29 PM PDT 24
Peak memory 206900 kb
Host smart-d07cd27e-cafb-48a9-8a54-41826ef82e96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976631877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1976631877
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3885185204
Short name T283
Test name
Test status
Simulation time 27451976 ps
CPU time 1.32 seconds
Started Jun 25 05:45:26 PM PDT 24
Finished Jun 25 05:45:29 PM PDT 24
Peak memory 207000 kb
Host smart-0913638a-be40-47d9-a5e2-79dea8d42183
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885185204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3885185204
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3625717518
Short name T1127
Test name
Test status
Simulation time 239899699 ps
CPU time 3.64 seconds
Started Jun 25 05:45:25 PM PDT 24
Finished Jun 25 05:45:30 PM PDT 24
Peak memory 215208 kb
Host smart-98f0bce3-c3b5-4042-b65e-ce62a5ab90df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625717518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3625717518
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.917066525
Short name T305
Test name
Test status
Simulation time 109218996 ps
CPU time 1.77 seconds
Started Jun 25 05:45:25 PM PDT 24
Finished Jun 25 05:45:28 PM PDT 24
Peak memory 215144 kb
Host smart-8d087d90-68d9-4113-88df-d84c797c351f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917066525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.917066525
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2478763296
Short name T1060
Test name
Test status
Simulation time 23002923 ps
CPU time 1.61 seconds
Started Jun 25 05:45:25 PM PDT 24
Finished Jun 25 05:45:28 PM PDT 24
Peak memory 215204 kb
Host smart-3ead12d0-6304-476d-972b-68eea946c5ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478763296 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2478763296
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.761887711
Short name T1048
Test name
Test status
Simulation time 14854222 ps
CPU time 0.92 seconds
Started Jun 25 05:45:25 PM PDT 24
Finished Jun 25 05:45:27 PM PDT 24
Peak memory 206972 kb
Host smart-32d55238-9877-4cba-8e86-0809e753a51c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761887711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.761887711
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1733971528
Short name T1057
Test name
Test status
Simulation time 14317776 ps
CPU time 0.92 seconds
Started Jun 25 05:45:26 PM PDT 24
Finished Jun 25 05:45:29 PM PDT 24
Peak memory 206980 kb
Host smart-4463f4ce-d79c-4151-a333-dfcd82c4ff98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733971528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1733971528
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3840306806
Short name T1059
Test name
Test status
Simulation time 33971691 ps
CPU time 1.02 seconds
Started Jun 25 05:45:25 PM PDT 24
Finished Jun 25 05:45:28 PM PDT 24
Peak memory 206976 kb
Host smart-76d8aaa5-b197-4cbb-9edd-d96e4be3869b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840306806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3840306806
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.139541105
Short name T1004
Test name
Test status
Simulation time 361300066 ps
CPU time 2.91 seconds
Started Jun 25 05:45:28 PM PDT 24
Finished Jun 25 05:45:32 PM PDT 24
Peak memory 215208 kb
Host smart-0d991fa2-735e-48d2-a0e0-0438eaa830e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139541105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.139541105
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2778234206
Short name T1104
Test name
Test status
Simulation time 357591681 ps
CPU time 2.54 seconds
Started Jun 25 05:45:26 PM PDT 24
Finished Jun 25 05:45:30 PM PDT 24
Peak memory 206960 kb
Host smart-52c82d8f-37f3-4df0-aa4f-824a42d29ad0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778234206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2778234206
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.928112970
Short name T1005
Test name
Test status
Simulation time 119152354 ps
CPU time 1.27 seconds
Started Jun 25 05:45:24 PM PDT 24
Finished Jun 25 05:45:26 PM PDT 24
Peak memory 215212 kb
Host smart-5f37b701-d048-4662-b23b-662043382002
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928112970 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.928112970
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.344468684
Short name T274
Test name
Test status
Simulation time 13549461 ps
CPU time 0.89 seconds
Started Jun 25 05:45:26 PM PDT 24
Finished Jun 25 05:45:28 PM PDT 24
Peak memory 206964 kb
Host smart-63742b54-9381-4390-9725-ea3e19610fbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344468684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.344468684
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1992306082
Short name T1014
Test name
Test status
Simulation time 36377747 ps
CPU time 0.79 seconds
Started Jun 25 05:45:25 PM PDT 24
Finished Jun 25 05:45:27 PM PDT 24
Peak memory 206732 kb
Host smart-efddcec4-6ac0-4ee4-bb5b-1fe16f655db3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992306082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1992306082
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.404129061
Short name T1111
Test name
Test status
Simulation time 67984269 ps
CPU time 1.06 seconds
Started Jun 25 05:45:26 PM PDT 24
Finished Jun 25 05:45:28 PM PDT 24
Peak memory 206968 kb
Host smart-4c84ac96-a45e-4814-bda8-f32221a87a66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404129061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_ou
tstanding.404129061
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1731338520
Short name T1123
Test name
Test status
Simulation time 55685695 ps
CPU time 2.28 seconds
Started Jun 25 05:45:25 PM PDT 24
Finished Jun 25 05:45:28 PM PDT 24
Peak memory 215236 kb
Host smart-4bac8dc4-020c-4a7c-b3b2-c4b99213ea69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731338520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1731338520
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.742815726
Short name T306
Test name
Test status
Simulation time 95649169 ps
CPU time 2.5 seconds
Started Jun 25 05:45:28 PM PDT 24
Finished Jun 25 05:45:32 PM PDT 24
Peak memory 206896 kb
Host smart-73ad20fa-61fb-457f-b541-ba650f7c6841
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742815726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.742815726
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.4078879298
Short name T1019
Test name
Test status
Simulation time 39910418 ps
CPU time 1.28 seconds
Started Jun 25 05:45:33 PM PDT 24
Finished Jun 25 05:45:36 PM PDT 24
Peak memory 215220 kb
Host smart-38543902-bb05-465f-8a48-00195859fe52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078879298 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.4078879298
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2413339056
Short name T1120
Test name
Test status
Simulation time 48584205 ps
CPU time 0.94 seconds
Started Jun 25 05:45:27 PM PDT 24
Finished Jun 25 05:45:29 PM PDT 24
Peak memory 206960 kb
Host smart-05073dfa-3843-4f7e-9355-e935f721f92f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413339056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2413339056
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3290670832
Short name T1087
Test name
Test status
Simulation time 70399434 ps
CPU time 0.9 seconds
Started Jun 25 05:45:24 PM PDT 24
Finished Jun 25 05:45:26 PM PDT 24
Peak memory 206888 kb
Host smart-9e99dc5f-2bc1-4388-9361-73fbeef15835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290670832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3290670832
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2740435866
Short name T1121
Test name
Test status
Simulation time 28870809 ps
CPU time 1.11 seconds
Started Jun 25 05:45:32 PM PDT 24
Finished Jun 25 05:45:34 PM PDT 24
Peak memory 206944 kb
Host smart-cfe6bc4a-a4b9-4fe8-9562-264a94676e2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740435866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2740435866
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2486523968
Short name T1006
Test name
Test status
Simulation time 154212359 ps
CPU time 2.29 seconds
Started Jun 25 05:45:24 PM PDT 24
Finished Jun 25 05:45:27 PM PDT 24
Peak memory 215248 kb
Host smart-d62475d7-17c5-4404-b977-099c8a2f32df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486523968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2486523968
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3959149558
Short name T296
Test name
Test status
Simulation time 1022490882 ps
CPU time 4.91 seconds
Started Jun 25 05:45:30 PM PDT 24
Finished Jun 25 05:45:36 PM PDT 24
Peak memory 215160 kb
Host smart-1e11f2da-6b36-45b0-80e3-67b0436dfe59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959149558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3959149558
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.638273871
Short name T996
Test name
Test status
Simulation time 24590761 ps
CPU time 1.2 seconds
Started Jun 25 05:45:32 PM PDT 24
Finished Jun 25 05:45:34 PM PDT 24
Peak memory 215372 kb
Host smart-1cdfcf45-d47d-49a4-8281-58f1ea7696db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638273871 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.638273871
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3175887807
Short name T277
Test name
Test status
Simulation time 12221648 ps
CPU time 0.88 seconds
Started Jun 25 05:45:33 PM PDT 24
Finished Jun 25 05:45:35 PM PDT 24
Peak memory 206972 kb
Host smart-9d9e1f40-c93f-4d24-821b-8ecdc6a5c01b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175887807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3175887807
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2446781025
Short name T993
Test name
Test status
Simulation time 29549754 ps
CPU time 0.97 seconds
Started Jun 25 05:45:34 PM PDT 24
Finished Jun 25 05:45:36 PM PDT 24
Peak memory 206888 kb
Host smart-a7d789e9-46a6-4fa9-ab41-2cdd2167d81c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446781025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2446781025
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.736464761
Short name T282
Test name
Test status
Simulation time 16556161 ps
CPU time 0.93 seconds
Started Jun 25 05:45:32 PM PDT 24
Finished Jun 25 05:45:34 PM PDT 24
Peak memory 207084 kb
Host smart-f476d4fe-df16-401e-880e-ed5c941aef13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736464761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.736464761
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.180442734
Short name T1108
Test name
Test status
Simulation time 642299939 ps
CPU time 2.01 seconds
Started Jun 25 05:45:36 PM PDT 24
Finished Jun 25 05:45:38 PM PDT 24
Peak memory 215224 kb
Host smart-51552016-7e27-4456-809a-87e1be67792e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180442734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.180442734
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2748991677
Short name T1117
Test name
Test status
Simulation time 2419369427 ps
CPU time 4.01 seconds
Started Jun 25 05:45:32 PM PDT 24
Finished Jun 25 05:45:37 PM PDT 24
Peak memory 207072 kb
Host smart-617d43f9-6690-46a1-8df2-1d832998ca1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748991677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2748991677
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1178604546
Short name T1073
Test name
Test status
Simulation time 23047018 ps
CPU time 1.4 seconds
Started Jun 25 05:45:34 PM PDT 24
Finished Jun 25 05:45:36 PM PDT 24
Peak memory 215360 kb
Host smart-4bf33f7d-9de5-492e-89a1-d06a579d0edc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178604546 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1178604546
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2817654104
Short name T1102
Test name
Test status
Simulation time 51966685 ps
CPU time 0.99 seconds
Started Jun 25 05:45:35 PM PDT 24
Finished Jun 25 05:45:37 PM PDT 24
Peak memory 206956 kb
Host smart-532b9c91-5fb4-4595-ab4e-2c3afed79c2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817654104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2817654104
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3598188920
Short name T1075
Test name
Test status
Simulation time 47091673 ps
CPU time 0.83 seconds
Started Jun 25 05:45:32 PM PDT 24
Finished Jun 25 05:45:34 PM PDT 24
Peak memory 207220 kb
Host smart-ea1a1f9b-13b0-493e-9392-6152d7abb6cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598188920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3598188920
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2625732958
Short name T285
Test name
Test status
Simulation time 52751602 ps
CPU time 1.37 seconds
Started Jun 25 05:45:35 PM PDT 24
Finished Jun 25 05:45:37 PM PDT 24
Peak memory 206964 kb
Host smart-02f497ff-7da9-4491-bb4c-7bf201cd84d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625732958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2625732958
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3992805567
Short name T1053
Test name
Test status
Simulation time 24102645 ps
CPU time 1.74 seconds
Started Jun 25 05:45:34 PM PDT 24
Finished Jun 25 05:45:37 PM PDT 24
Peak memory 215280 kb
Host smart-6e8aafe3-2420-465b-8c0a-085e2fd6b76e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992805567 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3992805567
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2987997377
Short name T1069
Test name
Test status
Simulation time 190226342 ps
CPU time 2.08 seconds
Started Jun 25 05:45:34 PM PDT 24
Finished Jun 25 05:45:37 PM PDT 24
Peak memory 207172 kb
Host smart-3dcd3474-5a2f-4298-bae9-93bfdbd1f3ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987997377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2987997377
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1060623548
Short name T1027
Test name
Test status
Simulation time 40097624 ps
CPU time 1.14 seconds
Started Jun 25 05:44:48 PM PDT 24
Finished Jun 25 05:44:49 PM PDT 24
Peak memory 206960 kb
Host smart-f5b8d61c-a8e6-45ed-8351-71fc902eaf2e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060623548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1060623548
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.18160916
Short name T1013
Test name
Test status
Simulation time 285504418 ps
CPU time 1.92 seconds
Started Jun 25 05:44:47 PM PDT 24
Finished Jun 25 05:44:49 PM PDT 24
Peak memory 207032 kb
Host smart-ccb44195-98d1-4328-8f5e-424392d588c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18160916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.18160916
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4236463101
Short name T1071
Test name
Test status
Simulation time 306691195 ps
CPU time 1.21 seconds
Started Jun 25 05:44:46 PM PDT 24
Finished Jun 25 05:44:48 PM PDT 24
Peak memory 215288 kb
Host smart-af2a4bd1-e861-4d04-830d-2475bd0d0674
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236463101 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.4236463101
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1872639584
Short name T1078
Test name
Test status
Simulation time 43214904 ps
CPU time 0.86 seconds
Started Jun 25 05:44:44 PM PDT 24
Finished Jun 25 05:44:46 PM PDT 24
Peak memory 206964 kb
Host smart-b365b605-4719-4774-84d8-9f1dc33fe3b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872639584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1872639584
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.4228729347
Short name T1086
Test name
Test status
Simulation time 35083824 ps
CPU time 0.82 seconds
Started Jun 25 05:44:37 PM PDT 24
Finished Jun 25 05:44:39 PM PDT 24
Peak memory 206740 kb
Host smart-3b2705f0-9ee2-4706-bb1d-37e3ad9c7b7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228729347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.4228729347
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3258479796
Short name T1081
Test name
Test status
Simulation time 134493172 ps
CPU time 1.51 seconds
Started Jun 25 05:44:47 PM PDT 24
Finished Jun 25 05:44:49 PM PDT 24
Peak memory 206936 kb
Host smart-2e40fae7-ef75-4604-a49a-9bec92ab6dd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258479796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3258479796
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.304347322
Short name T1034
Test name
Test status
Simulation time 28432336 ps
CPU time 2.16 seconds
Started Jun 25 05:44:38 PM PDT 24
Finished Jun 25 05:44:41 PM PDT 24
Peak memory 219256 kb
Host smart-0ea36320-fd77-4218-a5ca-f11a71a0d164
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304347322 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.304347322
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3406843594
Short name T1065
Test name
Test status
Simulation time 170980500 ps
CPU time 1.71 seconds
Started Jun 25 05:44:38 PM PDT 24
Finished Jun 25 05:44:41 PM PDT 24
Peak memory 207136 kb
Host smart-171c77ae-4fec-414d-b6e7-e1409e3bb2fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406843594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3406843594
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1621498419
Short name T1015
Test name
Test status
Simulation time 46428772 ps
CPU time 0.87 seconds
Started Jun 25 05:45:32 PM PDT 24
Finished Jun 25 05:45:34 PM PDT 24
Peak memory 206884 kb
Host smart-0260f74b-d404-4aaf-a1e5-9572f2d91382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621498419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1621498419
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.4161962275
Short name T1080
Test name
Test status
Simulation time 29785123 ps
CPU time 0.93 seconds
Started Jun 25 05:45:33 PM PDT 24
Finished Jun 25 05:45:34 PM PDT 24
Peak memory 206840 kb
Host smart-8b3203f1-295d-4efd-9345-025b2eed76b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161962275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.4161962275
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3241840270
Short name T1097
Test name
Test status
Simulation time 13669153 ps
CPU time 0.85 seconds
Started Jun 25 05:45:34 PM PDT 24
Finished Jun 25 05:45:36 PM PDT 24
Peak memory 206916 kb
Host smart-49c20a03-b541-4a72-873f-e23bf38709a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241840270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3241840270
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1266894436
Short name T1010
Test name
Test status
Simulation time 37967163 ps
CPU time 0.8 seconds
Started Jun 25 05:45:34 PM PDT 24
Finished Jun 25 05:45:35 PM PDT 24
Peak memory 206716 kb
Host smart-67021127-b0f4-4332-8997-c61665388c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266894436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1266894436
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3176158944
Short name T1093
Test name
Test status
Simulation time 13594548 ps
CPU time 0.91 seconds
Started Jun 25 05:45:35 PM PDT 24
Finished Jun 25 05:45:37 PM PDT 24
Peak memory 206900 kb
Host smart-4ed6f8c0-b0cd-40eb-9e79-1987b9cbda4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176158944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3176158944
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3866307153
Short name T1074
Test name
Test status
Simulation time 12844485 ps
CPU time 0.96 seconds
Started Jun 25 05:45:46 PM PDT 24
Finished Jun 25 05:45:48 PM PDT 24
Peak memory 206596 kb
Host smart-f483e14f-09c6-46c0-a20a-7e6267b87cdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866307153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3866307153
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.4049198415
Short name T995
Test name
Test status
Simulation time 17633463 ps
CPU time 1.03 seconds
Started Jun 25 05:45:45 PM PDT 24
Finished Jun 25 05:45:47 PM PDT 24
Peak memory 206876 kb
Host smart-b4a1e1b4-907c-4731-b0a4-c1807062be5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049198415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.4049198415
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3534613851
Short name T1056
Test name
Test status
Simulation time 43579578 ps
CPU time 0.83 seconds
Started Jun 25 05:45:43 PM PDT 24
Finished Jun 25 05:45:44 PM PDT 24
Peak memory 206676 kb
Host smart-ccf92405-f44d-4360-b364-b72ae656c7f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534613851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3534613851
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.4221331577
Short name T1031
Test name
Test status
Simulation time 16035682 ps
CPU time 0.93 seconds
Started Jun 25 05:45:44 PM PDT 24
Finished Jun 25 05:45:46 PM PDT 24
Peak memory 206896 kb
Host smart-863f604c-2bd0-48bc-bd2b-0e46af701628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221331577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.4221331577
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3680042567
Short name T1077
Test name
Test status
Simulation time 56848617 ps
CPU time 0.84 seconds
Started Jun 25 05:45:41 PM PDT 24
Finished Jun 25 05:45:43 PM PDT 24
Peak memory 206716 kb
Host smart-7a6e422d-a8c7-484c-bb21-938571e06d6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680042567 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3680042567
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1288436074
Short name T1024
Test name
Test status
Simulation time 50331324 ps
CPU time 1.18 seconds
Started Jun 25 05:44:47 PM PDT 24
Finished Jun 25 05:44:49 PM PDT 24
Peak memory 206976 kb
Host smart-6c1f9395-b1d6-439e-96db-730f9c91427b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288436074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1288436074
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3427079072
Short name T1107
Test name
Test status
Simulation time 644959512 ps
CPU time 5.15 seconds
Started Jun 25 05:44:46 PM PDT 24
Finished Jun 25 05:44:51 PM PDT 24
Peak memory 206984 kb
Host smart-dacf9e17-e271-4913-afc5-12d801dc7661
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427079072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3427079072
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3782618615
Short name T276
Test name
Test status
Simulation time 58187674 ps
CPU time 0.96 seconds
Started Jun 25 05:44:47 PM PDT 24
Finished Jun 25 05:44:49 PM PDT 24
Peak memory 206876 kb
Host smart-c2655505-26a5-430d-b5dc-c60602c60523
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782618615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3782618615
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2778561288
Short name T1039
Test name
Test status
Simulation time 30181927 ps
CPU time 1.09 seconds
Started Jun 25 05:44:47 PM PDT 24
Finished Jun 25 05:44:49 PM PDT 24
Peak memory 215148 kb
Host smart-047f543d-5ce6-48a4-a32a-251b394d9b9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778561288 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2778561288
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.4138394416
Short name T1028
Test name
Test status
Simulation time 37763439 ps
CPU time 0.84 seconds
Started Jun 25 05:44:45 PM PDT 24
Finished Jun 25 05:44:47 PM PDT 24
Peak memory 206976 kb
Host smart-06f29d6a-ed9a-452f-970e-76afc775dbac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138394416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.4138394416
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1557782711
Short name T1105
Test name
Test status
Simulation time 15468506 ps
CPU time 0.9 seconds
Started Jun 25 05:44:45 PM PDT 24
Finished Jun 25 05:44:46 PM PDT 24
Peak memory 206836 kb
Host smart-1ce2338e-fc1c-47dd-8d0e-080cbfa0fca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557782711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1557782711
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2837550502
Short name T1098
Test name
Test status
Simulation time 23165060 ps
CPU time 0.98 seconds
Started Jun 25 05:44:46 PM PDT 24
Finished Jun 25 05:44:47 PM PDT 24
Peak memory 206768 kb
Host smart-9df24145-1322-41b3-b89b-2ed446e4f92b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837550502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2837550502
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.780554066
Short name T1100
Test name
Test status
Simulation time 314695090 ps
CPU time 3.2 seconds
Started Jun 25 05:44:48 PM PDT 24
Finished Jun 25 05:44:52 PM PDT 24
Peak memory 215376 kb
Host smart-caf29108-e2a4-4f2b-87ff-356da5906bb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780554066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.780554066
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.4161914942
Short name T307
Test name
Test status
Simulation time 54379773 ps
CPU time 1.75 seconds
Started Jun 25 05:44:45 PM PDT 24
Finished Jun 25 05:44:47 PM PDT 24
Peak memory 207216 kb
Host smart-7b4bb4b6-98e4-4ad1-8433-7bc7c3a37ca0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161914942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.4161914942
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.380807822
Short name T1114
Test name
Test status
Simulation time 150874678 ps
CPU time 1.03 seconds
Started Jun 25 05:45:45 PM PDT 24
Finished Jun 25 05:45:47 PM PDT 24
Peak memory 206820 kb
Host smart-a296c7c2-8792-424b-acd3-9a227fcd3e3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380807822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.380807822
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3648359839
Short name T1118
Test name
Test status
Simulation time 25280805 ps
CPU time 0.9 seconds
Started Jun 25 05:45:45 PM PDT 24
Finished Jun 25 05:45:47 PM PDT 24
Peak memory 206904 kb
Host smart-d20b40eb-2053-4c81-9cb6-aeee2253870d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648359839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3648359839
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2310065198
Short name T1095
Test name
Test status
Simulation time 41224584 ps
CPU time 0.84 seconds
Started Jun 25 05:45:42 PM PDT 24
Finished Jun 25 05:45:43 PM PDT 24
Peak memory 206828 kb
Host smart-e39c04e6-5a56-4763-8706-8a3df07a1cca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310065198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2310065198
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3046183004
Short name T1003
Test name
Test status
Simulation time 21634794 ps
CPU time 0.85 seconds
Started Jun 25 05:45:44 PM PDT 24
Finished Jun 25 05:45:46 PM PDT 24
Peak memory 206884 kb
Host smart-26d81ffa-9d22-4044-a2ac-c3f3ade15cd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046183004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3046183004
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1841696975
Short name T1041
Test name
Test status
Simulation time 35245859 ps
CPU time 0.89 seconds
Started Jun 25 05:45:45 PM PDT 24
Finished Jun 25 05:45:47 PM PDT 24
Peak memory 206824 kb
Host smart-e0830184-bf6b-4b4a-9831-4356cce5d1c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841696975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1841696975
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1495985016
Short name T1036
Test name
Test status
Simulation time 14387814 ps
CPU time 0.91 seconds
Started Jun 25 05:45:42 PM PDT 24
Finished Jun 25 05:45:44 PM PDT 24
Peak memory 206840 kb
Host smart-105b9897-542d-4f47-bde9-afcf596c13af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495985016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1495985016
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.54149149
Short name T1115
Test name
Test status
Simulation time 16701695 ps
CPU time 0.95 seconds
Started Jun 25 05:45:46 PM PDT 24
Finished Jun 25 05:45:48 PM PDT 24
Peak memory 206676 kb
Host smart-7999fcba-b3ab-4524-bcb5-9fb78b3f5519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54149149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.54149149
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3724988559
Short name T1017
Test name
Test status
Simulation time 14668333 ps
CPU time 0.85 seconds
Started Jun 25 05:45:44 PM PDT 24
Finished Jun 25 05:45:45 PM PDT 24
Peak memory 206856 kb
Host smart-cc08105b-9ad8-4d07-aae9-9ab98daa9bc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724988559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3724988559
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.136781292
Short name T1064
Test name
Test status
Simulation time 34263219 ps
CPU time 0.81 seconds
Started Jun 25 05:45:41 PM PDT 24
Finished Jun 25 05:45:43 PM PDT 24
Peak memory 206712 kb
Host smart-0b1d8ea9-e5ec-465b-a00d-c75ed76cf15e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136781292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.136781292
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1851727757
Short name T1068
Test name
Test status
Simulation time 14736309 ps
CPU time 0.94 seconds
Started Jun 25 05:45:43 PM PDT 24
Finished Jun 25 05:45:44 PM PDT 24
Peak memory 206836 kb
Host smart-839f5e8f-78bc-49fb-8af9-cde8c9f1c94a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851727757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1851727757
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3088562268
Short name T273
Test name
Test status
Simulation time 78367245 ps
CPU time 1.21 seconds
Started Jun 25 05:44:52 PM PDT 24
Finished Jun 25 05:44:54 PM PDT 24
Peak memory 206944 kb
Host smart-af9f3f71-3248-4bb1-a8c1-38a5920f0f41
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088562268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3088562268
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2295141248
Short name T280
Test name
Test status
Simulation time 266563890 ps
CPU time 6.33 seconds
Started Jun 25 05:44:53 PM PDT 24
Finished Jun 25 05:45:00 PM PDT 24
Peak memory 206948 kb
Host smart-fac9ebe5-a265-44a5-9d12-14fa2343bc21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295141248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2295141248
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3046597377
Short name T1032
Test name
Test status
Simulation time 88635425 ps
CPU time 1.01 seconds
Started Jun 25 05:44:54 PM PDT 24
Finished Jun 25 05:44:56 PM PDT 24
Peak memory 206876 kb
Host smart-861b15cf-bc18-4b86-8b71-760f5b39bc7e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046597377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3046597377
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3407564914
Short name T1023
Test name
Test status
Simulation time 50389426 ps
CPU time 1.82 seconds
Started Jun 25 05:44:55 PM PDT 24
Finished Jun 25 05:44:58 PM PDT 24
Peak memory 215252 kb
Host smart-b3cbdaf4-0d78-4b1e-b22f-17315f156867
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407564914 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3407564914
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.402137893
Short name T286
Test name
Test status
Simulation time 30741445 ps
CPU time 0.78 seconds
Started Jun 25 05:44:53 PM PDT 24
Finished Jun 25 05:44:54 PM PDT 24
Peak memory 206764 kb
Host smart-5dad5510-2075-4d95-9247-bf5e3239ab9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402137893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.402137893
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2718448220
Short name T999
Test name
Test status
Simulation time 47841926 ps
CPU time 0.85 seconds
Started Jun 25 05:44:56 PM PDT 24
Finished Jun 25 05:44:57 PM PDT 24
Peak memory 206872 kb
Host smart-5b7d5181-e5ef-4838-8c0c-ee1f7571c8d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718448220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2718448220
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2015557729
Short name T284
Test name
Test status
Simulation time 66575944 ps
CPU time 1.09 seconds
Started Jun 25 05:44:53 PM PDT 24
Finished Jun 25 05:44:55 PM PDT 24
Peak memory 207020 kb
Host smart-beb19a0b-856e-47d6-9b57-405db15f7b1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015557729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2015557729
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2502471961
Short name T1000
Test name
Test status
Simulation time 123430517 ps
CPU time 4.11 seconds
Started Jun 25 05:44:53 PM PDT 24
Finished Jun 25 05:44:57 PM PDT 24
Peak memory 215212 kb
Host smart-5ac5e1f4-23b0-4998-982e-ab0d25c3f3e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502471961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2502471961
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.796080156
Short name T302
Test name
Test status
Simulation time 511648447 ps
CPU time 2.98 seconds
Started Jun 25 05:44:56 PM PDT 24
Finished Jun 25 05:44:59 PM PDT 24
Peak memory 215188 kb
Host smart-ad47031d-61b8-41e0-a82e-2389131d4799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796080156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.796080156
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1094761338
Short name T1035
Test name
Test status
Simulation time 13068638 ps
CPU time 0.92 seconds
Started Jun 25 05:45:45 PM PDT 24
Finished Jun 25 05:45:47 PM PDT 24
Peak memory 206904 kb
Host smart-dfc491fb-d207-48c6-85ba-ee65744a78fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094761338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1094761338
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.643070106
Short name T1009
Test name
Test status
Simulation time 92432963 ps
CPU time 0.91 seconds
Started Jun 25 05:45:42 PM PDT 24
Finished Jun 25 05:45:44 PM PDT 24
Peak memory 206896 kb
Host smart-761274f5-f28a-40ae-855b-65bf54f08014
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643070106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.643070106
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3246277989
Short name T1055
Test name
Test status
Simulation time 70506370 ps
CPU time 0.93 seconds
Started Jun 25 05:45:46 PM PDT 24
Finished Jun 25 05:45:48 PM PDT 24
Peak memory 206828 kb
Host smart-407967a5-85a3-4d59-95ca-bbf008bb0b0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246277989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3246277989
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.470945469
Short name T1012
Test name
Test status
Simulation time 20917975 ps
CPU time 0.84 seconds
Started Jun 25 05:45:50 PM PDT 24
Finished Jun 25 05:45:51 PM PDT 24
Peak memory 206716 kb
Host smart-785d67a7-39b0-4a5b-88f1-444f206b805d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470945469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.470945469
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1447720144
Short name T1018
Test name
Test status
Simulation time 98109059 ps
CPU time 0.84 seconds
Started Jun 25 05:45:49 PM PDT 24
Finished Jun 25 05:45:51 PM PDT 24
Peak memory 206828 kb
Host smart-e4225b69-23c3-4dd5-99cb-83f36e230b2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447720144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1447720144
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3429719772
Short name T1082
Test name
Test status
Simulation time 15331790 ps
CPU time 0.92 seconds
Started Jun 25 05:45:52 PM PDT 24
Finished Jun 25 05:45:54 PM PDT 24
Peak memory 206912 kb
Host smart-3142c17b-e337-46d6-be27-743c5a44f5b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429719772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3429719772
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.79419266
Short name T1008
Test name
Test status
Simulation time 19776334 ps
CPU time 0.86 seconds
Started Jun 25 05:45:53 PM PDT 24
Finished Jun 25 05:45:55 PM PDT 24
Peak memory 206832 kb
Host smart-01186a8b-7ab0-42cd-8a60-9b79da8b005a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79419266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.79419266
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2064691471
Short name T1103
Test name
Test status
Simulation time 23666764 ps
CPU time 0.87 seconds
Started Jun 25 05:45:51 PM PDT 24
Finished Jun 25 05:45:53 PM PDT 24
Peak memory 206888 kb
Host smart-d82b1e1c-ccfd-49da-bddf-901c575e8979
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064691471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2064691471
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.660947028
Short name T1007
Test name
Test status
Simulation time 11921864 ps
CPU time 0.86 seconds
Started Jun 25 05:45:50 PM PDT 24
Finished Jun 25 05:45:52 PM PDT 24
Peak memory 206876 kb
Host smart-9610ca89-c3ae-4cf1-b6e7-f95c542faec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660947028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.660947028
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2103595171
Short name T1096
Test name
Test status
Simulation time 16598124 ps
CPU time 0.81 seconds
Started Jun 25 05:45:50 PM PDT 24
Finished Jun 25 05:45:52 PM PDT 24
Peak memory 206716 kb
Host smart-2754da07-6fff-4f02-b5a0-cde3bd64a615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103595171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2103595171
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3971142471
Short name T1002
Test name
Test status
Simulation time 301523925 ps
CPU time 1.54 seconds
Started Jun 25 05:44:59 PM PDT 24
Finished Jun 25 05:45:01 PM PDT 24
Peak memory 215212 kb
Host smart-8d8f8f09-d1b5-4fae-b3e7-cb2702651162
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971142471 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3971142471
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1219393153
Short name T998
Test name
Test status
Simulation time 25690533 ps
CPU time 1.11 seconds
Started Jun 25 05:45:02 PM PDT 24
Finished Jun 25 05:45:03 PM PDT 24
Peak memory 206944 kb
Host smart-add2c490-e36c-4c23-8792-aef1738ff277
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219393153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1219393153
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3758444338
Short name T1092
Test name
Test status
Simulation time 52227690 ps
CPU time 0.94 seconds
Started Jun 25 05:45:00 PM PDT 24
Finished Jun 25 05:45:01 PM PDT 24
Peak memory 206836 kb
Host smart-09fcf32a-882d-4a24-a759-50fd7357d465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758444338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3758444338
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3514134154
Short name T1051
Test name
Test status
Simulation time 356235303 ps
CPU time 1.45 seconds
Started Jun 25 05:45:01 PM PDT 24
Finished Jun 25 05:45:03 PM PDT 24
Peak memory 206984 kb
Host smart-879f6700-5b7a-47a8-bb67-622e2240c652
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514134154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3514134154
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.4076804145
Short name T1084
Test name
Test status
Simulation time 230801597 ps
CPU time 2.25 seconds
Started Jun 25 05:44:52 PM PDT 24
Finished Jun 25 05:44:55 PM PDT 24
Peak memory 223468 kb
Host smart-885e48b8-48ba-4a52-9753-27de99069197
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076804145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.4076804145
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1679880117
Short name T295
Test name
Test status
Simulation time 902502719 ps
CPU time 3.32 seconds
Started Jun 25 05:44:52 PM PDT 24
Finished Jun 25 05:44:56 PM PDT 24
Peak memory 215384 kb
Host smart-fafc3bc7-5426-4d39-aa4a-a3510cd57e3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679880117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1679880117
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2081895230
Short name T1054
Test name
Test status
Simulation time 71151192 ps
CPU time 1.1 seconds
Started Jun 25 05:45:16 PM PDT 24
Finished Jun 25 05:45:18 PM PDT 24
Peak memory 216484 kb
Host smart-280b6c0c-c48f-433d-a7db-f2f7b5f95858
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081895230 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2081895230
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2555582046
Short name T1046
Test name
Test status
Simulation time 14745942 ps
CPU time 0.99 seconds
Started Jun 25 05:45:02 PM PDT 24
Finished Jun 25 05:45:03 PM PDT 24
Peak memory 207116 kb
Host smart-5cac0a3d-556b-4593-8430-fdd6f1ffb90e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555582046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2555582046
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3551490775
Short name T1089
Test name
Test status
Simulation time 19457831 ps
CPU time 0.94 seconds
Started Jun 25 05:45:03 PM PDT 24
Finished Jun 25 05:45:04 PM PDT 24
Peak memory 206852 kb
Host smart-10b52b6c-eae6-40bb-8cc1-342846f269f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551490775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3551490775
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2196185587
Short name T1079
Test name
Test status
Simulation time 55331150 ps
CPU time 1.09 seconds
Started Jun 25 05:45:03 PM PDT 24
Finished Jun 25 05:45:04 PM PDT 24
Peak memory 206924 kb
Host smart-040fb51b-150e-49e3-b79f-7d4a758d770e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196185587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2196185587
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3641207019
Short name T1112
Test name
Test status
Simulation time 153790257 ps
CPU time 4.09 seconds
Started Jun 25 05:45:01 PM PDT 24
Finished Jun 25 05:45:05 PM PDT 24
Peak memory 215384 kb
Host smart-c2915d2b-499c-44ca-a592-2fdf4776b38d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641207019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3641207019
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3799991656
Short name T1016
Test name
Test status
Simulation time 428315776 ps
CPU time 2.5 seconds
Started Jun 25 05:45:03 PM PDT 24
Finished Jun 25 05:45:06 PM PDT 24
Peak memory 206940 kb
Host smart-d1460335-124f-4aa0-af43-2f4aae9e95cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799991656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3799991656
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2461524350
Short name T1026
Test name
Test status
Simulation time 18484333 ps
CPU time 1.13 seconds
Started Jun 25 05:45:17 PM PDT 24
Finished Jun 25 05:45:20 PM PDT 24
Peak memory 206956 kb
Host smart-2c23ace8-b669-41db-8318-c1c205b26ecd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461524350 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2461524350
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1011142079
Short name T1052
Test name
Test status
Simulation time 23873167 ps
CPU time 0.89 seconds
Started Jun 25 05:45:17 PM PDT 24
Finished Jun 25 05:45:19 PM PDT 24
Peak memory 206944 kb
Host smart-3c17670e-5f7f-414b-b83c-58436a8996f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011142079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1011142079
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3237112762
Short name T1094
Test name
Test status
Simulation time 16719049 ps
CPU time 0.88 seconds
Started Jun 25 05:45:16 PM PDT 24
Finished Jun 25 05:45:18 PM PDT 24
Peak memory 206888 kb
Host smart-600e4e0c-f6d4-496f-bc71-07762b16c391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237112762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3237112762
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2480138210
Short name T1122
Test name
Test status
Simulation time 40683859 ps
CPU time 1.05 seconds
Started Jun 25 05:45:20 PM PDT 24
Finished Jun 25 05:45:22 PM PDT 24
Peak memory 207048 kb
Host smart-c1c7d60d-c2f8-4ddb-963a-8de328413a32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480138210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2480138210
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2993625230
Short name T1076
Test name
Test status
Simulation time 97059522 ps
CPU time 2.83 seconds
Started Jun 25 05:45:18 PM PDT 24
Finished Jun 25 05:45:22 PM PDT 24
Peak memory 215220 kb
Host smart-a20cffe9-ed39-410e-a0ee-10c257577a2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993625230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2993625230
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.171625394
Short name T1090
Test name
Test status
Simulation time 128852028 ps
CPU time 2.53 seconds
Started Jun 25 05:45:17 PM PDT 24
Finished Jun 25 05:45:21 PM PDT 24
Peak memory 215152 kb
Host smart-01c66bd1-6bd1-4c9e-bb57-7a569e07089c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171625394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.171625394
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3057245610
Short name T1037
Test name
Test status
Simulation time 35177478 ps
CPU time 1.33 seconds
Started Jun 25 05:45:17 PM PDT 24
Finished Jun 25 05:45:20 PM PDT 24
Peak memory 215268 kb
Host smart-3cd0f8bc-cdf2-41ea-ae60-1a2a9d1c35c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057245610 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3057245610
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1931580219
Short name T1022
Test name
Test status
Simulation time 22429972 ps
CPU time 0.91 seconds
Started Jun 25 05:45:16 PM PDT 24
Finished Jun 25 05:45:18 PM PDT 24
Peak memory 206884 kb
Host smart-69908dc2-b5fc-4430-a7fa-8ca8b656f6f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931580219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1931580219
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1872814161
Short name T1063
Test name
Test status
Simulation time 151024467 ps
CPU time 0.82 seconds
Started Jun 25 05:45:16 PM PDT 24
Finished Jun 25 05:45:18 PM PDT 24
Peak memory 206716 kb
Host smart-4a184062-70ec-49c9-86cb-6805a8718239
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872814161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1872814161
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2233443952
Short name T281
Test name
Test status
Simulation time 59673652 ps
CPU time 1.08 seconds
Started Jun 25 05:45:15 PM PDT 24
Finished Jun 25 05:45:17 PM PDT 24
Peak memory 206896 kb
Host smart-174d3cce-079b-4111-bb65-6cc059ed9d92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233443952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2233443952
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2470688513
Short name T1001
Test name
Test status
Simulation time 116422073 ps
CPU time 2.65 seconds
Started Jun 25 05:45:17 PM PDT 24
Finished Jun 25 05:45:21 PM PDT 24
Peak memory 215208 kb
Host smart-ddf0ec2f-ca12-4910-9526-f414787b9bad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470688513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2470688513
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1311070682
Short name T297
Test name
Test status
Simulation time 152859554 ps
CPU time 2.29 seconds
Started Jun 25 05:45:18 PM PDT 24
Finished Jun 25 05:45:22 PM PDT 24
Peak memory 206952 kb
Host smart-761323e7-a660-4c11-b638-d75bdf2760dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311070682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1311070682
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2044661592
Short name T1058
Test name
Test status
Simulation time 207647823 ps
CPU time 1.16 seconds
Started Jun 25 05:45:19 PM PDT 24
Finished Jun 25 05:45:21 PM PDT 24
Peak memory 215248 kb
Host smart-0c08b791-048b-42da-87a5-cece8f3e5e29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044661592 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2044661592
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.929864434
Short name T1011
Test name
Test status
Simulation time 15057206 ps
CPU time 0.95 seconds
Started Jun 25 05:45:19 PM PDT 24
Finished Jun 25 05:45:21 PM PDT 24
Peak memory 206944 kb
Host smart-b4d8aeaa-0d3e-496c-98a6-4100318dcfea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929864434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.929864434
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.4098892980
Short name T1042
Test name
Test status
Simulation time 34179106 ps
CPU time 0.85 seconds
Started Jun 25 05:45:18 PM PDT 24
Finished Jun 25 05:45:20 PM PDT 24
Peak memory 206720 kb
Host smart-c7cf7455-c629-4a0d-bcbc-017f7ceb35f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098892980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.4098892980
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.339528770
Short name T1062
Test name
Test status
Simulation time 198749694 ps
CPU time 1.07 seconds
Started Jun 25 05:45:18 PM PDT 24
Finished Jun 25 05:45:21 PM PDT 24
Peak memory 206880 kb
Host smart-4f57b111-0e92-42c6-9056-308a789e336f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339528770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.339528770
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3323995118
Short name T997
Test name
Test status
Simulation time 105333622 ps
CPU time 3.11 seconds
Started Jun 25 05:45:17 PM PDT 24
Finished Jun 25 05:45:21 PM PDT 24
Peak memory 215240 kb
Host smart-b7bf4c6c-dd00-482c-81af-7dd9ee8fb18d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323995118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3323995118
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/default/0.edn_alert.2468571792
Short name T316
Test name
Test status
Simulation time 36397930 ps
CPU time 1.21 seconds
Started Jun 25 05:48:04 PM PDT 24
Finished Jun 25 05:48:07 PM PDT 24
Peak memory 219804 kb
Host smart-127063e6-4b20-4b80-9cfb-c3672cb1598b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468571792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2468571792
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.1263316102
Short name T724
Test name
Test status
Simulation time 44329669 ps
CPU time 0.89 seconds
Started Jun 25 05:48:03 PM PDT 24
Finished Jun 25 05:48:04 PM PDT 24
Peak memory 215220 kb
Host smart-eb919b13-4254-4360-abc0-70159b205a14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263316102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1263316102
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.3421258249
Short name T362
Test name
Test status
Simulation time 10984308 ps
CPU time 0.92 seconds
Started Jun 25 05:48:06 PM PDT 24
Finished Jun 25 05:48:08 PM PDT 24
Peak memory 216556 kb
Host smart-6c8b443e-2884-4b62-8756-eeb863e6454b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421258249 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3421258249
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3077982687
Short name T853
Test name
Test status
Simulation time 51926370 ps
CPU time 1.1 seconds
Started Jun 25 05:48:04 PM PDT 24
Finished Jun 25 05:48:06 PM PDT 24
Peak memory 218844 kb
Host smart-3a0100d0-0d55-4b2e-95e6-76cd3a8c8438
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077982687 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3077982687
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.2536476931
Short name T924
Test name
Test status
Simulation time 32506877 ps
CPU time 1.01 seconds
Started Jun 25 05:48:04 PM PDT 24
Finished Jun 25 05:48:06 PM PDT 24
Peak memory 223988 kb
Host smart-5a6a82c3-8cc2-4693-a6c7-b18ab668eaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536476931 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2536476931
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.3671200581
Short name T62
Test name
Test status
Simulation time 38229703 ps
CPU time 1.02 seconds
Started Jun 25 05:48:06 PM PDT 24
Finished Jun 25 05:48:08 PM PDT 24
Peak memory 224280 kb
Host smart-9b582152-3cb7-4d93-bfd6-68c1d767dab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671200581 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3671200581
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.764199807
Short name T313
Test name
Test status
Simulation time 39761274 ps
CPU time 0.99 seconds
Started Jun 25 05:48:02 PM PDT 24
Finished Jun 25 05:48:04 PM PDT 24
Peak memory 207476 kb
Host smart-6330592a-5278-4f3f-8b46-81f80c49c337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764199807 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.764199807
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.736689084
Short name T19
Test name
Test status
Simulation time 911004049 ps
CPU time 4.58 seconds
Started Jun 25 05:48:05 PM PDT 24
Finished Jun 25 05:48:10 PM PDT 24
Peak memory 235672 kb
Host smart-a3f6d708-63ca-41e8-8349-9ee0539e1e5f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736689084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.736689084
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.3930588019
Short name T817
Test name
Test status
Simulation time 20899591 ps
CPU time 0.9 seconds
Started Jun 25 05:48:03 PM PDT 24
Finished Jun 25 05:48:05 PM PDT 24
Peak memory 215616 kb
Host smart-8f8f2d18-96cd-405d-8e99-0b172282f242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930588019 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3930588019
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3636676441
Short name T243
Test name
Test status
Simulation time 103184736163 ps
CPU time 1754.96 seconds
Started Jun 25 05:48:06 PM PDT 24
Finished Jun 25 06:17:22 PM PDT 24
Peak memory 226088 kb
Host smart-f4c773e3-cfb2-4e24-8d39-ec5af1be20b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636676441 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3636676441
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.771091114
Short name T136
Test name
Test status
Simulation time 42994642 ps
CPU time 1.24 seconds
Started Jun 25 05:48:12 PM PDT 24
Finished Jun 25 05:48:14 PM PDT 24
Peak memory 218988 kb
Host smart-bdf22118-4117-418b-922f-2c4ded6a944f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771091114 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.771091114
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.2083726348
Short name T650
Test name
Test status
Simulation time 20597267 ps
CPU time 0.83 seconds
Started Jun 25 05:48:13 PM PDT 24
Finished Jun 25 05:48:15 PM PDT 24
Peak memory 207108 kb
Host smart-bb3f5416-95ba-4c3d-8469-8f406b53c1c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083726348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2083726348
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.886431860
Short name T174
Test name
Test status
Simulation time 27245711 ps
CPU time 0.82 seconds
Started Jun 25 05:48:12 PM PDT 24
Finished Jun 25 05:48:15 PM PDT 24
Peak memory 216600 kb
Host smart-b2dadbe1-c75d-4234-b7ea-beae25d2e925
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886431860 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.886431860
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.685092311
Short name T580
Test name
Test status
Simulation time 77264078 ps
CPU time 1.08 seconds
Started Jun 25 05:48:17 PM PDT 24
Finished Jun 25 05:48:19 PM PDT 24
Peak memory 217256 kb
Host smart-b0df87c8-9185-4114-a3a4-71eb56711605
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685092311 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_dis
able_auto_req_mode.685092311
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_intr.4014847046
Short name T618
Test name
Test status
Simulation time 21977516 ps
CPU time 1.14 seconds
Started Jun 25 05:48:15 PM PDT 24
Finished Jun 25 05:48:18 PM PDT 24
Peak memory 215864 kb
Host smart-ae3c99bf-8d61-4e10-ae2e-5fde608bb970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014847046 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.4014847046
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1342442775
Short name T66
Test name
Test status
Simulation time 233934168 ps
CPU time 4.58 seconds
Started Jun 25 05:48:15 PM PDT 24
Finished Jun 25 05:48:22 PM PDT 24
Peak memory 236096 kb
Host smart-fb521f2d-156a-497c-a05b-e9b1c5169565
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342442775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1342442775
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1620600962
Short name T358
Test name
Test status
Simulation time 27539858 ps
CPU time 1.14 seconds
Started Jun 25 05:48:06 PM PDT 24
Finished Jun 25 05:48:08 PM PDT 24
Peak memory 215692 kb
Host smart-267185bd-6196-456a-8db7-a73931597568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620600962 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1620600962
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1246384096
Short name T707
Test name
Test status
Simulation time 391601836 ps
CPU time 3.92 seconds
Started Jun 25 05:48:04 PM PDT 24
Finished Jun 25 05:48:09 PM PDT 24
Peak memory 217776 kb
Host smart-024e3180-f818-44f3-8371-c735c7094590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246384096 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1246384096
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.4250809682
Short name T244
Test name
Test status
Simulation time 303188003945 ps
CPU time 441.05 seconds
Started Jun 25 05:48:05 PM PDT 24
Finished Jun 25 05:55:27 PM PDT 24
Peak memory 224052 kb
Host smart-dc40084c-8b05-4edc-9f69-aabfcf8d7370
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250809682 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.4250809682
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3694767477
Short name T708
Test name
Test status
Simulation time 262754258 ps
CPU time 1.39 seconds
Started Jun 25 05:48:34 PM PDT 24
Finished Jun 25 05:48:36 PM PDT 24
Peak memory 220192 kb
Host smart-7b15b0d1-d868-483f-a3c2-ed10d98d897d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694767477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3694767477
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2061041798
Short name T459
Test name
Test status
Simulation time 20909395 ps
CPU time 1.06 seconds
Started Jun 25 05:48:29 PM PDT 24
Finished Jun 25 05:48:31 PM PDT 24
Peak memory 215472 kb
Host smart-6401c4a8-2880-4c19-851a-ed425c9ce7d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061041798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2061041798
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_err.1242915900
Short name T61
Test name
Test status
Simulation time 95727078 ps
CPU time 1.26 seconds
Started Jun 25 05:48:32 PM PDT 24
Finished Jun 25 05:48:35 PM PDT 24
Peak memory 225188 kb
Host smart-33a90892-a14e-4d32-8a7c-27487b367017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242915900 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1242915900
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2510357506
Short name T989
Test name
Test status
Simulation time 76753216 ps
CPU time 1.28 seconds
Started Jun 25 05:48:31 PM PDT 24
Finished Jun 25 05:48:34 PM PDT 24
Peak memory 219156 kb
Host smart-8f4b5ff6-3ed9-4ee7-9409-933615ad13cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510357506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2510357506
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.1392457111
Short name T25
Test name
Test status
Simulation time 177873341 ps
CPU time 0.96 seconds
Started Jun 25 05:48:31 PM PDT 24
Finished Jun 25 05:48:34 PM PDT 24
Peak memory 215440 kb
Host smart-c5ed44ae-773d-4efe-a498-86b4efca4c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392457111 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1392457111
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.801598946
Short name T400
Test name
Test status
Simulation time 162894199 ps
CPU time 3.63 seconds
Started Jun 25 05:48:30 PM PDT 24
Finished Jun 25 05:48:34 PM PDT 24
Peak memory 217824 kb
Host smart-02db6251-daa0-4e05-9f0d-f107933f37ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801598946 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.801598946
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.4057896487
Short name T48
Test name
Test status
Simulation time 34604742227 ps
CPU time 765.88 seconds
Started Jun 25 05:48:32 PM PDT 24
Finished Jun 25 06:01:19 PM PDT 24
Peak memory 218672 kb
Host smart-8ef15bcf-cfd5-43ce-963e-dc613946269d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057896487 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.4057896487
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.434169580
Short name T264
Test name
Test status
Simulation time 30591908 ps
CPU time 1.39 seconds
Started Jun 25 05:50:31 PM PDT 24
Finished Jun 25 05:50:34 PM PDT 24
Peak memory 220216 kb
Host smart-da5f9b89-1067-45fd-b2bd-2e3eb88cd6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434169580 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.434169580
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.362594339
Short name T382
Test name
Test status
Simulation time 44228950 ps
CPU time 1.58 seconds
Started Jun 25 05:50:23 PM PDT 24
Finished Jun 25 05:50:26 PM PDT 24
Peak memory 218684 kb
Host smart-041a13e3-3c7d-4bb6-8bc3-b2d60352e006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362594339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.362594339
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.2831668041
Short name T546
Test name
Test status
Simulation time 29063121 ps
CPU time 1.33 seconds
Started Jun 25 05:50:32 PM PDT 24
Finished Jun 25 05:50:36 PM PDT 24
Peak memory 219428 kb
Host smart-14ec5561-68cf-431d-aa9a-785a747460f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831668041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.2831668041
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.1770931202
Short name T952
Test name
Test status
Simulation time 42944364 ps
CPU time 1.66 seconds
Started Jun 25 05:50:29 PM PDT 24
Finished Jun 25 05:50:32 PM PDT 24
Peak memory 218008 kb
Host smart-f4334704-964e-44d0-85e6-a68ef6a55bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770931202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1770931202
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.1615838641
Short name T314
Test name
Test status
Simulation time 26722244 ps
CPU time 1.16 seconds
Started Jun 25 05:50:32 PM PDT 24
Finished Jun 25 05:50:36 PM PDT 24
Peak memory 218904 kb
Host smart-794f99a2-9ecf-4428-9614-1bf96ef0b43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615838641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.1615838641
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.3919256546
Short name T799
Test name
Test status
Simulation time 39382484 ps
CPU time 1.24 seconds
Started Jun 25 05:50:31 PM PDT 24
Finished Jun 25 05:50:34 PM PDT 24
Peak memory 220248 kb
Host smart-2d6f9ccc-b728-4bf2-8323-fd12320e6c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919256546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3919256546
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.2153370253
Short name T141
Test name
Test status
Simulation time 65546715 ps
CPU time 1.35 seconds
Started Jun 25 05:50:29 PM PDT 24
Finished Jun 25 05:50:32 PM PDT 24
Peak memory 215988 kb
Host smart-dc70bbc3-fbc2-4b97-a50e-0c15b94efbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153370253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.2153370253
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/104.edn_alert.1446404855
Short name T986
Test name
Test status
Simulation time 35009744 ps
CPU time 1.25 seconds
Started Jun 25 05:50:29 PM PDT 24
Finished Jun 25 05:50:32 PM PDT 24
Peak memory 215892 kb
Host smart-27236cdb-b11b-4ff4-9123-a8fc9922151e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446404855 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.1446404855
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.3676424343
Short name T390
Test name
Test status
Simulation time 33982198 ps
CPU time 1.28 seconds
Started Jun 25 05:50:32 PM PDT 24
Finished Jun 25 05:50:36 PM PDT 24
Peak memory 217632 kb
Host smart-fda02389-5980-467e-9c87-a0675db1dd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676424343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3676424343
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.920798876
Short name T299
Test name
Test status
Simulation time 25769242 ps
CPU time 1.28 seconds
Started Jun 25 05:50:29 PM PDT 24
Finished Jun 25 05:50:32 PM PDT 24
Peak memory 220876 kb
Host smart-63b9991b-e6c6-4faf-9064-1fa279e39282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920798876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.920798876
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.869531298
Short name T408
Test name
Test status
Simulation time 49574980 ps
CPU time 1.77 seconds
Started Jun 25 05:50:31 PM PDT 24
Finished Jun 25 05:50:35 PM PDT 24
Peak memory 218984 kb
Host smart-09d05cc3-b91e-45cc-aff4-1d17976e9e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869531298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.869531298
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.781893083
Short name T514
Test name
Test status
Simulation time 112000460 ps
CPU time 1.13 seconds
Started Jun 25 05:50:31 PM PDT 24
Finished Jun 25 05:50:35 PM PDT 24
Peak memory 219748 kb
Host smart-ce7aff71-ffac-41d2-925d-378c620cd366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781893083 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.781893083
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.1279603339
Short name T564
Test name
Test status
Simulation time 53252088 ps
CPU time 1.34 seconds
Started Jun 25 05:50:32 PM PDT 24
Finished Jun 25 05:50:35 PM PDT 24
Peak memory 218820 kb
Host smart-e5c3407f-bc52-4c7b-a37c-c6a9cca6a7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279603339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1279603339
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.3876568729
Short name T290
Test name
Test status
Simulation time 84525360 ps
CPU time 1.29 seconds
Started Jun 25 05:50:32 PM PDT 24
Finished Jun 25 05:50:35 PM PDT 24
Peak memory 220876 kb
Host smart-1e3f5d8b-2788-4704-ae6d-45c4b2087c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876568729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.3876568729
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.736923754
Short name T765
Test name
Test status
Simulation time 21937222 ps
CPU time 1.09 seconds
Started Jun 25 05:50:33 PM PDT 24
Finished Jun 25 05:50:36 PM PDT 24
Peak memory 217692 kb
Host smart-4c5bf162-2fc1-4467-bd9a-3de2e970ad97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736923754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.736923754
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2365206455
Short name T418
Test name
Test status
Simulation time 46914504 ps
CPU time 1.45 seconds
Started Jun 25 05:50:29 PM PDT 24
Finished Jun 25 05:50:32 PM PDT 24
Peak memory 217528 kb
Host smart-12a76830-e3f6-4922-b8a5-3db24b53d635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365206455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2365206455
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.1370266323
Short name T294
Test name
Test status
Simulation time 46950184 ps
CPU time 1.39 seconds
Started Jun 25 05:50:29 PM PDT 24
Finished Jun 25 05:50:32 PM PDT 24
Peak memory 220424 kb
Host smart-9fb73b8d-8bbe-4549-818f-ceb93dc2ab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370266323 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.1370266323
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.3527270061
Short name T804
Test name
Test status
Simulation time 35400303 ps
CPU time 1.7 seconds
Started Jun 25 05:50:29 PM PDT 24
Finished Jun 25 05:50:33 PM PDT 24
Peak memory 217808 kb
Host smart-83ec75df-d585-49b4-8c28-c800787bbe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527270061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3527270061
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.4012691031
Short name T534
Test name
Test status
Simulation time 143597440 ps
CPU time 1.2 seconds
Started Jun 25 05:48:37 PM PDT 24
Finished Jun 25 05:48:39 PM PDT 24
Peak memory 221076 kb
Host smart-b6d9860e-992e-49ca-b02f-15350422d104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012691031 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.4012691031
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.2230911332
Short name T228
Test name
Test status
Simulation time 39217661 ps
CPU time 0.91 seconds
Started Jun 25 05:48:41 PM PDT 24
Finished Jun 25 05:48:43 PM PDT 24
Peak memory 216604 kb
Host smart-6a7f91ba-1893-43e3-a2ad-2b2d82cb8efb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230911332 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2230911332
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3049532675
Short name T728
Test name
Test status
Simulation time 81738725 ps
CPU time 1.41 seconds
Started Jun 25 05:48:42 PM PDT 24
Finished Jun 25 05:48:44 PM PDT 24
Peak memory 217336 kb
Host smart-bb9e6707-f391-4533-a05a-e0f81c229654
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049532675 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3049532675
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1568562163
Short name T126
Test name
Test status
Simulation time 26668425 ps
CPU time 1.03 seconds
Started Jun 25 05:48:36 PM PDT 24
Finished Jun 25 05:48:37 PM PDT 24
Peak memory 220112 kb
Host smart-4fa0a8e7-394e-433d-a044-671853c27015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568562163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1568562163
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2003124646
Short name T498
Test name
Test status
Simulation time 116662807 ps
CPU time 1.19 seconds
Started Jun 25 05:48:30 PM PDT 24
Finished Jun 25 05:48:32 PM PDT 24
Peak memory 217612 kb
Host smart-4eb6a0ff-1b5d-4c60-bbc3-72ad26f33089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003124646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2003124646
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.485579406
Short name T831
Test name
Test status
Simulation time 31900214 ps
CPU time 0.86 seconds
Started Jun 25 05:48:37 PM PDT 24
Finished Jun 25 05:48:39 PM PDT 24
Peak memory 215712 kb
Host smart-6e6d5a1d-fb54-4dc1-acee-8ff60d6bc766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485579406 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.485579406
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.698064470
Short name T830
Test name
Test status
Simulation time 31534715 ps
CPU time 0.92 seconds
Started Jun 25 05:48:32 PM PDT 24
Finished Jun 25 05:48:34 PM PDT 24
Peak memory 215648 kb
Host smart-6d3ff015-969d-4839-ac41-269eb2d0b177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698064470 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.698064470
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.332593885
Short name T104
Test name
Test status
Simulation time 315870545 ps
CPU time 2.3 seconds
Started Jun 25 05:48:29 PM PDT 24
Finished Jun 25 05:48:32 PM PDT 24
Peak memory 217540 kb
Host smart-e419b2ac-efb6-4363-80f7-5c1937505759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332593885 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.332593885
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/110.edn_alert.2877707827
Short name T945
Test name
Test status
Simulation time 26444509 ps
CPU time 1.21 seconds
Started Jun 25 05:50:31 PM PDT 24
Finished Jun 25 05:50:35 PM PDT 24
Peak memory 219060 kb
Host smart-a90bde2e-3ec1-4b11-84f6-5a4e21576264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877707827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.2877707827
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.837677376
Short name T950
Test name
Test status
Simulation time 32981587 ps
CPU time 1.06 seconds
Started Jun 25 05:50:30 PM PDT 24
Finished Jun 25 05:50:33 PM PDT 24
Peak memory 217632 kb
Host smart-3c870bb2-40e3-4978-ae9a-66c0183a5bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837677376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.837677376
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.3145353041
Short name T506
Test name
Test status
Simulation time 301057595 ps
CPU time 1.51 seconds
Started Jun 25 05:50:30 PM PDT 24
Finished Jun 25 05:50:34 PM PDT 24
Peak memory 222136 kb
Host smart-b50f87d8-6093-4574-ac98-eb62974c3b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145353041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.3145353041
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.4256946618
Short name T706
Test name
Test status
Simulation time 196547811 ps
CPU time 3.19 seconds
Started Jun 25 05:50:31 PM PDT 24
Finished Jun 25 05:50:36 PM PDT 24
Peak memory 220252 kb
Host smart-02d9ef62-87ee-4093-a02f-361312b42cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256946618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.4256946618
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.2453432247
Short name T841
Test name
Test status
Simulation time 26270480 ps
CPU time 1.22 seconds
Started Jun 25 05:50:30 PM PDT 24
Finished Jun 25 05:50:32 PM PDT 24
Peak memory 216056 kb
Host smart-86045fd7-334f-4268-b558-392e133c911f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453432247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.2453432247
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.3693041225
Short name T601
Test name
Test status
Simulation time 66284751 ps
CPU time 1.03 seconds
Started Jun 25 05:50:28 PM PDT 24
Finished Jun 25 05:50:31 PM PDT 24
Peak memory 217564 kb
Host smart-ded75807-d26c-465b-b219-b82f6ab22c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693041225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3693041225
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.4204112072
Short name T914
Test name
Test status
Simulation time 40751029 ps
CPU time 1.19 seconds
Started Jun 25 05:50:29 PM PDT 24
Finished Jun 25 05:50:32 PM PDT 24
Peak memory 220352 kb
Host smart-55ad1587-bacd-421b-9bdf-ef5b1073b10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204112072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.4204112072
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.481227949
Short name T667
Test name
Test status
Simulation time 60510254 ps
CPU time 1.37 seconds
Started Jun 25 05:50:29 PM PDT 24
Finished Jun 25 05:50:32 PM PDT 24
Peak memory 217952 kb
Host smart-d07d1315-a51f-4288-85c2-8dec4784dffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481227949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.481227949
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.3593855219
Short name T175
Test name
Test status
Simulation time 67954774 ps
CPU time 1.06 seconds
Started Jun 25 05:50:28 PM PDT 24
Finished Jun 25 05:50:31 PM PDT 24
Peak memory 220532 kb
Host smart-e971fe48-a195-4028-b378-18e9a876f34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593855219 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3593855219
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.164967986
Short name T940
Test name
Test status
Simulation time 61244377 ps
CPU time 1.12 seconds
Started Jun 25 05:50:30 PM PDT 24
Finished Jun 25 05:50:34 PM PDT 24
Peak memory 220316 kb
Host smart-e7c4dd41-ee1a-4b11-9e32-98175c36bae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164967986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.164967986
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.724760850
Short name T970
Test name
Test status
Simulation time 33129622 ps
CPU time 1.17 seconds
Started Jun 25 05:50:30 PM PDT 24
Finished Jun 25 05:50:33 PM PDT 24
Peak memory 219196 kb
Host smart-d95e8bec-61b3-444a-8041-6d4b6457c6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724760850 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.724760850
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.4258188612
Short name T850
Test name
Test status
Simulation time 45881258 ps
CPU time 1.29 seconds
Started Jun 25 05:50:32 PM PDT 24
Finished Jun 25 05:50:36 PM PDT 24
Peak memory 217860 kb
Host smart-0663582b-f317-4125-9472-0adc356d89b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258188612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.4258188612
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.1117310896
Short name T312
Test name
Test status
Simulation time 69557387 ps
CPU time 1.14 seconds
Started Jun 25 05:50:30 PM PDT 24
Finished Jun 25 05:50:32 PM PDT 24
Peak memory 219124 kb
Host smart-af9362e3-474a-437f-972c-c592cefe6536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117310896 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.1117310896
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/117.edn_alert.1386512503
Short name T107
Test name
Test status
Simulation time 22097344 ps
CPU time 1.25 seconds
Started Jun 25 05:50:32 PM PDT 24
Finished Jun 25 05:50:35 PM PDT 24
Peak memory 219048 kb
Host smart-bd9cbd0f-759d-4566-ad1c-560bdb21e9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386512503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1386512503
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.3530142614
Short name T340
Test name
Test status
Simulation time 54724006 ps
CPU time 2.13 seconds
Started Jun 25 05:50:31 PM PDT 24
Finished Jun 25 05:50:36 PM PDT 24
Peak memory 218904 kb
Host smart-220f8a77-f68c-461b-96a7-073ff8fddecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530142614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3530142614
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.4049445706
Short name T832
Test name
Test status
Simulation time 98102904 ps
CPU time 1.36 seconds
Started Jun 25 05:50:29 PM PDT 24
Finished Jun 25 05:50:32 PM PDT 24
Peak memory 216036 kb
Host smart-18b6bced-eb00-40c7-886b-b21aabbb6fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049445706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.4049445706
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.113610540
Short name T622
Test name
Test status
Simulation time 346898129 ps
CPU time 3.23 seconds
Started Jun 25 05:50:31 PM PDT 24
Finished Jun 25 05:50:37 PM PDT 24
Peak memory 220704 kb
Host smart-d155a16c-2a44-4df3-9db1-49b45d853a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113610540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.113610540
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.2218380854
Short name T657
Test name
Test status
Simulation time 36654673 ps
CPU time 1.13 seconds
Started Jun 25 05:50:32 PM PDT 24
Finished Jun 25 05:50:36 PM PDT 24
Peak memory 219764 kb
Host smart-72c1c2a1-932e-4eb5-b392-2756626ff39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218380854 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.2218380854
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.3253225110
Short name T902
Test name
Test status
Simulation time 93501819 ps
CPU time 1.11 seconds
Started Jun 25 05:50:30 PM PDT 24
Finished Jun 25 05:50:34 PM PDT 24
Peak memory 220492 kb
Host smart-b485952c-357d-483c-a1a4-53c27cd22c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253225110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3253225110
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.4287357233
Short name T637
Test name
Test status
Simulation time 35608031 ps
CPU time 1.1 seconds
Started Jun 25 05:48:39 PM PDT 24
Finished Jun 25 05:48:41 PM PDT 24
Peak memory 219292 kb
Host smart-12429051-044f-4cbc-adda-9665a2c3ba0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287357233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.4287357233
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.878822516
Short name T435
Test name
Test status
Simulation time 14805375 ps
CPU time 0.97 seconds
Started Jun 25 05:48:39 PM PDT 24
Finished Jun 25 05:48:41 PM PDT 24
Peak memory 215448 kb
Host smart-1e484f02-78c1-4b3d-a137-4d950398d29e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878822516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.878822516
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.4029191217
Short name T209
Test name
Test status
Simulation time 40134466 ps
CPU time 1.32 seconds
Started Jun 25 05:48:38 PM PDT 24
Finished Jun 25 05:48:41 PM PDT 24
Peak memory 217244 kb
Host smart-bd2c10f2-7f02-42b9-a840-b3c03ad5ac06
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029191217 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.4029191217
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.2640216194
Short name T471
Test name
Test status
Simulation time 34419671 ps
CPU time 1.13 seconds
Started Jun 25 05:48:38 PM PDT 24
Finished Jun 25 05:48:40 PM PDT 24
Peak memory 218904 kb
Host smart-6f6ee8de-1045-4f84-92eb-b2422b1fec65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640216194 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2640216194
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1066859918
Short name T819
Test name
Test status
Simulation time 41040712 ps
CPU time 1.54 seconds
Started Jun 25 05:48:37 PM PDT 24
Finished Jun 25 05:48:39 PM PDT 24
Peak memory 219080 kb
Host smart-069ea40c-e5d0-48c9-b48c-2a310a23c63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066859918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1066859918
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.713810809
Short name T714
Test name
Test status
Simulation time 22825289 ps
CPU time 1.25 seconds
Started Jun 25 05:48:39 PM PDT 24
Finished Jun 25 05:48:41 PM PDT 24
Peak memory 224344 kb
Host smart-8b43394d-c423-4158-918b-6d8a546dbae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713810809 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.713810809
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.3364959912
Short name T910
Test name
Test status
Simulation time 55180222 ps
CPU time 0.94 seconds
Started Jun 25 05:48:41 PM PDT 24
Finished Jun 25 05:48:42 PM PDT 24
Peak memory 215620 kb
Host smart-1441b7b9-229f-4574-af76-a049150c1e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364959912 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3364959912
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.379896680
Short name T671
Test name
Test status
Simulation time 174603308 ps
CPU time 1.33 seconds
Started Jun 25 05:48:38 PM PDT 24
Finished Jun 25 05:48:41 PM PDT 24
Peak memory 206944 kb
Host smart-0a1c873a-2e4e-4e72-8523-3406f555ef85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379896680 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.379896680
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1139172580
Short name T822
Test name
Test status
Simulation time 152447598313 ps
CPU time 2024.23 seconds
Started Jun 25 05:48:36 PM PDT 24
Finished Jun 25 06:22:21 PM PDT 24
Peak memory 230184 kb
Host smart-fcd50093-236e-425f-b22d-330c024afe3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139172580 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1139172580
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.2955392815
Short name T596
Test name
Test status
Simulation time 80104418 ps
CPU time 1.23 seconds
Started Jun 25 05:50:29 PM PDT 24
Finished Jun 25 05:50:32 PM PDT 24
Peak memory 217448 kb
Host smart-d328046a-1e92-423c-9fbb-42af12c008e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955392815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2955392815
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.634090180
Short name T916
Test name
Test status
Simulation time 22592823 ps
CPU time 1.17 seconds
Started Jun 25 05:50:33 PM PDT 24
Finished Jun 25 05:50:36 PM PDT 24
Peak memory 220148 kb
Host smart-0e3d14ee-9d22-4cd5-835b-0793eb61774e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634090180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.634090180
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.3719682062
Short name T906
Test name
Test status
Simulation time 85775156 ps
CPU time 1.47 seconds
Started Jun 25 05:50:30 PM PDT 24
Finished Jun 25 05:50:33 PM PDT 24
Peak memory 219040 kb
Host smart-5cc963a5-67c2-498e-bdc8-088304c21e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719682062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3719682062
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.3310296362
Short name T896
Test name
Test status
Simulation time 57121786 ps
CPU time 1.26 seconds
Started Jun 25 05:50:30 PM PDT 24
Finished Jun 25 05:50:34 PM PDT 24
Peak memory 218696 kb
Host smart-78bda1a0-5959-4bfb-afd1-cc9a35d421f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310296362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3310296362
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.2124863052
Short name T679
Test name
Test status
Simulation time 28365336 ps
CPU time 1.29 seconds
Started Jun 25 05:50:37 PM PDT 24
Finished Jun 25 05:50:39 PM PDT 24
Peak memory 220808 kb
Host smart-548b1013-59c5-4a5a-bfa1-a2f9f1211e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124863052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.2124863052
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.2240448226
Short name T698
Test name
Test status
Simulation time 117150742 ps
CPU time 1.37 seconds
Started Jun 25 05:50:42 PM PDT 24
Finished Jun 25 05:50:44 PM PDT 24
Peak memory 220400 kb
Host smart-7d42a708-3b8b-4230-816b-18a92681a4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240448226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2240448226
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.2959901172
Short name T773
Test name
Test status
Simulation time 90740086 ps
CPU time 1.41 seconds
Started Jun 25 05:50:37 PM PDT 24
Finished Jun 25 05:50:39 PM PDT 24
Peak memory 219036 kb
Host smart-91f6c017-d58b-4af4-9621-f41697ebbf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959901172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.2959901172
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.3866039740
Short name T475
Test name
Test status
Simulation time 42458977 ps
CPU time 1.46 seconds
Started Jun 25 05:50:39 PM PDT 24
Finished Jun 25 05:50:42 PM PDT 24
Peak memory 218764 kb
Host smart-ed3de479-8072-4992-b6b3-ea44c7a21ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866039740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3866039740
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.1631485457
Short name T101
Test name
Test status
Simulation time 25020674 ps
CPU time 1.17 seconds
Started Jun 25 05:50:41 PM PDT 24
Finished Jun 25 05:50:43 PM PDT 24
Peak memory 220084 kb
Host smart-5c723399-147c-4394-b86e-3a71b49c4622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631485457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.1631485457
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.15775867
Short name T616
Test name
Test status
Simulation time 44946885 ps
CPU time 1.73 seconds
Started Jun 25 05:50:38 PM PDT 24
Finished Jun 25 05:50:41 PM PDT 24
Peak memory 218912 kb
Host smart-f02c6abe-64a7-4830-a9c9-f7e65cb31248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15775867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.15775867
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.1007655354
Short name T411
Test name
Test status
Simulation time 23938926 ps
CPU time 1.21 seconds
Started Jun 25 05:50:42 PM PDT 24
Finished Jun 25 05:50:44 PM PDT 24
Peak memory 220036 kb
Host smart-a90c0acc-26d0-4993-b95f-52d2d3de5aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007655354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.1007655354
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/128.edn_alert.3561584931
Short name T122
Test name
Test status
Simulation time 109570928 ps
CPU time 1.26 seconds
Started Jun 25 05:50:35 PM PDT 24
Finished Jun 25 05:50:38 PM PDT 24
Peak memory 219952 kb
Host smart-6321fcdc-9169-4537-bc95-4deab962d5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561584931 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.3561584931
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.1388766407
Short name T731
Test name
Test status
Simulation time 98497034 ps
CPU time 1.5 seconds
Started Jun 25 05:50:41 PM PDT 24
Finished Jun 25 05:50:43 PM PDT 24
Peak memory 219272 kb
Host smart-c9263804-dd43-498d-8a72-4910a57037d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388766407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1388766407
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.2544104529
Short name T749
Test name
Test status
Simulation time 25302201 ps
CPU time 1.22 seconds
Started Jun 25 05:50:39 PM PDT 24
Finished Jun 25 05:50:41 PM PDT 24
Peak memory 219964 kb
Host smart-afc9447e-9cb8-4fd0-bc3f-ac3221390897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544104529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.2544104529
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.407358772
Short name T585
Test name
Test status
Simulation time 79077951 ps
CPU time 1.28 seconds
Started Jun 25 05:50:37 PM PDT 24
Finished Jun 25 05:50:39 PM PDT 24
Peak memory 219144 kb
Host smart-aa97e951-e5e7-46a2-abe3-c175163d3f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407358772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.407358772
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.496254748
Short name T905
Test name
Test status
Simulation time 27144001 ps
CPU time 1.17 seconds
Started Jun 25 05:48:37 PM PDT 24
Finished Jun 25 05:48:40 PM PDT 24
Peak memory 220076 kb
Host smart-b2b5846f-8a99-4c2b-85c2-5548d2e515be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496254748 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.496254748
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2021765252
Short name T603
Test name
Test status
Simulation time 18844130 ps
CPU time 0.98 seconds
Started Jun 25 05:48:39 PM PDT 24
Finished Jun 25 05:48:41 PM PDT 24
Peak memory 215236 kb
Host smart-4c4559cd-49d5-4e7e-8a61-e394b406f9e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021765252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2021765252
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.4224310101
Short name T194
Test name
Test status
Simulation time 32702374 ps
CPU time 0.8 seconds
Started Jun 25 05:48:37 PM PDT 24
Finished Jun 25 05:48:39 PM PDT 24
Peak memory 216564 kb
Host smart-d7f2e879-66d1-49d7-8db6-c01bb3b61a48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224310101 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.4224310101
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2879694185
Short name T292
Test name
Test status
Simulation time 16756048 ps
CPU time 1.03 seconds
Started Jun 25 05:48:44 PM PDT 24
Finished Jun 25 05:48:46 PM PDT 24
Peak memory 218736 kb
Host smart-74dfe0e6-5dbf-4269-995d-42e1b1b74f5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879694185 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2879694185
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1948471706
Short name T383
Test name
Test status
Simulation time 30325618 ps
CPU time 1.08 seconds
Started Jun 25 05:48:37 PM PDT 24
Finished Jun 25 05:48:40 PM PDT 24
Peak memory 219208 kb
Host smart-ff789c8e-4734-40c0-af98-caa83fe864c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948471706 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1948471706
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.4169703045
Short name T791
Test name
Test status
Simulation time 155197730 ps
CPU time 1.77 seconds
Started Jun 25 05:48:37 PM PDT 24
Finished Jun 25 05:48:39 PM PDT 24
Peak memory 220604 kb
Host smart-881e629c-139f-4bda-9601-a2fa021ec5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169703045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.4169703045
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.2375928062
Short name T480
Test name
Test status
Simulation time 23767677 ps
CPU time 0.9 seconds
Started Jun 25 05:48:43 PM PDT 24
Finished Jun 25 05:48:45 PM PDT 24
Peak memory 215624 kb
Host smart-7c8110f0-1416-4b04-80b6-80a2005f994d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375928062 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2375928062
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2009975727
Short name T716
Test name
Test status
Simulation time 295371780 ps
CPU time 2.25 seconds
Started Jun 25 05:48:37 PM PDT 24
Finished Jun 25 05:48:40 PM PDT 24
Peak memory 217764 kb
Host smart-dbec49b8-66d2-4af0-9223-49171df1a0be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009975727 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2009975727
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2496415893
Short name T948
Test name
Test status
Simulation time 429575264300 ps
CPU time 1344.16 seconds
Started Jun 25 05:48:38 PM PDT 24
Finished Jun 25 06:11:03 PM PDT 24
Peak memory 224308 kb
Host smart-3d76cf49-cc25-4a8d-8d19-3fd7ea686dc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496415893 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2496415893
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.4129198908
Short name T604
Test name
Test status
Simulation time 85647418 ps
CPU time 1.24 seconds
Started Jun 25 05:50:38 PM PDT 24
Finished Jun 25 05:50:41 PM PDT 24
Peak memory 219044 kb
Host smart-5a1f1706-e204-4381-b306-d6e38184c7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129198908 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.4129198908
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.1773349747
Short name T441
Test name
Test status
Simulation time 70361445 ps
CPU time 1.29 seconds
Started Jun 25 05:50:37 PM PDT 24
Finished Jun 25 05:50:40 PM PDT 24
Peak memory 218844 kb
Host smart-65dd178b-52db-41d2-9413-f4daa7fcbb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773349747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1773349747
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.3174221999
Short name T779
Test name
Test status
Simulation time 26363036 ps
CPU time 1.3 seconds
Started Jun 25 05:50:38 PM PDT 24
Finished Jun 25 05:50:40 PM PDT 24
Peak memory 219024 kb
Host smart-4ec1daee-fcc7-405a-a0cb-ff4e3e0fb64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174221999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.3174221999
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.1298359512
Short name T344
Test name
Test status
Simulation time 188827238 ps
CPU time 1.3 seconds
Started Jun 25 05:50:39 PM PDT 24
Finished Jun 25 05:50:41 PM PDT 24
Peak memory 219000 kb
Host smart-d8c59bdb-2c85-422c-892d-525e3b4a4313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298359512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1298359512
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.843031992
Short name T388
Test name
Test status
Simulation time 70084045 ps
CPU time 1.38 seconds
Started Jun 25 05:50:38 PM PDT 24
Finished Jun 25 05:50:41 PM PDT 24
Peak memory 218968 kb
Host smart-57ca8b99-998a-4af4-b317-2056e1f112c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843031992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.843031992
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.2830611705
Short name T409
Test name
Test status
Simulation time 192090633 ps
CPU time 1.1 seconds
Started Jun 25 05:50:39 PM PDT 24
Finished Jun 25 05:50:41 PM PDT 24
Peak memory 217624 kb
Host smart-6a72e80f-d6db-404f-8aaf-274f2a0e1bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830611705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2830611705
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2791239233
Short name T525
Test name
Test status
Simulation time 31621121 ps
CPU time 1.15 seconds
Started Jun 25 05:50:38 PM PDT 24
Finished Jun 25 05:50:40 PM PDT 24
Peak memory 217544 kb
Host smart-d4d6ae9b-a9a6-4835-afc8-2bb6c179ced7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791239233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2791239233
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.517787418
Short name T151
Test name
Test status
Simulation time 52438324 ps
CPU time 1.16 seconds
Started Jun 25 05:50:43 PM PDT 24
Finished Jun 25 05:50:45 PM PDT 24
Peak memory 221032 kb
Host smart-33053bbc-5ad5-4a40-86cf-b5d8681e4301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517787418 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.517787418
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.947375325
Short name T780
Test name
Test status
Simulation time 392392403 ps
CPU time 4.67 seconds
Started Jun 25 05:50:43 PM PDT 24
Finished Jun 25 05:50:48 PM PDT 24
Peak memory 220368 kb
Host smart-cb6b21e8-670e-48ed-9f4d-bbda65655d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947375325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.947375325
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.4237485315
Short name T783
Test name
Test status
Simulation time 25216491 ps
CPU time 1.1 seconds
Started Jun 25 05:50:42 PM PDT 24
Finished Jun 25 05:50:44 PM PDT 24
Peak memory 220184 kb
Host smart-0f7880d1-e022-4c51-a0ca-9d09c5c73dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237485315 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.4237485315
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/137.edn_alert.4045694572
Short name T736
Test name
Test status
Simulation time 33677737 ps
CPU time 1.43 seconds
Started Jun 25 05:50:41 PM PDT 24
Finished Jun 25 05:50:44 PM PDT 24
Peak memory 216028 kb
Host smart-c4f0a630-6afa-4fcb-8954-30b956236296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045694572 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.4045694572
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.387479061
Short name T614
Test name
Test status
Simulation time 171810157 ps
CPU time 1.7 seconds
Started Jun 25 05:50:41 PM PDT 24
Finished Jun 25 05:50:44 PM PDT 24
Peak memory 217756 kb
Host smart-d591f64c-f718-4d4e-b764-fa092e89260a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387479061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.387479061
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.3710316703
Short name T606
Test name
Test status
Simulation time 152220566 ps
CPU time 1.13 seconds
Started Jun 25 05:50:39 PM PDT 24
Finished Jun 25 05:50:41 PM PDT 24
Peak memory 218916 kb
Host smart-e29db20f-f958-4208-8957-9561cb20578c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710316703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3710316703
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.2578587435
Short name T55
Test name
Test status
Simulation time 76166604 ps
CPU time 1.62 seconds
Started Jun 25 05:50:37 PM PDT 24
Finished Jun 25 05:50:40 PM PDT 24
Peak memory 218744 kb
Host smart-18b28363-2d3a-4964-a2ff-c434081dbf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578587435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2578587435
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.4273080242
Short name T764
Test name
Test status
Simulation time 117465024 ps
CPU time 1.49 seconds
Started Jun 25 05:50:37 PM PDT 24
Finished Jun 25 05:50:40 PM PDT 24
Peak memory 220340 kb
Host smart-c7ffef66-4573-401b-9e11-6f876d13a3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273080242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.4273080242
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3190322126
Short name T396
Test name
Test status
Simulation time 50478203 ps
CPU time 1.24 seconds
Started Jun 25 05:48:38 PM PDT 24
Finished Jun 25 05:48:40 PM PDT 24
Peak memory 220012 kb
Host smart-25c5def8-f92f-41b3-86f3-eead602040ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190322126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3190322126
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.2775149874
Short name T846
Test name
Test status
Simulation time 24804806 ps
CPU time 0.92 seconds
Started Jun 25 05:48:38 PM PDT 24
Finished Jun 25 05:48:40 PM PDT 24
Peak memory 215152 kb
Host smart-90af6b8b-b0d4-4b50-8243-b51a8827b097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775149874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2775149874
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.769876052
Short name T369
Test name
Test status
Simulation time 40899156 ps
CPU time 1.31 seconds
Started Jun 25 05:48:37 PM PDT 24
Finished Jun 25 05:48:40 PM PDT 24
Peak memory 217240 kb
Host smart-e0c428be-3e1c-4e74-a4f5-a33328900d03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769876052 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.769876052
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3484526599
Short name T777
Test name
Test status
Simulation time 32495964 ps
CPU time 1.38 seconds
Started Jun 25 05:48:39 PM PDT 24
Finished Jun 25 05:48:41 PM PDT 24
Peak memory 225804 kb
Host smart-416e077d-4868-4004-9606-7d42be4ea062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484526599 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3484526599
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1602910054
Short name T959
Test name
Test status
Simulation time 46371731 ps
CPU time 1.35 seconds
Started Jun 25 05:48:36 PM PDT 24
Finished Jun 25 05:48:38 PM PDT 24
Peak memory 220364 kb
Host smart-ad447948-9f2a-4cde-9ab6-07284128b78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602910054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1602910054
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.913679687
Short name T58
Test name
Test status
Simulation time 26000403 ps
CPU time 1.06 seconds
Started Jun 25 05:48:38 PM PDT 24
Finished Jun 25 05:48:40 PM PDT 24
Peak memory 224296 kb
Host smart-e10c5cc3-2060-4403-9a4c-3b7b98421ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913679687 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.913679687
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.817489138
Short name T960
Test name
Test status
Simulation time 16353303 ps
CPU time 1 seconds
Started Jun 25 05:48:41 PM PDT 24
Finished Jun 25 05:48:43 PM PDT 24
Peak memory 215680 kb
Host smart-8a58e6f2-c6b9-4402-9807-680717f09502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817489138 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.817489138
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.443763221
Short name T378
Test name
Test status
Simulation time 741837653 ps
CPU time 3.66 seconds
Started Jun 25 05:48:43 PM PDT 24
Finished Jun 25 05:48:48 PM PDT 24
Peak memory 217536 kb
Host smart-65490659-a48c-4b05-b267-63b822e77ff4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443763221 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.443763221
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.385316675
Short name T578
Test name
Test status
Simulation time 453629155708 ps
CPU time 1634.4 seconds
Started Jun 25 05:48:38 PM PDT 24
Finished Jun 25 06:15:54 PM PDT 24
Peak memory 227308 kb
Host smart-b2b8d0b1-8d0c-4bac-b4a1-10643c4aa2f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385316675 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.385316675
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.297184835
Short name T121
Test name
Test status
Simulation time 37673547 ps
CPU time 1.13 seconds
Started Jun 25 05:50:36 PM PDT 24
Finished Jun 25 05:50:38 PM PDT 24
Peak memory 220512 kb
Host smart-de6cb98f-9b8a-4a47-ad17-fa504f6401ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297184835 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.297184835
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.3207791899
Short name T93
Test name
Test status
Simulation time 53339387 ps
CPU time 1.52 seconds
Started Jun 25 05:50:37 PM PDT 24
Finished Jun 25 05:50:40 PM PDT 24
Peak memory 218808 kb
Host smart-98e40a35-4c45-4956-a49a-92dd73e13145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207791899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3207791899
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.2426533342
Short name T793
Test name
Test status
Simulation time 75871579 ps
CPU time 1.18 seconds
Started Jun 25 05:50:43 PM PDT 24
Finished Jun 25 05:50:45 PM PDT 24
Peak memory 218976 kb
Host smart-57583e8e-e77d-4a46-bf7e-e61abcf8580f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426533342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2426533342
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.3158193149
Short name T648
Test name
Test status
Simulation time 77589852 ps
CPU time 1.67 seconds
Started Jun 25 05:50:35 PM PDT 24
Finished Jun 25 05:50:38 PM PDT 24
Peak memory 219136 kb
Host smart-94e5b175-77e8-41e6-a662-679e3e4e77e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158193149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3158193149
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.1783526116
Short name T158
Test name
Test status
Simulation time 88714848 ps
CPU time 1.29 seconds
Started Jun 25 05:50:45 PM PDT 24
Finished Jun 25 05:50:48 PM PDT 24
Peak memory 219012 kb
Host smart-97462195-310f-448e-9eac-477249d23de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783526116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.1783526116
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.1038154308
Short name T935
Test name
Test status
Simulation time 66561690 ps
CPU time 1.39 seconds
Started Jun 25 05:50:47 PM PDT 24
Finished Jun 25 05:50:50 PM PDT 24
Peak memory 218232 kb
Host smart-a0896c86-e3ec-4c79-8958-8261cb4cdc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038154308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1038154308
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.1784055909
Short name T198
Test name
Test status
Simulation time 82945923 ps
CPU time 1.17 seconds
Started Jun 25 05:50:47 PM PDT 24
Finished Jun 25 05:50:49 PM PDT 24
Peak memory 220796 kb
Host smart-a0d496c3-c929-4a48-aa1f-f4110197ce88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784055909 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1784055909
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.2413878761
Short name T91
Test name
Test status
Simulation time 71834908 ps
CPU time 1.15 seconds
Started Jun 25 05:50:48 PM PDT 24
Finished Jun 25 05:50:50 PM PDT 24
Peak memory 217540 kb
Host smart-71f3542a-61ae-4a3f-86ae-44a626374d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413878761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2413878761
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.391424789
Short name T897
Test name
Test status
Simulation time 115788633 ps
CPU time 1.09 seconds
Started Jun 25 05:50:44 PM PDT 24
Finished Jun 25 05:50:46 PM PDT 24
Peak memory 219968 kb
Host smart-31d563ab-1c88-4864-847d-771acb69da7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391424789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.391424789
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.1945853271
Short name T788
Test name
Test status
Simulation time 121611550 ps
CPU time 1.56 seconds
Started Jun 25 05:50:44 PM PDT 24
Finished Jun 25 05:50:47 PM PDT 24
Peak memory 219488 kb
Host smart-e8e53ef2-7d34-4e7d-8db1-b324a892cbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945853271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1945853271
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.1636016399
Short name T193
Test name
Test status
Simulation time 90925924 ps
CPU time 1.21 seconds
Started Jun 25 05:50:45 PM PDT 24
Finished Jun 25 05:50:48 PM PDT 24
Peak memory 220232 kb
Host smart-d3a9f55b-4f1e-4720-8657-5448ac825fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636016399 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.1636016399
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.1365788787
Short name T977
Test name
Test status
Simulation time 44068684 ps
CPU time 1.51 seconds
Started Jun 25 05:50:47 PM PDT 24
Finished Jun 25 05:50:50 PM PDT 24
Peak memory 215616 kb
Host smart-464ff420-f6e0-45a7-b42d-0c9a1020b9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365788787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1365788787
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.3679683378
Short name T513
Test name
Test status
Simulation time 25376065 ps
CPU time 1.32 seconds
Started Jun 25 05:50:44 PM PDT 24
Finished Jun 25 05:50:47 PM PDT 24
Peak memory 219760 kb
Host smart-4b34d983-3d47-4784-9d77-13c09d3f32bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679683378 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.3679683378
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2354945074
Short name T834
Test name
Test status
Simulation time 88793873 ps
CPU time 3.09 seconds
Started Jun 25 05:50:45 PM PDT 24
Finished Jun 25 05:50:49 PM PDT 24
Peak memory 215660 kb
Host smart-6fa0fd7f-307b-4e58-be64-10ef7d72db4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354945074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2354945074
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.281068965
Short name T455
Test name
Test status
Simulation time 37861424 ps
CPU time 1.19 seconds
Started Jun 25 05:50:43 PM PDT 24
Finished Jun 25 05:50:46 PM PDT 24
Peak memory 220304 kb
Host smart-82fc5494-4110-482b-b919-633552102aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281068965 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.281068965
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.2268927598
Short name T974
Test name
Test status
Simulation time 98095056 ps
CPU time 1.28 seconds
Started Jun 25 05:50:46 PM PDT 24
Finished Jun 25 05:50:49 PM PDT 24
Peak memory 217752 kb
Host smart-03d4cf2f-c9e8-49e0-90cb-b25af2e64ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268927598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2268927598
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.2557900319
Short name T857
Test name
Test status
Simulation time 42873938 ps
CPU time 1.17 seconds
Started Jun 25 05:50:47 PM PDT 24
Finished Jun 25 05:50:49 PM PDT 24
Peak memory 220144 kb
Host smart-91d15fb1-7625-49e0-b4ab-a81e1c5d9472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557900319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.2557900319
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.1785129183
Short name T763
Test name
Test status
Simulation time 44778103 ps
CPU time 1.28 seconds
Started Jun 25 05:50:44 PM PDT 24
Finished Jun 25 05:50:47 PM PDT 24
Peak memory 218840 kb
Host smart-f9413a1b-cb26-48b5-aa90-6a27f2197ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785129183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1785129183
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2291640427
Short name T502
Test name
Test status
Simulation time 86061528 ps
CPU time 1.2 seconds
Started Jun 25 05:48:47 PM PDT 24
Finished Jun 25 05:48:50 PM PDT 24
Peak memory 221292 kb
Host smart-12a3bad6-5d3a-4968-8d00-32789edfa692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291640427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2291640427
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2202750980
Short name T903
Test name
Test status
Simulation time 62166662 ps
CPU time 0.91 seconds
Started Jun 25 05:48:47 PM PDT 24
Finished Jun 25 05:48:50 PM PDT 24
Peak memory 207104 kb
Host smart-bac72366-cea4-440b-beb2-e309e6f6edb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202750980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2202750980
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3965021621
Short name T778
Test name
Test status
Simulation time 18431204 ps
CPU time 0.88 seconds
Started Jun 25 05:48:46 PM PDT 24
Finished Jun 25 05:48:48 PM PDT 24
Peak memory 216568 kb
Host smart-dba0f6b0-e925-4d85-9ade-8ae02155d978
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965021621 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3965021621
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2567974707
Short name T699
Test name
Test status
Simulation time 37787365 ps
CPU time 1.28 seconds
Started Jun 25 05:48:46 PM PDT 24
Finished Jun 25 05:48:48 PM PDT 24
Peak memory 217280 kb
Host smart-edd006ea-ca34-4121-bc79-8edd96dc03d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567974707 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2567974707
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.250511467
Short name T38
Test name
Test status
Simulation time 23313957 ps
CPU time 1.01 seconds
Started Jun 25 05:48:47 PM PDT 24
Finished Jun 25 05:48:50 PM PDT 24
Peak memory 219020 kb
Host smart-d1308f0a-a07d-49d4-a4db-7e592af819da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250511467 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.250511467
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.260982037
Short name T894
Test name
Test status
Simulation time 30380353 ps
CPU time 1.11 seconds
Started Jun 25 05:48:44 PM PDT 24
Finished Jun 25 05:48:45 PM PDT 24
Peak memory 218856 kb
Host smart-13bed424-f405-41c0-8602-7b1b148a5263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260982037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.260982037
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.3292846296
Short name T364
Test name
Test status
Simulation time 31530303 ps
CPU time 0.89 seconds
Started Jun 25 05:48:37 PM PDT 24
Finished Jun 25 05:48:39 PM PDT 24
Peak memory 215624 kb
Host smart-d1ccf450-298b-436d-a8f2-9200f1e3d04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292846296 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3292846296
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2006435093
Short name T691
Test name
Test status
Simulation time 171668391 ps
CPU time 3.68 seconds
Started Jun 25 05:48:38 PM PDT 24
Finished Jun 25 05:48:43 PM PDT 24
Peak memory 218816 kb
Host smart-fe1f388f-4bd4-4601-85a7-26ae81773666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006435093 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2006435093
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2314275163
Short name T240
Test name
Test status
Simulation time 17558063528 ps
CPU time 202.38 seconds
Started Jun 25 05:48:37 PM PDT 24
Finished Jun 25 05:52:01 PM PDT 24
Peak memory 218292 kb
Host smart-72816e86-25b0-4a62-a814-108ffb5fadad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314275163 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2314275163
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.42235753
Short name T318
Test name
Test status
Simulation time 31991479 ps
CPU time 1.34 seconds
Started Jun 25 05:50:47 PM PDT 24
Finished Jun 25 05:50:50 PM PDT 24
Peak memory 221344 kb
Host smart-cefeae66-57f9-453e-92f5-97a93304a501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42235753 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.42235753
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.3570041369
Short name T15
Test name
Test status
Simulation time 105325140 ps
CPU time 1.27 seconds
Started Jun 25 05:50:44 PM PDT 24
Finished Jun 25 05:50:47 PM PDT 24
Peak memory 220416 kb
Host smart-6760d808-faeb-466d-b4fd-d6b1f94591f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570041369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3570041369
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.3186673428
Short name T95
Test name
Test status
Simulation time 89227296 ps
CPU time 1.25 seconds
Started Jun 25 05:50:44 PM PDT 24
Finished Jun 25 05:50:46 PM PDT 24
Peak memory 218768 kb
Host smart-4017d5a7-e64b-43f3-a2e8-314d09b65373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186673428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.3186673428
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.3451985814
Short name T713
Test name
Test status
Simulation time 38336723 ps
CPU time 1.19 seconds
Started Jun 25 05:50:45 PM PDT 24
Finished Jun 25 05:50:48 PM PDT 24
Peak memory 220380 kb
Host smart-95060ac6-7491-43e5-800b-4c8e7b43cfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451985814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3451985814
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.4132452918
Short name T529
Test name
Test status
Simulation time 48473765 ps
CPU time 1.21 seconds
Started Jun 25 05:50:45 PM PDT 24
Finished Jun 25 05:50:48 PM PDT 24
Peak memory 218960 kb
Host smart-69fef97a-573a-4928-a319-ab8fa2259b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132452918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.4132452918
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.941624733
Short name T528
Test name
Test status
Simulation time 60088013 ps
CPU time 1.06 seconds
Started Jun 25 05:50:44 PM PDT 24
Finished Jun 25 05:50:46 PM PDT 24
Peak memory 217648 kb
Host smart-3d7bce27-1214-43ae-97f7-8836ef75f2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941624733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.941624733
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.1343539824
Short name T744
Test name
Test status
Simulation time 99723992 ps
CPU time 1.07 seconds
Started Jun 25 05:50:45 PM PDT 24
Finished Jun 25 05:50:48 PM PDT 24
Peak memory 219808 kb
Host smart-af501c64-bd5b-427e-93c2-98240db4a6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343539824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1343539824
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.3683529057
Short name T811
Test name
Test status
Simulation time 44221452 ps
CPU time 1.66 seconds
Started Jun 25 05:50:46 PM PDT 24
Finished Jun 25 05:50:49 PM PDT 24
Peak memory 218844 kb
Host smart-ad24df26-fd81-4f71-99db-15fe9287855f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683529057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3683529057
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.4278020589
Short name T412
Test name
Test status
Simulation time 42994508 ps
CPU time 1.23 seconds
Started Jun 25 05:50:46 PM PDT 24
Finished Jun 25 05:50:49 PM PDT 24
Peak memory 219900 kb
Host smart-473ac296-8615-4308-bc3f-7b2ec13e9f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278020589 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.4278020589
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.254916882
Short name T966
Test name
Test status
Simulation time 69525155 ps
CPU time 1.55 seconds
Started Jun 25 05:50:44 PM PDT 24
Finished Jun 25 05:50:46 PM PDT 24
Peak memory 220292 kb
Host smart-537020ab-7e23-43f4-821f-6d2dbe478e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254916882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.254916882
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.2636026737
Short name T743
Test name
Test status
Simulation time 29825907 ps
CPU time 1.29 seconds
Started Jun 25 05:50:47 PM PDT 24
Finished Jun 25 05:50:49 PM PDT 24
Peak memory 216000 kb
Host smart-6a014f96-9335-44b7-a4fb-454f605d7eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636026737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.2636026737
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.807528935
Short name T623
Test name
Test status
Simulation time 46417486 ps
CPU time 1.45 seconds
Started Jun 25 05:50:48 PM PDT 24
Finished Jun 25 05:50:51 PM PDT 24
Peak memory 218732 kb
Host smart-47155a27-c795-4cc9-ad33-825ee07cbb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807528935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.807528935
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.3131784973
Short name T92
Test name
Test status
Simulation time 69375389 ps
CPU time 1.41 seconds
Started Jun 25 05:50:45 PM PDT 24
Finished Jun 25 05:50:48 PM PDT 24
Peak memory 219128 kb
Host smart-80b77a17-f4e2-4960-9dcf-7c508056b6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131784973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3131784973
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.1205324452
Short name T147
Test name
Test status
Simulation time 31257760 ps
CPU time 1.14 seconds
Started Jun 25 05:50:48 PM PDT 24
Finished Jun 25 05:50:50 PM PDT 24
Peak memory 219120 kb
Host smart-63446540-e585-40b0-af83-93d04acfedc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205324452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.1205324452
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/158.edn_alert.11954827
Short name T530
Test name
Test status
Simulation time 40913194 ps
CPU time 1.11 seconds
Started Jun 25 05:50:47 PM PDT 24
Finished Jun 25 05:50:50 PM PDT 24
Peak memory 220180 kb
Host smart-14c25e5d-1150-4ba5-bb65-bb42862f38a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11954827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.11954827
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.2791947373
Short name T563
Test name
Test status
Simulation time 61821614 ps
CPU time 1.37 seconds
Started Jun 25 05:50:43 PM PDT 24
Finished Jun 25 05:50:45 PM PDT 24
Peak memory 217540 kb
Host smart-566ea7a1-92c0-44ad-abd3-ac230f807061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791947373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2791947373
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.3482145896
Short name T192
Test name
Test status
Simulation time 39835366 ps
CPU time 1.11 seconds
Started Jun 25 05:50:44 PM PDT 24
Finished Jun 25 05:50:47 PM PDT 24
Peak memory 219484 kb
Host smart-d17dea4e-a5b4-401d-ab05-6388ccb23c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482145896 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.3482145896
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.105855827
Short name T768
Test name
Test status
Simulation time 66288389 ps
CPU time 1.18 seconds
Started Jun 25 05:50:45 PM PDT 24
Finished Jun 25 05:50:48 PM PDT 24
Peak memory 220248 kb
Host smart-2842c70d-ebb6-4ce6-88e6-2efeba34c6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105855827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.105855827
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2054726397
Short name T782
Test name
Test status
Simulation time 33986498 ps
CPU time 1.34 seconds
Started Jun 25 05:48:45 PM PDT 24
Finished Jun 25 05:48:47 PM PDT 24
Peak memory 219168 kb
Host smart-bc8a120c-a494-41a5-a5a0-d2e4ea72dfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054726397 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2054726397
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1017532107
Short name T654
Test name
Test status
Simulation time 60486651 ps
CPU time 0.98 seconds
Started Jun 25 05:48:48 PM PDT 24
Finished Jun 25 05:48:51 PM PDT 24
Peak memory 207072 kb
Host smart-f1da00bd-ab35-4885-ba47-0b088cab6222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017532107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1017532107
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.421629543
Short name T849
Test name
Test status
Simulation time 21689125 ps
CPU time 0.89 seconds
Started Jun 25 05:48:48 PM PDT 24
Finished Jun 25 05:48:51 PM PDT 24
Peak memory 216372 kb
Host smart-9c76ed1e-4dc8-4fbf-9df3-2728b4357ef0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421629543 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.421629543
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.3586624482
Short name T149
Test name
Test status
Simulation time 101890240 ps
CPU time 1.43 seconds
Started Jun 25 05:48:47 PM PDT 24
Finished Jun 25 05:48:49 PM PDT 24
Peak memory 225832 kb
Host smart-68dd5b88-1220-425e-b23b-7ba6b833cfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586624482 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3586624482
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3204877382
Short name T605
Test name
Test status
Simulation time 51689606 ps
CPU time 1.24 seconds
Started Jun 25 05:48:48 PM PDT 24
Finished Jun 25 05:48:51 PM PDT 24
Peak memory 217620 kb
Host smart-68f4fd4d-a44a-41ac-bb23-93c5188141ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204877382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3204877382
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.524419797
Short name T723
Test name
Test status
Simulation time 21106914 ps
CPU time 1.11 seconds
Started Jun 25 05:48:48 PM PDT 24
Finished Jun 25 05:48:51 PM PDT 24
Peak memory 216196 kb
Host smart-f39d01a2-8f77-479e-a991-1a1aea5a0578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524419797 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.524419797
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.4224069235
Short name T37
Test name
Test status
Simulation time 22064474 ps
CPU time 0.95 seconds
Started Jun 25 05:48:47 PM PDT 24
Finished Jun 25 05:48:50 PM PDT 24
Peak memory 215668 kb
Host smart-47e18585-2e07-4b4c-8510-26b391f498c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224069235 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.4224069235
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2509970964
Short name T366
Test name
Test status
Simulation time 34496698 ps
CPU time 1.02 seconds
Started Jun 25 05:48:48 PM PDT 24
Finished Jun 25 05:48:51 PM PDT 24
Peak memory 207068 kb
Host smart-e83f9c44-841c-41db-b5ac-94f75cb7e0cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509970964 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2509970964
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2729812024
Short name T235
Test name
Test status
Simulation time 54362440736 ps
CPU time 500.54 seconds
Started Jun 25 05:48:51 PM PDT 24
Finished Jun 25 05:57:13 PM PDT 24
Peak memory 217984 kb
Host smart-3f4e7349-ab9b-424d-af0a-a5ffafd6698c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729812024 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2729812024
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.823963561
Short name T722
Test name
Test status
Simulation time 124568591 ps
CPU time 1.39 seconds
Started Jun 25 05:50:45 PM PDT 24
Finished Jun 25 05:50:47 PM PDT 24
Peak memory 220460 kb
Host smart-122fda6d-4b25-4e97-82f3-c453d6677c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823963561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.823963561
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.3154426136
Short name T630
Test name
Test status
Simulation time 44386930 ps
CPU time 1.25 seconds
Started Jun 25 05:50:46 PM PDT 24
Finished Jun 25 05:50:49 PM PDT 24
Peak memory 215636 kb
Host smart-367ac24f-c5c2-487f-8406-f78abc27a5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154426136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3154426136
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.823703536
Short name T867
Test name
Test status
Simulation time 25283123 ps
CPU time 1.19 seconds
Started Jun 25 05:50:48 PM PDT 24
Finished Jun 25 05:50:50 PM PDT 24
Peak memory 216124 kb
Host smart-5846fcdc-718b-4a71-9f3d-64c0151ba18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823703536 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.823703536
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.3039726201
Short name T642
Test name
Test status
Simulation time 123372933 ps
CPU time 1.53 seconds
Started Jun 25 05:50:44 PM PDT 24
Finished Jun 25 05:50:47 PM PDT 24
Peak memory 220356 kb
Host smart-5c93a99b-8b40-4f33-9f13-444f4872248a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039726201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3039726201
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.565114169
Short name T944
Test name
Test status
Simulation time 27750874 ps
CPU time 1.26 seconds
Started Jun 25 05:50:55 PM PDT 24
Finished Jun 25 05:50:57 PM PDT 24
Peak memory 216068 kb
Host smart-1625699c-a7de-490c-89e7-e4effc14e2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565114169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.565114169
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.2220943317
Short name T613
Test name
Test status
Simulation time 75574518 ps
CPU time 1.34 seconds
Started Jun 25 05:50:43 PM PDT 24
Finished Jun 25 05:50:46 PM PDT 24
Peak memory 219212 kb
Host smart-55b464cf-2c1b-4abd-8933-57cb11924c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220943317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2220943317
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2655875433
Short name T845
Test name
Test status
Simulation time 104285460 ps
CPU time 1.23 seconds
Started Jun 25 05:50:55 PM PDT 24
Finished Jun 25 05:50:58 PM PDT 24
Peak memory 216068 kb
Host smart-47db764e-c781-401b-9cbc-e00ffc6f6b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655875433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2655875433
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/165.edn_alert.302788137
Short name T310
Test name
Test status
Simulation time 48218346 ps
CPU time 1.22 seconds
Started Jun 25 05:50:55 PM PDT 24
Finished Jun 25 05:50:57 PM PDT 24
Peak memory 219176 kb
Host smart-5d0d784d-8740-4423-9414-378490d3dd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302788137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.302788137
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.3852513881
Short name T800
Test name
Test status
Simulation time 71873349 ps
CPU time 1.24 seconds
Started Jun 25 05:50:54 PM PDT 24
Finished Jun 25 05:50:56 PM PDT 24
Peak memory 217560 kb
Host smart-2b380f78-fe50-47a8-97e5-834d1a34f81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852513881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3852513881
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.3551118687
Short name T499
Test name
Test status
Simulation time 272379180 ps
CPU time 1.43 seconds
Started Jun 25 05:50:53 PM PDT 24
Finished Jun 25 05:50:55 PM PDT 24
Peak memory 216020 kb
Host smart-9b1dc42e-31d2-449e-b375-ed7f4713d257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551118687 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.3551118687
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.2592069728
Short name T673
Test name
Test status
Simulation time 39930273 ps
CPU time 1.44 seconds
Started Jun 25 05:50:55 PM PDT 24
Finished Jun 25 05:50:58 PM PDT 24
Peak memory 218788 kb
Host smart-a023ba10-40bd-453a-9632-c4f4836b3a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592069728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2592069728
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.2832305944
Short name T837
Test name
Test status
Simulation time 57452640 ps
CPU time 1.47 seconds
Started Jun 25 05:50:56 PM PDT 24
Finished Jun 25 05:50:59 PM PDT 24
Peak memory 219280 kb
Host smart-69bc827f-e20c-4fac-8445-b4ca4f0d3a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832305944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2832305944
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.108636276
Short name T484
Test name
Test status
Simulation time 45966094 ps
CPU time 1.27 seconds
Started Jun 25 05:51:02 PM PDT 24
Finished Jun 25 05:51:05 PM PDT 24
Peak memory 219692 kb
Host smart-15f6b974-4995-4d6c-8179-d4f4aff03901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108636276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.108636276
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1807649581
Short name T965
Test name
Test status
Simulation time 55640379 ps
CPU time 1.17 seconds
Started Jun 25 05:50:57 PM PDT 24
Finished Jun 25 05:50:59 PM PDT 24
Peak memory 215676 kb
Host smart-166dce6e-ba85-4546-9974-570e5ff9f46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807649581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1807649581
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.1576565635
Short name T148
Test name
Test status
Simulation time 148739666 ps
CPU time 1.17 seconds
Started Jun 25 05:50:54 PM PDT 24
Finished Jun 25 05:50:56 PM PDT 24
Peak memory 218960 kb
Host smart-cebef221-66e8-40ea-8a50-861057c68d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576565635 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.1576565635
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.2196559952
Short name T636
Test name
Test status
Simulation time 66028654 ps
CPU time 1.06 seconds
Started Jun 25 05:50:53 PM PDT 24
Finished Jun 25 05:50:55 PM PDT 24
Peak memory 217484 kb
Host smart-1bae0767-2478-41f9-86a8-2608d95fc620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196559952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2196559952
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.4151033545
Short name T825
Test name
Test status
Simulation time 25819095 ps
CPU time 1.17 seconds
Started Jun 25 05:48:45 PM PDT 24
Finished Jun 25 05:48:47 PM PDT 24
Peak memory 219820 kb
Host smart-1844ea07-f5ef-4b88-b0b0-19257222137a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151033545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.4151033545
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3264982101
Short name T878
Test name
Test status
Simulation time 18798787 ps
CPU time 0.92 seconds
Started Jun 25 05:48:47 PM PDT 24
Finished Jun 25 05:48:49 PM PDT 24
Peak memory 207048 kb
Host smart-3ecc0968-579b-47e3-9ca7-8e2ced6ef63e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264982101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3264982101
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.221291125
Short name T214
Test name
Test status
Simulation time 125407983 ps
CPU time 1.23 seconds
Started Jun 25 05:48:48 PM PDT 24
Finished Jun 25 05:48:51 PM PDT 24
Peak memory 217416 kb
Host smart-1ccc1c49-6cc4-464d-a250-1f1e11c11266
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221291125 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.221291125
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.202618626
Short name T961
Test name
Test status
Simulation time 33632802 ps
CPU time 0.97 seconds
Started Jun 25 05:48:45 PM PDT 24
Finished Jun 25 05:48:47 PM PDT 24
Peak memory 224092 kb
Host smart-a9ff1afb-3a09-4ee2-8c47-1f272a38ee8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202618626 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.202618626
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_intr.131743259
Short name T44
Test name
Test status
Simulation time 57136843 ps
CPU time 0.85 seconds
Started Jun 25 05:48:45 PM PDT 24
Finished Jun 25 05:48:47 PM PDT 24
Peak memory 215692 kb
Host smart-a028a458-8a7c-4249-9e10-7170e69d5c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131743259 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.131743259
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3032385278
Short name T875
Test name
Test status
Simulation time 28232122 ps
CPU time 0.97 seconds
Started Jun 25 05:48:48 PM PDT 24
Finished Jun 25 05:48:51 PM PDT 24
Peak memory 215664 kb
Host smart-588d6bfb-27b3-4550-a292-99ca0629a7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032385278 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3032385278
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.378054913
Short name T327
Test name
Test status
Simulation time 953215506 ps
CPU time 4.92 seconds
Started Jun 25 05:48:47 PM PDT 24
Finished Jun 25 05:48:54 PM PDT 24
Peak memory 217796 kb
Host smart-daac9e91-cfeb-4910-bad6-2b55023d907e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378054913 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.378054913
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1308911320
Short name T242
Test name
Test status
Simulation time 66733013771 ps
CPU time 1534.67 seconds
Started Jun 25 05:48:47 PM PDT 24
Finished Jun 25 06:14:23 PM PDT 24
Peak memory 223216 kb
Host smart-74b1eb9a-a823-494b-9a54-176aa48f0479
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308911320 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1308911320
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.2099269600
Short name T179
Test name
Test status
Simulation time 23877896 ps
CPU time 1.17 seconds
Started Jun 25 05:50:55 PM PDT 24
Finished Jun 25 05:50:58 PM PDT 24
Peak memory 218928 kb
Host smart-f44d3090-96fc-40c0-b483-ab42c436bb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099269600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.2099269600
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.4016369158
Short name T413
Test name
Test status
Simulation time 42763698 ps
CPU time 1.18 seconds
Started Jun 25 05:51:01 PM PDT 24
Finished Jun 25 05:51:03 PM PDT 24
Peak memory 219200 kb
Host smart-7c21ccd4-e06b-424f-9a4a-9707f6c558b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016369158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.4016369158
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.990464744
Short name T458
Test name
Test status
Simulation time 82546330 ps
CPU time 1.22 seconds
Started Jun 25 05:50:55 PM PDT 24
Finished Jun 25 05:50:57 PM PDT 24
Peak memory 219432 kb
Host smart-0e7f6989-8520-463b-8520-a3bc0067f4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990464744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.990464744
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.977524417
Short name T541
Test name
Test status
Simulation time 54416110 ps
CPU time 1.19 seconds
Started Jun 25 05:51:02 PM PDT 24
Finished Jun 25 05:51:04 PM PDT 24
Peak memory 217540 kb
Host smart-d5def321-1d90-49fa-b5fb-f778e6042551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977524417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.977524417
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1628213910
Short name T633
Test name
Test status
Simulation time 24775733 ps
CPU time 1.25 seconds
Started Jun 25 05:50:53 PM PDT 24
Finished Jun 25 05:50:55 PM PDT 24
Peak memory 218940 kb
Host smart-3b06b680-30a7-4ef3-9262-b4b44aa58963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628213910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1628213910
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.3061869324
Short name T838
Test name
Test status
Simulation time 72789291 ps
CPU time 1.3 seconds
Started Jun 25 05:50:52 PM PDT 24
Finished Jun 25 05:50:54 PM PDT 24
Peak memory 217620 kb
Host smart-f08fdfdf-690e-4080-bbbb-b6b4d5719120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061869324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3061869324
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.1931632912
Short name T162
Test name
Test status
Simulation time 40299252 ps
CPU time 1.3 seconds
Started Jun 25 05:50:57 PM PDT 24
Finished Jun 25 05:50:59 PM PDT 24
Peak memory 219020 kb
Host smart-1fba1a8b-0aed-4e1b-998e-ece15ef9ec11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931632912 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.1931632912
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.507029741
Short name T864
Test name
Test status
Simulation time 30798009 ps
CPU time 1.24 seconds
Started Jun 25 05:50:55 PM PDT 24
Finished Jun 25 05:50:57 PM PDT 24
Peak memory 217728 kb
Host smart-ddcaa8a1-289b-41fe-8bd7-b26299217f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507029741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.507029741
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.1327836710
Short name T565
Test name
Test status
Simulation time 73282760 ps
CPU time 1.18 seconds
Started Jun 25 05:50:55 PM PDT 24
Finished Jun 25 05:50:57 PM PDT 24
Peak memory 219764 kb
Host smart-7e92b36e-c18c-4e34-9b9b-632daf247068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327836710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.1327836710
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.2968902045
Short name T856
Test name
Test status
Simulation time 31369539 ps
CPU time 1.31 seconds
Started Jun 25 05:51:01 PM PDT 24
Finished Jun 25 05:51:04 PM PDT 24
Peak memory 220364 kb
Host smart-efa1edc6-ec0f-4c3f-b682-162fb946e6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968902045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2968902045
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3959255505
Short name T189
Test name
Test status
Simulation time 42950471 ps
CPU time 1.13 seconds
Started Jun 25 05:50:53 PM PDT 24
Finished Jun 25 05:50:55 PM PDT 24
Peak memory 219968 kb
Host smart-0180a368-1a45-415a-b6c2-41efd225820c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959255505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3959255505
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.2889117816
Short name T549
Test name
Test status
Simulation time 294984937 ps
CPU time 3.92 seconds
Started Jun 25 05:50:55 PM PDT 24
Finished Jun 25 05:51:00 PM PDT 24
Peak memory 220688 kb
Host smart-b269edda-31f4-4927-9685-de18aea88243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889117816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2889117816
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.2358426694
Short name T807
Test name
Test status
Simulation time 44070112 ps
CPU time 1.14 seconds
Started Jun 25 05:50:53 PM PDT 24
Finished Jun 25 05:50:55 PM PDT 24
Peak memory 220092 kb
Host smart-20374644-bb08-4e03-a24b-0c34ca3111e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358426694 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2358426694
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.995679503
Short name T730
Test name
Test status
Simulation time 132710101 ps
CPU time 1.68 seconds
Started Jun 25 05:50:55 PM PDT 24
Finished Jun 25 05:50:59 PM PDT 24
Peak memory 219304 kb
Host smart-2aadb0bc-d524-4d90-a84e-b306e02048fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995679503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.995679503
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.2008339757
Short name T22
Test name
Test status
Simulation time 24051395 ps
CPU time 1.22 seconds
Started Jun 25 05:50:55 PM PDT 24
Finished Jun 25 05:50:58 PM PDT 24
Peak memory 220168 kb
Host smart-c898d86d-ab86-454b-8ecf-97ec32d98e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008339757 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.2008339757
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.3886171907
Short name T561
Test name
Test status
Simulation time 40218494 ps
CPU time 1.44 seconds
Started Jun 25 05:51:03 PM PDT 24
Finished Jun 25 05:51:06 PM PDT 24
Peak memory 219116 kb
Host smart-df80d47d-f68e-4d88-a9c3-2226cb9d2f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886171907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3886171907
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.1622164170
Short name T870
Test name
Test status
Simulation time 30449688 ps
CPU time 1.14 seconds
Started Jun 25 05:50:56 PM PDT 24
Finished Jun 25 05:50:59 PM PDT 24
Peak memory 216076 kb
Host smart-4fec0982-b00e-4e04-9b18-37487058b374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622164170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.1622164170
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.323140115
Short name T353
Test name
Test status
Simulation time 282575764 ps
CPU time 3.94 seconds
Started Jun 25 05:50:55 PM PDT 24
Finished Jun 25 05:51:01 PM PDT 24
Peak memory 220500 kb
Host smart-1e0e8a9f-f346-4b1e-8353-4753dc43d667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323140115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.323140115
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.3023103523
Short name T137
Test name
Test status
Simulation time 118277677 ps
CPU time 1.28 seconds
Started Jun 25 05:50:55 PM PDT 24
Finished Jun 25 05:50:58 PM PDT 24
Peak memory 220588 kb
Host smart-b51fefee-00d3-478e-871b-086c495ee0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023103523 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3023103523
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.2915713329
Short name T666
Test name
Test status
Simulation time 114951398 ps
CPU time 2.68 seconds
Started Jun 25 05:50:54 PM PDT 24
Finished Jun 25 05:50:58 PM PDT 24
Peak memory 220464 kb
Host smart-f643751e-b55b-4e67-a397-01c9c17dd957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915713329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2915713329
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.371692825
Short name T911
Test name
Test status
Simulation time 27482535 ps
CPU time 0.92 seconds
Started Jun 25 05:48:49 PM PDT 24
Finished Jun 25 05:48:52 PM PDT 24
Peak memory 206992 kb
Host smart-cba75711-a500-438e-89d8-febd34daf056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371692825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.371692825
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3345181707
Short name T939
Test name
Test status
Simulation time 23878563 ps
CPU time 0.86 seconds
Started Jun 25 05:48:51 PM PDT 24
Finished Jun 25 05:48:53 PM PDT 24
Peak memory 216588 kb
Host smart-8b1995f8-19b7-438c-803c-5d3350cb19ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345181707 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3345181707
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.1518016162
Short name T249
Test name
Test status
Simulation time 36097192 ps
CPU time 1.4 seconds
Started Jun 25 05:48:45 PM PDT 24
Finished Jun 25 05:48:47 PM PDT 24
Peak memory 215816 kb
Host smart-1b8272ef-7a0c-4e69-b890-53db616e2233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518016162 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1518016162
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.735230446
Short name T812
Test name
Test status
Simulation time 22787091 ps
CPU time 1.27 seconds
Started Jun 25 05:48:47 PM PDT 24
Finished Jun 25 05:48:49 PM PDT 24
Peak memory 218024 kb
Host smart-69ed786f-87e0-46a2-adcc-d2fcb9f96e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735230446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.735230446
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.177274019
Short name T28
Test name
Test status
Simulation time 20648094 ps
CPU time 1.05 seconds
Started Jun 25 05:48:48 PM PDT 24
Finished Jun 25 05:48:51 PM PDT 24
Peak memory 216128 kb
Host smart-14ec95c7-c2e1-42e8-a01b-660604853172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177274019 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.177274019
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3622399559
Short name T883
Test name
Test status
Simulation time 23797668 ps
CPU time 0.96 seconds
Started Jun 25 05:48:48 PM PDT 24
Finished Jun 25 05:48:51 PM PDT 24
Peak memory 215548 kb
Host smart-16008dbc-24cf-4361-a9b5-33c4b33a36e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622399559 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3622399559
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1985330582
Short name T377
Test name
Test status
Simulation time 252311375 ps
CPU time 3.26 seconds
Started Jun 25 05:48:48 PM PDT 24
Finished Jun 25 05:48:53 PM PDT 24
Peak memory 215700 kb
Host smart-0b28310e-7140-4d1c-a9b5-d13bb18bc4a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985330582 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1985330582
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1511386030
Short name T437
Test name
Test status
Simulation time 55872047770 ps
CPU time 1261.47 seconds
Started Jun 25 05:48:48 PM PDT 24
Finished Jun 25 06:09:52 PM PDT 24
Peak memory 222116 kb
Host smart-c88afa24-ea8a-4872-a493-669582a2920b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511386030 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1511386030
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.3189331812
Short name T755
Test name
Test status
Simulation time 401135774 ps
CPU time 1.61 seconds
Started Jun 25 05:51:02 PM PDT 24
Finished Jun 25 05:51:06 PM PDT 24
Peak memory 221224 kb
Host smart-700ca49d-8e6d-4116-9592-6faffd5c9733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189331812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.3189331812
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.1794652830
Short name T871
Test name
Test status
Simulation time 71026276 ps
CPU time 1.57 seconds
Started Jun 25 05:51:02 PM PDT 24
Finished Jun 25 05:51:06 PM PDT 24
Peak memory 219448 kb
Host smart-aa43bc09-1b25-492f-ab18-6f0d04a89bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794652830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1794652830
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.2294101995
Short name T493
Test name
Test status
Simulation time 36085601 ps
CPU time 1.15 seconds
Started Jun 25 05:50:54 PM PDT 24
Finished Jun 25 05:50:56 PM PDT 24
Peak memory 219000 kb
Host smart-37bcae0d-3e63-45b9-879d-18ad035340b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294101995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.2294101995
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.1178356416
Short name T848
Test name
Test status
Simulation time 41331360 ps
CPU time 1.59 seconds
Started Jun 25 05:50:55 PM PDT 24
Finished Jun 25 05:50:58 PM PDT 24
Peak memory 215576 kb
Host smart-fb3cc1e2-ae71-48b4-9183-3a091e835146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178356416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1178356416
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.1270500844
Short name T818
Test name
Test status
Simulation time 66804908 ps
CPU time 1.09 seconds
Started Jun 25 05:50:54 PM PDT 24
Finished Jun 25 05:50:57 PM PDT 24
Peak memory 218852 kb
Host smart-d575e4c1-8d6b-4bd7-9e40-af6ab8a70655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270500844 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.1270500844
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.3747798432
Short name T771
Test name
Test status
Simulation time 63422647 ps
CPU time 1.4 seconds
Started Jun 25 05:51:02 PM PDT 24
Finished Jun 25 05:51:04 PM PDT 24
Peak memory 218720 kb
Host smart-abc646df-60f5-4cb7-b79f-e34333466449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747798432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3747798432
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.3658715602
Short name T787
Test name
Test status
Simulation time 81384716 ps
CPU time 1.14 seconds
Started Jun 25 05:50:54 PM PDT 24
Finished Jun 25 05:50:56 PM PDT 24
Peak memory 220528 kb
Host smart-494ad0c3-fcf1-4afd-b9ea-7bca5204b983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658715602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.3658715602
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.404199544
Short name T389
Test name
Test status
Simulation time 86844214 ps
CPU time 1.2 seconds
Started Jun 25 05:50:54 PM PDT 24
Finished Jun 25 05:50:57 PM PDT 24
Peak memory 220284 kb
Host smart-3ee4f623-9b24-4a13-9a84-afc6da2441a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404199544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.404199544
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.2874596433
Short name T405
Test name
Test status
Simulation time 24484737 ps
CPU time 1.14 seconds
Started Jun 25 05:50:53 PM PDT 24
Finished Jun 25 05:50:55 PM PDT 24
Peak memory 218732 kb
Host smart-bf99fe09-9931-44ff-bd98-02b5233e9c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874596433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.2874596433
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.498316099
Short name T620
Test name
Test status
Simulation time 38269638 ps
CPU time 1.82 seconds
Started Jun 25 05:50:52 PM PDT 24
Finished Jun 25 05:50:55 PM PDT 24
Peak memory 218860 kb
Host smart-2744c157-be29-4860-9ef9-8b5f088b04f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498316099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.498316099
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.3078005412
Short name T515
Test name
Test status
Simulation time 326451058 ps
CPU time 1.12 seconds
Started Jun 25 05:50:55 PM PDT 24
Finished Jun 25 05:50:58 PM PDT 24
Peak memory 220128 kb
Host smart-7adfe655-ce8d-41bc-8b9b-d8bc0e711114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078005412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.3078005412
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.1069819508
Short name T537
Test name
Test status
Simulation time 94462577 ps
CPU time 1.47 seconds
Started Jun 25 05:50:54 PM PDT 24
Finished Jun 25 05:50:57 PM PDT 24
Peak memory 217592 kb
Host smart-8abccc9e-0a92-4234-a676-ac2b9bb7b544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069819508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1069819508
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.2088692298
Short name T784
Test name
Test status
Simulation time 51163671 ps
CPU time 1.24 seconds
Started Jun 25 05:51:02 PM PDT 24
Finished Jun 25 05:51:04 PM PDT 24
Peak memory 219944 kb
Host smart-2944fc35-e722-4947-8b97-061a23f0e215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088692298 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2088692298
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.21212134
Short name T984
Test name
Test status
Simulation time 109260274 ps
CPU time 1.14 seconds
Started Jun 25 05:50:54 PM PDT 24
Finished Jun 25 05:50:56 PM PDT 24
Peak memory 219224 kb
Host smart-bf29d591-b28c-4997-a459-6486195def55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21212134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.21212134
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.612273309
Short name T556
Test name
Test status
Simulation time 80980285 ps
CPU time 1.2 seconds
Started Jun 25 05:50:54 PM PDT 24
Finished Jun 25 05:50:57 PM PDT 24
Peak memory 219788 kb
Host smart-e6149b28-a3b8-4107-bc3e-396d9bc464e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612273309 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.612273309
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.1959001435
Short name T690
Test name
Test status
Simulation time 56375942 ps
CPU time 1.32 seconds
Started Jun 25 05:50:53 PM PDT 24
Finished Jun 25 05:50:55 PM PDT 24
Peak memory 218752 kb
Host smart-ca433ff7-47a4-4d65-940d-327f721f329d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959001435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1959001435
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.2830592960
Short name T967
Test name
Test status
Simulation time 84741388 ps
CPU time 3.08 seconds
Started Jun 25 05:50:53 PM PDT 24
Finished Jun 25 05:50:57 PM PDT 24
Peak memory 218796 kb
Host smart-35b1b16c-088e-4bf1-91fc-55c0b3c3dd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830592960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2830592960
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.142391163
Short name T445
Test name
Test status
Simulation time 184407388 ps
CPU time 1.15 seconds
Started Jun 25 05:51:01 PM PDT 24
Finished Jun 25 05:51:04 PM PDT 24
Peak memory 219748 kb
Host smart-361b3fa2-1ea4-4003-b7ea-7561871ecba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142391163 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.142391163
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2710082262
Short name T54
Test name
Test status
Simulation time 53786921 ps
CPU time 1.36 seconds
Started Jun 25 05:51:06 PM PDT 24
Finished Jun 25 05:51:09 PM PDT 24
Peak memory 217660 kb
Host smart-ebf33c07-85e9-4705-9d4c-2751333848e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710082262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2710082262
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2399616214
Short name T551
Test name
Test status
Simulation time 24848149 ps
CPU time 1.25 seconds
Started Jun 25 05:48:54 PM PDT 24
Finished Jun 25 05:48:57 PM PDT 24
Peak memory 220840 kb
Host smart-87aba8ca-9fd3-4592-ad09-852a5ce5647b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399616214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2399616214
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.4241606464
Short name T609
Test name
Test status
Simulation time 49750166 ps
CPU time 0.91 seconds
Started Jun 25 05:48:55 PM PDT 24
Finished Jun 25 05:48:57 PM PDT 24
Peak memory 206936 kb
Host smart-8e81edbe-2169-4863-acc2-e7bbcf5d4301
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241606464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.4241606464
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.3918951562
Short name T222
Test name
Test status
Simulation time 13788590 ps
CPU time 0.93 seconds
Started Jun 25 05:48:54 PM PDT 24
Finished Jun 25 05:48:56 PM PDT 24
Peak memory 216780 kb
Host smart-233c59f8-5f41-43cf-8657-3563ca21890d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918951562 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3918951562
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3440205100
Short name T146
Test name
Test status
Simulation time 130634884 ps
CPU time 1 seconds
Started Jun 25 05:48:55 PM PDT 24
Finished Jun 25 05:48:58 PM PDT 24
Peak memory 220072 kb
Host smart-8547d05d-874e-4c24-9fe6-c4a0369c3d41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440205100 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3440205100
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.207980366
Short name T9
Test name
Test status
Simulation time 57880860 ps
CPU time 0.99 seconds
Started Jun 25 05:48:57 PM PDT 24
Finished Jun 25 05:49:00 PM PDT 24
Peak memory 220088 kb
Host smart-10a30977-3378-42ac-81f9-08b7920055ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207980366 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.207980366
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1813633507
Short name T419
Test name
Test status
Simulation time 41451971 ps
CPU time 1.37 seconds
Started Jun 25 05:48:47 PM PDT 24
Finished Jun 25 05:48:50 PM PDT 24
Peak memory 219240 kb
Host smart-833e8780-0bfd-49ae-ae67-cd18206186ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813633507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1813633507
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1545660089
Short name T681
Test name
Test status
Simulation time 33207189 ps
CPU time 0.93 seconds
Started Jun 25 05:48:47 PM PDT 24
Finished Jun 25 05:48:50 PM PDT 24
Peak memory 215916 kb
Host smart-162e5498-0a5f-499e-bb63-3a3081f11083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545660089 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1545660089
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.110027118
Short name T888
Test name
Test status
Simulation time 20452019 ps
CPU time 0.93 seconds
Started Jun 25 05:48:48 PM PDT 24
Finished Jun 25 05:48:50 PM PDT 24
Peak memory 215488 kb
Host smart-52640ba3-348a-4a79-ab83-b5f7d6fd0be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110027118 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.110027118
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3324685087
Short name T205
Test name
Test status
Simulation time 459110543 ps
CPU time 5.08 seconds
Started Jun 25 05:48:48 PM PDT 24
Finished Jun 25 05:48:55 PM PDT 24
Peak memory 220900 kb
Host smart-3d966df5-463e-4efb-bd79-4dd5cd684b6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324685087 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3324685087
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3771672953
Short name T922
Test name
Test status
Simulation time 19645199775 ps
CPU time 442.47 seconds
Started Jun 25 05:48:47 PM PDT 24
Finished Jun 25 05:56:11 PM PDT 24
Peak memory 223100 kb
Host smart-953f05d3-a7ae-4cc5-97d1-589737be570c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771672953 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3771672953
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.1765592319
Short name T901
Test name
Test status
Simulation time 22477360 ps
CPU time 1.18 seconds
Started Jun 25 05:51:03 PM PDT 24
Finished Jun 25 05:51:06 PM PDT 24
Peak memory 220028 kb
Host smart-e2b9e86c-4463-4c7b-97c4-903a49cace5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765592319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.1765592319
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.674036396
Short name T774
Test name
Test status
Simulation time 42943626 ps
CPU time 1.22 seconds
Started Jun 25 05:51:04 PM PDT 24
Finished Jun 25 05:51:07 PM PDT 24
Peak memory 220256 kb
Host smart-b5717dfe-9502-4a69-8859-4849e15ef1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674036396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.674036396
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.234739170
Short name T644
Test name
Test status
Simulation time 40084547 ps
CPU time 1.16 seconds
Started Jun 25 05:51:04 PM PDT 24
Finished Jun 25 05:51:08 PM PDT 24
Peak memory 218936 kb
Host smart-16de22fb-20b3-4740-9877-41db703df26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234739170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.234739170
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.4092485617
Short name T386
Test name
Test status
Simulation time 56775425 ps
CPU time 1.19 seconds
Started Jun 25 05:51:01 PM PDT 24
Finished Jun 25 05:51:03 PM PDT 24
Peak memory 219108 kb
Host smart-bb0a712e-cd92-4389-a948-89b5549216dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092485617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.4092485617
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.3703899160
Short name T177
Test name
Test status
Simulation time 21819538 ps
CPU time 1.3 seconds
Started Jun 25 05:51:07 PM PDT 24
Finished Jun 25 05:51:10 PM PDT 24
Peak memory 220332 kb
Host smart-cef2dbd0-3b9e-4f41-adda-84a2f7c54ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703899160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3703899160
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.2920945643
Short name T13
Test name
Test status
Simulation time 77037543 ps
CPU time 1.27 seconds
Started Jun 25 05:51:04 PM PDT 24
Finished Jun 25 05:51:08 PM PDT 24
Peak memory 219292 kb
Host smart-d740929d-b060-4463-8342-6c44eebfa307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920945643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2920945643
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.2643738250
Short name T559
Test name
Test status
Simulation time 39190624 ps
CPU time 1.17 seconds
Started Jun 25 05:51:02 PM PDT 24
Finished Jun 25 05:51:05 PM PDT 24
Peak memory 219608 kb
Host smart-7fab6c3d-be45-4c78-9257-3535b8c8753c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643738250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.2643738250
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.2289158180
Short name T794
Test name
Test status
Simulation time 19546533 ps
CPU time 1.13 seconds
Started Jun 25 05:51:03 PM PDT 24
Finished Jun 25 05:51:06 PM PDT 24
Peak memory 217600 kb
Host smart-4bfe6b1d-ae10-4afc-be03-af8d9aece331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289158180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2289158180
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.4103827063
Short name T308
Test name
Test status
Simulation time 28546082 ps
CPU time 1.33 seconds
Started Jun 25 05:51:02 PM PDT 24
Finished Jun 25 05:51:05 PM PDT 24
Peak memory 220188 kb
Host smart-25a08816-9fe1-4f0e-9efb-0e05a2782aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103827063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.4103827063
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.3899137114
Short name T661
Test name
Test status
Simulation time 51074876 ps
CPU time 1.54 seconds
Started Jun 25 05:51:02 PM PDT 24
Finished Jun 25 05:51:05 PM PDT 24
Peak memory 215584 kb
Host smart-c9598050-2f1c-4955-81d9-0864d299090e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899137114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3899137114
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.1811617812
Short name T696
Test name
Test status
Simulation time 23752008 ps
CPU time 1.19 seconds
Started Jun 25 05:51:02 PM PDT 24
Finished Jun 25 05:51:04 PM PDT 24
Peak memory 218960 kb
Host smart-b80dee38-a076-4e0a-9672-78bbda3dcae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811617812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.1811617812
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.3606110164
Short name T927
Test name
Test status
Simulation time 67345557 ps
CPU time 2.62 seconds
Started Jun 25 05:51:01 PM PDT 24
Finished Jun 25 05:51:04 PM PDT 24
Peak memory 218892 kb
Host smart-76096489-184d-4a9f-baa0-b4c839ed4b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606110164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3606110164
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.3070079822
Short name T521
Test name
Test status
Simulation time 25377536 ps
CPU time 1.28 seconds
Started Jun 25 05:51:03 PM PDT 24
Finished Jun 25 05:51:06 PM PDT 24
Peak memory 220184 kb
Host smart-3c0c8d7a-aca6-416b-b2ba-d749fc8ff42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070079822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.3070079822
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.1734439133
Short name T320
Test name
Test status
Simulation time 40992022 ps
CPU time 1.09 seconds
Started Jun 25 05:51:05 PM PDT 24
Finished Jun 25 05:51:08 PM PDT 24
Peak memory 217596 kb
Host smart-3992115b-0510-4b03-90f5-035591461064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734439133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1734439133
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.2384296960
Short name T858
Test name
Test status
Simulation time 28152055 ps
CPU time 1.27 seconds
Started Jun 25 05:51:05 PM PDT 24
Finished Jun 25 05:51:08 PM PDT 24
Peak memory 220892 kb
Host smart-0d6805b2-403f-4f02-a0f6-4fdaf5ae6266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384296960 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.2384296960
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.4253478645
Short name T665
Test name
Test status
Simulation time 36302191 ps
CPU time 1.16 seconds
Started Jun 25 05:51:05 PM PDT 24
Finished Jun 25 05:51:08 PM PDT 24
Peak memory 217720 kb
Host smart-3375c897-342d-449c-8acd-a1319e0f6290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253478645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.4253478645
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.3638633693
Short name T291
Test name
Test status
Simulation time 25304784 ps
CPU time 1.26 seconds
Started Jun 25 05:51:01 PM PDT 24
Finished Jun 25 05:51:04 PM PDT 24
Peak memory 221140 kb
Host smart-8c1272b1-0170-4e13-8fd8-c69ede702260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638633693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.3638633693
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.1994346650
Short name T504
Test name
Test status
Simulation time 22306784 ps
CPU time 1.24 seconds
Started Jun 25 05:51:07 PM PDT 24
Finished Jun 25 05:51:09 PM PDT 24
Peak memory 217512 kb
Host smart-4d6264a0-8270-438e-9547-07c2a1c78159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994346650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1994346650
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.4210441932
Short name T742
Test name
Test status
Simulation time 43737236 ps
CPU time 1.26 seconds
Started Jun 25 05:51:02 PM PDT 24
Finished Jun 25 05:51:05 PM PDT 24
Peak memory 221048 kb
Host smart-af83b03c-43f8-4cc2-9ec3-71bfd789f36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210441932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.4210441932
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.2389042138
Short name T748
Test name
Test status
Simulation time 48954042 ps
CPU time 1.22 seconds
Started Jun 25 05:51:02 PM PDT 24
Finished Jun 25 05:51:05 PM PDT 24
Peak memory 218996 kb
Host smart-ea9cccd1-a0a4-41dc-bbbc-955c94b74097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389042138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2389042138
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3128857266
Short name T685
Test name
Test status
Simulation time 38023255 ps
CPU time 1.12 seconds
Started Jun 25 05:48:16 PM PDT 24
Finished Jun 25 05:48:19 PM PDT 24
Peak memory 221252 kb
Host smart-41080174-879d-42f0-a73e-388c29b58756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128857266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3128857266
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3824566906
Short name T116
Test name
Test status
Simulation time 35361829 ps
CPU time 0.89 seconds
Started Jun 25 05:48:13 PM PDT 24
Finished Jun 25 05:48:16 PM PDT 24
Peak memory 215208 kb
Host smart-9fb1080c-1ff4-4673-b0c2-8cbd99b74d58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824566906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3824566906
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1339435280
Short name T168
Test name
Test status
Simulation time 17656479 ps
CPU time 0.86 seconds
Started Jun 25 05:48:15 PM PDT 24
Finished Jun 25 05:48:18 PM PDT 24
Peak memory 215676 kb
Host smart-b42c49bc-1525-49c9-a2cf-31f947090e1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339435280 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1339435280
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.2553066301
Short name T143
Test name
Test status
Simulation time 34685699 ps
CPU time 1.32 seconds
Started Jun 25 05:48:12 PM PDT 24
Finished Jun 25 05:48:15 PM PDT 24
Peak memory 230048 kb
Host smart-15121f35-72fc-4d03-b25f-7517d450b10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553066301 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2553066301
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.2517542295
Short name T323
Test name
Test status
Simulation time 41376301 ps
CPU time 1.41 seconds
Started Jun 25 05:48:15 PM PDT 24
Finished Jun 25 05:48:18 PM PDT 24
Peak memory 218060 kb
Host smart-4f036a8a-fd6f-4a6b-95ec-a8cb26f3d528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517542295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2517542295
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.4221651615
Short name T701
Test name
Test status
Simulation time 23293303 ps
CPU time 1.24 seconds
Started Jun 25 05:48:14 PM PDT 24
Finished Jun 25 05:48:17 PM PDT 24
Peak memory 224164 kb
Host smart-2045777e-92c1-4c0f-b81c-145f44b3f23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221651615 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.4221651615
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2149863880
Short name T109
Test name
Test status
Simulation time 49617581 ps
CPU time 0.95 seconds
Started Jun 25 05:48:15 PM PDT 24
Finished Jun 25 05:48:18 PM PDT 24
Peak memory 207392 kb
Host smart-23146c56-2bf2-4567-b8c0-e7f66e08d68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149863880 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2149863880
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.108018188
Short name T20
Test name
Test status
Simulation time 456875173 ps
CPU time 4.09 seconds
Started Jun 25 05:48:13 PM PDT 24
Finished Jun 25 05:48:18 PM PDT 24
Peak memory 242276 kb
Host smart-de593f67-7149-4422-bc26-25d967a38657
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108018188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.108018188
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1556124316
Short name T379
Test name
Test status
Simulation time 15792192 ps
CPU time 1.01 seconds
Started Jun 25 05:48:12 PM PDT 24
Finished Jun 25 05:48:13 PM PDT 24
Peak memory 215676 kb
Host smart-ce6a39db-1023-410f-b3cc-b08c98ae4788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556124316 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1556124316
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3522526854
Short name T288
Test name
Test status
Simulation time 128444316 ps
CPU time 2.85 seconds
Started Jun 25 05:48:16 PM PDT 24
Finished Jun 25 05:48:20 PM PDT 24
Peak memory 217548 kb
Host smart-391827ff-6899-43c6-827b-1e10e9027596
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522526854 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3522526854
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1612233920
Short name T734
Test name
Test status
Simulation time 239210109735 ps
CPU time 1512.72 seconds
Started Jun 25 05:48:11 PM PDT 24
Finished Jun 25 06:13:25 PM PDT 24
Peak memory 227508 kb
Host smart-5c475733-0d38-495f-992c-5994c0397635
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612233920 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1612233920
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2576614009
Short name T775
Test name
Test status
Simulation time 80776071 ps
CPU time 1.2 seconds
Started Jun 25 05:48:53 PM PDT 24
Finished Jun 25 05:48:55 PM PDT 24
Peak memory 219940 kb
Host smart-b5b926fe-3107-4881-99cf-94654bc722a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576614009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2576614009
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3156451311
Short name T876
Test name
Test status
Simulation time 45793084 ps
CPU time 0.98 seconds
Started Jun 25 05:48:55 PM PDT 24
Finished Jun 25 05:48:58 PM PDT 24
Peak memory 207204 kb
Host smart-f3507558-aed8-4975-b99a-8e63618d788f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156451311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3156451311
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.635179546
Short name T494
Test name
Test status
Simulation time 19904211 ps
CPU time 0.93 seconds
Started Jun 25 05:48:55 PM PDT 24
Finished Jun 25 05:48:57 PM PDT 24
Peak memory 215772 kb
Host smart-2f8188b6-0dfb-48bf-a472-5a30d3fc13c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635179546 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.635179546
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.2188602030
Short name T872
Test name
Test status
Simulation time 19229279 ps
CPU time 1.22 seconds
Started Jun 25 05:48:58 PM PDT 24
Finished Jun 25 05:49:01 PM PDT 24
Peak memory 224312 kb
Host smart-b104313b-5f88-4a5c-bfe5-b89c99e61328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188602030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2188602030
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_intr.211122372
Short name T683
Test name
Test status
Simulation time 29236119 ps
CPU time 0.92 seconds
Started Jun 25 05:49:01 PM PDT 24
Finished Jun 25 05:49:03 PM PDT 24
Peak memory 215736 kb
Host smart-cce9e0da-36af-401b-b0f6-dae9ce336cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211122372 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.211122372
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2153438649
Short name T479
Test name
Test status
Simulation time 23727604 ps
CPU time 0.98 seconds
Started Jun 25 05:48:56 PM PDT 24
Finished Jun 25 05:48:59 PM PDT 24
Peak memory 215636 kb
Host smart-4a7e58b8-0c49-4160-b44f-1823561b8aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153438649 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2153438649
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1457733000
Short name T105
Test name
Test status
Simulation time 328400321 ps
CPU time 6.69 seconds
Started Jun 25 05:48:55 PM PDT 24
Finished Jun 25 05:49:03 PM PDT 24
Peak memory 218832 kb
Host smart-3aef0b29-ec28-4c9f-be5d-f257cfd821c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457733000 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1457733000
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3396766395
Short name T106
Test name
Test status
Simulation time 143910770798 ps
CPU time 1637.65 seconds
Started Jun 25 05:48:56 PM PDT 24
Finished Jun 25 06:16:16 PM PDT 24
Peak memory 225996 kb
Host smart-95560b13-76cd-4168-bb32-f63d4b0e70a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396766395 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3396766395
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.485117306
Short name T943
Test name
Test status
Simulation time 36598134 ps
CPU time 1.55 seconds
Started Jun 25 05:51:03 PM PDT 24
Finished Jun 25 05:51:06 PM PDT 24
Peak memory 218912 kb
Host smart-bedc7541-fffc-43ea-b87e-8795f5934af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485117306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.485117306
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2175661406
Short name T926
Test name
Test status
Simulation time 49965117 ps
CPU time 1.79 seconds
Started Jun 25 05:51:05 PM PDT 24
Finished Jun 25 05:51:09 PM PDT 24
Peak memory 217144 kb
Host smart-0703291a-42cb-4296-9851-7b71b9dea9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175661406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2175661406
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1760731370
Short name T69
Test name
Test status
Simulation time 126979489 ps
CPU time 2.95 seconds
Started Jun 25 05:51:05 PM PDT 24
Finished Jun 25 05:51:10 PM PDT 24
Peak memory 220508 kb
Host smart-80bca0bb-4d46-4b86-a704-3a8628649d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760731370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1760731370
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.4083207990
Short name T336
Test name
Test status
Simulation time 137150225 ps
CPU time 1.28 seconds
Started Jun 25 05:51:02 PM PDT 24
Finished Jun 25 05:51:04 PM PDT 24
Peak memory 219152 kb
Host smart-1062682a-7bf9-4c57-9800-2f164a2aa033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083207990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.4083207990
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2734818753
Short name T516
Test name
Test status
Simulation time 117793742 ps
CPU time 1.64 seconds
Started Jun 25 05:51:05 PM PDT 24
Finished Jun 25 05:51:08 PM PDT 24
Peak memory 218592 kb
Host smart-98589627-fa5c-4c78-b313-1f29b97c4359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734818753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2734818753
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.2159854097
Short name T821
Test name
Test status
Simulation time 71006601 ps
CPU time 1.58 seconds
Started Jun 25 05:51:04 PM PDT 24
Finished Jun 25 05:51:08 PM PDT 24
Peak memory 220056 kb
Host smart-9afb9e51-f8a4-490a-9dff-3108eda93ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159854097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.2159854097
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2799345946
Short name T345
Test name
Test status
Simulation time 190560089 ps
CPU time 3.28 seconds
Started Jun 25 05:51:02 PM PDT 24
Finished Jun 25 05:51:07 PM PDT 24
Peak memory 220068 kb
Host smart-9ae446bf-88a8-4a10-a9cf-ff4f02d8bfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799345946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2799345946
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1051406715
Short name T861
Test name
Test status
Simulation time 42151201 ps
CPU time 1.51 seconds
Started Jun 25 05:51:02 PM PDT 24
Finished Jun 25 05:51:05 PM PDT 24
Peak memory 217612 kb
Host smart-02ec84eb-a80a-4adc-b69c-3cac5c5964ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051406715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1051406715
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2789753853
Short name T402
Test name
Test status
Simulation time 41948016 ps
CPU time 1.24 seconds
Started Jun 25 05:51:03 PM PDT 24
Finished Jun 25 05:51:06 PM PDT 24
Peak memory 218840 kb
Host smart-dbd2ffc0-95a0-4c7d-9a32-59f3ddaecd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789753853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2789753853
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.174361321
Short name T86
Test name
Test status
Simulation time 54232744 ps
CPU time 1.47 seconds
Started Jun 25 05:51:06 PM PDT 24
Finished Jun 25 05:51:09 PM PDT 24
Peak memory 218956 kb
Host smart-dc1bb003-a5cf-4734-80a7-3106c5674653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174361321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.174361321
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2511534539
Short name T309
Test name
Test status
Simulation time 23488544 ps
CPU time 1.25 seconds
Started Jun 25 05:48:55 PM PDT 24
Finished Jun 25 05:48:58 PM PDT 24
Peak memory 220364 kb
Host smart-a39eb308-b885-440a-ab95-4218da1e1b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511534539 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2511534539
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2751842738
Short name T827
Test name
Test status
Simulation time 14990861 ps
CPU time 0.94 seconds
Started Jun 25 05:48:55 PM PDT 24
Finished Jun 25 05:48:58 PM PDT 24
Peak memory 215496 kb
Host smart-4bdb2e00-4c38-4cd3-bf4c-c02d98857382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751842738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2751842738
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.4187352510
Short name T33
Test name
Test status
Simulation time 10651337 ps
CPU time 0.88 seconds
Started Jun 25 05:48:55 PM PDT 24
Finished Jun 25 05:48:58 PM PDT 24
Peak memory 216276 kb
Host smart-a49fe0df-43e6-4671-afd7-2c5aa9c3b353
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187352510 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.4187352510
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3251761315
Short name T392
Test name
Test status
Simulation time 35441472 ps
CPU time 1.17 seconds
Started Jun 25 05:49:02 PM PDT 24
Finished Jun 25 05:49:04 PM PDT 24
Peak memory 217260 kb
Host smart-adbcc529-aea2-494e-9384-e8e2486f7068
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251761315 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3251761315
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.1440417011
Short name T166
Test name
Test status
Simulation time 43956636 ps
CPU time 1.25 seconds
Started Jun 25 05:48:58 PM PDT 24
Finished Jun 25 05:49:01 PM PDT 24
Peak memory 225956 kb
Host smart-c7847bc5-2103-47b0-b4e6-6f1aacc711d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440417011 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1440417011
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2320881950
Short name T568
Test name
Test status
Simulation time 113088107 ps
CPU time 1.2 seconds
Started Jun 25 05:48:55 PM PDT 24
Finished Jun 25 05:48:58 PM PDT 24
Peak memory 217752 kb
Host smart-ed73d75d-f02f-4ca3-8d9a-8ff5346f8b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320881950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2320881950
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1168803214
Short name T41
Test name
Test status
Simulation time 33027268 ps
CPU time 0.92 seconds
Started Jun 25 05:48:55 PM PDT 24
Finished Jun 25 05:48:57 PM PDT 24
Peak memory 215980 kb
Host smart-ce1ff6be-34b9-4945-8f33-251ecffe1667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168803214 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1168803214
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.4267573992
Short name T550
Test name
Test status
Simulation time 19296068 ps
CPU time 1.02 seconds
Started Jun 25 05:48:57 PM PDT 24
Finished Jun 25 05:49:00 PM PDT 24
Peak memory 215660 kb
Host smart-48f0d43c-0389-4cec-bce2-3907694d5a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267573992 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.4267573992
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2377670742
Short name T401
Test name
Test status
Simulation time 593363746 ps
CPU time 7.2 seconds
Started Jun 25 05:48:57 PM PDT 24
Finished Jun 25 05:49:06 PM PDT 24
Peak memory 215628 kb
Host smart-7ec781f7-ed7d-42c2-b82b-7ca6f3a4a894
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377670742 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2377670742
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.158998054
Short name T647
Test name
Test status
Simulation time 60626484761 ps
CPU time 781.65 seconds
Started Jun 25 05:48:54 PM PDT 24
Finished Jun 25 06:01:57 PM PDT 24
Peak memory 224032 kb
Host smart-8f873f59-884a-453c-8302-daa61e745c06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158998054 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.158998054
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2060909954
Short name T560
Test name
Test status
Simulation time 56120905 ps
CPU time 1.43 seconds
Started Jun 25 05:51:03 PM PDT 24
Finished Jun 25 05:51:07 PM PDT 24
Peak memory 219168 kb
Host smart-66ebbe5a-8f33-4c10-97c8-588d30adbe8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060909954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2060909954
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.929159579
Short name T703
Test name
Test status
Simulation time 47820785 ps
CPU time 1.25 seconds
Started Jun 25 05:51:03 PM PDT 24
Finished Jun 25 05:51:07 PM PDT 24
Peak memory 215644 kb
Host smart-9818b8ec-b102-4abe-9667-1b78e5aca1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929159579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.929159579
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2361603277
Short name T407
Test name
Test status
Simulation time 30533925 ps
CPU time 1.28 seconds
Started Jun 25 05:51:03 PM PDT 24
Finished Jun 25 05:51:07 PM PDT 24
Peak memory 218744 kb
Host smart-b00c886f-223e-40ac-8284-4f87a80f0bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361603277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2361603277
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.214890567
Short name T410
Test name
Test status
Simulation time 47554389 ps
CPU time 1.35 seconds
Started Jun 25 05:51:04 PM PDT 24
Finished Jun 25 05:51:07 PM PDT 24
Peak memory 219376 kb
Host smart-dcaab31a-3441-4e18-97ee-12f38a590450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214890567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.214890567
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.56002063
Short name T766
Test name
Test status
Simulation time 65215531 ps
CPU time 1.26 seconds
Started Jun 25 05:51:04 PM PDT 24
Finished Jun 25 05:51:07 PM PDT 24
Peak memory 217800 kb
Host smart-1deefd0f-8fae-4c75-a2f7-d70e7693b753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56002063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.56002063
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2320473660
Short name T660
Test name
Test status
Simulation time 42800336 ps
CPU time 1.44 seconds
Started Jun 25 05:51:04 PM PDT 24
Finished Jun 25 05:51:07 PM PDT 24
Peak memory 217552 kb
Host smart-e9327f73-3687-4575-a4d3-3a5a2e857828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320473660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2320473660
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.3289232446
Short name T548
Test name
Test status
Simulation time 147491241 ps
CPU time 3.3 seconds
Started Jun 25 05:51:03 PM PDT 24
Finished Jun 25 05:51:09 PM PDT 24
Peak memory 220496 kb
Host smart-3fdf951b-ed8d-4709-85f6-90f71339f6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289232446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.3289232446
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.981774791
Short name T907
Test name
Test status
Simulation time 49431276 ps
CPU time 1.5 seconds
Started Jun 25 05:51:07 PM PDT 24
Finished Jun 25 05:51:10 PM PDT 24
Peak memory 217732 kb
Host smart-63e1c59d-a2b6-4a89-ac97-0fd67528517e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981774791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.981774791
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3749681371
Short name T840
Test name
Test status
Simulation time 42472902 ps
CPU time 1.42 seconds
Started Jun 25 05:51:03 PM PDT 24
Finished Jun 25 05:51:06 PM PDT 24
Peak memory 218960 kb
Host smart-af420435-8b93-49e9-94ad-ad0e6922db9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749681371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3749681371
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2055127438
Short name T740
Test name
Test status
Simulation time 39506217 ps
CPU time 1.47 seconds
Started Jun 25 05:51:05 PM PDT 24
Finished Jun 25 05:51:09 PM PDT 24
Peak memory 220044 kb
Host smart-816fd0f1-a207-4cad-ab81-2db62ed2c9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055127438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2055127438
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1597289817
Short name T478
Test name
Test status
Simulation time 83190409 ps
CPU time 1.42 seconds
Started Jun 25 05:48:56 PM PDT 24
Finished Jun 25 05:48:59 PM PDT 24
Peak memory 219132 kb
Host smart-3023bd27-4b11-46a6-9afe-d9101dc1a37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597289817 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1597289817
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.511771179
Short name T544
Test name
Test status
Simulation time 19710517 ps
CPU time 1.01 seconds
Started Jun 25 05:48:57 PM PDT 24
Finished Jun 25 05:49:00 PM PDT 24
Peak memory 207092 kb
Host smart-0775f844-bb73-44ec-99e2-77cbd0031f02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511771179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.511771179
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.4065107905
Short name T688
Test name
Test status
Simulation time 39143636 ps
CPU time 0.84 seconds
Started Jun 25 05:49:02 PM PDT 24
Finished Jun 25 05:49:03 PM PDT 24
Peak memory 216552 kb
Host smart-d630e0b3-b34a-4e63-9657-312523c0531f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065107905 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.4065107905
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3527669651
Short name T223
Test name
Test status
Simulation time 176968709 ps
CPU time 1.28 seconds
Started Jun 25 05:48:57 PM PDT 24
Finished Jun 25 05:49:00 PM PDT 24
Peak memory 217204 kb
Host smart-0579b45b-8220-4e35-b9d0-21c78f2d6e9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527669651 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3527669651
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3595070586
Short name T942
Test name
Test status
Simulation time 30560692 ps
CPU time 1.02 seconds
Started Jun 25 05:48:55 PM PDT 24
Finished Jun 25 05:48:57 PM PDT 24
Peak memory 224092 kb
Host smart-7287c4af-ee75-41a7-83fb-47c65de30f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595070586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3595070586
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3526928203
Short name T577
Test name
Test status
Simulation time 121701351 ps
CPU time 1.6 seconds
Started Jun 25 05:49:01 PM PDT 24
Finished Jun 25 05:49:03 PM PDT 24
Peak memory 220160 kb
Host smart-b84d6cd4-ddb7-4956-a5e6-8694d1318579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526928203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3526928203
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.825063240
Short name T360
Test name
Test status
Simulation time 40888850 ps
CPU time 0.9 seconds
Started Jun 25 05:48:54 PM PDT 24
Finished Jun 25 05:48:57 PM PDT 24
Peak memory 215872 kb
Host smart-8943bb88-723d-4b89-99f2-f148a5190edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825063240 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.825063240
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.4282955171
Short name T453
Test name
Test status
Simulation time 33851941 ps
CPU time 0.9 seconds
Started Jun 25 05:48:55 PM PDT 24
Finished Jun 25 05:48:57 PM PDT 24
Peak memory 215648 kb
Host smart-68f72a3a-951d-4214-815f-2cf9a4a013de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282955171 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.4282955171
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2317371487
Short name T397
Test name
Test status
Simulation time 60450381 ps
CPU time 1.73 seconds
Started Jun 25 05:48:54 PM PDT 24
Finished Jun 25 05:48:57 PM PDT 24
Peak memory 215636 kb
Host smart-bd486bd6-ddc8-4e76-a5e9-b839ed13439c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317371487 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2317371487
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2383356317
Short name T621
Test name
Test status
Simulation time 36940463832 ps
CPU time 796.62 seconds
Started Jun 25 05:48:58 PM PDT 24
Finished Jun 25 06:02:16 PM PDT 24
Peak memory 224052 kb
Host smart-792ad1ee-b046-4cbe-90f7-8a74d0c41cd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383356317 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2383356317
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2207784463
Short name T100
Test name
Test status
Simulation time 84707771 ps
CPU time 1.19 seconds
Started Jun 25 05:51:01 PM PDT 24
Finished Jun 25 05:51:04 PM PDT 24
Peak memory 219052 kb
Host smart-30ef49f4-4a10-426b-a36a-7f3ec395edb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207784463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2207784463
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2195911249
Short name T434
Test name
Test status
Simulation time 59685082 ps
CPU time 1.29 seconds
Started Jun 25 05:51:04 PM PDT 24
Finished Jun 25 05:51:08 PM PDT 24
Peak memory 218704 kb
Host smart-66d4e07f-83b2-4372-b799-deda6a5635a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195911249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2195911249
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3929922876
Short name T890
Test name
Test status
Simulation time 48877622 ps
CPU time 1.37 seconds
Started Jun 25 05:51:03 PM PDT 24
Finished Jun 25 05:51:07 PM PDT 24
Peak memory 218992 kb
Host smart-2efceb12-6cae-4e8c-bccc-d81034952c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929922876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3929922876
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.409479511
Short name T338
Test name
Test status
Simulation time 92702721 ps
CPU time 1.59 seconds
Started Jun 25 05:51:05 PM PDT 24
Finished Jun 25 05:51:09 PM PDT 24
Peak memory 219124 kb
Host smart-3dd77011-a863-4800-9773-c255343a0a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409479511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.409479511
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.4243322400
Short name T374
Test name
Test status
Simulation time 90603624 ps
CPU time 3.2 seconds
Started Jun 25 05:51:03 PM PDT 24
Finished Jun 25 05:51:09 PM PDT 24
Peak memory 220564 kb
Host smart-e07cc782-6916-40bd-b8cd-e8dea64f1d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243322400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.4243322400
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1182284006
Short name T718
Test name
Test status
Simulation time 70542191 ps
CPU time 1.06 seconds
Started Jun 25 05:51:05 PM PDT 24
Finished Jun 25 05:51:08 PM PDT 24
Peak memory 217700 kb
Host smart-0dd5530a-0270-425c-b975-67d0318bd0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182284006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1182284006
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.527441334
Short name T946
Test name
Test status
Simulation time 35160163 ps
CPU time 1.35 seconds
Started Jun 25 05:51:12 PM PDT 24
Finished Jun 25 05:51:15 PM PDT 24
Peak memory 220280 kb
Host smart-5df833f7-ed85-41cf-a873-09dca784a3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527441334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.527441334
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.451479003
Short name T420
Test name
Test status
Simulation time 34779434 ps
CPU time 1.08 seconds
Started Jun 25 05:51:12 PM PDT 24
Finished Jun 25 05:51:15 PM PDT 24
Peak memory 220432 kb
Host smart-345c428a-98bf-4bab-bb2c-f0e6b89093d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451479003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.451479003
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.486036628
Short name T96
Test name
Test status
Simulation time 23861885 ps
CPU time 1.16 seconds
Started Jun 25 05:51:15 PM PDT 24
Finished Jun 25 05:51:17 PM PDT 24
Peak memory 217692 kb
Host smart-b20e3810-b698-43b4-949d-6e86e8964482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486036628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.486036628
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3286808702
Short name T341
Test name
Test status
Simulation time 34665164 ps
CPU time 1.25 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:27 PM PDT 24
Peak memory 218812 kb
Host smart-38990a6d-390f-4c75-a1b2-f8e9a1e440a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286808702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3286808702
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1459378362
Short name T391
Test name
Test status
Simulation time 23072625 ps
CPU time 1.21 seconds
Started Jun 25 05:49:03 PM PDT 24
Finished Jun 25 05:49:05 PM PDT 24
Peak memory 218896 kb
Host smart-c5288d76-a9b1-4d32-9c77-ba10214cd31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459378362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1459378362
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.88137784
Short name T920
Test name
Test status
Simulation time 44162572 ps
CPU time 1 seconds
Started Jun 25 05:49:02 PM PDT 24
Finished Jun 25 05:49:04 PM PDT 24
Peak memory 207064 kb
Host smart-f2c15ea8-f443-423c-862c-d118f90abebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88137784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.88137784
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2667659496
Short name T224
Test name
Test status
Simulation time 18929497 ps
CPU time 0.86 seconds
Started Jun 25 05:49:05 PM PDT 24
Finished Jun 25 05:49:07 PM PDT 24
Peak memory 216564 kb
Host smart-14f7759b-4232-4c86-bcf5-756ae01dfe76
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667659496 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2667659496
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3956796428
Short name T923
Test name
Test status
Simulation time 87755544 ps
CPU time 1.04 seconds
Started Jun 25 05:49:03 PM PDT 24
Finished Jun 25 05:49:05 PM PDT 24
Peak memory 218576 kb
Host smart-98903393-dcfa-4d0c-8ed8-38a9fc3f95fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956796428 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3956796428
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1212845179
Short name T427
Test name
Test status
Simulation time 47319614 ps
CPU time 1.05 seconds
Started Jun 25 05:49:04 PM PDT 24
Finished Jun 25 05:49:06 PM PDT 24
Peak memory 219092 kb
Host smart-3dc67ff4-9bc6-4d9d-a548-a1c24d8cf2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212845179 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1212845179
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2372111628
Short name T97
Test name
Test status
Simulation time 51541639 ps
CPU time 2.06 seconds
Started Jun 25 05:48:56 PM PDT 24
Finished Jun 25 05:49:00 PM PDT 24
Peak memory 218920 kb
Host smart-032ef95a-59a3-4c65-ba41-57c20f659313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372111628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2372111628
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3935549419
Short name T517
Test name
Test status
Simulation time 39518017 ps
CPU time 0.88 seconds
Started Jun 25 05:49:08 PM PDT 24
Finished Jun 25 05:49:10 PM PDT 24
Peak memory 215852 kb
Host smart-1ba6a352-29f8-4761-9d04-75c3dfce9026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935549419 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3935549419
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2912646389
Short name T835
Test name
Test status
Simulation time 83086672 ps
CPU time 0.95 seconds
Started Jun 25 05:48:57 PM PDT 24
Finished Jun 25 05:49:00 PM PDT 24
Peak memory 207452 kb
Host smart-e648ddfd-415a-43c2-905f-5ff7d5c5aaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912646389 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2912646389
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2824973310
Short name T909
Test name
Test status
Simulation time 96897611 ps
CPU time 2.27 seconds
Started Jun 25 05:49:01 PM PDT 24
Finished Jun 25 05:49:04 PM PDT 24
Peak memory 215612 kb
Host smart-4d7cfdc2-1402-4582-bdf5-551e1b00511f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824973310 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2824973310
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3384926361
Short name T562
Test name
Test status
Simulation time 220300859752 ps
CPU time 421.84 seconds
Started Jun 25 05:49:03 PM PDT 24
Finished Jun 25 05:56:06 PM PDT 24
Peak memory 222736 kb
Host smart-1122d1c4-30c8-4bd9-b4d7-a7385748f69e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384926361 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3384926361
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.474971320
Short name T456
Test name
Test status
Simulation time 44294983 ps
CPU time 1.47 seconds
Started Jun 25 05:51:15 PM PDT 24
Finished Jun 25 05:51:17 PM PDT 24
Peak memory 218924 kb
Host smart-bac417d1-6396-4b10-8fc2-0337eca30a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474971320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.474971320
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3516833126
Short name T542
Test name
Test status
Simulation time 43736000 ps
CPU time 1.35 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:27 PM PDT 24
Peak memory 218900 kb
Host smart-d146d773-df56-4017-8dfb-129e7eb226a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516833126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3516833126
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3606155451
Short name T367
Test name
Test status
Simulation time 67293376 ps
CPU time 1.13 seconds
Started Jun 25 05:51:11 PM PDT 24
Finished Jun 25 05:51:13 PM PDT 24
Peak memory 217788 kb
Host smart-cf83eef2-4b9c-4fbc-8e46-dc407f4ac63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606155451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3606155451
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3170654324
Short name T985
Test name
Test status
Simulation time 46477980 ps
CPU time 1.32 seconds
Started Jun 25 05:51:10 PM PDT 24
Finished Jun 25 05:51:12 PM PDT 24
Peak memory 218960 kb
Host smart-3097ca23-efd2-4c73-9dee-b89a611d0230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170654324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3170654324
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2489046725
Short name T566
Test name
Test status
Simulation time 93699038 ps
CPU time 1.17 seconds
Started Jun 25 05:51:23 PM PDT 24
Finished Jun 25 05:51:26 PM PDT 24
Peak memory 217712 kb
Host smart-bad67c98-2327-4d8c-815c-337d1b86ee76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489046725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2489046725
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2002734899
Short name T913
Test name
Test status
Simulation time 48409319 ps
CPU time 1.47 seconds
Started Jun 25 05:51:10 PM PDT 24
Finished Jun 25 05:51:13 PM PDT 24
Peak memory 219248 kb
Host smart-4210f194-729f-4b88-b703-12b284bb3bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002734899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2002734899
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.371385055
Short name T555
Test name
Test status
Simulation time 115958007 ps
CPU time 2.15 seconds
Started Jun 25 05:51:13 PM PDT 24
Finished Jun 25 05:51:16 PM PDT 24
Peak memory 220472 kb
Host smart-42884e94-0b1b-4e4f-8199-da5dc856d188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371385055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.371385055
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.4211320053
Short name T83
Test name
Test status
Simulation time 112851985 ps
CPU time 2.35 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:28 PM PDT 24
Peak memory 218852 kb
Host smart-0b79f78d-2401-41f8-9733-138036b43360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211320053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.4211320053
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3546347365
Short name T346
Test name
Test status
Simulation time 57361045 ps
CPU time 1.29 seconds
Started Jun 25 05:51:14 PM PDT 24
Finished Jun 25 05:51:16 PM PDT 24
Peak memory 218996 kb
Host smart-071ac2f7-c7ea-41ca-889a-6bb6cd1958fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546347365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3546347365
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3606719827
Short name T447
Test name
Test status
Simulation time 32424390 ps
CPU time 1.29 seconds
Started Jun 25 05:51:12 PM PDT 24
Finished Jun 25 05:51:14 PM PDT 24
Peak memory 217620 kb
Host smart-1102a3a2-fda6-41d4-9666-47dc5f1a03c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606719827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3606719827
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.769591294
Short name T631
Test name
Test status
Simulation time 75569334 ps
CPU time 1.1 seconds
Started Jun 25 05:49:04 PM PDT 24
Finished Jun 25 05:49:06 PM PDT 24
Peak memory 218804 kb
Host smart-8a32cc94-549b-4158-84c8-c499dc9117b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769591294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.769591294
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2760844731
Short name T457
Test name
Test status
Simulation time 37580572 ps
CPU time 1.01 seconds
Started Jun 25 05:49:03 PM PDT 24
Finished Jun 25 05:49:05 PM PDT 24
Peak memory 207064 kb
Host smart-d72afcf1-aa21-46e1-987f-c0ddd55eae32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760844731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2760844731
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1596054453
Short name T50
Test name
Test status
Simulation time 10986019 ps
CPU time 0.94 seconds
Started Jun 25 05:49:03 PM PDT 24
Finished Jun 25 05:49:05 PM PDT 24
Peak memory 216536 kb
Host smart-710c3f46-461a-4ff1-8b41-dcd0a22dfc0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596054453 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1596054453
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1096206436
Short name T156
Test name
Test status
Simulation time 30899904 ps
CPU time 1.26 seconds
Started Jun 25 05:49:06 PM PDT 24
Finished Jun 25 05:49:08 PM PDT 24
Peak memory 217392 kb
Host smart-f99fe1ad-612f-4f4a-8966-108bfe0cd979
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096206436 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1096206436
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3757367274
Short name T889
Test name
Test status
Simulation time 36657151 ps
CPU time 1.22 seconds
Started Jun 25 05:49:03 PM PDT 24
Finished Jun 25 05:49:05 PM PDT 24
Peak memory 220988 kb
Host smart-2f7ae8c2-af7e-4a3a-92b5-cbc6c66b08e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757367274 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3757367274
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1079254736
Short name T414
Test name
Test status
Simulation time 59450981 ps
CPU time 1.49 seconds
Started Jun 25 05:49:04 PM PDT 24
Finished Jun 25 05:49:07 PM PDT 24
Peak memory 218836 kb
Host smart-27796b54-edcd-499f-bb98-d67416fa982c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079254736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1079254736
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3468217375
Short name T461
Test name
Test status
Simulation time 36815309 ps
CPU time 0.92 seconds
Started Jun 25 05:49:05 PM PDT 24
Finished Jun 25 05:49:07 PM PDT 24
Peak memory 215748 kb
Host smart-b75fdf39-ecb3-4ed9-9697-8e1921c707aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468217375 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3468217375
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1277112248
Short name T503
Test name
Test status
Simulation time 49951380 ps
CPU time 0.96 seconds
Started Jun 25 05:49:05 PM PDT 24
Finished Jun 25 05:49:07 PM PDT 24
Peak memory 215648 kb
Host smart-59c366ef-cecb-4aab-ac9d-dabfb5ab500a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277112248 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1277112248
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2347773244
Short name T628
Test name
Test status
Simulation time 334285577 ps
CPU time 3.86 seconds
Started Jun 25 05:49:02 PM PDT 24
Finished Jun 25 05:49:06 PM PDT 24
Peak memory 215740 kb
Host smart-35797640-57a8-4491-8ca2-a092ba8f4718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347773244 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2347773244
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3293236778
Short name T342
Test name
Test status
Simulation time 58743487477 ps
CPU time 459.1 seconds
Started Jun 25 05:49:07 PM PDT 24
Finished Jun 25 05:56:46 PM PDT 24
Peak memory 218284 kb
Host smart-b06de888-90ce-426e-932a-b95ef6b74bf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293236778 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3293236778
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.373694274
Short name T84
Test name
Test status
Simulation time 46341255 ps
CPU time 1.71 seconds
Started Jun 25 05:51:11 PM PDT 24
Finished Jun 25 05:51:14 PM PDT 24
Peak memory 219008 kb
Host smart-d622d53c-883b-4d37-8fc3-24227275d6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373694274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.373694274
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3397638719
Short name T354
Test name
Test status
Simulation time 58234447 ps
CPU time 1.95 seconds
Started Jun 25 05:51:10 PM PDT 24
Finished Jun 25 05:51:13 PM PDT 24
Peak memory 219904 kb
Host smart-ba469f8f-5a34-48af-9ff8-4c2ef4e0e8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397638719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3397638719
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2206242105
Short name T330
Test name
Test status
Simulation time 76534095 ps
CPU time 1.34 seconds
Started Jun 25 05:51:11 PM PDT 24
Finished Jun 25 05:51:14 PM PDT 24
Peak memory 219012 kb
Host smart-7ff72df5-0050-4a80-bb72-53332096d8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206242105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2206242105
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.69420156
Short name T941
Test name
Test status
Simulation time 58046940 ps
CPU time 1.32 seconds
Started Jun 25 05:51:10 PM PDT 24
Finished Jun 25 05:51:12 PM PDT 24
Peak memory 218784 kb
Host smart-c523ac75-0066-4557-85fd-bdb1bbdc5240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69420156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.69420156
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1749463332
Short name T540
Test name
Test status
Simulation time 57793671 ps
CPU time 2.01 seconds
Started Jun 25 05:51:25 PM PDT 24
Finished Jun 25 05:51:29 PM PDT 24
Peak memory 217924 kb
Host smart-75b746be-fc57-44da-b8a9-98ed5f57b623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749463332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1749463332
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2106967598
Short name T891
Test name
Test status
Simulation time 98918229 ps
CPU time 1.38 seconds
Started Jun 25 05:51:12 PM PDT 24
Finished Jun 25 05:51:14 PM PDT 24
Peak memory 219160 kb
Host smart-eeadaa44-368a-449a-82d7-d6c67b05335f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106967598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2106967598
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2409999677
Short name T520
Test name
Test status
Simulation time 56964360 ps
CPU time 1.22 seconds
Started Jun 25 05:51:11 PM PDT 24
Finished Jun 25 05:51:13 PM PDT 24
Peak memory 219248 kb
Host smart-a0d9c023-2d3b-4baa-9d08-d22a2061309e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409999677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2409999677
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1460957815
Short name T988
Test name
Test status
Simulation time 92673047 ps
CPU time 1.31 seconds
Started Jun 25 05:51:09 PM PDT 24
Finished Jun 25 05:51:11 PM PDT 24
Peak memory 220460 kb
Host smart-9e1efc56-77f7-4b72-889e-1eb13cf2282b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460957815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1460957815
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2143873336
Short name T361
Test name
Test status
Simulation time 92793340 ps
CPU time 1.05 seconds
Started Jun 25 05:51:09 PM PDT 24
Finished Jun 25 05:51:11 PM PDT 24
Peak memory 217612 kb
Host smart-f3495512-b0ad-45f9-9c82-6a605bb21bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143873336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2143873336
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.622813788
Short name T670
Test name
Test status
Simulation time 47089289 ps
CPU time 1.94 seconds
Started Jun 25 05:51:10 PM PDT 24
Finished Jun 25 05:51:13 PM PDT 24
Peak memory 219096 kb
Host smart-35282d01-ad6e-448e-9665-e7799a481a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622813788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.622813788
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.631562326
Short name T862
Test name
Test status
Simulation time 30089973 ps
CPU time 1.32 seconds
Started Jun 25 05:49:03 PM PDT 24
Finished Jun 25 05:49:06 PM PDT 24
Peak memory 218816 kb
Host smart-3725ba7b-b59c-4251-b7b5-c3517bdbb3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631562326 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.631562326
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2519393121
Short name T880
Test name
Test status
Simulation time 17255145 ps
CPU time 0.91 seconds
Started Jun 25 05:49:05 PM PDT 24
Finished Jun 25 05:49:07 PM PDT 24
Peak memory 215208 kb
Host smart-e7a210b6-221a-41d4-a4fc-3c3319cbf1c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519393121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2519393121
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.179465300
Short name T645
Test name
Test status
Simulation time 37681163 ps
CPU time 0.89 seconds
Started Jun 25 05:49:03 PM PDT 24
Finished Jun 25 05:49:05 PM PDT 24
Peak memory 215688 kb
Host smart-879238af-7487-484c-903f-9f0534dd69b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179465300 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.179465300
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2870847736
Short name T161
Test name
Test status
Simulation time 41682974 ps
CPU time 1.37 seconds
Started Jun 25 05:49:03 PM PDT 24
Finished Jun 25 05:49:06 PM PDT 24
Peak memory 217360 kb
Host smart-544dfd71-d2e7-403d-a322-124a286c46e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870847736 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2870847736
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2037487566
Short name T717
Test name
Test status
Simulation time 21132398 ps
CPU time 1.16 seconds
Started Jun 25 05:49:04 PM PDT 24
Finished Jun 25 05:49:06 PM PDT 24
Peak memory 219744 kb
Host smart-a7c4d5d9-87d6-4408-9096-7d346126b3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037487566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2037487566
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.570610534
Short name T331
Test name
Test status
Simulation time 90250640 ps
CPU time 2.15 seconds
Started Jun 25 05:49:06 PM PDT 24
Finished Jun 25 05:49:09 PM PDT 24
Peak memory 218952 kb
Host smart-8d59ba5c-ae6c-4888-9c88-8d8d7392cac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570610534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.570610534
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2582949596
Short name T39
Test name
Test status
Simulation time 20594341 ps
CPU time 1.12 seconds
Started Jun 25 05:49:05 PM PDT 24
Finished Jun 25 05:49:07 PM PDT 24
Peak memory 216052 kb
Host smart-ad05c907-2612-400c-9519-3375eaa6162c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582949596 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2582949596
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1650808718
Short name T395
Test name
Test status
Simulation time 26955032 ps
CPU time 1.03 seconds
Started Jun 25 05:49:04 PM PDT 24
Finished Jun 25 05:49:06 PM PDT 24
Peak memory 207476 kb
Host smart-75f4bf81-2701-481d-9633-0af46bdd27c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650808718 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1650808718
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.4256159341
Short name T904
Test name
Test status
Simulation time 1102923321 ps
CPU time 2.64 seconds
Started Jun 25 05:49:03 PM PDT 24
Finished Jun 25 05:49:06 PM PDT 24
Peak memory 217752 kb
Host smart-9097e604-58e6-4ba3-b2eb-5d32057f1c26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256159341 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.4256159341
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1072631282
Short name T501
Test name
Test status
Simulation time 19586858099 ps
CPU time 281.43 seconds
Started Jun 25 05:49:05 PM PDT 24
Finished Jun 25 05:53:48 PM PDT 24
Peak memory 223888 kb
Host smart-473f5459-6bd2-405e-85b6-078a62af599f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072631282 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1072631282
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3898037709
Short name T932
Test name
Test status
Simulation time 36055586 ps
CPU time 1.25 seconds
Started Jun 25 05:51:11 PM PDT 24
Finished Jun 25 05:51:13 PM PDT 24
Peak memory 217832 kb
Host smart-9c28a688-83d4-4847-a2c3-d2a02f06ff3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898037709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3898037709
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.3804375653
Short name T51
Test name
Test status
Simulation time 74179965 ps
CPU time 1.37 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:27 PM PDT 24
Peak memory 219184 kb
Host smart-51a3dd96-6938-4d31-89bc-49503401c515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804375653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3804375653
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1952912667
Short name T854
Test name
Test status
Simulation time 59462107 ps
CPU time 1.08 seconds
Started Jun 25 05:51:14 PM PDT 24
Finished Jun 25 05:51:16 PM PDT 24
Peak memory 218980 kb
Host smart-4b676849-d910-4621-834b-7625422ace5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952912667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1952912667
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.416718440
Short name T658
Test name
Test status
Simulation time 136576047 ps
CPU time 1.08 seconds
Started Jun 25 05:51:11 PM PDT 24
Finished Jun 25 05:51:13 PM PDT 24
Peak memory 217612 kb
Host smart-f43b5fd6-5370-4baf-bdc4-df49ca7822f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416718440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.416718440
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.4043029308
Short name T587
Test name
Test status
Simulation time 56629843 ps
CPU time 1.22 seconds
Started Jun 25 05:51:09 PM PDT 24
Finished Jun 25 05:51:12 PM PDT 24
Peak memory 215572 kb
Host smart-0168eca6-c6c0-4e82-bfc8-1550bc70018b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043029308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.4043029308
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2794673990
Short name T446
Test name
Test status
Simulation time 93799238 ps
CPU time 1.39 seconds
Started Jun 25 05:51:08 PM PDT 24
Finished Jun 25 05:51:10 PM PDT 24
Peak memory 219112 kb
Host smart-898df796-82dc-43cb-9476-4dd6410ada69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794673990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2794673990
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1985198027
Short name T692
Test name
Test status
Simulation time 54568035 ps
CPU time 1.19 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:26 PM PDT 24
Peak memory 215640 kb
Host smart-da99a323-4084-4683-89b3-fad28e41a2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985198027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1985198027
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3530004645
Short name T488
Test name
Test status
Simulation time 146366274 ps
CPU time 1.12 seconds
Started Jun 25 05:51:11 PM PDT 24
Finished Jun 25 05:51:13 PM PDT 24
Peak memory 217488 kb
Host smart-8b007b5c-14cf-4d31-9409-97de8b0f0529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530004645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3530004645
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1455769152
Short name T82
Test name
Test status
Simulation time 76418544 ps
CPU time 1.92 seconds
Started Jun 25 05:51:15 PM PDT 24
Finished Jun 25 05:51:17 PM PDT 24
Peak memory 220404 kb
Host smart-6b133e2f-b1ba-4cde-98a8-c6bdeaf22a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455769152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1455769152
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.411533778
Short name T469
Test name
Test status
Simulation time 61535398 ps
CPU time 1.43 seconds
Started Jun 25 05:51:13 PM PDT 24
Finished Jun 25 05:51:15 PM PDT 24
Peak memory 218992 kb
Host smart-5f2bafa9-8d65-4133-a5b1-7e852f524194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411533778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.411533778
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2191156653
Short name T976
Test name
Test status
Simulation time 144435258 ps
CPU time 1.15 seconds
Started Jun 25 05:49:04 PM PDT 24
Finished Jun 25 05:49:06 PM PDT 24
Peak memory 218868 kb
Host smart-7215ee65-1db4-43d3-8542-cf8c1bed9522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191156653 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2191156653
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.403599267
Short name T450
Test name
Test status
Simulation time 63886725 ps
CPU time 0.86 seconds
Started Jun 25 05:49:11 PM PDT 24
Finished Jun 25 05:49:13 PM PDT 24
Peak memory 206812 kb
Host smart-19e037f6-1364-4b22-b741-69766b568473
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403599267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.403599267
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3607629775
Short name T930
Test name
Test status
Simulation time 11127613 ps
CPU time 0.93 seconds
Started Jun 25 05:49:09 PM PDT 24
Finished Jun 25 05:49:11 PM PDT 24
Peak memory 216384 kb
Host smart-eb9a7503-ce3d-4a8d-a474-710df85696ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607629775 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3607629775
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1721990239
Short name T586
Test name
Test status
Simulation time 73520184 ps
CPU time 1.32 seconds
Started Jun 25 05:49:11 PM PDT 24
Finished Jun 25 05:49:15 PM PDT 24
Peak memory 217240 kb
Host smart-db9df3af-fd33-4776-a221-d0bd3caf4b21
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721990239 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1721990239
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.4158215248
Short name T140
Test name
Test status
Simulation time 28665692 ps
CPU time 1.21 seconds
Started Jun 25 05:49:03 PM PDT 24
Finished Jun 25 05:49:06 PM PDT 24
Peak memory 220796 kb
Host smart-5c155e4f-69c8-4ba6-a943-a88883354973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158215248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.4158215248
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2906387217
Short name T687
Test name
Test status
Simulation time 53588894 ps
CPU time 1.41 seconds
Started Jun 25 05:49:06 PM PDT 24
Finished Jun 25 05:49:08 PM PDT 24
Peak memory 217784 kb
Host smart-db64a873-c59c-46ae-9016-ff9abc4c9ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906387217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2906387217
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.842591224
Short name T40
Test name
Test status
Simulation time 26280650 ps
CPU time 0.81 seconds
Started Jun 25 05:49:02 PM PDT 24
Finished Jun 25 05:49:04 PM PDT 24
Peak memory 215908 kb
Host smart-c0bf33d9-fdaf-40e0-a297-cd0a58075a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842591224 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.842591224
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2003865328
Short name T500
Test name
Test status
Simulation time 19849705 ps
CPU time 1 seconds
Started Jun 25 05:49:07 PM PDT 24
Finished Jun 25 05:49:09 PM PDT 24
Peak memory 215664 kb
Host smart-4cc0796a-cb1c-4253-bb8c-1fea40a88b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003865328 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2003865328
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.4022564692
Short name T254
Test name
Test status
Simulation time 165464252 ps
CPU time 3.56 seconds
Started Jun 25 05:49:05 PM PDT 24
Finished Jun 25 05:49:09 PM PDT 24
Peak memory 220808 kb
Host smart-4c0237b1-e5b9-4291-9aa3-e733d246abd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022564692 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.4022564692
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3094951435
Short name T686
Test name
Test status
Simulation time 25678688732 ps
CPU time 657.57 seconds
Started Jun 25 05:49:08 PM PDT 24
Finished Jun 25 06:00:07 PM PDT 24
Peak memory 218148 kb
Host smart-0b10b595-881f-4c8d-a39f-7df95add3a6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094951435 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3094951435
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.2217905634
Short name T422
Test name
Test status
Simulation time 73462371 ps
CPU time 1.43 seconds
Started Jun 25 05:51:10 PM PDT 24
Finished Jun 25 05:51:12 PM PDT 24
Peak memory 219600 kb
Host smart-549108af-5e2d-49e8-a054-206df811e08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217905634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2217905634
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1991849628
Short name T557
Test name
Test status
Simulation time 49142449 ps
CPU time 2 seconds
Started Jun 25 05:51:10 PM PDT 24
Finished Jun 25 05:51:13 PM PDT 24
Peak memory 218988 kb
Host smart-91610cc9-d78b-42d5-ab63-3512ae9dd11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991849628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1991849628
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2225257260
Short name T971
Test name
Test status
Simulation time 8812468436 ps
CPU time 110.85 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:53:16 PM PDT 24
Peak memory 220860 kb
Host smart-4294c34e-beca-42ba-9573-3fc418fcc2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225257260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2225257260
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2064196506
Short name T735
Test name
Test status
Simulation time 38066384 ps
CPU time 1.67 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:28 PM PDT 24
Peak memory 218744 kb
Host smart-cf0ec362-e945-44b2-8486-235b380b3774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064196506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2064196506
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.217289369
Short name T624
Test name
Test status
Simulation time 35829856 ps
CPU time 1.1 seconds
Started Jun 25 05:51:13 PM PDT 24
Finished Jun 25 05:51:15 PM PDT 24
Peak memory 218896 kb
Host smart-9ff154a6-22fe-4655-94fc-4a3de5e18b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217289369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.217289369
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.812014363
Short name T575
Test name
Test status
Simulation time 47483706 ps
CPU time 1.54 seconds
Started Jun 25 05:51:13 PM PDT 24
Finished Jun 25 05:51:15 PM PDT 24
Peak memory 218832 kb
Host smart-605d5fe2-a362-4829-af68-af52fc6d918e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812014363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.812014363
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2487105817
Short name T365
Test name
Test status
Simulation time 81772910 ps
CPU time 1.76 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:28 PM PDT 24
Peak memory 219012 kb
Host smart-bb8227eb-ca88-4b68-a53c-d9c8cf31f8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487105817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2487105817
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.392811719
Short name T709
Test name
Test status
Simulation time 75092613 ps
CPU time 1.24 seconds
Started Jun 25 05:51:17 PM PDT 24
Finished Jun 25 05:51:19 PM PDT 24
Peak memory 219216 kb
Host smart-fa144fff-9d1c-493b-9f60-b3996ffe3755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392811719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.392811719
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2088384636
Short name T376
Test name
Test status
Simulation time 56034383 ps
CPU time 1.77 seconds
Started Jun 25 05:51:21 PM PDT 24
Finished Jun 25 05:51:24 PM PDT 24
Peak memory 218620 kb
Host smart-cc5183a8-b31a-4452-9f5d-90194e868ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088384636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2088384636
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2961903200
Short name T476
Test name
Test status
Simulation time 124551550 ps
CPU time 1.13 seconds
Started Jun 25 05:49:12 PM PDT 24
Finished Jun 25 05:49:15 PM PDT 24
Peak memory 219736 kb
Host smart-4c4e49b8-f1e9-4a96-a66c-6e4f8d061e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961903200 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2961903200
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.778667034
Short name T403
Test name
Test status
Simulation time 45964532 ps
CPU time 0.86 seconds
Started Jun 25 05:49:20 PM PDT 24
Finished Jun 25 05:49:23 PM PDT 24
Peak memory 207024 kb
Host smart-0afd3dfc-579d-4209-b440-a89a29ac7054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778667034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.778667034
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3096725752
Short name T759
Test name
Test status
Simulation time 21409528 ps
CPU time 0.92 seconds
Started Jun 25 05:49:11 PM PDT 24
Finished Jun 25 05:49:13 PM PDT 24
Peak memory 216292 kb
Host smart-1b9b6d3c-98bb-43e8-8410-439ae9555ae0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096725752 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3096725752
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.4122219261
Short name T363
Test name
Test status
Simulation time 94645633 ps
CPU time 1.11 seconds
Started Jun 25 05:49:12 PM PDT 24
Finished Jun 25 05:49:15 PM PDT 24
Peak memory 217128 kb
Host smart-202a0349-45fa-4df5-9d22-e7d8ab4c0cd6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122219261 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.4122219261
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_genbits.1123897635
Short name T729
Test name
Test status
Simulation time 69429610 ps
CPU time 1.62 seconds
Started Jun 25 05:49:12 PM PDT 24
Finished Jun 25 05:49:16 PM PDT 24
Peak memory 219108 kb
Host smart-c7f34564-8d79-43fb-b587-98b43a943525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123897635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1123897635
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.3287926264
Short name T626
Test name
Test status
Simulation time 45994790 ps
CPU time 0.99 seconds
Started Jun 25 05:49:11 PM PDT 24
Finished Jun 25 05:49:13 PM PDT 24
Peak memory 224148 kb
Host smart-78d0c410-d59f-4cfa-9b99-34ec3d9d856f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287926264 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3287926264
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2431760661
Short name T761
Test name
Test status
Simulation time 51422894 ps
CPU time 0.98 seconds
Started Jun 25 05:49:13 PM PDT 24
Finished Jun 25 05:49:16 PM PDT 24
Peak memory 215868 kb
Host smart-fbec126b-beba-44ca-8982-ce7593bcb4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431760661 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2431760661
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3594267236
Short name T70
Test name
Test status
Simulation time 60202209 ps
CPU time 1.75 seconds
Started Jun 25 05:49:12 PM PDT 24
Finished Jun 25 05:49:16 PM PDT 24
Peak memory 218816 kb
Host smart-d0504bb2-7de6-4df5-9110-a94c41a19170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594267236 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3594267236
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.920974882
Short name T237
Test name
Test status
Simulation time 92770138249 ps
CPU time 1220.54 seconds
Started Jun 25 05:49:13 PM PDT 24
Finished Jun 25 06:09:36 PM PDT 24
Peak memory 225632 kb
Host smart-f7a31053-aad9-4174-a8b7-ac73a507d866
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920974882 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.920974882
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1289935030
Short name T334
Test name
Test status
Simulation time 84462334 ps
CPU time 1.39 seconds
Started Jun 25 05:51:19 PM PDT 24
Finished Jun 25 05:51:22 PM PDT 24
Peak memory 219408 kb
Host smart-ce7b8876-bbe2-4895-ae08-26bf193df603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289935030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1289935030
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2152080931
Short name T357
Test name
Test status
Simulation time 33941178 ps
CPU time 1.48 seconds
Started Jun 25 05:51:17 PM PDT 24
Finished Jun 25 05:51:20 PM PDT 24
Peak memory 218788 kb
Host smart-f9686c1b-82fb-4030-ac35-bfb134fe2f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152080931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2152080931
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1220948288
Short name T617
Test name
Test status
Simulation time 40404204 ps
CPU time 1.55 seconds
Started Jun 25 05:51:17 PM PDT 24
Finished Jun 25 05:51:20 PM PDT 24
Peak memory 218972 kb
Host smart-356da313-ff1b-4983-a653-7540d8453170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220948288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1220948288
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2363662401
Short name T762
Test name
Test status
Simulation time 56117306 ps
CPU time 1.26 seconds
Started Jun 25 05:51:16 PM PDT 24
Finished Jun 25 05:51:18 PM PDT 24
Peak memory 217736 kb
Host smart-fbef18c4-27da-442e-9085-ba195a4d6003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363662401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2363662401
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3176800347
Short name T332
Test name
Test status
Simulation time 77589035 ps
CPU time 1.29 seconds
Started Jun 25 05:51:16 PM PDT 24
Finished Jun 25 05:51:18 PM PDT 24
Peak memory 220324 kb
Host smart-0ff5f25c-dae0-4310-a64b-efb1ee7f7827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176800347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3176800347
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2422646550
Short name T481
Test name
Test status
Simulation time 160817302 ps
CPU time 1.55 seconds
Started Jun 25 05:51:16 PM PDT 24
Finished Jun 25 05:51:19 PM PDT 24
Peak memory 219348 kb
Host smart-912fef17-d0cd-4794-80c5-f7089e17ffd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422646550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2422646550
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.435343654
Short name T947
Test name
Test status
Simulation time 87673888 ps
CPU time 1.38 seconds
Started Jun 25 05:51:18 PM PDT 24
Finished Jun 25 05:51:20 PM PDT 24
Peak memory 219208 kb
Host smart-d439a0fc-9aab-4d8b-9f6c-42a421bc4a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435343654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.435343654
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1751744728
Short name T36
Test name
Test status
Simulation time 43008220 ps
CPU time 1 seconds
Started Jun 25 05:51:20 PM PDT 24
Finished Jun 25 05:51:23 PM PDT 24
Peak memory 217648 kb
Host smart-1264b2f0-8d20-4c33-8215-dcf74b35ffc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751744728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1751744728
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1715744403
Short name T524
Test name
Test status
Simulation time 39118078 ps
CPU time 1.36 seconds
Started Jun 25 05:51:17 PM PDT 24
Finished Jun 25 05:51:20 PM PDT 24
Peak memory 218848 kb
Host smart-f93fa184-0fe0-4117-8429-548fdf958003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715744403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1715744403
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2781487753
Short name T347
Test name
Test status
Simulation time 20653149 ps
CPU time 1.13 seconds
Started Jun 25 05:51:16 PM PDT 24
Finished Jun 25 05:51:18 PM PDT 24
Peak memory 217872 kb
Host smart-ac7cb038-851d-4901-be8a-c11396e32d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781487753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2781487753
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2909187458
Short name T492
Test name
Test status
Simulation time 65216458 ps
CPU time 1.11 seconds
Started Jun 25 05:49:14 PM PDT 24
Finished Jun 25 05:49:17 PM PDT 24
Peak memory 219380 kb
Host smart-adbe4679-aae6-4582-9c8f-efb98b51439d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909187458 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2909187458
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2931974551
Short name T579
Test name
Test status
Simulation time 41071005 ps
CPU time 0.91 seconds
Started Jun 25 05:49:13 PM PDT 24
Finished Jun 25 05:49:16 PM PDT 24
Peak memory 207040 kb
Host smart-70887030-19fa-4c28-abb8-1d753ab70bcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931974551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2931974551
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1678326490
Short name T802
Test name
Test status
Simulation time 10508539 ps
CPU time 0.86 seconds
Started Jun 25 05:49:10 PM PDT 24
Finished Jun 25 05:49:13 PM PDT 24
Peak memory 216364 kb
Host smart-d26695bf-1ae1-46de-8a8b-d242b68d1cc2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678326490 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1678326490
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1921617370
Short name T11
Test name
Test status
Simulation time 38053089 ps
CPU time 1.4 seconds
Started Jun 25 05:49:22 PM PDT 24
Finished Jun 25 05:49:26 PM PDT 24
Peak memory 217076 kb
Host smart-b7986542-60ec-4cd5-a416-5579f9ef7d72
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921617370 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1921617370
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2697961103
Short name T826
Test name
Test status
Simulation time 37228922 ps
CPU time 1 seconds
Started Jun 25 05:49:13 PM PDT 24
Finished Jun 25 05:49:16 PM PDT 24
Peak memory 224336 kb
Host smart-0e8ce1b0-b2c1-4e40-b44f-6883d5670a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697961103 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2697961103
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.945436703
Short name T430
Test name
Test status
Simulation time 91452502 ps
CPU time 1.16 seconds
Started Jun 25 05:49:10 PM PDT 24
Finished Jun 25 05:49:12 PM PDT 24
Peak memory 217836 kb
Host smart-daa99ce4-f3a7-497d-bb85-9529327502e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945436703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.945436703
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3652750672
Short name T46
Test name
Test status
Simulation time 20104469 ps
CPU time 1.07 seconds
Started Jun 25 05:49:12 PM PDT 24
Finished Jun 25 05:49:16 PM PDT 24
Peak memory 216136 kb
Host smart-a00632e8-2323-48c7-b04c-189adb8622b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652750672 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3652750672
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2196266593
Short name T583
Test name
Test status
Simulation time 24453913 ps
CPU time 0.97 seconds
Started Jun 25 05:49:22 PM PDT 24
Finished Jun 25 05:49:26 PM PDT 24
Peak memory 215604 kb
Host smart-7c0f492d-0141-4acf-a02d-696023500405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196266593 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2196266593
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1441592355
Short name T57
Test name
Test status
Simulation time 187193457 ps
CPU time 2.31 seconds
Started Jun 25 05:49:13 PM PDT 24
Finished Jun 25 05:49:17 PM PDT 24
Peak memory 217568 kb
Host smart-5194918b-cf46-4bb7-84ab-2bef687adfe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441592355 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1441592355
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1450780848
Short name T547
Test name
Test status
Simulation time 79086901111 ps
CPU time 1941.67 seconds
Started Jun 25 05:49:21 PM PDT 24
Finished Jun 25 06:21:46 PM PDT 24
Peak memory 236856 kb
Host smart-68a8ee87-4af0-41c6-b91f-fcaf38c1f2a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450780848 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1450780848
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1089044448
Short name T674
Test name
Test status
Simulation time 56869637 ps
CPU time 1.37 seconds
Started Jun 25 05:51:18 PM PDT 24
Finished Jun 25 05:51:21 PM PDT 24
Peak memory 217744 kb
Host smart-93089ece-aee7-4e82-9bb2-cac63d870847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089044448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1089044448
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3988225528
Short name T394
Test name
Test status
Simulation time 146617175 ps
CPU time 1.16 seconds
Started Jun 25 05:51:19 PM PDT 24
Finished Jun 25 05:51:22 PM PDT 24
Peak memory 217632 kb
Host smart-095d88b3-d07f-46e9-b287-3e72f6751295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988225528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3988225528
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2129586637
Short name T882
Test name
Test status
Simulation time 60445908 ps
CPU time 1.6 seconds
Started Jun 25 05:51:18 PM PDT 24
Finished Jun 25 05:51:21 PM PDT 24
Peak memory 218860 kb
Host smart-fde4c695-d3ae-4fab-9ace-18938c73f72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129586637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2129586637
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1619512558
Short name T951
Test name
Test status
Simulation time 202101935 ps
CPU time 1.08 seconds
Started Jun 25 05:51:17 PM PDT 24
Finished Jun 25 05:51:19 PM PDT 24
Peak memory 217564 kb
Host smart-b65193d3-42ec-4434-a71e-7b9671c366a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619512558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1619512558
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2314907394
Short name T343
Test name
Test status
Simulation time 66123012 ps
CPU time 1.55 seconds
Started Jun 25 05:51:19 PM PDT 24
Finished Jun 25 05:51:23 PM PDT 24
Peak memory 219212 kb
Host smart-44ae24ca-3318-41e7-833f-e9fcb4f1f2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314907394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2314907394
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1151775879
Short name T634
Test name
Test status
Simulation time 57858144 ps
CPU time 1.55 seconds
Started Jun 25 05:51:15 PM PDT 24
Finished Jun 25 05:51:18 PM PDT 24
Peak memory 219064 kb
Host smart-b2d78ff5-38e8-474a-a0e1-4356e668ad2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151775879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1151775879
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2777791387
Short name T675
Test name
Test status
Simulation time 44878246 ps
CPU time 1.72 seconds
Started Jun 25 05:51:18 PM PDT 24
Finished Jun 25 05:51:21 PM PDT 24
Peak memory 218872 kb
Host smart-487777f0-4320-4abc-a978-c9c64ee1c0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777791387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2777791387
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2351538740
Short name T53
Test name
Test status
Simulation time 96068540 ps
CPU time 2.86 seconds
Started Jun 25 05:51:18 PM PDT 24
Finished Jun 25 05:51:22 PM PDT 24
Peak memory 218980 kb
Host smart-c5b9a161-db49-4425-a34d-8c4020dbe986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351538740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2351538740
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2639457983
Short name T518
Test name
Test status
Simulation time 72877782 ps
CPU time 1.19 seconds
Started Jun 25 05:51:20 PM PDT 24
Finished Jun 25 05:51:22 PM PDT 24
Peak memory 217600 kb
Host smart-af1e85ef-5f73-4fd6-a2d8-79efe70ffb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639457983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2639457983
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1337875305
Short name T532
Test name
Test status
Simulation time 95672543 ps
CPU time 1.66 seconds
Started Jun 25 05:51:16 PM PDT 24
Finished Jun 25 05:51:19 PM PDT 24
Peak memory 219080 kb
Host smart-7272e2f0-daaa-4ca6-8a3c-82ee6ff4a149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337875305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1337875305
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1622750184
Short name T108
Test name
Test status
Simulation time 42419616 ps
CPU time 1.15 seconds
Started Jun 25 05:49:11 PM PDT 24
Finished Jun 25 05:49:14 PM PDT 24
Peak memory 219964 kb
Host smart-751bdab4-fb8e-4dd7-9c6f-2f09f4b4c9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622750184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1622750184
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1427342739
Short name T969
Test name
Test status
Simulation time 36769382 ps
CPU time 0.93 seconds
Started Jun 25 05:49:14 PM PDT 24
Finished Jun 25 05:49:17 PM PDT 24
Peak memory 207064 kb
Host smart-4be019af-7044-42b8-9828-96f676bb5d8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427342739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1427342739
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.130561382
Short name T957
Test name
Test status
Simulation time 30932286 ps
CPU time 0.86 seconds
Started Jun 25 05:49:22 PM PDT 24
Finished Jun 25 05:49:26 PM PDT 24
Peak memory 216244 kb
Host smart-c1063899-212e-43f2-8257-fe6570da37df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130561382 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.130561382
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3250848220
Short name T247
Test name
Test status
Simulation time 40808413 ps
CPU time 1.28 seconds
Started Jun 25 05:49:21 PM PDT 24
Finished Jun 25 05:49:24 PM PDT 24
Peak memory 217276 kb
Host smart-6c21e11f-8448-4aa1-8001-2df925271786
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250848220 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3250848220
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.961125600
Short name T572
Test name
Test status
Simulation time 198785001 ps
CPU time 1.11 seconds
Started Jun 25 05:49:12 PM PDT 24
Finished Jun 25 05:49:15 PM PDT 24
Peak memory 219992 kb
Host smart-ec8d24b9-e908-44fd-b4c2-177782adc7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961125600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.961125600
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2216768677
Short name T805
Test name
Test status
Simulation time 66800146 ps
CPU time 1.21 seconds
Started Jun 25 05:49:12 PM PDT 24
Finished Jun 25 05:49:16 PM PDT 24
Peak memory 217756 kb
Host smart-61bc4630-9697-45c3-b3be-3542614df25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216768677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2216768677
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.1445702249
Short name T466
Test name
Test status
Simulation time 36523746 ps
CPU time 1.09 seconds
Started Jun 25 05:49:15 PM PDT 24
Finished Jun 25 05:49:17 PM PDT 24
Peak memory 224344 kb
Host smart-4f01900c-f341-4e5a-8ada-7962dfa3415c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445702249 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1445702249
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.830642791
Short name T436
Test name
Test status
Simulation time 67970596 ps
CPU time 0.88 seconds
Started Jun 25 05:49:12 PM PDT 24
Finished Jun 25 05:49:15 PM PDT 24
Peak memory 215644 kb
Host smart-42a94034-76bb-4dbc-9e6b-a6c4034e3ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830642791 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.830642791
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1824281649
Short name T487
Test name
Test status
Simulation time 231897852 ps
CPU time 1.64 seconds
Started Jun 25 05:49:10 PM PDT 24
Finished Jun 25 05:49:13 PM PDT 24
Peak memory 217744 kb
Host smart-c9a5374c-171f-4789-888a-21e6d5acc7ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824281649 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1824281649
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/290.edn_genbits.1406077651
Short name T610
Test name
Test status
Simulation time 168582554 ps
CPU time 1.15 seconds
Started Jun 25 05:51:20 PM PDT 24
Finished Jun 25 05:51:23 PM PDT 24
Peak memory 217724 kb
Host smart-74a6be66-5c2e-43ad-bf3a-732f940a01ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406077651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1406077651
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2547218768
Short name T643
Test name
Test status
Simulation time 47342391 ps
CPU time 1.23 seconds
Started Jun 25 05:51:17 PM PDT 24
Finished Jun 25 05:51:19 PM PDT 24
Peak memory 217584 kb
Host smart-367953f0-b86b-44f3-86bf-9f6d79e3b1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547218768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2547218768
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1413011672
Short name T592
Test name
Test status
Simulation time 38915828 ps
CPU time 1.58 seconds
Started Jun 25 05:51:20 PM PDT 24
Finished Jun 25 05:51:23 PM PDT 24
Peak memory 219860 kb
Host smart-d73b4f46-0996-4c7c-981d-5393db80d354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413011672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1413011672
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3343673041
Short name T103
Test name
Test status
Simulation time 95530036 ps
CPU time 1.49 seconds
Started Jun 25 05:51:16 PM PDT 24
Finished Jun 25 05:51:19 PM PDT 24
Peak memory 219248 kb
Host smart-5e870bec-2584-404c-bb45-efcc251d2078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343673041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3343673041
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3542676154
Short name T321
Test name
Test status
Simulation time 49583910 ps
CPU time 1.21 seconds
Started Jun 25 05:51:18 PM PDT 24
Finished Jun 25 05:51:20 PM PDT 24
Peak memory 217736 kb
Host smart-5cbd5a7b-3131-4749-9e20-4dd2c44c29ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542676154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3542676154
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1032696722
Short name T625
Test name
Test status
Simulation time 86461647 ps
CPU time 1.22 seconds
Started Jun 25 05:51:23 PM PDT 24
Finished Jun 25 05:51:26 PM PDT 24
Peak memory 217712 kb
Host smart-991b19bf-a650-4a34-b62e-7875043b98e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032696722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1032696722
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1153799403
Short name T739
Test name
Test status
Simulation time 41765407 ps
CPU time 1.67 seconds
Started Jun 25 05:51:18 PM PDT 24
Finished Jun 25 05:51:22 PM PDT 24
Peak memory 218712 kb
Host smart-9b9b787c-54ea-4e10-bd8e-b5f89fef03a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153799403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1153799403
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2397679134
Short name T664
Test name
Test status
Simulation time 73428163 ps
CPU time 1.2 seconds
Started Jun 25 05:51:20 PM PDT 24
Finished Jun 25 05:51:22 PM PDT 24
Peak memory 219248 kb
Host smart-224de071-33cc-4cc0-8920-4b5bbbccb2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397679134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2397679134
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.241666199
Short name T915
Test name
Test status
Simulation time 88844298 ps
CPU time 1.21 seconds
Started Jun 25 05:51:17 PM PDT 24
Finished Jun 25 05:51:20 PM PDT 24
Peak memory 217548 kb
Host smart-94d73075-3a29-4fa0-bea5-be5b3db9ceb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241666199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.241666199
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.536590663
Short name T860
Test name
Test status
Simulation time 59014014 ps
CPU time 1.03 seconds
Started Jun 25 05:51:18 PM PDT 24
Finished Jun 25 05:51:20 PM PDT 24
Peak memory 217664 kb
Host smart-04346141-06fe-4f2d-a8df-45265e63ff51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536590663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.536590663
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1869135922
Short name T31
Test name
Test status
Simulation time 70662516 ps
CPU time 1.17 seconds
Started Jun 25 05:48:13 PM PDT 24
Finished Jun 25 05:48:16 PM PDT 24
Peak memory 219928 kb
Host smart-8d1d0c91-098e-4f73-8516-facd754af40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869135922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1869135922
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.726495548
Short name T508
Test name
Test status
Simulation time 29953667 ps
CPU time 0.97 seconds
Started Jun 25 05:48:14 PM PDT 24
Finished Jun 25 05:48:17 PM PDT 24
Peak memory 215468 kb
Host smart-a0893ac7-0a92-4297-a938-366f0c9a2d95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726495548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.726495548
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3830953662
Short name T584
Test name
Test status
Simulation time 165402797 ps
CPU time 1.03 seconds
Started Jun 25 05:48:14 PM PDT 24
Finished Jun 25 05:48:17 PM PDT 24
Peak memory 218884 kb
Host smart-1fc1b193-2b35-48b3-bcfa-87b7e122f11a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830953662 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3830953662
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.152445614
Short name T767
Test name
Test status
Simulation time 46230057 ps
CPU time 0.91 seconds
Started Jun 25 05:48:16 PM PDT 24
Finished Jun 25 05:48:19 PM PDT 24
Peak memory 220004 kb
Host smart-37915bd3-0b73-4282-a569-24c21835eb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152445614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.152445614
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_intr.2610319768
Short name T978
Test name
Test status
Simulation time 47301441 ps
CPU time 0.99 seconds
Started Jun 25 05:48:13 PM PDT 24
Finished Jun 25 05:48:15 PM PDT 24
Peak memory 224180 kb
Host smart-97282a38-e36e-4b83-ac7b-a009e1ccc258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610319768 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2610319768
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.3732898036
Short name T750
Test name
Test status
Simulation time 30775028 ps
CPU time 0.96 seconds
Started Jun 25 05:48:15 PM PDT 24
Finished Jun 25 05:48:18 PM PDT 24
Peak memory 207388 kb
Host smart-6c7b04e0-17f4-4f35-9ecd-79ea5d8bd1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732898036 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3732898036
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.2186486613
Short name T372
Test name
Test status
Simulation time 30175923 ps
CPU time 1.04 seconds
Started Jun 25 05:48:14 PM PDT 24
Finished Jun 25 05:48:17 PM PDT 24
Peak memory 215636 kb
Host smart-2a29d349-e21f-4242-867f-25ef44cfea5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186486613 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2186486613
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3869199587
Short name T429
Test name
Test status
Simulation time 164679753 ps
CPU time 2.18 seconds
Started Jun 25 05:48:16 PM PDT 24
Finished Jun 25 05:48:20 PM PDT 24
Peak memory 217648 kb
Host smart-7e5e4da7-e091-4c4e-99a6-95ad2f132869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869199587 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3869199587
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.4176196524
Short name T669
Test name
Test status
Simulation time 25704285651 ps
CPU time 167.57 seconds
Started Jun 25 05:48:12 PM PDT 24
Finished Jun 25 05:51:01 PM PDT 24
Peak memory 223772 kb
Host smart-34498fb0-66b5-499f-8b83-ed854071c90b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176196524 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.4176196524
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert_test.3246745563
Short name T416
Test name
Test status
Simulation time 35952940 ps
CPU time 0.83 seconds
Started Jun 25 05:49:19 PM PDT 24
Finished Jun 25 05:49:21 PM PDT 24
Peak memory 207076 kb
Host smart-4f6730f2-5a90-487b-bd22-677e6835b51a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246745563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3246745563
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1679684673
Short name T844
Test name
Test status
Simulation time 16879308 ps
CPU time 0.9 seconds
Started Jun 25 05:49:21 PM PDT 24
Finished Jun 25 05:49:24 PM PDT 24
Peak memory 216572 kb
Host smart-313e2219-06ed-474a-8a81-068de9118664
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679684673 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1679684673
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.890669633
Short name T155
Test name
Test status
Simulation time 51686108 ps
CPU time 1.11 seconds
Started Jun 25 05:49:20 PM PDT 24
Finished Jun 25 05:49:23 PM PDT 24
Peak memory 217128 kb
Host smart-0b8e316a-e7ae-4660-a406-48cf40cbdf00
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890669633 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.890669633
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3783727691
Short name T576
Test name
Test status
Simulation time 22879132 ps
CPU time 0.93 seconds
Started Jun 25 05:49:20 PM PDT 24
Finished Jun 25 05:49:22 PM PDT 24
Peak memory 218760 kb
Host smart-a18a6fd9-259b-4ba6-9f95-732ff8f25e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783727691 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3783727691
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3445569075
Short name T539
Test name
Test status
Simulation time 54116054 ps
CPU time 1.42 seconds
Started Jun 25 05:49:22 PM PDT 24
Finished Jun 25 05:49:26 PM PDT 24
Peak memory 220332 kb
Host smart-5b38a5ad-1990-427b-a9e9-d40b2b26fe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445569075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3445569075
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2978322888
Short name T440
Test name
Test status
Simulation time 23208581 ps
CPU time 1.14 seconds
Started Jun 25 05:49:23 PM PDT 24
Finished Jun 25 05:49:27 PM PDT 24
Peak memory 215872 kb
Host smart-1f72695d-7a4c-4932-9ad6-0369bd85fd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978322888 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2978322888
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3943481301
Short name T824
Test name
Test status
Simulation time 52980157 ps
CPU time 0.88 seconds
Started Jun 25 05:49:20 PM PDT 24
Finished Jun 25 05:49:23 PM PDT 24
Peak memory 215604 kb
Host smart-40ac86c0-b827-43e3-b6c1-55bb296892d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943481301 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3943481301
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1369562557
Short name T73
Test name
Test status
Simulation time 331661566 ps
CPU time 2.17 seconds
Started Jun 25 05:49:20 PM PDT 24
Finished Jun 25 05:49:24 PM PDT 24
Peak memory 217860 kb
Host smart-30f2c650-537c-4a7f-8ab5-d1833243e6f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369562557 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1369562557
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_alert.751583744
Short name T866
Test name
Test status
Simulation time 54987186 ps
CPU time 1.14 seconds
Started Jun 25 05:49:22 PM PDT 24
Finished Jun 25 05:49:26 PM PDT 24
Peak memory 220160 kb
Host smart-3c8daf8f-2aa4-45b2-9667-7d56df854dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751583744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.751583744
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1282026197
Short name T483
Test name
Test status
Simulation time 43867845 ps
CPU time 1.37 seconds
Started Jun 25 05:49:23 PM PDT 24
Finished Jun 25 05:49:27 PM PDT 24
Peak memory 207156 kb
Host smart-37a21a11-36a2-45e9-9edb-801b0a2e235c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282026197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1282026197
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2056779050
Short name T497
Test name
Test status
Simulation time 19253830 ps
CPU time 0.92 seconds
Started Jun 25 05:49:21 PM PDT 24
Finished Jun 25 05:49:25 PM PDT 24
Peak memory 215684 kb
Host smart-c65bbc04-def0-4016-97cd-4b918ebbb762
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056779050 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2056779050
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.2271151665
Short name T159
Test name
Test status
Simulation time 37332448 ps
CPU time 1.15 seconds
Started Jun 25 05:49:22 PM PDT 24
Finished Jun 25 05:49:26 PM PDT 24
Peak memory 220844 kb
Host smart-b4d139e5-30d7-4576-8b1c-4437de5a57ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271151665 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2271151665
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.900310467
Short name T482
Test name
Test status
Simulation time 112784122 ps
CPU time 1.73 seconds
Started Jun 25 05:49:23 PM PDT 24
Finished Jun 25 05:49:27 PM PDT 24
Peak memory 219488 kb
Host smart-baf6b416-753c-4f22-ae7a-623116eeca0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900310467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.900310467
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2734486466
Short name T98
Test name
Test status
Simulation time 21736591 ps
CPU time 1.06 seconds
Started Jun 25 05:49:22 PM PDT 24
Finished Jun 25 05:49:26 PM PDT 24
Peak memory 215880 kb
Host smart-4cad0c9b-e284-4a32-a526-4a0bcef4260f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734486466 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2734486466
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.50876790
Short name T619
Test name
Test status
Simulation time 14461708 ps
CPU time 0.97 seconds
Started Jun 25 05:49:21 PM PDT 24
Finished Jun 25 05:49:24 PM PDT 24
Peak memory 215656 kb
Host smart-70125503-dbc4-4c40-86b8-2380c56fd844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50876790 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.50876790
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1998800280
Short name T252
Test name
Test status
Simulation time 680143671 ps
CPU time 5.16 seconds
Started Jun 25 05:49:20 PM PDT 24
Finished Jun 25 05:49:27 PM PDT 24
Peak memory 220696 kb
Host smart-d67d468d-73b3-4c8f-a444-a50225e6bb1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998800280 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1998800280
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1092986735
Short name T241
Test name
Test status
Simulation time 98490440194 ps
CPU time 860.2 seconds
Started Jun 25 05:49:21 PM PDT 24
Finished Jun 25 06:03:44 PM PDT 24
Peak memory 224088 kb
Host smart-ddd7e40f-13b5-4f74-a4ac-77ab9ec7c9ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092986735 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1092986735
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2225993365
Short name T727
Test name
Test status
Simulation time 40493044 ps
CPU time 1.13 seconds
Started Jun 25 05:49:19 PM PDT 24
Finished Jun 25 05:49:22 PM PDT 24
Peak memory 219024 kb
Host smart-99a8e95a-0330-452c-8729-9a747057f69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225993365 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2225993365
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2286878206
Short name T115
Test name
Test status
Simulation time 58704364 ps
CPU time 1.03 seconds
Started Jun 25 05:49:20 PM PDT 24
Finished Jun 25 05:49:22 PM PDT 24
Peak memory 215528 kb
Host smart-b0ac014c-f766-46cc-9a61-bcfa5dc9fee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286878206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2286878206
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.682130306
Short name T796
Test name
Test status
Simulation time 18960235 ps
CPU time 0.93 seconds
Started Jun 25 05:49:19 PM PDT 24
Finished Jun 25 05:49:21 PM PDT 24
Peak memory 216540 kb
Host smart-2f451462-03f4-48fa-8747-fbca66a0a1eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682130306 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.682130306
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1455679419
Short name T808
Test name
Test status
Simulation time 288829211 ps
CPU time 1.09 seconds
Started Jun 25 05:49:21 PM PDT 24
Finished Jun 25 05:49:25 PM PDT 24
Peak memory 220012 kb
Host smart-195cbe90-2e79-4ebf-b3a4-e5749904fd76
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455679419 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1455679419
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.573895183
Short name T955
Test name
Test status
Simulation time 38796271 ps
CPU time 1.44 seconds
Started Jun 25 05:49:21 PM PDT 24
Finished Jun 25 05:49:26 PM PDT 24
Peak memory 226020 kb
Host smart-0ed6c365-e5d7-4d35-bfa3-56bf7b98049e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573895183 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.573895183
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1801728281
Short name T432
Test name
Test status
Simulation time 36526771 ps
CPU time 1.36 seconds
Started Jun 25 05:49:21 PM PDT 24
Finished Jun 25 05:49:24 PM PDT 24
Peak memory 217600 kb
Host smart-9bcb619e-0faf-4892-813b-02b88d5c3186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801728281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1801728281
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1728192831
Short name T954
Test name
Test status
Simulation time 22830924 ps
CPU time 1.12 seconds
Started Jun 25 05:49:19 PM PDT 24
Finished Jun 25 05:49:21 PM PDT 24
Peak memory 215764 kb
Host smart-6501c268-d4d5-464a-aba8-e62a2adc37dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728192831 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1728192831
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.625136990
Short name T467
Test name
Test status
Simulation time 26396661 ps
CPU time 1.02 seconds
Started Jun 25 05:49:20 PM PDT 24
Finished Jun 25 05:49:23 PM PDT 24
Peak memory 215636 kb
Host smart-809825e5-e7f2-4cc7-a7c0-4dcdfa7afd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625136990 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.625136990
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2574173744
Short name T865
Test name
Test status
Simulation time 957811365 ps
CPU time 5.16 seconds
Started Jun 25 05:49:20 PM PDT 24
Finished Jun 25 05:49:27 PM PDT 24
Peak memory 215636 kb
Host smart-97ae4648-cfe0-4251-a99c-2e24ba2ab60d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574173744 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2574173744
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2848884927
Short name T246
Test name
Test status
Simulation time 98424506304 ps
CPU time 2081.16 seconds
Started Jun 25 05:49:23 PM PDT 24
Finished Jun 25 06:24:07 PM PDT 24
Peak memory 226972 kb
Host smart-b595019a-4cd8-48aa-ae79-6594bccd2ae2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848884927 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2848884927
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3417976351
Short name T710
Test name
Test status
Simulation time 29690051 ps
CPU time 1.25 seconds
Started Jun 25 05:49:19 PM PDT 24
Finished Jun 25 05:49:21 PM PDT 24
Peak memory 220060 kb
Host smart-e9cdec67-d974-4350-bb08-648c2d4c77b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417976351 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3417976351
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1611930714
Short name T908
Test name
Test status
Simulation time 50549590 ps
CPU time 0.85 seconds
Started Jun 25 05:49:23 PM PDT 24
Finished Jun 25 05:49:26 PM PDT 24
Peak memory 207064 kb
Host smart-a85e1c81-9a77-4bc9-99ed-bed8b4720508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611930714 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1611930714
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1083551309
Short name T925
Test name
Test status
Simulation time 96569645 ps
CPU time 1.09 seconds
Started Jun 25 05:49:21 PM PDT 24
Finished Jun 25 05:49:25 PM PDT 24
Peak memory 218956 kb
Host smart-a05427df-9eac-4cc9-8d8d-3059f65d5077
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083551309 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1083551309
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3966680427
Short name T806
Test name
Test status
Simulation time 21529739 ps
CPU time 1.15 seconds
Started Jun 25 05:49:20 PM PDT 24
Finished Jun 25 05:49:23 PM PDT 24
Peak memory 229828 kb
Host smart-b3e9b02a-aea3-4a1f-9f9d-3b851bcf3245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966680427 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3966680427
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.59790443
Short name T569
Test name
Test status
Simulation time 40372920 ps
CPU time 1.39 seconds
Started Jun 25 05:49:23 PM PDT 24
Finished Jun 25 05:49:27 PM PDT 24
Peak memory 217700 kb
Host smart-d31b4dbc-109e-45ef-9ad5-aa0350952599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59790443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.59790443
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.631216807
Short name T261
Test name
Test status
Simulation time 30230240 ps
CPU time 0.99 seconds
Started Jun 25 05:49:22 PM PDT 24
Finished Jun 25 05:49:26 PM PDT 24
Peak memory 215892 kb
Host smart-58cf0fdf-6b47-49c2-997c-2d9d2e884767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631216807 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.631216807
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1974211356
Short name T704
Test name
Test status
Simulation time 14622516 ps
CPU time 0.96 seconds
Started Jun 25 05:49:20 PM PDT 24
Finished Jun 25 05:49:22 PM PDT 24
Peak memory 207464 kb
Host smart-f8f88a88-ae6d-4911-b400-8df113c4a5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974211356 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1974211356
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1000488628
Short name T851
Test name
Test status
Simulation time 297535013 ps
CPU time 5.96 seconds
Started Jun 25 05:49:21 PM PDT 24
Finished Jun 25 05:49:30 PM PDT 24
Peak memory 217716 kb
Host smart-29913f10-482a-45e0-858a-2fbcca1a3fde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000488628 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1000488628
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.901661064
Short name T992
Test name
Test status
Simulation time 39705000339 ps
CPU time 860.25 seconds
Started Jun 25 05:49:21 PM PDT 24
Finished Jun 25 06:03:43 PM PDT 24
Peak memory 218516 kb
Host smart-161760a5-2230-4a70-90a1-10c8fadf79cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901661064 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.901661064
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3584345914
Short name T248
Test name
Test status
Simulation time 34123117 ps
CPU time 1.44 seconds
Started Jun 25 05:49:23 PM PDT 24
Finished Jun 25 05:49:27 PM PDT 24
Peak memory 220080 kb
Host smart-0368bc88-8a1b-4c03-9a4f-711134ee6112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584345914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3584345914
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2346403403
Short name T639
Test name
Test status
Simulation time 23555033 ps
CPU time 1.08 seconds
Started Jun 25 05:49:23 PM PDT 24
Finished Jun 25 05:49:26 PM PDT 24
Peak memory 207064 kb
Host smart-18d407d6-e3d7-4843-b504-d006837718e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346403403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2346403403
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1967664237
Short name T187
Test name
Test status
Simulation time 18595090 ps
CPU time 0.9 seconds
Started Jun 25 05:49:21 PM PDT 24
Finished Jun 25 05:49:24 PM PDT 24
Peak memory 216520 kb
Host smart-7dd15e3b-d1d1-49f4-9017-34b2bdce1ca2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967664237 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1967664237
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2250423536
Short name T219
Test name
Test status
Simulation time 72346510 ps
CPU time 1.18 seconds
Started Jun 25 05:49:22 PM PDT 24
Finished Jun 25 05:49:26 PM PDT 24
Peak memory 217228 kb
Host smart-321e719c-e41f-46ae-a72b-7756cd2a70f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250423536 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2250423536
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.116045018
Short name T128
Test name
Test status
Simulation time 32390647 ps
CPU time 1.03 seconds
Started Jun 25 05:49:23 PM PDT 24
Finished Jun 25 05:49:26 PM PDT 24
Peak memory 219884 kb
Host smart-ccd89653-ad1f-4f4a-baad-5d12f7e1ed1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116045018 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.116045018
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1431958615
Short name T859
Test name
Test status
Simulation time 63053519 ps
CPU time 1.78 seconds
Started Jun 25 05:49:22 PM PDT 24
Finished Jun 25 05:49:26 PM PDT 24
Peak memory 218668 kb
Host smart-0b027631-cf88-4e34-92a8-894d8b154ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431958615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1431958615
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.512355005
Short name T652
Test name
Test status
Simulation time 58411938 ps
CPU time 0.84 seconds
Started Jun 25 05:49:21 PM PDT 24
Finished Jun 25 05:49:25 PM PDT 24
Peak memory 215564 kb
Host smart-d058e1ca-f0d7-46f7-9e24-34f1e3930607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512355005 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.512355005
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.792937493
Short name T725
Test name
Test status
Simulation time 22374042 ps
CPU time 0.91 seconds
Started Jun 25 05:49:21 PM PDT 24
Finished Jun 25 05:49:25 PM PDT 24
Peak memory 215576 kb
Host smart-9abcbd6e-965a-4560-af46-f4513483ba6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792937493 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.792937493
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1913347109
Short name T936
Test name
Test status
Simulation time 190599062 ps
CPU time 1.78 seconds
Started Jun 25 05:49:20 PM PDT 24
Finished Jun 25 05:49:23 PM PDT 24
Peak memory 217720 kb
Host smart-34a9c370-2ad7-46ec-80af-da9b1e92660e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913347109 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1913347109
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2205117088
Short name T712
Test name
Test status
Simulation time 52328349758 ps
CPU time 1019.25 seconds
Started Jun 25 05:49:21 PM PDT 24
Finished Jun 25 06:06:22 PM PDT 24
Peak memory 224044 kb
Host smart-3eb9101f-d626-422c-860c-afe89486c99c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205117088 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2205117088
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.971474062
Short name T921
Test name
Test status
Simulation time 26457401 ps
CPU time 1.29 seconds
Started Jun 25 05:49:32 PM PDT 24
Finished Jun 25 05:49:34 PM PDT 24
Peak memory 219028 kb
Host smart-324967e0-20c5-4b3e-b4a0-e132d6f056de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971474062 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.971474062
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.385901895
Short name T581
Test name
Test status
Simulation time 16919146 ps
CPU time 0.97 seconds
Started Jun 25 05:49:31 PM PDT 24
Finished Jun 25 05:49:33 PM PDT 24
Peak memory 207004 kb
Host smart-89b8b09c-efb2-4f78-819b-f24fb0358286
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385901895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.385901895
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2399580775
Short name T602
Test name
Test status
Simulation time 18214775 ps
CPU time 0.86 seconds
Started Jun 25 05:49:28 PM PDT 24
Finished Jun 25 05:49:30 PM PDT 24
Peak memory 216656 kb
Host smart-6e034d22-ea6a-4774-ad48-4717f16f4452
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399580775 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2399580775
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.738307907
Short name T130
Test name
Test status
Simulation time 41011631 ps
CPU time 1.12 seconds
Started Jun 25 05:49:29 PM PDT 24
Finished Jun 25 05:49:31 PM PDT 24
Peak memory 217196 kb
Host smart-12cfe8aa-da55-44ec-951b-aa4e02287096
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738307907 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.738307907
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1718394273
Short name T769
Test name
Test status
Simulation time 20648777 ps
CPU time 1 seconds
Started Jun 25 05:49:31 PM PDT 24
Finished Jun 25 05:49:33 PM PDT 24
Peak memory 218652 kb
Host smart-46a89c0a-1144-4ade-8b40-a2bc0eaf0b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718394273 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1718394273
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1360605292
Short name T423
Test name
Test status
Simulation time 51443938 ps
CPU time 1.18 seconds
Started Jun 25 05:49:30 PM PDT 24
Finished Jun 25 05:49:32 PM PDT 24
Peak memory 220216 kb
Host smart-9e2fafeb-c36f-41dc-a589-dbb2a0b45f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360605292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1360605292
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.4150489411
Short name T656
Test name
Test status
Simulation time 20247148 ps
CPU time 1.08 seconds
Started Jun 25 05:49:30 PM PDT 24
Finished Jun 25 05:49:32 PM PDT 24
Peak memory 216244 kb
Host smart-094e1abc-4855-4d54-a746-3bd143f8723d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150489411 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.4150489411
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1791292828
Short name T258
Test name
Test status
Simulation time 26451017 ps
CPU time 0.96 seconds
Started Jun 25 05:49:20 PM PDT 24
Finished Jun 25 05:49:23 PM PDT 24
Peak memory 215644 kb
Host smart-901b60f8-2b72-4844-b77f-fa2b68440c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791292828 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1791292828
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.393773129
Short name T490
Test name
Test status
Simulation time 211747589 ps
CPU time 4.6 seconds
Started Jun 25 05:49:29 PM PDT 24
Finished Jun 25 05:49:35 PM PDT 24
Peak memory 217508 kb
Host smart-f34e413c-a5e7-4038-809d-4a9e4e18f354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393773129 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.393773129
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.603136201
Short name T833
Test name
Test status
Simulation time 106459751584 ps
CPU time 2528.84 seconds
Started Jun 25 05:49:28 PM PDT 24
Finished Jun 25 06:31:38 PM PDT 24
Peak memory 229256 kb
Host smart-6e0bfda0-4d6a-4cc9-8dc7-54ca0f742e8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603136201 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.603136201
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3678960687
Short name T963
Test name
Test status
Simulation time 23985799 ps
CPU time 1.22 seconds
Started Jun 25 05:49:34 PM PDT 24
Finished Jun 25 05:49:36 PM PDT 24
Peak memory 218960 kb
Host smart-51c62726-17e1-4119-8449-0e4e16f89b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678960687 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3678960687
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1058612070
Short name T869
Test name
Test status
Simulation time 47417849 ps
CPU time 0.93 seconds
Started Jun 25 05:49:31 PM PDT 24
Finished Jun 25 05:49:33 PM PDT 24
Peak memory 207084 kb
Host smart-d4d6a014-2bc2-4365-9326-f2be7bfec026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058612070 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1058612070
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2918567602
Short name T745
Test name
Test status
Simulation time 28075816 ps
CPU time 0.86 seconds
Started Jun 25 05:49:30 PM PDT 24
Finished Jun 25 05:49:32 PM PDT 24
Peak memory 215740 kb
Host smart-e303346b-bc1b-4cb5-ada3-d880eb1d9ab7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918567602 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2918567602
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3599317859
Short name T160
Test name
Test status
Simulation time 65610211 ps
CPU time 1.11 seconds
Started Jun 25 05:49:33 PM PDT 24
Finished Jun 25 05:49:35 PM PDT 24
Peak memory 217136 kb
Host smart-4d4228d7-c925-43b0-9ad7-07b072354f73
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599317859 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3599317859
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1853447684
Short name T79
Test name
Test status
Simulation time 28732443 ps
CPU time 0.86 seconds
Started Jun 25 05:49:31 PM PDT 24
Finished Jun 25 05:49:34 PM PDT 24
Peak memory 218664 kb
Host smart-6142e75c-f03c-4cf6-84dc-2744e5642fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853447684 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1853447684
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.86058768
Short name T836
Test name
Test status
Simulation time 73582364 ps
CPU time 1.23 seconds
Started Jun 25 05:49:33 PM PDT 24
Finished Jun 25 05:49:35 PM PDT 24
Peak memory 218856 kb
Host smart-8e72196b-613b-453b-895e-2f11ab008b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86058768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.86058768
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2170196149
Short name T59
Test name
Test status
Simulation time 22446686 ps
CPU time 1.26 seconds
Started Jun 25 05:49:29 PM PDT 24
Finished Jun 25 05:49:32 PM PDT 24
Peak memory 224348 kb
Host smart-9f3a98f5-9fa5-4c83-a8b0-3ae51f27ca85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170196149 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2170196149
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1629191410
Short name T426
Test name
Test status
Simulation time 18110383 ps
CPU time 1.01 seconds
Started Jun 25 05:49:28 PM PDT 24
Finished Jun 25 05:49:30 PM PDT 24
Peak memory 215648 kb
Host smart-e84b648c-06ab-41db-8ff0-7971a266929a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629191410 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1629191410
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2285769415
Short name T326
Test name
Test status
Simulation time 225558554 ps
CPU time 2.11 seconds
Started Jun 25 05:49:32 PM PDT 24
Finished Jun 25 05:49:36 PM PDT 24
Peak memory 215660 kb
Host smart-29bc804f-1d4b-4d62-a89c-8f70a549d57f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285769415 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2285769415
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1933260628
Short name T239
Test name
Test status
Simulation time 19106873319 ps
CPU time 365.9 seconds
Started Jun 25 05:49:30 PM PDT 24
Finished Jun 25 05:55:37 PM PDT 24
Peak memory 218880 kb
Host smart-e37d49c4-409b-4f4c-aa9b-eb3e573307c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933260628 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1933260628
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3659290875
Short name T803
Test name
Test status
Simulation time 77465835 ps
CPU time 1.13 seconds
Started Jun 25 05:49:33 PM PDT 24
Finished Jun 25 05:49:36 PM PDT 24
Peak memory 219380 kb
Host smart-1f96e6b6-12f4-4b16-b40d-c500f81c0106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659290875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3659290875
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2824394379
Short name T593
Test name
Test status
Simulation time 19822035 ps
CPU time 0.97 seconds
Started Jun 25 05:49:31 PM PDT 24
Finished Jun 25 05:49:34 PM PDT 24
Peak memory 207068 kb
Host smart-f6d38a94-06ad-45fe-9f00-634fec45ce31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824394379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2824394379
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3728137658
Short name T531
Test name
Test status
Simulation time 32275203 ps
CPU time 0.85 seconds
Started Jun 25 05:49:29 PM PDT 24
Finished Jun 25 05:49:31 PM PDT 24
Peak memory 216360 kb
Host smart-66786a96-635b-44f6-8fe5-e33bf92f99b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728137658 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3728137658
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3986973591
Short name T415
Test name
Test status
Simulation time 156168804 ps
CPU time 0.97 seconds
Started Jun 25 05:49:28 PM PDT 24
Finished Jun 25 05:49:29 PM PDT 24
Peak memory 217096 kb
Host smart-43ac26fe-5e5b-4253-8713-034f0b08cc7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986973591 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3986973591
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1018108981
Short name T190
Test name
Test status
Simulation time 23836849 ps
CPU time 1.05 seconds
Started Jun 25 05:49:30 PM PDT 24
Finished Jun 25 05:49:33 PM PDT 24
Peak memory 224284 kb
Host smart-bdd3700e-e3fc-4c91-a6cd-d96dec7f5edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018108981 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1018108981
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.539238644
Short name T781
Test name
Test status
Simulation time 38517906 ps
CPU time 1.37 seconds
Started Jun 25 05:49:29 PM PDT 24
Finished Jun 25 05:49:31 PM PDT 24
Peak memory 217732 kb
Host smart-6c9d9829-b4a6-4239-bdcd-3b900ff72194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539238644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.539238644
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3828714868
Short name T979
Test name
Test status
Simulation time 56204605 ps
CPU time 0.92 seconds
Started Jun 25 05:49:29 PM PDT 24
Finished Jun 25 05:49:31 PM PDT 24
Peak memory 215576 kb
Host smart-66bdee62-b15e-417d-83cd-ea3829825b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828714868 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3828714868
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3716538203
Short name T368
Test name
Test status
Simulation time 51182950 ps
CPU time 0.96 seconds
Started Jun 25 05:49:34 PM PDT 24
Finished Jun 25 05:49:36 PM PDT 24
Peak memory 215632 kb
Host smart-18233804-e8f3-40ea-8854-0ed154789488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716538203 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3716538203
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3363908823
Short name T653
Test name
Test status
Simulation time 337817407 ps
CPU time 2.17 seconds
Started Jun 25 05:49:29 PM PDT 24
Finished Jun 25 05:49:33 PM PDT 24
Peak memory 215664 kb
Host smart-6c81b1a3-0dd5-44e6-99b8-1bcedb4e9af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363908823 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3363908823
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.305827039
Short name T873
Test name
Test status
Simulation time 184623297364 ps
CPU time 488.02 seconds
Started Jun 25 05:49:30 PM PDT 24
Finished Jun 25 05:57:39 PM PDT 24
Peak memory 220088 kb
Host smart-971c4eb0-3f51-40df-9588-9ddd5065870b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305827039 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.305827039
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1897157126
Short name T227
Test name
Test status
Simulation time 32303253 ps
CPU time 1.38 seconds
Started Jun 25 05:49:31 PM PDT 24
Finished Jun 25 05:49:34 PM PDT 24
Peak memory 216028 kb
Host smart-024c71e4-35ae-40b2-a6c5-9def24878770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897157126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1897157126
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3155127615
Short name T387
Test name
Test status
Simulation time 51015531 ps
CPU time 0.9 seconds
Started Jun 25 05:49:31 PM PDT 24
Finished Jun 25 05:49:33 PM PDT 24
Peak memory 215508 kb
Host smart-34811f2a-fcf3-4c31-b508-f0da4a2cb110
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155127615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3155127615
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3668845774
Short name T868
Test name
Test status
Simulation time 14384005 ps
CPU time 0.95 seconds
Started Jun 25 05:49:34 PM PDT 24
Finished Jun 25 05:49:36 PM PDT 24
Peak memory 216688 kb
Host smart-a1f5166d-dc1d-40e5-8a55-9a7c0c474fec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668845774 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3668845774
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2249797626
Short name T702
Test name
Test status
Simulation time 24485516 ps
CPU time 0.97 seconds
Started Jun 25 05:49:30 PM PDT 24
Finished Jun 25 05:49:32 PM PDT 24
Peak memory 217244 kb
Host smart-202989c4-9ac5-4b06-8c53-8d8ec5b4a368
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249797626 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2249797626
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1229158921
Short name T16
Test name
Test status
Simulation time 21034762 ps
CPU time 1.02 seconds
Started Jun 25 05:49:33 PM PDT 24
Finished Jun 25 05:49:35 PM PDT 24
Peak memory 224264 kb
Host smart-2e3f27bc-3114-4066-b0cd-64cd5e75ab04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229158921 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1229158921
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3601184783
Short name T694
Test name
Test status
Simulation time 82849010 ps
CPU time 1.39 seconds
Started Jun 25 05:49:29 PM PDT 24
Finished Jun 25 05:49:31 PM PDT 24
Peak memory 218828 kb
Host smart-6ea8c43e-98c9-491a-8a05-a94e7b2004e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601184783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3601184783
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1657806787
Short name T63
Test name
Test status
Simulation time 20550776 ps
CPU time 1.25 seconds
Started Jun 25 05:49:31 PM PDT 24
Finished Jun 25 05:49:33 PM PDT 24
Peak memory 224452 kb
Host smart-e2b438f0-0c1a-446f-9034-7db6b5d8292d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657806787 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1657806787
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3813954655
Short name T425
Test name
Test status
Simulation time 40460607 ps
CPU time 0.89 seconds
Started Jun 25 05:49:31 PM PDT 24
Finished Jun 25 05:49:34 PM PDT 24
Peak memory 215660 kb
Host smart-fa06ab26-d855-45c6-ba44-aadd92dda297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813954655 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3813954655
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2673220
Short name T519
Test name
Test status
Simulation time 925152014 ps
CPU time 2.29 seconds
Started Jun 25 05:49:28 PM PDT 24
Finished Jun 25 05:49:32 PM PDT 24
Peak memory 217496 kb
Host smart-7481ad42-dda2-4dff-9016-3e57aa04037d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673220 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2673220
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3538988320
Short name T594
Test name
Test status
Simulation time 49016176042 ps
CPU time 640.38 seconds
Started Jun 25 05:49:31 PM PDT 24
Finished Jun 25 06:00:13 PM PDT 24
Peak memory 224120 kb
Host smart-7be27256-4ea0-4fde-8a32-c405d5f33e50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538988320 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3538988320
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2140498819
Short name T29
Test name
Test status
Simulation time 29718162 ps
CPU time 1.29 seconds
Started Jun 25 05:49:28 PM PDT 24
Finished Jun 25 05:49:30 PM PDT 24
Peak memory 219928 kb
Host smart-b5f344b4-0d7c-4342-9e9e-6dd8e1267c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140498819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2140498819
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.4194897843
Short name T705
Test name
Test status
Simulation time 13402965 ps
CPU time 0.96 seconds
Started Jun 25 05:49:38 PM PDT 24
Finished Jun 25 05:49:40 PM PDT 24
Peak memory 215140 kb
Host smart-0898098f-21ab-466e-b532-5f83f6e0a650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194897843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.4194897843
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1862785301
Short name T792
Test name
Test status
Simulation time 11854514 ps
CPU time 0.87 seconds
Started Jun 25 05:49:28 PM PDT 24
Finished Jun 25 05:49:29 PM PDT 24
Peak memory 215736 kb
Host smart-7acf5c58-5b7a-43c0-959e-30e9676ac72b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862785301 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1862785301
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2675286175
Short name T232
Test name
Test status
Simulation time 333342868 ps
CPU time 1.19 seconds
Started Jun 25 05:49:37 PM PDT 24
Finished Jun 25 05:49:39 PM PDT 24
Peak memory 220012 kb
Host smart-30843f40-2692-4709-b151-6bae7274bd03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675286175 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2675286175
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2971267831
Short name T433
Test name
Test status
Simulation time 24495120 ps
CPU time 1.22 seconds
Started Jun 25 05:49:34 PM PDT 24
Finished Jun 25 05:49:36 PM PDT 24
Peak memory 219112 kb
Host smart-59a0f812-d5a9-4078-9589-0a09f31ee46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971267831 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2971267831
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_intr.3285677012
Short name T259
Test name
Test status
Simulation time 28757550 ps
CPU time 0.93 seconds
Started Jun 25 05:49:28 PM PDT 24
Finished Jun 25 05:49:30 PM PDT 24
Peak memory 215896 kb
Host smart-bf07d4c2-98be-4086-995e-683c11f34cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285677012 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3285677012
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.671980368
Short name T477
Test name
Test status
Simulation time 23199949 ps
CPU time 0.98 seconds
Started Jun 25 05:49:29 PM PDT 24
Finished Jun 25 05:49:31 PM PDT 24
Peak memory 215648 kb
Host smart-216ff76d-62ec-4576-ab87-83aca079556a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671980368 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.671980368
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3616309843
Short name T253
Test name
Test status
Simulation time 168308666 ps
CPU time 3.65 seconds
Started Jun 25 05:49:30 PM PDT 24
Finished Jun 25 05:49:35 PM PDT 24
Peak memory 217536 kb
Host smart-ee6f0663-47c5-410d-9d37-371ed6c7955f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616309843 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3616309843
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.149265348
Short name T47
Test name
Test status
Simulation time 37624681848 ps
CPU time 220.2 seconds
Started Jun 25 05:49:30 PM PDT 24
Finished Jun 25 05:53:11 PM PDT 24
Peak memory 219528 kb
Host smart-3bdc5d7c-c5b3-42e8-bc59-73051cc1f03c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149265348 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.149265348
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3624058047
Short name T720
Test name
Test status
Simulation time 300809315 ps
CPU time 1.42 seconds
Started Jun 25 05:48:15 PM PDT 24
Finished Jun 25 05:48:19 PM PDT 24
Peak memory 219760 kb
Host smart-474442c6-2066-4bdc-9f4b-2b45b8f772d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624058047 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3624058047
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.588718393
Short name T473
Test name
Test status
Simulation time 48038207 ps
CPU time 1.43 seconds
Started Jun 25 05:48:14 PM PDT 24
Finished Jun 25 05:48:17 PM PDT 24
Peak memory 207192 kb
Host smart-156dd2a0-620c-4e0e-a10e-e747c1e64be1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588718393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.588718393
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1560200145
Short name T216
Test name
Test status
Simulation time 12621069 ps
CPU time 0.95 seconds
Started Jun 25 05:48:14 PM PDT 24
Finished Jun 25 05:48:17 PM PDT 24
Peak memory 216760 kb
Host smart-28b75883-b0a1-43e6-9519-670d3b3b4b0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560200145 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1560200145
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.200788143
Short name T213
Test name
Test status
Simulation time 90100075 ps
CPU time 1.21 seconds
Started Jun 25 05:48:15 PM PDT 24
Finished Jun 25 05:48:18 PM PDT 24
Peak memory 217232 kb
Host smart-c429f3c1-963b-48a1-bbb4-18dc130c4ff5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200788143 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.200788143
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.722114527
Short name T558
Test name
Test status
Simulation time 72990326 ps
CPU time 1.1 seconds
Started Jun 25 05:48:15 PM PDT 24
Finished Jun 25 05:48:18 PM PDT 24
Peak memory 219856 kb
Host smart-a3109f0e-93f0-4c2d-a4c2-abf742081bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722114527 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.722114527
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1262547545
Short name T668
Test name
Test status
Simulation time 169705698 ps
CPU time 3.59 seconds
Started Jun 25 05:48:13 PM PDT 24
Finished Jun 25 05:48:18 PM PDT 24
Peak memory 220496 kb
Host smart-a0a69f65-c962-4e6d-bd66-36aedc6b9860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262547545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1262547545
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3800692026
Short name T640
Test name
Test status
Simulation time 52571728 ps
CPU time 0.87 seconds
Started Jun 25 05:48:13 PM PDT 24
Finished Jun 25 05:48:16 PM PDT 24
Peak memory 215692 kb
Host smart-9f7da93e-3654-44d7-8364-1d84546ea5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800692026 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3800692026
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.4196475340
Short name T42
Test name
Test status
Simulation time 18062685 ps
CPU time 1.04 seconds
Started Jun 25 05:48:13 PM PDT 24
Finished Jun 25 05:48:16 PM PDT 24
Peak memory 207432 kb
Host smart-121950b3-bc9a-415b-a16e-62d928959264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196475340 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.4196475340
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2000056810
Short name T65
Test name
Test status
Simulation time 270533791 ps
CPU time 4.98 seconds
Started Jun 25 05:48:14 PM PDT 24
Finished Jun 25 05:48:21 PM PDT 24
Peak memory 237632 kb
Host smart-bb5ce87d-75e7-400c-9511-e77952915512
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000056810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2000056810
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2373167173
Short name T76
Test name
Test status
Simulation time 17228701 ps
CPU time 0.99 seconds
Started Jun 25 05:48:12 PM PDT 24
Finished Jun 25 05:48:14 PM PDT 24
Peak memory 215644 kb
Host smart-f5c12545-1681-4885-8399-da1c1884869c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373167173 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2373167173
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1368056934
Short name T937
Test name
Test status
Simulation time 566143124 ps
CPU time 3.42 seconds
Started Jun 25 05:48:16 PM PDT 24
Finished Jun 25 05:48:22 PM PDT 24
Peak memory 215624 kb
Host smart-db7adf4e-4e76-4d4a-a5b0-0967acfacdbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368056934 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1368056934
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3478068103
Short name T958
Test name
Test status
Simulation time 121261772305 ps
CPU time 1585.63 seconds
Started Jun 25 05:48:13 PM PDT 24
Finished Jun 25 06:14:41 PM PDT 24
Peak memory 227460 kb
Host smart-28332eb3-b183-48ee-b18f-8e571c8b12d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478068103 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3478068103
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1729978170
Short name T439
Test name
Test status
Simulation time 64450803 ps
CPU time 1.11 seconds
Started Jun 25 05:49:37 PM PDT 24
Finished Jun 25 05:49:39 PM PDT 24
Peak memory 221040 kb
Host smart-fa2b31bb-254b-4658-887b-8303ac1d4ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729978170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1729978170
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3997973133
Short name T895
Test name
Test status
Simulation time 30712182 ps
CPU time 0.94 seconds
Started Jun 25 05:49:47 PM PDT 24
Finished Jun 25 05:49:50 PM PDT 24
Peak memory 207176 kb
Host smart-1992794e-d10f-43da-8852-f876d4e435ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997973133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3997973133
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2562365391
Short name T88
Test name
Test status
Simulation time 23183270 ps
CPU time 0.9 seconds
Started Jun 25 05:49:36 PM PDT 24
Finished Jun 25 05:49:37 PM PDT 24
Peak memory 216576 kb
Host smart-3c0d7e30-5e6b-4649-80e4-606b1dd52d0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562365391 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2562365391
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_err.3892853797
Short name T202
Test name
Test status
Simulation time 19433681 ps
CPU time 1.24 seconds
Started Jun 25 05:49:41 PM PDT 24
Finished Jun 25 05:49:43 PM PDT 24
Peak memory 229832 kb
Host smart-7f71d8a7-95f7-4c00-a685-e956a2766dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892853797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3892853797
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_intr.4294956214
Short name T99
Test name
Test status
Simulation time 24788144 ps
CPU time 0.98 seconds
Started Jun 25 05:49:37 PM PDT 24
Finished Jun 25 05:49:39 PM PDT 24
Peak memory 215776 kb
Host smart-2d3b4d2c-1509-44fd-92b4-7d702ffbd25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294956214 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.4294956214
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1086972123
Short name T741
Test name
Test status
Simulation time 65685342 ps
CPU time 0.89 seconds
Started Jun 25 05:49:48 PM PDT 24
Finished Jun 25 05:49:50 PM PDT 24
Peak memory 215652 kb
Host smart-d12e482a-267e-43e6-a423-4a829a46f8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086972123 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1086972123
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.622316468
Short name T417
Test name
Test status
Simulation time 472824226 ps
CPU time 1.56 seconds
Started Jun 25 05:49:37 PM PDT 24
Finished Jun 25 05:49:40 PM PDT 24
Peak memory 215560 kb
Host smart-5c08c70d-1a1a-4d17-a7da-e40ef69736c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622316468 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.622316468
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3223666461
Short name T772
Test name
Test status
Simulation time 124287385854 ps
CPU time 1047.55 seconds
Started Jun 25 05:49:49 PM PDT 24
Finished Jun 25 06:07:18 PM PDT 24
Peak memory 222420 kb
Host smart-f514f5ed-a5a1-4dd5-9a53-b7447f99b8e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223666461 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3223666461
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3989092541
Short name T176
Test name
Test status
Simulation time 78594238 ps
CPU time 1.13 seconds
Started Jun 25 05:49:38 PM PDT 24
Finished Jun 25 05:49:41 PM PDT 24
Peak memory 220088 kb
Host smart-1ced4d91-16bf-4486-b356-5d65becb428b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989092541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3989092541
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1135439305
Short name T463
Test name
Test status
Simulation time 51650289 ps
CPU time 0.91 seconds
Started Jun 25 05:49:37 PM PDT 24
Finished Jun 25 05:49:39 PM PDT 24
Peak memory 207028 kb
Host smart-e797c1ef-d336-4336-b56c-fd9ca27782dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135439305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1135439305
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3432003743
Short name T582
Test name
Test status
Simulation time 9976604 ps
CPU time 0.86 seconds
Started Jun 25 05:49:37 PM PDT 24
Finished Jun 25 05:49:39 PM PDT 24
Peak memory 216680 kb
Host smart-ed616266-4244-4865-8c8a-532b6be77b7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432003743 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3432003743
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_err.857063078
Short name T200
Test name
Test status
Simulation time 19059012 ps
CPU time 1.15 seconds
Started Jun 25 05:49:37 PM PDT 24
Finished Jun 25 05:49:38 PM PDT 24
Peak memory 224300 kb
Host smart-7793dc0d-1159-4aa5-9929-596a5bf44815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857063078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.857063078
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.570190215
Short name T715
Test name
Test status
Simulation time 76545424 ps
CPU time 1.31 seconds
Started Jun 25 05:49:38 PM PDT 24
Finished Jun 25 05:49:40 PM PDT 24
Peak memory 220256 kb
Host smart-541a79c3-1513-4e19-a72a-d4c8252153b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570190215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.570190215
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2381408271
Short name T124
Test name
Test status
Simulation time 23105195 ps
CPU time 0.94 seconds
Started Jun 25 05:49:36 PM PDT 24
Finished Jun 25 05:49:38 PM PDT 24
Peak memory 216196 kb
Host smart-e157bbab-5532-40b2-8d3e-770ac6e553fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381408271 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2381408271
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.488191133
Short name T751
Test name
Test status
Simulation time 51930691 ps
CPU time 0.91 seconds
Started Jun 25 05:49:39 PM PDT 24
Finished Jun 25 05:49:41 PM PDT 24
Peak memory 215644 kb
Host smart-bd4fd433-5ba8-45f2-9968-28f971e917bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488191133 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.488191133
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2652658545
Short name T931
Test name
Test status
Simulation time 426299490 ps
CPU time 4.85 seconds
Started Jun 25 05:49:49 PM PDT 24
Finished Jun 25 05:49:55 PM PDT 24
Peak memory 215592 kb
Host smart-3d91498b-62df-4ae0-8f34-61928ea3dd7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652658545 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2652658545
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2538575358
Short name T68
Test name
Test status
Simulation time 24087312029 ps
CPU time 557.09 seconds
Started Jun 25 05:49:38 PM PDT 24
Finished Jun 25 05:58:56 PM PDT 24
Peak memory 223896 kb
Host smart-d2df4c61-b8ce-451d-b83c-fdcec8c6734d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538575358 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2538575358
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3459060904
Short name T293
Test name
Test status
Simulation time 213715846 ps
CPU time 1.38 seconds
Started Jun 25 05:49:40 PM PDT 24
Finished Jun 25 05:49:42 PM PDT 24
Peak memory 216016 kb
Host smart-b3d6d373-adc8-49d3-b218-47f290cab147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459060904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3459060904
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3223323388
Short name T983
Test name
Test status
Simulation time 61564919 ps
CPU time 0.83 seconds
Started Jun 25 05:49:36 PM PDT 24
Finished Jun 25 05:49:38 PM PDT 24
Peak memory 206904 kb
Host smart-5d89ac65-3244-411f-8033-ca7b325a1bf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223323388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3223323388
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.162478600
Short name T452
Test name
Test status
Simulation time 26797434 ps
CPU time 0.84 seconds
Started Jun 25 05:49:48 PM PDT 24
Finished Jun 25 05:49:51 PM PDT 24
Peak memory 215768 kb
Host smart-20556cd4-197e-4698-9af6-c43cdb90546e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162478600 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.162478600
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3136698161
Short name T133
Test name
Test status
Simulation time 71978598 ps
CPU time 1.09 seconds
Started Jun 25 05:49:39 PM PDT 24
Finished Jun 25 05:49:41 PM PDT 24
Peak memory 217252 kb
Host smart-e1dff128-0f48-4028-baf7-b35f3bf1afe2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136698161 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3136698161
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1365342768
Short name T786
Test name
Test status
Simulation time 19212890 ps
CPU time 0.97 seconds
Started Jun 25 05:49:38 PM PDT 24
Finished Jun 25 05:49:40 PM PDT 24
Peak memory 218760 kb
Host smart-b9abdeda-d2f4-450a-9ac6-98f6daf20728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365342768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1365342768
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_intr.3500403396
Short name T438
Test name
Test status
Simulation time 26152620 ps
CPU time 0.98 seconds
Started Jun 25 05:49:40 PM PDT 24
Finished Jun 25 05:49:42 PM PDT 24
Peak memory 215860 kb
Host smart-4cfd765c-4094-41b3-b509-925b7fcc7881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500403396 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3500403396
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.1681163591
Short name T462
Test name
Test status
Simulation time 16306701 ps
CPU time 1 seconds
Started Jun 25 05:49:37 PM PDT 24
Finished Jun 25 05:49:40 PM PDT 24
Peak memory 215644 kb
Host smart-972a8035-2333-4d4b-9df9-8601e3666e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681163591 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1681163591
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.495953336
Short name T298
Test name
Test status
Simulation time 455903527 ps
CPU time 4.64 seconds
Started Jun 25 05:49:37 PM PDT 24
Finished Jun 25 05:49:43 PM PDT 24
Peak memory 218828 kb
Host smart-3c6f0be1-8a23-433c-a177-693bc409f784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495953336 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.495953336
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3777783788
Short name T879
Test name
Test status
Simulation time 132267020208 ps
CPU time 2049.7 seconds
Started Jun 25 05:49:38 PM PDT 24
Finished Jun 25 06:23:49 PM PDT 24
Peak memory 230340 kb
Host smart-e932002d-aac5-4f06-b7fa-eb6aede50d73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777783788 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3777783788
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.3068466021
Short name T589
Test name
Test status
Simulation time 32839660 ps
CPU time 1.38 seconds
Started Jun 25 05:49:37 PM PDT 24
Finished Jun 25 05:49:39 PM PDT 24
Peak memory 216024 kb
Host smart-83d0251c-0a3c-42bf-87ef-6644e6c28b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068466021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3068466021
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1563894269
Short name T738
Test name
Test status
Simulation time 22840694 ps
CPU time 0.84 seconds
Started Jun 25 05:49:43 PM PDT 24
Finished Jun 25 05:49:44 PM PDT 24
Peak memory 215048 kb
Host smart-220315a7-68cb-4e7b-b1ae-8de49fa55684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563894269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1563894269
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2978893364
Short name T847
Test name
Test status
Simulation time 14270909 ps
CPU time 1 seconds
Started Jun 25 05:49:46 PM PDT 24
Finished Jun 25 05:49:48 PM PDT 24
Peak memory 216700 kb
Host smart-f50586ce-46ae-4276-abae-98eb1bc29355
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978893364 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2978893364
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2142715390
Short name T962
Test name
Test status
Simulation time 27677370 ps
CPU time 1.16 seconds
Started Jun 25 05:49:46 PM PDT 24
Finished Jun 25 05:49:48 PM PDT 24
Peak memory 218704 kb
Host smart-380ef5be-4a74-491e-8b44-f3fa8772e6d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142715390 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2142715390
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.493807674
Short name T505
Test name
Test status
Simulation time 21541493 ps
CPU time 0.92 seconds
Started Jun 25 05:49:38 PM PDT 24
Finished Jun 25 05:49:40 PM PDT 24
Peak memory 218804 kb
Host smart-9f9d2cdc-6242-4bdc-9f55-732df50bb4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493807674 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.493807674
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2808599375
Short name T511
Test name
Test status
Simulation time 112610971 ps
CPU time 1.21 seconds
Started Jun 25 05:49:36 PM PDT 24
Finished Jun 25 05:49:38 PM PDT 24
Peak memory 217692 kb
Host smart-e2fa93dd-82ad-439a-8570-a71b1ab33ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808599375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2808599375
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2274501005
Short name T933
Test name
Test status
Simulation time 30028927 ps
CPU time 1 seconds
Started Jun 25 05:49:37 PM PDT 24
Finished Jun 25 05:49:40 PM PDT 24
Peak memory 215768 kb
Host smart-90a58add-8018-42c4-9b30-df80f8bccbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274501005 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2274501005
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2222555408
Short name T693
Test name
Test status
Simulation time 39032999 ps
CPU time 0.92 seconds
Started Jun 25 05:49:37 PM PDT 24
Finished Jun 25 05:49:40 PM PDT 24
Peak memory 215564 kb
Host smart-39211c5c-9668-434b-921e-f4e7b394a17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222555408 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2222555408
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2514926355
Short name T90
Test name
Test status
Simulation time 43152534 ps
CPU time 1.3 seconds
Started Jun 25 05:49:48 PM PDT 24
Finished Jun 25 05:49:51 PM PDT 24
Peak memory 219000 kb
Host smart-e4ee75af-2dc1-4589-bc28-f25e81d4d05f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514926355 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2514926355
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2797669125
Short name T676
Test name
Test status
Simulation time 53089677204 ps
CPU time 1359.1 seconds
Started Jun 25 05:49:49 PM PDT 24
Finished Jun 25 06:12:29 PM PDT 24
Peak memory 224248 kb
Host smart-498d1178-a5ca-41ab-b5b9-ccfde3ce18a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797669125 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2797669125
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2588987457
Short name T912
Test name
Test status
Simulation time 22872512 ps
CPU time 1.19 seconds
Started Jun 25 05:49:44 PM PDT 24
Finished Jun 25 05:49:47 PM PDT 24
Peak memory 219092 kb
Host smart-f0e892cf-a24e-4fc1-b9c9-243e77fb7df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588987457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2588987457
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1668639600
Short name T949
Test name
Test status
Simulation time 23986145 ps
CPU time 0.95 seconds
Started Jun 25 05:49:45 PM PDT 24
Finished Jun 25 05:49:48 PM PDT 24
Peak memory 206984 kb
Host smart-94bce959-d619-49be-98f4-9961dcb4b63a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668639600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1668639600
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1766980465
Short name T918
Test name
Test status
Simulation time 44965553 ps
CPU time 1.09 seconds
Started Jun 25 05:49:43 PM PDT 24
Finished Jun 25 05:49:45 PM PDT 24
Peak memory 218756 kb
Host smart-ddcbab76-b394-4852-9763-c516783074ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766980465 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1766980465
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3157872012
Short name T71
Test name
Test status
Simulation time 74317978 ps
CPU time 1.05 seconds
Started Jun 25 05:49:43 PM PDT 24
Finished Jun 25 05:49:46 PM PDT 24
Peak memory 219976 kb
Host smart-18f23b31-5769-418c-aa5b-e99c0c8c954e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157872012 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3157872012
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1240658320
Short name T964
Test name
Test status
Simulation time 92228657 ps
CPU time 1.29 seconds
Started Jun 25 05:49:46 PM PDT 24
Finished Jun 25 05:49:49 PM PDT 24
Peak memory 217552 kb
Host smart-0d777e47-1d11-42a1-9e50-fa7d24272300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240658320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1240658320
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2717822714
Short name T843
Test name
Test status
Simulation time 28732154 ps
CPU time 1.01 seconds
Started Jun 25 05:49:44 PM PDT 24
Finished Jun 25 05:49:47 PM PDT 24
Peak memory 215888 kb
Host smart-e84ec1d0-b47d-441f-8450-b3fc5cba9fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717822714 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2717822714
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2357097015
Short name T649
Test name
Test status
Simulation time 27548269 ps
CPU time 0.95 seconds
Started Jun 25 05:49:47 PM PDT 24
Finished Jun 25 05:49:49 PM PDT 24
Peak memory 215656 kb
Host smart-34002ae5-ed23-43ee-a2ce-fca7704d4cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357097015 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2357097015
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2312059449
Short name T325
Test name
Test status
Simulation time 77902837 ps
CPU time 2.03 seconds
Started Jun 25 05:49:45 PM PDT 24
Finished Jun 25 05:49:49 PM PDT 24
Peak memory 217664 kb
Host smart-2185acb0-4467-4c3d-ac2a-82639ac4c4e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312059449 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2312059449
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2291376748
Short name T512
Test name
Test status
Simulation time 20804503303 ps
CPU time 519.89 seconds
Started Jun 25 05:49:48 PM PDT 24
Finished Jun 25 05:58:30 PM PDT 24
Peak memory 218824 kb
Host smart-c148f312-0e4c-40ab-8a49-88e6220bc19c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291376748 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2291376748
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1381165429
Short name T934
Test name
Test status
Simulation time 474611817 ps
CPU time 1.73 seconds
Started Jun 25 05:49:46 PM PDT 24
Finished Jun 25 05:49:49 PM PDT 24
Peak memory 216004 kb
Host smart-4e6f43c9-849b-42a3-8e72-5b486d80bac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381165429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1381165429
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1457929924
Short name T509
Test name
Test status
Simulation time 55214504 ps
CPU time 1.01 seconds
Started Jun 25 05:49:48 PM PDT 24
Finished Jun 25 05:49:50 PM PDT 24
Peak memory 215256 kb
Host smart-d87714d8-ae74-4fd3-9a5f-fbffba3c510e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457929924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1457929924
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3834907401
Short name T233
Test name
Test status
Simulation time 27850367 ps
CPU time 0.81 seconds
Started Jun 25 05:49:47 PM PDT 24
Finished Jun 25 05:49:49 PM PDT 24
Peak memory 215736 kb
Host smart-95ec331d-2798-4cdd-9eef-a4a7711171a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834907401 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3834907401
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2803964089
Short name T968
Test name
Test status
Simulation time 36649309 ps
CPU time 1.36 seconds
Started Jun 25 05:49:43 PM PDT 24
Finished Jun 25 05:49:46 PM PDT 24
Peak memory 217428 kb
Host smart-7d368426-9ed7-43dc-8c56-f83566ad621c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803964089 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2803964089
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1349942626
Short name T201
Test name
Test status
Simulation time 22680869 ps
CPU time 0.92 seconds
Started Jun 25 05:49:45 PM PDT 24
Finished Jun 25 05:49:47 PM PDT 24
Peak memory 218480 kb
Host smart-0aacb3d8-5e8f-409c-9cb4-230868971331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349942626 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1349942626
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2497205275
Short name T460
Test name
Test status
Simulation time 58659288 ps
CPU time 1.32 seconds
Started Jun 25 05:49:47 PM PDT 24
Finished Jun 25 05:49:50 PM PDT 24
Peak memory 218836 kb
Host smart-d58e2b86-8f87-474c-b04b-f2a4efe98314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497205275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2497205275
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.859456317
Short name T491
Test name
Test status
Simulation time 27829031 ps
CPU time 0.97 seconds
Started Jun 25 05:49:44 PM PDT 24
Finished Jun 25 05:49:46 PM PDT 24
Peak memory 215876 kb
Host smart-2fd8e5cf-84be-4d3e-a2ca-e6971f62d06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859456317 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.859456317
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.428460053
Short name T611
Test name
Test status
Simulation time 55557520 ps
CPU time 1.01 seconds
Started Jun 25 05:49:45 PM PDT 24
Finished Jun 25 05:49:47 PM PDT 24
Peak memory 215632 kb
Host smart-697493dc-3a8d-4a22-959f-72265e6c00ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428460053 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.428460053
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3830430389
Short name T443
Test name
Test status
Simulation time 41557978 ps
CPU time 1.48 seconds
Started Jun 25 05:49:49 PM PDT 24
Finished Jun 25 05:49:53 PM PDT 24
Peak memory 215656 kb
Host smart-caff4f6d-fa1f-4c95-a13d-7c92111d5639
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830430389 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3830430389
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2680109758
Short name T245
Test name
Test status
Simulation time 58727948760 ps
CPU time 337.67 seconds
Started Jun 25 05:49:48 PM PDT 24
Finished Jun 25 05:55:27 PM PDT 24
Peak memory 224056 kb
Host smart-f6e6def3-384c-4a10-906d-418320e1607c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680109758 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2680109758
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3838187535
Short name T635
Test name
Test status
Simulation time 24946625 ps
CPU time 1.21 seconds
Started Jun 25 05:49:46 PM PDT 24
Finished Jun 25 05:49:48 PM PDT 24
Peak memory 216068 kb
Host smart-5ce6982f-640d-4d6a-9898-3b99d49b9219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838187535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3838187535
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2198313310
Short name T24
Test name
Test status
Simulation time 19397787 ps
CPU time 1 seconds
Started Jun 25 05:49:44 PM PDT 24
Finished Jun 25 05:49:47 PM PDT 24
Peak memory 215492 kb
Host smart-61b6870e-f641-4fcc-a059-a89d4982b32f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198313310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2198313310
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3433375894
Short name T167
Test name
Test status
Simulation time 28277406 ps
CPU time 0.83 seconds
Started Jun 25 05:49:48 PM PDT 24
Finished Jun 25 05:49:50 PM PDT 24
Peak memory 215752 kb
Host smart-dfcd0343-d8e5-451d-ad87-660ffb22f187
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433375894 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3433375894
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1553070695
Short name T797
Test name
Test status
Simulation time 64233081 ps
CPU time 1.11 seconds
Started Jun 25 05:49:44 PM PDT 24
Finished Jun 25 05:49:47 PM PDT 24
Peak memory 217336 kb
Host smart-16184bc0-4256-466a-9691-7b6552519d26
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553070695 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1553070695
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1077445690
Short name T129
Test name
Test status
Simulation time 50856354 ps
CPU time 0.94 seconds
Started Jun 25 05:49:48 PM PDT 24
Finished Jun 25 05:49:51 PM PDT 24
Peak memory 220720 kb
Host smart-8061cb06-9bf5-4e23-9eef-d8ff479d2f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077445690 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1077445690
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1789049434
Short name T884
Test name
Test status
Simulation time 69100628 ps
CPU time 1.09 seconds
Started Jun 25 05:49:49 PM PDT 24
Finished Jun 25 05:49:52 PM PDT 24
Peak memory 217692 kb
Host smart-1e7fb30f-4f18-4326-9fe6-14a58d72c30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789049434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1789049434
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3080973628
Short name T123
Test name
Test status
Simulation time 27400775 ps
CPU time 1.01 seconds
Started Jun 25 05:49:44 PM PDT 24
Finished Jun 25 05:49:47 PM PDT 24
Peak memory 216276 kb
Host smart-629bffa6-c2f1-439b-b14d-712dc28c6981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080973628 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3080973628
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.158183996
Short name T64
Test name
Test status
Simulation time 51126309 ps
CPU time 0.92 seconds
Started Jun 25 05:49:44 PM PDT 24
Finished Jun 25 05:49:46 PM PDT 24
Peak memory 215608 kb
Host smart-49c83a72-20eb-4bea-bcec-de08af130bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158183996 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.158183996
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1809652497
Short name T250
Test name
Test status
Simulation time 324839401 ps
CPU time 4.97 seconds
Started Jun 25 05:49:46 PM PDT 24
Finished Jun 25 05:49:52 PM PDT 24
Peak memory 217736 kb
Host smart-1da9a3ff-febc-4f75-8951-a114658e3737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809652497 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1809652497
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.4061048384
Short name T711
Test name
Test status
Simulation time 64803995852 ps
CPU time 1592.67 seconds
Started Jun 25 05:49:43 PM PDT 24
Finished Jun 25 06:16:17 PM PDT 24
Peak memory 226308 kb
Host smart-31cc0fe3-5f77-48c0-9612-ba9841a6002f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061048384 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.4061048384
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3599951314
Short name T74
Test name
Test status
Simulation time 43928041 ps
CPU time 1.15 seconds
Started Jun 25 05:49:46 PM PDT 24
Finished Jun 25 05:49:49 PM PDT 24
Peak memory 221104 kb
Host smart-6e26dda3-61d4-447a-a510-15e4c18eebad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599951314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3599951314
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1529855119
Short name T495
Test name
Test status
Simulation time 41884223 ps
CPU time 0.99 seconds
Started Jun 25 05:49:53 PM PDT 24
Finished Jun 25 05:49:54 PM PDT 24
Peak memory 215336 kb
Host smart-d71e8e9c-6b25-40cc-a13b-e9f468e4d2e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529855119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1529855119
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3938262334
Short name T181
Test name
Test status
Simulation time 14444840 ps
CPU time 0.96 seconds
Started Jun 25 05:49:43 PM PDT 24
Finished Jun 25 05:49:45 PM PDT 24
Peak memory 216776 kb
Host smart-8f749948-236f-4a01-a110-8a131105277e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938262334 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3938262334
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2948514387
Short name T814
Test name
Test status
Simulation time 210249150 ps
CPU time 1.06 seconds
Started Jun 25 05:49:47 PM PDT 24
Finished Jun 25 05:49:49 PM PDT 24
Peak memory 217320 kb
Host smart-3cf4034a-7013-4a1e-904f-3c00f409303d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948514387 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2948514387
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2971495322
Short name T553
Test name
Test status
Simulation time 72394906 ps
CPU time 1.19 seconds
Started Jun 25 05:49:44 PM PDT 24
Finished Jun 25 05:49:47 PM PDT 24
Peak memory 220072 kb
Host smart-3e62e5ed-4137-4039-850e-41fa29a5d46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971495322 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2971495322
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3963569696
Short name T26
Test name
Test status
Simulation time 81740875 ps
CPU time 1.34 seconds
Started Jun 25 05:49:44 PM PDT 24
Finished Jun 25 05:49:47 PM PDT 24
Peak memory 217576 kb
Host smart-65d0649c-415a-4ccd-92da-d0b09ad4890f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963569696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3963569696
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_smoke.1385866290
Short name T746
Test name
Test status
Simulation time 16073900 ps
CPU time 1.05 seconds
Started Jun 25 05:49:45 PM PDT 24
Finished Jun 25 05:49:47 PM PDT 24
Peak memory 215676 kb
Host smart-347cce23-e30d-4e85-b4fa-062cd86d78d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385866290 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1385866290
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2209025175
Short name T206
Test name
Test status
Simulation time 73523301 ps
CPU time 1.03 seconds
Started Jun 25 05:49:44 PM PDT 24
Finished Jun 25 05:49:46 PM PDT 24
Peak memory 215668 kb
Host smart-08c47dc6-bc92-4b13-99ce-53f632af0f9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209025175 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2209025175
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1780266864
Short name T898
Test name
Test status
Simulation time 86487334074 ps
CPU time 1026.07 seconds
Started Jun 25 05:49:45 PM PDT 24
Finished Jun 25 06:06:52 PM PDT 24
Peak memory 223080 kb
Host smart-7a2b02ec-499a-45ee-bc0b-43e9725b61dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780266864 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1780266864
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3052056514
Short name T381
Test name
Test status
Simulation time 122411560 ps
CPU time 1.13 seconds
Started Jun 25 05:49:55 PM PDT 24
Finished Jun 25 05:49:57 PM PDT 24
Peak memory 220708 kb
Host smart-a67f727d-ccfd-483a-8f90-68dee6e6fb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052056514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3052056514
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2610165650
Short name T600
Test name
Test status
Simulation time 14542336 ps
CPU time 0.91 seconds
Started Jun 25 05:49:56 PM PDT 24
Finished Jun 25 05:49:59 PM PDT 24
Peak memory 207268 kb
Host smart-cc8d52c3-e745-4361-8020-ccefda53b8d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610165650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2610165650
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3806284597
Short name T210
Test name
Test status
Simulation time 38540517 ps
CPU time 0.86 seconds
Started Jun 25 05:49:52 PM PDT 24
Finished Jun 25 05:49:54 PM PDT 24
Peak memory 216624 kb
Host smart-13d5ec72-a000-4767-aac7-198779a57c2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806284597 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3806284597
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1552794349
Short name T207
Test name
Test status
Simulation time 43300684 ps
CPU time 1.18 seconds
Started Jun 25 05:49:54 PM PDT 24
Finished Jun 25 05:49:56 PM PDT 24
Peak memory 218692 kb
Host smart-24f2623d-be86-48cd-b674-ac3aa80bb447
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552794349 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1552794349
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.541805483
Short name T485
Test name
Test status
Simulation time 21621752 ps
CPU time 0.99 seconds
Started Jun 25 05:49:56 PM PDT 24
Finished Jun 25 05:49:58 PM PDT 24
Peak memory 218972 kb
Host smart-66cb9609-f047-442d-957c-15cb4cf4b800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541805483 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.541805483
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2814312219
Short name T421
Test name
Test status
Simulation time 61496525 ps
CPU time 1.22 seconds
Started Jun 25 05:49:54 PM PDT 24
Finished Jun 25 05:49:56 PM PDT 24
Peak memory 218708 kb
Host smart-3f168a88-78b0-411a-a863-0a50ec3c1f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814312219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2814312219
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2858373290
Short name T607
Test name
Test status
Simulation time 36788363 ps
CPU time 0.91 seconds
Started Jun 25 05:49:55 PM PDT 24
Finished Jun 25 05:49:57 PM PDT 24
Peak memory 215576 kb
Host smart-0ddcd5d7-1844-4dfb-9d47-1b9e57428306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858373290 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2858373290
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.315445887
Short name T507
Test name
Test status
Simulation time 15363876 ps
CPU time 1.04 seconds
Started Jun 25 05:49:57 PM PDT 24
Finished Jun 25 05:49:59 PM PDT 24
Peak memory 215644 kb
Host smart-e23a8be8-87f1-496a-ad38-240b6021d15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315445887 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.315445887
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1885737735
Short name T975
Test name
Test status
Simulation time 58222166 ps
CPU time 1.17 seconds
Started Jun 25 05:49:56 PM PDT 24
Finished Jun 25 05:49:58 PM PDT 24
Peak memory 215644 kb
Host smart-960418fd-bc54-4e45-86d1-7abb45254bc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885737735 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1885737735
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3209375405
Short name T981
Test name
Test status
Simulation time 144279509121 ps
CPU time 1684.15 seconds
Started Jun 25 05:49:55 PM PDT 24
Finished Jun 25 06:18:01 PM PDT 24
Peak memory 225552 kb
Host smart-70869f80-2ad2-4e9a-8646-8ce1b22a0b3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209375405 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3209375405
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2743545364
Short name T406
Test name
Test status
Simulation time 26053201 ps
CPU time 1.26 seconds
Started Jun 25 05:49:57 PM PDT 24
Finished Jun 25 05:50:00 PM PDT 24
Peak memory 220124 kb
Host smart-c5e3ed96-765a-455d-9ee8-d122d7699356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743545364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2743545364
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.4243430876
Short name T465
Test name
Test status
Simulation time 54158468 ps
CPU time 0.98 seconds
Started Jun 25 05:49:54 PM PDT 24
Finished Jun 25 05:49:56 PM PDT 24
Peak memory 207048 kb
Host smart-9ec8b412-48d9-4b49-bb8d-a023dcaf1554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243430876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.4243430876
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1416710961
Short name T87
Test name
Test status
Simulation time 34763872 ps
CPU time 0.91 seconds
Started Jun 25 05:49:53 PM PDT 24
Finished Jun 25 05:49:55 PM PDT 24
Peak memory 216680 kb
Host smart-c516aafb-d53a-418c-b8bd-a6eb7e027c87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416710961 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1416710961
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1986211310
Short name T815
Test name
Test status
Simulation time 31884229 ps
CPU time 1.07 seconds
Started Jun 25 05:49:53 PM PDT 24
Finished Jun 25 05:49:54 PM PDT 24
Peak memory 218704 kb
Host smart-d0cfe233-2194-4634-866f-b2ba94d18a95
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986211310 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1986211310
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.856232267
Short name T142
Test name
Test status
Simulation time 67442303 ps
CPU time 1.01 seconds
Started Jun 25 05:49:57 PM PDT 24
Finished Jun 25 05:49:59 PM PDT 24
Peak memory 229736 kb
Host smart-cf14d2d9-c125-4d65-943a-7331482c180f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856232267 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.856232267
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3024156326
Short name T956
Test name
Test status
Simulation time 36350066 ps
CPU time 1.53 seconds
Started Jun 25 05:49:56 PM PDT 24
Finished Jun 25 05:49:58 PM PDT 24
Peak memory 218920 kb
Host smart-759fec3c-d159-4ac6-86e4-5de71890350e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024156326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3024156326
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.406766199
Short name T449
Test name
Test status
Simulation time 20545125 ps
CPU time 1.16 seconds
Started Jun 25 05:49:57 PM PDT 24
Finished Jun 25 05:49:59 PM PDT 24
Peak memory 215756 kb
Host smart-e1ca4235-7eef-4c33-8209-9b0301a0abad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406766199 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.406766199
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2361148728
Short name T798
Test name
Test status
Simulation time 32518526 ps
CPU time 0.94 seconds
Started Jun 25 05:49:54 PM PDT 24
Finished Jun 25 05:49:56 PM PDT 24
Peak memory 215644 kb
Host smart-4bf2075c-a038-4505-b184-27f29787db28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361148728 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2361148728
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1413279708
Short name T839
Test name
Test status
Simulation time 941905844 ps
CPU time 4.99 seconds
Started Jun 25 05:49:55 PM PDT 24
Finished Jun 25 05:50:02 PM PDT 24
Peak memory 215064 kb
Host smart-74064b89-86a0-45fc-9af1-6713e3035c3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413279708 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1413279708
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1158983811
Short name T238
Test name
Test status
Simulation time 99516709874 ps
CPU time 439.28 seconds
Started Jun 25 05:49:54 PM PDT 24
Finished Jun 25 05:57:14 PM PDT 24
Peak memory 219796 kb
Host smart-946c734d-265a-4ed0-a5f4-a20a10622a1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158983811 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1158983811
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1991924380
Short name T319
Test name
Test status
Simulation time 25781535 ps
CPU time 1.22 seconds
Started Jun 25 05:48:16 PM PDT 24
Finished Jun 25 05:48:19 PM PDT 24
Peak memory 220160 kb
Host smart-35f715e2-4b21-480a-8787-e46ecd83f707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991924380 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1991924380
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3625635952
Short name T615
Test name
Test status
Simulation time 63384170 ps
CPU time 0.84 seconds
Started Jun 25 05:48:21 PM PDT 24
Finished Jun 25 05:48:23 PM PDT 24
Peak memory 206632 kb
Host smart-80aa05a5-71ea-422b-ad83-39fe25b54623
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625635952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3625635952
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3534211702
Short name T641
Test name
Test status
Simulation time 20922839 ps
CPU time 0.87 seconds
Started Jun 25 05:48:20 PM PDT 24
Finished Jun 25 05:48:21 PM PDT 24
Peak memory 216596 kb
Host smart-f12e866f-6098-456d-a503-091b388a7323
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534211702 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3534211702
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_err.4275459202
Short name T809
Test name
Test status
Simulation time 45214613 ps
CPU time 1.14 seconds
Started Jun 25 05:48:16 PM PDT 24
Finished Jun 25 05:48:19 PM PDT 24
Peak memory 229504 kb
Host smart-09a1acd8-2a01-4624-8790-0be42e438cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275459202 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.4275459202
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.4152267739
Short name T329
Test name
Test status
Simulation time 72610289 ps
CPU time 1.4 seconds
Started Jun 25 05:48:16 PM PDT 24
Finished Jun 25 05:48:20 PM PDT 24
Peak memory 219228 kb
Host smart-90e7679b-da8b-4d7e-b0f4-9ffb975b17b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152267739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.4152267739
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.865060262
Short name T554
Test name
Test status
Simulation time 32100587 ps
CPU time 0.93 seconds
Started Jun 25 05:48:15 PM PDT 24
Finished Jun 25 05:48:18 PM PDT 24
Peak memory 215860 kb
Host smart-7009da0f-0306-42e3-8f2a-753b9a55a412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865060262 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.865060262
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1935337714
Short name T1
Test name
Test status
Simulation time 53488156 ps
CPU time 0.91 seconds
Started Jun 25 05:48:17 PM PDT 24
Finished Jun 25 05:48:19 PM PDT 24
Peak memory 207444 kb
Host smart-fd486209-fd79-4cd4-900b-4bcce2b2d9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935337714 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1935337714
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3295192315
Short name T375
Test name
Test status
Simulation time 88348456 ps
CPU time 0.95 seconds
Started Jun 25 05:48:16 PM PDT 24
Finished Jun 25 05:48:19 PM PDT 24
Peak memory 215632 kb
Host smart-77869fac-ff43-4d35-98f7-8e8901cd80d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295192315 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3295192315
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.692559281
Short name T627
Test name
Test status
Simulation time 279588673 ps
CPU time 5.41 seconds
Started Jun 25 05:48:15 PM PDT 24
Finished Jun 25 05:48:22 PM PDT 24
Peak memory 215976 kb
Host smart-60e1f842-a0ca-4092-ae77-be219337b85d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692559281 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.692559281
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2271797613
Short name T236
Test name
Test status
Simulation time 137081011561 ps
CPU time 588.7 seconds
Started Jun 25 05:48:14 PM PDT 24
Finished Jun 25 05:58:05 PM PDT 24
Peak memory 220332 kb
Host smart-20c5a17b-2eaf-4c0b-8398-d58bebc33a12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271797613 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2271797613
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.1173178110
Short name T489
Test name
Test status
Simulation time 27771073 ps
CPU time 1.31 seconds
Started Jun 25 05:49:55 PM PDT 24
Finished Jun 25 05:49:58 PM PDT 24
Peak memory 221080 kb
Host smart-5ac9ca9b-fae4-4828-926f-a2802159d761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173178110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.1173178110
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.1641058888
Short name T150
Test name
Test status
Simulation time 32441854 ps
CPU time 1.07 seconds
Started Jun 25 05:49:53 PM PDT 24
Finished Jun 25 05:49:55 PM PDT 24
Peak memory 224252 kb
Host smart-4cf5d0f5-f0ec-401b-9cda-81fdba56411f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641058888 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1641058888
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1121998671
Short name T842
Test name
Test status
Simulation time 36929665 ps
CPU time 1.66 seconds
Started Jun 25 05:49:53 PM PDT 24
Finished Jun 25 05:49:56 PM PDT 24
Peak memory 217788 kb
Host smart-c8d16ada-2829-4748-a1fb-ecc82341c895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121998671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1121998671
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.1013738504
Short name T266
Test name
Test status
Simulation time 57697911 ps
CPU time 1.26 seconds
Started Jun 25 05:49:56 PM PDT 24
Finished Jun 25 05:49:58 PM PDT 24
Peak memory 219532 kb
Host smart-c2a8857b-1116-4b53-bc63-75a1e0a6cc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013738504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.1013738504
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.2424408965
Short name T789
Test name
Test status
Simulation time 51946824 ps
CPU time 1.08 seconds
Started Jun 25 05:49:56 PM PDT 24
Finished Jun 25 05:49:58 PM PDT 24
Peak memory 220076 kb
Host smart-97db8cbc-73bd-4409-8161-fe8f85f08ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424408965 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2424408965
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3571591474
Short name T474
Test name
Test status
Simulation time 81825432 ps
CPU time 1.06 seconds
Started Jun 25 05:49:56 PM PDT 24
Finished Jun 25 05:49:58 PM PDT 24
Peak memory 217652 kb
Host smart-12d444f1-9a12-44f9-8d8f-2f9514d24fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571591474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3571591474
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.1669283556
Short name T733
Test name
Test status
Simulation time 23680294 ps
CPU time 1.22 seconds
Started Jun 25 05:49:56 PM PDT 24
Finished Jun 25 05:49:58 PM PDT 24
Peak memory 218864 kb
Host smart-0aae7001-8982-4319-9e1d-fbf74512b037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669283556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.1669283556
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_genbits.974745093
Short name T472
Test name
Test status
Simulation time 38597576 ps
CPU time 1.42 seconds
Started Jun 25 05:49:55 PM PDT 24
Finished Jun 25 05:49:58 PM PDT 24
Peak memory 218976 kb
Host smart-a51cde19-5c8f-446e-9c66-5a0d7414aba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974745093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.974745093
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.3520520001
Short name T182
Test name
Test status
Simulation time 186312983 ps
CPU time 1.28 seconds
Started Jun 25 05:50:05 PM PDT 24
Finished Jun 25 05:50:08 PM PDT 24
Peak memory 219856 kb
Host smart-aada13b8-9e18-4098-9b3d-2582a7370a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520520001 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.3520520001
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.2290400740
Short name T118
Test name
Test status
Simulation time 34147661 ps
CPU time 1.06 seconds
Started Jun 25 05:50:01 PM PDT 24
Finished Jun 25 05:50:04 PM PDT 24
Peak memory 229996 kb
Host smart-c1fec6fc-a711-4ddb-8172-eba5f10fc797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290400740 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2290400740
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1301990658
Short name T887
Test name
Test status
Simulation time 62137220 ps
CPU time 0.92 seconds
Started Jun 25 05:50:00 PM PDT 24
Finished Jun 25 05:50:03 PM PDT 24
Peak memory 217892 kb
Host smart-c897fd16-04fd-4285-884c-83b79b09af3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301990658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1301990658
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.3286095421
Short name T760
Test name
Test status
Simulation time 25743689 ps
CPU time 1.27 seconds
Started Jun 25 05:50:01 PM PDT 24
Finished Jun 25 05:50:04 PM PDT 24
Peak memory 218840 kb
Host smart-e6fbcc26-e6f8-4c06-8c1f-26b7f4df51ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286095421 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3286095421
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2405721097
Short name T991
Test name
Test status
Simulation time 21902412 ps
CPU time 1.1 seconds
Started Jun 25 05:50:01 PM PDT 24
Finished Jun 25 05:50:04 PM PDT 24
Peak memory 224316 kb
Host smart-b24115e6-3b91-48c3-830a-3a9bfbb1e4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405721097 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2405721097
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.626763464
Short name T351
Test name
Test status
Simulation time 67959013 ps
CPU time 1.49 seconds
Started Jun 25 05:50:02 PM PDT 24
Finished Jun 25 05:50:05 PM PDT 24
Peak memory 220288 kb
Host smart-fd521d36-b9bb-487b-aeeb-b73922b0c652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626763464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.626763464
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.734887137
Short name T638
Test name
Test status
Simulation time 23964710 ps
CPU time 1.21 seconds
Started Jun 25 05:50:02 PM PDT 24
Finished Jun 25 05:50:06 PM PDT 24
Peak memory 218868 kb
Host smart-ed43b590-c9b7-4076-bc56-d828652abf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734887137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.734887137
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.1523824726
Short name T131
Test name
Test status
Simulation time 30565610 ps
CPU time 1.31 seconds
Started Jun 25 05:50:00 PM PDT 24
Finished Jun 25 05:50:03 PM PDT 24
Peak memory 220952 kb
Host smart-5f14ec28-1668-4161-a4ab-b503ec1e3b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523824726 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1523824726
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3565604074
Short name T526
Test name
Test status
Simulation time 38507266 ps
CPU time 1.14 seconds
Started Jun 25 05:50:00 PM PDT 24
Finished Jun 25 05:50:02 PM PDT 24
Peak memory 220228 kb
Host smart-1b9d753c-c0d4-419c-a749-c1832550360f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565604074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3565604074
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.1102551870
Short name T111
Test name
Test status
Simulation time 30738872 ps
CPU time 1.36 seconds
Started Jun 25 05:50:02 PM PDT 24
Finished Jun 25 05:50:06 PM PDT 24
Peak memory 220328 kb
Host smart-938acdf6-3527-4a64-98bd-b9fa6369ab0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102551870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.1102551870
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.2188675114
Short name T747
Test name
Test status
Simulation time 27568470 ps
CPU time 0.86 seconds
Started Jun 25 05:50:00 PM PDT 24
Finished Jun 25 05:50:02 PM PDT 24
Peak memory 218736 kb
Host smart-04d8edc7-9bc4-45bc-8227-3e1c880847eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188675114 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2188675114
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2891507976
Short name T399
Test name
Test status
Simulation time 54514209 ps
CPU time 2.03 seconds
Started Jun 25 05:50:00 PM PDT 24
Finished Jun 25 05:50:03 PM PDT 24
Peak memory 219924 kb
Host smart-8a12dd6f-73c5-4be3-8022-bfffec9f4e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891507976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2891507976
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.613728664
Short name T770
Test name
Test status
Simulation time 30173268 ps
CPU time 1.38 seconds
Started Jun 25 05:50:05 PM PDT 24
Finished Jun 25 05:50:07 PM PDT 24
Peak memory 220148 kb
Host smart-06f10040-51ab-48b7-9654-a342784f118c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613728664 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.613728664
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_genbits.3560626746
Short name T595
Test name
Test status
Simulation time 63309459 ps
CPU time 1.25 seconds
Started Jun 25 05:50:02 PM PDT 24
Finished Jun 25 05:50:06 PM PDT 24
Peak memory 219184 kb
Host smart-39a66977-6c7f-40a0-b254-831158a7d952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560626746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3560626746
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.3689395
Short name T929
Test name
Test status
Simulation time 278379004 ps
CPU time 1.11 seconds
Started Jun 25 05:50:01 PM PDT 24
Finished Jun 25 05:50:04 PM PDT 24
Peak memory 218936 kb
Host smart-f5aeb5bc-c79a-434e-b1ea-f15128a3261c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.3689395
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.4010238766
Short name T689
Test name
Test status
Simulation time 68859182 ps
CPU time 0.83 seconds
Started Jun 25 05:50:05 PM PDT 24
Finished Jun 25 05:50:07 PM PDT 24
Peak memory 218824 kb
Host smart-9b4264a8-8cac-480c-9187-40528ae05765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010238766 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.4010238766
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1001457053
Short name T522
Test name
Test status
Simulation time 35653538 ps
CPU time 1.36 seconds
Started Jun 25 05:50:01 PM PDT 24
Finished Jun 25 05:50:05 PM PDT 24
Peak memory 217676 kb
Host smart-59fd2ff0-836b-42b7-ab0d-60b6cfe9ec98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001457053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1001457053
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.3232362435
Short name T135
Test name
Test status
Simulation time 88151358 ps
CPU time 1.35 seconds
Started Jun 25 05:50:00 PM PDT 24
Finished Jun 25 05:50:03 PM PDT 24
Peak memory 220104 kb
Host smart-c8ba39bb-1013-4929-aa8f-2888443d6f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232362435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.3232362435
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.4168975270
Short name T165
Test name
Test status
Simulation time 25201284 ps
CPU time 0.97 seconds
Started Jun 25 05:50:03 PM PDT 24
Finished Jun 25 05:50:06 PM PDT 24
Peak memory 219192 kb
Host smart-02c71ea9-2b14-4fdf-aceb-73be0b15cd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168975270 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.4168975270
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.654938633
Short name T917
Test name
Test status
Simulation time 58541436 ps
CPU time 1.22 seconds
Started Jun 25 05:50:01 PM PDT 24
Finished Jun 25 05:50:04 PM PDT 24
Peak memory 217792 kb
Host smart-7049fa11-16ab-49f2-99f0-04608eba23ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654938633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.654938633
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2812629842
Short name T152
Test name
Test status
Simulation time 52022322 ps
CPU time 1.27 seconds
Started Jun 25 05:48:23 PM PDT 24
Finished Jun 25 05:48:25 PM PDT 24
Peak memory 215968 kb
Host smart-eb318cd0-9525-4a1c-b1e6-7971ee922b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812629842 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2812629842
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2379975104
Short name T574
Test name
Test status
Simulation time 55844040 ps
CPU time 0.89 seconds
Started Jun 25 05:48:29 PM PDT 24
Finished Jun 25 05:48:31 PM PDT 24
Peak memory 207048 kb
Host smart-fd509d73-073d-4dca-88fd-9149c34fc32a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379975104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2379975104
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2091018517
Short name T196
Test name
Test status
Simulation time 15651637 ps
CPU time 0.94 seconds
Started Jun 25 05:48:22 PM PDT 24
Finished Jun 25 05:48:24 PM PDT 24
Peak memory 216756 kb
Host smart-f9f05222-71e3-4257-9b0a-9f104d117ee9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091018517 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2091018517
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1409429284
Short name T289
Test name
Test status
Simulation time 258964518 ps
CPU time 1.29 seconds
Started Jun 25 05:48:21 PM PDT 24
Finished Jun 25 05:48:23 PM PDT 24
Peak memory 217152 kb
Host smart-a477e9cf-8029-48a7-8039-e061a9b25a7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409429284 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1409429284
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2076060423
Short name T753
Test name
Test status
Simulation time 19130061 ps
CPU time 1.1 seconds
Started Jun 25 05:48:22 PM PDT 24
Finished Jun 25 05:48:24 PM PDT 24
Peak memory 218716 kb
Host smart-a55cf9f2-fb9a-44a1-b6db-81d4df1e3b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076060423 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2076060423
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1901278306
Short name T94
Test name
Test status
Simulation time 38601021 ps
CPU time 1.6 seconds
Started Jun 25 05:48:23 PM PDT 24
Finished Jun 25 05:48:26 PM PDT 24
Peak memory 220104 kb
Host smart-6a446b61-3839-445b-893c-1e2afc6136ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901278306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1901278306
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2756027059
Short name T754
Test name
Test status
Simulation time 26774286 ps
CPU time 0.91 seconds
Started Jun 25 05:48:20 PM PDT 24
Finished Jun 25 05:48:22 PM PDT 24
Peak memory 216184 kb
Host smart-8a05aebb-6ad5-42ee-8518-dba8f073a493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756027059 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2756027059
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.2566426138
Short name T315
Test name
Test status
Simulation time 17157339 ps
CPU time 0.97 seconds
Started Jun 25 05:48:30 PM PDT 24
Finished Jun 25 05:48:32 PM PDT 24
Peak memory 207372 kb
Host smart-0956a944-c016-4e7d-9090-499fdf387976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566426138 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2566426138
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1615418930
Short name T597
Test name
Test status
Simulation time 18523663 ps
CPU time 1.02 seconds
Started Jun 25 05:48:22 PM PDT 24
Finished Jun 25 05:48:24 PM PDT 24
Peak memory 215648 kb
Host smart-4162ca35-4b30-4b18-8ce8-13ab54368d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615418930 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1615418930
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.271854227
Short name T251
Test name
Test status
Simulation time 174744870 ps
CPU time 2.51 seconds
Started Jun 25 05:48:22 PM PDT 24
Finished Jun 25 05:48:25 PM PDT 24
Peak memory 215512 kb
Host smart-109dae0b-064f-4f0d-871e-43068cc58661
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271854227 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.271854227
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.429495394
Short name T810
Test name
Test status
Simulation time 40789011880 ps
CPU time 918.47 seconds
Started Jun 25 05:48:22 PM PDT 24
Finished Jun 25 06:03:42 PM PDT 24
Peak memory 219388 kb
Host smart-c6faeba1-e699-48d6-9f39-0fb98296a5c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429495394 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.429495394
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.1542288412
Short name T428
Test name
Test status
Simulation time 89137597 ps
CPU time 1.21 seconds
Started Jun 25 05:50:03 PM PDT 24
Finished Jun 25 05:50:06 PM PDT 24
Peak memory 219972 kb
Host smart-9235899c-66ab-422e-82e5-c22aa0b2fe48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542288412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1542288412
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.2870977533
Short name T973
Test name
Test status
Simulation time 44816092 ps
CPU time 1.19 seconds
Started Jun 25 05:50:01 PM PDT 24
Finished Jun 25 05:50:05 PM PDT 24
Peak memory 220048 kb
Host smart-54d892ed-9df8-4b9e-a23f-a1666c90b248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870977533 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2870977533
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.398393500
Short name T612
Test name
Test status
Simulation time 60086922 ps
CPU time 2.22 seconds
Started Jun 25 05:50:01 PM PDT 24
Finished Jun 25 05:50:05 PM PDT 24
Peak memory 218860 kb
Host smart-ad697e5c-adc6-4f1e-bd5a-f5f18d287019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398393500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.398393500
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1242677931
Short name T726
Test name
Test status
Simulation time 24947933 ps
CPU time 1.23 seconds
Started Jun 25 05:50:02 PM PDT 24
Finished Jun 25 05:50:06 PM PDT 24
Peak memory 219016 kb
Host smart-0d68a84e-ee51-4dad-917a-498ce279d8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242677931 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1242677931
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.2270064810
Short name T80
Test name
Test status
Simulation time 24558068 ps
CPU time 1.07 seconds
Started Jun 25 05:50:02 PM PDT 24
Finished Jun 25 05:50:04 PM PDT 24
Peak memory 218692 kb
Host smart-0359ef44-9c13-49d6-b4a8-c88a3d0c82c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270064810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2270064810
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2834421525
Short name T356
Test name
Test status
Simulation time 38738305 ps
CPU time 1.42 seconds
Started Jun 25 05:50:01 PM PDT 24
Finished Jun 25 05:50:04 PM PDT 24
Peak memory 220308 kb
Host smart-bbde902b-d0fb-4a81-b691-898619490dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834421525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2834421525
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.4010569003
Short name T454
Test name
Test status
Simulation time 211523713 ps
CPU time 1.16 seconds
Started Jun 25 05:50:05 PM PDT 24
Finished Jun 25 05:50:07 PM PDT 24
Peak memory 219932 kb
Host smart-726aac43-52b3-4097-8488-1e076941a074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010569003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.4010569003
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.3874204120
Short name T938
Test name
Test status
Simulation time 25951943 ps
CPU time 0.99 seconds
Started Jun 25 05:50:05 PM PDT 24
Finished Jun 25 05:50:07 PM PDT 24
Peak memory 219996 kb
Host smart-f09549c5-c3a4-41f2-963c-bc558d3c860c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874204120 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3874204120
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1529635191
Short name T677
Test name
Test status
Simulation time 39491922 ps
CPU time 1.19 seconds
Started Jun 25 05:50:02 PM PDT 24
Finished Jun 25 05:50:05 PM PDT 24
Peak memory 219124 kb
Host smart-c5aed03e-c2b6-47ea-b086-4170d16e6a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529635191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1529635191
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.1471081857
Short name T164
Test name
Test status
Simulation time 41701257 ps
CPU time 1.27 seconds
Started Jun 25 05:50:02 PM PDT 24
Finished Jun 25 05:50:05 PM PDT 24
Peak memory 225992 kb
Host smart-ab15d021-f972-4f45-a606-1c019c5aab88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471081857 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1471081857
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2390506180
Short name T900
Test name
Test status
Simulation time 277684910 ps
CPU time 3.06 seconds
Started Jun 25 05:50:05 PM PDT 24
Finished Jun 25 05:50:09 PM PDT 24
Peak memory 220212 kb
Host smart-2794e6c7-5c95-4598-8bd2-430aac9e6946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390506180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2390506180
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.998389689
Short name T700
Test name
Test status
Simulation time 25517294 ps
CPU time 1.19 seconds
Started Jun 25 05:50:05 PM PDT 24
Finished Jun 25 05:50:08 PM PDT 24
Peak memory 218852 kb
Host smart-f0f4d301-3ca1-4002-97f7-5f3639b5098b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998389689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.998389689
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.727246194
Short name T215
Test name
Test status
Simulation time 32014468 ps
CPU time 0.92 seconds
Started Jun 25 05:49:59 PM PDT 24
Finished Jun 25 05:50:01 PM PDT 24
Peak memory 219068 kb
Host smart-50bd1e47-7510-4afc-965c-b8a40ec1a591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727246194 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.727246194
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.747164689
Short name T552
Test name
Test status
Simulation time 73218854 ps
CPU time 2.71 seconds
Started Jun 25 05:50:02 PM PDT 24
Finished Jun 25 05:50:06 PM PDT 24
Peak memory 220068 kb
Host smart-2d109db7-b0b7-4378-a7be-142fd16e7927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747164689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.747164689
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.749025957
Short name T23
Test name
Test status
Simulation time 84669712 ps
CPU time 1.1 seconds
Started Jun 25 05:50:11 PM PDT 24
Finished Jun 25 05:50:13 PM PDT 24
Peak memory 218840 kb
Host smart-5da05c80-0624-4157-ac93-0f2cf690c158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749025957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.749025957
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.4047727067
Short name T208
Test name
Test status
Simulation time 31117543 ps
CPU time 0.9 seconds
Started Jun 25 05:50:13 PM PDT 24
Finished Jun 25 05:50:16 PM PDT 24
Peak memory 219068 kb
Host smart-9e7c9cca-7c41-4693-a3ee-74bb3d4e25ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047727067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.4047727067
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3621004614
Short name T380
Test name
Test status
Simulation time 27449354 ps
CPU time 1.16 seconds
Started Jun 25 05:50:09 PM PDT 24
Finished Jun 25 05:50:11 PM PDT 24
Peak memory 219796 kb
Host smart-54b091cc-406f-4bce-8315-5f1559fd0695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621004614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3621004614
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.1139660396
Short name T538
Test name
Test status
Simulation time 86349944 ps
CPU time 1.19 seconds
Started Jun 25 05:50:11 PM PDT 24
Finished Jun 25 05:50:13 PM PDT 24
Peak memory 219044 kb
Host smart-5b51b77f-ea42-4d1d-a490-84627f48db3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139660396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.1139660396
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1237965693
Short name T17
Test name
Test status
Simulation time 19026125 ps
CPU time 1.16 seconds
Started Jun 25 05:50:10 PM PDT 24
Finished Jun 25 05:50:12 PM PDT 24
Peak memory 224292 kb
Host smart-3d977a42-9c61-47c8-8131-02014a211850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237965693 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1237965693
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1964023171
Short name T829
Test name
Test status
Simulation time 108885688 ps
CPU time 1.01 seconds
Started Jun 25 05:50:10 PM PDT 24
Finished Jun 25 05:50:12 PM PDT 24
Peak memory 217808 kb
Host smart-419ea473-0dc7-4ac8-9006-97b41cd44765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964023171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1964023171
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.1715556452
Short name T590
Test name
Test status
Simulation time 24830168 ps
CPU time 1.16 seconds
Started Jun 25 05:50:11 PM PDT 24
Finished Jun 25 05:50:14 PM PDT 24
Peak memory 218940 kb
Host smart-1c54d7ca-245e-461c-8a1a-0d65ab90a354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715556452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.1715556452
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1595588192
Short name T785
Test name
Test status
Simulation time 20981431 ps
CPU time 1.12 seconds
Started Jun 25 05:50:11 PM PDT 24
Finished Jun 25 05:50:13 PM PDT 24
Peak memory 219976 kb
Host smart-cd4b04f9-93a5-4435-b83b-d9a6bd616c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595588192 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1595588192
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2606582659
Short name T543
Test name
Test status
Simulation time 67968543 ps
CPU time 1.37 seconds
Started Jun 25 05:50:10 PM PDT 24
Finished Jun 25 05:50:11 PM PDT 24
Peak memory 217796 kb
Host smart-be8b2835-86a6-4966-b263-4f5e71014887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606582659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2606582659
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.3182728110
Short name T828
Test name
Test status
Simulation time 168786367 ps
CPU time 1.12 seconds
Started Jun 25 05:50:12 PM PDT 24
Finished Jun 25 05:50:15 PM PDT 24
Peak memory 219908 kb
Host smart-5b1061c0-ba7e-412b-bcca-d032b93ede1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182728110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.3182728110
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.1366502334
Short name T144
Test name
Test status
Simulation time 23619731 ps
CPU time 1.14 seconds
Started Jun 25 05:50:10 PM PDT 24
Finished Jun 25 05:50:12 PM PDT 24
Peak memory 220116 kb
Host smart-98c99282-31f0-4883-b69a-cbbed9be74d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366502334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1366502334
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3940963808
Short name T823
Test name
Test status
Simulation time 44614843 ps
CPU time 1.95 seconds
Started Jun 25 05:50:11 PM PDT 24
Finished Jun 25 05:50:15 PM PDT 24
Peak memory 218984 kb
Host smart-438d78c7-e2c7-49fc-b9ec-b295cb5f3e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940963808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3940963808
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.1467364622
Short name T431
Test name
Test status
Simulation time 107441074 ps
CPU time 1.27 seconds
Started Jun 25 05:50:10 PM PDT 24
Finished Jun 25 05:50:12 PM PDT 24
Peak memory 218680 kb
Host smart-5c60e357-10ce-4c70-8209-d57e2a03cf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467364622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.1467364622
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2922123465
Short name T881
Test name
Test status
Simulation time 37058260 ps
CPU time 0.98 seconds
Started Jun 25 05:50:11 PM PDT 24
Finished Jun 25 05:50:13 PM PDT 24
Peak memory 219972 kb
Host smart-76fbfd02-fa9e-45ba-812f-1b59de0185f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922123465 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2922123465
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.684470201
Short name T3
Test name
Test status
Simulation time 75092862 ps
CPU time 1.18 seconds
Started Jun 25 05:50:14 PM PDT 24
Finished Jun 25 05:50:16 PM PDT 24
Peak memory 219272 kb
Host smart-4033b678-f444-4827-82ad-fde2fa0f7447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684470201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.684470201
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2303828605
Short name T226
Test name
Test status
Simulation time 235552907 ps
CPU time 1.33 seconds
Started Jun 25 05:48:30 PM PDT 24
Finished Jun 25 05:48:33 PM PDT 24
Peak memory 216036 kb
Host smart-89c63ce1-6229-4a61-b939-669f85cfcfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303828605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2303828605
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3855073631
Short name T398
Test name
Test status
Simulation time 42774255 ps
CPU time 0.84 seconds
Started Jun 25 05:48:29 PM PDT 24
Finished Jun 25 05:48:30 PM PDT 24
Peak memory 215204 kb
Host smart-1b1bc24c-2a0b-45b9-b863-74faeb52c9e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855073631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3855073631
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1867024175
Short name T588
Test name
Test status
Simulation time 11784290 ps
CPU time 0.94 seconds
Started Jun 25 05:48:33 PM PDT 24
Finished Jun 25 05:48:35 PM PDT 24
Peak memory 215936 kb
Host smart-4320af33-3b48-4822-9cca-1fb93a7a24b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867024175 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1867024175
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.135001559
Short name T145
Test name
Test status
Simulation time 18462553 ps
CPU time 1.04 seconds
Started Jun 25 05:48:32 PM PDT 24
Finished Jun 25 05:48:35 PM PDT 24
Peak memory 217116 kb
Host smart-b00ee852-5505-409f-831c-032d26103fc5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135001559 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.135001559
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3774409424
Short name T183
Test name
Test status
Simulation time 30515253 ps
CPU time 1.03 seconds
Started Jun 25 05:48:32 PM PDT 24
Finished Jun 25 05:48:35 PM PDT 24
Peak memory 224100 kb
Host smart-27239c4a-4d0b-4ff5-aac9-08e49b90f981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774409424 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3774409424
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2004087249
Short name T470
Test name
Test status
Simulation time 50257914 ps
CPU time 1.33 seconds
Started Jun 25 05:48:22 PM PDT 24
Finished Jun 25 05:48:25 PM PDT 24
Peak memory 217644 kb
Host smart-f5fafe60-829f-4d45-9927-14866fe7c0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004087249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2004087249
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.525942962
Short name T527
Test name
Test status
Simulation time 32993424 ps
CPU time 1.01 seconds
Started Jun 25 05:48:22 PM PDT 24
Finished Jun 25 05:48:23 PM PDT 24
Peak memory 224412 kb
Host smart-5845ba22-3755-4687-b079-596c3aa1d540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525942962 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.525942962
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.944194362
Short name T2
Test name
Test status
Simulation time 28799991 ps
CPU time 0.95 seconds
Started Jun 25 05:48:21 PM PDT 24
Finished Jun 25 05:48:23 PM PDT 24
Peak memory 207440 kb
Host smart-5366d29e-65f3-492b-8714-d3ba312a9967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944194362 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.944194362
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1126730736
Short name T444
Test name
Test status
Simulation time 68499924 ps
CPU time 0.9 seconds
Started Jun 25 05:48:30 PM PDT 24
Finished Jun 25 05:48:32 PM PDT 24
Peak memory 215440 kb
Host smart-5b6cd6d0-8fa5-49b2-954a-172d96abb529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126730736 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1126730736
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3539591569
Short name T75
Test name
Test status
Simulation time 339640801 ps
CPU time 2.86 seconds
Started Jun 25 05:48:23 PM PDT 24
Finished Jun 25 05:48:27 PM PDT 24
Peak memory 217680 kb
Host smart-e025d6c4-3fe0-4053-8ea4-17b3458008b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539591569 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3539591569
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2098039965
Short name T863
Test name
Test status
Simulation time 37734739521 ps
CPU time 208.54 seconds
Started Jun 25 05:48:30 PM PDT 24
Finished Jun 25 05:52:00 PM PDT 24
Peak memory 218660 kb
Host smart-8b949a5d-799c-4982-95e4-949bf1725ec6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098039965 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2098039965
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.3541967111
Short name T545
Test name
Test status
Simulation time 45041944 ps
CPU time 1.2 seconds
Started Jun 25 05:50:09 PM PDT 24
Finished Jun 25 05:50:11 PM PDT 24
Peak memory 220192 kb
Host smart-da36e8e5-205d-4aa4-9a17-edc1c7b17dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541967111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.3541967111
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.3035881392
Short name T139
Test name
Test status
Simulation time 30704605 ps
CPU time 0.94 seconds
Started Jun 25 05:50:13 PM PDT 24
Finished Jun 25 05:50:16 PM PDT 24
Peak memory 219896 kb
Host smart-534c132c-d53e-41ac-8910-bfe4e2794be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035881392 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3035881392
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3251502566
Short name T608
Test name
Test status
Simulation time 37175925 ps
CPU time 1.49 seconds
Started Jun 25 05:50:15 PM PDT 24
Finished Jun 25 05:50:17 PM PDT 24
Peak memory 215564 kb
Host smart-0db09243-2bec-49e2-908a-38d54222c598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251502566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3251502566
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.992079998
Short name T113
Test name
Test status
Simulation time 26268422 ps
CPU time 1.26 seconds
Started Jun 25 05:50:16 PM PDT 24
Finished Jun 25 05:50:18 PM PDT 24
Peak memory 220132 kb
Host smart-0427ac70-fc95-4820-b4df-014d5b54a509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992079998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.992079998
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.570184591
Short name T184
Test name
Test status
Simulation time 20951931 ps
CPU time 0.94 seconds
Started Jun 25 05:50:11 PM PDT 24
Finished Jun 25 05:50:14 PM PDT 24
Peak memory 218728 kb
Host smart-373ad592-0bef-4b3d-b0bd-cb28e5823481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570184591 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.570184591
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.4261579374
Short name T573
Test name
Test status
Simulation time 44840989 ps
CPU time 1.4 seconds
Started Jun 25 05:50:11 PM PDT 24
Finished Jun 25 05:50:13 PM PDT 24
Peak memory 217588 kb
Host smart-3483eec0-7dec-4e1c-8db1-82be5e08209a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261579374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.4261579374
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.2572737963
Short name T953
Test name
Test status
Simulation time 30492414 ps
CPU time 1.34 seconds
Started Jun 25 05:50:10 PM PDT 24
Finished Jun 25 05:50:12 PM PDT 24
Peak memory 216028 kb
Host smart-897ea832-22fe-4653-9c0b-8c0e8a22a6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572737963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.2572737963
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3455846242
Short name T127
Test name
Test status
Simulation time 25183108 ps
CPU time 1.35 seconds
Started Jun 25 05:50:13 PM PDT 24
Finished Jun 25 05:50:16 PM PDT 24
Peak memory 230060 kb
Host smart-f6c0c702-4376-4c3c-a1c8-75f4cdb7dc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455846242 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3455846242
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.4056904784
Short name T451
Test name
Test status
Simulation time 58633188 ps
CPU time 1.1 seconds
Started Jun 25 05:50:13 PM PDT 24
Finished Jun 25 05:50:16 PM PDT 24
Peak memory 217744 kb
Host smart-07fde6f7-1989-4b75-ac9f-3d2cf25577f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056904784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.4056904784
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.2088840880
Short name T170
Test name
Test status
Simulation time 73063693 ps
CPU time 1.21 seconds
Started Jun 25 05:50:14 PM PDT 24
Finished Jun 25 05:50:16 PM PDT 24
Peak memory 219952 kb
Host smart-23fd47d2-d71b-4159-b85b-7d5d37a65c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088840880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2088840880
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.1907767515
Short name T598
Test name
Test status
Simulation time 22927914 ps
CPU time 0.97 seconds
Started Jun 25 05:50:13 PM PDT 24
Finished Jun 25 05:50:16 PM PDT 24
Peak memory 218964 kb
Host smart-214f0643-7c2e-4686-bf35-75238ad13422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907767515 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1907767515
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2837981985
Short name T570
Test name
Test status
Simulation time 71287646 ps
CPU time 1.66 seconds
Started Jun 25 05:50:14 PM PDT 24
Finished Jun 25 05:50:17 PM PDT 24
Peak memory 219180 kb
Host smart-c3475731-2309-490e-be20-3e8829ea62bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837981985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2837981985
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.2591387923
Short name T719
Test name
Test status
Simulation time 35106691 ps
CPU time 1.18 seconds
Started Jun 25 05:50:16 PM PDT 24
Finished Jun 25 05:50:18 PM PDT 24
Peak memory 219112 kb
Host smart-417e9471-0d42-4891-9572-816eb8f9f23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591387923 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.2591387923
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.1813427093
Short name T77
Test name
Test status
Simulation time 20749529 ps
CPU time 1.12 seconds
Started Jun 25 05:50:14 PM PDT 24
Finished Jun 25 05:50:16 PM PDT 24
Peak memory 219668 kb
Host smart-917b9117-7012-4143-a5f5-52ce55e32139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813427093 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1813427093
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3138314388
Short name T85
Test name
Test status
Simulation time 336256108 ps
CPU time 4.36 seconds
Started Jun 25 05:50:12 PM PDT 24
Finished Jun 25 05:50:18 PM PDT 24
Peak memory 220664 kb
Host smart-7597f004-84cb-4e5b-ae8e-9dbb6521f931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138314388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3138314388
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.835803496
Short name T212
Test name
Test status
Simulation time 28441904 ps
CPU time 0.89 seconds
Started Jun 25 05:50:11 PM PDT 24
Finished Jun 25 05:50:13 PM PDT 24
Peak memory 218872 kb
Host smart-b0c367ed-1b5b-481f-8487-6b4f79d9dd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835803496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.835803496
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.4018564050
Short name T370
Test name
Test status
Simulation time 67538756 ps
CPU time 1.15 seconds
Started Jun 25 05:50:09 PM PDT 24
Finished Jun 25 05:50:11 PM PDT 24
Peak memory 219188 kb
Host smart-ae7b7d7a-1c6c-4678-bd2b-24a5ff981475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018564050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.4018564050
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.154357338
Short name T112
Test name
Test status
Simulation time 25356607 ps
CPU time 1.13 seconds
Started Jun 25 05:50:11 PM PDT 24
Finished Jun 25 05:50:14 PM PDT 24
Peak memory 218968 kb
Host smart-e446ea2f-57f9-4c89-8548-2c7b63aa3836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154357338 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.154357338
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.4153768784
Short name T218
Test name
Test status
Simulation time 30962672 ps
CPU time 1.06 seconds
Started Jun 25 05:50:10 PM PDT 24
Finished Jun 25 05:50:12 PM PDT 24
Peak memory 220300 kb
Host smart-c00803d4-9b6f-4380-acaa-80f60b3c9922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153768784 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.4153768784
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3924535570
Short name T695
Test name
Test status
Simulation time 37785834 ps
CPU time 1.54 seconds
Started Jun 25 05:50:11 PM PDT 24
Finished Jun 25 05:50:13 PM PDT 24
Peak memory 218716 kb
Host smart-ee60aad0-f2ba-47b0-9cfd-6669b7fb56a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924535570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3924535570
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.1670603406
Short name T682
Test name
Test status
Simulation time 64024717 ps
CPU time 1.2 seconds
Started Jun 25 05:50:13 PM PDT 24
Finished Jun 25 05:50:16 PM PDT 24
Peak memory 219436 kb
Host smart-c9563079-a368-44e0-8921-cb3c7749ff35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670603406 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.1670603406
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_genbits.559475847
Short name T404
Test name
Test status
Simulation time 36586746 ps
CPU time 1.38 seconds
Started Jun 25 05:50:10 PM PDT 24
Finished Jun 25 05:50:13 PM PDT 24
Peak memory 220160 kb
Host smart-1f3d0071-721c-49a5-972c-125a37b61eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559475847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.559475847
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.4145993363
Short name T893
Test name
Test status
Simulation time 75425238 ps
CPU time 1.23 seconds
Started Jun 25 05:50:14 PM PDT 24
Finished Jun 25 05:50:17 PM PDT 24
Peak memory 219460 kb
Host smart-e9de591c-45d7-4b61-82bd-ab48ac794034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145993363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.4145993363
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.2873045340
Short name T373
Test name
Test status
Simulation time 55109511 ps
CPU time 0.99 seconds
Started Jun 25 05:50:13 PM PDT 24
Finished Jun 25 05:50:16 PM PDT 24
Peak memory 220028 kb
Host smart-ebd47e2d-fb6f-4ac3-912d-8f4b4e222352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873045340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2873045340
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.167300299
Short name T990
Test name
Test status
Simulation time 80362131 ps
CPU time 1.1 seconds
Started Jun 25 05:50:13 PM PDT 24
Finished Jun 25 05:50:16 PM PDT 24
Peak memory 217836 kb
Host smart-888d166f-8234-4d2a-9263-3118f3cf6549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167300299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.167300299
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.1593004528
Short name T157
Test name
Test status
Simulation time 69789523 ps
CPU time 1.14 seconds
Started Jun 25 05:50:15 PM PDT 24
Finished Jun 25 05:50:17 PM PDT 24
Peak memory 219512 kb
Host smart-9a5288f1-7d25-4b57-9c9d-58fa5e1a6f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593004528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1593004528
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.3750841676
Short name T651
Test name
Test status
Simulation time 23563082 ps
CPU time 1.09 seconds
Started Jun 25 05:50:12 PM PDT 24
Finished Jun 25 05:50:15 PM PDT 24
Peak memory 218688 kb
Host smart-e4303648-ab5a-439d-82d5-f14222ebbab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750841676 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3750841676
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3166683829
Short name T533
Test name
Test status
Simulation time 147996379 ps
CPU time 1.22 seconds
Started Jun 25 05:50:10 PM PDT 24
Finished Jun 25 05:50:12 PM PDT 24
Peak memory 218920 kb
Host smart-d3bb63ea-6ba9-421e-9a57-07699062f03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166683829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3166683829
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2639971905
Short name T255
Test name
Test status
Simulation time 31124057 ps
CPU time 1.38 seconds
Started Jun 25 05:48:33 PM PDT 24
Finished Jun 25 05:48:36 PM PDT 24
Peak memory 216024 kb
Host smart-1327dabc-34dc-41cb-8e75-0e43652fc1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639971905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2639971905
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2655595842
Short name T448
Test name
Test status
Simulation time 88770215 ps
CPU time 0.98 seconds
Started Jun 25 05:48:30 PM PDT 24
Finished Jun 25 05:48:33 PM PDT 24
Peak memory 207052 kb
Host smart-d111f369-b1c5-4a80-859d-ce0ff1cb26b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655595842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2655595842
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3330817974
Short name T877
Test name
Test status
Simulation time 38051669 ps
CPU time 0.88 seconds
Started Jun 25 05:48:32 PM PDT 24
Finished Jun 25 05:48:35 PM PDT 24
Peak memory 216600 kb
Host smart-729ec478-d851-4198-98e4-3b544b95795f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330817974 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3330817974
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1108091825
Short name T536
Test name
Test status
Simulation time 97791507 ps
CPU time 1.14 seconds
Started Jun 25 05:48:32 PM PDT 24
Finished Jun 25 05:48:35 PM PDT 24
Peak memory 217216 kb
Host smart-7a83a49b-3068-4076-adec-a591c4a6aa70
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108091825 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1108091825
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1900754541
Short name T632
Test name
Test status
Simulation time 36000579 ps
CPU time 0.92 seconds
Started Jun 25 05:48:32 PM PDT 24
Finished Jun 25 05:48:34 PM PDT 24
Peak memory 218560 kb
Host smart-fd2c876c-8609-4c4d-bd8a-a9a0fa7a3397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900754541 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1900754541
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1786132683
Short name T393
Test name
Test status
Simulation time 29137506 ps
CPU time 1.38 seconds
Started Jun 25 05:48:28 PM PDT 24
Finished Jun 25 05:48:30 PM PDT 24
Peak memory 217948 kb
Host smart-a420bff7-71c6-4b9b-a0bd-17c53048d6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786132683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1786132683
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.4013219702
Short name T27
Test name
Test status
Simulation time 43927760 ps
CPU time 0.87 seconds
Started Jun 25 05:48:32 PM PDT 24
Finished Jun 25 05:48:35 PM PDT 24
Peak memory 215996 kb
Host smart-e4a56dc5-b928-44b1-9a2f-d3d5d18c1a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013219702 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.4013219702
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3082346345
Short name T599
Test name
Test status
Simulation time 26576342 ps
CPU time 0.98 seconds
Started Jun 25 05:48:30 PM PDT 24
Finished Jun 25 05:48:32 PM PDT 24
Peak memory 207436 kb
Host smart-cc073a8e-aff8-44dc-bcb1-77dd2969d011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082346345 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3082346345
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2888823470
Short name T359
Test name
Test status
Simulation time 14657639 ps
CPU time 0.97 seconds
Started Jun 25 05:48:30 PM PDT 24
Finished Jun 25 05:48:32 PM PDT 24
Peak memory 215636 kb
Host smart-90e58005-92dd-4a17-be3c-40857abb1f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888823470 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2888823470
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3264586505
Short name T571
Test name
Test status
Simulation time 865905307 ps
CPU time 4.24 seconds
Started Jun 25 05:48:32 PM PDT 24
Finished Jun 25 05:48:37 PM PDT 24
Peak memory 217524 kb
Host smart-32e2b0e1-5923-4dd4-9013-508d27845911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264586505 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3264586505
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.570017901
Short name T672
Test name
Test status
Simulation time 206365277928 ps
CPU time 1191.26 seconds
Started Jun 25 05:48:29 PM PDT 24
Finished Jun 25 06:08:21 PM PDT 24
Peak memory 222812 kb
Host smart-da311bb2-0184-4d09-9bf5-f5bf4baa0e16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570017901 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.570017901
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.519783549
Short name T262
Test name
Test status
Simulation time 27687362 ps
CPU time 1.25 seconds
Started Jun 25 05:50:12 PM PDT 24
Finished Jun 25 05:50:14 PM PDT 24
Peak memory 219052 kb
Host smart-ce4af89e-3a21-43f8-a31c-df26e284b8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519783549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.519783549
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.1752319032
Short name T178
Test name
Test status
Simulation time 32287974 ps
CPU time 1.03 seconds
Started Jun 25 05:50:12 PM PDT 24
Finished Jun 25 05:50:15 PM PDT 24
Peak memory 224040 kb
Host smart-67dd9a1e-9e19-47cb-a35b-0a12796a1d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752319032 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1752319032
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3146236373
Short name T350
Test name
Test status
Simulation time 51712059 ps
CPU time 1.64 seconds
Started Jun 25 05:50:12 PM PDT 24
Finished Jun 25 05:50:16 PM PDT 24
Peak memory 218968 kb
Host smart-3841a306-e4ad-4082-af33-ab3a1f8721b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146236373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3146236373
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.386097163
Short name T886
Test name
Test status
Simulation time 43684886 ps
CPU time 1.19 seconds
Started Jun 25 05:50:11 PM PDT 24
Finished Jun 25 05:50:14 PM PDT 24
Peak memory 220448 kb
Host smart-6d5421e5-d442-4aad-84b3-29ae3a034525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386097163 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.386097163
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.3437809569
Short name T180
Test name
Test status
Simulation time 19331235 ps
CPU time 1.1 seconds
Started Jun 25 05:50:11 PM PDT 24
Finished Jun 25 05:50:13 PM PDT 24
Peak memory 218760 kb
Host smart-0cbe2d8d-b744-47c1-ab9d-de61b0b8d4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437809569 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3437809569
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3295303390
Short name T14
Test name
Test status
Simulation time 49772553 ps
CPU time 1.26 seconds
Started Jun 25 05:50:16 PM PDT 24
Finished Jun 25 05:50:19 PM PDT 24
Peak memory 220276 kb
Host smart-ba49cae2-f7d7-4946-956c-c5467cae7bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295303390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3295303390
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.3299066658
Short name T680
Test name
Test status
Simulation time 66017603 ps
CPU time 1.11 seconds
Started Jun 25 05:50:11 PM PDT 24
Finished Jun 25 05:50:14 PM PDT 24
Peak memory 218884 kb
Host smart-a138c4e3-8922-4013-873f-9eaf7cb88ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299066658 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.3299066658
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.98662242
Short name T171
Test name
Test status
Simulation time 21510237 ps
CPU time 0.95 seconds
Started Jun 25 05:50:14 PM PDT 24
Finished Jun 25 05:50:16 PM PDT 24
Peak memory 218752 kb
Host smart-4397312f-a073-4a50-86e2-21e8a635b50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98662242 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.98662242
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.683250608
Short name T790
Test name
Test status
Simulation time 31772167 ps
CPU time 1.42 seconds
Started Jun 25 05:50:13 PM PDT 24
Finished Jun 25 05:50:16 PM PDT 24
Peak memory 218820 kb
Host smart-7069e5ae-8b27-4fac-aa9a-f22493240e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683250608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.683250608
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.1730034019
Short name T972
Test name
Test status
Simulation time 91162190 ps
CPU time 1.16 seconds
Started Jun 25 05:50:20 PM PDT 24
Finished Jun 25 05:50:22 PM PDT 24
Peak memory 219200 kb
Host smart-b53e302c-a4ad-40df-9953-7ad29824f1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730034019 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.1730034019
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.928732090
Short name T260
Test name
Test status
Simulation time 33082421 ps
CPU time 1.07 seconds
Started Jun 25 05:50:25 PM PDT 24
Finished Jun 25 05:50:27 PM PDT 24
Peak memory 221096 kb
Host smart-2df2fa99-bc66-405c-a3e5-986c00c60195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928732090 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.928732090
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2245026803
Short name T384
Test name
Test status
Simulation time 101494401 ps
CPU time 1.16 seconds
Started Jun 25 05:50:20 PM PDT 24
Finished Jun 25 05:50:22 PM PDT 24
Peak memory 217644 kb
Host smart-bb4847a4-8f1a-4188-a2a9-0e9275bf64d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245026803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2245026803
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.1816768786
Short name T567
Test name
Test status
Simulation time 74523378 ps
CPU time 1.19 seconds
Started Jun 25 05:50:22 PM PDT 24
Finished Jun 25 05:50:24 PM PDT 24
Peak memory 218848 kb
Host smart-c3119c84-1576-4181-910d-7fd8e087e65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816768786 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.1816768786
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.2093085566
Short name T153
Test name
Test status
Simulation time 21043650 ps
CPU time 1.22 seconds
Started Jun 25 05:50:20 PM PDT 24
Finished Jun 25 05:50:22 PM PDT 24
Peak memory 220148 kb
Host smart-569bb278-7abc-4561-a6ec-3c63698bb2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093085566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2093085566
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.618881723
Short name T980
Test name
Test status
Simulation time 37898297 ps
CPU time 1.62 seconds
Started Jun 25 05:50:21 PM PDT 24
Finished Jun 25 05:50:23 PM PDT 24
Peak memory 218832 kb
Host smart-aa5a47b0-6dbb-430a-a0dc-efc7c26acadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618881723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.618881723
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.3866010773
Short name T72
Test name
Test status
Simulation time 40447765 ps
CPU time 1.18 seconds
Started Jun 25 05:50:22 PM PDT 24
Finished Jun 25 05:50:24 PM PDT 24
Peak memory 219128 kb
Host smart-2a543ba6-9e84-4be6-b02d-15fdcdfa41b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866010773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.3866010773
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.24282228
Short name T172
Test name
Test status
Simulation time 20086102 ps
CPU time 1.03 seconds
Started Jun 25 05:50:18 PM PDT 24
Finished Jun 25 05:50:20 PM PDT 24
Peak memory 218888 kb
Host smart-07036477-ed37-4a57-9ca5-d9c21f77fc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24282228 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.24282228
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2860990419
Short name T662
Test name
Test status
Simulation time 30918179 ps
CPU time 1.37 seconds
Started Jun 25 05:50:24 PM PDT 24
Finished Jun 25 05:50:27 PM PDT 24
Peak memory 218176 kb
Host smart-8d501c9f-6cd0-459b-8624-06f84190d20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860990419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2860990419
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.804819325
Short name T132
Test name
Test status
Simulation time 29232578 ps
CPU time 1.3 seconds
Started Jun 25 05:50:24 PM PDT 24
Finished Jun 25 05:50:27 PM PDT 24
Peak memory 217708 kb
Host smart-a94ff6ac-4bb0-43dd-99c1-225e370cbece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804819325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.804819325
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3145165288
Short name T257
Test name
Test status
Simulation time 25522102 ps
CPU time 1.27 seconds
Started Jun 25 05:50:23 PM PDT 24
Finished Jun 25 05:50:25 PM PDT 24
Peak memory 217664 kb
Host smart-195ed83e-947b-4e35-bd6b-3c65996997a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145165288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3145165288
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.3916005609
Short name T757
Test name
Test status
Simulation time 102680655 ps
CPU time 1.17 seconds
Started Jun 25 05:50:19 PM PDT 24
Finished Jun 25 05:50:21 PM PDT 24
Peak memory 220744 kb
Host smart-690a9442-f492-4740-a788-2b38dcffa834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916005609 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.3916005609
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.856698163
Short name T442
Test name
Test status
Simulation time 153130383 ps
CPU time 0.89 seconds
Started Jun 25 05:50:28 PM PDT 24
Finished Jun 25 05:50:29 PM PDT 24
Peak memory 220024 kb
Host smart-9e7b2471-35e4-4a45-b7c9-c78ea7c0743f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856698163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.856698163
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.69054136
Short name T655
Test name
Test status
Simulation time 43566915 ps
CPU time 1.26 seconds
Started Jun 25 05:50:26 PM PDT 24
Finished Jun 25 05:50:28 PM PDT 24
Peak memory 218840 kb
Host smart-41bf999b-9d3f-4ea6-b0bf-f211229bcb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69054136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.69054136
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.1811483404
Short name T684
Test name
Test status
Simulation time 55003801 ps
CPU time 1.25 seconds
Started Jun 25 05:50:22 PM PDT 24
Finished Jun 25 05:50:24 PM PDT 24
Peak memory 219072 kb
Host smart-645b070e-7193-4fa3-8024-11877ca39c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811483404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.1811483404
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.3165762200
Short name T721
Test name
Test status
Simulation time 19244209 ps
CPU time 1.18 seconds
Started Jun 25 05:50:22 PM PDT 24
Finished Jun 25 05:50:24 PM PDT 24
Peak memory 224260 kb
Host smart-eb3d5a97-e49f-41b5-a426-9e4574a83eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165762200 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3165762200
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/89.edn_alert.3655170267
Short name T464
Test name
Test status
Simulation time 26742948 ps
CPU time 1.1 seconds
Started Jun 25 05:50:19 PM PDT 24
Finished Jun 25 05:50:21 PM PDT 24
Peak memory 218956 kb
Host smart-adcda123-7d53-4ba6-bc72-3a1aa3ab7cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655170267 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.3655170267
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.513386523
Short name T173
Test name
Test status
Simulation time 19994976 ps
CPU time 1.11 seconds
Started Jun 25 05:50:23 PM PDT 24
Finished Jun 25 05:50:26 PM PDT 24
Peak memory 218760 kb
Host smart-0e273218-5a6b-4dc2-a176-b76a2209c284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513386523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.513386523
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1433048831
Short name T816
Test name
Test status
Simulation time 70213967 ps
CPU time 1.47 seconds
Started Jun 25 05:50:19 PM PDT 24
Finished Jun 25 05:50:22 PM PDT 24
Peak memory 219164 kb
Host smart-3a1acd37-464b-435e-be4c-34eecefe7410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433048831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1433048831
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3760093077
Short name T776
Test name
Test status
Simulation time 65907394 ps
CPU time 1.11 seconds
Started Jun 25 05:48:31 PM PDT 24
Finished Jun 25 05:48:34 PM PDT 24
Peak memory 220236 kb
Host smart-4c1877c3-4e88-4c6a-bc7a-e78b57d785c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760093077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3760093077
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.3642026558
Short name T756
Test name
Test status
Simulation time 28089956 ps
CPU time 0.85 seconds
Started Jun 25 05:48:32 PM PDT 24
Finished Jun 25 05:48:35 PM PDT 24
Peak memory 206840 kb
Host smart-be98f457-7e33-4850-b977-25c753659fdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642026558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3642026558
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1157162927
Short name T185
Test name
Test status
Simulation time 16962848 ps
CPU time 0.91 seconds
Started Jun 25 05:48:30 PM PDT 24
Finished Jun 25 05:48:32 PM PDT 24
Peak memory 216768 kb
Host smart-ee88009f-959f-4abc-b42a-bd538e63dbda
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157162927 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1157162927
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.978912273
Short name T982
Test name
Test status
Simulation time 132564590 ps
CPU time 1.19 seconds
Started Jun 25 05:48:31 PM PDT 24
Finished Jun 25 05:48:34 PM PDT 24
Peak memory 217264 kb
Host smart-812c7f64-5046-4eee-863e-10405dba5743
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978912273 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.978912273
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.521389140
Short name T371
Test name
Test status
Simulation time 21968097 ps
CPU time 1 seconds
Started Jun 25 05:48:42 PM PDT 24
Finished Jun 25 05:48:44 PM PDT 24
Peak memory 218864 kb
Host smart-ce63be22-2126-4a7f-a2fe-05c47137fea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521389140 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.521389140
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1711237050
Short name T899
Test name
Test status
Simulation time 112299084 ps
CPU time 1.66 seconds
Started Jun 25 05:48:32 PM PDT 24
Finished Jun 25 05:48:35 PM PDT 24
Peak memory 219040 kb
Host smart-7c03539c-9892-40ff-aa95-cce6b4c12fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711237050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1711237050
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.639414128
Short name T125
Test name
Test status
Simulation time 21814521 ps
CPU time 1.14 seconds
Started Jun 25 05:48:31 PM PDT 24
Finished Jun 25 05:48:34 PM PDT 24
Peak memory 216104 kb
Host smart-f0a4f98e-aaf1-4ab5-8078-a0984df8d5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639414128 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.639414128
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3985077942
Short name T919
Test name
Test status
Simulation time 26991343 ps
CPU time 0.95 seconds
Started Jun 25 05:48:28 PM PDT 24
Finished Jun 25 05:48:30 PM PDT 24
Peak memory 207444 kb
Host smart-757419af-675d-4dc9-8ad6-f094176e97d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985077942 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3985077942
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.626790401
Short name T678
Test name
Test status
Simulation time 76833517 ps
CPU time 0.95 seconds
Started Jun 25 05:48:29 PM PDT 24
Finished Jun 25 05:48:31 PM PDT 24
Peak memory 207452 kb
Host smart-53c7eb51-7722-4fbf-a893-6253ae2df248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626790401 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.626790401
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1308850227
Short name T510
Test name
Test status
Simulation time 298558300 ps
CPU time 5.41 seconds
Started Jun 25 05:48:30 PM PDT 24
Finished Jun 25 05:48:37 PM PDT 24
Peak memory 220352 kb
Host smart-f14b796c-dcb7-48d3-9499-005d245190a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308850227 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1308850227
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/90.edn_err.1850648574
Short name T138
Test name
Test status
Simulation time 34935695 ps
CPU time 1.11 seconds
Started Jun 25 05:50:22 PM PDT 24
Finished Jun 25 05:50:24 PM PDT 24
Peak memory 219948 kb
Host smart-2b912b37-5494-4fc3-ae1b-fc7195e0d241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850648574 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1850648574
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.760898500
Short name T928
Test name
Test status
Simulation time 149563068 ps
CPU time 1.86 seconds
Started Jun 25 05:50:20 PM PDT 24
Finished Jun 25 05:50:23 PM PDT 24
Peak memory 220192 kb
Host smart-b1da64f9-b0ef-4652-8749-48fed719b498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760898500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.760898500
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.1695382666
Short name T468
Test name
Test status
Simulation time 86820981 ps
CPU time 1.16 seconds
Started Jun 25 05:50:20 PM PDT 24
Finished Jun 25 05:50:22 PM PDT 24
Peak memory 219852 kb
Host smart-8e35927a-13ba-405d-b1ec-ed21b692f7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695382666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.1695382666
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.2207818098
Short name T752
Test name
Test status
Simulation time 45878111 ps
CPU time 1.01 seconds
Started Jun 25 05:50:23 PM PDT 24
Finished Jun 25 05:50:26 PM PDT 24
Peak memory 220120 kb
Host smart-8f7397bf-4746-478f-94a4-94b0c4acf7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207818098 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2207818098
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1496072273
Short name T333
Test name
Test status
Simulation time 142559653 ps
CPU time 2.11 seconds
Started Jun 25 05:50:25 PM PDT 24
Finished Jun 25 05:50:29 PM PDT 24
Peak memory 220044 kb
Host smart-4fb8a7c7-7cd0-48f0-a1b3-6845c62e3eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496072273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1496072273
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.2178562731
Short name T120
Test name
Test status
Simulation time 200883679 ps
CPU time 1.26 seconds
Started Jun 25 05:50:24 PM PDT 24
Finished Jun 25 05:50:26 PM PDT 24
Peak memory 220920 kb
Host smart-9c0ea842-dcc6-451e-8a18-7a48d649a01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178562731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.2178562731
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.3138797524
Short name T8
Test name
Test status
Simulation time 20886821 ps
CPU time 1.2 seconds
Started Jun 25 05:50:26 PM PDT 24
Finished Jun 25 05:50:28 PM PDT 24
Peak memory 220152 kb
Host smart-6c008184-8302-4f3a-9d3a-83b79c29fc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138797524 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3138797524
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3218079422
Short name T35
Test name
Test status
Simulation time 154381068 ps
CPU time 1.06 seconds
Started Jun 25 05:50:19 PM PDT 24
Finished Jun 25 05:50:22 PM PDT 24
Peak memory 217740 kb
Host smart-cafa7724-5a7a-4773-9e9c-c100fcdf1126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218079422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3218079422
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.1105438916
Short name T496
Test name
Test status
Simulation time 71186932 ps
CPU time 1.18 seconds
Started Jun 25 05:50:22 PM PDT 24
Finished Jun 25 05:50:24 PM PDT 24
Peak memory 219092 kb
Host smart-05afe7c1-254c-4966-9a76-25fcf5f7b406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105438916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.1105438916
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.2567069569
Short name T795
Test name
Test status
Simulation time 51261203 ps
CPU time 1.4 seconds
Started Jun 25 05:50:23 PM PDT 24
Finished Jun 25 05:50:26 PM PDT 24
Peak memory 225968 kb
Host smart-cac0793a-b07c-4e3c-912b-677bf3bfcfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567069569 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2567069569
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3081861058
Short name T256
Test name
Test status
Simulation time 169974970 ps
CPU time 2.5 seconds
Started Jun 25 05:50:21 PM PDT 24
Finished Jun 25 05:50:25 PM PDT 24
Peak memory 220496 kb
Host smart-55aa451c-1cd2-4143-998f-8023a4a91331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081861058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3081861058
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1841670838
Short name T169
Test name
Test status
Simulation time 21515536 ps
CPU time 1.16 seconds
Started Jun 25 05:50:20 PM PDT 24
Finished Jun 25 05:50:22 PM PDT 24
Peak memory 219164 kb
Host smart-8f8d93ee-9267-4375-bf3f-48f21e92e8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841670838 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1841670838
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.846855438
Short name T154
Test name
Test status
Simulation time 25175317 ps
CPU time 1.03 seconds
Started Jun 25 05:50:23 PM PDT 24
Finished Jun 25 05:50:25 PM PDT 24
Peak memory 220056 kb
Host smart-ef691357-472b-435b-b80b-2ab1b185ca07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846855438 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.846855438
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.571191756
Short name T758
Test name
Test status
Simulation time 41371466 ps
CPU time 1.39 seconds
Started Jun 25 05:50:20 PM PDT 24
Finished Jun 25 05:50:22 PM PDT 24
Peak memory 218752 kb
Host smart-5154409a-f3a2-4035-822a-3b008f64c596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571191756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.571191756
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.390268036
Short name T225
Test name
Test status
Simulation time 33397584 ps
CPU time 1.15 seconds
Started Jun 25 05:50:21 PM PDT 24
Finished Jun 25 05:50:24 PM PDT 24
Peak memory 220640 kb
Host smart-b9b5afd1-37b1-4b9c-8311-0a4ef4a29f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390268036 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.390268036
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1476945508
Short name T855
Test name
Test status
Simulation time 27921408 ps
CPU time 0.91 seconds
Started Jun 25 05:50:19 PM PDT 24
Finished Jun 25 05:50:21 PM PDT 24
Peak memory 218664 kb
Host smart-6df41138-bd32-45bd-a809-1e07805d02a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476945508 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1476945508
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3185444165
Short name T892
Test name
Test status
Simulation time 57020158 ps
CPU time 1.54 seconds
Started Jun 25 05:50:21 PM PDT 24
Finished Jun 25 05:50:24 PM PDT 24
Peak memory 217548 kb
Host smart-cb133bc2-aead-4423-9861-e203bb37c667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185444165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3185444165
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.3548553210
Short name T163
Test name
Test status
Simulation time 28479321 ps
CPU time 1.35 seconds
Started Jun 25 05:50:23 PM PDT 24
Finished Jun 25 05:50:26 PM PDT 24
Peak memory 220408 kb
Host smart-26831f83-62e0-47b2-8bf1-42c23d2129c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548553210 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.3548553210
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.1285071708
Short name T737
Test name
Test status
Simulation time 61652560 ps
CPU time 1 seconds
Started Jun 25 05:50:21 PM PDT 24
Finished Jun 25 05:50:23 PM PDT 24
Peak memory 224096 kb
Host smart-bfa8f6a3-dfb2-4418-8446-8f52664f6f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285071708 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1285071708
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1417358572
Short name T820
Test name
Test status
Simulation time 36727044 ps
CPU time 1.41 seconds
Started Jun 25 05:50:25 PM PDT 24
Finished Jun 25 05:50:28 PM PDT 24
Peak memory 217768 kb
Host smart-6279a385-45c5-48c3-b289-119515d21b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417358572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1417358572
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.1730989496
Short name T230
Test name
Test status
Simulation time 32287930 ps
CPU time 1.11 seconds
Started Jun 25 05:50:28 PM PDT 24
Finished Jun 25 05:50:29 PM PDT 24
Peak memory 219788 kb
Host smart-cdcc5817-3dbf-43d4-a80e-fba016b8476b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730989496 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.1730989496
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.2179431388
Short name T659
Test name
Test status
Simulation time 26614642 ps
CPU time 1.23 seconds
Started Jun 25 05:50:24 PM PDT 24
Finished Jun 25 05:50:26 PM PDT 24
Peak memory 220952 kb
Host smart-b70c4fa2-9df3-4baa-818e-5817bd0180b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179431388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2179431388
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.427595344
Short name T301
Test name
Test status
Simulation time 52758336 ps
CPU time 1.22 seconds
Started Jun 25 05:50:19 PM PDT 24
Finished Jun 25 05:50:21 PM PDT 24
Peak memory 217608 kb
Host smart-3b6ff21d-197b-4d59-81e0-9ea450385983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427595344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.427595344
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.2058806015
Short name T231
Test name
Test status
Simulation time 54343346 ps
CPU time 1.21 seconds
Started Jun 25 05:50:23 PM PDT 24
Finished Jun 25 05:50:26 PM PDT 24
Peak memory 216116 kb
Host smart-abbd1b2f-8208-418a-94a0-758bb37e17c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058806015 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.2058806015
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.3012226319
Short name T697
Test name
Test status
Simulation time 46158201 ps
CPU time 1.07 seconds
Started Jun 25 05:50:22 PM PDT 24
Finished Jun 25 05:50:24 PM PDT 24
Peak memory 218752 kb
Host smart-026becf9-60ad-4f60-aeb3-1d62d9c12cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012226319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3012226319
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2612291854
Short name T348
Test name
Test status
Simulation time 34815303 ps
CPU time 1.37 seconds
Started Jun 25 05:50:20 PM PDT 24
Finished Jun 25 05:50:22 PM PDT 24
Peak memory 218720 kb
Host smart-a297ee5a-8702-4b01-84d2-bb2a52996294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612291854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2612291854
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.792387651
Short name T197
Test name
Test status
Simulation time 91878571 ps
CPU time 1.06 seconds
Started Jun 25 05:50:25 PM PDT 24
Finished Jun 25 05:50:27 PM PDT 24
Peak memory 220824 kb
Host smart-b48ca008-b3ed-470f-a12f-96210d9bed7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792387651 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.792387651
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.1746564989
Short name T217
Test name
Test status
Simulation time 36878503 ps
CPU time 0.84 seconds
Started Jun 25 05:50:22 PM PDT 24
Finished Jun 25 05:50:24 PM PDT 24
Peak memory 219480 kb
Host smart-dff7c4c2-efed-476c-8fd9-6b27b61bb54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746564989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1746564989
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1659018418
Short name T523
Test name
Test status
Simulation time 36092272 ps
CPU time 1.65 seconds
Started Jun 25 05:50:19 PM PDT 24
Finished Jun 25 05:50:22 PM PDT 24
Peak memory 217772 kb
Host smart-a6eda4dc-d699-4837-9698-e350faa56984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659018418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1659018418
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%