Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.71 98.25 93.85 97.02 93.02 96.37 99.77 91.70


Total test records in report: 1130
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T1016 /workspace/coverage/cover_reg_top/37.edn_intr_test.248879578 Jun 26 06:37:52 PM PDT 24 Jun 26 06:38:00 PM PDT 24 48793016 ps
T1017 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1312198924 Jun 26 06:36:47 PM PDT 24 Jun 26 06:37:15 PM PDT 24 58734944 ps
T1018 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2238233118 Jun 26 06:36:58 PM PDT 24 Jun 26 06:37:26 PM PDT 24 81556166 ps
T269 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.446446206 Jun 26 06:36:48 PM PDT 24 Jun 26 06:37:15 PM PDT 24 21236067 ps
T254 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1115588110 Jun 26 06:36:51 PM PDT 24 Jun 26 06:37:18 PM PDT 24 71772886 ps
T255 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3348935338 Jun 26 06:36:54 PM PDT 24 Jun 26 06:37:21 PM PDT 24 34955016 ps
T1019 /workspace/coverage/cover_reg_top/16.edn_intr_test.2810369648 Jun 26 06:37:35 PM PDT 24 Jun 26 06:37:47 PM PDT 24 49948876 ps
T1020 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1837188323 Jun 26 06:36:58 PM PDT 24 Jun 26 06:37:27 PM PDT 24 102084838 ps
T1021 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3474237072 Jun 26 06:36:34 PM PDT 24 Jun 26 06:36:50 PM PDT 24 26810105 ps
T285 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2800701080 Jun 26 06:36:57 PM PDT 24 Jun 26 06:37:26 PM PDT 24 115096268 ps
T1022 /workspace/coverage/cover_reg_top/22.edn_intr_test.1615796568 Jun 26 06:37:56 PM PDT 24 Jun 26 06:38:03 PM PDT 24 25098494 ps
T1023 /workspace/coverage/cover_reg_top/46.edn_intr_test.3443700331 Jun 26 06:37:50 PM PDT 24 Jun 26 06:37:56 PM PDT 24 16563556 ps
T1024 /workspace/coverage/cover_reg_top/2.edn_intr_test.3121638096 Jun 26 06:36:42 PM PDT 24 Jun 26 06:37:07 PM PDT 24 95500227 ps
T1025 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1170981012 Jun 26 06:36:35 PM PDT 24 Jun 26 06:36:55 PM PDT 24 88861672 ps
T1026 /workspace/coverage/cover_reg_top/15.edn_intr_test.3017768194 Jun 26 06:37:37 PM PDT 24 Jun 26 06:37:48 PM PDT 24 61864148 ps
T1027 /workspace/coverage/cover_reg_top/10.edn_intr_test.118152085 Jun 26 06:37:23 PM PDT 24 Jun 26 06:37:38 PM PDT 24 54656555 ps
T256 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2787583027 Jun 26 06:36:35 PM PDT 24 Jun 26 06:36:52 PM PDT 24 19496208 ps
T1028 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2623436754 Jun 26 06:36:55 PM PDT 24 Jun 26 06:37:21 PM PDT 24 41008575 ps
T284 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2579366129 Jun 26 06:36:51 PM PDT 24 Jun 26 06:37:19 PM PDT 24 152252168 ps
T1029 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2579601252 Jun 26 06:37:13 PM PDT 24 Jun 26 06:37:34 PM PDT 24 69691698 ps
T1030 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.4069052089 Jun 26 06:37:23 PM PDT 24 Jun 26 06:37:39 PM PDT 24 24531474 ps
T1031 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2791989183 Jun 26 06:37:36 PM PDT 24 Jun 26 06:37:48 PM PDT 24 216842894 ps
T1032 /workspace/coverage/cover_reg_top/1.edn_intr_test.2522143274 Jun 26 06:36:59 PM PDT 24 Jun 26 06:37:24 PM PDT 24 18512034 ps
T1033 /workspace/coverage/cover_reg_top/36.edn_intr_test.2571501790 Jun 26 06:37:53 PM PDT 24 Jun 26 06:38:00 PM PDT 24 40474619 ps
T1034 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1612678327 Jun 26 06:37:11 PM PDT 24 Jun 26 06:37:34 PM PDT 24 91701369 ps
T1035 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.214407619 Jun 26 06:37:37 PM PDT 24 Jun 26 06:37:48 PM PDT 24 29847630 ps
T1036 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2140079561 Jun 26 06:36:57 PM PDT 24 Jun 26 06:37:24 PM PDT 24 31111536 ps
T257 /workspace/coverage/cover_reg_top/3.edn_csr_rw.4009811553 Jun 26 06:36:45 PM PDT 24 Jun 26 06:37:10 PM PDT 24 48263578 ps
T1037 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3350597427 Jun 26 06:37:57 PM PDT 24 Jun 26 06:38:04 PM PDT 24 44607842 ps
T1038 /workspace/coverage/cover_reg_top/38.edn_intr_test.2140056002 Jun 26 06:37:55 PM PDT 24 Jun 26 06:38:02 PM PDT 24 88159188 ps
T1039 /workspace/coverage/cover_reg_top/16.edn_tl_errors.357058968 Jun 26 06:37:36 PM PDT 24 Jun 26 06:37:48 PM PDT 24 389541678 ps
T261 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.230139666 Jun 26 06:37:00 PM PDT 24 Jun 26 06:37:27 PM PDT 24 68316257 ps
T1040 /workspace/coverage/cover_reg_top/4.edn_intr_test.1986707275 Jun 26 06:36:47 PM PDT 24 Jun 26 06:37:14 PM PDT 24 14835596 ps
T1041 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.506729779 Jun 26 06:37:23 PM PDT 24 Jun 26 06:37:40 PM PDT 24 158484485 ps
T1042 /workspace/coverage/cover_reg_top/7.edn_intr_test.556396976 Jun 26 06:36:57 PM PDT 24 Jun 26 06:37:24 PM PDT 24 92886801 ps
T1043 /workspace/coverage/cover_reg_top/34.edn_intr_test.308828328 Jun 26 06:37:57 PM PDT 24 Jun 26 06:38:03 PM PDT 24 34304852 ps
T1044 /workspace/coverage/cover_reg_top/18.edn_intr_test.2620306802 Jun 26 06:37:55 PM PDT 24 Jun 26 06:38:02 PM PDT 24 67433585 ps
T1045 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3745841848 Jun 26 06:36:55 PM PDT 24 Jun 26 06:37:21 PM PDT 24 31915362 ps
T1046 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3638166055 Jun 26 06:37:22 PM PDT 24 Jun 26 06:37:39 PM PDT 24 436087931 ps
T286 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2877334727 Jun 26 06:36:45 PM PDT 24 Jun 26 06:37:13 PM PDT 24 140309148 ps
T1047 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.717935168 Jun 26 06:37:22 PM PDT 24 Jun 26 06:37:38 PM PDT 24 171566729 ps
T1048 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2165589427 Jun 26 06:37:09 PM PDT 24 Jun 26 06:37:35 PM PDT 24 233567255 ps
T1049 /workspace/coverage/cover_reg_top/13.edn_intr_test.3784017553 Jun 26 06:37:36 PM PDT 24 Jun 26 06:37:47 PM PDT 24 13660492 ps
T1050 /workspace/coverage/cover_reg_top/35.edn_intr_test.2216581710 Jun 26 06:38:57 PM PDT 24 Jun 26 06:39:05 PM PDT 24 10442444 ps
T1051 /workspace/coverage/cover_reg_top/31.edn_intr_test.104218446 Jun 26 06:37:50 PM PDT 24 Jun 26 06:37:56 PM PDT 24 30926282 ps
T287 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.972150524 Jun 26 06:37:37 PM PDT 24 Jun 26 06:37:56 PM PDT 24 547984371 ps
T1052 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.753426677 Jun 26 06:37:23 PM PDT 24 Jun 26 06:37:39 PM PDT 24 98554112 ps
T1053 /workspace/coverage/cover_reg_top/26.edn_intr_test.2135460715 Jun 26 06:37:57 PM PDT 24 Jun 26 06:38:04 PM PDT 24 14604708 ps
T288 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1073832727 Jun 26 06:37:50 PM PDT 24 Jun 26 06:37:59 PM PDT 24 154474276 ps
T1054 /workspace/coverage/cover_reg_top/14.edn_intr_test.2799026152 Jun 26 06:37:38 PM PDT 24 Jun 26 06:37:49 PM PDT 24 23530827 ps
T1055 /workspace/coverage/cover_reg_top/42.edn_intr_test.616504704 Jun 26 06:37:51 PM PDT 24 Jun 26 06:37:57 PM PDT 24 14375926 ps
T1056 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3382429611 Jun 26 06:36:59 PM PDT 24 Jun 26 06:37:33 PM PDT 24 631580390 ps
T1057 /workspace/coverage/cover_reg_top/30.edn_intr_test.2551771971 Jun 26 06:37:53 PM PDT 24 Jun 26 06:38:00 PM PDT 24 46668947 ps
T1058 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1146948555 Jun 26 06:36:50 PM PDT 24 Jun 26 06:37:16 PM PDT 24 142042061 ps
T1059 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1448938251 Jun 26 06:36:46 PM PDT 24 Jun 26 06:37:14 PM PDT 24 58844538 ps
T1060 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1873406627 Jun 26 06:37:52 PM PDT 24 Jun 26 06:37:59 PM PDT 24 68549950 ps
T1061 /workspace/coverage/cover_reg_top/15.edn_tl_errors.3699370995 Jun 26 06:37:37 PM PDT 24 Jun 26 06:37:50 PM PDT 24 82370811 ps
T1062 /workspace/coverage/cover_reg_top/19.edn_intr_test.2128968999 Jun 26 06:37:56 PM PDT 24 Jun 26 06:38:03 PM PDT 24 24626642 ps
T1063 /workspace/coverage/cover_reg_top/24.edn_intr_test.3950004269 Jun 26 06:37:50 PM PDT 24 Jun 26 06:37:57 PM PDT 24 31328660 ps
T1064 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1958043544 Jun 26 06:37:25 PM PDT 24 Jun 26 06:37:39 PM PDT 24 132528779 ps
T1065 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.339026509 Jun 26 06:36:51 PM PDT 24 Jun 26 06:37:19 PM PDT 24 60662748 ps
T1066 /workspace/coverage/cover_reg_top/20.edn_intr_test.371789427 Jun 26 06:37:56 PM PDT 24 Jun 26 06:38:03 PM PDT 24 12321502 ps
T1067 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1143209331 Jun 26 06:37:36 PM PDT 24 Jun 26 06:37:47 PM PDT 24 77945220 ps
T1068 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.4056033771 Jun 26 06:37:36 PM PDT 24 Jun 26 06:37:48 PM PDT 24 29178272 ps
T1069 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3353357529 Jun 26 06:37:36 PM PDT 24 Jun 26 06:37:47 PM PDT 24 21826022 ps
T1070 /workspace/coverage/cover_reg_top/29.edn_intr_test.1872849787 Jun 26 06:37:53 PM PDT 24 Jun 26 06:38:00 PM PDT 24 12413441 ps
T1071 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1650935010 Jun 26 06:37:35 PM PDT 24 Jun 26 06:37:47 PM PDT 24 42536730 ps
T1072 /workspace/coverage/cover_reg_top/2.edn_tl_errors.95037025 Jun 26 06:36:47 PM PDT 24 Jun 26 06:37:14 PM PDT 24 241801192 ps
T1073 /workspace/coverage/cover_reg_top/27.edn_intr_test.3517688284 Jun 26 06:37:56 PM PDT 24 Jun 26 06:38:03 PM PDT 24 33012772 ps
T1074 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1336457162 Jun 26 06:37:23 PM PDT 24 Jun 26 06:37:40 PM PDT 24 291927139 ps
T1075 /workspace/coverage/cover_reg_top/8.edn_intr_test.2941642117 Jun 26 06:37:09 PM PDT 24 Jun 26 06:37:32 PM PDT 24 23896167 ps
T1076 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3825514140 Jun 26 06:37:21 PM PDT 24 Jun 26 06:37:40 PM PDT 24 94186929 ps
T1077 /workspace/coverage/cover_reg_top/49.edn_intr_test.1000777867 Jun 26 06:38:12 PM PDT 24 Jun 26 06:38:17 PM PDT 24 18734051 ps
T1078 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1287596484 Jun 26 06:37:37 PM PDT 24 Jun 26 06:37:49 PM PDT 24 52762147 ps
T258 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.201902768 Jun 26 06:36:40 PM PDT 24 Jun 26 06:37:03 PM PDT 24 34834164 ps
T1079 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2982671383 Jun 26 06:36:35 PM PDT 24 Jun 26 06:36:53 PM PDT 24 128845009 ps
T1080 /workspace/coverage/cover_reg_top/28.edn_intr_test.2703663418 Jun 26 06:37:53 PM PDT 24 Jun 26 06:38:00 PM PDT 24 50402913 ps
T259 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1731524618 Jun 26 06:37:08 PM PDT 24 Jun 26 06:37:32 PM PDT 24 30168921 ps
T1081 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4210990294 Jun 26 06:37:37 PM PDT 24 Jun 26 06:37:48 PM PDT 24 55221104 ps
T1082 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1087514934 Jun 26 06:37:56 PM PDT 24 Jun 26 06:38:05 PM PDT 24 198937581 ps
T1083 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3495223039 Jun 26 06:37:50 PM PDT 24 Jun 26 06:37:57 PM PDT 24 63764131 ps
T1084 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3729483436 Jun 26 06:37:35 PM PDT 24 Jun 26 06:37:46 PM PDT 24 42161750 ps
T1085 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2981144585 Jun 26 06:37:00 PM PDT 24 Jun 26 06:37:26 PM PDT 24 12352325 ps
T1086 /workspace/coverage/cover_reg_top/40.edn_intr_test.1263606655 Jun 26 06:37:52 PM PDT 24 Jun 26 06:37:58 PM PDT 24 35499372 ps
T1087 /workspace/coverage/cover_reg_top/5.edn_csr_rw.990186885 Jun 26 06:36:58 PM PDT 24 Jun 26 06:37:24 PM PDT 24 33332106 ps
T1088 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1396752120 Jun 26 06:36:55 PM PDT 24 Jun 26 06:37:23 PM PDT 24 1312063397 ps
T1089 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1873599140 Jun 26 06:36:57 PM PDT 24 Jun 26 06:37:26 PM PDT 24 100335394 ps
T1090 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.591302177 Jun 26 06:37:03 PM PDT 24 Jun 26 06:37:30 PM PDT 24 567913082 ps
T1091 /workspace/coverage/cover_reg_top/23.edn_intr_test.3583303051 Jun 26 06:37:51 PM PDT 24 Jun 26 06:37:58 PM PDT 24 12454665 ps
T1092 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.976184994 Jun 26 06:37:37 PM PDT 24 Jun 26 06:37:48 PM PDT 24 38196802 ps
T1093 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1919587584 Jun 26 06:37:08 PM PDT 24 Jun 26 06:37:32 PM PDT 24 106354978 ps
T1094 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1370434513 Jun 26 06:37:09 PM PDT 24 Jun 26 06:37:32 PM PDT 24 38238323 ps
T1095 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2191994686 Jun 26 06:36:45 PM PDT 24 Jun 26 06:37:12 PM PDT 24 18449098 ps
T1096 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3852174202 Jun 26 06:36:47 PM PDT 24 Jun 26 06:37:12 PM PDT 24 12332951 ps
T1097 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.71058544 Jun 26 06:37:35 PM PDT 24 Jun 26 06:37:47 PM PDT 24 74567020 ps
T1098 /workspace/coverage/cover_reg_top/44.edn_intr_test.3583512508 Jun 26 06:37:56 PM PDT 24 Jun 26 06:38:03 PM PDT 24 17354403 ps
T260 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1233794240 Jun 26 06:36:47 PM PDT 24 Jun 26 06:37:13 PM PDT 24 52368131 ps
T1099 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2242332243 Jun 26 06:37:04 PM PDT 24 Jun 26 06:37:30 PM PDT 24 48885833 ps
T1100 /workspace/coverage/cover_reg_top/18.edn_csr_rw.243115603 Jun 26 06:37:51 PM PDT 24 Jun 26 06:37:57 PM PDT 24 15784229 ps
T1101 /workspace/coverage/cover_reg_top/0.edn_intr_test.2078746667 Jun 26 06:36:34 PM PDT 24 Jun 26 06:36:50 PM PDT 24 40625396 ps
T262 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2736674705 Jun 26 06:36:50 PM PDT 24 Jun 26 06:37:16 PM PDT 24 52189585 ps
T1102 /workspace/coverage/cover_reg_top/17.edn_intr_test.2251268163 Jun 26 06:37:37 PM PDT 24 Jun 26 06:37:48 PM PDT 24 19963097 ps
T1103 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1170822039 Jun 26 06:37:36 PM PDT 24 Jun 26 06:37:47 PM PDT 24 40867215 ps
T1104 /workspace/coverage/cover_reg_top/21.edn_intr_test.4093023369 Jun 26 06:37:51 PM PDT 24 Jun 26 06:37:58 PM PDT 24 40533446 ps
T1105 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.569960336 Jun 26 06:37:41 PM PDT 24 Jun 26 06:37:50 PM PDT 24 17523074 ps
T1106 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3479624853 Jun 26 06:37:38 PM PDT 24 Jun 26 06:37:49 PM PDT 24 458960485 ps
T1107 /workspace/coverage/cover_reg_top/0.edn_tl_errors.4106892924 Jun 26 06:36:34 PM PDT 24 Jun 26 06:36:51 PM PDT 24 48671522 ps
T1108 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.32055750 Jun 26 06:37:23 PM PDT 24 Jun 26 06:37:39 PM PDT 24 98572674 ps
T1109 /workspace/coverage/cover_reg_top/6.edn_csr_rw.227584557 Jun 26 06:36:58 PM PDT 24 Jun 26 06:37:24 PM PDT 24 15018396 ps
T1110 /workspace/coverage/cover_reg_top/9.edn_intr_test.1714655891 Jun 26 06:37:10 PM PDT 24 Jun 26 06:37:33 PM PDT 24 14581519 ps
T1111 /workspace/coverage/cover_reg_top/3.edn_intr_test.1796637398 Jun 26 06:36:50 PM PDT 24 Jun 26 06:37:16 PM PDT 24 18138365 ps
T1112 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.652140681 Jun 26 06:37:24 PM PDT 24 Jun 26 06:37:40 PM PDT 24 466035359 ps
T1113 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2097736919 Jun 26 06:37:38 PM PDT 24 Jun 26 06:37:49 PM PDT 24 39954692 ps
T1114 /workspace/coverage/cover_reg_top/13.edn_tl_errors.4053506799 Jun 26 06:37:24 PM PDT 24 Jun 26 06:37:41 PM PDT 24 173257799 ps
T1115 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1510991471 Jun 26 06:36:46 PM PDT 24 Jun 26 06:37:12 PM PDT 24 74996176 ps
T1116 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2006822301 Jun 26 06:37:55 PM PDT 24 Jun 26 06:38:03 PM PDT 24 52776993 ps
T1117 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3806406411 Jun 26 06:37:50 PM PDT 24 Jun 26 06:37:56 PM PDT 24 71927686 ps
T1118 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1673965030 Jun 26 06:37:00 PM PDT 24 Jun 26 06:37:26 PM PDT 24 18522687 ps
T1119 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.819112161 Jun 26 06:36:47 PM PDT 24 Jun 26 06:37:14 PM PDT 24 34872133 ps
T1120 /workspace/coverage/cover_reg_top/12.edn_intr_test.3016469323 Jun 26 06:37:23 PM PDT 24 Jun 26 06:37:38 PM PDT 24 12300268 ps
T1121 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.4221185937 Jun 26 06:36:43 PM PDT 24 Jun 26 06:37:08 PM PDT 24 40466690 ps
T1122 /workspace/coverage/cover_reg_top/33.edn_intr_test.2291053698 Jun 26 06:37:52 PM PDT 24 Jun 26 06:37:59 PM PDT 24 13216287 ps
T1123 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2222919017 Jun 26 06:37:54 PM PDT 24 Jun 26 06:38:02 PM PDT 24 16407470 ps
T1124 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1662321719 Jun 26 06:36:59 PM PDT 24 Jun 26 06:37:24 PM PDT 24 18201729 ps
T1125 /workspace/coverage/cover_reg_top/1.edn_tl_errors.382227269 Jun 26 06:36:34 PM PDT 24 Jun 26 06:36:55 PM PDT 24 130236551 ps
T1126 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2460826798 Jun 26 06:37:11 PM PDT 24 Jun 26 06:37:36 PM PDT 24 42847762 ps
T1127 /workspace/coverage/cover_reg_top/43.edn_intr_test.3222724840 Jun 26 06:37:52 PM PDT 24 Jun 26 06:38:00 PM PDT 24 17165616 ps
T1128 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3823954317 Jun 26 06:37:11 PM PDT 24 Jun 26 06:37:34 PM PDT 24 52043028 ps
T1129 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2657210870 Jun 26 06:36:59 PM PDT 24 Jun 26 06:37:26 PM PDT 24 33868352 ps
T1130 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.235543625 Jun 26 06:36:44 PM PDT 24 Jun 26 06:37:15 PM PDT 24 985775342 ps

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.133196079
Short name T3
Test name
Test status
Simulation time 485125454830 ps
CPU time 1527.28 seconds
Started Jun 26 06:27:23 PM PDT 24
Finished Jun 26 06:52:55 PM PDT 24
Peak memory 225240 kb
Host smart-6bbc041d-c4b7-4b76-a410-bf17b33c2756
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133196079 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.133196079
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.edn_alert.3706052413
Short name T27
Test name
Test status
Simulation time 83918285 ps
CPU time 1.28 seconds
Started Jun 26 06:27:16 PM PDT 24
Finished Jun 26 06:27:22 PM PDT 24
Peak memory 219040 kb
Host smart-be6e363a-712b-4e00-a10a-591cd44026ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706052413 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3706052413
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.638502546
Short name T20
Test name
Test status
Simulation time 113583419 ps
CPU time 2.48 seconds
Started Jun 26 06:28:44 PM PDT 24
Finished Jun 26 06:28:50 PM PDT 24
Peak memory 219440 kb
Host smart-95500fa9-3867-4a35-a445-7cfeba0137ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638502546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.638502546
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_sec_cm.650197918
Short name T14
Test name
Test status
Simulation time 905929225 ps
CPU time 7.88 seconds
Started Jun 26 06:26:55 PM PDT 24
Finished Jun 26 06:27:05 PM PDT 24
Peak memory 237912 kb
Host smart-dc9e6bf3-6521-4c76-8064-4aa13b3e03be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650197918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.650197918
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/91.edn_alert.936749723
Short name T43
Test name
Test status
Simulation time 42522103 ps
CPU time 1.47 seconds
Started Jun 26 06:28:34 PM PDT 24
Finished Jun 26 06:28:40 PM PDT 24
Peak memory 221584 kb
Host smart-02a9a1b8-5474-420a-90f2-1b22fb0c47c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936749723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.936749723
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/34.edn_disable.4141494147
Short name T177
Test name
Test status
Simulation time 13982677 ps
CPU time 0.9 seconds
Started Jun 26 06:27:54 PM PDT 24
Finished Jun 26 06:27:56 PM PDT 24
Peak memory 216576 kb
Host smart-69486bc2-a3c0-4407-a48f-6b8e03b8bd35
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141494147 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.4141494147
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/33.edn_err.3475911970
Short name T54
Test name
Test status
Simulation time 34734431 ps
CPU time 1.44 seconds
Started Jun 26 06:27:46 PM PDT 24
Finished Jun 26 06:27:49 PM PDT 24
Peak memory 226076 kb
Host smart-a4fe7b9c-7971-497a-87d6-b2f7e2809b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475911970 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3475911970
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/152.edn_alert.868215072
Short name T28
Test name
Test status
Simulation time 35321615 ps
CPU time 1.36 seconds
Started Jun 26 06:29:02 PM PDT 24
Finished Jun 26 06:29:04 PM PDT 24
Peak memory 220360 kb
Host smart-a902df0d-d39e-45b8-8cad-bc7fe20eac70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868215072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.868215072
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2381039810
Short name T19
Test name
Test status
Simulation time 30009363 ps
CPU time 1.13 seconds
Started Jun 26 06:27:19 PM PDT 24
Finished Jun 26 06:27:25 PM PDT 24
Peak memory 217276 kb
Host smart-8d61a944-04f9-4eef-aa8b-0038c2a1370e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381039810 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2381039810
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/129.edn_alert.2462494916
Short name T159
Test name
Test status
Simulation time 46293085 ps
CPU time 1.09 seconds
Started Jun 26 06:28:42 PM PDT 24
Finished Jun 26 06:28:47 PM PDT 24
Peak memory 219140 kb
Host smart-696a5ddd-5b9c-4dfb-95bc-0ea9c16ad56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462494916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.2462494916
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/0.edn_regwen.758136412
Short name T25
Test name
Test status
Simulation time 16356774 ps
CPU time 1 seconds
Started Jun 26 06:26:48 PM PDT 24
Finished Jun 26 06:26:51 PM PDT 24
Peak memory 207456 kb
Host smart-4e8f73c6-acae-491e-8951-5a2e7bbe36f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758136412 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.758136412
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/255.edn_genbits.106726735
Short name T46
Test name
Test status
Simulation time 57263796 ps
CPU time 1.34 seconds
Started Jun 26 06:29:19 PM PDT 24
Finished Jun 26 06:29:24 PM PDT 24
Peak memory 218908 kb
Host smart-1ff554d2-ddd7-4fdd-af89-85e6218cd8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106726735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.106726735
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1580621225
Short name T4
Test name
Test status
Simulation time 45085028327 ps
CPU time 957.17 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:43:14 PM PDT 24
Peak memory 224160 kb
Host smart-e7764ce6-f3bc-4499-83cc-1bd539567753
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580621225 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1580621225
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.edn_disable.1823863098
Short name T157
Test name
Test status
Simulation time 19172771 ps
CPU time 0.86 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:23 PM PDT 24
Peak memory 216704 kb
Host smart-fdaa481b-69e5-43b6-8837-c19ca3badd61
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823863098 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1823863098
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/83.edn_alert.2065459807
Short name T77
Test name
Test status
Simulation time 40025059 ps
CPU time 1.16 seconds
Started Jun 26 06:28:30 PM PDT 24
Finished Jun 26 06:28:33 PM PDT 24
Peak memory 220660 kb
Host smart-a07838b9-8999-4939-8db2-259f86f9bde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065459807 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.2065459807
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1799766208
Short name T251
Test name
Test status
Simulation time 51681576 ps
CPU time 0.9 seconds
Started Jun 26 06:37:22 PM PDT 24
Finished Jun 26 06:37:38 PM PDT 24
Peak memory 206908 kb
Host smart-1ac6795b-6a27-4b4f-a641-8fae2221d71d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799766208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1799766208
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1138198416
Short name T76
Test name
Test status
Simulation time 65548077 ps
CPU time 1.3 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:23 PM PDT 24
Peak memory 217020 kb
Host smart-8922a9d6-3844-44ed-81e7-1b7b6aacbe5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138198416 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1138198416
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1433686463
Short name T275
Test name
Test status
Simulation time 45929633 ps
CPU time 1.54 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:36:53 PM PDT 24
Peak memory 207012 kb
Host smart-6b9b97b4-2d8e-403f-a873-e1f670aa5ac4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433686463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1433686463
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_err.3190003476
Short name T191
Test name
Test status
Simulation time 20659146 ps
CPU time 1.02 seconds
Started Jun 26 06:26:47 PM PDT 24
Finished Jun 26 06:26:50 PM PDT 24
Peak memory 218960 kb
Host smart-58558204-64e3-4890-88aa-8910d48e7ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190003476 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3190003476
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/17.edn_disable.409987192
Short name T196
Test name
Test status
Simulation time 13737040 ps
CPU time 0.97 seconds
Started Jun 26 06:27:37 PM PDT 24
Finished Jun 26 06:27:40 PM PDT 24
Peak memory 216664 kb
Host smart-1e3bd979-7c5c-4617-8a62-e1a93fa1a304
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409987192 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.409987192
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable.2652589503
Short name T201
Test name
Test status
Simulation time 31936514 ps
CPU time 0.88 seconds
Started Jun 26 06:27:37 PM PDT 24
Finished Jun 26 06:27:40 PM PDT 24
Peak memory 216624 kb
Host smart-a96bd154-e71e-4f7c-8ccf-d737c35d4b0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652589503 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2652589503
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/92.edn_alert.1051625953
Short name T81
Test name
Test status
Simulation time 23912403 ps
CPU time 1.19 seconds
Started Jun 26 06:28:24 PM PDT 24
Finished Jun 26 06:28:27 PM PDT 24
Peak memory 221044 kb
Host smart-ad7dd74c-500b-4d76-9924-ab1864ab86cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051625953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.1051625953
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert.1505041466
Short name T41
Test name
Test status
Simulation time 135995674 ps
CPU time 1.28 seconds
Started Jun 26 06:27:43 PM PDT 24
Finished Jun 26 06:27:46 PM PDT 24
Peak memory 219916 kb
Host smart-9e8f0986-f0b0-43a4-bf17-1a9ad71a93be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505041466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1505041466
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/198.edn_alert.2027890546
Short name T133
Test name
Test status
Simulation time 53953353 ps
CPU time 1.25 seconds
Started Jun 26 06:29:09 PM PDT 24
Finished Jun 26 06:29:12 PM PDT 24
Peak memory 219020 kb
Host smart-b62c2fd7-f4d5-4c06-b2f4-9f8acae087a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027890546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.2027890546
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/135.edn_alert.1040260617
Short name T430
Test name
Test status
Simulation time 214581889 ps
CPU time 1.12 seconds
Started Jun 26 06:28:42 PM PDT 24
Finished Jun 26 06:28:47 PM PDT 24
Peak memory 219928 kb
Host smart-99c5a359-f491-4131-bc7f-7ed0f067d1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040260617 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.1040260617
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.978724516
Short name T492
Test name
Test status
Simulation time 72973550 ps
CPU time 1.35 seconds
Started Jun 26 06:28:42 PM PDT 24
Finished Jun 26 06:28:47 PM PDT 24
Peak memory 219472 kb
Host smart-4a47d4c6-a428-4ff3-bb1a-194b454a41b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978724516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.978724516
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.480358880
Short name T188
Test name
Test status
Simulation time 23794432 ps
CPU time 1.16 seconds
Started Jun 26 06:28:38 PM PDT 24
Finished Jun 26 06:28:44 PM PDT 24
Peak memory 219232 kb
Host smart-09978bfb-2574-455a-92ef-32a53a7bbdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480358880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.480358880
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.4216479550
Short name T86
Test name
Test status
Simulation time 18924830 ps
CPU time 0.96 seconds
Started Jun 26 06:27:32 PM PDT 24
Finished Jun 26 06:27:36 PM PDT 24
Peak memory 218724 kb
Host smart-4be3dba3-ffe0-4f1f-a3ba-614b29080ad1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216479550 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.4216479550
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/103.edn_alert.1661856088
Short name T148
Test name
Test status
Simulation time 62835058 ps
CPU time 1.35 seconds
Started Jun 26 06:28:28 PM PDT 24
Finished Jun 26 06:28:31 PM PDT 24
Peak memory 220036 kb
Host smart-132b306c-0da4-452f-b9a3-f08af9bb9340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661856088 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1661856088
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/111.edn_alert.464268904
Short name T184
Test name
Test status
Simulation time 76638695 ps
CPU time 1.13 seconds
Started Jun 26 06:28:30 PM PDT 24
Finished Jun 26 06:28:34 PM PDT 24
Peak memory 221036 kb
Host smart-9a76706e-a5f0-49df-9042-2b874d002829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464268904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.464268904
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/120.edn_alert.4140850102
Short name T792
Test name
Test status
Simulation time 89495958 ps
CPU time 1.13 seconds
Started Jun 26 06:28:35 PM PDT 24
Finished Jun 26 06:28:41 PM PDT 24
Peak memory 221112 kb
Host smart-cc17bd27-9e6c-4d75-9d98-1c9a6ef271a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140850102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.4140850102
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/176.edn_alert.1165682270
Short name T180
Test name
Test status
Simulation time 340207283 ps
CPU time 1.36 seconds
Started Jun 26 06:29:12 PM PDT 24
Finished Jun 26 06:29:18 PM PDT 24
Peak memory 215924 kb
Host smart-d2f115c6-0f26-4ef5-ba7e-3c7676669239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165682270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.1165682270
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/48.edn_intr.4116159722
Short name T34
Test name
Test status
Simulation time 38357673 ps
CPU time 0.88 seconds
Started Jun 26 06:28:25 PM PDT 24
Finished Jun 26 06:28:28 PM PDT 24
Peak memory 215900 kb
Host smart-711a80b7-cbd6-44c9-b079-040e8a34603b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116159722 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.4116159722
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/10.edn_disable.1385748897
Short name T558
Test name
Test status
Simulation time 10566547 ps
CPU time 0.9 seconds
Started Jun 26 06:27:19 PM PDT 24
Finished Jun 26 06:27:25 PM PDT 24
Peak memory 215732 kb
Host smart-0865245e-cece-42ca-b31b-abea9e82de22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385748897 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1385748897
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/38.edn_intr.3505388601
Short name T58
Test name
Test status
Simulation time 22194520 ps
CPU time 1.28 seconds
Started Jun 26 06:29:03 PM PDT 24
Finished Jun 26 06:29:05 PM PDT 24
Peak memory 224316 kb
Host smart-9d9cfcd2-390a-42ee-bcfa-6c3a4a427080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505388601 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3505388601
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/14.edn_intr.1667948182
Short name T37
Test name
Test status
Simulation time 25342611 ps
CPU time 0.97 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:24 PM PDT 24
Peak memory 216240 kb
Host smart-e5b21b1a-c592-441f-872e-f186bbc898b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667948182 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1667948182
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/118.edn_alert.2619711457
Short name T172
Test name
Test status
Simulation time 28137233 ps
CPU time 1.11 seconds
Started Jun 26 06:28:46 PM PDT 24
Finished Jun 26 06:28:51 PM PDT 24
Peak memory 220132 kb
Host smart-2a39463d-2a59-4813-9342-4c56bd41c4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619711457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.2619711457
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3537694502
Short name T729
Test name
Test status
Simulation time 117079773 ps
CPU time 1.13 seconds
Started Jun 26 06:27:16 PM PDT 24
Finished Jun 26 06:27:22 PM PDT 24
Peak memory 218516 kb
Host smart-145b7fee-7c75-4092-ad12-5f3be584a9f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537694502 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3537694502
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/141.edn_alert.2888181612
Short name T128
Test name
Test status
Simulation time 25309077 ps
CPU time 1.22 seconds
Started Jun 26 06:28:51 PM PDT 24
Finished Jun 26 06:28:55 PM PDT 24
Peak memory 220092 kb
Host smart-f5b904e4-06bd-41dc-9e60-ec0b18c8beea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888181612 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2888181612
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/21.edn_disable.163268484
Short name T975
Test name
Test status
Simulation time 19742066 ps
CPU time 0.9 seconds
Started Jun 26 06:27:29 PM PDT 24
Finished Jun 26 06:27:34 PM PDT 24
Peak memory 216608 kb
Host smart-479cb75a-7dec-487a-b84c-8b3f350e74fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163268484 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.163268484
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.1653003947
Short name T193
Test name
Test status
Simulation time 19153890 ps
CPU time 1.2 seconds
Started Jun 26 06:27:33 PM PDT 24
Finished Jun 26 06:27:37 PM PDT 24
Peak memory 229972 kb
Host smart-8a722c08-5853-4c94-aa16-6b9360bedb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653003947 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1653003947
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/25.edn_disable.2460517441
Short name T202
Test name
Test status
Simulation time 13598216 ps
CPU time 0.94 seconds
Started Jun 26 06:27:33 PM PDT 24
Finished Jun 26 06:27:37 PM PDT 24
Peak memory 217060 kb
Host smart-bb55c3a5-89f7-45a4-a99a-4390cebb682b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460517441 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2460517441
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3086280182
Short name T144
Test name
Test status
Simulation time 102563637 ps
CPU time 1.19 seconds
Started Jun 26 06:27:36 PM PDT 24
Finished Jun 26 06:27:40 PM PDT 24
Peak memory 217164 kb
Host smart-11996a1a-2927-47f5-98a5-7405f0dee6ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086280182 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3086280182
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_disable.2402448113
Short name T217
Test name
Test status
Simulation time 27082474 ps
CPU time 0.84 seconds
Started Jun 26 06:27:39 PM PDT 24
Finished Jun 26 06:27:43 PM PDT 24
Peak memory 216164 kb
Host smart-b55bb0a4-8883-412f-8278-0af3974352b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402448113 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2402448113
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable.2255457411
Short name T186
Test name
Test status
Simulation time 13376182 ps
CPU time 0.93 seconds
Started Jun 26 06:27:44 PM PDT 24
Finished Jun 26 06:27:47 PM PDT 24
Peak memory 216748 kb
Host smart-9547cc8a-2b5f-4332-867e-6c95612d356d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255457411 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2255457411
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable.2232459433
Short name T216
Test name
Test status
Simulation time 16586446 ps
CPU time 0.91 seconds
Started Jun 26 06:27:15 PM PDT 24
Finished Jun 26 06:27:20 PM PDT 24
Peak memory 216792 kb
Host smart-59631da7-dbba-49b5-a502-1209c2cc6fcd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232459433 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2232459433
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/98.edn_err.2163042208
Short name T182
Test name
Test status
Simulation time 21612147 ps
CPU time 1.06 seconds
Started Jun 26 06:28:39 PM PDT 24
Finished Jun 26 06:28:44 PM PDT 24
Peak memory 224404 kb
Host smart-2b3f61d2-1518-48fe-8f06-ff17565bafab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163042208 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2163042208
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1817057596
Short name T228
Test name
Test status
Simulation time 138127882542 ps
CPU time 971.82 seconds
Started Jun 26 06:27:25 PM PDT 24
Finished Jun 26 06:43:40 PM PDT 24
Peak memory 223568 kb
Host smart-e3bd0135-e0fc-4643-b05c-ab3e7c52e038
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817057596 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1817057596
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/162.edn_genbits.1058363703
Short name T47
Test name
Test status
Simulation time 68503789 ps
CPU time 1.38 seconds
Started Jun 26 06:29:08 PM PDT 24
Finished Jun 26 06:29:12 PM PDT 24
Peak memory 218964 kb
Host smart-3c70a262-5884-4e9a-99be-26da58b3f240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058363703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1058363703
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_alert_test.1455457230
Short name T339
Test name
Test status
Simulation time 22106260 ps
CPU time 1.06 seconds
Started Jun 26 06:27:13 PM PDT 24
Finished Jun 26 06:27:16 PM PDT 24
Peak memory 215212 kb
Host smart-35917b65-25de-4126-8a8e-ea2203cf337a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455457230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1455457230
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/225.edn_genbits.2716992647
Short name T283
Test name
Test status
Simulation time 163820318 ps
CPU time 1.47 seconds
Started Jun 26 06:29:22 PM PDT 24
Finished Jun 26 06:29:27 PM PDT 24
Peak memory 218908 kb
Host smart-d187f0aa-b76d-4ab4-bcc0-367d577d62bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716992647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2716992647
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_genbits.2623937515
Short name T293
Test name
Test status
Simulation time 34547575 ps
CPU time 1.49 seconds
Started Jun 26 06:26:48 PM PDT 24
Finished Jun 26 06:26:52 PM PDT 24
Peak memory 217736 kb
Host smart-6ffd2241-ac75-428d-86f7-118e11e5120c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623937515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2623937515
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.748037757
Short name T306
Test name
Test status
Simulation time 52442285 ps
CPU time 1.07 seconds
Started Jun 26 06:29:14 PM PDT 24
Finished Jun 26 06:29:20 PM PDT 24
Peak memory 220316 kb
Host smart-87f3c5b4-77b0-405b-835c-4d057b68e6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748037757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.748037757
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_genbits.3979141928
Short name T426
Test name
Test status
Simulation time 82567107 ps
CPU time 1.49 seconds
Started Jun 26 06:28:31 PM PDT 24
Finished Jun 26 06:28:34 PM PDT 24
Peak memory 219120 kb
Host smart-438e25cc-98da-4e32-b01e-68a24fbac0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979141928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3979141928
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2959716401
Short name T684
Test name
Test status
Simulation time 80770543 ps
CPU time 1.11 seconds
Started Jun 26 06:28:21 PM PDT 24
Finished Jun 26 06:28:24 PM PDT 24
Peak memory 220484 kb
Host smart-830c6c05-0d6f-482f-944d-ca642b05d61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959716401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2959716401
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/9.edn_intr.2081802630
Short name T33
Test name
Test status
Simulation time 20526928 ps
CPU time 1.09 seconds
Started Jun 26 06:27:19 PM PDT 24
Finished Jun 26 06:27:25 PM PDT 24
Peak memory 216192 kb
Host smart-39715733-9cdd-4751-a5c0-549236b02ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081802630 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2081802630
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2447558387
Short name T268
Test name
Test status
Simulation time 12818547 ps
CPU time 0.86 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:36:52 PM PDT 24
Peak memory 206900 kb
Host smart-b8b32f05-df60-4c5e-b5c9-e797efb24eb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447558387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2447558387
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.972150524
Short name T287
Test name
Test status
Simulation time 547984371 ps
CPU time 8.73 seconds
Started Jun 26 06:37:37 PM PDT 24
Finished Jun 26 06:37:56 PM PDT 24
Peak memory 206780 kb
Host smart-1f38e5ef-592c-415a-a756-cf01c06f3b38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972150524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.972150524
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/default/102.edn_genbits.1091930539
Short name T333
Test name
Test status
Simulation time 49776783 ps
CPU time 1.22 seconds
Started Jun 26 06:28:36 PM PDT 24
Finished Jun 26 06:28:42 PM PDT 24
Peak memory 218876 kb
Host smart-5dd27dea-29b5-4c16-9d9b-de812c4e4c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091930539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1091930539
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.2783450308
Short name T301
Test name
Test status
Simulation time 83382965 ps
CPU time 1.48 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:38 PM PDT 24
Peak memory 219220 kb
Host smart-6bb5c8b1-f85f-45d5-9a79-bdfe0bab0c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783450308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2783450308
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.638925127
Short name T805
Test name
Test status
Simulation time 150167957 ps
CPU time 3.05 seconds
Started Jun 26 06:28:36 PM PDT 24
Finished Jun 26 06:28:44 PM PDT 24
Peak memory 219480 kb
Host smart-3e9fb6ff-f8a5-4150-9dee-33994e83218b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638925127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.638925127
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/130.edn_genbits.750338761
Short name T303
Test name
Test status
Simulation time 298865624 ps
CPU time 1.35 seconds
Started Jun 26 06:28:41 PM PDT 24
Finished Jun 26 06:28:46 PM PDT 24
Peak memory 220424 kb
Host smart-b74d9858-d0ef-4bc2-b237-1e1aeff50aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750338761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.750338761
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.494542450
Short name T297
Test name
Test status
Simulation time 57039636 ps
CPU time 1.17 seconds
Started Jun 26 06:28:49 PM PDT 24
Finished Jun 26 06:28:53 PM PDT 24
Peak memory 217600 kb
Host smart-4f47b563-0a22-4fa3-be3d-ef8277f44f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494542450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.494542450
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2682544991
Short name T82
Test name
Test status
Simulation time 34029894 ps
CPU time 1.59 seconds
Started Jun 26 06:29:20 PM PDT 24
Finished Jun 26 06:29:25 PM PDT 24
Peak memory 218892 kb
Host smart-ec9e3481-be3a-42fa-8543-6a1d088d297d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682544991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2682544991
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2291716767
Short name T312
Test name
Test status
Simulation time 81609933 ps
CPU time 2.54 seconds
Started Jun 26 06:29:20 PM PDT 24
Finished Jun 26 06:29:26 PM PDT 24
Peak memory 215608 kb
Host smart-d0c6cfda-335f-456b-b8c5-e64294a36640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291716767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2291716767
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_stress_all.2655668845
Short name T198
Test name
Test status
Simulation time 274385096 ps
CPU time 1.5 seconds
Started Jun 26 06:27:32 PM PDT 24
Finished Jun 26 06:27:37 PM PDT 24
Peak memory 217756 kb
Host smart-312642b1-c029-4fcb-a956-097430ff4576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655668845 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2655668845
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1791252379
Short name T272
Test name
Test status
Simulation time 90849568 ps
CPU time 1.21 seconds
Started Jun 26 06:27:13 PM PDT 24
Finished Jun 26 06:27:16 PM PDT 24
Peak memory 217324 kb
Host smart-6a37228c-2c30-47b8-997b-ed079365a648
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791252379 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1791252379
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_intr.2645024320
Short name T30
Test name
Test status
Simulation time 29591583 ps
CPU time 0.86 seconds
Started Jun 26 06:27:45 PM PDT 24
Finished Jun 26 06:27:48 PM PDT 24
Peak memory 215892 kb
Host smart-5d324934-897d-4220-8ef1-0b07c021c74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645024320 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2645024320
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/146.edn_genbits.3205394610
Short name T437
Test name
Test status
Simulation time 71910613 ps
CPU time 1.67 seconds
Started Jun 26 06:28:54 PM PDT 24
Finished Jun 26 06:28:58 PM PDT 24
Peak memory 220568 kb
Host smart-85c774e8-e352-47ad-99ad-e538d9ac7c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205394610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3205394610
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/100.edn_alert.3595924977
Short name T533
Test name
Test status
Simulation time 28562364 ps
CPU time 1.22 seconds
Started Jun 26 06:28:36 PM PDT 24
Finished Jun 26 06:28:42 PM PDT 24
Peak memory 215992 kb
Host smart-e000ca9b-cb16-4709-a5ce-e0076c72c48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595924977 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.3595924977
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/101.edn_alert.3206566490
Short name T105
Test name
Test status
Simulation time 32798370 ps
CPU time 1.22 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:39 PM PDT 24
Peak memory 218852 kb
Host smart-f456c0be-14a0-4d36-a915-b5a30e3852a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206566490 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.3206566490
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.201902768
Short name T258
Test name
Test status
Simulation time 34834164 ps
CPU time 1.54 seconds
Started Jun 26 06:36:40 PM PDT 24
Finished Jun 26 06:37:03 PM PDT 24
Peak memory 206996 kb
Host smart-56bfb433-b88c-4a71-acce-326950e9b5c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201902768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.201902768
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1340168287
Short name T1005
Test name
Test status
Simulation time 56327517 ps
CPU time 3.14 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:36:54 PM PDT 24
Peak memory 207036 kb
Host smart-3364e00c-86f4-464c-82fe-26cb800ce526
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340168287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1340168287
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4068757554
Short name T999
Test name
Test status
Simulation time 14944253 ps
CPU time 0.87 seconds
Started Jun 26 06:36:55 PM PDT 24
Finished Jun 26 06:37:22 PM PDT 24
Peak memory 206908 kb
Host smart-7fc0bf99-1342-4eaa-a407-1fd3ea9e0760
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068757554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.4068757554
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2623436754
Short name T1028
Test name
Test status
Simulation time 41008575 ps
CPU time 1.12 seconds
Started Jun 26 06:36:55 PM PDT 24
Finished Jun 26 06:37:21 PM PDT 24
Peak memory 215240 kb
Host smart-c189af7a-726f-41d2-b105-8e176bf08697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623436754 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2623436754
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2078746667
Short name T1101
Test name
Test status
Simulation time 40625396 ps
CPU time 0.83 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:36:50 PM PDT 24
Peak memory 207064 kb
Host smart-11f16943-350a-482c-9968-27a66e9cda6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078746667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2078746667
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2905236379
Short name T265
Test name
Test status
Simulation time 30404573 ps
CPU time 1.34 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:36:52 PM PDT 24
Peak memory 207044 kb
Host smart-8289815f-cedd-408e-bc85-57ce90892ace
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905236379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2905236379
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.4106892924
Short name T1107
Test name
Test status
Simulation time 48671522 ps
CPU time 1.67 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:36:51 PM PDT 24
Peak memory 215188 kb
Host smart-cd518fea-72b3-4c7c-8c21-9c89723ce2b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106892924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.4106892924
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.569960336
Short name T1105
Test name
Test status
Simulation time 17523074 ps
CPU time 1.05 seconds
Started Jun 26 06:37:41 PM PDT 24
Finished Jun 26 06:37:50 PM PDT 24
Peak memory 206912 kb
Host smart-4467511f-0a72-4a3e-bf15-6a0f03a604ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569960336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.569960336
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3348935338
Short name T255
Test name
Test status
Simulation time 34955016 ps
CPU time 1.99 seconds
Started Jun 26 06:36:54 PM PDT 24
Finished Jun 26 06:37:21 PM PDT 24
Peak memory 206932 kb
Host smart-eadf81d3-c82c-47b0-94b0-0d339ae38cd8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348935338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3348935338
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2787583027
Short name T256
Test name
Test status
Simulation time 19496208 ps
CPU time 0.98 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:36:52 PM PDT 24
Peak memory 206968 kb
Host smart-bc203eea-3f26-4ccc-9d1e-9a0b5fd2c9c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787583027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2787583027
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3745841848
Short name T1045
Test name
Test status
Simulation time 31915362 ps
CPU time 1.36 seconds
Started Jun 26 06:36:55 PM PDT 24
Finished Jun 26 06:37:21 PM PDT 24
Peak memory 217572 kb
Host smart-bc44029e-eaaa-4eb9-aba1-9888f8c69b7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745841848 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3745841848
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.785046222
Short name T253
Test name
Test status
Simulation time 13654669 ps
CPU time 0.88 seconds
Started Jun 26 06:36:32 PM PDT 24
Finished Jun 26 06:36:45 PM PDT 24
Peak memory 206972 kb
Host smart-a065c49e-8ee6-4a23-bcd8-49ae53edaf2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785046222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.785046222
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2522143274
Short name T1032
Test name
Test status
Simulation time 18512034 ps
CPU time 0.92 seconds
Started Jun 26 06:36:59 PM PDT 24
Finished Jun 26 06:37:24 PM PDT 24
Peak memory 206668 kb
Host smart-0fa1d355-d902-4600-abda-ce3f37621374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522143274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2522143274
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1662321719
Short name T1124
Test name
Test status
Simulation time 18201729 ps
CPU time 1.05 seconds
Started Jun 26 06:36:59 PM PDT 24
Finished Jun 26 06:37:24 PM PDT 24
Peak memory 206752 kb
Host smart-f6248571-4a25-4331-a935-26c673b564fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662321719 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1662321719
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.382227269
Short name T1125
Test name
Test status
Simulation time 130236551 ps
CPU time 4.1 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:36:55 PM PDT 24
Peak memory 215216 kb
Host smart-7c83a7fc-3fd0-4cad-a4ba-c352f4b7b7f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382227269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.382227269
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1170981012
Short name T1025
Test name
Test status
Simulation time 88861672 ps
CPU time 1.6 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:36:55 PM PDT 24
Peak memory 207044 kb
Host smart-1e938f2d-1b82-4654-84d3-fb1c0bc4607a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170981012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1170981012
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4167220356
Short name T1001
Test name
Test status
Simulation time 65036353 ps
CPU time 1.49 seconds
Started Jun 26 06:37:22 PM PDT 24
Finished Jun 26 06:37:38 PM PDT 24
Peak memory 215220 kb
Host smart-c9dc7be7-52cb-4484-9aaf-c03071844fe8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167220356 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.4167220356
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.118152085
Short name T1027
Test name
Test status
Simulation time 54656555 ps
CPU time 0.82 seconds
Started Jun 26 06:37:23 PM PDT 24
Finished Jun 26 06:37:38 PM PDT 24
Peak memory 206684 kb
Host smart-0420d0bf-71fc-4071-a9d3-e1a68f69b4a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118152085 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.118152085
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1292373999
Short name T263
Test name
Test status
Simulation time 35979675 ps
CPU time 1.31 seconds
Started Jun 26 06:37:22 PM PDT 24
Finished Jun 26 06:37:38 PM PDT 24
Peak memory 207044 kb
Host smart-894cd0d5-9284-4ec7-bb42-caf5d5f925fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292373999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1292373999
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3909188341
Short name T1009
Test name
Test status
Simulation time 376792432 ps
CPU time 3.12 seconds
Started Jun 26 06:37:22 PM PDT 24
Finished Jun 26 06:37:40 PM PDT 24
Peak memory 215248 kb
Host smart-43ed6b12-8970-41bc-895b-874a079865c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909188341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3909188341
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.652140681
Short name T1112
Test name
Test status
Simulation time 466035359 ps
CPU time 2.01 seconds
Started Jun 26 06:37:24 PM PDT 24
Finished Jun 26 06:37:40 PM PDT 24
Peak memory 206872 kb
Host smart-ad57f861-1855-4f87-8071-aef6ae64c93b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652140681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.652140681
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.4069052089
Short name T1030
Test name
Test status
Simulation time 24531474 ps
CPU time 1.25 seconds
Started Jun 26 06:37:23 PM PDT 24
Finished Jun 26 06:37:39 PM PDT 24
Peak memory 215168 kb
Host smart-5878f6de-351e-4940-bbc1-736ee3d16d55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069052089 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.4069052089
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3240014902
Short name T1003
Test name
Test status
Simulation time 100620529 ps
CPU time 0.87 seconds
Started Jun 26 06:37:21 PM PDT 24
Finished Jun 26 06:37:38 PM PDT 24
Peak memory 207164 kb
Host smart-febc0f52-fad0-4c06-b0a4-f58f7a32b50f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240014902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3240014902
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3925464206
Short name T1000
Test name
Test status
Simulation time 38339228 ps
CPU time 0.79 seconds
Started Jun 26 06:37:24 PM PDT 24
Finished Jun 26 06:37:39 PM PDT 24
Peak memory 206588 kb
Host smart-73d50dc6-6bff-4fab-a27f-0fa546bb8b60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925464206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3925464206
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3714199707
Short name T250
Test name
Test status
Simulation time 63966079 ps
CPU time 0.94 seconds
Started Jun 26 06:37:22 PM PDT 24
Finished Jun 26 06:37:38 PM PDT 24
Peak memory 206992 kb
Host smart-855c0f62-6e07-4679-b0fa-f8fae25cd831
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714199707 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3714199707
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1336457162
Short name T1074
Test name
Test status
Simulation time 291927139 ps
CPU time 3.23 seconds
Started Jun 26 06:37:23 PM PDT 24
Finished Jun 26 06:37:40 PM PDT 24
Peak memory 215364 kb
Host smart-7aba3604-25d4-476c-ab97-fb56c59bc4bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336457162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1336457162
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.506729779
Short name T1041
Test name
Test status
Simulation time 158484485 ps
CPU time 2.04 seconds
Started Jun 26 06:37:23 PM PDT 24
Finished Jun 26 06:37:40 PM PDT 24
Peak memory 207088 kb
Host smart-89170ab6-435a-4a54-bf8e-2ad7bf10d363
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506729779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.506729779
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.753426677
Short name T1052
Test name
Test status
Simulation time 98554112 ps
CPU time 1.22 seconds
Started Jun 26 06:37:23 PM PDT 24
Finished Jun 26 06:37:39 PM PDT 24
Peak memory 215284 kb
Host smart-2ef28b25-e091-4c46-821b-6842b23ef62b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753426677 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.753426677
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1958043544
Short name T1064
Test name
Test status
Simulation time 132528779 ps
CPU time 0.81 seconds
Started Jun 26 06:37:25 PM PDT 24
Finished Jun 26 06:37:39 PM PDT 24
Peak memory 206744 kb
Host smart-e0792acb-4e14-4c97-ae72-8e25ac0f3c6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958043544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1958043544
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3016469323
Short name T1120
Test name
Test status
Simulation time 12300268 ps
CPU time 0.82 seconds
Started Jun 26 06:37:23 PM PDT 24
Finished Jun 26 06:37:38 PM PDT 24
Peak memory 206928 kb
Host smart-a4e0cc36-39e9-4996-862a-fc0b3cbf2adb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016469323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3016469323
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.717935168
Short name T1047
Test name
Test status
Simulation time 171566729 ps
CPU time 1.34 seconds
Started Jun 26 06:37:22 PM PDT 24
Finished Jun 26 06:37:38 PM PDT 24
Peak memory 206968 kb
Host smart-743e7075-5649-4ac6-8c8d-4554dabe617a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717935168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.717935168
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3825514140
Short name T1076
Test name
Test status
Simulation time 94186929 ps
CPU time 2.87 seconds
Started Jun 26 06:37:21 PM PDT 24
Finished Jun 26 06:37:40 PM PDT 24
Peak memory 219436 kb
Host smart-48295ce5-4397-4f7b-8c88-d18d63eb4c35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825514140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3825514140
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3638166055
Short name T1046
Test name
Test status
Simulation time 436087931 ps
CPU time 2.08 seconds
Started Jun 26 06:37:22 PM PDT 24
Finished Jun 26 06:37:39 PM PDT 24
Peak memory 215216 kb
Host smart-282307a1-5563-4a26-99af-f86c94bb5ffa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638166055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3638166055
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.4056033771
Short name T1068
Test name
Test status
Simulation time 29178272 ps
CPU time 1.21 seconds
Started Jun 26 06:37:36 PM PDT 24
Finished Jun 26 06:37:48 PM PDT 24
Peak memory 217184 kb
Host smart-9410d5f7-3434-4c66-8639-7c046e5e6b68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056033771 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.4056033771
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3353357529
Short name T1069
Test name
Test status
Simulation time 21826022 ps
CPU time 0.85 seconds
Started Jun 26 06:37:36 PM PDT 24
Finished Jun 26 06:37:47 PM PDT 24
Peak memory 206920 kb
Host smart-261ac5cf-9b3e-46b8-a183-c28e7530c146
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353357529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3353357529
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3784017553
Short name T1049
Test name
Test status
Simulation time 13660492 ps
CPU time 0.86 seconds
Started Jun 26 06:37:36 PM PDT 24
Finished Jun 26 06:37:47 PM PDT 24
Peak memory 206888 kb
Host smart-b4193574-6c6c-4a18-81fb-3fdb78919ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784017553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3784017553
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.71058544
Short name T1097
Test name
Test status
Simulation time 74567020 ps
CPU time 1.49 seconds
Started Jun 26 06:37:35 PM PDT 24
Finished Jun 26 06:37:47 PM PDT 24
Peak memory 206980 kb
Host smart-3a454355-3fe3-42d3-a4ba-53fe0129e4c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71058544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_out
standing.71058544
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.4053506799
Short name T1114
Test name
Test status
Simulation time 173257799 ps
CPU time 3.11 seconds
Started Jun 26 06:37:24 PM PDT 24
Finished Jun 26 06:37:41 PM PDT 24
Peak memory 215088 kb
Host smart-f61d2fc3-5afd-4742-a5e1-1a9aafbb5098
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053506799 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.4053506799
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2608182563
Short name T277
Test name
Test status
Simulation time 183154303 ps
CPU time 1.62 seconds
Started Jun 26 06:37:37 PM PDT 24
Finished Jun 26 06:37:49 PM PDT 24
Peak memory 206976 kb
Host smart-0ed8f634-33c2-4c16-9221-02c46838b03a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608182563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2608182563
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2791989183
Short name T1031
Test name
Test status
Simulation time 216842894 ps
CPU time 1.03 seconds
Started Jun 26 06:37:36 PM PDT 24
Finished Jun 26 06:37:48 PM PDT 24
Peak memory 215192 kb
Host smart-4f58848e-c746-4599-af70-46618c2da54d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791989183 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2791989183
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2954731289
Short name T266
Test name
Test status
Simulation time 14593294 ps
CPU time 0.88 seconds
Started Jun 26 06:37:36 PM PDT 24
Finished Jun 26 06:37:47 PM PDT 24
Peak memory 206992 kb
Host smart-de2cc356-4ca7-4e8a-bc54-64f559e84f4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954731289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2954731289
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2799026152
Short name T1054
Test name
Test status
Simulation time 23530827 ps
CPU time 0.85 seconds
Started Jun 26 06:37:38 PM PDT 24
Finished Jun 26 06:37:49 PM PDT 24
Peak memory 206868 kb
Host smart-1da57eea-2e36-4d0a-a99b-1935802e6d84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799026152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2799026152
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1143209331
Short name T1067
Test name
Test status
Simulation time 77945220 ps
CPU time 0.91 seconds
Started Jun 26 06:37:36 PM PDT 24
Finished Jun 26 06:37:47 PM PDT 24
Peak memory 206912 kb
Host smart-ac385d1a-7770-4a47-a975-b855fc1c4d95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143209331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1143209331
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2097736919
Short name T1113
Test name
Test status
Simulation time 39954692 ps
CPU time 1.84 seconds
Started Jun 26 06:37:38 PM PDT 24
Finished Jun 26 06:37:49 PM PDT 24
Peak memory 215252 kb
Host smart-bf3b5c29-1d40-411b-a42f-fb94624cff23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097736919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2097736919
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3479624853
Short name T1106
Test name
Test status
Simulation time 458960485 ps
CPU time 1.64 seconds
Started Jun 26 06:37:38 PM PDT 24
Finished Jun 26 06:37:49 PM PDT 24
Peak memory 206908 kb
Host smart-4a06445d-0f07-4506-b261-c01c85d5e310
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479624853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3479624853
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1650935010
Short name T1071
Test name
Test status
Simulation time 42536730 ps
CPU time 1.49 seconds
Started Jun 26 06:37:35 PM PDT 24
Finished Jun 26 06:37:47 PM PDT 24
Peak memory 215232 kb
Host smart-add3561d-dc2e-4ffe-a0fe-e6b465fca9fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650935010 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1650935010
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2463421251
Short name T248
Test name
Test status
Simulation time 59906902 ps
CPU time 0.8 seconds
Started Jun 26 06:37:36 PM PDT 24
Finished Jun 26 06:37:47 PM PDT 24
Peak memory 206808 kb
Host smart-ecc410e4-3e97-4ead-92cb-d5c168a78a90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463421251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2463421251
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3017768194
Short name T1026
Test name
Test status
Simulation time 61864148 ps
CPU time 0.78 seconds
Started Jun 26 06:37:37 PM PDT 24
Finished Jun 26 06:37:48 PM PDT 24
Peak memory 206716 kb
Host smart-ad367647-7764-4d3d-8a34-c50d7cb97b7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017768194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3017768194
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.469256556
Short name T264
Test name
Test status
Simulation time 38380287 ps
CPU time 0.98 seconds
Started Jun 26 06:37:36 PM PDT 24
Finished Jun 26 06:37:48 PM PDT 24
Peak memory 207040 kb
Host smart-d3194440-e390-409b-b563-d8909e4f032d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469256556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.469256556
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3699370995
Short name T1061
Test name
Test status
Simulation time 82370811 ps
CPU time 2.85 seconds
Started Jun 26 06:37:37 PM PDT 24
Finished Jun 26 06:37:50 PM PDT 24
Peak memory 215068 kb
Host smart-916caf13-d9b2-4788-b921-9732d8c7a961
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699370995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3699370995
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4210990294
Short name T1081
Test name
Test status
Simulation time 55221104 ps
CPU time 1.72 seconds
Started Jun 26 06:37:37 PM PDT 24
Finished Jun 26 06:37:48 PM PDT 24
Peak memory 215168 kb
Host smart-562b195a-8472-4ced-9382-0634d05d2496
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210990294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.4210990294
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.976184994
Short name T1092
Test name
Test status
Simulation time 38196802 ps
CPU time 1.38 seconds
Started Jun 26 06:37:37 PM PDT 24
Finished Jun 26 06:37:48 PM PDT 24
Peak memory 215252 kb
Host smart-2004b432-e3f9-44af-bd93-b5d79ea49b16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976184994 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.976184994
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2140939179
Short name T1014
Test name
Test status
Simulation time 21216712 ps
CPU time 0.83 seconds
Started Jun 26 06:37:37 PM PDT 24
Finished Jun 26 06:37:48 PM PDT 24
Peak memory 206948 kb
Host smart-382e8a3b-0b26-4d1c-83ef-f17539ede796
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140939179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2140939179
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2810369648
Short name T1019
Test name
Test status
Simulation time 49948876 ps
CPU time 0.88 seconds
Started Jun 26 06:37:35 PM PDT 24
Finished Jun 26 06:37:47 PM PDT 24
Peak memory 206908 kb
Host smart-87116edf-7e6b-4d44-bc8d-69224c0dd1bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810369648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2810369648
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3729483436
Short name T1084
Test name
Test status
Simulation time 42161750 ps
CPU time 1.18 seconds
Started Jun 26 06:37:35 PM PDT 24
Finished Jun 26 06:37:46 PM PDT 24
Peak memory 206960 kb
Host smart-8f79e4e9-6008-4a95-96f8-f33ae98c3155
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729483436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3729483436
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.357058968
Short name T1039
Test name
Test status
Simulation time 389541678 ps
CPU time 2.33 seconds
Started Jun 26 06:37:36 PM PDT 24
Finished Jun 26 06:37:48 PM PDT 24
Peak memory 215256 kb
Host smart-11b1de7c-5217-47d6-a170-84bb2d4955b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357058968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.357058968
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1287596484
Short name T1078
Test name
Test status
Simulation time 52762147 ps
CPU time 1.65 seconds
Started Jun 26 06:37:37 PM PDT 24
Finished Jun 26 06:37:49 PM PDT 24
Peak memory 215132 kb
Host smart-fee4e001-d108-4eed-b6c8-151b694e5bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287596484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1287596484
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1481226977
Short name T1010
Test name
Test status
Simulation time 35806118 ps
CPU time 1.03 seconds
Started Jun 26 06:37:55 PM PDT 24
Finished Jun 26 06:38:02 PM PDT 24
Peak memory 215192 kb
Host smart-49ce27ad-8fdc-418e-83de-1eff398f47aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481226977 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1481226977
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1170822039
Short name T1103
Test name
Test status
Simulation time 40867215 ps
CPU time 0.85 seconds
Started Jun 26 06:37:36 PM PDT 24
Finished Jun 26 06:37:47 PM PDT 24
Peak memory 206984 kb
Host smart-9d23196e-254a-4035-99dd-3a7bb8619527
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170822039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1170822039
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2251268163
Short name T1102
Test name
Test status
Simulation time 19963097 ps
CPU time 0.87 seconds
Started Jun 26 06:37:37 PM PDT 24
Finished Jun 26 06:37:48 PM PDT 24
Peak memory 206920 kb
Host smart-f42d2ebc-c4af-4957-a118-1244ab3b2bf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251268163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2251268163
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.214407619
Short name T1035
Test name
Test status
Simulation time 29847630 ps
CPU time 1.07 seconds
Started Jun 26 06:37:37 PM PDT 24
Finished Jun 26 06:37:48 PM PDT 24
Peak memory 206956 kb
Host smart-3bb4e6b7-4e68-4b5a-aefa-070ea59eb1df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214407619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.214407619
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.4168313152
Short name T1006
Test name
Test status
Simulation time 131554966 ps
CPU time 2.46 seconds
Started Jun 26 06:37:37 PM PDT 24
Finished Jun 26 06:37:50 PM PDT 24
Peak memory 215216 kb
Host smart-79b3b5d0-a016-4da1-838e-6f64079444c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168313152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.4168313152
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3350597427
Short name T1037
Test name
Test status
Simulation time 44607842 ps
CPU time 1.26 seconds
Started Jun 26 06:37:57 PM PDT 24
Finished Jun 26 06:38:04 PM PDT 24
Peak memory 217544 kb
Host smart-37dae960-3b27-42cf-b746-6942df3ce4ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350597427 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3350597427
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.243115603
Short name T1100
Test name
Test status
Simulation time 15784229 ps
CPU time 0.97 seconds
Started Jun 26 06:37:51 PM PDT 24
Finished Jun 26 06:37:57 PM PDT 24
Peak memory 206940 kb
Host smart-1c84e373-d6d3-44c0-a4cc-7494dbbf041e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243115603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.243115603
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2620306802
Short name T1044
Test name
Test status
Simulation time 67433585 ps
CPU time 0.86 seconds
Started Jun 26 06:37:55 PM PDT 24
Finished Jun 26 06:38:02 PM PDT 24
Peak memory 206852 kb
Host smart-d4ca1232-f7d1-424b-8ec5-a411cb0c997f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620306802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2620306802
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3806406411
Short name T1117
Test name
Test status
Simulation time 71927686 ps
CPU time 0.98 seconds
Started Jun 26 06:37:50 PM PDT 24
Finished Jun 26 06:37:56 PM PDT 24
Peak memory 206940 kb
Host smart-18b8468f-579a-43da-8134-934eeba4e0de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806406411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3806406411
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2006822301
Short name T1116
Test name
Test status
Simulation time 52776993 ps
CPU time 1.89 seconds
Started Jun 26 06:37:55 PM PDT 24
Finished Jun 26 06:38:03 PM PDT 24
Peak memory 215164 kb
Host smart-baf2ca3c-9e88-44b9-8e2e-5a465c06430c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006822301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2006822301
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1073832727
Short name T288
Test name
Test status
Simulation time 154474276 ps
CPU time 3.18 seconds
Started Jun 26 06:37:50 PM PDT 24
Finished Jun 26 06:37:59 PM PDT 24
Peak memory 206940 kb
Host smart-9a51bdea-6ca4-408a-825c-65f140aeeb04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073832727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1073832727
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3495223039
Short name T1083
Test name
Test status
Simulation time 63764131 ps
CPU time 1 seconds
Started Jun 26 06:37:50 PM PDT 24
Finished Jun 26 06:37:57 PM PDT 24
Peak memory 207044 kb
Host smart-bfd6d396-f9ac-4313-ba60-8b254eee3f3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495223039 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3495223039
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2222919017
Short name T1123
Test name
Test status
Simulation time 16407470 ps
CPU time 0.95 seconds
Started Jun 26 06:37:54 PM PDT 24
Finished Jun 26 06:38:02 PM PDT 24
Peak memory 206924 kb
Host smart-feb943b3-7395-4311-8bbf-8c8ff6ad31af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222919017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2222919017
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2128968999
Short name T1062
Test name
Test status
Simulation time 24626642 ps
CPU time 0.85 seconds
Started Jun 26 06:37:56 PM PDT 24
Finished Jun 26 06:38:03 PM PDT 24
Peak memory 206920 kb
Host smart-acc5688f-0aa7-4d1b-9648-fd327a0df827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128968999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2128968999
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1815326675
Short name T249
Test name
Test status
Simulation time 15147529 ps
CPU time 1.01 seconds
Started Jun 26 06:37:50 PM PDT 24
Finished Jun 26 06:37:57 PM PDT 24
Peak memory 207280 kb
Host smart-6626f7ae-dc5e-42ef-af83-01eab565685d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815326675 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1815326675
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1087514934
Short name T1082
Test name
Test status
Simulation time 198937581 ps
CPU time 3.15 seconds
Started Jun 26 06:37:56 PM PDT 24
Finished Jun 26 06:38:05 PM PDT 24
Peak memory 219104 kb
Host smart-3a1c4877-0c16-4d86-bced-efff0f965c87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087514934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1087514934
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1873406627
Short name T1060
Test name
Test status
Simulation time 68549950 ps
CPU time 1.41 seconds
Started Jun 26 06:37:52 PM PDT 24
Finished Jun 26 06:37:59 PM PDT 24
Peak memory 207120 kb
Host smart-fda6c8dc-ead0-4ed2-b4ea-a4aa2ffdddce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873406627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1873406627
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4182646236
Short name T252
Test name
Test status
Simulation time 87131361 ps
CPU time 1.17 seconds
Started Jun 26 06:36:45 PM PDT 24
Finished Jun 26 06:37:10 PM PDT 24
Peak memory 206940 kb
Host smart-7aa068bc-b0d6-472c-80fa-fc7efcb328ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182646236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.4182646236
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.235543625
Short name T1130
Test name
Test status
Simulation time 985775342 ps
CPU time 6.19 seconds
Started Jun 26 06:36:44 PM PDT 24
Finished Jun 26 06:37:15 PM PDT 24
Peak memory 206844 kb
Host smart-e66e6aaf-1fc9-4406-b36c-793fafb61d7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235543625 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.235543625
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.4221185937
Short name T1121
Test name
Test status
Simulation time 40466690 ps
CPU time 0.8 seconds
Started Jun 26 06:36:43 PM PDT 24
Finished Jun 26 06:37:08 PM PDT 24
Peak memory 206748 kb
Host smart-3d35a78d-a389-452a-83c6-041fe33c0027
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221185937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.4221185937
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1312198924
Short name T1017
Test name
Test status
Simulation time 58734944 ps
CPU time 1.41 seconds
Started Jun 26 06:36:47 PM PDT 24
Finished Jun 26 06:37:15 PM PDT 24
Peak memory 215164 kb
Host smart-fa3a3913-3872-4406-8b87-665cff9239ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312198924 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1312198924
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2191994686
Short name T1095
Test name
Test status
Simulation time 18449098 ps
CPU time 0.95 seconds
Started Jun 26 06:36:45 PM PDT 24
Finished Jun 26 06:37:12 PM PDT 24
Peak memory 206940 kb
Host smart-884234f6-0f0c-4be0-81c7-b6999d21d27c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191994686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2191994686
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3121638096
Short name T1024
Test name
Test status
Simulation time 95500227 ps
CPU time 0.9 seconds
Started Jun 26 06:36:42 PM PDT 24
Finished Jun 26 06:37:07 PM PDT 24
Peak memory 206904 kb
Host smart-9d012554-fc6b-4bfa-9515-8835afe35aa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121638096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3121638096
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1510991471
Short name T1115
Test name
Test status
Simulation time 74996176 ps
CPU time 1.02 seconds
Started Jun 26 06:36:46 PM PDT 24
Finished Jun 26 06:37:12 PM PDT 24
Peak memory 206996 kb
Host smart-77629e33-0495-4d73-ae57-73e535998f85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510991471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1510991471
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.95037025
Short name T1072
Test name
Test status
Simulation time 241801192 ps
CPU time 2.15 seconds
Started Jun 26 06:36:47 PM PDT 24
Finished Jun 26 06:37:14 PM PDT 24
Peak memory 218948 kb
Host smart-0e9ed9ed-7692-42f8-8a85-4643dcab64b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95037025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.95037025
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2877334727
Short name T286
Test name
Test status
Simulation time 140309148 ps
CPU time 1.7 seconds
Started Jun 26 06:36:45 PM PDT 24
Finished Jun 26 06:37:13 PM PDT 24
Peak memory 206948 kb
Host smart-8e016139-4ca7-431f-b739-bc73c54594ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877334727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2877334727
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.371789427
Short name T1066
Test name
Test status
Simulation time 12321502 ps
CPU time 0.86 seconds
Started Jun 26 06:37:56 PM PDT 24
Finished Jun 26 06:38:03 PM PDT 24
Peak memory 206912 kb
Host smart-01de46a7-2be5-4f7d-a28b-f97e7b57d383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371789427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.371789427
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.4093023369
Short name T1104
Test name
Test status
Simulation time 40533446 ps
CPU time 0.83 seconds
Started Jun 26 06:37:51 PM PDT 24
Finished Jun 26 06:37:58 PM PDT 24
Peak memory 206716 kb
Host smart-9d239a52-803b-4fbd-baff-8c47787f1bfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093023369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.4093023369
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1615796568
Short name T1022
Test name
Test status
Simulation time 25098494 ps
CPU time 0.88 seconds
Started Jun 26 06:37:56 PM PDT 24
Finished Jun 26 06:38:03 PM PDT 24
Peak memory 206916 kb
Host smart-6ad7ba46-b2c6-4915-a15b-8218d166b6ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615796568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1615796568
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3583303051
Short name T1091
Test name
Test status
Simulation time 12454665 ps
CPU time 0.84 seconds
Started Jun 26 06:37:51 PM PDT 24
Finished Jun 26 06:37:58 PM PDT 24
Peak memory 206856 kb
Host smart-1b559abe-fb3f-4187-86de-ce22e788edff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583303051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3583303051
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3950004269
Short name T1063
Test name
Test status
Simulation time 31328660 ps
CPU time 0.76 seconds
Started Jun 26 06:37:50 PM PDT 24
Finished Jun 26 06:37:57 PM PDT 24
Peak memory 206748 kb
Host smart-90b54b8c-ac28-45f8-b99a-5e020d81ebd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950004269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3950004269
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3488704631
Short name T1013
Test name
Test status
Simulation time 35848385 ps
CPU time 0.78 seconds
Started Jun 26 06:37:56 PM PDT 24
Finished Jun 26 06:38:03 PM PDT 24
Peak memory 206668 kb
Host smart-8d93e044-a33b-44d1-9093-1952fed8ef0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488704631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3488704631
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2135460715
Short name T1053
Test name
Test status
Simulation time 14604708 ps
CPU time 0.91 seconds
Started Jun 26 06:37:57 PM PDT 24
Finished Jun 26 06:38:04 PM PDT 24
Peak memory 206892 kb
Host smart-77fdb6e5-a5c7-42f4-92a2-fbddd7da5bbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135460715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2135460715
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3517688284
Short name T1073
Test name
Test status
Simulation time 33012772 ps
CPU time 0.83 seconds
Started Jun 26 06:37:56 PM PDT 24
Finished Jun 26 06:38:03 PM PDT 24
Peak memory 206668 kb
Host smart-44f6a418-aa90-4917-83b5-f0fd20e889d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517688284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3517688284
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2703663418
Short name T1080
Test name
Test status
Simulation time 50402913 ps
CPU time 0.81 seconds
Started Jun 26 06:37:53 PM PDT 24
Finished Jun 26 06:38:00 PM PDT 24
Peak memory 206780 kb
Host smart-a2fef5c5-0259-4a36-90ba-a841156f53d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703663418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2703663418
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1872849787
Short name T1070
Test name
Test status
Simulation time 12413441 ps
CPU time 0.81 seconds
Started Jun 26 06:37:53 PM PDT 24
Finished Jun 26 06:38:00 PM PDT 24
Peak memory 206876 kb
Host smart-e0971cfd-b498-47b4-8d59-683d12189093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872849787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1872849787
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1146948555
Short name T1058
Test name
Test status
Simulation time 142042061 ps
CPU time 1.24 seconds
Started Jun 26 06:36:50 PM PDT 24
Finished Jun 26 06:37:16 PM PDT 24
Peak memory 206896 kb
Host smart-86f9dfab-7a00-4e32-a9d5-e3c2acf8c9df
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146948555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1146948555
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1115588110
Short name T254
Test name
Test status
Simulation time 71772886 ps
CPU time 3.26 seconds
Started Jun 26 06:36:51 PM PDT 24
Finished Jun 26 06:37:18 PM PDT 24
Peak memory 207040 kb
Host smart-98ba5f3e-8034-43e0-bd1b-5becc88db7df
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115588110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1115588110
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2736674705
Short name T262
Test name
Test status
Simulation time 52189585 ps
CPU time 0.91 seconds
Started Jun 26 06:36:50 PM PDT 24
Finished Jun 26 06:37:16 PM PDT 24
Peak memory 206896 kb
Host smart-b0e0caa5-d426-41a5-a8ed-b2efc0885906
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736674705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2736674705
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.339026509
Short name T1065
Test name
Test status
Simulation time 60662748 ps
CPU time 1.56 seconds
Started Jun 26 06:36:51 PM PDT 24
Finished Jun 26 06:37:19 PM PDT 24
Peak memory 215164 kb
Host smart-495c2cfa-53f8-4b96-9c61-d6ee3978b13c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339026509 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.339026509
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.4009811553
Short name T257
Test name
Test status
Simulation time 48263578 ps
CPU time 0.96 seconds
Started Jun 26 06:36:45 PM PDT 24
Finished Jun 26 06:37:10 PM PDT 24
Peak memory 206896 kb
Host smart-c6877e3f-dfcf-4d7e-a956-7b793b7246bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009811553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.4009811553
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1796637398
Short name T1111
Test name
Test status
Simulation time 18138365 ps
CPU time 0.95 seconds
Started Jun 26 06:36:50 PM PDT 24
Finished Jun 26 06:37:16 PM PDT 24
Peak memory 206844 kb
Host smart-4b1871da-882c-44c5-ae8e-409148fa3b17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796637398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1796637398
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.819112161
Short name T1119
Test name
Test status
Simulation time 34872133 ps
CPU time 1.15 seconds
Started Jun 26 06:36:47 PM PDT 24
Finished Jun 26 06:37:14 PM PDT 24
Peak memory 206908 kb
Host smart-25c1626a-b586-4bb5-9779-8006a1e4141e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819112161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.819112161
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1448938251
Short name T1059
Test name
Test status
Simulation time 58844538 ps
CPU time 2.36 seconds
Started Jun 26 06:36:46 PM PDT 24
Finished Jun 26 06:37:14 PM PDT 24
Peak memory 215212 kb
Host smart-1c70d4fe-c792-445f-bce9-329fb1c3e826
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448938251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1448938251
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2579366129
Short name T284
Test name
Test status
Simulation time 152252168 ps
CPU time 2.28 seconds
Started Jun 26 06:36:51 PM PDT 24
Finished Jun 26 06:37:19 PM PDT 24
Peak memory 206904 kb
Host smart-c78f534f-5d31-4b73-981e-be786141b4ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579366129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2579366129
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2551771971
Short name T1057
Test name
Test status
Simulation time 46668947 ps
CPU time 0.8 seconds
Started Jun 26 06:37:53 PM PDT 24
Finished Jun 26 06:38:00 PM PDT 24
Peak memory 206656 kb
Host smart-9ba6f898-a316-4569-813c-ea90e9f73d26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551771971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2551771971
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.104218446
Short name T1051
Test name
Test status
Simulation time 30926282 ps
CPU time 0.79 seconds
Started Jun 26 06:37:50 PM PDT 24
Finished Jun 26 06:37:56 PM PDT 24
Peak memory 206752 kb
Host smart-5696e07b-3db0-4bf6-b75c-8c6a52b79646
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104218446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.104218446
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1638505866
Short name T1015
Test name
Test status
Simulation time 20942525 ps
CPU time 0.87 seconds
Started Jun 26 06:37:49 PM PDT 24
Finished Jun 26 06:37:55 PM PDT 24
Peak memory 206788 kb
Host smart-230d70f7-8fe1-4694-99a8-bd34cd97c352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638505866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1638505866
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2291053698
Short name T1122
Test name
Test status
Simulation time 13216287 ps
CPU time 0.88 seconds
Started Jun 26 06:37:52 PM PDT 24
Finished Jun 26 06:37:59 PM PDT 24
Peak memory 206836 kb
Host smart-e3ae92fc-876d-407c-867b-ba6fa1913d19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291053698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2291053698
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.308828328
Short name T1043
Test name
Test status
Simulation time 34304852 ps
CPU time 0.83 seconds
Started Jun 26 06:37:57 PM PDT 24
Finished Jun 26 06:38:03 PM PDT 24
Peak memory 206716 kb
Host smart-c404a7a8-9664-41e5-9d2c-3a29c8886719
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308828328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.308828328
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2216581710
Short name T1050
Test name
Test status
Simulation time 10442444 ps
CPU time 0.8 seconds
Started Jun 26 06:38:57 PM PDT 24
Finished Jun 26 06:39:05 PM PDT 24
Peak memory 206856 kb
Host smart-bd1693d4-617b-4b5c-b335-ae7bdcf3f634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216581710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2216581710
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2571501790
Short name T1033
Test name
Test status
Simulation time 40474619 ps
CPU time 0.82 seconds
Started Jun 26 06:37:53 PM PDT 24
Finished Jun 26 06:38:00 PM PDT 24
Peak memory 206964 kb
Host smart-1a29bb48-91c2-44d3-8cb1-ad7767dd1e62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571501790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2571501790
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.248879578
Short name T1016
Test name
Test status
Simulation time 48793016 ps
CPU time 0.85 seconds
Started Jun 26 06:37:52 PM PDT 24
Finished Jun 26 06:38:00 PM PDT 24
Peak memory 206832 kb
Host smart-de73fc6a-0cd2-420d-933d-430b0f42ee1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248879578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.248879578
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2140056002
Short name T1038
Test name
Test status
Simulation time 88159188 ps
CPU time 0.8 seconds
Started Jun 26 06:37:55 PM PDT 24
Finished Jun 26 06:38:02 PM PDT 24
Peak memory 206732 kb
Host smart-b5864b29-064b-4ecd-9c53-192844b410e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140056002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2140056002
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.320297963
Short name T1012
Test name
Test status
Simulation time 14470849 ps
CPU time 0.89 seconds
Started Jun 26 06:37:52 PM PDT 24
Finished Jun 26 06:38:00 PM PDT 24
Peak memory 206920 kb
Host smart-e48005fa-a4a3-4364-bdd0-5fdd07796eaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320297963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.320297963
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1233794240
Short name T260
Test name
Test status
Simulation time 52368131 ps
CPU time 1.5 seconds
Started Jun 26 06:36:47 PM PDT 24
Finished Jun 26 06:37:13 PM PDT 24
Peak memory 206872 kb
Host smart-fed7b3e2-0f4c-4213-9563-a8e9a7804b38
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233794240 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1233794240
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.230139666
Short name T261
Test name
Test status
Simulation time 68316257 ps
CPU time 1.93 seconds
Started Jun 26 06:37:00 PM PDT 24
Finished Jun 26 06:37:27 PM PDT 24
Peak memory 207120 kb
Host smart-459a2f6c-5c79-4b2d-983d-298498313288
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230139666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.230139666
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2428748806
Short name T1008
Test name
Test status
Simulation time 33099233 ps
CPU time 0.98 seconds
Started Jun 26 06:36:47 PM PDT 24
Finished Jun 26 06:37:14 PM PDT 24
Peak memory 206872 kb
Host smart-b2b69c6c-6a98-4efb-9c59-8ee4ad18bf43
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428748806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2428748806
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3474237072
Short name T1021
Test name
Test status
Simulation time 26810105 ps
CPU time 1.32 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:36:50 PM PDT 24
Peak memory 215348 kb
Host smart-00ed2807-d3d4-4c5b-ba7d-a88dd47fa9aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474237072 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3474237072
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3852174202
Short name T1096
Test name
Test status
Simulation time 12332951 ps
CPU time 0.81 seconds
Started Jun 26 06:36:47 PM PDT 24
Finished Jun 26 06:37:12 PM PDT 24
Peak memory 206708 kb
Host smart-fc78d6d5-aaed-44d7-aeb5-6bb7c86ccd85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852174202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3852174202
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1986707275
Short name T1040
Test name
Test status
Simulation time 14835596 ps
CPU time 0.84 seconds
Started Jun 26 06:36:47 PM PDT 24
Finished Jun 26 06:37:14 PM PDT 24
Peak memory 206820 kb
Host smart-fcc286b3-f87c-4f65-8241-2e65caf692c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986707275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1986707275
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2982671383
Short name T1079
Test name
Test status
Simulation time 128845009 ps
CPU time 1.43 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:36:53 PM PDT 24
Peak memory 206956 kb
Host smart-e323f8c6-e88c-43aa-af8f-1db8dc629ab5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982671383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2982671383
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2238233118
Short name T1018
Test name
Test status
Simulation time 81556166 ps
CPU time 3.02 seconds
Started Jun 26 06:36:58 PM PDT 24
Finished Jun 26 06:37:26 PM PDT 24
Peak memory 219028 kb
Host smart-1f3e8de8-d933-44ac-892f-8ec2e2cdd066
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238233118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2238233118
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1396752120
Short name T1088
Test name
Test status
Simulation time 1312063397 ps
CPU time 2.02 seconds
Started Jun 26 06:36:55 PM PDT 24
Finished Jun 26 06:37:23 PM PDT 24
Peak memory 206916 kb
Host smart-4e2782c3-28a8-4c96-bfa7-f7273067ce4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396752120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1396752120
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1263606655
Short name T1086
Test name
Test status
Simulation time 35499372 ps
CPU time 0.91 seconds
Started Jun 26 06:37:52 PM PDT 24
Finished Jun 26 06:37:58 PM PDT 24
Peak memory 206924 kb
Host smart-e857f105-e887-48e4-9985-9aa016b7653f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263606655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1263606655
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.962291556
Short name T996
Test name
Test status
Simulation time 17634437 ps
CPU time 0.93 seconds
Started Jun 26 06:37:56 PM PDT 24
Finished Jun 26 06:38:03 PM PDT 24
Peak memory 206840 kb
Host smart-01bccd4d-9410-4bed-9761-d9718098950b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962291556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.962291556
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.616504704
Short name T1055
Test name
Test status
Simulation time 14375926 ps
CPU time 0.92 seconds
Started Jun 26 06:37:51 PM PDT 24
Finished Jun 26 06:37:57 PM PDT 24
Peak memory 206920 kb
Host smart-439f4638-f690-471c-aac7-1a8cabbdcf09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616504704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.616504704
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3222724840
Short name T1127
Test name
Test status
Simulation time 17165616 ps
CPU time 0.92 seconds
Started Jun 26 06:37:52 PM PDT 24
Finished Jun 26 06:38:00 PM PDT 24
Peak memory 206908 kb
Host smart-1583948a-0ce8-4d88-ad24-720477d7ea53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222724840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3222724840
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3583512508
Short name T1098
Test name
Test status
Simulation time 17354403 ps
CPU time 0.93 seconds
Started Jun 26 06:37:56 PM PDT 24
Finished Jun 26 06:38:03 PM PDT 24
Peak memory 206832 kb
Host smart-195b3e93-3178-49c4-bac6-7e05fcd0756a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583512508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3583512508
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.488235981
Short name T1002
Test name
Test status
Simulation time 33746342 ps
CPU time 0.78 seconds
Started Jun 26 06:37:52 PM PDT 24
Finished Jun 26 06:37:58 PM PDT 24
Peak memory 206700 kb
Host smart-1d80d787-c2e7-4585-b171-d21ac605d7de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488235981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.488235981
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3443700331
Short name T1023
Test name
Test status
Simulation time 16563556 ps
CPU time 0.82 seconds
Started Jun 26 06:37:50 PM PDT 24
Finished Jun 26 06:37:56 PM PDT 24
Peak memory 206908 kb
Host smart-9d84e265-a76e-4a54-9cc8-997b65c40de1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443700331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3443700331
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3699607424
Short name T997
Test name
Test status
Simulation time 19118468 ps
CPU time 0.82 seconds
Started Jun 26 06:37:57 PM PDT 24
Finished Jun 26 06:38:03 PM PDT 24
Peak memory 206892 kb
Host smart-30326cd0-9711-4253-8d65-587299cc5506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699607424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3699607424
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1737040274
Short name T998
Test name
Test status
Simulation time 27753629 ps
CPU time 0.9 seconds
Started Jun 26 06:37:57 PM PDT 24
Finished Jun 26 06:38:04 PM PDT 24
Peak memory 206816 kb
Host smart-397d562f-708d-44b5-af62-8c2592a73727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737040274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1737040274
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1000777867
Short name T1077
Test name
Test status
Simulation time 18734051 ps
CPU time 0.83 seconds
Started Jun 26 06:38:12 PM PDT 24
Finished Jun 26 06:38:17 PM PDT 24
Peak memory 206708 kb
Host smart-f2d1e2ad-3baa-40a2-8d2a-ce9af36bded2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000777867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1000777867
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1673965030
Short name T1118
Test name
Test status
Simulation time 18522687 ps
CPU time 1.21 seconds
Started Jun 26 06:37:00 PM PDT 24
Finished Jun 26 06:37:26 PM PDT 24
Peak memory 215320 kb
Host smart-0eee569b-45bd-43ee-a3d5-93616e24b631
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673965030 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1673965030
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.990186885
Short name T1087
Test name
Test status
Simulation time 33332106 ps
CPU time 0.82 seconds
Started Jun 26 06:36:58 PM PDT 24
Finished Jun 26 06:37:24 PM PDT 24
Peak memory 206624 kb
Host smart-c3bb9038-ec17-4fde-8a60-d16c39d4c6d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990186885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.990186885
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.606254598
Short name T1011
Test name
Test status
Simulation time 17515890 ps
CPU time 0.96 seconds
Started Jun 26 06:36:58 PM PDT 24
Finished Jun 26 06:37:24 PM PDT 24
Peak memory 206924 kb
Host smart-61141536-d5d4-4270-86ef-8bb38308f6b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606254598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.606254598
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.446446206
Short name T269
Test name
Test status
Simulation time 21236067 ps
CPU time 1.12 seconds
Started Jun 26 06:36:48 PM PDT 24
Finished Jun 26 06:37:15 PM PDT 24
Peak memory 206936 kb
Host smart-6d9c476d-ed7c-4f01-8faf-1964be303a83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446446206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.446446206
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1837188323
Short name T1020
Test name
Test status
Simulation time 102084838 ps
CPU time 3.71 seconds
Started Jun 26 06:36:58 PM PDT 24
Finished Jun 26 06:37:27 PM PDT 24
Peak memory 215236 kb
Host smart-7f789f2f-878c-472e-ae72-776fbe35895c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837188323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1837188323
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3382429611
Short name T1056
Test name
Test status
Simulation time 631580390 ps
CPU time 9.6 seconds
Started Jun 26 06:36:59 PM PDT 24
Finished Jun 26 06:37:33 PM PDT 24
Peak memory 215000 kb
Host smart-6df7acea-3a22-4182-906b-62ab66e5c9b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382429611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3382429611
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2140079561
Short name T1036
Test name
Test status
Simulation time 31111536 ps
CPU time 1.27 seconds
Started Jun 26 06:36:57 PM PDT 24
Finished Jun 26 06:37:24 PM PDT 24
Peak memory 218180 kb
Host smart-3a57cdf1-834c-4e34-8058-8dea1536beea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140079561 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2140079561
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.227584557
Short name T1109
Test name
Test status
Simulation time 15018396 ps
CPU time 0.9 seconds
Started Jun 26 06:36:58 PM PDT 24
Finished Jun 26 06:37:24 PM PDT 24
Peak memory 206952 kb
Host smart-fed2c088-e03e-4aa2-af16-457c69777019
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227584557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.227584557
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.20730408
Short name T1004
Test name
Test status
Simulation time 40827375 ps
CPU time 0.84 seconds
Started Jun 26 06:36:57 PM PDT 24
Finished Jun 26 06:37:22 PM PDT 24
Peak memory 206908 kb
Host smart-95e9a01f-5091-4b13-a41b-e254e742d74a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20730408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.20730408
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2657210870
Short name T1129
Test name
Test status
Simulation time 33868352 ps
CPU time 1.42 seconds
Started Jun 26 06:36:59 PM PDT 24
Finished Jun 26 06:37:26 PM PDT 24
Peak memory 207064 kb
Host smart-ed560fa3-896c-45a8-a71c-8cc92c4b4922
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657210870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2657210870
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1873599140
Short name T1089
Test name
Test status
Simulation time 100335394 ps
CPU time 3.2 seconds
Started Jun 26 06:36:57 PM PDT 24
Finished Jun 26 06:37:26 PM PDT 24
Peak memory 215236 kb
Host smart-257e2bcb-78a6-4e6a-8b25-acee76810646
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873599140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1873599140
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2800701080
Short name T285
Test name
Test status
Simulation time 115096268 ps
CPU time 2.73 seconds
Started Jun 26 06:36:57 PM PDT 24
Finished Jun 26 06:37:26 PM PDT 24
Peak memory 206912 kb
Host smart-9e057f16-7e61-430e-ae0f-9145e6b195e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800701080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2800701080
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1370434513
Short name T1094
Test name
Test status
Simulation time 38238323 ps
CPU time 1.13 seconds
Started Jun 26 06:37:09 PM PDT 24
Finished Jun 26 06:37:32 PM PDT 24
Peak memory 215336 kb
Host smart-f1317721-b9a0-4f6b-b188-fefed24947ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370434513 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1370434513
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2981144585
Short name T1085
Test name
Test status
Simulation time 12352325 ps
CPU time 0.86 seconds
Started Jun 26 06:37:00 PM PDT 24
Finished Jun 26 06:37:26 PM PDT 24
Peak memory 206976 kb
Host smart-659bdedc-a6e9-4084-962b-88386c3eb2f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981144585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2981144585
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.556396976
Short name T1042
Test name
Test status
Simulation time 92886801 ps
CPU time 0.92 seconds
Started Jun 26 06:36:57 PM PDT 24
Finished Jun 26 06:37:24 PM PDT 24
Peak memory 206848 kb
Host smart-6c4b9b03-6d4b-409e-a1ac-ed92b87605ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556396976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.556396976
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.604137763
Short name T267
Test name
Test status
Simulation time 127680329 ps
CPU time 1.08 seconds
Started Jun 26 06:36:57 PM PDT 24
Finished Jun 26 06:37:22 PM PDT 24
Peak memory 206984 kb
Host smart-e603d26e-8206-4f6c-90ab-2746b48c3c10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604137763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.604137763
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2242332243
Short name T1099
Test name
Test status
Simulation time 48885833 ps
CPU time 1.91 seconds
Started Jun 26 06:37:04 PM PDT 24
Finished Jun 26 06:37:30 PM PDT 24
Peak memory 215104 kb
Host smart-6934c345-b43f-4d5c-bd65-415d7c0d8f23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242332243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2242332243
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.591302177
Short name T1090
Test name
Test status
Simulation time 567913082 ps
CPU time 2.11 seconds
Started Jun 26 06:37:03 PM PDT 24
Finished Jun 26 06:37:30 PM PDT 24
Peak memory 207028 kb
Host smart-ff7c97e1-2a2d-4d96-82ba-6cc36278c1b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591302177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.591302177
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1612678327
Short name T1034
Test name
Test status
Simulation time 91701369 ps
CPU time 1.15 seconds
Started Jun 26 06:37:11 PM PDT 24
Finished Jun 26 06:37:34 PM PDT 24
Peak memory 215272 kb
Host smart-9e622ec5-f357-4640-8efe-abb0e6da51e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612678327 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1612678327
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1731524618
Short name T259
Test name
Test status
Simulation time 30168921 ps
CPU time 0.93 seconds
Started Jun 26 06:37:08 PM PDT 24
Finished Jun 26 06:37:32 PM PDT 24
Peak memory 206984 kb
Host smart-5cfc07c8-3f48-4a66-9564-28847edc9904
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731524618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1731524618
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2941642117
Short name T1075
Test name
Test status
Simulation time 23896167 ps
CPU time 0.84 seconds
Started Jun 26 06:37:09 PM PDT 24
Finished Jun 26 06:37:32 PM PDT 24
Peak memory 206928 kb
Host smart-37a1a40b-5f56-41bd-8342-e681c928a8ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941642117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2941642117
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1919587584
Short name T1093
Test name
Test status
Simulation time 106354978 ps
CPU time 1.29 seconds
Started Jun 26 06:37:08 PM PDT 24
Finished Jun 26 06:37:32 PM PDT 24
Peak memory 206972 kb
Host smart-a9422507-40f9-4929-958f-211b641ec817
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919587584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1919587584
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1853176107
Short name T1007
Test name
Test status
Simulation time 168609175 ps
CPU time 2.85 seconds
Started Jun 26 06:37:11 PM PDT 24
Finished Jun 26 06:37:36 PM PDT 24
Peak memory 215144 kb
Host smart-48f160d6-c0e6-4c91-9bd3-e24c5aed432e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853176107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1853176107
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2585065229
Short name T276
Test name
Test status
Simulation time 158052590 ps
CPU time 2.26 seconds
Started Jun 26 06:37:11 PM PDT 24
Finished Jun 26 06:37:35 PM PDT 24
Peak memory 207108 kb
Host smart-e8029067-1b4c-43c9-82c4-6f2b2f42db41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585065229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2585065229
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.32055750
Short name T1108
Test name
Test status
Simulation time 98572674 ps
CPU time 1.35 seconds
Started Jun 26 06:37:23 PM PDT 24
Finished Jun 26 06:37:39 PM PDT 24
Peak memory 215196 kb
Host smart-46cda5bd-8927-402a-95b8-92f3b33a2ec2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32055750 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.32055750
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3823954317
Short name T1128
Test name
Test status
Simulation time 52043028 ps
CPU time 0.83 seconds
Started Jun 26 06:37:11 PM PDT 24
Finished Jun 26 06:37:34 PM PDT 24
Peak memory 206764 kb
Host smart-0808ca38-5401-4628-82d5-85a8aff9b3dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823954317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3823954317
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1714655891
Short name T1110
Test name
Test status
Simulation time 14581519 ps
CPU time 0.9 seconds
Started Jun 26 06:37:10 PM PDT 24
Finished Jun 26 06:37:33 PM PDT 24
Peak memory 206872 kb
Host smart-252c712a-87fc-45e2-b756-0fcb009f378c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714655891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1714655891
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2579601252
Short name T1029
Test name
Test status
Simulation time 69691698 ps
CPU time 1 seconds
Started Jun 26 06:37:13 PM PDT 24
Finished Jun 26 06:37:34 PM PDT 24
Peak memory 206976 kb
Host smart-ce6204da-52a0-406f-9093-278eeedeac10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579601252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2579601252
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2460826798
Short name T1126
Test name
Test status
Simulation time 42847762 ps
CPU time 3.05 seconds
Started Jun 26 06:37:11 PM PDT 24
Finished Jun 26 06:37:36 PM PDT 24
Peak memory 215208 kb
Host smart-cdda66f1-9c99-4e0f-a9a1-9d913770387d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460826798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2460826798
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2165589427
Short name T1048
Test name
Test status
Simulation time 233567255 ps
CPU time 2.9 seconds
Started Jun 26 06:37:09 PM PDT 24
Finished Jun 26 06:37:35 PM PDT 24
Peak memory 215144 kb
Host smart-c06a7eaf-faad-4895-8040-42090eb96e7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165589427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2165589427
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3666343454
Short name T963
Test name
Test status
Simulation time 24151100 ps
CPU time 1.2 seconds
Started Jun 26 06:26:50 PM PDT 24
Finished Jun 26 06:26:52 PM PDT 24
Peak memory 219188 kb
Host smart-e8258f47-d512-4f56-ae72-a7ecb27e59dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666343454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3666343454
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.3175014642
Short name T459
Test name
Test status
Simulation time 26730210 ps
CPU time 0.91 seconds
Started Jun 26 06:26:50 PM PDT 24
Finished Jun 26 06:26:52 PM PDT 24
Peak memory 207000 kb
Host smart-680a0cb8-930c-49c3-8c26-ee8257adf725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175014642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3175014642
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.1566472903
Short name T225
Test name
Test status
Simulation time 13863147 ps
CPU time 0.99 seconds
Started Jun 26 06:26:47 PM PDT 24
Finished Jun 26 06:26:49 PM PDT 24
Peak memory 216704 kb
Host smart-b50b1f16-6ad4-4cb3-b662-fc1a50b65149
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566472903 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1566472903
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2781764013
Short name T485
Test name
Test status
Simulation time 101781611 ps
CPU time 1.08 seconds
Started Jun 26 06:26:50 PM PDT 24
Finished Jun 26 06:26:52 PM PDT 24
Peak memory 219728 kb
Host smart-f357558a-ee2e-42dd-893b-dd1ae6d7441c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781764013 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2781764013
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_intr.1456219646
Short name T109
Test name
Test status
Simulation time 26455601 ps
CPU time 0.9 seconds
Started Jun 26 06:26:45 PM PDT 24
Finished Jun 26 06:26:47 PM PDT 24
Peak memory 216212 kb
Host smart-0e450fc5-cb8e-46a5-a298-27cbaf26118c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456219646 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1456219646
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.856000740
Short name T63
Test name
Test status
Simulation time 918047942 ps
CPU time 8.28 seconds
Started Jun 26 06:26:45 PM PDT 24
Finished Jun 26 06:26:55 PM PDT 24
Peak memory 244104 kb
Host smart-4d00554d-3e50-440b-93e1-3cf4f9d29763
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856000740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.856000740
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.707431065
Short name T360
Test name
Test status
Simulation time 21043584 ps
CPU time 0.96 seconds
Started Jun 26 06:26:48 PM PDT 24
Finished Jun 26 06:26:51 PM PDT 24
Peak memory 215616 kb
Host smart-b2ac07f2-0828-45ed-9f6f-da95f3c3b37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707431065 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.707431065
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1944300424
Short name T376
Test name
Test status
Simulation time 580356954 ps
CPU time 5.68 seconds
Started Jun 26 06:26:50 PM PDT 24
Finished Jun 26 06:26:57 PM PDT 24
Peak memory 215640 kb
Host smart-74b05f40-92e2-4231-a703-c1ba7dbd0db4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944300424 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1944300424
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2196800183
Short name T832
Test name
Test status
Simulation time 18756096209 ps
CPU time 401.61 seconds
Started Jun 26 06:26:49 PM PDT 24
Finished Jun 26 06:33:32 PM PDT 24
Peak memory 221836 kb
Host smart-39d6d38f-3dda-4be6-9e66-c8790bc45e57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196800183 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2196800183
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.664823727
Short name T527
Test name
Test status
Simulation time 30122589 ps
CPU time 1.35 seconds
Started Jun 26 06:26:56 PM PDT 24
Finished Jun 26 06:26:59 PM PDT 24
Peak memory 219960 kb
Host smart-1e370ebd-f569-4a6b-8f54-d152f15c3668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664823727 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.664823727
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.3863828364
Short name T397
Test name
Test status
Simulation time 26000036 ps
CPU time 0.97 seconds
Started Jun 26 06:26:55 PM PDT 24
Finished Jun 26 06:26:58 PM PDT 24
Peak memory 215260 kb
Host smart-520239df-9a52-4296-9e2e-ffb59e2a5689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863828364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3863828364
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.2104299352
Short name T833
Test name
Test status
Simulation time 11856371 ps
CPU time 0.91 seconds
Started Jun 26 06:26:56 PM PDT 24
Finished Jun 26 06:26:59 PM PDT 24
Peak memory 216316 kb
Host smart-5e43b71f-2681-4884-8846-dca13b5b5179
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104299352 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2104299352
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1352878253
Short name T18
Test name
Test status
Simulation time 42754926 ps
CPU time 1.32 seconds
Started Jun 26 06:26:52 PM PDT 24
Finished Jun 26 06:26:55 PM PDT 24
Peak memory 218832 kb
Host smart-904340e9-ca68-4b89-816f-5f878f5a015a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352878253 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1352878253
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.4170881959
Short name T541
Test name
Test status
Simulation time 45802429 ps
CPU time 1.01 seconds
Started Jun 26 06:26:56 PM PDT 24
Finished Jun 26 06:26:59 PM PDT 24
Peak memory 224328 kb
Host smart-4ad6ba4f-064c-44d2-9af5-8b6383ae9ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170881959 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.4170881959
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2155774338
Short name T51
Test name
Test status
Simulation time 67878266 ps
CPU time 1.48 seconds
Started Jun 26 06:26:53 PM PDT 24
Finished Jun 26 06:26:56 PM PDT 24
Peak memory 219148 kb
Host smart-c8967bcb-0425-46c5-a2ef-f21c5593bff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155774338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2155774338
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1652839775
Short name T907
Test name
Test status
Simulation time 21651865 ps
CPU time 1.07 seconds
Started Jun 26 06:26:53 PM PDT 24
Finished Jun 26 06:26:55 PM PDT 24
Peak memory 216120 kb
Host smart-b27e4b51-9210-4f57-b310-1b1ee324c203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652839775 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1652839775
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.639952724
Short name T918
Test name
Test status
Simulation time 42605535 ps
CPU time 0.92 seconds
Started Jun 26 06:26:57 PM PDT 24
Finished Jun 26 06:26:59 PM PDT 24
Peak memory 207444 kb
Host smart-154b6210-0bad-4e89-9cb6-e4c1bf729b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639952724 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.639952724
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.87911153
Short name T17
Test name
Test status
Simulation time 1001014485 ps
CPU time 8.16 seconds
Started Jun 26 06:26:54 PM PDT 24
Finished Jun 26 06:27:04 PM PDT 24
Peak memory 237880 kb
Host smart-098e2f45-5807-45cb-b13d-cdb9e5121561
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87911153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.87911153
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.266046292
Short name T683
Test name
Test status
Simulation time 16423134 ps
CPU time 0.99 seconds
Started Jun 26 06:26:48 PM PDT 24
Finished Jun 26 06:26:51 PM PDT 24
Peak memory 215580 kb
Host smart-3bcfade5-858a-4e77-a26e-6de291918ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266046292 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.266046292
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.797958032
Short name T828
Test name
Test status
Simulation time 43525148 ps
CPU time 1.54 seconds
Started Jun 26 06:26:53 PM PDT 24
Finished Jun 26 06:26:56 PM PDT 24
Peak memory 217664 kb
Host smart-52cbff9d-df3d-4275-a4f6-13b808083a8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797958032 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.797958032
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1887439850
Short name T237
Test name
Test status
Simulation time 36488230863 ps
CPU time 783.61 seconds
Started Jun 26 06:26:56 PM PDT 24
Finished Jun 26 06:40:02 PM PDT 24
Peak memory 218824 kb
Host smart-879f05f6-f833-4341-8f0c-fb31a6d51f67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887439850 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1887439850
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.635733767
Short name T852
Test name
Test status
Simulation time 26606058 ps
CPU time 1.3 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:27:20 PM PDT 24
Peak memory 219984 kb
Host smart-27fa373e-a190-4486-aa8f-29ca93a9842b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635733767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.635733767
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1888087607
Short name T447
Test name
Test status
Simulation time 28720638 ps
CPU time 1.07 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:27:19 PM PDT 24
Peak memory 218840 kb
Host smart-5430e373-5cc3-434d-ba68-d7cc6bf2eede
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888087607 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1888087607
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.2729384837
Short name T772
Test name
Test status
Simulation time 32369062 ps
CPU time 0.87 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:24 PM PDT 24
Peak memory 218800 kb
Host smart-df39a985-744d-4362-883e-d0103dc9695b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729384837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2729384837
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.321681720
Short name T639
Test name
Test status
Simulation time 36422545 ps
CPU time 1.46 seconds
Started Jun 26 06:27:15 PM PDT 24
Finished Jun 26 06:27:21 PM PDT 24
Peak memory 218888 kb
Host smart-3eea9303-0c46-45c0-84fa-4a236598aabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321681720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.321681720
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1461902594
Short name T548
Test name
Test status
Simulation time 68602570 ps
CPU time 0.99 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:24 PM PDT 24
Peak memory 215652 kb
Host smart-49ccb0ed-4b28-4924-8d90-31cfbba3e714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461902594 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1461902594
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2847015659
Short name T336
Test name
Test status
Simulation time 17494963 ps
CPU time 1.01 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:27:18 PM PDT 24
Peak memory 215628 kb
Host smart-2b204260-1e97-48b8-ba8e-d67e2461154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847015659 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2847015659
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2804898782
Short name T199
Test name
Test status
Simulation time 95089635 ps
CPU time 1.55 seconds
Started Jun 26 06:27:12 PM PDT 24
Finished Jun 26 06:27:15 PM PDT 24
Peak memory 217600 kb
Host smart-e8d5d2e5-906f-439c-93b2-269969898d63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804898782 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2804898782
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3048197483
Short name T809
Test name
Test status
Simulation time 965852277689 ps
CPU time 1684.19 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:55:23 PM PDT 24
Peak memory 224672 kb
Host smart-33ccaa54-2b48-400a-b522-af48e4f50696
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048197483 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3048197483
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.921236121
Short name T408
Test name
Test status
Simulation time 29296739 ps
CPU time 1.37 seconds
Started Jun 26 06:28:28 PM PDT 24
Finished Jun 26 06:28:31 PM PDT 24
Peak memory 217872 kb
Host smart-ceea2fcd-4940-47d6-a2a6-72ae3f867e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921236121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.921236121
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.1116977272
Short name T389
Test name
Test status
Simulation time 61840234 ps
CPU time 1.27 seconds
Started Jun 26 06:28:30 PM PDT 24
Finished Jun 26 06:28:33 PM PDT 24
Peak memory 218904 kb
Host smart-aa807afa-8ee1-4994-bedf-552db6fff89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116977272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1116977272
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.2338358771
Short name T317
Test name
Test status
Simulation time 275538165 ps
CPU time 1.12 seconds
Started Jun 26 06:28:31 PM PDT 24
Finished Jun 26 06:28:34 PM PDT 24
Peak memory 220072 kb
Host smart-6b57ee4b-0b41-40aa-a951-a5afb937c0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338358771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.2338358771
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.3573361825
Short name T441
Test name
Test status
Simulation time 32707626 ps
CPU time 0.98 seconds
Started Jun 26 06:28:40 PM PDT 24
Finished Jun 26 06:28:45 PM PDT 24
Peak memory 217524 kb
Host smart-10f2b132-d24d-41a0-8dc1-69ee9a8560f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573361825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3573361825
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.1545311561
Short name T708
Test name
Test status
Simulation time 31679053 ps
CPU time 1.14 seconds
Started Jun 26 06:28:32 PM PDT 24
Finished Jun 26 06:28:37 PM PDT 24
Peak memory 219940 kb
Host smart-d5ac5612-1035-4b10-aae2-80731ea0c2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545311561 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.1545311561
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.2288874010
Short name T973
Test name
Test status
Simulation time 754982827 ps
CPU time 3.84 seconds
Started Jun 26 06:28:34 PM PDT 24
Finished Jun 26 06:28:42 PM PDT 24
Peak memory 220580 kb
Host smart-c7ecac3b-4aed-4e1b-bac7-53a4814aad00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288874010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2288874010
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.2000951672
Short name T894
Test name
Test status
Simulation time 105312344 ps
CPU time 1.1 seconds
Started Jun 26 06:28:31 PM PDT 24
Finished Jun 26 06:28:34 PM PDT 24
Peak memory 219840 kb
Host smart-27c01a2e-ad00-4b4c-8783-f737c9cfc569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000951672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.2000951672
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.2493002522
Short name T757
Test name
Test status
Simulation time 44294542 ps
CPU time 1.53 seconds
Started Jun 26 06:28:38 PM PDT 24
Finished Jun 26 06:28:44 PM PDT 24
Peak memory 217568 kb
Host smart-cd3f0101-ff38-4340-8d4d-d5c41ed16d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493002522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2493002522
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1523788168
Short name T61
Test name
Test status
Simulation time 69045115 ps
CPU time 1.04 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:38 PM PDT 24
Peak memory 217668 kb
Host smart-23af4538-9cd0-4821-9e19-122745a9da23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523788168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1523788168
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.3281520950
Short name T624
Test name
Test status
Simulation time 239272920 ps
CPU time 1.11 seconds
Started Jun 26 06:28:34 PM PDT 24
Finished Jun 26 06:28:40 PM PDT 24
Peak memory 221460 kb
Host smart-b2503c46-987c-4a18-b33e-b853abbe588e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281520950 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.3281520950
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.277528009
Short name T354
Test name
Test status
Simulation time 44507990 ps
CPU time 1.07 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:38 PM PDT 24
Peak memory 217640 kb
Host smart-bcad7fb3-025c-4a10-9f59-67b64fa29c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277528009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.277528009
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.3363806538
Short name T241
Test name
Test status
Simulation time 42598384 ps
CPU time 1.24 seconds
Started Jun 26 06:28:29 PM PDT 24
Finished Jun 26 06:28:33 PM PDT 24
Peak memory 219576 kb
Host smart-1ad96971-5db4-4652-a057-b3294b04c24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363806538 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.3363806538
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.2539137697
Short name T342
Test name
Test status
Simulation time 46061145 ps
CPU time 1.27 seconds
Started Jun 26 06:28:36 PM PDT 24
Finished Jun 26 06:28:42 PM PDT 24
Peak memory 218820 kb
Host smart-9cc892d7-1728-4996-b443-311935445ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539137697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2539137697
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.3240658757
Short name T976
Test name
Test status
Simulation time 27985429 ps
CPU time 1.18 seconds
Started Jun 26 06:28:42 PM PDT 24
Finished Jun 26 06:28:47 PM PDT 24
Peak memory 218920 kb
Host smart-4693d581-0014-4201-8db4-81b8f9c9b057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240658757 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3240658757
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.951221324
Short name T481
Test name
Test status
Simulation time 776423546 ps
CPU time 5.41 seconds
Started Jun 26 06:28:29 PM PDT 24
Finished Jun 26 06:28:36 PM PDT 24
Peak memory 218280 kb
Host smart-5e6d3144-918a-4324-a333-d26621692942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951221324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.951221324
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.557617244
Short name T647
Test name
Test status
Simulation time 36818934 ps
CPU time 1.2 seconds
Started Jun 26 06:27:18 PM PDT 24
Finished Jun 26 06:27:25 PM PDT 24
Peak memory 219112 kb
Host smart-5fa2aaf1-3433-4ffb-9bf2-5ef52764accb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557617244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.557617244
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3034509094
Short name T345
Test name
Test status
Simulation time 21097205 ps
CPU time 0.89 seconds
Started Jun 26 06:27:13 PM PDT 24
Finished Jun 26 06:27:16 PM PDT 24
Peak memory 207124 kb
Host smart-50cbfa97-397e-4090-a0c7-fafe0dd11038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034509094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3034509094
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.4248526520
Short name T9
Test name
Test status
Simulation time 70226300 ps
CPU time 1.28 seconds
Started Jun 26 06:27:12 PM PDT 24
Finished Jun 26 06:27:14 PM PDT 24
Peak memory 217108 kb
Host smart-767c47a0-285e-4bf3-aee1-dd3a09806362
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248526520 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.4248526520
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1002316049
Short name T138
Test name
Test status
Simulation time 26232793 ps
CPU time 1.2 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:27:18 PM PDT 24
Peak memory 219044 kb
Host smart-064bff8c-12e5-4db1-a771-38db3702be84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002316049 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1002316049
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.3872110745
Short name T681
Test name
Test status
Simulation time 76704902 ps
CPU time 1.17 seconds
Started Jun 26 06:27:15 PM PDT 24
Finished Jun 26 06:27:20 PM PDT 24
Peak memory 219100 kb
Host smart-dd4066f0-bbcf-4ff4-8399-7bee112cd3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872110745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3872110745
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1943436166
Short name T632
Test name
Test status
Simulation time 26378291 ps
CPU time 1.06 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:27:17 PM PDT 24
Peak memory 224372 kb
Host smart-67062d97-438f-4c0e-9149-e3b5dbf35dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943436166 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1943436166
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.542206745
Short name T330
Test name
Test status
Simulation time 165607946 ps
CPU time 1.04 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:24 PM PDT 24
Peak memory 207416 kb
Host smart-e0d85788-782a-4b1d-bbb9-a244ddcfb13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542206745 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.542206745
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2445490557
Short name T292
Test name
Test status
Simulation time 409481731 ps
CPU time 2.74 seconds
Started Jun 26 06:27:20 PM PDT 24
Finished Jun 26 06:27:28 PM PDT 24
Peak memory 220336 kb
Host smart-c46770f6-3c4f-408d-9191-bee2a8e76a2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445490557 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2445490557
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2639544815
Short name T236
Test name
Test status
Simulation time 153660894565 ps
CPU time 1338.05 seconds
Started Jun 26 06:27:20 PM PDT 24
Finished Jun 26 06:49:44 PM PDT 24
Peak memory 222980 kb
Host smart-4fd2e36b-e8b8-4899-826e-5b56a2048aee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639544815 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2639544815
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.2693777144
Short name T100
Test name
Test status
Simulation time 37166457 ps
CPU time 1.21 seconds
Started Jun 26 06:28:34 PM PDT 24
Finished Jun 26 06:28:40 PM PDT 24
Peak memory 218808 kb
Host smart-43e8a780-8b75-4e90-8fab-2507d62643d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693777144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.2693777144
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.1441218051
Short name T11
Test name
Test status
Simulation time 101507800 ps
CPU time 1.31 seconds
Started Jun 26 06:28:31 PM PDT 24
Finished Jun 26 06:28:36 PM PDT 24
Peak memory 219700 kb
Host smart-402b8a62-df33-4cf9-99f1-31e48d19d4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441218051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1441218051
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3908655371
Short name T320
Test name
Test status
Simulation time 25280757 ps
CPU time 1.25 seconds
Started Jun 26 06:28:30 PM PDT 24
Finished Jun 26 06:28:34 PM PDT 24
Peak memory 220136 kb
Host smart-ffd54306-ba56-4d38-a46a-2fded5fc7882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908655371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3908655371
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.907608049
Short name T64
Test name
Test status
Simulation time 53179871 ps
CPU time 1.27 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:38 PM PDT 24
Peak memory 219008 kb
Host smart-ba350ee8-93e5-47c1-b254-6e305c2631d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907608049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.907608049
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.3644524768
Short name T861
Test name
Test status
Simulation time 41884752 ps
CPU time 1.13 seconds
Started Jun 26 06:28:44 PM PDT 24
Finished Jun 26 06:28:49 PM PDT 24
Peak memory 219880 kb
Host smart-5cdb6c55-90ab-4063-9f68-934c26c58833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644524768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.3644524768
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.1980398021
Short name T497
Test name
Test status
Simulation time 47111094 ps
CPU time 1.69 seconds
Started Jun 26 06:28:41 PM PDT 24
Finished Jun 26 06:28:46 PM PDT 24
Peak memory 218996 kb
Host smart-fd8307e4-2117-4264-87ae-3118a9c7630a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980398021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1980398021
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.727865805
Short name T587
Test name
Test status
Simulation time 24586734 ps
CPU time 1.22 seconds
Started Jun 26 06:28:35 PM PDT 24
Finished Jun 26 06:28:40 PM PDT 24
Peak memory 220140 kb
Host smart-ae3633ba-e940-4d0e-ad68-70efaab02710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727865805 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.727865805
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.1736808524
Short name T545
Test name
Test status
Simulation time 40689538 ps
CPU time 1.39 seconds
Started Jun 26 06:28:38 PM PDT 24
Finished Jun 26 06:28:44 PM PDT 24
Peak memory 219076 kb
Host smart-569adc6b-657b-43a0-aa53-c8d8f5040101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736808524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1736808524
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.1052433358
Short name T970
Test name
Test status
Simulation time 31455837 ps
CPU time 1.19 seconds
Started Jun 26 06:28:40 PM PDT 24
Finished Jun 26 06:28:45 PM PDT 24
Peak memory 221164 kb
Host smart-389cdf79-f331-4eb0-accd-c66f5ed4c13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052433358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.1052433358
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.87091961
Short name T995
Test name
Test status
Simulation time 43883035 ps
CPU time 1.13 seconds
Started Jun 26 06:28:40 PM PDT 24
Finished Jun 26 06:28:46 PM PDT 24
Peak memory 217700 kb
Host smart-46b48534-0f31-47f7-b8a6-3e55b102d706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87091961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.87091961
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.3919210790
Short name T224
Test name
Test status
Simulation time 187462216 ps
CPU time 1.29 seconds
Started Jun 26 06:28:38 PM PDT 24
Finished Jun 26 06:28:57 PM PDT 24
Peak memory 219052 kb
Host smart-b069620f-8ed3-4b83-b6cf-ed9c98288f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919210790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.3919210790
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.1532362012
Short name T83
Test name
Test status
Simulation time 372845886 ps
CPU time 3.51 seconds
Started Jun 26 06:28:43 PM PDT 24
Finished Jun 26 06:28:50 PM PDT 24
Peak memory 220520 kb
Host smart-78833ce0-c072-4552-adb8-12549d962d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532362012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1532362012
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.4193889500
Short name T564
Test name
Test status
Simulation time 38362569 ps
CPU time 1.2 seconds
Started Jun 26 06:28:36 PM PDT 24
Finished Jun 26 06:28:42 PM PDT 24
Peak memory 220228 kb
Host smart-9dfcb0ce-beef-4221-9e3e-ad8d31c2af42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193889500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.4193889500
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.661083250
Short name T421
Test name
Test status
Simulation time 33487364 ps
CPU time 1.34 seconds
Started Jun 26 06:28:35 PM PDT 24
Finished Jun 26 06:28:41 PM PDT 24
Peak memory 217656 kb
Host smart-942b7131-9f5f-41c1-a286-7ca57ef849c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661083250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.661083250
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3161658630
Short name T875
Test name
Test status
Simulation time 117666700 ps
CPU time 1.26 seconds
Started Jun 26 06:28:41 PM PDT 24
Finished Jun 26 06:28:47 PM PDT 24
Peak memory 217956 kb
Host smart-d587541f-8cb6-4426-a1b7-b7adbc889475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161658630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3161658630
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.451443666
Short name T74
Test name
Test status
Simulation time 153150723 ps
CPU time 1.07 seconds
Started Jun 26 06:28:43 PM PDT 24
Finished Jun 26 06:28:48 PM PDT 24
Peak memory 218776 kb
Host smart-b48f822c-4296-4c76-a04e-09e1f3b77d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451443666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.451443666
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.3087558336
Short name T850
Test name
Test status
Simulation time 54637065 ps
CPU time 1.25 seconds
Started Jun 26 06:28:35 PM PDT 24
Finished Jun 26 06:28:41 PM PDT 24
Peak memory 217524 kb
Host smart-c497fc0b-6e41-4e1f-9cec-354f389068c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087558336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3087558336
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1533815117
Short name T951
Test name
Test status
Simulation time 72894714 ps
CPU time 1.13 seconds
Started Jun 26 06:27:15 PM PDT 24
Finished Jun 26 06:27:21 PM PDT 24
Peak memory 219536 kb
Host smart-bbdfeafc-15bb-40ff-b2ec-3b7955fa83f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533815117 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1533815117
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3155763306
Short name T549
Test name
Test status
Simulation time 30602495 ps
CPU time 0.98 seconds
Started Jun 26 06:27:15 PM PDT 24
Finished Jun 26 06:27:20 PM PDT 24
Peak memory 215204 kb
Host smart-ab6a916f-f30c-452e-a5f4-a957936bdf89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155763306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3155763306
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.3770100443
Short name T23
Test name
Test status
Simulation time 35455452 ps
CPU time 0.88 seconds
Started Jun 26 06:27:19 PM PDT 24
Finished Jun 26 06:27:25 PM PDT 24
Peak memory 216304 kb
Host smart-01baccd3-d04e-42f6-b8e0-acfc63c4aa1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770100443 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3770100443
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.2681354647
Short name T163
Test name
Test status
Simulation time 18588349 ps
CPU time 1.14 seconds
Started Jun 26 06:27:15 PM PDT 24
Finished Jun 26 06:27:21 PM PDT 24
Peak memory 218660 kb
Host smart-01c763af-9326-48c7-b874-3d33e92a35d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681354647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2681354647
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.817028384
Short name T353
Test name
Test status
Simulation time 37688323 ps
CPU time 1.18 seconds
Started Jun 26 06:27:20 PM PDT 24
Finished Jun 26 06:27:27 PM PDT 24
Peak memory 219120 kb
Host smart-c4499a73-1af4-4069-a1a0-d54bf56ef632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817028384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.817028384
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.2008090998
Short name T915
Test name
Test status
Simulation time 25970758 ps
CPU time 1.16 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:23 PM PDT 24
Peak memory 224328 kb
Host smart-bbeda060-0545-456e-b70f-c9414dc2540a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008090998 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2008090998
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.3847155226
Short name T500
Test name
Test status
Simulation time 16022316 ps
CPU time 1.06 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:27:17 PM PDT 24
Peak memory 215644 kb
Host smart-e23a0363-426e-4680-853d-0389abb958a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847155226 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3847155226
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2412531489
Short name T407
Test name
Test status
Simulation time 316824241 ps
CPU time 4.94 seconds
Started Jun 26 06:27:15 PM PDT 24
Finished Jun 26 06:27:23 PM PDT 24
Peak memory 215592 kb
Host smart-7b27fa66-36ce-43c8-9d41-9664c5882e4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412531489 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2412531489
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1439259642
Short name T383
Test name
Test status
Simulation time 149496990887 ps
CPU time 1849.85 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:58:06 PM PDT 24
Peak memory 229460 kb
Host smart-0ff8a994-56e1-4bd4-8632-23b07505f289
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439259642 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1439259642
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.1675683861
Short name T928
Test name
Test status
Simulation time 94134684 ps
CPU time 1.59 seconds
Started Jun 26 06:28:46 PM PDT 24
Finished Jun 26 06:28:52 PM PDT 24
Peak memory 219228 kb
Host smart-9f84f129-30c3-491a-b8ec-c4b34586f192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675683861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1675683861
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.2937435772
Short name T688
Test name
Test status
Simulation time 25048514 ps
CPU time 1.23 seconds
Started Jun 26 06:28:35 PM PDT 24
Finished Jun 26 06:28:41 PM PDT 24
Peak memory 221056 kb
Host smart-c8247d4f-c4a2-4fb4-bae3-2d80e4b8ae15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937435772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.2937435772
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.611256336
Short name T756
Test name
Test status
Simulation time 54538387 ps
CPU time 1.68 seconds
Started Jun 26 06:28:40 PM PDT 24
Finished Jun 26 06:28:46 PM PDT 24
Peak memory 218920 kb
Host smart-f0a278c7-d9f0-4412-82cc-c1d65b986e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611256336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.611256336
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.1737200223
Short name T986
Test name
Test status
Simulation time 22939209 ps
CPU time 1.13 seconds
Started Jun 26 06:28:43 PM PDT 24
Finished Jun 26 06:28:48 PM PDT 24
Peak memory 220852 kb
Host smart-86edd48b-ea32-4d92-9cb7-4e29a62fc9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737200223 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.1737200223
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.723823730
Short name T550
Test name
Test status
Simulation time 74661901 ps
CPU time 1.44 seconds
Started Jun 26 06:28:43 PM PDT 24
Finished Jun 26 06:28:48 PM PDT 24
Peak memory 219264 kb
Host smart-92f9b310-d95a-4b72-b582-872f8f60bcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723823730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.723823730
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.2480446316
Short name T315
Test name
Test status
Simulation time 349175454 ps
CPU time 1.38 seconds
Started Jun 26 06:28:50 PM PDT 24
Finished Jun 26 06:28:54 PM PDT 24
Peak memory 221148 kb
Host smart-0a513812-7056-448c-bf01-6952cc1ce957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480446316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2480446316
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.3583357915
Short name T403
Test name
Test status
Simulation time 60882158 ps
CPU time 1.28 seconds
Started Jun 26 06:28:40 PM PDT 24
Finished Jun 26 06:28:45 PM PDT 24
Peak memory 215620 kb
Host smart-7152378d-9fdd-413e-965e-99e638717ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583357915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3583357915
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.2665041170
Short name T930
Test name
Test status
Simulation time 92567185 ps
CPU time 1.06 seconds
Started Jun 26 06:28:35 PM PDT 24
Finished Jun 26 06:28:41 PM PDT 24
Peak memory 218912 kb
Host smart-abe3ac93-f25b-4a94-80cd-03d0e27559d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665041170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.2665041170
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.3886345084
Short name T955
Test name
Test status
Simulation time 78404520 ps
CPU time 2.64 seconds
Started Jun 26 06:28:51 PM PDT 24
Finished Jun 26 06:28:56 PM PDT 24
Peak memory 220288 kb
Host smart-b8b5c7ea-a56a-46dd-a642-507f402ff7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886345084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3886345084
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.3855126879
Short name T678
Test name
Test status
Simulation time 33241376 ps
CPU time 1.33 seconds
Started Jun 26 06:28:42 PM PDT 24
Finished Jun 26 06:28:47 PM PDT 24
Peak memory 216020 kb
Host smart-6a0a9d64-e754-42b6-a454-4d0b5a7dac2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855126879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.3855126879
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.3083343681
Short name T604
Test name
Test status
Simulation time 57560782 ps
CPU time 1.39 seconds
Started Jun 26 06:28:42 PM PDT 24
Finished Jun 26 06:28:47 PM PDT 24
Peak memory 218996 kb
Host smart-eac963a5-1b55-4e68-bdb6-2c57cd843d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083343681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3083343681
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.2893252808
Short name T221
Test name
Test status
Simulation time 25942272 ps
CPU time 1.26 seconds
Started Jun 26 06:28:41 PM PDT 24
Finished Jun 26 06:28:46 PM PDT 24
Peak memory 220124 kb
Host smart-482d14e4-7d4f-4bc6-922e-07e678b4c355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893252808 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.2893252808
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.592267716
Short name T433
Test name
Test status
Simulation time 31002368 ps
CPU time 1.29 seconds
Started Jun 26 06:28:51 PM PDT 24
Finished Jun 26 06:28:55 PM PDT 24
Peak memory 218840 kb
Host smart-98ed0a3d-bd9d-44c7-9fc9-eb4ff205181d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592267716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.592267716
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.1937390416
Short name T181
Test name
Test status
Simulation time 24671236 ps
CPU time 1.09 seconds
Started Jun 26 06:28:35 PM PDT 24
Finished Jun 26 06:28:41 PM PDT 24
Peak memory 219724 kb
Host smart-c6c4de9d-48d2-455e-b73f-0f4e308e8748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937390416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.1937390416
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.3824841954
Short name T461
Test name
Test status
Simulation time 57832740 ps
CPU time 1.3 seconds
Started Jun 26 06:28:37 PM PDT 24
Finished Jun 26 06:28:43 PM PDT 24
Peak memory 219024 kb
Host smart-825e4974-b32c-4028-8b7f-68606f0012bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824841954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3824841954
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.1190016506
Short name T638
Test name
Test status
Simulation time 40475770 ps
CPU time 1.15 seconds
Started Jun 26 06:28:43 PM PDT 24
Finished Jun 26 06:28:48 PM PDT 24
Peak memory 219004 kb
Host smart-06c976c3-b491-4850-8423-5ade7db46f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190016506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.1190016506
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2092688593
Short name T956
Test name
Test status
Simulation time 26240524 ps
CPU time 0.91 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:23 PM PDT 24
Peak memory 215136 kb
Host smart-3721efb9-d3c8-4926-8dc5-3b82c9ab3061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092688593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2092688593
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.653162354
Short name T164
Test name
Test status
Simulation time 22335307 ps
CPU time 0.91 seconds
Started Jun 26 06:27:19 PM PDT 24
Finished Jun 26 06:27:25 PM PDT 24
Peak memory 216536 kb
Host smart-cce08e5b-4795-41fd-ab79-d3cefb3bd7ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653162354 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.653162354
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.334507587
Short name T818
Test name
Test status
Simulation time 38474283 ps
CPU time 1.19 seconds
Started Jun 26 06:27:15 PM PDT 24
Finished Jun 26 06:27:20 PM PDT 24
Peak memory 221132 kb
Host smart-473e2000-953e-4556-bfd2-38ee5bbfe23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334507587 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.334507587
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2806877340
Short name T542
Test name
Test status
Simulation time 98458428 ps
CPU time 2.11 seconds
Started Jun 26 06:27:28 PM PDT 24
Finished Jun 26 06:27:34 PM PDT 24
Peak memory 220536 kb
Host smart-7ac0ad4a-fbc7-4ea9-9f4d-045621ce91e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806877340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2806877340
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3606865860
Short name T697
Test name
Test status
Simulation time 30088145 ps
CPU time 0.9 seconds
Started Jun 26 06:27:29 PM PDT 24
Finished Jun 26 06:27:33 PM PDT 24
Peak memory 216072 kb
Host smart-d301eed9-5136-4d7a-9273-352e39e5e04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606865860 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3606865860
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.3938592857
Short name T334
Test name
Test status
Simulation time 16643328 ps
CPU time 0.99 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:23 PM PDT 24
Peak memory 215592 kb
Host smart-9c574274-cd38-4f3d-9e39-61dc8c6bcefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938592857 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3938592857
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3774488265
Short name T72
Test name
Test status
Simulation time 556737634 ps
CPU time 4.25 seconds
Started Jun 26 06:27:19 PM PDT 24
Finished Jun 26 06:27:28 PM PDT 24
Peak memory 217844 kb
Host smart-bfcc6587-4a92-49df-8a73-6b36b762ec57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774488265 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3774488265
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1501119328
Short name T378
Test name
Test status
Simulation time 55391797088 ps
CPU time 1196.67 seconds
Started Jun 26 06:27:16 PM PDT 24
Finished Jun 26 06:47:17 PM PDT 24
Peak memory 223988 kb
Host smart-c5f8b738-d36b-41b6-a892-2a99b4f513c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501119328 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1501119328
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.2989963393
Short name T700
Test name
Test status
Simulation time 86992466 ps
CPU time 1.25 seconds
Started Jun 26 06:28:42 PM PDT 24
Finished Jun 26 06:28:47 PM PDT 24
Peak memory 220560 kb
Host smart-be62ead9-0bc5-4a64-8ff7-43ceb66bfe04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989963393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2989963393
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/131.edn_alert.2757636730
Short name T666
Test name
Test status
Simulation time 152250273 ps
CPU time 1.45 seconds
Started Jun 26 06:28:55 PM PDT 24
Finished Jun 26 06:28:58 PM PDT 24
Peak memory 220372 kb
Host smart-99065eb1-fb26-4830-832a-42071f2faf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757636730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.2757636730
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/132.edn_alert.1101201689
Short name T519
Test name
Test status
Simulation time 88404639 ps
CPU time 1.23 seconds
Started Jun 26 06:28:45 PM PDT 24
Finished Jun 26 06:28:49 PM PDT 24
Peak memory 221804 kb
Host smart-4255ee4f-5c32-4ae9-a344-904e1fa46f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101201689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.1101201689
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.4284890684
Short name T889
Test name
Test status
Simulation time 77076916 ps
CPU time 1.67 seconds
Started Jun 26 06:28:57 PM PDT 24
Finished Jun 26 06:29:01 PM PDT 24
Peak memory 219296 kb
Host smart-ad317ee7-ba2d-47d9-afcb-04a002386d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284890684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.4284890684
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.1962145001
Short name T371
Test name
Test status
Simulation time 139601381 ps
CPU time 1.35 seconds
Started Jun 26 06:28:43 PM PDT 24
Finished Jun 26 06:28:48 PM PDT 24
Peak memory 220160 kb
Host smart-ef9a7408-53c5-42ce-88ec-aade54cb8843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962145001 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.1962145001
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.3361439905
Short name T65
Test name
Test status
Simulation time 116936189 ps
CPU time 1.29 seconds
Started Jun 26 06:28:51 PM PDT 24
Finished Jun 26 06:28:55 PM PDT 24
Peak memory 219196 kb
Host smart-2643696d-c37d-4956-abbe-abc77e305ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361439905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3361439905
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.3216309024
Short name T498
Test name
Test status
Simulation time 40058205 ps
CPU time 1.2 seconds
Started Jun 26 06:28:51 PM PDT 24
Finished Jun 26 06:28:54 PM PDT 24
Peak memory 219420 kb
Host smart-7dc864ef-1228-4464-a098-79db04fad325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216309024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.3216309024
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.3228543841
Short name T628
Test name
Test status
Simulation time 38210046 ps
CPU time 1.4 seconds
Started Jun 26 06:28:55 PM PDT 24
Finished Jun 26 06:28:58 PM PDT 24
Peak memory 218856 kb
Host smart-eef14a3f-72cc-4b0a-8e54-98f1cec4d184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228543841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3228543841
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.325872547
Short name T475
Test name
Test status
Simulation time 49166311 ps
CPU time 1.23 seconds
Started Jun 26 06:28:45 PM PDT 24
Finished Jun 26 06:28:51 PM PDT 24
Peak memory 218936 kb
Host smart-2e32546a-bbd7-443f-b612-016b3574bf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325872547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.325872547
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.1866943827
Short name T691
Test name
Test status
Simulation time 56172880 ps
CPU time 1.22 seconds
Started Jun 26 06:28:41 PM PDT 24
Finished Jun 26 06:28:46 PM PDT 24
Peak memory 220092 kb
Host smart-8cd826b2-0713-47de-b66e-e1e2fb7570da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866943827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1866943827
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.745405966
Short name T988
Test name
Test status
Simulation time 65722374 ps
CPU time 1.36 seconds
Started Jun 26 06:29:04 PM PDT 24
Finished Jun 26 06:29:07 PM PDT 24
Peak memory 218832 kb
Host smart-1481b99b-eb0a-45c4-bcec-4018ffe4f76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745405966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.745405966
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.4025457535
Short name T807
Test name
Test status
Simulation time 31251866 ps
CPU time 1.38 seconds
Started Jun 26 06:28:47 PM PDT 24
Finished Jun 26 06:28:52 PM PDT 24
Peak memory 220872 kb
Host smart-16f95a7e-7b2a-4fe2-9393-7cd739b17958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025457535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.4025457535
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.1918026629
Short name T424
Test name
Test status
Simulation time 90188931 ps
CPU time 1.33 seconds
Started Jun 26 06:28:57 PM PDT 24
Finished Jun 26 06:29:01 PM PDT 24
Peak memory 217600 kb
Host smart-0c329ffb-74c9-4bbf-94fe-59b6c6d67665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918026629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1918026629
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.2248622141
Short name T139
Test name
Test status
Simulation time 22859657 ps
CPU time 1.11 seconds
Started Jun 26 06:28:44 PM PDT 24
Finished Jun 26 06:28:49 PM PDT 24
Peak memory 221004 kb
Host smart-1b861339-af17-41a0-a10c-756d94d5d077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248622141 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.2248622141
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.1989185862
Short name T959
Test name
Test status
Simulation time 86118304 ps
CPU time 1.19 seconds
Started Jun 26 06:28:45 PM PDT 24
Finished Jun 26 06:28:51 PM PDT 24
Peak memory 217688 kb
Host smart-95abed0c-256f-40d2-9646-f289a923eb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989185862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1989185862
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.384249651
Short name T925
Test name
Test status
Simulation time 44193340 ps
CPU time 1.3 seconds
Started Jun 26 06:28:51 PM PDT 24
Finished Jun 26 06:28:54 PM PDT 24
Peak memory 220668 kb
Host smart-88cf5ac7-2be8-4b3e-88fd-c51ea795ba35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384249651 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.384249651
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.599909302
Short name T777
Test name
Test status
Simulation time 53182341 ps
CPU time 1.09 seconds
Started Jun 26 06:28:46 PM PDT 24
Finished Jun 26 06:28:51 PM PDT 24
Peak memory 219208 kb
Host smart-bdec3c03-3030-405e-907d-a9d29569066a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599909302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.599909302
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1602290723
Short name T132
Test name
Test status
Simulation time 73304382 ps
CPU time 1.18 seconds
Started Jun 26 06:27:27 PM PDT 24
Finished Jun 26 06:27:32 PM PDT 24
Peak memory 220084 kb
Host smart-f07b7121-2323-48b1-8d98-55206d9aaa77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602290723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1602290723
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.726601113
Short name T390
Test name
Test status
Simulation time 19497583 ps
CPU time 0.98 seconds
Started Jun 26 06:27:28 PM PDT 24
Finished Jun 26 06:27:33 PM PDT 24
Peak memory 206968 kb
Host smart-7fc92376-f864-49b3-b78d-66dc1f142876
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726601113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.726601113
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.668271271
Short name T783
Test name
Test status
Simulation time 11902861 ps
CPU time 0.87 seconds
Started Jun 26 06:27:27 PM PDT 24
Finished Jun 26 06:27:32 PM PDT 24
Peak memory 216320 kb
Host smart-5819c8ce-8df8-4514-a063-4e19957d58fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668271271 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.668271271
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1326384427
Short name T945
Test name
Test status
Simulation time 57629855 ps
CPU time 1.07 seconds
Started Jun 26 06:27:19 PM PDT 24
Finished Jun 26 06:27:25 PM PDT 24
Peak memory 218800 kb
Host smart-676b424b-3e32-4f61-96c2-1536d1d81f43
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326384427 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1326384427
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3162156692
Short name T57
Test name
Test status
Simulation time 69469254 ps
CPU time 1.17 seconds
Started Jun 26 06:27:16 PM PDT 24
Finished Jun 26 06:27:22 PM PDT 24
Peak memory 225944 kb
Host smart-add3f361-6b8d-4b9f-b3f5-697eeab4ca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162156692 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3162156692
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2049505374
Short name T10
Test name
Test status
Simulation time 154182489 ps
CPU time 1.36 seconds
Started Jun 26 06:27:18 PM PDT 24
Finished Jun 26 06:27:25 PM PDT 24
Peak memory 218020 kb
Host smart-0caeed2a-efcc-40f3-a60f-97812365d555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049505374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2049505374
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.3389336326
Short name T370
Test name
Test status
Simulation time 25509897 ps
CPU time 1.05 seconds
Started Jun 26 06:27:15 PM PDT 24
Finished Jun 26 06:27:20 PM PDT 24
Peak memory 215656 kb
Host smart-6ecef27a-d7e1-4671-a641-19a354c9e682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389336326 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3389336326
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2947251470
Short name T629
Test name
Test status
Simulation time 361926306 ps
CPU time 4.01 seconds
Started Jun 26 06:27:18 PM PDT 24
Finished Jun 26 06:27:27 PM PDT 24
Peak memory 218772 kb
Host smart-586185cc-df4a-48c2-b1c1-aebf93a1513e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947251470 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2947251470
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.699450856
Short name T888
Test name
Test status
Simulation time 27246041497 ps
CPU time 343.71 seconds
Started Jun 26 06:27:28 PM PDT 24
Finished Jun 26 06:33:16 PM PDT 24
Peak memory 223984 kb
Host smart-c0da0ae9-efe4-4345-85a5-2abe057eeec5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699450856 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.699450856
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.3233454748
Short name T749
Test name
Test status
Simulation time 26155718 ps
CPU time 1.21 seconds
Started Jun 26 06:29:04 PM PDT 24
Finished Jun 26 06:29:06 PM PDT 24
Peak memory 219160 kb
Host smart-22c0faa1-0a34-4995-bd4d-fb43ab94d640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233454748 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.3233454748
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.1668122502
Short name T489
Test name
Test status
Simulation time 296100995 ps
CPU time 4.37 seconds
Started Jun 26 06:28:51 PM PDT 24
Finished Jun 26 06:28:58 PM PDT 24
Peak memory 220824 kb
Host smart-fce60e25-f7cf-429c-973d-67dd247a5401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668122502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1668122502
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.3901267791
Short name T671
Test name
Test status
Simulation time 67197255 ps
CPU time 1.68 seconds
Started Jun 26 06:28:56 PM PDT 24
Finished Jun 26 06:28:59 PM PDT 24
Peak memory 218972 kb
Host smart-66c99c6c-1fae-467e-bf4e-8ce14d1f3025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901267791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3901267791
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.3498467917
Short name T279
Test name
Test status
Simulation time 94014082 ps
CPU time 1.26 seconds
Started Jun 26 06:28:53 PM PDT 24
Finished Jun 26 06:28:57 PM PDT 24
Peak memory 219016 kb
Host smart-37adc6c8-7ac3-472e-be19-6da6a3cc0363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498467917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3498467917
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.2185676131
Short name T591
Test name
Test status
Simulation time 67152040 ps
CPU time 1.26 seconds
Started Jun 26 06:29:52 PM PDT 24
Finished Jun 26 06:29:55 PM PDT 24
Peak memory 219424 kb
Host smart-4f828292-a357-4718-9e4e-9d337c2dd746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185676131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2185676131
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.2235201568
Short name T165
Test name
Test status
Simulation time 50003627 ps
CPU time 1.15 seconds
Started Jun 26 06:28:55 PM PDT 24
Finished Jun 26 06:28:58 PM PDT 24
Peak memory 219976 kb
Host smart-aeed5e77-0dd7-4805-82b7-58c93e57f1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235201568 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.2235201568
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/144.edn_alert.4064629817
Short name T101
Test name
Test status
Simulation time 88000227 ps
CPU time 1.25 seconds
Started Jun 26 06:28:45 PM PDT 24
Finished Jun 26 06:28:50 PM PDT 24
Peak memory 219980 kb
Host smart-ccac24ae-6e6a-4f0c-9d73-94e17d8f92c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064629817 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.4064629817
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.3973444241
Short name T620
Test name
Test status
Simulation time 55366229 ps
CPU time 1.23 seconds
Started Jun 26 06:28:51 PM PDT 24
Finished Jun 26 06:28:55 PM PDT 24
Peak memory 217624 kb
Host smart-023dc79e-58a9-409c-bdde-bd98b5498df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973444241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3973444241
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.70777187
Short name T723
Test name
Test status
Simulation time 49826566 ps
CPU time 1.2 seconds
Started Jun 26 06:28:52 PM PDT 24
Finished Jun 26 06:28:56 PM PDT 24
Peak memory 220028 kb
Host smart-88b7b4b8-eae7-478c-8926-ba7105303fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70777187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.70777187
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.2352947980
Short name T940
Test name
Test status
Simulation time 48615384 ps
CPU time 1.54 seconds
Started Jun 26 06:28:43 PM PDT 24
Finished Jun 26 06:28:48 PM PDT 24
Peak memory 220436 kb
Host smart-7cc57d9c-a03a-48e0-9fda-aaa5c597e2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352947980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2352947980
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.3990830681
Short name T92
Test name
Test status
Simulation time 22378927 ps
CPU time 1.17 seconds
Started Jun 26 06:28:54 PM PDT 24
Finished Jun 26 06:28:58 PM PDT 24
Peak memory 219040 kb
Host smart-d9d4aba3-7f88-45c5-981c-97b62bb02fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990830681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.3990830681
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/147.edn_alert.2243325453
Short name T668
Test name
Test status
Simulation time 26122161 ps
CPU time 1.23 seconds
Started Jun 26 06:28:43 PM PDT 24
Finished Jun 26 06:28:47 PM PDT 24
Peak memory 219924 kb
Host smart-8c15ecda-fa3d-4520-b31c-3e3d6b302a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243325453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.2243325453
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3928667514
Short name T657
Test name
Test status
Simulation time 98427010 ps
CPU time 1.05 seconds
Started Jun 26 06:28:43 PM PDT 24
Finished Jun 26 06:28:49 PM PDT 24
Peak memory 217680 kb
Host smart-08b58ca1-5fce-431f-85af-79417fa95892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928667514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3928667514
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.1368105502
Short name T786
Test name
Test status
Simulation time 24887815 ps
CPU time 1.16 seconds
Started Jun 26 06:28:46 PM PDT 24
Finished Jun 26 06:28:51 PM PDT 24
Peak memory 220052 kb
Host smart-d38cf9d2-413c-4c68-bc62-538c5e602a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368105502 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.1368105502
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.4013584421
Short name T561
Test name
Test status
Simulation time 50122448 ps
CPU time 1.6 seconds
Started Jun 26 06:28:53 PM PDT 24
Finished Jun 26 06:28:57 PM PDT 24
Peak memory 215688 kb
Host smart-19eff33f-c599-46be-a5d7-57c78743309c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013584421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.4013584421
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.100079580
Short name T495
Test name
Test status
Simulation time 89582581 ps
CPU time 1.28 seconds
Started Jun 26 06:28:57 PM PDT 24
Finished Jun 26 06:29:01 PM PDT 24
Peak memory 219664 kb
Host smart-cc192eb9-74aa-41f6-b7c0-972a9f3a2195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100079580 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.100079580
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.3491815080
Short name T452
Test name
Test status
Simulation time 52049236 ps
CPU time 2 seconds
Started Jun 26 06:28:45 PM PDT 24
Finished Jun 26 06:28:51 PM PDT 24
Peak memory 220344 kb
Host smart-52d8c194-7d7d-45be-b9e4-ee175c48904a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491815080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3491815080
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1071362525
Short name T80
Test name
Test status
Simulation time 68839489 ps
CPU time 1.18 seconds
Started Jun 26 06:27:27 PM PDT 24
Finished Jun 26 06:27:33 PM PDT 24
Peak memory 220096 kb
Host smart-adcc43af-8e33-4919-bcd9-38f8561efdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071362525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1071362525
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1432970881
Short name T857
Test name
Test status
Simulation time 39488156 ps
CPU time 0.83 seconds
Started Jun 26 06:27:16 PM PDT 24
Finished Jun 26 06:27:23 PM PDT 24
Peak memory 206860 kb
Host smart-4223de6a-45dd-4c94-8cb7-314f79f4d53f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432970881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1432970881
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1199014629
Short name T483
Test name
Test status
Simulation time 34106918 ps
CPU time 0.81 seconds
Started Jun 26 06:27:28 PM PDT 24
Finished Jun 26 06:27:33 PM PDT 24
Peak memory 215628 kb
Host smart-3fc61d00-e012-4ad5-a4b0-a8d9c12a8d2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199014629 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1199014629
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.2089387082
Short name T174
Test name
Test status
Simulation time 18021377 ps
CPU time 1.15 seconds
Started Jun 26 06:27:56 PM PDT 24
Finished Jun 26 06:27:58 PM PDT 24
Peak memory 224352 kb
Host smart-769a486b-c399-4c02-b9ac-75e914f708d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089387082 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2089387082
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.941168468
Short name T770
Test name
Test status
Simulation time 61373713 ps
CPU time 2.22 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:27:18 PM PDT 24
Peak memory 220312 kb
Host smart-f963b059-3983-4a98-9370-3eb7a0a1f02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941168468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.941168468
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2003844898
Short name T394
Test name
Test status
Simulation time 24107286 ps
CPU time 1.08 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:23 PM PDT 24
Peak memory 215584 kb
Host smart-944f7a48-5215-455b-a9b8-a1c2cdd51e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003844898 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2003844898
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.390020936
Short name T595
Test name
Test status
Simulation time 30777936 ps
CPU time 0.96 seconds
Started Jun 26 06:27:29 PM PDT 24
Finished Jun 26 06:27:34 PM PDT 24
Peak memory 215520 kb
Host smart-287b4514-df1e-45e7-b302-f0d85691a20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390020936 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.390020936
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.729469262
Short name T596
Test name
Test status
Simulation time 241108415 ps
CPU time 1.86 seconds
Started Jun 26 06:27:19 PM PDT 24
Finished Jun 26 06:27:26 PM PDT 24
Peak memory 217588 kb
Host smart-aad7ca1c-660d-4e81-a036-4961a6acd211
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729469262 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.729469262
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2733951649
Short name T368
Test name
Test status
Simulation time 121620786542 ps
CPU time 559.51 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:36:41 PM PDT 24
Peak memory 220728 kb
Host smart-596c0fc7-434b-4609-95c0-afef292ba885
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733951649 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2733951649
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.3630963545
Short name T146
Test name
Test status
Simulation time 82498574 ps
CPU time 1.22 seconds
Started Jun 26 06:29:06 PM PDT 24
Finished Jun 26 06:29:09 PM PDT 24
Peak memory 219420 kb
Host smart-b02a845a-c794-48d4-bdb7-a1030ebd32f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630963545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.3630963545
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.1745521309
Short name T946
Test name
Test status
Simulation time 33493515 ps
CPU time 1.52 seconds
Started Jun 26 06:28:49 PM PDT 24
Finished Jun 26 06:28:54 PM PDT 24
Peak memory 219068 kb
Host smart-c99409d5-bcc4-404c-84b8-af76d8209797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745521309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1745521309
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.2284782543
Short name T189
Test name
Test status
Simulation time 34318575 ps
CPU time 1.27 seconds
Started Jun 26 06:28:54 PM PDT 24
Finished Jun 26 06:28:58 PM PDT 24
Peak memory 216052 kb
Host smart-68244c64-882f-4f39-b536-cd7c12da20a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284782543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.2284782543
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.3948095386
Short name T350
Test name
Test status
Simulation time 42752431 ps
CPU time 1.24 seconds
Started Jun 26 06:28:59 PM PDT 24
Finished Jun 26 06:29:01 PM PDT 24
Peak memory 219048 kb
Host smart-a9f9b91d-13b4-4f25-a5ff-233fd4d3ec3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948095386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3948095386
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.4119568532
Short name T307
Test name
Test status
Simulation time 41099152 ps
CPU time 1.14 seconds
Started Jun 26 06:29:09 PM PDT 24
Finished Jun 26 06:29:12 PM PDT 24
Peak memory 220300 kb
Host smart-c03480bd-ace4-445e-954c-dfe04dcdac10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119568532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.4119568532
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.1154979063
Short name T468
Test name
Test status
Simulation time 36561546 ps
CPU time 1.21 seconds
Started Jun 26 06:28:55 PM PDT 24
Finished Jun 26 06:28:58 PM PDT 24
Peak memory 219012 kb
Host smart-f8aa1ad7-44ce-4c2e-a69c-3975bb300ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154979063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1154979063
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.3838080156
Short name T509
Test name
Test status
Simulation time 39820621 ps
CPU time 1.49 seconds
Started Jun 26 06:29:13 PM PDT 24
Finished Jun 26 06:29:20 PM PDT 24
Peak memory 218772 kb
Host smart-7a66536c-6a75-4caf-a42a-013c15f65a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838080156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3838080156
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.2122211735
Short name T758
Test name
Test status
Simulation time 98340818 ps
CPU time 1.27 seconds
Started Jun 26 06:28:54 PM PDT 24
Finished Jun 26 06:28:58 PM PDT 24
Peak memory 218836 kb
Host smart-30104811-a65f-4f74-882a-0d1ce45182ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122211735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.2122211735
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1436161883
Short name T516
Test name
Test status
Simulation time 59143703 ps
CPU time 1.21 seconds
Started Jun 26 06:28:56 PM PDT 24
Finished Jun 26 06:28:58 PM PDT 24
Peak memory 217628 kb
Host smart-9cb46544-83c7-43df-ae85-cb15dd3a85e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436161883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1436161883
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.364505993
Short name T321
Test name
Test status
Simulation time 24456179 ps
CPU time 1.13 seconds
Started Jun 26 06:28:57 PM PDT 24
Finished Jun 26 06:29:00 PM PDT 24
Peak memory 220192 kb
Host smart-91cff9f4-b645-4553-9978-22b885198c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364505993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.364505993
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.74634471
Short name T742
Test name
Test status
Simulation time 24106379 ps
CPU time 1.28 seconds
Started Jun 26 06:29:00 PM PDT 24
Finished Jun 26 06:29:02 PM PDT 24
Peak memory 217628 kb
Host smart-fc251a9d-7303-4a28-936a-8d19d5f23942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74634471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.74634471
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.209657452
Short name T183
Test name
Test status
Simulation time 22955974 ps
CPU time 1.21 seconds
Started Jun 26 06:28:58 PM PDT 24
Finished Jun 26 06:29:01 PM PDT 24
Peak memory 220184 kb
Host smart-f0d616b2-b5a9-4429-9376-abb5afa1da65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209657452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.209657452
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.2630455725
Short name T768
Test name
Test status
Simulation time 37238452 ps
CPU time 1.41 seconds
Started Jun 26 06:28:54 PM PDT 24
Finished Jun 26 06:28:58 PM PDT 24
Peak memory 218868 kb
Host smart-8dad47a1-f52e-4975-acd0-9168d6bdc01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630455725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2630455725
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.2440903438
Short name T851
Test name
Test status
Simulation time 51112576 ps
CPU time 1.39 seconds
Started Jun 26 06:29:08 PM PDT 24
Finished Jun 26 06:29:12 PM PDT 24
Peak memory 216024 kb
Host smart-98e0832e-942f-431d-8c32-55d339db5173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440903438 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.2440903438
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.1102941825
Short name T581
Test name
Test status
Simulation time 59220526 ps
CPU time 1.25 seconds
Started Jun 26 06:29:04 PM PDT 24
Finished Jun 26 06:29:07 PM PDT 24
Peak memory 219264 kb
Host smart-9d5539fa-62bd-4290-94bd-5218f96dff4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102941825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1102941825
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.3853895748
Short name T813
Test name
Test status
Simulation time 27127029 ps
CPU time 1.22 seconds
Started Jun 26 06:28:52 PM PDT 24
Finished Jun 26 06:28:56 PM PDT 24
Peak memory 219848 kb
Host smart-5cdab8f4-5d57-48fb-96a6-20bc69712f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853895748 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.3853895748
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.110695479
Short name T952
Test name
Test status
Simulation time 33045991 ps
CPU time 1.26 seconds
Started Jun 26 06:29:13 PM PDT 24
Finished Jun 26 06:29:19 PM PDT 24
Peak memory 217696 kb
Host smart-6a56c0ea-1980-41bb-9b18-1983d4006290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110695479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.110695479
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.531971126
Short name T137
Test name
Test status
Simulation time 41893356 ps
CPU time 1.2 seconds
Started Jun 26 06:29:01 PM PDT 24
Finished Jun 26 06:29:03 PM PDT 24
Peak memory 219104 kb
Host smart-417ba8fc-154d-4e20-afa9-d9b78e93239f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531971126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.531971126
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.1833908948
Short name T302
Test name
Test status
Simulation time 39980133 ps
CPU time 1.71 seconds
Started Jun 26 06:28:57 PM PDT 24
Finished Jun 26 06:29:01 PM PDT 24
Peak memory 219032 kb
Host smart-79c30508-f7ec-4221-9108-dbaaf1c3a7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833908948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1833908948
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3815800873
Short name T107
Test name
Test status
Simulation time 22615767 ps
CPU time 1.15 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:23 PM PDT 24
Peak memory 219080 kb
Host smart-aaa8e7b2-0955-46d5-bda4-d9be5b819bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815800873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3815800873
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2291414509
Short name T899
Test name
Test status
Simulation time 14636183 ps
CPU time 0.95 seconds
Started Jun 26 06:27:24 PM PDT 24
Finished Jun 26 06:27:29 PM PDT 24
Peak memory 215532 kb
Host smart-a861fa52-ab9d-4ac2-bb58-1fbc52909e14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291414509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2291414509
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.419504386
Short name T566
Test name
Test status
Simulation time 25848353 ps
CPU time 0.86 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:23 PM PDT 24
Peak memory 215704 kb
Host smart-32855238-562a-49f5-96b6-8516f4216db0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419504386 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.419504386
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1061405201
Short name T761
Test name
Test status
Simulation time 87062328 ps
CPU time 1.07 seconds
Started Jun 26 06:27:19 PM PDT 24
Finished Jun 26 06:27:25 PM PDT 24
Peak memory 217172 kb
Host smart-3eece530-4853-4ffc-9288-1996986887e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061405201 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1061405201
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1346833999
Short name T111
Test name
Test status
Simulation time 24840352 ps
CPU time 1.13 seconds
Started Jun 26 06:27:28 PM PDT 24
Finished Jun 26 06:27:33 PM PDT 24
Peak memory 220876 kb
Host smart-36203824-8635-4694-b080-ff49bb1d6763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346833999 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1346833999
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.332899437
Short name T648
Test name
Test status
Simulation time 83585987 ps
CPU time 1.02 seconds
Started Jun 26 06:27:19 PM PDT 24
Finished Jun 26 06:27:25 PM PDT 24
Peak memory 217684 kb
Host smart-1943e004-8e76-4c63-86f3-e4116a3c0e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332899437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.332899437
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.203033863
Short name T29
Test name
Test status
Simulation time 36449159 ps
CPU time 1.03 seconds
Started Jun 26 06:27:16 PM PDT 24
Finished Jun 26 06:27:22 PM PDT 24
Peak memory 215956 kb
Host smart-feb674e3-887b-4079-b5d1-82d20125c9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203033863 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.203033863
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1028130766
Short name T898
Test name
Test status
Simulation time 43424125 ps
CPU time 0.93 seconds
Started Jun 26 06:27:28 PM PDT 24
Finished Jun 26 06:27:33 PM PDT 24
Peak memory 215580 kb
Host smart-e1e0f360-5646-4e8f-a593-1a2c00f8360d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028130766 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1028130766
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3976940523
Short name T505
Test name
Test status
Simulation time 33095556 ps
CPU time 0.94 seconds
Started Jun 26 06:27:28 PM PDT 24
Finished Jun 26 06:27:33 PM PDT 24
Peak memory 206780 kb
Host smart-7c668b2c-6793-499c-a795-a54edcb81d01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976940523 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3976940523
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.995708750
Short name T569
Test name
Test status
Simulation time 6002337350 ps
CPU time 147.1 seconds
Started Jun 26 06:27:15 PM PDT 24
Finished Jun 26 06:29:46 PM PDT 24
Peak memory 222072 kb
Host smart-26dca961-0e98-43d8-82f9-45876c56ee91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995708750 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.995708750
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.2129621698
Short name T322
Test name
Test status
Simulation time 65271068 ps
CPU time 1.2 seconds
Started Jun 26 06:29:12 PM PDT 24
Finished Jun 26 06:29:16 PM PDT 24
Peak memory 219120 kb
Host smart-b3565b20-4f1d-4e38-b192-7cce43f0a12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129621698 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.2129621698
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.4274312067
Short name T554
Test name
Test status
Simulation time 31653972 ps
CPU time 1.33 seconds
Started Jun 26 06:29:05 PM PDT 24
Finished Jun 26 06:29:08 PM PDT 24
Peak memory 220284 kb
Host smart-e7cdee59-0f99-4269-b343-3e9da973e97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274312067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.4274312067
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.2529968238
Short name T153
Test name
Test status
Simulation time 23778101 ps
CPU time 1.15 seconds
Started Jun 26 06:28:59 PM PDT 24
Finished Jun 26 06:29:01 PM PDT 24
Peak memory 219108 kb
Host smart-d0b34919-fd24-459f-b051-7aba4008f868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529968238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.2529968238
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.2297241059
Short name T680
Test name
Test status
Simulation time 44971516 ps
CPU time 1.27 seconds
Started Jun 26 06:29:14 PM PDT 24
Finished Jun 26 06:29:20 PM PDT 24
Peak memory 220436 kb
Host smart-62ee86a2-b489-49fc-8762-06cae1031caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297241059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2297241059
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.780894445
Short name T592
Test name
Test status
Simulation time 25832942 ps
CPU time 1.21 seconds
Started Jun 26 06:29:10 PM PDT 24
Finished Jun 26 06:29:12 PM PDT 24
Peak memory 220300 kb
Host smart-339c99c2-2190-478a-9993-32d47156d11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780894445 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.780894445
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/163.edn_alert.4156218620
Short name T886
Test name
Test status
Simulation time 68920857 ps
CPU time 1.29 seconds
Started Jun 26 06:29:01 PM PDT 24
Finished Jun 26 06:29:03 PM PDT 24
Peak memory 218836 kb
Host smart-04e74e84-d50f-4ab7-aa1d-43f670481e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156218620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.4156218620
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.2211738984
Short name T978
Test name
Test status
Simulation time 34364819 ps
CPU time 1.43 seconds
Started Jun 26 06:29:04 PM PDT 24
Finished Jun 26 06:29:06 PM PDT 24
Peak memory 220376 kb
Host smart-b7e93f8e-fdc5-423e-9d6f-87f3cf86d822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211738984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2211738984
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.1027128986
Short name T439
Test name
Test status
Simulation time 49938345 ps
CPU time 1.24 seconds
Started Jun 26 06:28:56 PM PDT 24
Finished Jun 26 06:28:59 PM PDT 24
Peak memory 216044 kb
Host smart-253be306-c96d-4fe2-bf2f-8a3ae0589c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027128986 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.1027128986
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.3088743790
Short name T876
Test name
Test status
Simulation time 65278432 ps
CPU time 1.3 seconds
Started Jun 26 06:29:02 PM PDT 24
Finished Jun 26 06:29:04 PM PDT 24
Peak memory 218972 kb
Host smart-073ad246-d903-4086-a1b6-9468af3f5337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088743790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3088743790
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.1407993947
Short name T323
Test name
Test status
Simulation time 78044990 ps
CPU time 1.13 seconds
Started Jun 26 06:29:13 PM PDT 24
Finished Jun 26 06:29:19 PM PDT 24
Peak memory 219108 kb
Host smart-d729470d-cd8a-437c-9e3d-fd55087383db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407993947 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.1407993947
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.3167890027
Short name T943
Test name
Test status
Simulation time 25660905 ps
CPU time 1.36 seconds
Started Jun 26 06:29:01 PM PDT 24
Finished Jun 26 06:29:03 PM PDT 24
Peak memory 219080 kb
Host smart-f9708c65-c198-41fc-947d-48a5961349bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167890027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3167890027
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.3358765502
Short name T923
Test name
Test status
Simulation time 97303051 ps
CPU time 1.26 seconds
Started Jun 26 06:28:57 PM PDT 24
Finished Jun 26 06:29:00 PM PDT 24
Peak memory 220152 kb
Host smart-ad29289b-5611-4584-ad55-335fc31f6964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358765502 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.3358765502
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.3056699160
Short name T641
Test name
Test status
Simulation time 97573423 ps
CPU time 1.34 seconds
Started Jun 26 06:29:11 PM PDT 24
Finished Jun 26 06:29:15 PM PDT 24
Peak memory 220368 kb
Host smart-4116c95c-2d2d-4d1e-80d6-a661b1ea7338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056699160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3056699160
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.3360593227
Short name T593
Test name
Test status
Simulation time 25538924 ps
CPU time 1.19 seconds
Started Jun 26 06:29:15 PM PDT 24
Finished Jun 26 06:29:21 PM PDT 24
Peak memory 220240 kb
Host smart-d6448cb5-5643-42cc-ade3-7d47d05626a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360593227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.3360593227
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.3149875282
Short name T733
Test name
Test status
Simulation time 54273703 ps
CPU time 1.83 seconds
Started Jun 26 06:29:06 PM PDT 24
Finished Jun 26 06:29:10 PM PDT 24
Peak memory 218688 kb
Host smart-0ee77da9-4c57-42a7-b60e-3e15074ff8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149875282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3149875282
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.1277863393
Short name T440
Test name
Test status
Simulation time 30681594 ps
CPU time 1.35 seconds
Started Jun 26 06:28:56 PM PDT 24
Finished Jun 26 06:28:59 PM PDT 24
Peak memory 215996 kb
Host smart-625016ec-9a4c-423d-bf0d-f712652d275a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277863393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.1277863393
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1024473530
Short name T445
Test name
Test status
Simulation time 41178629 ps
CPU time 1.53 seconds
Started Jun 26 06:28:54 PM PDT 24
Finished Jun 26 06:28:58 PM PDT 24
Peak memory 218844 kb
Host smart-61769d86-1951-40c9-a492-72a4431d8d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024473530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1024473530
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.2852168486
Short name T473
Test name
Test status
Simulation time 57792912 ps
CPU time 1.28 seconds
Started Jun 26 06:28:56 PM PDT 24
Finished Jun 26 06:28:59 PM PDT 24
Peak memory 215992 kb
Host smart-fa57c557-f3f4-417a-805e-cc02c5fe1e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852168486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2852168486
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.3661390979
Short name T95
Test name
Test status
Simulation time 38518051 ps
CPU time 1.28 seconds
Started Jun 26 06:29:03 PM PDT 24
Finished Jun 26 06:29:05 PM PDT 24
Peak memory 218848 kb
Host smart-0046d246-432b-489a-bffe-4c6c3fce981b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661390979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3661390979
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2825135848
Short name T453
Test name
Test status
Simulation time 25598098 ps
CPU time 1.26 seconds
Started Jun 26 06:27:24 PM PDT 24
Finished Jun 26 06:27:29 PM PDT 24
Peak memory 220204 kb
Host smart-1b41d39c-687e-48b7-9176-579f8088aac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825135848 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2825135848
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.4191113344
Short name T244
Test name
Test status
Simulation time 34124914 ps
CPU time 0.96 seconds
Started Jun 26 06:27:27 PM PDT 24
Finished Jun 26 06:27:32 PM PDT 24
Peak memory 207096 kb
Host smart-981c20fc-92e6-4636-ba8c-555d557f9fb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191113344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.4191113344
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3989374771
Short name T719
Test name
Test status
Simulation time 44974858 ps
CPU time 0.99 seconds
Started Jun 26 06:27:26 PM PDT 24
Finished Jun 26 06:27:31 PM PDT 24
Peak memory 219020 kb
Host smart-6a86c6cd-5038-4b77-aca4-b80f75b50c4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989374771 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3989374771
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.3420929171
Short name T195
Test name
Test status
Simulation time 32497053 ps
CPU time 0.92 seconds
Started Jun 26 06:27:23 PM PDT 24
Finished Jun 26 06:27:28 PM PDT 24
Peak memory 218504 kb
Host smart-090a6bc5-698e-4b06-9b10-f37b31a1d371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420929171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3420929171
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.648319992
Short name T469
Test name
Test status
Simulation time 85706090 ps
CPU time 1.49 seconds
Started Jun 26 06:27:37 PM PDT 24
Finished Jun 26 06:27:41 PM PDT 24
Peak memory 219180 kb
Host smart-47ed31e4-190a-411b-b1ea-ea8d0397bf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648319992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.648319992
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1280152322
Short name T108
Test name
Test status
Simulation time 21232862 ps
CPU time 1.17 seconds
Started Jun 26 06:27:24 PM PDT 24
Finished Jun 26 06:27:29 PM PDT 24
Peak memory 216268 kb
Host smart-0d212e57-2a29-480a-af81-c6f1a0736495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280152322 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1280152322
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1583396545
Short name T905
Test name
Test status
Simulation time 26951747 ps
CPU time 0.97 seconds
Started Jun 26 06:27:25 PM PDT 24
Finished Jun 26 06:27:30 PM PDT 24
Peak memory 215668 kb
Host smart-da6de368-e2f0-42b2-9387-d28958f99763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583396545 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1583396545
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.198122753
Short name T364
Test name
Test status
Simulation time 422423864 ps
CPU time 7.36 seconds
Started Jun 26 06:27:21 PM PDT 24
Finished Jun 26 06:27:33 PM PDT 24
Peak memory 215628 kb
Host smart-6f0a6033-5f9d-41e1-bfc7-9017d6a7bf17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198122753 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.198122753
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2104817366
Short name T398
Test name
Test status
Simulation time 301327852284 ps
CPU time 625.13 seconds
Started Jun 26 06:27:22 PM PDT 24
Finished Jun 26 06:37:52 PM PDT 24
Peak memory 230208 kb
Host smart-ce502995-3003-4965-ad96-53b59ed3b57f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104817366 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2104817366
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.3396719679
Short name T908
Test name
Test status
Simulation time 107149656 ps
CPU time 1.16 seconds
Started Jun 26 06:29:01 PM PDT 24
Finished Jun 26 06:29:03 PM PDT 24
Peak memory 219656 kb
Host smart-eedfebb3-5ebd-4b32-93de-e5379a530533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396719679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.3396719679
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.2573790568
Short name T575
Test name
Test status
Simulation time 74470043 ps
CPU time 2.68 seconds
Started Jun 26 06:28:57 PM PDT 24
Finished Jun 26 06:29:02 PM PDT 24
Peak memory 220704 kb
Host smart-3549eec3-5192-4ebb-a111-7a033daadfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573790568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2573790568
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.1016993338
Short name T625
Test name
Test status
Simulation time 26465371 ps
CPU time 1.23 seconds
Started Jun 26 06:29:06 PM PDT 24
Finished Jun 26 06:29:09 PM PDT 24
Peak memory 219900 kb
Host smart-1b0a0ea2-0817-480a-a80e-22d68df33225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016993338 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.1016993338
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.2807184686
Short name T982
Test name
Test status
Simulation time 153056983 ps
CPU time 1.43 seconds
Started Jun 26 06:29:07 PM PDT 24
Finished Jun 26 06:29:11 PM PDT 24
Peak memory 217664 kb
Host smart-ee68332b-5775-493e-9db9-b8b85fdfae3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807184686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2807184686
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.3635245025
Short name T934
Test name
Test status
Simulation time 60976002 ps
CPU time 1.23 seconds
Started Jun 26 06:29:17 PM PDT 24
Finished Jun 26 06:29:23 PM PDT 24
Peak memory 216048 kb
Host smart-d8e18213-920b-4c6b-8b2c-4e2bd2d1713e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635245025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.3635245025
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.987556754
Short name T392
Test name
Test status
Simulation time 98761799 ps
CPU time 1.34 seconds
Started Jun 26 06:29:05 PM PDT 24
Finished Jun 26 06:29:09 PM PDT 24
Peak memory 219616 kb
Host smart-80945f2e-a3f4-417b-a400-fec45edd2d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987556754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.987556754
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.2428319071
Short name T754
Test name
Test status
Simulation time 48542234 ps
CPU time 1.24 seconds
Started Jun 26 06:29:05 PM PDT 24
Finished Jun 26 06:29:09 PM PDT 24
Peak memory 220348 kb
Host smart-30de68d1-b7d2-4cbb-a329-3110dc3629de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428319071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.2428319071
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.3896416225
Short name T747
Test name
Test status
Simulation time 57493072 ps
CPU time 1.3 seconds
Started Jun 26 06:29:17 PM PDT 24
Finished Jun 26 06:29:23 PM PDT 24
Peak memory 217708 kb
Host smart-b5567c9c-6dea-4696-8874-54c24ab12cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896416225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3896416225
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.3887400986
Short name T574
Test name
Test status
Simulation time 69861549 ps
CPU time 1.2 seconds
Started Jun 26 06:29:06 PM PDT 24
Finished Jun 26 06:29:09 PM PDT 24
Peak memory 220320 kb
Host smart-32794c01-263c-4877-b5c0-a78d45efd6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887400986 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.3887400986
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.728960662
Short name T824
Test name
Test status
Simulation time 35940566 ps
CPU time 1.39 seconds
Started Jun 26 06:29:02 PM PDT 24
Finished Jun 26 06:29:04 PM PDT 24
Peak memory 219892 kb
Host smart-88466923-2d65-43c8-bbec-ddff9f89e2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728960662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.728960662
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.1075824316
Short name T220
Test name
Test status
Simulation time 72641357 ps
CPU time 1.12 seconds
Started Jun 26 06:29:04 PM PDT 24
Finished Jun 26 06:29:07 PM PDT 24
Peak memory 219396 kb
Host smart-956d043a-cefb-4feb-a1ab-0ee663978dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075824316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.1075824316
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.4237197658
Short name T704
Test name
Test status
Simulation time 66808883 ps
CPU time 1.34 seconds
Started Jun 26 06:29:05 PM PDT 24
Finished Jun 26 06:29:09 PM PDT 24
Peak memory 219456 kb
Host smart-c1c64752-cca4-4dbd-ba6e-cb6006b8bccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237197658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.4237197658
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.3276335215
Short name T88
Test name
Test status
Simulation time 77093628 ps
CPU time 1.14 seconds
Started Jun 26 06:29:07 PM PDT 24
Finished Jun 26 06:29:10 PM PDT 24
Peak memory 219896 kb
Host smart-74340fe2-c51d-4042-9c96-16a3bb9aaef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276335215 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.3276335215
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.1201886967
Short name T881
Test name
Test status
Simulation time 249796577 ps
CPU time 1.21 seconds
Started Jun 26 06:29:10 PM PDT 24
Finished Jun 26 06:29:13 PM PDT 24
Peak memory 217648 kb
Host smart-ebed1be3-1191-4578-a14f-3bfc6930696c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201886967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1201886967
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.719594081
Short name T863
Test name
Test status
Simulation time 25449961 ps
CPU time 1.16 seconds
Started Jun 26 06:29:17 PM PDT 24
Finished Jun 26 06:29:22 PM PDT 24
Peak memory 220164 kb
Host smart-9d2f643f-5d22-42aa-99e0-be915f98b382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719594081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.719594081
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.1727230462
Short name T706
Test name
Test status
Simulation time 79584361 ps
CPU time 2.26 seconds
Started Jun 26 06:29:13 PM PDT 24
Finished Jun 26 06:29:20 PM PDT 24
Peak memory 220556 kb
Host smart-e70b9f09-74ac-4b28-9535-1fc4300f8085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727230462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1727230462
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.2538915465
Short name T664
Test name
Test status
Simulation time 35732244 ps
CPU time 1.28 seconds
Started Jun 26 06:29:14 PM PDT 24
Finished Jun 26 06:29:20 PM PDT 24
Peak memory 220052 kb
Host smart-926e02f4-929c-4934-958c-29f9240812b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538915465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.2538915465
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.1446981187
Short name T993
Test name
Test status
Simulation time 101134519 ps
CPU time 1.72 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:37 PM PDT 24
Peak memory 219064 kb
Host smart-cf23e14e-9ca5-49de-b426-979a7db9e121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446981187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1446981187
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.801353968
Short name T386
Test name
Test status
Simulation time 322635536 ps
CPU time 1.25 seconds
Started Jun 26 06:27:36 PM PDT 24
Finished Jun 26 06:27:40 PM PDT 24
Peak memory 219884 kb
Host smart-fbbd7121-0c2e-4a2c-890a-82fb9f776e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801353968 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.801353968
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.204030410
Short name T960
Test name
Test status
Simulation time 18261168 ps
CPU time 1 seconds
Started Jun 26 06:27:27 PM PDT 24
Finished Jun 26 06:27:31 PM PDT 24
Peak memory 207084 kb
Host smart-6ee1f8f1-0c0b-4372-8f91-a560709c7aea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204030410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.204030410
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2756210352
Short name T523
Test name
Test status
Simulation time 27189021 ps
CPU time 0.83 seconds
Started Jun 26 06:27:26 PM PDT 24
Finished Jun 26 06:27:31 PM PDT 24
Peak memory 216588 kb
Host smart-dedd15f0-2737-4ed3-b2a4-0552055ef3c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756210352 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2756210352
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2002695630
Short name T450
Test name
Test status
Simulation time 115732861 ps
CPU time 1.1 seconds
Started Jun 26 06:27:25 PM PDT 24
Finished Jun 26 06:27:30 PM PDT 24
Peak memory 218672 kb
Host smart-5fd90563-080e-4c7b-aa73-bc50144550db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002695630 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2002695630
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2838281232
Short name T665
Test name
Test status
Simulation time 49415639 ps
CPU time 1.07 seconds
Started Jun 26 06:27:38 PM PDT 24
Finished Jun 26 06:27:42 PM PDT 24
Peak memory 220120 kb
Host smart-54b64c1a-a629-4328-9d98-3e809a8f4089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838281232 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2838281232
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.887286774
Short name T760
Test name
Test status
Simulation time 20309136 ps
CPU time 1.01 seconds
Started Jun 26 06:27:22 PM PDT 24
Finished Jun 26 06:27:28 PM PDT 24
Peak memory 220056 kb
Host smart-12d372fc-f782-41d9-927f-47493c47780d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887286774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.887286774
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2142288865
Short name T436
Test name
Test status
Simulation time 20270031 ps
CPU time 1.11 seconds
Started Jun 26 06:27:38 PM PDT 24
Finished Jun 26 06:27:42 PM PDT 24
Peak memory 215704 kb
Host smart-d67cc04d-dacd-4c48-9be7-d96974aaccdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142288865 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2142288865
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1660995483
Short name T589
Test name
Test status
Simulation time 25931318 ps
CPU time 0.92 seconds
Started Jun 26 06:27:37 PM PDT 24
Finished Jun 26 06:27:40 PM PDT 24
Peak memory 215340 kb
Host smart-047cff76-d088-449f-a806-5ea0b3e6586c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660995483 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1660995483
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1276246058
Short name T716
Test name
Test status
Simulation time 205661001 ps
CPU time 1.57 seconds
Started Jun 26 06:27:22 PM PDT 24
Finished Jun 26 06:27:29 PM PDT 24
Peak memory 207496 kb
Host smart-a4101275-12b7-47de-aa41-12c9b9861d8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276246058 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1276246058
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1678553644
Short name T429
Test name
Test status
Simulation time 110041487896 ps
CPU time 471.15 seconds
Started Jun 26 06:27:25 PM PDT 24
Finished Jun 26 06:35:20 PM PDT 24
Peak memory 220152 kb
Host smart-42f9b232-201a-47b4-bff2-0fd9c1c4255d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678553644 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1678553644
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.2044240388
Short name T739
Test name
Test status
Simulation time 87050298 ps
CPU time 1.16 seconds
Started Jun 26 06:29:14 PM PDT 24
Finished Jun 26 06:29:20 PM PDT 24
Peak memory 219212 kb
Host smart-ae669f30-c2d7-4df2-9ca2-93a680b19395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044240388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.2044240388
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.3470505356
Short name T725
Test name
Test status
Simulation time 69762376 ps
CPU time 1.21 seconds
Started Jun 26 06:29:05 PM PDT 24
Finished Jun 26 06:29:08 PM PDT 24
Peak memory 219380 kb
Host smart-d391ecf1-533f-4b83-af2e-3878de1f2d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470505356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3470505356
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.1648838615
Short name T821
Test name
Test status
Simulation time 32315022 ps
CPU time 1.16 seconds
Started Jun 26 06:29:16 PM PDT 24
Finished Jun 26 06:29:22 PM PDT 24
Peak memory 220888 kb
Host smart-c62cb6ca-0784-4c41-8d63-1cf168f2fedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648838615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.1648838615
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.408970147
Short name T294
Test name
Test status
Simulation time 80701962 ps
CPU time 1.26 seconds
Started Jun 26 06:29:15 PM PDT 24
Finished Jun 26 06:29:21 PM PDT 24
Peak memory 219376 kb
Host smart-217546fd-c14f-4eea-9857-16198670dd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408970147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.408970147
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.2443520471
Short name T649
Test name
Test status
Simulation time 40581084 ps
CPU time 1.13 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:37 PM PDT 24
Peak memory 219168 kb
Host smart-ebbdca96-6055-437e-aa71-c72b995b216f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443520471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2443520471
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.1657335780
Short name T2
Test name
Test status
Simulation time 108202380 ps
CPU time 1.38 seconds
Started Jun 26 06:29:10 PM PDT 24
Finished Jun 26 06:29:13 PM PDT 24
Peak memory 219420 kb
Host smart-ca65ea53-1af8-4717-b001-4a64a6ed89c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657335780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1657335780
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.168875807
Short name T924
Test name
Test status
Simulation time 63817817 ps
CPU time 1.1 seconds
Started Jun 26 06:29:18 PM PDT 24
Finished Jun 26 06:29:23 PM PDT 24
Peak memory 220632 kb
Host smart-9de42903-bf26-45ba-beac-7e794319a9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168875807 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.168875807
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.3881397826
Short name T513
Test name
Test status
Simulation time 92423341 ps
CPU time 1.71 seconds
Started Jun 26 06:29:19 PM PDT 24
Finished Jun 26 06:29:25 PM PDT 24
Peak memory 218876 kb
Host smart-4f732401-b792-4b40-ac5a-9afe3cfc17a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881397826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3881397826
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.2013471544
Short name T585
Test name
Test status
Simulation time 123922622 ps
CPU time 1.24 seconds
Started Jun 26 06:29:15 PM PDT 24
Finished Jun 26 06:29:21 PM PDT 24
Peak memory 218816 kb
Host smart-cdc4b383-26a9-4beb-b17d-ed3afcad011f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013471544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.2013471544
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.1486593054
Short name T944
Test name
Test status
Simulation time 40942545 ps
CPU time 1.15 seconds
Started Jun 26 06:29:19 PM PDT 24
Finished Jun 26 06:29:24 PM PDT 24
Peak memory 217932 kb
Host smart-a56aa4ce-a073-4d9c-aa25-f7d20e1517a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486593054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1486593054
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.2428860948
Short name T89
Test name
Test status
Simulation time 34165503 ps
CPU time 1.22 seconds
Started Jun 26 06:29:13 PM PDT 24
Finished Jun 26 06:29:19 PM PDT 24
Peak memory 220268 kb
Host smart-937abe4e-8bd0-4921-a3b8-b20f9ff4aa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428860948 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.2428860948
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.210126570
Short name T610
Test name
Test status
Simulation time 132076581 ps
CPU time 1.48 seconds
Started Jun 26 06:29:22 PM PDT 24
Finished Jun 26 06:29:27 PM PDT 24
Peak memory 217604 kb
Host smart-ad33f092-b6ee-4670-a5e9-e9f4f5fe7a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210126570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.210126570
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.999383284
Short name T611
Test name
Test status
Simulation time 44348883 ps
CPU time 1.21 seconds
Started Jun 26 06:29:06 PM PDT 24
Finished Jun 26 06:29:09 PM PDT 24
Peak memory 219420 kb
Host smart-09d165eb-1e64-4138-ad47-a5251caf92b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999383284 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.999383284
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.2565215090
Short name T633
Test name
Test status
Simulation time 70004209 ps
CPU time 1.26 seconds
Started Jun 26 06:29:07 PM PDT 24
Finished Jun 26 06:29:10 PM PDT 24
Peak memory 217780 kb
Host smart-d15bc12d-4080-43a1-89d5-f156707291c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565215090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2565215090
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.214563784
Short name T736
Test name
Test status
Simulation time 29807416 ps
CPU time 1.36 seconds
Started Jun 26 06:29:15 PM PDT 24
Finished Jun 26 06:29:22 PM PDT 24
Peak memory 221216 kb
Host smart-0e0e2ac4-dd4b-4a57-ba29-29b239033180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214563784 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.214563784
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.728566106
Short name T726
Test name
Test status
Simulation time 60261596 ps
CPU time 1.58 seconds
Started Jun 26 06:29:21 PM PDT 24
Finished Jun 26 06:29:27 PM PDT 24
Peak memory 218960 kb
Host smart-a556c156-b561-4d24-b8f6-be6f875cca29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728566106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.728566106
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.2860920523
Short name T314
Test name
Test status
Simulation time 40720932 ps
CPU time 1.16 seconds
Started Jun 26 06:29:24 PM PDT 24
Finished Jun 26 06:29:29 PM PDT 24
Peak memory 219168 kb
Host smart-e8aaf1d4-6586-47ef-8211-3f6c08da4928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860920523 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2860920523
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.522762062
Short name T788
Test name
Test status
Simulation time 42842130 ps
CPU time 1.43 seconds
Started Jun 26 06:29:10 PM PDT 24
Finished Jun 26 06:29:13 PM PDT 24
Peak memory 220324 kb
Host smart-5705eb1a-9d92-42f5-943b-b4d6cd4b1742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522762062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.522762062
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.581949446
Short name T799
Test name
Test status
Simulation time 49298948 ps
CPU time 1.23 seconds
Started Jun 26 06:29:04 PM PDT 24
Finished Jun 26 06:29:08 PM PDT 24
Peak memory 220048 kb
Host smart-e534459f-f862-431e-82b7-dd37c05330ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581949446 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.581949446
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.355257486
Short name T961
Test name
Test status
Simulation time 253734960 ps
CPU time 1.17 seconds
Started Jun 26 06:29:04 PM PDT 24
Finished Jun 26 06:29:07 PM PDT 24
Peak memory 219144 kb
Host smart-1b6518ae-d2a4-4deb-946b-d51d325f311e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355257486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.355257486
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2068505891
Short name T862
Test name
Test status
Simulation time 25074439 ps
CPU time 1.16 seconds
Started Jun 26 06:27:52 PM PDT 24
Finished Jun 26 06:27:54 PM PDT 24
Peak memory 220208 kb
Host smart-226fc13b-e646-4f58-a69c-8dc2b066a3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068505891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2068505891
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.185625233
Short name T103
Test name
Test status
Simulation time 48095062 ps
CPU time 0.89 seconds
Started Jun 26 06:27:24 PM PDT 24
Finished Jun 26 06:27:29 PM PDT 24
Peak memory 215256 kb
Host smart-cdce376b-77c3-4406-9ece-4987c4496be1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185625233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.185625233
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.3350444489
Short name T630
Test name
Test status
Simulation time 15906233 ps
CPU time 0.84 seconds
Started Jun 26 06:27:36 PM PDT 24
Finished Jun 26 06:27:40 PM PDT 24
Peak memory 216280 kb
Host smart-5edafef9-74d5-46f2-a80d-abadf0f0eb60
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350444489 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3350444489
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2965656808
Short name T117
Test name
Test status
Simulation time 38928445 ps
CPU time 1.28 seconds
Started Jun 26 06:27:29 PM PDT 24
Finished Jun 26 06:27:34 PM PDT 24
Peak memory 217104 kb
Host smart-130a37d6-36b6-4fa0-b19f-fafa1922fcb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965656808 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2965656808
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.539111570
Short name T560
Test name
Test status
Simulation time 104314185 ps
CPU time 1.06 seconds
Started Jun 26 06:27:37 PM PDT 24
Finished Jun 26 06:27:40 PM PDT 24
Peak memory 219996 kb
Host smart-3509fa69-6634-4431-8d4f-65cc6d87d355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539111570 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.539111570
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.410118974
Short name T586
Test name
Test status
Simulation time 194268463 ps
CPU time 1.48 seconds
Started Jun 26 06:27:37 PM PDT 24
Finished Jun 26 06:27:41 PM PDT 24
Peak memory 218888 kb
Host smart-9bb1a932-5b42-4deb-b448-211a49527e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410118974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.410118974
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3886844415
Short name T829
Test name
Test status
Simulation time 22229698 ps
CPU time 1.07 seconds
Started Jun 26 06:27:29 PM PDT 24
Finished Jun 26 06:27:33 PM PDT 24
Peak memory 215768 kb
Host smart-afb852cb-7027-48f6-b9d5-d957f0802eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886844415 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3886844415
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.15402042
Short name T375
Test name
Test status
Simulation time 24753374 ps
CPU time 0.93 seconds
Started Jun 26 06:27:36 PM PDT 24
Finished Jun 26 06:27:39 PM PDT 24
Peak memory 215476 kb
Host smart-8df03109-b6cd-45a5-9b83-df01036c5ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15402042 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.15402042
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1258715248
Short name T717
Test name
Test status
Simulation time 265078343 ps
CPU time 5.28 seconds
Started Jun 26 06:27:28 PM PDT 24
Finished Jun 26 06:27:37 PM PDT 24
Peak memory 217456 kb
Host smart-f4789e90-1adc-4c96-9aba-9455a7587d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258715248 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1258715248
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/190.edn_alert.4172515055
Short name T415
Test name
Test status
Simulation time 271073386 ps
CPU time 1.28 seconds
Started Jun 26 06:29:08 PM PDT 24
Finished Jun 26 06:29:12 PM PDT 24
Peak memory 218884 kb
Host smart-d994703d-9d1a-49b9-81e3-3c12a80ca277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172515055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.4172515055
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.1402133071
Short name T295
Test name
Test status
Simulation time 200075955 ps
CPU time 2.84 seconds
Started Jun 26 06:29:05 PM PDT 24
Finished Jun 26 06:29:10 PM PDT 24
Peak memory 218908 kb
Host smart-f484fe4c-8e7a-4eeb-8fa0-3ebce855465c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402133071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1402133071
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.1645092944
Short name T171
Test name
Test status
Simulation time 243979274 ps
CPU time 1.2 seconds
Started Jun 26 06:29:07 PM PDT 24
Finished Jun 26 06:29:10 PM PDT 24
Peak memory 219788 kb
Host smart-0805aa5f-d5d1-4f26-9090-f94fcc396c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645092944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.1645092944
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.2386118381
Short name T713
Test name
Test status
Simulation time 56085895 ps
CPU time 1.96 seconds
Started Jun 26 06:29:05 PM PDT 24
Finished Jun 26 06:29:09 PM PDT 24
Peak memory 218832 kb
Host smart-70c0ab99-ac22-426f-85f2-4b92686abf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386118381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2386118381
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.3881114530
Short name T154
Test name
Test status
Simulation time 70886967 ps
CPU time 1.12 seconds
Started Jun 26 06:29:10 PM PDT 24
Finished Jun 26 06:29:13 PM PDT 24
Peak memory 220348 kb
Host smart-d20c9f0e-2214-4361-a86c-78bd95b54d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881114530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3881114530
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.1379561441
Short name T931
Test name
Test status
Simulation time 38929313 ps
CPU time 1.39 seconds
Started Jun 26 06:29:04 PM PDT 24
Finished Jun 26 06:29:07 PM PDT 24
Peak memory 218724 kb
Host smart-0870fbab-af6e-438f-b78b-7e9c8f35f98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379561441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1379561441
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.2436739903
Short name T318
Test name
Test status
Simulation time 39635038 ps
CPU time 1.16 seconds
Started Jun 26 06:29:14 PM PDT 24
Finished Jun 26 06:29:20 PM PDT 24
Peak memory 220160 kb
Host smart-9e0e0b27-dfac-450c-8a38-13640a1a3b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436739903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.2436739903
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.3287540212
Short name T727
Test name
Test status
Simulation time 69461382 ps
CPU time 1.15 seconds
Started Jun 26 06:29:21 PM PDT 24
Finished Jun 26 06:29:26 PM PDT 24
Peak memory 217572 kb
Host smart-f1e4f82b-7d71-43e2-a3c0-2b0738dc1e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287540212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3287540212
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.1115056148
Short name T192
Test name
Test status
Simulation time 63869305 ps
CPU time 1.17 seconds
Started Jun 26 06:29:22 PM PDT 24
Finished Jun 26 06:29:26 PM PDT 24
Peak memory 219652 kb
Host smart-3a6890fb-a72b-458a-9560-016b575356db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115056148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.1115056148
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.176878498
Short name T380
Test name
Test status
Simulation time 63046780 ps
CPU time 1.4 seconds
Started Jun 26 06:29:10 PM PDT 24
Finished Jun 26 06:29:13 PM PDT 24
Peak memory 220280 kb
Host smart-04e74911-292a-4229-ba14-edf1308dc2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176878498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.176878498
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.2914540450
Short name T240
Test name
Test status
Simulation time 283068303 ps
CPU time 1.13 seconds
Started Jun 26 06:29:16 PM PDT 24
Finished Jun 26 06:29:22 PM PDT 24
Peak memory 219004 kb
Host smart-a062be9e-15d1-4b88-9294-ad15b430e6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914540450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2914540450
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.674250627
Short name T346
Test name
Test status
Simulation time 50812615 ps
CPU time 1.31 seconds
Started Jun 26 06:29:26 PM PDT 24
Finished Jun 26 06:29:33 PM PDT 24
Peak memory 217672 kb
Host smart-0553107e-1d1d-4c22-89fc-0a39ef82863f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674250627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.674250627
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.4119555561
Short name T374
Test name
Test status
Simulation time 80667698 ps
CPU time 1.23 seconds
Started Jun 26 06:29:21 PM PDT 24
Finished Jun 26 06:29:26 PM PDT 24
Peak memory 218920 kb
Host smart-211cd0a6-0ba8-4a79-a3e2-97aeda401452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119555561 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.4119555561
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.2413314090
Short name T682
Test name
Test status
Simulation time 50902900 ps
CPU time 1.74 seconds
Started Jun 26 06:29:19 PM PDT 24
Finished Jun 26 06:29:25 PM PDT 24
Peak memory 219092 kb
Host smart-de807ae3-c724-46fc-aad8-a0a2c69366ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413314090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2413314090
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.3016373584
Short name T48
Test name
Test status
Simulation time 28155484 ps
CPU time 1.27 seconds
Started Jun 26 06:29:19 PM PDT 24
Finished Jun 26 06:29:25 PM PDT 24
Peak memory 219688 kb
Host smart-e6e163d1-2a17-4b09-9c18-c2687be28738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016373584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3016373584
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.4085413529
Short name T570
Test name
Test status
Simulation time 64757738 ps
CPU time 1.38 seconds
Started Jun 26 06:29:17 PM PDT 24
Finished Jun 26 06:29:23 PM PDT 24
Peak memory 217836 kb
Host smart-051cac23-215e-4617-a4de-876ff35db1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085413529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.4085413529
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.1739461040
Short name T798
Test name
Test status
Simulation time 102127825 ps
CPU time 1.69 seconds
Started Jun 26 06:29:15 PM PDT 24
Finished Jun 26 06:29:22 PM PDT 24
Peak memory 218612 kb
Host smart-583af112-fcaa-431a-b123-9debbd4f78ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739461040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1739461040
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.2462011108
Short name T903
Test name
Test status
Simulation time 221802350 ps
CPU time 1.35 seconds
Started Jun 26 06:29:19 PM PDT 24
Finished Jun 26 06:29:24 PM PDT 24
Peak memory 221040 kb
Host smart-ff751b2f-6041-4204-a9de-59debae559af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462011108 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.2462011108
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.1660829635
Short name T476
Test name
Test status
Simulation time 39311109 ps
CPU time 1.53 seconds
Started Jun 26 06:29:26 PM PDT 24
Finished Jun 26 06:29:33 PM PDT 24
Peak memory 216768 kb
Host smart-3e678b37-d75f-46fd-8813-9b42acf46546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660829635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1660829635
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.6991327
Short name T711
Test name
Test status
Simulation time 48627586 ps
CPU time 1.21 seconds
Started Jun 26 06:26:52 PM PDT 24
Finished Jun 26 06:26:55 PM PDT 24
Peak memory 220428 kb
Host smart-57bd7510-4ca3-413d-ab54-f4bff419c290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6991327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.6991327
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2698198440
Short name T938
Test name
Test status
Simulation time 56076977 ps
CPU time 0.95 seconds
Started Jun 26 06:26:56 PM PDT 24
Finished Jun 26 06:26:59 PM PDT 24
Peak memory 207040 kb
Host smart-f2ffe3ce-7265-48ce-b201-fe9becb93c59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698198440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2698198440
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1694068077
Short name T537
Test name
Test status
Simulation time 38234833 ps
CPU time 0.82 seconds
Started Jun 26 06:26:56 PM PDT 24
Finished Jun 26 06:26:58 PM PDT 24
Peak memory 216560 kb
Host smart-df3c7c01-3edc-4dfb-a27a-0febe8f857ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694068077 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1694068077
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1731207357
Short name T271
Test name
Test status
Simulation time 50357777 ps
CPU time 0.99 seconds
Started Jun 26 06:26:55 PM PDT 24
Finished Jun 26 06:26:58 PM PDT 24
Peak memory 218784 kb
Host smart-d41a5491-8d4f-4b46-8852-948791b0e2b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731207357 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1731207357
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1371798896
Short name T175
Test name
Test status
Simulation time 27342917 ps
CPU time 0.93 seconds
Started Jun 26 06:26:53 PM PDT 24
Finished Jun 26 06:26:55 PM PDT 24
Peak memory 224068 kb
Host smart-b00b482b-9229-4914-9885-03d48d73e536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371798896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1371798896
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1539878264
Short name T381
Test name
Test status
Simulation time 68639788 ps
CPU time 1.03 seconds
Started Jun 26 06:26:53 PM PDT 24
Finished Jun 26 06:26:56 PM PDT 24
Peak memory 217608 kb
Host smart-c75a810d-3fcc-41ec-ae31-55b3fa718d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539878264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1539878264
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.794946115
Short name T791
Test name
Test status
Simulation time 33086776 ps
CPU time 0.89 seconds
Started Jun 26 06:26:54 PM PDT 24
Finished Jun 26 06:26:57 PM PDT 24
Peak memory 215632 kb
Host smart-aae0d389-8958-47c3-8d18-714ebabe4a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794946115 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.794946115
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.1265850388
Short name T769
Test name
Test status
Simulation time 26831138 ps
CPU time 0.96 seconds
Started Jun 26 06:26:56 PM PDT 24
Finished Jun 26 06:26:58 PM PDT 24
Peak memory 207444 kb
Host smart-e47d7cad-bd20-45d5-b045-44fec0932143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265850388 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1265850388
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.4061866071
Short name T332
Test name
Test status
Simulation time 21565885 ps
CPU time 1.02 seconds
Started Jun 26 06:26:54 PM PDT 24
Finished Jun 26 06:26:56 PM PDT 24
Peak memory 215668 kb
Host smart-019552c4-e19b-4287-ad8b-dd6a913d6c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061866071 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.4061866071
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.318602170
Short name T774
Test name
Test status
Simulation time 589220293 ps
CPU time 3.56 seconds
Started Jun 26 06:26:54 PM PDT 24
Finished Jun 26 06:26:59 PM PDT 24
Peak memory 217572 kb
Host smart-98492ef6-d98b-461c-95eb-00d579b82402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318602170 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.318602170
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1874196223
Short name T490
Test name
Test status
Simulation time 15433975782 ps
CPU time 348.53 seconds
Started Jun 26 06:26:56 PM PDT 24
Finished Jun 26 06:32:47 PM PDT 24
Peak memory 223412 kb
Host smart-d841ab4f-4449-46e5-b342-41b16fadf8cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874196223 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1874196223
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3746911995
Short name T524
Test name
Test status
Simulation time 116971968 ps
CPU time 1.15 seconds
Started Jun 26 06:27:25 PM PDT 24
Finished Jun 26 06:27:31 PM PDT 24
Peak memory 219020 kb
Host smart-aadacafc-260d-4551-a9b8-e11d280ae271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746911995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3746911995
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3703668951
Short name T361
Test name
Test status
Simulation time 19575829 ps
CPU time 0.99 seconds
Started Jun 26 06:27:26 PM PDT 24
Finished Jun 26 06:27:31 PM PDT 24
Peak memory 215244 kb
Host smart-9420b9ab-49fc-41dd-9018-c28a709b5a96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703668951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3703668951
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.2461365859
Short name T872
Test name
Test status
Simulation time 12306292 ps
CPU time 0.9 seconds
Started Jun 26 06:27:23 PM PDT 24
Finished Jun 26 06:27:28 PM PDT 24
Peak memory 216876 kb
Host smart-7f489ba0-52a1-4717-bc32-f28051ea05fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461365859 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2461365859
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1763458076
Short name T556
Test name
Test status
Simulation time 58124443 ps
CPU time 1.17 seconds
Started Jun 26 06:27:21 PM PDT 24
Finished Jun 26 06:27:27 PM PDT 24
Peak memory 217448 kb
Host smart-df2941cf-bed2-4cb1-af76-b921549e7c39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763458076 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1763458076
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.332976533
Short name T767
Test name
Test status
Simulation time 50314960 ps
CPU time 1.02 seconds
Started Jun 26 06:27:37 PM PDT 24
Finished Jun 26 06:27:40 PM PDT 24
Peak memory 218480 kb
Host smart-fda39051-fa3a-4e81-9106-8a3dd573e781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332976533 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.332976533
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2781835501
Short name T40
Test name
Test status
Simulation time 35538857 ps
CPU time 1.33 seconds
Started Jun 26 06:27:25 PM PDT 24
Finished Jun 26 06:27:30 PM PDT 24
Peak memory 218892 kb
Host smart-a02c40c3-9e6d-465a-87bc-1de06b9e9b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781835501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2781835501
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.573428869
Short name T854
Test name
Test status
Simulation time 22487834 ps
CPU time 1.17 seconds
Started Jun 26 06:27:39 PM PDT 24
Finished Jun 26 06:27:42 PM PDT 24
Peak memory 224288 kb
Host smart-b8a25841-993c-49dc-80f6-0c1d9f7cdf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573428869 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.573428869
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3174612749
Short name T477
Test name
Test status
Simulation time 245787689 ps
CPU time 0.94 seconds
Started Jun 26 06:27:23 PM PDT 24
Finished Jun 26 06:27:28 PM PDT 24
Peak memory 215596 kb
Host smart-fe48d19a-becd-4591-9812-308810fe7ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174612749 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3174612749
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1975295096
Short name T357
Test name
Test status
Simulation time 2080670930 ps
CPU time 5.04 seconds
Started Jun 26 06:27:24 PM PDT 24
Finished Jun 26 06:27:33 PM PDT 24
Peak memory 217720 kb
Host smart-c18862ac-a095-482b-b0d1-6a9c09c48803
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975295096 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1975295096
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/200.edn_genbits.3730665760
Short name T953
Test name
Test status
Simulation time 27066657 ps
CPU time 1.24 seconds
Started Jun 26 06:29:13 PM PDT 24
Finished Jun 26 06:29:19 PM PDT 24
Peak memory 217608 kb
Host smart-2861dd96-038e-4b9c-a935-60e87e5a4c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730665760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3730665760
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1075059029
Short name T431
Test name
Test status
Simulation time 33985346 ps
CPU time 1.33 seconds
Started Jun 26 06:29:17 PM PDT 24
Finished Jun 26 06:29:23 PM PDT 24
Peak memory 219172 kb
Host smart-9a6f99bc-457c-461d-9a00-a73469ab281a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075059029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1075059029
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1137938558
Short name T359
Test name
Test status
Simulation time 27974442 ps
CPU time 1.18 seconds
Started Jun 26 06:29:14 PM PDT 24
Finished Jun 26 06:29:20 PM PDT 24
Peak memory 217584 kb
Host smart-f88c67ea-cde4-4745-ae58-5a452ed5aec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137938558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1137938558
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2949629021
Short name T457
Test name
Test status
Simulation time 111683276 ps
CPU time 1.57 seconds
Started Jun 26 06:29:22 PM PDT 24
Finished Jun 26 06:29:27 PM PDT 24
Peak memory 220280 kb
Host smart-e97d19d5-694b-4e07-91d8-90a5586f870a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949629021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2949629021
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.625752465
Short name T676
Test name
Test status
Simulation time 50745359 ps
CPU time 1.61 seconds
Started Jun 26 06:29:13 PM PDT 24
Finished Jun 26 06:29:20 PM PDT 24
Peak memory 218928 kb
Host smart-3fc1a772-f1e8-4331-a2fb-030a9d17d57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625752465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.625752465
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3198595244
Short name T309
Test name
Test status
Simulation time 45003629 ps
CPU time 1.65 seconds
Started Jun 26 06:29:09 PM PDT 24
Finished Jun 26 06:29:13 PM PDT 24
Peak memory 217604 kb
Host smart-bc22a588-9d04-4b5f-83e9-fddad7a1eac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198595244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3198595244
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.591621895
Short name T528
Test name
Test status
Simulation time 53616607 ps
CPU time 1.31 seconds
Started Jun 26 06:29:16 PM PDT 24
Finished Jun 26 06:29:23 PM PDT 24
Peak memory 220296 kb
Host smart-eb49bd92-f5d2-45a8-be28-e2b665c42f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591621895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.591621895
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.458857772
Short name T916
Test name
Test status
Simulation time 91259169 ps
CPU time 1.21 seconds
Started Jun 26 06:29:11 PM PDT 24
Finished Jun 26 06:29:15 PM PDT 24
Peak memory 217908 kb
Host smart-328a914d-c122-4530-bc90-2de5a68d0118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458857772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.458857772
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.228109385
Short name T510
Test name
Test status
Simulation time 51427170 ps
CPU time 1.25 seconds
Started Jun 26 06:29:27 PM PDT 24
Finished Jun 26 06:29:34 PM PDT 24
Peak memory 218924 kb
Host smart-1737cbd6-c3f4-4971-ab92-d5ceec50e326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228109385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.228109385
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.492362384
Short name T136
Test name
Test status
Simulation time 29272106 ps
CPU time 1.27 seconds
Started Jun 26 06:27:25 PM PDT 24
Finished Jun 26 06:27:31 PM PDT 24
Peak memory 219988 kb
Host smart-067259f6-10cc-418f-8a52-48de0939563a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492362384 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.492362384
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3827908137
Short name T68
Test name
Test status
Simulation time 14103018 ps
CPU time 0.92 seconds
Started Jun 26 06:27:33 PM PDT 24
Finished Jun 26 06:27:38 PM PDT 24
Peak memory 207084 kb
Host smart-8d19780f-1e9e-48f5-b7e9-79a46666749e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827908137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3827908137
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1936408786
Short name T213
Test name
Test status
Simulation time 32561740 ps
CPU time 1.19 seconds
Started Jun 26 06:27:32 PM PDT 24
Finished Jun 26 06:27:37 PM PDT 24
Peak memory 217180 kb
Host smart-7f38ba2e-06fb-41f1-b18f-2fbe54082c10
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936408786 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1936408786
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.354652678
Short name T698
Test name
Test status
Simulation time 29975910 ps
CPU time 1.32 seconds
Started Jun 26 06:27:32 PM PDT 24
Finished Jun 26 06:27:37 PM PDT 24
Peak memory 220052 kb
Host smart-a50052cd-2108-4807-97f6-41b3175d1bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354652678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.354652678
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1081310939
Short name T327
Test name
Test status
Simulation time 32822526 ps
CPU time 1.29 seconds
Started Jun 26 06:27:22 PM PDT 24
Finished Jun 26 06:27:28 PM PDT 24
Peak memory 220244 kb
Host smart-89a9b50f-1fdf-4515-9570-5605a649267a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081310939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1081310939
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2986327662
Short name T800
Test name
Test status
Simulation time 25012925 ps
CPU time 0.96 seconds
Started Jun 26 06:27:35 PM PDT 24
Finished Jun 26 06:27:39 PM PDT 24
Peak memory 215768 kb
Host smart-735f1c3f-ffd5-4162-9d34-e10d73ef3ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986327662 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2986327662
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.951603264
Short name T366
Test name
Test status
Simulation time 18586702 ps
CPU time 1.06 seconds
Started Jun 26 06:27:26 PM PDT 24
Finished Jun 26 06:27:30 PM PDT 24
Peak memory 215620 kb
Host smart-8d522bc7-ed6b-450f-95dd-951625627830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951603264 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.951603264
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2093481816
Short name T895
Test name
Test status
Simulation time 97450065 ps
CPU time 1.13 seconds
Started Jun 26 06:27:24 PM PDT 24
Finished Jun 26 06:27:29 PM PDT 24
Peak memory 217696 kb
Host smart-49fd9d29-9449-49e7-bcd4-496ba292a0c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093481816 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2093481816
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.507252447
Short name T230
Test name
Test status
Simulation time 45042483232 ps
CPU time 528.39 seconds
Started Jun 26 06:27:23 PM PDT 24
Finished Jun 26 06:36:16 PM PDT 24
Peak memory 217884 kb
Host smart-929071cb-3081-461e-9bc6-f5bbd5f30566
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507252447 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.507252447
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3692235126
Short name T488
Test name
Test status
Simulation time 34597325 ps
CPU time 1.35 seconds
Started Jun 26 06:29:15 PM PDT 24
Finished Jun 26 06:29:21 PM PDT 24
Peak memory 220320 kb
Host smart-0c5babbc-d1ed-4c66-bbc4-6dfa854ce3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692235126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3692235126
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2954055122
Short name T419
Test name
Test status
Simulation time 40094040 ps
CPU time 1.07 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:37 PM PDT 24
Peak memory 217656 kb
Host smart-889ebac7-aac3-4130-9c3f-f2fa114e7295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954055122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2954055122
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1530142003
Short name T827
Test name
Test status
Simulation time 38884489 ps
CPU time 1.83 seconds
Started Jun 26 06:29:26 PM PDT 24
Finished Jun 26 06:29:41 PM PDT 24
Peak memory 219092 kb
Host smart-46309d36-dd1d-4fb6-854c-45bd8ecb7335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530142003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1530142003
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1242937855
Short name T520
Test name
Test status
Simulation time 59403386 ps
CPU time 1.72 seconds
Started Jun 26 06:29:26 PM PDT 24
Finished Jun 26 06:29:33 PM PDT 24
Peak memory 220484 kb
Host smart-3c0e1e26-f3d3-4fb3-b9e1-35c5fe812c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242937855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1242937855
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.4030675212
Short name T417
Test name
Test status
Simulation time 34437146 ps
CPU time 1.64 seconds
Started Jun 26 06:29:14 PM PDT 24
Finished Jun 26 06:29:21 PM PDT 24
Peak memory 218904 kb
Host smart-38f5268f-094a-433c-9be2-3e1aaaed75ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030675212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.4030675212
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1188857416
Short name T90
Test name
Test status
Simulation time 89709175 ps
CPU time 1.28 seconds
Started Jun 26 06:29:17 PM PDT 24
Finished Jun 26 06:29:23 PM PDT 24
Peak memory 217940 kb
Host smart-01fb35d7-cf54-44c6-adc4-4063db0ac416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188857416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1188857416
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1362617469
Short name T672
Test name
Test status
Simulation time 69273902 ps
CPU time 1.2 seconds
Started Jun 26 06:29:10 PM PDT 24
Finished Jun 26 06:29:13 PM PDT 24
Peak memory 217556 kb
Host smart-a333d4b6-8f7c-4295-af7f-03ab31d1ccab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362617469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1362617469
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1118250348
Short name T363
Test name
Test status
Simulation time 230376071 ps
CPU time 2.48 seconds
Started Jun 26 06:29:20 PM PDT 24
Finished Jun 26 06:29:26 PM PDT 24
Peak memory 217788 kb
Host smart-bd066d7e-fb90-46d5-bae3-dffcd14e02d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118250348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1118250348
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1315685325
Short name T583
Test name
Test status
Simulation time 128303793 ps
CPU time 1.48 seconds
Started Jun 26 06:29:18 PM PDT 24
Finished Jun 26 06:29:24 PM PDT 24
Peak memory 219144 kb
Host smart-b2bbf236-e015-401a-b34a-1ed90336053a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315685325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1315685325
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2418632127
Short name T543
Test name
Test status
Simulation time 62096850 ps
CPU time 2.34 seconds
Started Jun 26 06:29:27 PM PDT 24
Finished Jun 26 06:29:35 PM PDT 24
Peak memory 220728 kb
Host smart-251413fa-88fc-425a-ab2b-2b77a47bcc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418632127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2418632127
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.878136987
Short name T526
Test name
Test status
Simulation time 183823949 ps
CPU time 1.25 seconds
Started Jun 26 06:27:29 PM PDT 24
Finished Jun 26 06:27:34 PM PDT 24
Peak memory 219752 kb
Host smart-1d9d55b1-6d93-404e-a6d4-799ca9dd93c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878136987 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.878136987
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.703669231
Short name T341
Test name
Test status
Simulation time 25792645 ps
CPU time 0.88 seconds
Started Jun 26 06:27:30 PM PDT 24
Finished Jun 26 06:27:35 PM PDT 24
Peak memory 215224 kb
Host smart-16ab1fce-5bde-487f-84ef-8c01187e049a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703669231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.703669231
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.542307850
Short name T79
Test name
Test status
Simulation time 13774766 ps
CPU time 0.92 seconds
Started Jun 26 06:27:33 PM PDT 24
Finished Jun 26 06:27:37 PM PDT 24
Peak memory 216868 kb
Host smart-6b233311-54e4-4218-b9c0-cf17cbb75520
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542307850 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.542307850
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_err.1098474819
Short name T173
Test name
Test status
Simulation time 44749857 ps
CPU time 0.97 seconds
Started Jun 26 06:27:32 PM PDT 24
Finished Jun 26 06:27:36 PM PDT 24
Peak memory 224080 kb
Host smart-f1c244a0-3251-4007-8501-78c46e615fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098474819 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1098474819
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.4188641922
Short name T538
Test name
Test status
Simulation time 110465821 ps
CPU time 1.64 seconds
Started Jun 26 06:27:30 PM PDT 24
Finished Jun 26 06:27:35 PM PDT 24
Peak memory 219384 kb
Host smart-48f1a92d-6c15-413c-bd48-ab3b660113c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188641922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.4188641922
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2224878558
Short name T962
Test name
Test status
Simulation time 22858800 ps
CPU time 1.18 seconds
Started Jun 26 06:27:32 PM PDT 24
Finished Jun 26 06:27:37 PM PDT 24
Peak memory 224360 kb
Host smart-83b4bae7-a218-424b-80eb-755d93de8f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224878558 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2224878558
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2603709104
Short name T544
Test name
Test status
Simulation time 17592637 ps
CPU time 1.07 seconds
Started Jun 26 06:27:30 PM PDT 24
Finished Jun 26 06:27:34 PM PDT 24
Peak memory 215664 kb
Host smart-220d5118-8391-44f4-a1b5-f685928bd33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603709104 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2603709104
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3686999332
Short name T825
Test name
Test status
Simulation time 68804501068 ps
CPU time 709.88 seconds
Started Jun 26 06:27:33 PM PDT 24
Finished Jun 26 06:39:27 PM PDT 24
Peak memory 224116 kb
Host smart-6aaf6147-c9d1-466a-845f-c553962ea1bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686999332 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3686999332
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2749651077
Short name T352
Test name
Test status
Simulation time 273991249 ps
CPU time 1.12 seconds
Started Jun 26 06:29:21 PM PDT 24
Finished Jun 26 06:29:26 PM PDT 24
Peak memory 217684 kb
Host smart-57328b7e-7c31-49ea-a485-e9cd2ca75ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749651077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2749651077
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1432494690
Short name T964
Test name
Test status
Simulation time 70644924 ps
CPU time 1.15 seconds
Started Jun 26 06:29:25 PM PDT 24
Finished Jun 26 06:29:38 PM PDT 24
Peak memory 219316 kb
Host smart-c551eac5-795e-4812-bca5-970ce3a69f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432494690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1432494690
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1737411772
Short name T372
Test name
Test status
Simulation time 86025652 ps
CPU time 2.83 seconds
Started Jun 26 06:29:13 PM PDT 24
Finished Jun 26 06:29:21 PM PDT 24
Peak memory 220588 kb
Host smart-3faf8cb3-9558-47fa-8c1e-51df43050a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737411772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1737411772
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.566347480
Short name T750
Test name
Test status
Simulation time 59389341 ps
CPU time 1.23 seconds
Started Jun 26 06:29:11 PM PDT 24
Finished Jun 26 06:29:14 PM PDT 24
Peak memory 217644 kb
Host smart-612d0510-29f4-46f4-8052-2ca2f18d9277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566347480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.566347480
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.4249361685
Short name T812
Test name
Test status
Simulation time 29694514 ps
CPU time 1.25 seconds
Started Jun 26 06:29:11 PM PDT 24
Finished Jun 26 06:29:14 PM PDT 24
Peak memory 217640 kb
Host smart-3322505d-6d8e-467c-801e-b2506109239e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249361685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.4249361685
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1837550823
Short name T44
Test name
Test status
Simulation time 267748416 ps
CPU time 1.1 seconds
Started Jun 26 06:29:26 PM PDT 24
Finished Jun 26 06:29:33 PM PDT 24
Peak memory 217196 kb
Host smart-da7fa9ff-b3b5-48ff-a063-95b6036471a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837550823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1837550823
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2565484586
Short name T817
Test name
Test status
Simulation time 60163541 ps
CPU time 1.13 seconds
Started Jun 26 06:29:25 PM PDT 24
Finished Jun 26 06:29:30 PM PDT 24
Peak memory 217700 kb
Host smart-469484b7-2c8a-44a1-9876-ba88d208d30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565484586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2565484586
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2385342354
Short name T877
Test name
Test status
Simulation time 41482066 ps
CPU time 1.59 seconds
Started Jun 26 06:29:10 PM PDT 24
Finished Jun 26 06:29:13 PM PDT 24
Peak memory 217668 kb
Host smart-18f83fa2-788e-4eeb-a5dc-0244c1f9d609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385342354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2385342354
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3550204412
Short name T921
Test name
Test status
Simulation time 51400636 ps
CPU time 1.45 seconds
Started Jun 26 06:29:19 PM PDT 24
Finished Jun 26 06:29:25 PM PDT 24
Peak memory 219184 kb
Host smart-9e18bbb2-4c96-4ee6-a007-5d3f96f90eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550204412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3550204412
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1104910430
Short name T838
Test name
Test status
Simulation time 27809059 ps
CPU time 1.24 seconds
Started Jun 26 06:27:31 PM PDT 24
Finished Jun 26 06:27:36 PM PDT 24
Peak memory 220908 kb
Host smart-6fe641bf-669b-4af8-a517-c6199b0d59ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104910430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1104910430
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.839637982
Short name T536
Test name
Test status
Simulation time 71278219 ps
CPU time 1.01 seconds
Started Jun 26 06:27:31 PM PDT 24
Finished Jun 26 06:27:35 PM PDT 24
Peak memory 207024 kb
Host smart-fee83c5f-2316-4098-be82-f5050a74dd38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839637982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.839637982
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.484360043
Short name T151
Test name
Test status
Simulation time 16758660 ps
CPU time 0.86 seconds
Started Jun 26 06:27:30 PM PDT 24
Finished Jun 26 06:27:35 PM PDT 24
Peak memory 215768 kb
Host smart-7dd63a9d-28bd-4eda-a840-a4109a593095
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484360043 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.484360043
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3029376836
Short name T882
Test name
Test status
Simulation time 40047212 ps
CPU time 1.04 seconds
Started Jun 26 06:27:31 PM PDT 24
Finished Jun 26 06:27:35 PM PDT 24
Peak memory 217224 kb
Host smart-c6a82fc0-b240-4b00-8628-9b44803111f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029376836 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3029376836
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.828775027
Short name T134
Test name
Test status
Simulation time 33151286 ps
CPU time 1.05 seconds
Started Jun 26 06:27:32 PM PDT 24
Finished Jun 26 06:27:36 PM PDT 24
Peak memory 219808 kb
Host smart-79dad817-b656-4132-9e5d-12a39f196bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828775027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.828775027
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3155621655
Short name T555
Test name
Test status
Simulation time 23008911 ps
CPU time 1.19 seconds
Started Jun 26 06:27:31 PM PDT 24
Finished Jun 26 06:27:36 PM PDT 24
Peak memory 217472 kb
Host smart-a3ef4852-80aa-4403-8f0f-80e3a6df50a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155621655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3155621655
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1166187904
Short name T968
Test name
Test status
Simulation time 36373464 ps
CPU time 0.87 seconds
Started Jun 26 06:27:33 PM PDT 24
Finished Jun 26 06:27:37 PM PDT 24
Peak memory 215688 kb
Host smart-5dd11d80-02ff-4662-ae2a-6ba571708f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166187904 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1166187904
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.22670836
Short name T442
Test name
Test status
Simulation time 27495540 ps
CPU time 0.99 seconds
Started Jun 26 06:27:29 PM PDT 24
Finished Jun 26 06:27:34 PM PDT 24
Peak memory 215668 kb
Host smart-f6e3cf81-a3c9-4183-bdab-d8cfbb1784d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22670836 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.22670836
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.80656078
Short name T939
Test name
Test status
Simulation time 319295862 ps
CPU time 1.4 seconds
Started Jun 26 06:27:30 PM PDT 24
Finished Jun 26 06:27:35 PM PDT 24
Peak memory 215608 kb
Host smart-8eb1c307-9a85-4783-a0b2-a50070a4c92f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80656078 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.80656078
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.679247729
Short name T590
Test name
Test status
Simulation time 161443644445 ps
CPU time 985.78 seconds
Started Jun 26 06:27:30 PM PDT 24
Finished Jun 26 06:44:00 PM PDT 24
Peak memory 222236 kb
Host smart-6780f61c-f4da-4a78-8b01-01e36f1b3d67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679247729 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.679247729
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2139645749
Short name T991
Test name
Test status
Simulation time 124335586 ps
CPU time 1.38 seconds
Started Jun 26 06:29:13 PM PDT 24
Finished Jun 26 06:29:19 PM PDT 24
Peak memory 218992 kb
Host smart-5538dad8-78b9-4283-9f56-14468b19070d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139645749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2139645749
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1531501402
Short name T382
Test name
Test status
Simulation time 46223853 ps
CPU time 1.57 seconds
Started Jun 26 06:29:18 PM PDT 24
Finished Jun 26 06:29:24 PM PDT 24
Peak memory 218912 kb
Host smart-2b5f1cb4-702a-42e7-bed5-ca544f2c96b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531501402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1531501402
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.625424953
Short name T890
Test name
Test status
Simulation time 55066012 ps
CPU time 1.26 seconds
Started Jun 26 06:29:15 PM PDT 24
Finished Jun 26 06:29:21 PM PDT 24
Peak memory 217792 kb
Host smart-a112a458-3408-465c-9734-6bcf9269852a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625424953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.625424953
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1013262652
Short name T377
Test name
Test status
Simulation time 25161275 ps
CPU time 1.39 seconds
Started Jun 26 06:29:13 PM PDT 24
Finished Jun 26 06:29:20 PM PDT 24
Peak memory 217856 kb
Host smart-1fb5ded5-c3c2-44bd-aab1-6ca28b61d6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013262652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1013262652
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2747391366
Short name T983
Test name
Test status
Simulation time 28740026 ps
CPU time 1.25 seconds
Started Jun 26 06:29:16 PM PDT 24
Finished Jun 26 06:29:22 PM PDT 24
Peak memory 220180 kb
Host smart-f6ff393d-9248-4750-80a4-92e982a3f9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747391366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2747391366
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2696852165
Short name T75
Test name
Test status
Simulation time 70897262 ps
CPU time 1.52 seconds
Started Jun 26 06:29:12 PM PDT 24
Finished Jun 26 06:29:16 PM PDT 24
Peak memory 218808 kb
Host smart-14f292b3-71e2-4def-b9e4-768450a01df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696852165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2696852165
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.148554494
Short name T369
Test name
Test status
Simulation time 42564354 ps
CPU time 1.23 seconds
Started Jun 26 06:29:16 PM PDT 24
Finished Jun 26 06:29:23 PM PDT 24
Peak memory 219020 kb
Host smart-7fd6f72a-9bf2-4a01-a2f5-d07c5104182a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148554494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.148554494
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1222121954
Short name T763
Test name
Test status
Simulation time 75248320 ps
CPU time 1.11 seconds
Started Jun 26 06:29:24 PM PDT 24
Finished Jun 26 06:29:29 PM PDT 24
Peak memory 219332 kb
Host smart-adc9d0e2-b33e-46a6-b019-590a08d5a0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222121954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1222121954
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1246853608
Short name T94
Test name
Test status
Simulation time 43192288 ps
CPU time 1.67 seconds
Started Jun 26 06:29:15 PM PDT 24
Finished Jun 26 06:29:22 PM PDT 24
Peak memory 218964 kb
Host smart-240096c5-b391-4b16-8586-0a6719834240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246853608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1246853608
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.963314038
Short name T296
Test name
Test status
Simulation time 39360904 ps
CPU time 1.48 seconds
Started Jun 26 06:29:19 PM PDT 24
Finished Jun 26 06:29:25 PM PDT 24
Peak memory 220360 kb
Host smart-14f77fb1-52c5-4f9e-9c2d-849b139a2483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963314038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.963314038
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1423028382
Short name T580
Test name
Test status
Simulation time 171799644 ps
CPU time 1.18 seconds
Started Jun 26 06:27:34 PM PDT 24
Finished Jun 26 06:27:38 PM PDT 24
Peak memory 220144 kb
Host smart-2b54cab3-686f-4690-a5b4-df66288e0873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423028382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1423028382
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3980870423
Short name T420
Test name
Test status
Simulation time 20172592 ps
CPU time 0.85 seconds
Started Jun 26 06:27:32 PM PDT 24
Finished Jun 26 06:27:36 PM PDT 24
Peak memory 207160 kb
Host smart-fd90c90c-054c-472c-a15d-66f6dcb6aca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980870423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3980870423
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.36731236
Short name T223
Test name
Test status
Simulation time 17178875 ps
CPU time 0.87 seconds
Started Jun 26 06:27:31 PM PDT 24
Finished Jun 26 06:27:36 PM PDT 24
Peak memory 215796 kb
Host smart-5a97ce6a-ef5f-45ef-a41f-c04d2f021e90
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36731236 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.36731236
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.4267496935
Short name T273
Test name
Test status
Simulation time 33694480 ps
CPU time 1.28 seconds
Started Jun 26 06:27:32 PM PDT 24
Finished Jun 26 06:27:36 PM PDT 24
Peak memory 217108 kb
Host smart-b9bdb274-cf35-43e9-a79f-a335321aea8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267496935 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.4267496935
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_genbits.3403486957
Short name T785
Test name
Test status
Simulation time 117203771 ps
CPU time 1.7 seconds
Started Jun 26 06:27:30 PM PDT 24
Finished Jun 26 06:27:35 PM PDT 24
Peak memory 219348 kb
Host smart-55c3e10c-552f-4671-a4e6-9e9a5745d789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403486957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3403486957
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.545333572
Short name T948
Test name
Test status
Simulation time 36439363 ps
CPU time 1.09 seconds
Started Jun 26 06:27:31 PM PDT 24
Finished Jun 26 06:27:36 PM PDT 24
Peak memory 224136 kb
Host smart-cf3460a8-eb58-4051-99ee-b65671f6df94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545333572 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.545333572
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2152186510
Short name T486
Test name
Test status
Simulation time 17065659 ps
CPU time 1 seconds
Started Jun 26 06:27:30 PM PDT 24
Finished Jun 26 06:27:35 PM PDT 24
Peak memory 215616 kb
Host smart-f9056eb3-2246-4661-9610-2e7eb2b2b55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152186510 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2152186510
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.887105218
Short name T290
Test name
Test status
Simulation time 380853047 ps
CPU time 5.63 seconds
Started Jun 26 06:27:33 PM PDT 24
Finished Jun 26 06:27:42 PM PDT 24
Peak memory 215608 kb
Host smart-56af51f9-9bfc-4bf2-81a6-c2b25fbe529d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887105218 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.887105218
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1346226750
Short name T645
Test name
Test status
Simulation time 98587524157 ps
CPU time 550.19 seconds
Started Jun 26 06:27:32 PM PDT 24
Finished Jun 26 06:36:46 PM PDT 24
Peak memory 220016 kb
Host smart-6fceaedd-6092-4f32-a689-fff06ecb364f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346226750 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1346226750
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2163218868
Short name T654
Test name
Test status
Simulation time 48620144 ps
CPU time 1.3 seconds
Started Jun 26 06:29:14 PM PDT 24
Finished Jun 26 06:29:20 PM PDT 24
Peak memory 219096 kb
Host smart-a8170957-dace-4a00-ab3b-795b6ae97dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163218868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2163218868
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3070412865
Short name T709
Test name
Test status
Simulation time 38605803 ps
CPU time 1.32 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:37 PM PDT 24
Peak memory 217620 kb
Host smart-f01fa777-3505-42ea-84d9-5306036f32c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070412865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3070412865
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.410033383
Short name T491
Test name
Test status
Simulation time 39780617 ps
CPU time 1.7 seconds
Started Jun 26 06:29:16 PM PDT 24
Finished Jun 26 06:29:22 PM PDT 24
Peak memory 220532 kb
Host smart-42a9ce6b-51ba-4a55-9b3e-696f7a5518ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410033383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.410033383
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1625385144
Short name T310
Test name
Test status
Simulation time 49289815 ps
CPU time 1.53 seconds
Started Jun 26 06:29:14 PM PDT 24
Finished Jun 26 06:29:20 PM PDT 24
Peak memory 219376 kb
Host smart-413c4481-fe2b-4076-8331-8c59a53023cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625385144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1625385144
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2201942249
Short name T567
Test name
Test status
Simulation time 98554365 ps
CPU time 1.21 seconds
Started Jun 26 06:29:24 PM PDT 24
Finished Jun 26 06:29:30 PM PDT 24
Peak memory 217608 kb
Host smart-4e6cce2e-0e9a-434e-8d5e-5b1fb529b3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201942249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2201942249
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1805649378
Short name T299
Test name
Test status
Simulation time 80659507 ps
CPU time 1.41 seconds
Started Jun 26 06:29:14 PM PDT 24
Finished Jun 26 06:29:20 PM PDT 24
Peak memory 218972 kb
Host smart-5e7c92d2-287b-4e93-97a3-d8ba4c1db18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805649378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1805649378
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.421473433
Short name T243
Test name
Test status
Simulation time 90389399 ps
CPU time 2.75 seconds
Started Jun 26 06:29:28 PM PDT 24
Finished Jun 26 06:29:37 PM PDT 24
Peak memory 215672 kb
Host smart-3d0f3f25-0ab3-4058-870b-e0883e36669b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421473433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.421473433
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1244103973
Short name T340
Test name
Test status
Simulation time 60835286 ps
CPU time 1.3 seconds
Started Jun 26 06:29:19 PM PDT 24
Finished Jun 26 06:29:24 PM PDT 24
Peak memory 218812 kb
Host smart-31a0c732-b308-432a-b5cb-ee7097572636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244103973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1244103973
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1126149555
Short name T795
Test name
Test status
Simulation time 52306184 ps
CPU time 1.17 seconds
Started Jun 26 06:29:19 PM PDT 24
Finished Jun 26 06:29:24 PM PDT 24
Peak memory 217588 kb
Host smart-3e21a835-7058-4e94-9820-47a6f92da7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126149555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1126149555
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3752749554
Short name T119
Test name
Test status
Simulation time 74762857 ps
CPU time 1.22 seconds
Started Jun 26 06:27:32 PM PDT 24
Finished Jun 26 06:27:36 PM PDT 24
Peak memory 219004 kb
Host smart-78d3d4bd-d624-4208-bd9a-ee93cb40c678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752749554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3752749554
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.4026308914
Short name T878
Test name
Test status
Simulation time 90957141 ps
CPU time 1.03 seconds
Started Jun 26 06:27:32 PM PDT 24
Finished Jun 26 06:27:36 PM PDT 24
Peak memory 207124 kb
Host smart-c81acff8-7827-458d-9661-dfcb9e70a8e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026308914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.4026308914
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2094595704
Short name T860
Test name
Test status
Simulation time 47523951 ps
CPU time 1.35 seconds
Started Jun 26 06:27:31 PM PDT 24
Finished Jun 26 06:27:35 PM PDT 24
Peak memory 217396 kb
Host smart-d975c580-4dc9-44ac-942a-9ebd5fee2196
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094595704 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2094595704
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1809587792
Short name T149
Test name
Test status
Simulation time 31005163 ps
CPU time 1.29 seconds
Started Jun 26 06:27:31 PM PDT 24
Finished Jun 26 06:27:36 PM PDT 24
Peak memory 220116 kb
Host smart-00860386-eaa3-4760-9802-f335eb092caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809587792 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1809587792
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1085315499
Short name T764
Test name
Test status
Simulation time 31553574 ps
CPU time 1.24 seconds
Started Jun 26 06:27:31 PM PDT 24
Finished Jun 26 06:27:36 PM PDT 24
Peak memory 217716 kb
Host smart-827116e9-4eb3-4f15-afec-ea50813475c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085315499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1085315499
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.923241640
Short name T98
Test name
Test status
Simulation time 69362147 ps
CPU time 0.89 seconds
Started Jun 26 06:27:33 PM PDT 24
Finished Jun 26 06:27:37 PM PDT 24
Peak memory 215656 kb
Host smart-d91986f1-3504-48f0-8b05-78ba30b43982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923241640 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.923241640
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1722484035
Short name T373
Test name
Test status
Simulation time 24590083 ps
CPU time 1.05 seconds
Started Jun 26 06:27:33 PM PDT 24
Finished Jun 26 06:27:37 PM PDT 24
Peak memory 215640 kb
Host smart-2fad5c4e-4ae2-46be-b82e-b47f70b80cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722484035 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1722484035
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.278018660
Short name T741
Test name
Test status
Simulation time 216446498 ps
CPU time 4.59 seconds
Started Jun 26 06:27:34 PM PDT 24
Finished Jun 26 06:27:42 PM PDT 24
Peak memory 217696 kb
Host smart-a742ba2d-4fc0-49f7-9e32-f8347b95ec8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278018660 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.278018660
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2627431614
Short name T367
Test name
Test status
Simulation time 121741788993 ps
CPU time 2500.83 seconds
Started Jun 26 06:27:31 PM PDT 24
Finished Jun 26 07:09:16 PM PDT 24
Peak memory 232944 kb
Host smart-db2ee4a1-b811-4fe6-bca1-dbd0bebf984e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627431614 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2627431614
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.729935934
Short name T289
Test name
Test status
Simulation time 24327003 ps
CPU time 1.23 seconds
Started Jun 26 06:29:13 PM PDT 24
Finished Jun 26 06:29:19 PM PDT 24
Peak memory 217888 kb
Host smart-f130afaa-c99a-4d3b-aa67-c9ca9c13c4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729935934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.729935934
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2609431739
Short name T78
Test name
Test status
Simulation time 57952075 ps
CPU time 1.73 seconds
Started Jun 26 06:29:15 PM PDT 24
Finished Jun 26 06:29:22 PM PDT 24
Peak memory 219532 kb
Host smart-3f0398a4-6745-40e5-a014-2da6558e92c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609431739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2609431739
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.992126478
Short name T521
Test name
Test status
Simulation time 43971469 ps
CPU time 1.7 seconds
Started Jun 26 06:29:15 PM PDT 24
Finished Jun 26 06:29:22 PM PDT 24
Peak memory 217752 kb
Host smart-52a8673a-8085-421c-93c1-37f47cd29e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992126478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.992126478
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3418878748
Short name T480
Test name
Test status
Simulation time 49365584 ps
CPU time 1.11 seconds
Started Jun 26 06:29:23 PM PDT 24
Finished Jun 26 06:29:27 PM PDT 24
Peak memory 220060 kb
Host smart-f75f5865-ef1b-417a-8747-b3869ad8b4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418878748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3418878748
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1477117575
Short name T950
Test name
Test status
Simulation time 50264418 ps
CPU time 1.26 seconds
Started Jun 26 06:29:26 PM PDT 24
Finished Jun 26 06:29:33 PM PDT 24
Peak memory 218912 kb
Host smart-0e80db56-e57c-419e-91ba-858f553997e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477117575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1477117575
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1598127854
Short name T652
Test name
Test status
Simulation time 100879545 ps
CPU time 2.86 seconds
Started Jun 26 06:29:26 PM PDT 24
Finished Jun 26 06:29:39 PM PDT 24
Peak memory 217832 kb
Host smart-06c70778-771f-49b2-9879-0971b103eb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598127854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1598127854
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1603713953
Short name T484
Test name
Test status
Simulation time 98501406 ps
CPU time 1.45 seconds
Started Jun 26 06:29:26 PM PDT 24
Finished Jun 26 06:29:33 PM PDT 24
Peak memory 218012 kb
Host smart-ed893e15-a9c5-4ed1-9e0b-fc536ac138bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603713953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1603713953
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1505271797
Short name T423
Test name
Test status
Simulation time 51460667 ps
CPU time 1.19 seconds
Started Jun 26 06:29:26 PM PDT 24
Finished Jun 26 06:29:43 PM PDT 24
Peak memory 217640 kb
Host smart-90d5bec4-a0cf-4d20-b4cb-a52f6b81632f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505271797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1505271797
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.27534663
Short name T933
Test name
Test status
Simulation time 313349704 ps
CPU time 1.37 seconds
Started Jun 26 06:29:25 PM PDT 24
Finished Jun 26 06:29:31 PM PDT 24
Peak memory 220368 kb
Host smart-54ca970c-defa-44f8-b041-dfa07a4fedde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27534663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.27534663
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.767627077
Short name T831
Test name
Test status
Simulation time 50674160 ps
CPU time 1.37 seconds
Started Jun 26 06:27:39 PM PDT 24
Finished Jun 26 06:27:42 PM PDT 24
Peak memory 220296 kb
Host smart-e5ab7d4d-fa3f-4266-897f-15490c2c6d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767627077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.767627077
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3390070579
Short name T379
Test name
Test status
Simulation time 17816997 ps
CPU time 1.04 seconds
Started Jun 26 06:27:42 PM PDT 24
Finished Jun 26 06:27:45 PM PDT 24
Peak memory 207096 kb
Host smart-1a36cbe5-716a-430f-a79e-c5d1d2131437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390070579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3390070579
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2069236641
Short name T212
Test name
Test status
Simulation time 14712509 ps
CPU time 0.92 seconds
Started Jun 26 06:27:45 PM PDT 24
Finished Jun 26 06:27:47 PM PDT 24
Peak memory 215648 kb
Host smart-6f65e03d-9f75-4a63-ba25-af05dd8b4663
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069236641 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2069236641
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.2398469869
Short name T215
Test name
Test status
Simulation time 22214905 ps
CPU time 1.17 seconds
Started Jun 26 06:27:43 PM PDT 24
Finished Jun 26 06:27:45 PM PDT 24
Peak memory 219944 kb
Host smart-6d18df7c-2bb7-49a0-82f5-8718d15e226c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398469869 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2398469869
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1486548334
Short name T305
Test name
Test status
Simulation time 65345896 ps
CPU time 1.58 seconds
Started Jun 26 06:27:40 PM PDT 24
Finished Jun 26 06:27:43 PM PDT 24
Peak memory 218996 kb
Host smart-b1014e4d-12de-43dc-9cc1-77a29c4a00c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486548334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1486548334
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_smoke.2480752066
Short name T71
Test name
Test status
Simulation time 27790338 ps
CPU time 0.96 seconds
Started Jun 26 06:27:30 PM PDT 24
Finished Jun 26 06:27:34 PM PDT 24
Peak memory 215624 kb
Host smart-bd5ed5e6-7c67-4b1d-8a2f-689f4e195d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480752066 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2480752066
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2234002763
Short name T637
Test name
Test status
Simulation time 58846117 ps
CPU time 1.65 seconds
Started Jun 26 06:27:36 PM PDT 24
Finished Jun 26 06:27:40 PM PDT 24
Peak memory 215604 kb
Host smart-386fd35d-d365-40c5-beb2-80d61746e63d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234002763 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2234002763
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1091185457
Short name T674
Test name
Test status
Simulation time 65752518954 ps
CPU time 1536.43 seconds
Started Jun 26 06:27:38 PM PDT 24
Finished Jun 26 06:53:17 PM PDT 24
Peak memory 224108 kb
Host smart-6a09ae33-c24f-465a-ade4-029086c4ea46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091185457 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1091185457
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3904298419
Short name T971
Test name
Test status
Simulation time 49800089 ps
CPU time 1.04 seconds
Started Jun 26 06:29:23 PM PDT 24
Finished Jun 26 06:29:28 PM PDT 24
Peak memory 217560 kb
Host smart-1ddbe3eb-4b61-455b-99f9-c6a2b96ea49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904298419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3904298419
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1927406266
Short name T643
Test name
Test status
Simulation time 57755445 ps
CPU time 0.97 seconds
Started Jun 26 06:29:28 PM PDT 24
Finished Jun 26 06:29:35 PM PDT 24
Peak memory 217712 kb
Host smart-70f63ca1-ca8b-4437-842e-bcce3896d958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927406266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1927406266
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1297157903
Short name T572
Test name
Test status
Simulation time 83323141 ps
CPU time 1.46 seconds
Started Jun 26 06:29:26 PM PDT 24
Finished Jun 26 06:29:37 PM PDT 24
Peak memory 219244 kb
Host smart-47da6452-078c-4e68-810b-abf3d2ad766e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297157903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1297157903
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3219533832
Short name T896
Test name
Test status
Simulation time 33023154 ps
CPU time 1.02 seconds
Started Jun 26 06:29:26 PM PDT 24
Finished Jun 26 06:29:33 PM PDT 24
Peak memory 219936 kb
Host smart-1529ae27-9cf6-4ebb-9fcc-411ad0a436ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219533832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3219533832
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3968059726
Short name T885
Test name
Test status
Simulation time 76614046 ps
CPU time 1.1 seconds
Started Jun 26 06:29:27 PM PDT 24
Finished Jun 26 06:29:34 PM PDT 24
Peak memory 220072 kb
Host smart-149c68c3-4c2c-46a7-b590-a230a9b0f876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968059726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3968059726
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.4147560212
Short name T425
Test name
Test status
Simulation time 46551729 ps
CPU time 1.2 seconds
Started Jun 26 06:29:19 PM PDT 24
Finished Jun 26 06:29:24 PM PDT 24
Peak memory 218816 kb
Host smart-fa4299e8-0e40-420a-96a7-ccf01b0796da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147560212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.4147560212
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1898454604
Short name T335
Test name
Test status
Simulation time 46909174 ps
CPU time 1.71 seconds
Started Jun 26 06:29:14 PM PDT 24
Finished Jun 26 06:29:21 PM PDT 24
Peak memory 217736 kb
Host smart-64248883-a9b7-4314-94ae-201691627f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898454604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1898454604
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.135222835
Short name T356
Test name
Test status
Simulation time 89548720 ps
CPU time 1.16 seconds
Started Jun 26 06:29:34 PM PDT 24
Finished Jun 26 06:29:43 PM PDT 24
Peak memory 217492 kb
Host smart-22471f1d-daa9-4af4-9ef7-9178a6236e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135222835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.135222835
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.3840672525
Short name T922
Test name
Test status
Simulation time 120356297 ps
CPU time 1.18 seconds
Started Jun 26 06:29:14 PM PDT 24
Finished Jun 26 06:29:20 PM PDT 24
Peak memory 219964 kb
Host smart-fb095deb-8303-4e6f-9e8a-dfdf6b1b03b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840672525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.3840672525
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2258503200
Short name T384
Test name
Test status
Simulation time 75008573 ps
CPU time 1.07 seconds
Started Jun 26 06:29:25 PM PDT 24
Finished Jun 26 06:29:32 PM PDT 24
Peak memory 217616 kb
Host smart-292e201b-859b-4341-b64d-d63bc35c605c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258503200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2258503200
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3608094363
Short name T958
Test name
Test status
Simulation time 92941706 ps
CPU time 1.23 seconds
Started Jun 26 06:27:39 PM PDT 24
Finished Jun 26 06:27:43 PM PDT 24
Peak memory 215544 kb
Host smart-d56ba663-6405-4529-a3c1-c7bcb6f1a2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608094363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3608094363
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1535453003
Short name T646
Test name
Test status
Simulation time 20290162 ps
CPU time 1.05 seconds
Started Jun 26 06:27:36 PM PDT 24
Finished Jun 26 06:27:39 PM PDT 24
Peak memory 207028 kb
Host smart-e7d2dc0c-1919-4b53-867b-e41a975d5c2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535453003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1535453003
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.2688195116
Short name T806
Test name
Test status
Simulation time 10322146 ps
CPU time 0.92 seconds
Started Jun 26 06:27:36 PM PDT 24
Finished Jun 26 06:27:40 PM PDT 24
Peak memory 215696 kb
Host smart-abdf1394-7ac4-4e19-9dcc-9a60f8acc047
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688195116 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2688195116
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2414173178
Short name T765
Test name
Test status
Simulation time 36043009 ps
CPU time 1.03 seconds
Started Jun 26 06:27:43 PM PDT 24
Finished Jun 26 06:27:45 PM PDT 24
Peak memory 217256 kb
Host smart-961b3a06-6f30-4968-89e7-0a76812ff5df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414173178 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2414173178
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.912556357
Short name T694
Test name
Test status
Simulation time 22869350 ps
CPU time 0.98 seconds
Started Jun 26 06:27:37 PM PDT 24
Finished Jun 26 06:27:41 PM PDT 24
Peak memory 218936 kb
Host smart-165a3b88-c964-4062-a4fa-5f507b95131d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912556357 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.912556357
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1940422781
Short name T935
Test name
Test status
Simulation time 62566765 ps
CPU time 2.34 seconds
Started Jun 26 06:27:37 PM PDT 24
Finished Jun 26 06:27:42 PM PDT 24
Peak memory 220476 kb
Host smart-4a9865aa-0fcb-4187-a357-540f5b44980c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940422781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1940422781
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.224157117
Short name T493
Test name
Test status
Simulation time 38604396 ps
CPU time 0.99 seconds
Started Jun 26 06:27:42 PM PDT 24
Finished Jun 26 06:27:44 PM PDT 24
Peak memory 224152 kb
Host smart-a35d3eae-6fb8-46fa-b1fe-6b69be8cada8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224157117 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.224157117
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.701266096
Short name T640
Test name
Test status
Simulation time 19473071 ps
CPU time 0.99 seconds
Started Jun 26 06:27:39 PM PDT 24
Finished Jun 26 06:27:42 PM PDT 24
Peak memory 215652 kb
Host smart-5353d64e-5150-4f1c-880c-31afd3f4453a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701266096 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.701266096
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1144071356
Short name T331
Test name
Test status
Simulation time 189667258 ps
CPU time 2.46 seconds
Started Jun 26 06:27:36 PM PDT 24
Finished Jun 26 06:27:41 PM PDT 24
Peak memory 215644 kb
Host smart-11536ce7-efd2-4936-9976-f2f037ed9469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144071356 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1144071356
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3468547577
Short name T229
Test name
Test status
Simulation time 56103410763 ps
CPU time 1047.12 seconds
Started Jun 26 06:27:37 PM PDT 24
Finished Jun 26 06:45:07 PM PDT 24
Peak memory 222668 kb
Host smart-9aa39829-6bc0-4e9f-851f-1032b2a92582
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468547577 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3468547577
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1342628275
Short name T659
Test name
Test status
Simulation time 67446875 ps
CPU time 1.33 seconds
Started Jun 26 06:29:14 PM PDT 24
Finished Jun 26 06:29:21 PM PDT 24
Peak memory 219152 kb
Host smart-cf2a0047-f5a7-41b0-9cb9-1ecb6ec2cc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342628275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1342628275
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2363339256
Short name T525
Test name
Test status
Simulation time 79911842 ps
CPU time 1.12 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:44 PM PDT 24
Peak memory 217596 kb
Host smart-48aaa700-9253-453b-a32f-1f1e0b00d586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363339256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2363339256
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1446308998
Short name T388
Test name
Test status
Simulation time 69272336 ps
CPU time 1.08 seconds
Started Jun 26 06:29:26 PM PDT 24
Finished Jun 26 06:29:32 PM PDT 24
Peak memory 217576 kb
Host smart-c8923600-5925-4907-b0a8-847606ef558e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446308998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1446308998
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.431014290
Short name T515
Test name
Test status
Simulation time 59196578 ps
CPU time 1.44 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:37 PM PDT 24
Peak memory 220332 kb
Host smart-22ef6318-691c-4f2b-9261-33d0501c5851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431014290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.431014290
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.4178495789
Short name T507
Test name
Test status
Simulation time 34485410 ps
CPU time 1.43 seconds
Started Jun 26 06:29:30 PM PDT 24
Finished Jun 26 06:29:40 PM PDT 24
Peak memory 218728 kb
Host smart-c4db96c4-0bf2-4cac-8918-47c2fa28f6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178495789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.4178495789
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3856753833
Short name T746
Test name
Test status
Simulation time 149028964 ps
CPU time 0.98 seconds
Started Jun 26 06:29:24 PM PDT 24
Finished Jun 26 06:29:30 PM PDT 24
Peak memory 217572 kb
Host smart-27a35cbb-01df-4c9e-b855-c8a00144bbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856753833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3856753833
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3336212511
Short name T242
Test name
Test status
Simulation time 44152150 ps
CPU time 1.35 seconds
Started Jun 26 06:29:26 PM PDT 24
Finished Jun 26 06:29:34 PM PDT 24
Peak memory 217964 kb
Host smart-e0a3eeeb-1dbf-4987-876f-329d57f7c781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336212511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3336212511
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.691977732
Short name T775
Test name
Test status
Simulation time 89435534 ps
CPU time 1.15 seconds
Started Jun 26 06:29:24 PM PDT 24
Finished Jun 26 06:29:29 PM PDT 24
Peak memory 217676 kb
Host smart-4a8f2074-71be-47d2-8892-871254d5b6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691977732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.691977732
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3226342262
Short name T906
Test name
Test status
Simulation time 88497519 ps
CPU time 2.77 seconds
Started Jun 26 06:29:28 PM PDT 24
Finished Jun 26 06:29:44 PM PDT 24
Peak memory 218008 kb
Host smart-5952d9b7-88dc-4726-afd2-e9d430e909d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226342262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3226342262
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.618450023
Short name T39
Test name
Test status
Simulation time 47505869 ps
CPU time 1.51 seconds
Started Jun 26 06:29:20 PM PDT 24
Finished Jun 26 06:29:25 PM PDT 24
Peak memory 218736 kb
Host smart-aa1b51f6-d40e-4003-b8a5-447771409a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618450023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.618450023
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.346091484
Short name T981
Test name
Test status
Simulation time 44201093 ps
CPU time 0.86 seconds
Started Jun 26 06:27:36 PM PDT 24
Finished Jun 26 06:27:40 PM PDT 24
Peak memory 214992 kb
Host smart-298ebc53-4fde-4959-8b09-4db8de2f2c20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346091484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.346091484
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3866487960
Short name T21
Test name
Test status
Simulation time 26284153 ps
CPU time 1.17 seconds
Started Jun 26 06:27:39 PM PDT 24
Finished Jun 26 06:27:43 PM PDT 24
Peak memory 219992 kb
Host smart-d76a278c-daa3-40a2-a4b2-c1f51d5a725b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866487960 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3866487960
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1734477402
Short name T703
Test name
Test status
Simulation time 18399762 ps
CPU time 1.03 seconds
Started Jun 26 06:27:42 PM PDT 24
Finished Jun 26 06:27:44 PM PDT 24
Peak memory 218668 kb
Host smart-1bd88b3a-4bfb-4ce6-a357-c68884025d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734477402 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1734477402
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.799822447
Short name T522
Test name
Test status
Simulation time 37740756 ps
CPU time 1.35 seconds
Started Jun 26 06:27:38 PM PDT 24
Finished Jun 26 06:27:41 PM PDT 24
Peak memory 217600 kb
Host smart-c0e4d4f3-648f-4d64-abb2-0f0b4d658bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799822447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.799822447
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3397411698
Short name T36
Test name
Test status
Simulation time 30604932 ps
CPU time 1 seconds
Started Jun 26 06:27:40 PM PDT 24
Finished Jun 26 06:27:43 PM PDT 24
Peak memory 216112 kb
Host smart-d5ca2b54-0e2d-4cfb-8715-5dd9e6b326ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397411698 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3397411698
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1824634094
Short name T512
Test name
Test status
Simulation time 24706250 ps
CPU time 0.93 seconds
Started Jun 26 06:27:45 PM PDT 24
Finished Jun 26 06:27:47 PM PDT 24
Peak memory 215648 kb
Host smart-0e19877d-4f84-4e00-adc2-31c8d5db212a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824634094 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1824634094
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2915566503
Short name T744
Test name
Test status
Simulation time 225350926 ps
CPU time 4.8 seconds
Started Jun 26 06:27:44 PM PDT 24
Finished Jun 26 06:27:51 PM PDT 24
Peak memory 215668 kb
Host smart-3b81c9c8-7624-426c-91e5-70066040939f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915566503 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2915566503
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3504987977
Short name T38
Test name
Test status
Simulation time 71866700775 ps
CPU time 1575.83 seconds
Started Jun 26 06:27:38 PM PDT 24
Finished Jun 26 06:53:57 PM PDT 24
Peak memory 224308 kb
Host smart-d9123721-41f7-4a84-9470-04256397832a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504987977 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3504987977
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2395036425
Short name T730
Test name
Test status
Simulation time 127338807 ps
CPU time 1.52 seconds
Started Jun 26 06:29:20 PM PDT 24
Finished Jun 26 06:29:25 PM PDT 24
Peak memory 218900 kb
Host smart-f4343292-f9a0-4717-8240-def6f4a19cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395036425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2395036425
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3249116406
Short name T699
Test name
Test status
Simulation time 41231124 ps
CPU time 1.62 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:39 PM PDT 24
Peak memory 218940 kb
Host smart-ae9d6761-8a21-4984-825a-cdcc1831bcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249116406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3249116406
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2328285742
Short name T616
Test name
Test status
Simulation time 92142663 ps
CPU time 1.24 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:37 PM PDT 24
Peak memory 219180 kb
Host smart-09e386b8-5c2c-42c5-9112-f577ec017ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328285742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2328285742
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2286409410
Short name T517
Test name
Test status
Simulation time 33141802 ps
CPU time 1.29 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:38 PM PDT 24
Peak memory 215696 kb
Host smart-8889c77f-d25f-44f4-bc5b-6bdceab9dad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286409410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2286409410
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3644328263
Short name T355
Test name
Test status
Simulation time 72930396 ps
CPU time 1.09 seconds
Started Jun 26 06:29:31 PM PDT 24
Finished Jun 26 06:29:40 PM PDT 24
Peak memory 217716 kb
Host smart-062bd98f-0087-41d1-94bc-5316b3c3237f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644328263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3644328263
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3561117306
Short name T438
Test name
Test status
Simulation time 111052790 ps
CPU time 2.6 seconds
Started Jun 26 06:29:21 PM PDT 24
Finished Jun 26 06:29:27 PM PDT 24
Peak memory 220832 kb
Host smart-43f40499-a3e1-45c6-b168-fcfd0d6f76eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561117306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3561117306
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1483326066
Short name T502
Test name
Test status
Simulation time 73804977 ps
CPU time 1.38 seconds
Started Jun 26 06:29:30 PM PDT 24
Finished Jun 26 06:29:40 PM PDT 24
Peak memory 219068 kb
Host smart-db922661-0831-4375-bd77-447bf4169291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483326066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1483326066
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1272817281
Short name T937
Test name
Test status
Simulation time 48614016 ps
CPU time 1.31 seconds
Started Jun 26 06:29:20 PM PDT 24
Finished Jun 26 06:29:25 PM PDT 24
Peak memory 219404 kb
Host smart-0f07d4bf-922d-4165-a71d-9204b5b147ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272817281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1272817281
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2707236139
Short name T494
Test name
Test status
Simulation time 47989037 ps
CPU time 1.6 seconds
Started Jun 26 06:30:20 PM PDT 24
Finished Jun 26 06:30:25 PM PDT 24
Peak memory 220392 kb
Host smart-7f505d82-cc76-47de-9dec-1303fbbded3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707236139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2707236139
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2163779165
Short name T883
Test name
Test status
Simulation time 57622877 ps
CPU time 1.32 seconds
Started Jun 26 06:29:27 PM PDT 24
Finished Jun 26 06:29:34 PM PDT 24
Peak memory 219108 kb
Host smart-6f064c4d-c12b-4caa-868a-ee6cce798e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163779165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2163779165
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.4190593325
Short name T126
Test name
Test status
Simulation time 77595511 ps
CPU time 1.21 seconds
Started Jun 26 06:27:41 PM PDT 24
Finished Jun 26 06:27:44 PM PDT 24
Peak memory 218772 kb
Host smart-2669528d-24c0-4a3d-aa40-330d6b84e85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190593325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.4190593325
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.485648513
Short name T841
Test name
Test status
Simulation time 174106203 ps
CPU time 0.97 seconds
Started Jun 26 06:27:40 PM PDT 24
Finished Jun 26 06:27:43 PM PDT 24
Peak memory 207132 kb
Host smart-3d99847e-eefd-41cf-b908-c48f04f4f58e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485648513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.485648513
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.4226659828
Short name T178
Test name
Test status
Simulation time 11566332 ps
CPU time 0.89 seconds
Started Jun 26 06:27:43 PM PDT 24
Finished Jun 26 06:27:45 PM PDT 24
Peak memory 216376 kb
Host smart-f83080f6-691c-4bbb-8079-ee3d7baf863a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226659828 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.4226659828
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3679860815
Short name T347
Test name
Test status
Simulation time 197583983 ps
CPU time 1.03 seconds
Started Jun 26 06:27:43 PM PDT 24
Finished Jun 26 06:27:45 PM PDT 24
Peak memory 217172 kb
Host smart-660d4611-119e-4f37-ab90-4e24f7cb3644
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679860815 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3679860815
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3735616063
Short name T55
Test name
Test status
Simulation time 46313950 ps
CPU time 1.08 seconds
Started Jun 26 06:27:38 PM PDT 24
Finished Jun 26 06:27:41 PM PDT 24
Peak memory 224424 kb
Host smart-30526a5e-4017-4779-8c35-e8385278ec6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735616063 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3735616063
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2454886377
Short name T351
Test name
Test status
Simulation time 28587629 ps
CPU time 1.21 seconds
Started Jun 26 06:27:37 PM PDT 24
Finished Jun 26 06:27:41 PM PDT 24
Peak memory 218808 kb
Host smart-1c4b0929-97f5-491d-ad9d-2715e9c935da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454886377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2454886377
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.4028560440
Short name T712
Test name
Test status
Simulation time 20410819 ps
CPU time 1.1 seconds
Started Jun 26 06:27:45 PM PDT 24
Finished Jun 26 06:27:48 PM PDT 24
Peak memory 215652 kb
Host smart-3ba38303-2ee5-4667-900e-41c936978516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028560440 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.4028560440
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1921643174
Short name T518
Test name
Test status
Simulation time 39558242 ps
CPU time 0.98 seconds
Started Jun 26 06:27:37 PM PDT 24
Finished Jun 26 06:27:40 PM PDT 24
Peak memory 215644 kb
Host smart-aacef12c-dc7c-4d30-8c1a-cd689b94735f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921643174 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1921643174
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1814735467
Short name T622
Test name
Test status
Simulation time 394443607 ps
CPU time 3.05 seconds
Started Jun 26 06:27:42 PM PDT 24
Finished Jun 26 06:27:47 PM PDT 24
Peak memory 217460 kb
Host smart-0ccf97db-0073-4481-8362-3e2b75b303e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814735467 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1814735467
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3783059143
Short name T412
Test name
Test status
Simulation time 133464943318 ps
CPU time 866.73 seconds
Started Jun 26 06:27:45 PM PDT 24
Finished Jun 26 06:42:13 PM PDT 24
Peak memory 223748 kb
Host smart-71bf91e6-5f26-4461-beee-e1674335376d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783059143 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3783059143
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.198955369
Short name T467
Test name
Test status
Simulation time 38703463 ps
CPU time 1.38 seconds
Started Jun 26 06:29:19 PM PDT 24
Finished Jun 26 06:29:25 PM PDT 24
Peak memory 219012 kb
Host smart-d337c027-1cfe-4e7b-8402-e552d86dee85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198955369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.198955369
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2564012921
Short name T811
Test name
Test status
Simulation time 116356917 ps
CPU time 3.05 seconds
Started Jun 26 06:29:28 PM PDT 24
Finished Jun 26 06:29:38 PM PDT 24
Peak memory 220876 kb
Host smart-55278368-eb37-410d-8624-c2999657f8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564012921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2564012921
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2057148519
Short name T609
Test name
Test status
Simulation time 71776648 ps
CPU time 1.2 seconds
Started Jun 26 06:29:21 PM PDT 24
Finished Jun 26 06:29:25 PM PDT 24
Peak memory 217688 kb
Host smart-9b2033b6-5d37-4eca-902d-0272862510f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057148519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2057148519
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1248578531
Short name T393
Test name
Test status
Simulation time 31556141 ps
CPU time 1.27 seconds
Started Jun 26 06:29:22 PM PDT 24
Finished Jun 26 06:29:27 PM PDT 24
Peak memory 220252 kb
Host smart-36fe3b7b-16dd-4784-85be-7716eef90dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248578531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1248578531
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.513766774
Short name T584
Test name
Test status
Simulation time 206896207 ps
CPU time 1.72 seconds
Started Jun 26 06:29:23 PM PDT 24
Finished Jun 26 06:29:28 PM PDT 24
Peak memory 219136 kb
Host smart-0d5dee1e-4cd3-450a-abad-be07927a8c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513766774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.513766774
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1523920261
Short name T410
Test name
Test status
Simulation time 26522310 ps
CPU time 1.35 seconds
Started Jun 26 06:29:23 PM PDT 24
Finished Jun 26 06:29:29 PM PDT 24
Peak memory 217672 kb
Host smart-fc7373e0-0323-4bb3-ab9f-a6371d712b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523920261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1523920261
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3293446502
Short name T965
Test name
Test status
Simulation time 92308576 ps
CPU time 2.97 seconds
Started Jun 26 06:29:19 PM PDT 24
Finished Jun 26 06:29:26 PM PDT 24
Peak memory 220180 kb
Host smart-25c3d40b-8c8c-47ed-82da-c781123a11bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293446502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3293446502
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.265957826
Short name T84
Test name
Test status
Simulation time 38864315 ps
CPU time 1.4 seconds
Started Jun 26 06:29:26 PM PDT 24
Finished Jun 26 06:29:40 PM PDT 24
Peak memory 217724 kb
Host smart-b750f876-c47c-40c9-b68b-5476083b7a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265957826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.265957826
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.4167171191
Short name T282
Test name
Test status
Simulation time 79004008 ps
CPU time 1.18 seconds
Started Jun 26 06:29:31 PM PDT 24
Finished Jun 26 06:29:40 PM PDT 24
Peak memory 217952 kb
Host smart-be04ba26-1320-4562-b91e-c4f60ef5b0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167171191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.4167171191
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1254075360
Short name T900
Test name
Test status
Simulation time 139973779 ps
CPU time 2.16 seconds
Started Jun 26 06:29:20 PM PDT 24
Finished Jun 26 06:29:26 PM PDT 24
Peak memory 218092 kb
Host smart-55d37da5-1258-4f6a-beaa-5830c4308f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254075360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1254075360
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2160363252
Short name T8
Test name
Test status
Simulation time 75044387 ps
CPU time 1.22 seconds
Started Jun 26 06:26:55 PM PDT 24
Finished Jun 26 06:26:58 PM PDT 24
Peak memory 219396 kb
Host smart-94faa21e-7aa7-47bb-bcd9-ca65f4e0ffdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160363252 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2160363252
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2915941270
Short name T868
Test name
Test status
Simulation time 51220952 ps
CPU time 0.94 seconds
Started Jun 26 06:26:53 PM PDT 24
Finished Jun 26 06:26:56 PM PDT 24
Peak memory 207064 kb
Host smart-77967f32-3b08-4978-92ed-1f812fd04484
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915941270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2915941270
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2067226212
Short name T385
Test name
Test status
Simulation time 23037837 ps
CPU time 0.91 seconds
Started Jun 26 06:26:56 PM PDT 24
Finished Jun 26 06:26:59 PM PDT 24
Peak memory 216616 kb
Host smart-6ca7f194-acbe-429d-9b7f-02d552e3d27f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067226212 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2067226212
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.690044164
Short name T499
Test name
Test status
Simulation time 106349610 ps
CPU time 1.16 seconds
Started Jun 26 06:26:53 PM PDT 24
Finished Jun 26 06:26:56 PM PDT 24
Peak memory 217152 kb
Host smart-d1a21329-d2af-4392-ae4c-9727a3a04b9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690044164 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.690044164
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3931413551
Short name T794
Test name
Test status
Simulation time 23142132 ps
CPU time 1.04 seconds
Started Jun 26 06:26:53 PM PDT 24
Finished Jun 26 06:26:56 PM PDT 24
Peak memory 229812 kb
Host smart-68ebccd3-8360-4ea6-b6a7-8c6e6f6f03e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931413551 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3931413551
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.4097574392
Short name T653
Test name
Test status
Simulation time 38215196 ps
CPU time 1.31 seconds
Started Jun 26 06:26:55 PM PDT 24
Finished Jun 26 06:26:58 PM PDT 24
Peak memory 218936 kb
Host smart-07dc5677-ef89-42d0-a3b0-ae8101022d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097574392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.4097574392
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.999772980
Short name T245
Test name
Test status
Simulation time 22301628 ps
CPU time 1.15 seconds
Started Jun 26 06:26:53 PM PDT 24
Finished Jun 26 06:26:55 PM PDT 24
Peak memory 215740 kb
Host smart-46d13fc8-5a4b-472f-ae1c-b71aca26a70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999772980 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.999772980
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1363239795
Short name T803
Test name
Test status
Simulation time 16048776 ps
CPU time 1.05 seconds
Started Jun 26 06:26:57 PM PDT 24
Finished Jun 26 06:26:59 PM PDT 24
Peak memory 207484 kb
Host smart-40df38e9-02fb-479e-a1ff-1a18cc136886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363239795 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1363239795
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1957064017
Short name T16
Test name
Test status
Simulation time 495151937 ps
CPU time 4.26 seconds
Started Jun 26 06:26:54 PM PDT 24
Finished Jun 26 06:27:00 PM PDT 24
Peak memory 235532 kb
Host smart-b99dd0ce-5604-4b69-9130-cdf9aa48d0a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957064017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1957064017
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.154043020
Short name T358
Test name
Test status
Simulation time 23364050 ps
CPU time 0.9 seconds
Started Jun 26 06:26:57 PM PDT 24
Finished Jun 26 06:26:59 PM PDT 24
Peak memory 215624 kb
Host smart-3a72811d-3f17-46c6-862a-71bbd0eddbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154043020 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.154043020
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3541742973
Short name T197
Test name
Test status
Simulation time 344520963 ps
CPU time 2.45 seconds
Started Jun 26 06:26:56 PM PDT 24
Finished Jun 26 06:27:00 PM PDT 24
Peak memory 215612 kb
Host smart-a7715367-c6d5-4dea-9fbd-078cde641522
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541742973 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3541742973
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.578693532
Short name T231
Test name
Test status
Simulation time 263214250241 ps
CPU time 613.07 seconds
Started Jun 26 06:26:55 PM PDT 24
Finished Jun 26 06:37:10 PM PDT 24
Peak memory 228144 kb
Host smart-acfcfdd5-41f4-4a0e-8c76-6cc3f6f4f27f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578693532 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.578693532
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.4095928496
Short name T634
Test name
Test status
Simulation time 26036282 ps
CPU time 1.2 seconds
Started Jun 26 06:27:38 PM PDT 24
Finished Jun 26 06:27:41 PM PDT 24
Peak memory 219056 kb
Host smart-f40cb986-9a23-422f-a3fe-b3f5bb21c58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095928496 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.4095928496
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3167556573
Short name T966
Test name
Test status
Simulation time 55905671 ps
CPU time 0.98 seconds
Started Jun 26 06:27:39 PM PDT 24
Finished Jun 26 06:27:42 PM PDT 24
Peak memory 215476 kb
Host smart-f021887a-b0ad-4a63-b1c1-1ae8713a331f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167556573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3167556573
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2613359790
Short name T989
Test name
Test status
Simulation time 70757387 ps
CPU time 1.14 seconds
Started Jun 26 06:27:39 PM PDT 24
Finished Jun 26 06:27:42 PM PDT 24
Peak memory 217368 kb
Host smart-1053958f-c8b6-499d-9bbf-f4c9fe6de4e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613359790 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2613359790
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3246649721
Short name T209
Test name
Test status
Simulation time 98967446 ps
CPU time 1.07 seconds
Started Jun 26 06:27:45 PM PDT 24
Finished Jun 26 06:27:48 PM PDT 24
Peak memory 215720 kb
Host smart-16817dd0-039f-4352-863d-c8cef521ec3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246649721 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3246649721
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1463991304
Short name T300
Test name
Test status
Simulation time 88188803 ps
CPU time 1.36 seconds
Started Jun 26 06:27:39 PM PDT 24
Finished Jun 26 06:27:42 PM PDT 24
Peak memory 219192 kb
Host smart-64c8272c-59a7-42ce-8c27-def4ccfa364b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463991304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1463991304
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.781629394
Short name T540
Test name
Test status
Simulation time 35157367 ps
CPU time 1.01 seconds
Started Jun 26 06:27:42 PM PDT 24
Finished Jun 26 06:27:45 PM PDT 24
Peak memory 224384 kb
Host smart-0ece4562-790a-4071-9a9f-14898eafc5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781629394 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.781629394
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1150012932
Short name T957
Test name
Test status
Simulation time 17500273 ps
CPU time 0.97 seconds
Started Jun 26 06:27:41 PM PDT 24
Finished Jun 26 06:27:44 PM PDT 24
Peak memory 215628 kb
Host smart-def87b59-8ea2-4383-889b-282823ace9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150012932 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1150012932
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1477447918
Short name T239
Test name
Test status
Simulation time 524408156 ps
CPU time 5.11 seconds
Started Jun 26 06:27:45 PM PDT 24
Finished Jun 26 06:27:51 PM PDT 24
Peak memory 218860 kb
Host smart-0cff671f-ef97-44eb-8b46-d065b3e79831
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477447918 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1477447918
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2661302702
Short name T867
Test name
Test status
Simulation time 829934905535 ps
CPU time 2500.58 seconds
Started Jun 26 06:27:35 PM PDT 24
Finished Jun 26 07:09:19 PM PDT 24
Peak memory 228884 kb
Host smart-0f9c8c36-46a4-4afc-b948-f46187bab76e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661302702 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2661302702
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.104034650
Short name T93
Test name
Test status
Simulation time 47019776 ps
CPU time 1.22 seconds
Started Jun 26 06:27:51 PM PDT 24
Finished Jun 26 06:27:53 PM PDT 24
Peak memory 218876 kb
Host smart-6e700856-d0b6-4b96-92bc-3c1fb48f43b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104034650 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.104034650
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3825925814
Short name T710
Test name
Test status
Simulation time 57021248 ps
CPU time 0.89 seconds
Started Jun 26 06:27:43 PM PDT 24
Finished Jun 26 06:27:45 PM PDT 24
Peak memory 207056 kb
Host smart-bf2da40a-5946-4b4c-bf5c-f79e7780aa71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825925814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3825925814
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2431023221
Short name T158
Test name
Test status
Simulation time 18626317 ps
CPU time 0.85 seconds
Started Jun 26 06:27:55 PM PDT 24
Finished Jun 26 06:27:57 PM PDT 24
Peak memory 216496 kb
Host smart-624d2e85-5c60-4fef-8732-8a00a7dc1ef7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431023221 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2431023221
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2627095093
Short name T348
Test name
Test status
Simulation time 33183310 ps
CPU time 1.31 seconds
Started Jun 26 06:27:45 PM PDT 24
Finished Jun 26 06:27:48 PM PDT 24
Peak memory 218996 kb
Host smart-74aa2ca6-5493-474b-9451-42ccbcaf4868
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627095093 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2627095093
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1711367948
Short name T7
Test name
Test status
Simulation time 124885027 ps
CPU time 1.11 seconds
Started Jun 26 06:27:45 PM PDT 24
Finished Jun 26 06:27:48 PM PDT 24
Peak memory 219844 kb
Host smart-fbe06b16-9b8c-4e2a-ab12-701ff5e0269c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711367948 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1711367948
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2888708567
Short name T793
Test name
Test status
Simulation time 45328494 ps
CPU time 1.51 seconds
Started Jun 26 06:27:38 PM PDT 24
Finished Jun 26 06:27:42 PM PDT 24
Peak memory 218980 kb
Host smart-17057594-ec0d-46b1-a667-1e93b62c1077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888708567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2888708567
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2303129364
Short name T405
Test name
Test status
Simulation time 22470459 ps
CPU time 1.2 seconds
Started Jun 26 06:27:46 PM PDT 24
Finished Jun 26 06:27:49 PM PDT 24
Peak memory 224332 kb
Host smart-944e9039-d249-420c-bd6d-04915e908fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303129364 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2303129364
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1290902822
Short name T578
Test name
Test status
Simulation time 31121217 ps
CPU time 0.95 seconds
Started Jun 26 06:27:45 PM PDT 24
Finished Jun 26 06:27:48 PM PDT 24
Peak memory 215524 kb
Host smart-ca4f5b05-2816-4e53-98c1-61d8a31b5550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290902822 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1290902822
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3242335936
Short name T779
Test name
Test status
Simulation time 45798302 ps
CPU time 1.29 seconds
Started Jun 26 06:27:39 PM PDT 24
Finished Jun 26 06:27:43 PM PDT 24
Peak memory 217460 kb
Host smart-375350a2-678d-4d0f-8d1a-7452d85cf838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242335936 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3242335936
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2484564223
Short name T532
Test name
Test status
Simulation time 16294298335 ps
CPU time 402.5 seconds
Started Jun 26 06:27:46 PM PDT 24
Finished Jun 26 06:34:31 PM PDT 24
Peak memory 218684 kb
Host smart-2716163d-9eed-468f-a25f-8e7b944f45b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484564223 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2484564223
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3115344981
Short name T621
Test name
Test status
Simulation time 25237745 ps
CPU time 1.28 seconds
Started Jun 26 06:27:44 PM PDT 24
Finished Jun 26 06:27:47 PM PDT 24
Peak memory 218860 kb
Host smart-88a3b7de-7e42-4d36-9e2c-42b65127f8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115344981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3115344981
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3829295531
Short name T406
Test name
Test status
Simulation time 12820212 ps
CPU time 0.9 seconds
Started Jun 26 06:27:46 PM PDT 24
Finished Jun 26 06:27:49 PM PDT 24
Peak memory 215200 kb
Host smart-ba3f5367-d4da-4642-862e-331b4d8da90b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829295531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3829295531
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1712370745
Short name T967
Test name
Test status
Simulation time 106575522 ps
CPU time 1.06 seconds
Started Jun 26 06:27:44 PM PDT 24
Finished Jun 26 06:27:47 PM PDT 24
Peak memory 217108 kb
Host smart-d60fb42c-4895-480c-b30c-052964cf51f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712370745 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1712370745
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.510879027
Short name T456
Test name
Test status
Simulation time 138535372 ps
CPU time 1 seconds
Started Jun 26 06:27:55 PM PDT 24
Finished Jun 26 06:27:57 PM PDT 24
Peak memory 220848 kb
Host smart-ac25336c-76b7-4fd2-a526-6e973618f86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510879027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.510879027
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3064572112
Short name T474
Test name
Test status
Simulation time 44325197 ps
CPU time 1.17 seconds
Started Jun 26 06:27:43 PM PDT 24
Finished Jun 26 06:27:45 PM PDT 24
Peak memory 219124 kb
Host smart-bd9d72e7-5b8d-44b2-9232-cec77be18bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064572112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3064572112
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2332144344
Short name T35
Test name
Test status
Simulation time 48175511 ps
CPU time 0.92 seconds
Started Jun 26 06:27:45 PM PDT 24
Finished Jun 26 06:27:47 PM PDT 24
Peak memory 215916 kb
Host smart-8e3396fd-eff6-4323-8b8e-1c62404fe9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332144344 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2332144344
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.91575171
Short name T472
Test name
Test status
Simulation time 43157205 ps
CPU time 0.91 seconds
Started Jun 26 06:27:43 PM PDT 24
Finished Jun 26 06:27:46 PM PDT 24
Peak memory 215620 kb
Host smart-f8798964-c421-4af7-800f-3e9de6b41aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91575171 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.91575171
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3974580449
Short name T815
Test name
Test status
Simulation time 359664892 ps
CPU time 2.31 seconds
Started Jun 26 06:27:51 PM PDT 24
Finished Jun 26 06:27:54 PM PDT 24
Peak memory 217548 kb
Host smart-d72ed610-a4d6-4c4a-84ea-b0e0b74bbbaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974580449 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3974580449
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1743548111
Short name T226
Test name
Test status
Simulation time 196322886143 ps
CPU time 1049.56 seconds
Started Jun 26 06:28:01 PM PDT 24
Finished Jun 26 06:45:32 PM PDT 24
Peak memory 221816 kb
Host smart-3fbebda9-97fa-4271-8ced-25dbedbabdf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743548111 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1743548111
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.107852184
Short name T919
Test name
Test status
Simulation time 48977423 ps
CPU time 1.15 seconds
Started Jun 26 06:27:55 PM PDT 24
Finished Jun 26 06:27:57 PM PDT 24
Peak memory 218828 kb
Host smart-c4a84edf-48a6-4a06-8d67-deb9a5c58c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107852184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.107852184
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.754097710
Short name T869
Test name
Test status
Simulation time 51549800 ps
CPU time 0.89 seconds
Started Jun 26 06:27:43 PM PDT 24
Finished Jun 26 06:27:46 PM PDT 24
Peak memory 215188 kb
Host smart-49ad1c41-2f4c-4ca5-9513-e1c1c9620bcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754097710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.754097710
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1237276583
Short name T847
Test name
Test status
Simulation time 10081761 ps
CPU time 0.84 seconds
Started Jun 26 06:27:55 PM PDT 24
Finished Jun 26 06:27:57 PM PDT 24
Peak memory 216592 kb
Host smart-feb66c50-c4e2-40d3-a4d8-80991e0628c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237276583 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1237276583
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2771246360
Short name T912
Test name
Test status
Simulation time 50570101 ps
CPU time 1.62 seconds
Started Jun 26 06:27:47 PM PDT 24
Finished Jun 26 06:27:50 PM PDT 24
Peak memory 217224 kb
Host smart-d7c64c2a-8fd1-414d-941f-ab8c6af33631
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771246360 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2771246360
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_genbits.286988519
Short name T979
Test name
Test status
Simulation time 60190089 ps
CPU time 1.05 seconds
Started Jun 26 06:27:52 PM PDT 24
Finished Jun 26 06:27:54 PM PDT 24
Peak memory 219296 kb
Host smart-74c4e4ad-909b-4c2f-add4-e71079a2a4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286988519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.286988519
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3517132233
Short name T920
Test name
Test status
Simulation time 22451831 ps
CPU time 1.08 seconds
Started Jun 26 06:27:43 PM PDT 24
Finished Jun 26 06:27:45 PM PDT 24
Peak memory 215916 kb
Host smart-0dbf5622-701d-49a5-85a5-a63119a9b042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517132233 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3517132233
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2456148593
Short name T655
Test name
Test status
Simulation time 16659352 ps
CPU time 1.01 seconds
Started Jun 26 06:27:43 PM PDT 24
Finished Jun 26 06:27:46 PM PDT 24
Peak memory 215652 kb
Host smart-e37b3831-07e9-442c-89c0-ba16d143bd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456148593 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2456148593
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1107405221
Short name T308
Test name
Test status
Simulation time 189423255 ps
CPU time 4.14 seconds
Started Jun 26 06:27:52 PM PDT 24
Finished Jun 26 06:27:57 PM PDT 24
Peak memory 217576 kb
Host smart-950377a0-4734-4c97-b47e-85bee44afcbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107405221 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1107405221
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3827049397
Short name T60
Test name
Test status
Simulation time 98353913357 ps
CPU time 525.31 seconds
Started Jun 26 06:27:52 PM PDT 24
Finished Jun 26 06:36:38 PM PDT 24
Peak memory 224072 kb
Host smart-c5b65dd7-3579-46f2-80c6-e27a1ea6bd18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827049397 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3827049397
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.4108936003
Short name T601
Test name
Test status
Simulation time 104532604 ps
CPU time 1.02 seconds
Started Jun 26 06:27:55 PM PDT 24
Finished Jun 26 06:27:57 PM PDT 24
Peak memory 219980 kb
Host smart-2964291d-af29-470f-89e6-94c76ecfa35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108936003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.4108936003
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.146634529
Short name T402
Test name
Test status
Simulation time 33276440 ps
CPU time 1.02 seconds
Started Jun 26 06:27:54 PM PDT 24
Finished Jun 26 06:27:56 PM PDT 24
Peak memory 207060 kb
Host smart-afe7c4fc-b658-42be-ac03-0235ba589f9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146634529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.146634529
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.444997201
Short name T695
Test name
Test status
Simulation time 48708446 ps
CPU time 1.17 seconds
Started Jun 26 06:27:52 PM PDT 24
Finished Jun 26 06:27:54 PM PDT 24
Peak memory 217284 kb
Host smart-d1baa8ce-bf32-49cb-8f91-4d4172fae3ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444997201 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_di
sable_auto_req_mode.444997201
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.652220143
Short name T927
Test name
Test status
Simulation time 25102904 ps
CPU time 1.36 seconds
Started Jun 26 06:27:51 PM PDT 24
Finished Jun 26 06:27:54 PM PDT 24
Peak memory 232728 kb
Host smart-0c8a21fd-93e2-47ba-a56e-c88ad902c811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652220143 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.652220143
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.558264595
Short name T281
Test name
Test status
Simulation time 60863168 ps
CPU time 1.49 seconds
Started Jun 26 06:27:46 PM PDT 24
Finished Jun 26 06:27:49 PM PDT 24
Peak memory 215660 kb
Host smart-a53617e7-69d7-48d8-abff-ece1f3cc24b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558264595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.558264595
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.160307278
Short name T892
Test name
Test status
Simulation time 27431299 ps
CPU time 1.08 seconds
Started Jun 26 06:27:51 PM PDT 24
Finished Jun 26 06:27:53 PM PDT 24
Peak memory 224480 kb
Host smart-522a7095-d008-48cb-a8e4-418fb7752446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160307278 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.160307278
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1634824543
Short name T396
Test name
Test status
Simulation time 28697627 ps
CPU time 0.96 seconds
Started Jun 26 06:27:44 PM PDT 24
Finished Jun 26 06:27:46 PM PDT 24
Peak memory 215656 kb
Host smart-642f0b16-b33c-4af0-891e-d3a845766aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634824543 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1634824543
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.231072653
Short name T462
Test name
Test status
Simulation time 994941790 ps
CPU time 5.61 seconds
Started Jun 26 06:27:44 PM PDT 24
Finished Jun 26 06:27:51 PM PDT 24
Peak memory 215952 kb
Host smart-615fdfb6-5979-425f-8a07-58fcb1c3dfc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231072653 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.231072653
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2709938777
Short name T400
Test name
Test status
Simulation time 26432530348 ps
CPU time 653.16 seconds
Started Jun 26 06:27:44 PM PDT 24
Finished Jun 26 06:38:39 PM PDT 24
Peak memory 220900 kb
Host smart-f3f2494a-3330-4da9-a4a2-684c5b87afbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709938777 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2709938777
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.270959162
Short name T856
Test name
Test status
Simulation time 80169001 ps
CPU time 1.24 seconds
Started Jun 26 06:27:54 PM PDT 24
Finished Jun 26 06:27:56 PM PDT 24
Peak memory 221584 kb
Host smart-8498c123-d3f4-4299-ac68-9ec5c50266b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270959162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.270959162
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2759454071
Short name T427
Test name
Test status
Simulation time 31017135 ps
CPU time 0.88 seconds
Started Jun 26 06:27:51 PM PDT 24
Finished Jun 26 06:27:53 PM PDT 24
Peak memory 206860 kb
Host smart-c5445a51-9075-413a-8565-56d2af29b431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759454071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2759454071
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.451592959
Short name T990
Test name
Test status
Simulation time 37513368 ps
CPU time 0.84 seconds
Started Jun 26 06:27:56 PM PDT 24
Finished Jun 26 06:27:58 PM PDT 24
Peak memory 216376 kb
Host smart-d7f66461-4013-470f-b6d3-fe1bc420f034
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451592959 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.451592959
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3910216421
Short name T116
Test name
Test status
Simulation time 61241719 ps
CPU time 1.2 seconds
Started Jun 26 06:27:55 PM PDT 24
Finished Jun 26 06:27:58 PM PDT 24
Peak memory 217248 kb
Host smart-115bb36b-f879-4053-baaa-1682094c747c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910216421 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3910216421
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2928195898
Short name T471
Test name
Test status
Simulation time 18415548 ps
CPU time 1.06 seconds
Started Jun 26 06:27:53 PM PDT 24
Finished Jun 26 06:27:55 PM PDT 24
Peak memory 215804 kb
Host smart-a4f75662-62a8-4f05-895f-34f926fcc497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928195898 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2928195898
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3484677768
Short name T797
Test name
Test status
Simulation time 129128457 ps
CPU time 2.76 seconds
Started Jun 26 06:27:52 PM PDT 24
Finished Jun 26 06:27:56 PM PDT 24
Peak memory 220584 kb
Host smart-50cae2d3-4933-4bf6-9ce3-a4e6d5c7b98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484677768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3484677768
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2810794784
Short name T745
Test name
Test status
Simulation time 22660165 ps
CPU time 0.89 seconds
Started Jun 26 06:27:54 PM PDT 24
Finished Jun 26 06:27:55 PM PDT 24
Peak memory 216096 kb
Host smart-9ef4b966-afbc-4efd-830a-aa3c4265fe22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810794784 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2810794784
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.714927240
Short name T929
Test name
Test status
Simulation time 27291122 ps
CPU time 0.94 seconds
Started Jun 26 06:27:56 PM PDT 24
Finished Jun 26 06:27:58 PM PDT 24
Peak memory 215560 kb
Host smart-4da5c746-a90f-4a93-8a4e-ffb88ad91ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714927240 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.714927240
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.791384771
Short name T787
Test name
Test status
Simulation time 1348592453 ps
CPU time 5.93 seconds
Started Jun 26 06:27:54 PM PDT 24
Finished Jun 26 06:28:01 PM PDT 24
Peak memory 217792 kb
Host smart-2b874dad-818b-4833-979f-bd9c1fc037fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791384771 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.791384771
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.132004291
Short name T404
Test name
Test status
Simulation time 60731066290 ps
CPU time 709.24 seconds
Started Jun 26 06:27:51 PM PDT 24
Finished Jun 26 06:39:42 PM PDT 24
Peak memory 224032 kb
Host smart-746a2010-9564-408d-90a4-6716bd59f5c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132004291 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.132004291
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3195675168
Short name T614
Test name
Test status
Simulation time 63843768 ps
CPU time 1.27 seconds
Started Jun 26 06:27:54 PM PDT 24
Finished Jun 26 06:27:56 PM PDT 24
Peak memory 220656 kb
Host smart-6e3f2391-0b5f-436d-b51d-ee05024db11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195675168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3195675168
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.322714148
Short name T702
Test name
Test status
Simulation time 13004646 ps
CPU time 0.89 seconds
Started Jun 26 06:28:06 PM PDT 24
Finished Jun 26 06:28:08 PM PDT 24
Peak memory 207044 kb
Host smart-d077bd05-b7c2-46a1-ab37-538a2c0a9240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322714148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.322714148
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.4093145977
Short name T784
Test name
Test status
Simulation time 39766061 ps
CPU time 0.86 seconds
Started Jun 26 06:27:54 PM PDT 24
Finished Jun 26 06:27:56 PM PDT 24
Peak memory 216676 kb
Host smart-e82432cd-93d0-41af-bdc6-593992e35a0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093145977 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.4093145977
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1892934836
Short name T123
Test name
Test status
Simulation time 35074374 ps
CPU time 1.25 seconds
Started Jun 26 06:27:53 PM PDT 24
Finished Jun 26 06:27:56 PM PDT 24
Peak memory 217400 kb
Host smart-e0253407-53a2-41d8-abba-a2f946f8cc02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892934836 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1892934836
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2918857969
Short name T32
Test name
Test status
Simulation time 25230082 ps
CPU time 0.95 seconds
Started Jun 26 06:27:53 PM PDT 24
Finished Jun 26 06:27:55 PM PDT 24
Peak memory 219664 kb
Host smart-698634dd-ecad-4156-bb8f-e60eb3f6c6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918857969 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2918857969
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3903156112
Short name T582
Test name
Test status
Simulation time 349784907 ps
CPU time 2.12 seconds
Started Jun 26 06:27:52 PM PDT 24
Finished Jun 26 06:27:55 PM PDT 24
Peak memory 219628 kb
Host smart-be47247a-e2e3-41b7-add3-227fb23e86df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903156112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3903156112
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2460335992
Short name T97
Test name
Test status
Simulation time 36105709 ps
CPU time 0.9 seconds
Started Jun 26 06:27:52 PM PDT 24
Finished Jun 26 06:27:54 PM PDT 24
Peak memory 215688 kb
Host smart-2ae892e0-7939-4f0e-b9ca-a7992079dab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460335992 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2460335992
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2056320811
Short name T992
Test name
Test status
Simulation time 43033678 ps
CPU time 0.9 seconds
Started Jun 26 06:27:56 PM PDT 24
Finished Jun 26 06:27:58 PM PDT 24
Peak memory 215624 kb
Host smart-8c4449b9-87d8-48b6-892f-1a9c22c07b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056320811 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2056320811
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.4017519441
Short name T482
Test name
Test status
Simulation time 132384364 ps
CPU time 2.88 seconds
Started Jun 26 06:27:56 PM PDT 24
Finished Jun 26 06:28:00 PM PDT 24
Peak memory 217428 kb
Host smart-3e51125c-d7bd-433f-8ea8-dba2d2b8ed02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017519441 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.4017519441
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.484074381
Short name T985
Test name
Test status
Simulation time 28310206446 ps
CPU time 313.71 seconds
Started Jun 26 06:27:56 PM PDT 24
Finished Jun 26 06:33:11 PM PDT 24
Peak memory 216892 kb
Host smart-a8c8016c-9726-4d12-95cb-fe99b7db4fdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484074381 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.484074381
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.599408549
Short name T458
Test name
Test status
Simulation time 42450301 ps
CPU time 1.11 seconds
Started Jun 26 06:28:04 PM PDT 24
Finished Jun 26 06:28:07 PM PDT 24
Peak memory 218824 kb
Host smart-74e602fd-519e-45f9-9a72-5c8392f38830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599408549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.599408549
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.644198235
Short name T600
Test name
Test status
Simulation time 19661816 ps
CPU time 1.04 seconds
Started Jun 26 06:28:03 PM PDT 24
Finished Jun 26 06:28:05 PM PDT 24
Peak memory 215512 kb
Host smart-00e1a165-8132-4cdc-b77f-14289c3fe369
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644198235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.644198235
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2471002700
Short name T692
Test name
Test status
Simulation time 13033147 ps
CPU time 0.92 seconds
Started Jun 26 06:28:01 PM PDT 24
Finished Jun 26 06:28:03 PM PDT 24
Peak memory 215984 kb
Host smart-08adc6b8-1d73-4439-85a0-71472a7b3bf9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471002700 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2471002700
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1760147734
Short name T771
Test name
Test status
Simulation time 164632604 ps
CPU time 1.14 seconds
Started Jun 26 06:28:01 PM PDT 24
Finished Jun 26 06:28:03 PM PDT 24
Peak memory 219064 kb
Host smart-e00955c5-b0cc-42a0-865c-167c24164c16
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760147734 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1760147734
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.687430056
Short name T113
Test name
Test status
Simulation time 32953572 ps
CPU time 1.05 seconds
Started Jun 26 06:28:00 PM PDT 24
Finished Jun 26 06:28:02 PM PDT 24
Peak memory 230004 kb
Host smart-39ec7c79-b181-49d2-9d12-0cffb724307d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687430056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.687430056
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2876958344
Short name T910
Test name
Test status
Simulation time 54090080 ps
CPU time 1.81 seconds
Started Jun 26 06:28:03 PM PDT 24
Finished Jun 26 06:28:05 PM PDT 24
Peak memory 218832 kb
Host smart-e0ad0f89-409a-428b-9f67-e69896c9ae8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876958344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2876958344
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1848376963
Short name T753
Test name
Test status
Simulation time 24830250 ps
CPU time 1.01 seconds
Started Jun 26 06:28:05 PM PDT 24
Finished Jun 26 06:28:08 PM PDT 24
Peak memory 215784 kb
Host smart-28dffaea-8d7f-4457-861f-6fdf321e0f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848376963 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1848376963
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3343679491
Short name T496
Test name
Test status
Simulation time 38660604 ps
CPU time 0.95 seconds
Started Jun 26 06:28:07 PM PDT 24
Finished Jun 26 06:28:09 PM PDT 24
Peak memory 215640 kb
Host smart-38f691fd-9aba-437d-b612-c60ba9a3a5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343679491 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3343679491
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2287805073
Short name T67
Test name
Test status
Simulation time 159761382 ps
CPU time 3.52 seconds
Started Jun 26 06:27:59 PM PDT 24
Finished Jun 26 06:28:03 PM PDT 24
Peak memory 215608 kb
Host smart-dd9ca126-d981-4ad0-bf47-b3b068648078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287805073 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2287805073
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3768098771
Short name T464
Test name
Test status
Simulation time 85312940200 ps
CPU time 969.23 seconds
Started Jun 26 06:28:00 PM PDT 24
Finished Jun 26 06:44:11 PM PDT 24
Peak memory 224148 kb
Host smart-08bcc0da-0aae-4b88-84a9-18e3d8d559fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768098771 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3768098771
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3341180590
Short name T873
Test name
Test status
Simulation time 87578056 ps
CPU time 1.26 seconds
Started Jun 26 06:28:06 PM PDT 24
Finished Jun 26 06:28:09 PM PDT 24
Peak memory 220800 kb
Host smart-4b65aa6e-2d49-4bd8-b21f-f947a4d03722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341180590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3341180590
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.639851164
Short name T669
Test name
Test status
Simulation time 28297661 ps
CPU time 0.96 seconds
Started Jun 26 06:27:59 PM PDT 24
Finished Jun 26 06:28:01 PM PDT 24
Peak memory 207036 kb
Host smart-e6c64770-fcf1-46e3-9732-05a19cc0f77c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639851164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.639851164
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.584515878
Short name T644
Test name
Test status
Simulation time 13697936 ps
CPU time 0.94 seconds
Started Jun 26 06:28:24 PM PDT 24
Finished Jun 26 06:28:27 PM PDT 24
Peak memory 215860 kb
Host smart-46afac31-09a2-4469-828d-fb221ff87e18
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584515878 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.584515878
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3750316063
Short name T91
Test name
Test status
Simulation time 141277177 ps
CPU time 1.14 seconds
Started Jun 26 06:28:05 PM PDT 24
Finished Jun 26 06:28:08 PM PDT 24
Peak memory 217260 kb
Host smart-a0a73f48-0365-47c2-ad26-cb19d3d6c882
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750316063 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3750316063
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3416604685
Short name T106
Test name
Test status
Simulation time 33253187 ps
CPU time 1 seconds
Started Jun 26 06:28:04 PM PDT 24
Finished Jun 26 06:28:07 PM PDT 24
Peak memory 230016 kb
Host smart-93e9b722-e29a-424b-bbba-c8e5966d845a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416604685 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3416604685
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.226913350
Short name T565
Test name
Test status
Simulation time 58330356 ps
CPU time 1.63 seconds
Started Jun 26 06:28:05 PM PDT 24
Finished Jun 26 06:28:07 PM PDT 24
Peak memory 220496 kb
Host smart-eabaeedb-3704-42ba-80d2-566cf3ce222e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226913350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.226913350
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_smoke.3247158490
Short name T608
Test name
Test status
Simulation time 18829576 ps
CPU time 1 seconds
Started Jun 26 06:28:02 PM PDT 24
Finished Jun 26 06:28:04 PM PDT 24
Peak memory 215592 kb
Host smart-c55f5d7a-7ec3-4b68-a20e-a9a08ad000f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247158490 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3247158490
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3131268087
Short name T446
Test name
Test status
Simulation time 370274682 ps
CPU time 2.06 seconds
Started Jun 26 06:28:00 PM PDT 24
Finished Jun 26 06:28:03 PM PDT 24
Peak memory 220020 kb
Host smart-3ccb5752-b904-4907-8039-c5f0c4ed0689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131268087 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3131268087
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3226304095
Short name T949
Test name
Test status
Simulation time 71895481626 ps
CPU time 606.55 seconds
Started Jun 26 06:28:05 PM PDT 24
Finished Jun 26 06:38:13 PM PDT 24
Peak memory 224044 kb
Host smart-8f67ff33-1075-4949-93c4-c4e6785f2de7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226304095 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3226304095
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2955577504
Short name T766
Test name
Test status
Simulation time 27479427 ps
CPU time 1.26 seconds
Started Jun 26 06:28:07 PM PDT 24
Finished Jun 26 06:28:10 PM PDT 24
Peak memory 218956 kb
Host smart-11b59417-501e-4d83-a75e-9d8f5f133881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955577504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2955577504
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1200424658
Short name T571
Test name
Test status
Simulation time 30397928 ps
CPU time 1.01 seconds
Started Jun 26 06:28:06 PM PDT 24
Finished Jun 26 06:28:08 PM PDT 24
Peak memory 207088 kb
Host smart-38f34b86-4d97-444b-9858-9dbd7f686d89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200424658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1200424658
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2162021795
Short name T597
Test name
Test status
Simulation time 13377345 ps
CPU time 0.95 seconds
Started Jun 26 06:28:05 PM PDT 24
Finished Jun 26 06:28:08 PM PDT 24
Peak memory 216404 kb
Host smart-a5e56118-7735-404b-be90-fa18225de7f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162021795 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2162021795
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.874487199
Short name T205
Test name
Test status
Simulation time 141530591 ps
CPU time 1.14 seconds
Started Jun 26 06:28:16 PM PDT 24
Finished Jun 26 06:28:18 PM PDT 24
Peak memory 217268 kb
Host smart-9b1043f2-5c5c-4e63-a9d7-443ffed3fdea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874487199 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.874487199
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1331003716
Short name T129
Test name
Test status
Simulation time 25168764 ps
CPU time 1.32 seconds
Started Jun 26 06:28:01 PM PDT 24
Finished Jun 26 06:28:03 PM PDT 24
Peak memory 229932 kb
Host smart-608a908f-dded-40f8-a3fb-60d4464f6668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331003716 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1331003716
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1386619114
Short name T557
Test name
Test status
Simulation time 148641197 ps
CPU time 1.26 seconds
Started Jun 26 06:28:00 PM PDT 24
Finished Jun 26 06:28:02 PM PDT 24
Peak memory 217528 kb
Host smart-60462428-1b5e-43c0-b1d5-fdc91bc063e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386619114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1386619114
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2370368303
Short name T607
Test name
Test status
Simulation time 27698285 ps
CPU time 1.17 seconds
Started Jun 26 06:28:04 PM PDT 24
Finished Jun 26 06:28:06 PM PDT 24
Peak memory 224328 kb
Host smart-44883978-7169-46aa-95d1-f79a80a08359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370368303 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2370368303
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.700747797
Short name T338
Test name
Test status
Simulation time 30377863 ps
CPU time 0.99 seconds
Started Jun 26 06:27:59 PM PDT 24
Finished Jun 26 06:28:01 PM PDT 24
Peak memory 215624 kb
Host smart-577e48a2-f090-420b-8920-f5f7b20ecd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700747797 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.700747797
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.4211866079
Short name T840
Test name
Test status
Simulation time 854137291 ps
CPU time 5.03 seconds
Started Jun 26 06:28:01 PM PDT 24
Finished Jun 26 06:28:07 PM PDT 24
Peak memory 217556 kb
Host smart-5a43819f-900d-4fa5-878e-028cb4aa48fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211866079 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.4211866079
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3946297300
Short name T298
Test name
Test status
Simulation time 217848691855 ps
CPU time 1461.54 seconds
Started Jun 26 06:28:05 PM PDT 24
Finished Jun 26 06:52:27 PM PDT 24
Peak memory 225364 kb
Host smart-43589af8-95c4-4edb-817d-a41b39b6571a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946297300 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3946297300
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3225012786
Short name T546
Test name
Test status
Simulation time 29076553 ps
CPU time 1.3 seconds
Started Jun 26 06:27:00 PM PDT 24
Finished Jun 26 06:27:02 PM PDT 24
Peak memory 220164 kb
Host smart-3f081ea1-9634-4149-8914-968d9081a65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225012786 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3225012786
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2685608264
Short name T618
Test name
Test status
Simulation time 29274601 ps
CPU time 0.98 seconds
Started Jun 26 06:27:03 PM PDT 24
Finished Jun 26 06:27:05 PM PDT 24
Peak memory 207032 kb
Host smart-23b4be70-7ba6-496f-b7dc-2c6aacd8b65d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685608264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2685608264
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.6243744
Short name T42
Test name
Test status
Simulation time 40750013 ps
CPU time 0.92 seconds
Started Jun 26 06:27:03 PM PDT 24
Finished Jun 26 06:27:05 PM PDT 24
Peak memory 216640 kb
Host smart-cc3f8fdb-b424-4f72-af7a-101abb5fc8dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6243744 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.6243744
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.404270179
Short name T984
Test name
Test status
Simulation time 35369822 ps
CPU time 1.05 seconds
Started Jun 26 06:27:12 PM PDT 24
Finished Jun 26 06:27:15 PM PDT 24
Peak memory 218804 kb
Host smart-3404d15a-2e1e-4e82-93f8-7608d2f75074
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404270179 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.404270179
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1880095642
Short name T208
Test name
Test status
Simulation time 43361503 ps
CPU time 1.09 seconds
Started Jun 26 06:27:01 PM PDT 24
Finished Jun 26 06:27:03 PM PDT 24
Peak memory 220008 kb
Host smart-cddf0f3c-20b8-4af8-a640-baf99e8e8e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880095642 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1880095642
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.177986004
Short name T686
Test name
Test status
Simulation time 73203401 ps
CPU time 1.91 seconds
Started Jun 26 06:27:02 PM PDT 24
Finished Jun 26 06:27:05 PM PDT 24
Peak memory 220680 kb
Host smart-588e9fa8-54d7-4165-aa15-bf1c5bcf47b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177986004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.177986004
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3420100325
Short name T568
Test name
Test status
Simulation time 22340626 ps
CPU time 1.19 seconds
Started Jun 26 06:27:13 PM PDT 24
Finished Jun 26 06:27:16 PM PDT 24
Peak memory 224368 kb
Host smart-ac8d65be-52c1-4286-87de-d8d53457720c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420100325 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3420100325
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2683112376
Short name T26
Test name
Test status
Simulation time 16070095 ps
CPU time 0.99 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:27:18 PM PDT 24
Peak memory 207444 kb
Host smart-cfdeb1ac-6f5c-49c2-98be-678ae31d81dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683112376 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2683112376
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3242314147
Short name T62
Test name
Test status
Simulation time 346038256 ps
CPU time 4.57 seconds
Started Jun 26 06:27:13 PM PDT 24
Finished Jun 26 06:27:19 PM PDT 24
Peak memory 235672 kb
Host smart-544384e9-e3d0-4cc9-9266-010a479cf19e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242314147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3242314147
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.4130931972
Short name T434
Test name
Test status
Simulation time 46236756 ps
CPU time 0.91 seconds
Started Jun 26 06:27:04 PM PDT 24
Finished Jun 26 06:27:07 PM PDT 24
Peak memory 215668 kb
Host smart-83dfcfb4-5a5a-4a19-924f-6da96c6675f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130931972 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.4130931972
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.748243234
Short name T808
Test name
Test status
Simulation time 81507113 ps
CPU time 1.31 seconds
Started Jun 26 06:27:12 PM PDT 24
Finished Jun 26 06:27:14 PM PDT 24
Peak memory 215668 kb
Host smart-453ad1aa-7223-4d7e-a6a3-91c58d1f0f2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748243234 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.748243234
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.620142748
Short name T909
Test name
Test status
Simulation time 345393637249 ps
CPU time 2341.85 seconds
Started Jun 26 06:27:03 PM PDT 24
Finished Jun 26 07:06:06 PM PDT 24
Peak memory 231168 kb
Host smart-2d7ae703-21f8-4f50-a481-1190a2c93388
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620142748 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.620142748
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1288747308
Short name T324
Test name
Test status
Simulation time 87000677 ps
CPU time 1.17 seconds
Started Jun 26 06:27:58 PM PDT 24
Finished Jun 26 06:28:00 PM PDT 24
Peak memory 220760 kb
Host smart-6638b777-ad38-4803-83cd-2541d4cfd0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288747308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1288747308
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3343593544
Short name T819
Test name
Test status
Simulation time 69014002 ps
CPU time 0.92 seconds
Started Jun 26 06:28:09 PM PDT 24
Finished Jun 26 06:28:12 PM PDT 24
Peak memory 215272 kb
Host smart-d81e4c8b-4443-45c3-9403-40c0110b624b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343593544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3343593544
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2775841764
Short name T176
Test name
Test status
Simulation time 17287211 ps
CPU time 0.87 seconds
Started Jun 26 06:28:03 PM PDT 24
Finished Jun 26 06:28:04 PM PDT 24
Peak memory 216628 kb
Host smart-4163cfb4-6d1d-4a40-bda7-2de200cbc53c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775841764 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2775841764
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2348874023
Short name T85
Test name
Test status
Simulation time 55179210 ps
CPU time 1.19 seconds
Started Jun 26 06:28:12 PM PDT 24
Finished Jun 26 06:28:15 PM PDT 24
Peak memory 220056 kb
Host smart-e34c32e4-c898-4d9b-9279-762bd51c51b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348874023 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2348874023
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2732864458
Short name T677
Test name
Test status
Simulation time 29818597 ps
CPU time 0.91 seconds
Started Jun 26 06:28:04 PM PDT 24
Finished Jun 26 06:28:06 PM PDT 24
Peak memory 218908 kb
Host smart-cf109359-e2bf-4489-ab01-3ca9809470f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732864458 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2732864458
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.4273822667
Short name T326
Test name
Test status
Simulation time 63119813 ps
CPU time 1.15 seconds
Started Jun 26 06:28:09 PM PDT 24
Finished Jun 26 06:28:12 PM PDT 24
Peak memory 220248 kb
Host smart-0622d909-1116-4658-bc05-db6f5846244b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273822667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.4273822667
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1020311192
Short name T714
Test name
Test status
Simulation time 37202541 ps
CPU time 0.91 seconds
Started Jun 26 06:28:01 PM PDT 24
Finished Jun 26 06:28:02 PM PDT 24
Peak memory 215844 kb
Host smart-b57eb98d-12f7-4fd2-86df-64da50439ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020311192 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1020311192
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.601349804
Short name T660
Test name
Test status
Simulation time 97766421 ps
CPU time 0.94 seconds
Started Jun 26 06:28:08 PM PDT 24
Finished Jun 26 06:28:10 PM PDT 24
Peak memory 215596 kb
Host smart-ac941c12-5c46-4141-a313-ea773c0fc493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601349804 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.601349804
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3952763444
Short name T70
Test name
Test status
Simulation time 204254467 ps
CPU time 1.7 seconds
Started Jun 26 06:27:58 PM PDT 24
Finished Jun 26 06:28:00 PM PDT 24
Peak memory 215604 kb
Host smart-762341fb-a51b-45a2-901e-d0d31be99f8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952763444 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3952763444
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1327723611
Short name T69
Test name
Test status
Simulation time 73801496593 ps
CPU time 1773.22 seconds
Started Jun 26 06:28:05 PM PDT 24
Finished Jun 26 06:57:39 PM PDT 24
Peak memory 228276 kb
Host smart-e2ab2c7e-9203-424f-a0f8-b5a0c534e0a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327723611 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1327723611
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.662502055
Short name T465
Test name
Test status
Simulation time 41575471 ps
CPU time 1.15 seconds
Started Jun 26 06:28:04 PM PDT 24
Finished Jun 26 06:28:06 PM PDT 24
Peak memory 220120 kb
Host smart-330012aa-94f5-4e12-9cb4-10a5cca6ecb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662502055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.662502055
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.750833401
Short name T460
Test name
Test status
Simulation time 42864751 ps
CPU time 0.87 seconds
Started Jun 26 06:28:07 PM PDT 24
Finished Jun 26 06:28:10 PM PDT 24
Peak memory 206880 kb
Host smart-9fce24dc-8628-4e78-9e5b-1a0f48b24eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750833401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.750833401
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.314427940
Short name T428
Test name
Test status
Simulation time 12725328 ps
CPU time 0.91 seconds
Started Jun 26 06:28:00 PM PDT 24
Finished Jun 26 06:28:02 PM PDT 24
Peak memory 215884 kb
Host smart-c8e79e9e-dc35-4c96-acc8-87c718947122
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314427940 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.314427940
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1317983119
Short name T487
Test name
Test status
Simulation time 48159274 ps
CPU time 1.07 seconds
Started Jun 26 06:28:11 PM PDT 24
Finished Jun 26 06:28:14 PM PDT 24
Peak memory 218564 kb
Host smart-4b8aa1ff-b228-42ec-bdb7-65f6f274dd6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317983119 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1317983119
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3535441607
Short name T707
Test name
Test status
Simulation time 20366774 ps
CPU time 1.2 seconds
Started Jun 26 06:28:02 PM PDT 24
Finished Jun 26 06:28:04 PM PDT 24
Peak memory 220272 kb
Host smart-fa371390-0630-4965-bcd3-8b82f9d04406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535441607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3535441607
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2830544227
Short name T401
Test name
Test status
Simulation time 21931195 ps
CPU time 1.26 seconds
Started Jun 26 06:28:04 PM PDT 24
Finished Jun 26 06:28:06 PM PDT 24
Peak memory 217800 kb
Host smart-55e22b63-1d45-42ed-bb1c-9e013eabadd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830544227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2830544227
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1581296618
Short name T559
Test name
Test status
Simulation time 34904616 ps
CPU time 1.03 seconds
Started Jun 26 06:28:04 PM PDT 24
Finished Jun 26 06:28:06 PM PDT 24
Peak memory 224360 kb
Host smart-01d403ae-95da-40d1-9d41-ceca5c43b3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581296618 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1581296618
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2338396165
Short name T337
Test name
Test status
Simulation time 15635104 ps
CPU time 1.03 seconds
Started Jun 26 06:28:07 PM PDT 24
Finished Jun 26 06:28:09 PM PDT 24
Peak memory 215660 kb
Host smart-e26bf937-f297-4d09-a33d-260840c32616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338396165 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2338396165
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.876436374
Short name T836
Test name
Test status
Simulation time 317924125 ps
CPU time 2.16 seconds
Started Jun 26 06:28:05 PM PDT 24
Finished Jun 26 06:28:09 PM PDT 24
Peak memory 217800 kb
Host smart-f224015a-25d5-4e5f-978d-57290c724a41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876436374 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.876436374
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.62819087
Short name T227
Test name
Test status
Simulation time 25118006701 ps
CPU time 510.06 seconds
Started Jun 26 06:28:07 PM PDT 24
Finished Jun 26 06:36:38 PM PDT 24
Peak memory 224036 kb
Host smart-06f4002d-be4e-4243-a863-cb70f1f3359b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62819087 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.62819087
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2413937289
Short name T947
Test name
Test status
Simulation time 44109846 ps
CPU time 1.27 seconds
Started Jun 26 06:27:59 PM PDT 24
Finished Jun 26 06:28:01 PM PDT 24
Peak memory 220752 kb
Host smart-228f5e73-09b6-40cb-97ac-f332b0aaa61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413937289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2413937289
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3804020963
Short name T547
Test name
Test status
Simulation time 48964694 ps
CPU time 0.9 seconds
Started Jun 26 06:28:07 PM PDT 24
Finished Jun 26 06:28:09 PM PDT 24
Peak memory 215132 kb
Host smart-835afc8d-0f74-4ac1-bd04-29ee9f162596
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804020963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3804020963
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.556660887
Short name T187
Test name
Test status
Simulation time 55794607 ps
CPU time 0.89 seconds
Started Jun 26 06:28:04 PM PDT 24
Finished Jun 26 06:28:06 PM PDT 24
Peak memory 216536 kb
Host smart-2e294882-5538-43f0-9a7a-23d6c622eb0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556660887 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.556660887
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.435935018
Short name T145
Test name
Test status
Simulation time 93965154 ps
CPU time 1.09 seconds
Started Jun 26 06:28:12 PM PDT 24
Finished Jun 26 06:28:15 PM PDT 24
Peak memory 217240 kb
Host smart-aa92721c-b756-4c6c-8f1c-f6435a2f3c20
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435935018 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.435935018
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3605076722
Short name T143
Test name
Test status
Simulation time 23352720 ps
CPU time 1.28 seconds
Started Jun 26 06:28:03 PM PDT 24
Finished Jun 26 06:28:05 PM PDT 24
Peak memory 229884 kb
Host smart-7f2e4602-27f1-4ed0-ba0d-c0c5f5e9f969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605076722 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3605076722
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.650217408
Short name T448
Test name
Test status
Simulation time 25994637 ps
CPU time 1.24 seconds
Started Jun 26 06:28:03 PM PDT 24
Finished Jun 26 06:28:05 PM PDT 24
Peak memory 217704 kb
Host smart-7ce5ea8d-0454-4682-92c1-48e1e290fcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650217408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.650217408
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3227679297
Short name T732
Test name
Test status
Simulation time 23028827 ps
CPU time 1.25 seconds
Started Jun 26 06:28:17 PM PDT 24
Finished Jun 26 06:28:19 PM PDT 24
Peak memory 224320 kb
Host smart-1e2dd917-6544-49ed-970c-2015c0ca3ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227679297 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3227679297
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.616691562
Short name T349
Test name
Test status
Simulation time 17624070 ps
CPU time 1.07 seconds
Started Jun 26 06:28:04 PM PDT 24
Finished Jun 26 06:28:06 PM PDT 24
Peak memory 215648 kb
Host smart-ad8b14fd-c8bd-47e8-bc0d-90331f3055e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616691562 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.616691562
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1453588596
Short name T238
Test name
Test status
Simulation time 855637537 ps
CPU time 3.54 seconds
Started Jun 26 06:27:59 PM PDT 24
Finished Jun 26 06:28:03 PM PDT 24
Peak memory 217584 kb
Host smart-2c0bd5f6-5b4a-4fb6-b3e7-a6781d603706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453588596 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1453588596
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3698546756
Short name T233
Test name
Test status
Simulation time 98909159195 ps
CPU time 605.69 seconds
Started Jun 26 06:28:11 PM PDT 24
Finished Jun 26 06:38:18 PM PDT 24
Peak memory 224092 kb
Host smart-4c98d87d-4953-4b09-8dd8-414f1f69eaf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698546756 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3698546756
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.881219499
Short name T110
Test name
Test status
Simulation time 354640191 ps
CPU time 1.34 seconds
Started Jun 26 06:28:20 PM PDT 24
Finished Jun 26 06:28:23 PM PDT 24
Peak memory 220004 kb
Host smart-3896745f-5c2f-4fb4-a2f5-3806d29bd46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881219499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.881219499
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.4253957073
Short name T53
Test name
Test status
Simulation time 36871487 ps
CPU time 0.9 seconds
Started Jun 26 06:28:20 PM PDT 24
Finished Jun 26 06:28:23 PM PDT 24
Peak memory 207004 kb
Host smart-e95bfa91-1249-4eff-a05f-1361f6f048b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253957073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.4253957073
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3377997454
Short name T168
Test name
Test status
Simulation time 16169503 ps
CPU time 0.86 seconds
Started Jun 26 06:28:13 PM PDT 24
Finished Jun 26 06:28:15 PM PDT 24
Peak memory 216476 kb
Host smart-40273f3a-953d-487b-8932-d526c729480d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377997454 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3377997454
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2328094858
Short name T124
Test name
Test status
Simulation time 43387237 ps
CPU time 1.03 seconds
Started Jun 26 06:28:10 PM PDT 24
Finished Jun 26 06:28:12 PM PDT 24
Peak memory 217208 kb
Host smart-c36339fa-6675-44a5-b06b-70e83145a992
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328094858 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2328094858
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.455706057
Short name T914
Test name
Test status
Simulation time 34932418 ps
CPU time 1.54 seconds
Started Jun 26 06:28:15 PM PDT 24
Finished Jun 26 06:28:18 PM PDT 24
Peak memory 226024 kb
Host smart-68c29e23-bac8-4bd9-8498-9845c1c019db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455706057 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.455706057
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3765135506
Short name T529
Test name
Test status
Simulation time 85383454 ps
CPU time 1.14 seconds
Started Jun 26 06:28:11 PM PDT 24
Finished Jun 26 06:28:15 PM PDT 24
Peak memory 217720 kb
Host smart-f9609ac3-7f9d-4a80-ad87-bd13588cf5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765135506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3765135506
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.4129639098
Short name T31
Test name
Test status
Simulation time 45437080 ps
CPU time 0.83 seconds
Started Jun 26 06:28:11 PM PDT 24
Finished Jun 26 06:28:14 PM PDT 24
Peak memory 215800 kb
Host smart-3502e5c8-ab70-414e-b4f9-653c7a1923fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129639098 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.4129639098
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.4267299500
Short name T73
Test name
Test status
Simulation time 18418735 ps
CPU time 1.07 seconds
Started Jun 26 06:28:06 PM PDT 24
Finished Jun 26 06:28:09 PM PDT 24
Peak memory 215684 kb
Host smart-90641c35-6536-455f-9bd7-11050ab22726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267299500 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.4267299500
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1000488764
Short name T690
Test name
Test status
Simulation time 248944027 ps
CPU time 5.04 seconds
Started Jun 26 06:28:11 PM PDT 24
Finished Jun 26 06:28:17 PM PDT 24
Peak memory 217496 kb
Host smart-de7f6bf7-2505-4a8d-a769-e031e3f4a6fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000488764 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1000488764
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2447843669
Short name T810
Test name
Test status
Simulation time 70156738226 ps
CPU time 568.81 seconds
Started Jun 26 06:28:13 PM PDT 24
Finished Jun 26 06:37:44 PM PDT 24
Peak memory 218820 kb
Host smart-ab6acf8e-d781-4d3c-b1d5-e0cd8e0a25a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447843669 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2447843669
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.463154415
Short name T887
Test name
Test status
Simulation time 46770937 ps
CPU time 1.21 seconds
Started Jun 26 06:28:20 PM PDT 24
Finished Jun 26 06:28:23 PM PDT 24
Peak memory 220196 kb
Host smart-d8a5c205-65a4-4e93-9fd3-a00d1daee1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463154415 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.463154415
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.90016168
Short name T455
Test name
Test status
Simulation time 53998105 ps
CPU time 0.84 seconds
Started Jun 26 06:28:21 PM PDT 24
Finished Jun 26 06:28:24 PM PDT 24
Peak memory 214944 kb
Host smart-c20eb9e3-6303-4400-813e-20cb086df672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90016168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.90016168
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3700585652
Short name T87
Test name
Test status
Simulation time 13072945 ps
CPU time 0.97 seconds
Started Jun 26 06:28:10 PM PDT 24
Finished Jun 26 06:28:12 PM PDT 24
Peak memory 216496 kb
Host smart-75c61f79-af0b-4c9c-9e0e-656f59a078c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700585652 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3700585652
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3476384082
Short name T820
Test name
Test status
Simulation time 53546903 ps
CPU time 1.05 seconds
Started Jun 26 06:28:20 PM PDT 24
Finished Jun 26 06:28:23 PM PDT 24
Peak memory 220228 kb
Host smart-d435c90e-f8eb-4ea5-b4cc-e0c77a2dc279
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476384082 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3476384082
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2157933221
Short name T120
Test name
Test status
Simulation time 58142333 ps
CPU time 1.22 seconds
Started Jun 26 06:28:11 PM PDT 24
Finished Jun 26 06:28:14 PM PDT 24
Peak memory 229968 kb
Host smart-92398224-1d0f-4820-b548-6ca441efd891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157933221 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2157933221
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1180771643
Short name T531
Test name
Test status
Simulation time 63532986 ps
CPU time 1.21 seconds
Started Jun 26 06:28:13 PM PDT 24
Finished Jun 26 06:28:16 PM PDT 24
Peak memory 218788 kb
Host smart-0d1ac099-1e10-4a08-a14f-99a8cde08a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180771643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1180771643
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.4086471476
Short name T514
Test name
Test status
Simulation time 30314665 ps
CPU time 0.97 seconds
Started Jun 26 06:28:13 PM PDT 24
Finished Jun 26 06:28:16 PM PDT 24
Peak memory 215900 kb
Host smart-f48f1f72-a43d-4ecd-a451-89fdd036bc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086471476 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.4086471476
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1489704554
Short name T343
Test name
Test status
Simulation time 27409950 ps
CPU time 0.97 seconds
Started Jun 26 06:28:22 PM PDT 24
Finished Jun 26 06:28:25 PM PDT 24
Peak memory 215604 kb
Host smart-6e87c178-3a25-4e40-8266-90e98bfe6426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489704554 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1489704554
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2350743507
Short name T506
Test name
Test status
Simulation time 190293928 ps
CPU time 4.08 seconds
Started Jun 26 06:28:14 PM PDT 24
Finished Jun 26 06:28:25 PM PDT 24
Peak memory 215628 kb
Host smart-bd51e8dd-dbf9-44cb-bf60-20e089d31e80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350743507 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2350743507
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1875010008
Short name T391
Test name
Test status
Simulation time 186997321724 ps
CPU time 1256.5 seconds
Started Jun 26 06:28:26 PM PDT 24
Finished Jun 26 06:49:24 PM PDT 24
Peak memory 225568 kb
Host smart-67fa0dff-d12e-4d2a-80fc-ba22e2555f9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875010008 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1875010008
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.790723044
Short name T141
Test name
Test status
Simulation time 73672502 ps
CPU time 1.18 seconds
Started Jun 26 06:28:15 PM PDT 24
Finished Jun 26 06:28:17 PM PDT 24
Peak memory 219288 kb
Host smart-7b45b9d4-cb88-4bc2-a069-3b88c13648f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790723044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.790723044
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2775195878
Short name T718
Test name
Test status
Simulation time 22301412 ps
CPU time 1.03 seconds
Started Jun 26 06:28:13 PM PDT 24
Finished Jun 26 06:28:16 PM PDT 24
Peak memory 215604 kb
Host smart-a84fcf65-4dc5-48d3-88f2-ea2b426eebb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775195878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2775195878
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2379687269
Short name T835
Test name
Test status
Simulation time 12805767 ps
CPU time 0.9 seconds
Started Jun 26 06:28:19 PM PDT 24
Finished Jun 26 06:28:22 PM PDT 24
Peak memory 216884 kb
Host smart-1b5ab87c-ebfe-4e2a-8a3d-cc43e87dcc07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379687269 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2379687269
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1906836494
Short name T50
Test name
Test status
Simulation time 25835554 ps
CPU time 1.14 seconds
Started Jun 26 06:28:13 PM PDT 24
Finished Jun 26 06:28:16 PM PDT 24
Peak memory 217104 kb
Host smart-0523805e-b4fb-4d64-b87d-7faf2223eada
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906836494 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1906836494
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.111199605
Short name T56
Test name
Test status
Simulation time 60493053 ps
CPU time 0.99 seconds
Started Jun 26 06:28:08 PM PDT 24
Finished Jun 26 06:28:11 PM PDT 24
Peak memory 224144 kb
Host smart-f9e5518f-09e8-4727-b946-1470c73ed465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111199605 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.111199605
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1542533176
Short name T613
Test name
Test status
Simulation time 78642738 ps
CPU time 2.89 seconds
Started Jun 26 06:28:16 PM PDT 24
Finished Jun 26 06:28:20 PM PDT 24
Peak memory 219216 kb
Host smart-16b26183-1364-4b6b-baba-a03e04c80426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542533176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1542533176
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1950331479
Short name T904
Test name
Test status
Simulation time 38508304 ps
CPU time 0.93 seconds
Started Jun 26 06:28:08 PM PDT 24
Finished Jun 26 06:28:10 PM PDT 24
Peak memory 215768 kb
Host smart-67a7ec85-8089-4071-9eff-3544bfeb73f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950331479 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1950331479
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3889412656
Short name T689
Test name
Test status
Simulation time 15766732 ps
CPU time 1.01 seconds
Started Jun 26 06:28:09 PM PDT 24
Finished Jun 26 06:28:11 PM PDT 24
Peak memory 215632 kb
Host smart-0bf97cc8-91a2-45e1-97e7-02dbf6a77e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889412656 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3889412656
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2592938093
Short name T845
Test name
Test status
Simulation time 101280946 ps
CPU time 2.67 seconds
Started Jun 26 06:28:08 PM PDT 24
Finished Jun 26 06:28:12 PM PDT 24
Peak memory 215596 kb
Host smart-6dc53872-12a6-440e-bc23-f3fffc0ddcb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592938093 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2592938093
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2342007094
Short name T651
Test name
Test status
Simulation time 25680652455 ps
CPU time 336.06 seconds
Started Jun 26 06:28:23 PM PDT 24
Finished Jun 26 06:34:01 PM PDT 24
Peak memory 223916 kb
Host smart-7c265dae-1476-4bf6-9748-3ca04bcba215
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342007094 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2342007094
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2286494733
Short name T954
Test name
Test status
Simulation time 90635394 ps
CPU time 1.22 seconds
Started Jun 26 06:28:11 PM PDT 24
Finished Jun 26 06:28:14 PM PDT 24
Peak memory 220236 kb
Host smart-970b6e9c-d6e5-4a3f-beb2-f2a0d52660e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286494733 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2286494733
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.743306710
Short name T790
Test name
Test status
Simulation time 23550878 ps
CPU time 0.92 seconds
Started Jun 26 06:28:07 PM PDT 24
Finished Jun 26 06:28:10 PM PDT 24
Peak memory 207048 kb
Host smart-f5116687-6c62-4da2-b800-5681e6e2c8ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743306710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.743306710
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.147726839
Short name T781
Test name
Test status
Simulation time 21973115 ps
CPU time 0.88 seconds
Started Jun 26 06:28:28 PM PDT 24
Finished Jun 26 06:28:30 PM PDT 24
Peak memory 216552 kb
Host smart-73002f86-201b-492a-9939-81742affef3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147726839 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.147726839
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.4105162517
Short name T207
Test name
Test status
Simulation time 115501814 ps
CPU time 1.26 seconds
Started Jun 26 06:28:12 PM PDT 24
Finished Jun 26 06:28:15 PM PDT 24
Peak memory 217144 kb
Host smart-44e27109-5484-4009-ac84-231eec0cc0b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105162517 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.4105162517
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.100978701
Short name T6
Test name
Test status
Simulation time 31024778 ps
CPU time 1.14 seconds
Started Jun 26 06:28:08 PM PDT 24
Finished Jun 26 06:28:10 PM PDT 24
Peak memory 220788 kb
Host smart-7791ce71-4e23-49b9-8723-d34cd75a324c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100978701 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.100978701
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1711125752
Short name T663
Test name
Test status
Simulation time 122367038 ps
CPU time 0.99 seconds
Started Jun 26 06:28:20 PM PDT 24
Finished Jun 26 06:28:22 PM PDT 24
Peak memory 217696 kb
Host smart-37c02d53-beaa-43c4-8a9b-fc9ae8bd0e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711125752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1711125752
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.578721687
Short name T977
Test name
Test status
Simulation time 28592298 ps
CPU time 1.06 seconds
Started Jun 26 06:28:20 PM PDT 24
Finished Jun 26 06:28:23 PM PDT 24
Peak memory 224320 kb
Host smart-aff032fd-0b70-435c-a415-6fe649ab10f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578721687 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.578721687
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2673300054
Short name T479
Test name
Test status
Simulation time 16091370 ps
CPU time 0.97 seconds
Started Jun 26 06:28:21 PM PDT 24
Finished Jun 26 06:28:24 PM PDT 24
Peak memory 215592 kb
Host smart-41d33147-9b5c-4f1a-86ec-deb4f5513fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673300054 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2673300054
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.572309059
Short name T858
Test name
Test status
Simulation time 86012796 ps
CPU time 2.39 seconds
Started Jun 26 06:28:06 PM PDT 24
Finished Jun 26 06:28:10 PM PDT 24
Peak memory 215644 kb
Host smart-f8abeab5-5441-4da0-acb9-3ce0827b9cab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572309059 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.572309059
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.516634263
Short name T234
Test name
Test status
Simulation time 94072179392 ps
CPU time 2101.37 seconds
Started Jun 26 06:28:08 PM PDT 24
Finished Jun 26 07:03:11 PM PDT 24
Peak memory 227148 kb
Host smart-4dc4c153-9f1f-4e7e-8246-36f555771506
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516634263 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.516634263
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.27778939
Short name T190
Test name
Test status
Simulation time 44455358 ps
CPU time 1.19 seconds
Started Jun 26 06:28:13 PM PDT 24
Finished Jun 26 06:28:16 PM PDT 24
Peak memory 220012 kb
Host smart-76c4beb3-3385-43fa-a33b-857cc36115c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27778939 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.27778939
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1252817313
Short name T535
Test name
Test status
Simulation time 24510169 ps
CPU time 0.92 seconds
Started Jun 26 06:28:13 PM PDT 24
Finished Jun 26 06:28:15 PM PDT 24
Peak memory 215420 kb
Host smart-6c5758b9-746c-4008-9457-42e9fc60a193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252817313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1252817313
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1398894532
Short name T170
Test name
Test status
Simulation time 25589638 ps
CPU time 0.86 seconds
Started Jun 26 06:28:18 PM PDT 24
Finished Jun 26 06:28:19 PM PDT 24
Peak memory 216684 kb
Host smart-92101995-b2a1-4e7b-9cfd-f6f7e400d6ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398894532 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1398894532
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.904040475
Short name T870
Test name
Test status
Simulation time 21811041 ps
CPU time 1.04 seconds
Started Jun 26 06:28:25 PM PDT 24
Finished Jun 26 06:28:28 PM PDT 24
Peak memory 217312 kb
Host smart-83f3ebc2-fddf-4f73-8710-32e672abcbeb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904040475 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.904040475
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3168984193
Short name T203
Test name
Test status
Simulation time 110501560 ps
CPU time 0.99 seconds
Started Jun 26 06:28:19 PM PDT 24
Finished Jun 26 06:28:22 PM PDT 24
Peak memory 220212 kb
Host smart-3120474b-59b1-4e36-aefc-ec7dd321e70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168984193 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3168984193
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.890913843
Short name T612
Test name
Test status
Simulation time 29252880 ps
CPU time 1.18 seconds
Started Jun 26 06:28:21 PM PDT 24
Finished Jun 26 06:28:24 PM PDT 24
Peak memory 218908 kb
Host smart-1617df0f-5ce8-474f-9fc2-8b4ccd49ce91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890913843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.890913843
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2853180473
Short name T823
Test name
Test status
Simulation time 36923557 ps
CPU time 1.08 seconds
Started Jun 26 06:28:10 PM PDT 24
Finished Jun 26 06:28:12 PM PDT 24
Peak memory 224176 kb
Host smart-cc44c8a0-b841-4c31-9299-0288f8bfa089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853180473 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2853180473
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2409942491
Short name T435
Test name
Test status
Simulation time 73308155 ps
CPU time 0.93 seconds
Started Jun 26 06:28:13 PM PDT 24
Finished Jun 26 06:28:16 PM PDT 24
Peak memory 215664 kb
Host smart-38bc20d0-3d8e-4938-a01f-144ed3874019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409942491 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2409942491
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2021803049
Short name T562
Test name
Test status
Simulation time 35190198 ps
CPU time 1.02 seconds
Started Jun 26 06:28:10 PM PDT 24
Finished Jun 26 06:28:13 PM PDT 24
Peak memory 206888 kb
Host smart-afc4461c-6ed7-47e1-985f-0a0da425e3db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021803049 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2021803049
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2087660574
Short name T902
Test name
Test status
Simulation time 26412655908 ps
CPU time 269.33 seconds
Started Jun 26 06:28:22 PM PDT 24
Finished Jun 26 06:32:53 PM PDT 24
Peak memory 218720 kb
Host smart-8d9f64f6-858c-4e15-86e5-3e2a70a49a79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087660574 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2087660574
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.597886843
Short name T563
Test name
Test status
Simulation time 86720933 ps
CPU time 1.25 seconds
Started Jun 26 06:28:24 PM PDT 24
Finished Jun 26 06:28:26 PM PDT 24
Peak memory 220088 kb
Host smart-93601a4d-a3ae-4bec-b132-340c412e7a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597886843 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.597886843
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1615637829
Short name T752
Test name
Test status
Simulation time 15090997 ps
CPU time 0.92 seconds
Started Jun 26 06:28:21 PM PDT 24
Finished Jun 26 06:28:24 PM PDT 24
Peak memory 206948 kb
Host smart-7ff1b55d-1dd1-4630-9906-681d500604b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615637829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1615637829
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.253702839
Short name T734
Test name
Test status
Simulation time 11498099 ps
CPU time 0.87 seconds
Started Jun 26 06:28:11 PM PDT 24
Finished Jun 26 06:28:13 PM PDT 24
Peak memory 216744 kb
Host smart-1f195f27-20ef-48bc-bb67-9fdd43c93cf7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253702839 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.253702839
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.862426433
Short name T13
Test name
Test status
Simulation time 38814889 ps
CPU time 1.09 seconds
Started Jun 26 06:28:11 PM PDT 24
Finished Jun 26 06:28:14 PM PDT 24
Peak memory 218956 kb
Host smart-6ea925c1-460f-4fd9-84da-3449d4f30118
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862426433 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.862426433
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.47310999
Short name T853
Test name
Test status
Simulation time 63841337 ps
CPU time 1.23 seconds
Started Jun 26 06:28:20 PM PDT 24
Finished Jun 26 06:28:23 PM PDT 24
Peak memory 226144 kb
Host smart-238ef43f-b246-4ab5-863e-179de401751f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47310999 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.47310999
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.4165198616
Short name T693
Test name
Test status
Simulation time 50706772 ps
CPU time 1.54 seconds
Started Jun 26 06:28:11 PM PDT 24
Finished Jun 26 06:28:15 PM PDT 24
Peak memory 218828 kb
Host smart-f18647e3-1024-4275-be79-05e95c39473c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165198616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.4165198616
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_smoke.2563605800
Short name T855
Test name
Test status
Simulation time 19681743 ps
CPU time 1.03 seconds
Started Jun 26 06:28:13 PM PDT 24
Finished Jun 26 06:28:16 PM PDT 24
Peak memory 215656 kb
Host smart-8b77a78e-50f1-496d-98e5-473f119b164b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563605800 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2563605800
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3251082242
Short name T859
Test name
Test status
Simulation time 490452318 ps
CPU time 4.6 seconds
Started Jun 26 06:28:16 PM PDT 24
Finished Jun 26 06:28:22 PM PDT 24
Peak memory 217688 kb
Host smart-90ef47dd-d652-412e-89d3-2455be26b734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251082242 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3251082242
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3556728005
Short name T762
Test name
Test status
Simulation time 116955671729 ps
CPU time 752.66 seconds
Started Jun 26 06:28:11 PM PDT 24
Finished Jun 26 06:40:45 PM PDT 24
Peak memory 221984 kb
Host smart-2e92df2a-dbed-4597-abbe-931ad43d2c32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556728005 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3556728005
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.3946777224
Short name T501
Test name
Test status
Simulation time 105089229 ps
CPU time 1.12 seconds
Started Jun 26 06:28:29 PM PDT 24
Finished Jun 26 06:28:33 PM PDT 24
Peak memory 220092 kb
Host smart-1bd8727e-f277-47ff-a25c-9ac8114f5e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946777224 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3946777224
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3615679872
Short name T409
Test name
Test status
Simulation time 36121510 ps
CPU time 0.88 seconds
Started Jun 26 06:28:27 PM PDT 24
Finished Jun 26 06:28:30 PM PDT 24
Peak memory 207120 kb
Host smart-ebcc019f-216b-4f29-bf5d-ff6019c2c776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615679872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3615679872
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3194344516
Short name T206
Test name
Test status
Simulation time 14716717 ps
CPU time 0.91 seconds
Started Jun 26 06:29:15 PM PDT 24
Finished Jun 26 06:29:21 PM PDT 24
Peak memory 216708 kb
Host smart-8ee1b3ef-73cc-43bf-8771-d7139b8b1e4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194344516 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3194344516
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.66402398
Short name T603
Test name
Test status
Simulation time 29145036 ps
CPU time 1.12 seconds
Started Jun 26 06:28:18 PM PDT 24
Finished Jun 26 06:28:20 PM PDT 24
Peak memory 217136 kb
Host smart-34d21a48-8aa8-4b7b-8e48-129ef33c196e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66402398 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_dis
able_auto_req_mode.66402398
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.395448332
Short name T210
Test name
Test status
Simulation time 20543310 ps
CPU time 1.22 seconds
Started Jun 26 06:28:29 PM PDT 24
Finished Jun 26 06:28:33 PM PDT 24
Peak memory 224296 kb
Host smart-b43285c9-60a6-44c7-a5c4-87202ca6fae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395448332 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.395448332
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2089394030
Short name T631
Test name
Test status
Simulation time 302759886 ps
CPU time 3.31 seconds
Started Jun 26 06:28:11 PM PDT 24
Finished Jun 26 06:28:16 PM PDT 24
Peak memory 219968 kb
Host smart-955ea6c2-894f-4589-af6b-44013a3247e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089394030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2089394030
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2387524403
Short name T15
Test name
Test status
Simulation time 21397793 ps
CPU time 1.22 seconds
Started Jun 26 06:28:16 PM PDT 24
Finished Jun 26 06:28:18 PM PDT 24
Peak memory 224304 kb
Host smart-c89b5dbb-97de-4ccc-82e1-196fbb5df996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387524403 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2387524403
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1295905640
Short name T804
Test name
Test status
Simulation time 28207262 ps
CPU time 1.03 seconds
Started Jun 26 06:28:11 PM PDT 24
Finished Jun 26 06:28:13 PM PDT 24
Peak memory 215592 kb
Host smart-b923d069-5dea-4be2-9d60-39056f90c3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295905640 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1295905640
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.546849762
Short name T602
Test name
Test status
Simulation time 416760302 ps
CPU time 4.78 seconds
Started Jun 26 06:28:19 PM PDT 24
Finished Jun 26 06:28:26 PM PDT 24
Peak memory 217596 kb
Host smart-eda484b1-f249-4b23-a6e9-1d0e51ad3c01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546849762 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.546849762
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1754574786
Short name T454
Test name
Test status
Simulation time 18041113902 ps
CPU time 403.54 seconds
Started Jun 26 06:28:10 PM PDT 24
Finished Jun 26 06:34:55 PM PDT 24
Peak memory 218124 kb
Host smart-121f4843-eefb-49b2-b270-ace436b926db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754574786 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1754574786
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.2103234137
Short name T278
Test name
Test status
Simulation time 24748271 ps
CPU time 1.23 seconds
Started Jun 26 06:27:02 PM PDT 24
Finished Jun 26 06:27:04 PM PDT 24
Peak memory 219080 kb
Host smart-989b9c8a-8a47-4869-965d-3dd8271461b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103234137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2103234137
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2159498525
Short name T755
Test name
Test status
Simulation time 29632865 ps
CPU time 1.01 seconds
Started Jun 26 06:27:15 PM PDT 24
Finished Jun 26 06:27:20 PM PDT 24
Peak memory 207104 kb
Host smart-76312ede-b83a-4110-9cfe-d4be9daf08e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159498525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2159498525
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_err.1187574194
Short name T211
Test name
Test status
Simulation time 38294950 ps
CPU time 1.1 seconds
Started Jun 26 06:27:04 PM PDT 24
Finished Jun 26 06:27:06 PM PDT 24
Peak memory 219936 kb
Host smart-17914644-4eff-4cfb-8095-f96ec2a7e46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187574194 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1187574194
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1563395585
Short name T721
Test name
Test status
Simulation time 131115171 ps
CPU time 1.82 seconds
Started Jun 26 06:27:03 PM PDT 24
Finished Jun 26 06:27:06 PM PDT 24
Peak memory 219672 kb
Host smart-28619741-2b86-4a86-b2c9-e7e9e80c878d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563395585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1563395585
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1923588410
Short name T99
Test name
Test status
Simulation time 24236578 ps
CPU time 0.96 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:27:18 PM PDT 24
Peak memory 216144 kb
Host smart-2dd55d7a-229f-46e8-a7b3-429b02ad81ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923588410 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1923588410
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3775137938
Short name T316
Test name
Test status
Simulation time 14173223 ps
CPU time 0.93 seconds
Started Jun 26 06:27:12 PM PDT 24
Finished Jun 26 06:27:14 PM PDT 24
Peak memory 207640 kb
Host smart-b4b85b75-50e5-4087-9b84-7f848c20574c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775137938 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3775137938
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2027789862
Short name T864
Test name
Test status
Simulation time 58007673 ps
CPU time 0.9 seconds
Started Jun 26 06:27:11 PM PDT 24
Finished Jun 26 06:27:13 PM PDT 24
Peak memory 215668 kb
Host smart-98ff38e9-1308-4627-95d8-47decf73892e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027789862 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2027789862
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1043069004
Short name T539
Test name
Test status
Simulation time 329048377 ps
CPU time 4.01 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:27:21 PM PDT 24
Peak memory 217844 kb
Host smart-962a8e40-d532-4ed6-8220-2b325035520e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043069004 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1043069004
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1752903809
Short name T235
Test name
Test status
Simulation time 127315754453 ps
CPU time 1422.76 seconds
Started Jun 26 06:27:00 PM PDT 24
Finished Jun 26 06:50:44 PM PDT 24
Peak memory 224196 kb
Host smart-792ca59c-3e39-45ed-ae34-a5588b386708
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752903809 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1752903809
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.790045526
Short name T127
Test name
Test status
Simulation time 101626776 ps
CPU time 1.31 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:39 PM PDT 24
Peak memory 219984 kb
Host smart-506f9ea7-cafd-403c-beb3-08dda34810e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790045526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.790045526
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.1280837971
Short name T932
Test name
Test status
Simulation time 24772382 ps
CPU time 0.99 seconds
Started Jun 26 06:28:28 PM PDT 24
Finished Jun 26 06:28:30 PM PDT 24
Peak memory 219960 kb
Host smart-d2c1a5db-9435-439a-9838-a6c81fe7fb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280837971 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1280837971
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3454410493
Short name T399
Test name
Test status
Simulation time 74075398 ps
CPU time 1.32 seconds
Started Jun 26 06:28:27 PM PDT 24
Finished Jun 26 06:28:30 PM PDT 24
Peak memory 219212 kb
Host smart-170d6530-f81d-4db9-851e-459f4e099574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454410493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3454410493
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.892233379
Short name T246
Test name
Test status
Simulation time 115723779 ps
CPU time 1.24 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:38 PM PDT 24
Peak memory 219932 kb
Host smart-6ab38b12-51eb-4db3-900f-d1c77f88b8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892233379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.892233379
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.267331260
Short name T504
Test name
Test status
Simulation time 28447238 ps
CPU time 1.2 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:38 PM PDT 24
Peak memory 220036 kb
Host smart-5a9ef242-36df-47bd-9a09-6d3b977d92d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267331260 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.267331260
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2572500437
Short name T534
Test name
Test status
Simulation time 83272529 ps
CPU time 1.29 seconds
Started Jun 26 06:28:19 PM PDT 24
Finished Jun 26 06:28:22 PM PDT 24
Peak memory 217872 kb
Host smart-0fd47de7-1cad-4a09-bc80-932bf1c3d7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572500437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2572500437
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.3301604360
Short name T972
Test name
Test status
Simulation time 48343968 ps
CPU time 1.19 seconds
Started Jun 26 06:28:23 PM PDT 24
Finished Jun 26 06:28:26 PM PDT 24
Peak memory 220064 kb
Host smart-36f7439b-10be-4446-912c-5ae94273264f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301604360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.3301604360
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.3295590224
Short name T416
Test name
Test status
Simulation time 21496516 ps
CPU time 0.98 seconds
Started Jun 26 06:28:22 PM PDT 24
Finished Jun 26 06:28:25 PM PDT 24
Peak memory 218816 kb
Host smart-2c7738f7-bcd5-4acf-aa11-af9dbe86b3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295590224 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3295590224
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2114144831
Short name T344
Test name
Test status
Simulation time 56404485 ps
CPU time 1.49 seconds
Started Jun 26 06:28:20 PM PDT 24
Finished Jun 26 06:28:23 PM PDT 24
Peak memory 219028 kb
Host smart-36827ef9-f368-4859-9f9c-af61b0da15d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114144831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2114144831
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.3838671457
Short name T626
Test name
Test status
Simulation time 81254806 ps
CPU time 1.1 seconds
Started Jun 26 06:28:30 PM PDT 24
Finished Jun 26 06:28:34 PM PDT 24
Peak memory 220200 kb
Host smart-90ec35fb-3d68-4f32-b104-a623c886e6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838671457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.3838671457
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.3431551639
Short name T185
Test name
Test status
Simulation time 31106677 ps
CPU time 0.88 seconds
Started Jun 26 06:28:32 PM PDT 24
Finished Jun 26 06:28:37 PM PDT 24
Peak memory 218700 kb
Host smart-0652b4d3-4a53-4c8f-a525-05307e92badf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431551639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3431551639
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2374472494
Short name T615
Test name
Test status
Simulation time 48475833 ps
CPU time 1.6 seconds
Started Jun 26 06:28:27 PM PDT 24
Finished Jun 26 06:28:30 PM PDT 24
Peak memory 220524 kb
Host smart-89871fc8-a1c7-4247-b809-de98409fd5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374472494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2374472494
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.1641869503
Short name T135
Test name
Test status
Simulation time 86133215 ps
CPU time 1.21 seconds
Started Jun 26 06:28:31 PM PDT 24
Finished Jun 26 06:28:34 PM PDT 24
Peak memory 220052 kb
Host smart-86c4f4d5-b0d8-403b-a0b4-eb38b3718300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641869503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.1641869503
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.3942640744
Short name T842
Test name
Test status
Simulation time 45269316 ps
CPU time 0.91 seconds
Started Jun 26 06:28:17 PM PDT 24
Finished Jun 26 06:28:19 PM PDT 24
Peak memory 219988 kb
Host smart-8f215841-3caa-4fe1-82ce-cf8b82753945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942640744 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3942640744
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1210162958
Short name T801
Test name
Test status
Simulation time 43016794 ps
CPU time 1.17 seconds
Started Jun 26 06:28:19 PM PDT 24
Finished Jun 26 06:28:22 PM PDT 24
Peak memory 217588 kb
Host smart-872962f7-5a74-45b3-b589-e42fd51dc163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210162958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1210162958
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.542623385
Short name T102
Test name
Test status
Simulation time 43683543 ps
CPU time 1.19 seconds
Started Jun 26 06:28:16 PM PDT 24
Finished Jun 26 06:28:18 PM PDT 24
Peak memory 220008 kb
Host smart-b198f816-b415-484a-9772-7e8efbcb6d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542623385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.542623385
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.3638336749
Short name T642
Test name
Test status
Simulation time 21398992 ps
CPU time 0.99 seconds
Started Jun 26 06:28:20 PM PDT 24
Finished Jun 26 06:28:23 PM PDT 24
Peak memory 219972 kb
Host smart-8261f17b-54b3-40a5-b23d-5a3572a360a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638336749 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3638336749
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/56.edn_alert.1733149903
Short name T270
Test name
Test status
Simulation time 28942574 ps
CPU time 1.29 seconds
Started Jun 26 06:28:31 PM PDT 24
Finished Jun 26 06:28:35 PM PDT 24
Peak memory 218840 kb
Host smart-0cb11ab5-ec8a-4a90-9cd5-99931d986df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733149903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.1733149903
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.29000386
Short name T826
Test name
Test status
Simulation time 58897131 ps
CPU time 0.8 seconds
Started Jun 26 06:28:32 PM PDT 24
Finished Jun 26 06:28:35 PM PDT 24
Peak memory 219640 kb
Host smart-fa823791-19a0-4b16-9219-92529f9791c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29000386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.29000386
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1898012956
Short name T705
Test name
Test status
Simulation time 119148584 ps
CPU time 1.39 seconds
Started Jun 26 06:28:30 PM PDT 24
Finished Jun 26 06:28:34 PM PDT 24
Peak memory 217568 kb
Host smart-f98984d9-5f4b-4739-a7f0-815febf45529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898012956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1898012956
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.3969751673
Short name T814
Test name
Test status
Simulation time 28473799 ps
CPU time 1.22 seconds
Started Jun 26 06:28:29 PM PDT 24
Finished Jun 26 06:28:32 PM PDT 24
Peak memory 219112 kb
Host smart-f7cf7100-2e3c-471d-800d-2f36d57b9bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969751673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.3969751673
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.3064559916
Short name T606
Test name
Test status
Simulation time 29134561 ps
CPU time 0.91 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:37 PM PDT 24
Peak memory 218380 kb
Host smart-38374108-38bf-4227-acd9-ff4a2fc1efc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064559916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3064559916
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3736532981
Short name T411
Test name
Test status
Simulation time 73551046 ps
CPU time 1.26 seconds
Started Jun 26 06:28:20 PM PDT 24
Finished Jun 26 06:28:23 PM PDT 24
Peak memory 218960 kb
Host smart-11606ba5-d9c4-473e-9486-fcc723bc3cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736532981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3736532981
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.3298896839
Short name T936
Test name
Test status
Simulation time 23816289 ps
CPU time 1.27 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:38 PM PDT 24
Peak memory 221548 kb
Host smart-087af1be-ac8a-4cb2-bec2-0875dd9b27bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298896839 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.3298896839
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.2788112006
Short name T926
Test name
Test status
Simulation time 28405006 ps
CPU time 0.89 seconds
Started Jun 26 06:28:21 PM PDT 24
Finished Jun 26 06:28:23 PM PDT 24
Peak memory 218564 kb
Host smart-c264b922-7371-44ca-b41c-9cb4a65b94f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788112006 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2788112006
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.773398817
Short name T422
Test name
Test status
Simulation time 55725267 ps
CPU time 1.34 seconds
Started Jun 26 06:28:20 PM PDT 24
Finished Jun 26 06:28:23 PM PDT 24
Peak memory 219312 kb
Host smart-2c953284-5ba9-4a92-b53a-505175b0b4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773398817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.773398817
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.4206917389
Short name T118
Test name
Test status
Simulation time 64677128 ps
CPU time 1.19 seconds
Started Jun 26 06:28:30 PM PDT 24
Finished Jun 26 06:28:34 PM PDT 24
Peak memory 219056 kb
Host smart-2b086f1c-5fab-4c95-8fb6-e6b370fc33b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206917389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.4206917389
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.985997433
Short name T150
Test name
Test status
Simulation time 80386217 ps
CPU time 0.85 seconds
Started Jun 26 06:28:28 PM PDT 24
Finished Jun 26 06:28:31 PM PDT 24
Peak memory 215540 kb
Host smart-8116a1e2-b72c-4bdb-93dd-bd444edd0fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985997433 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.985997433
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.254367799
Short name T328
Test name
Test status
Simulation time 39404234 ps
CPU time 1.41 seconds
Started Jun 26 06:28:28 PM PDT 24
Finished Jun 26 06:28:31 PM PDT 24
Peak memory 220272 kb
Host smart-3fe8e776-1bf0-4ea9-95df-ee7e6294cbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254367799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.254367799
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.1964880713
Short name T617
Test name
Test status
Simulation time 48275808 ps
CPU time 1.32 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:27:17 PM PDT 24
Peak memory 215984 kb
Host smart-c9beded5-c7e6-4fb8-a049-c2e0100dc952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964880713 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1964880713
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3405699813
Short name T738
Test name
Test status
Simulation time 147676993 ps
CPU time 0.92 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:27:18 PM PDT 24
Peak memory 207020 kb
Host smart-456fdf15-ec30-4612-a20e-c38b4800dc42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405699813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3405699813
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.4133319285
Short name T22
Test name
Test status
Simulation time 16301182 ps
CPU time 0.91 seconds
Started Jun 26 06:27:03 PM PDT 24
Finished Jun 26 06:27:05 PM PDT 24
Peak memory 216584 kb
Host smart-680ddee8-96ea-4142-97b5-2d10a116adbb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133319285 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.4133319285
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1233159154
Short name T773
Test name
Test status
Simulation time 95843503 ps
CPU time 1.13 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:27:19 PM PDT 24
Peak memory 217292 kb
Host smart-215c5f78-2e47-4603-b89f-9b96d57c76bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233159154 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1233159154
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2742441090
Short name T204
Test name
Test status
Simulation time 68368592 ps
CPU time 1.22 seconds
Started Jun 26 06:27:02 PM PDT 24
Finished Jun 26 06:27:04 PM PDT 24
Peak memory 226072 kb
Host smart-707ca6f7-53f7-42c3-866c-8c537543cb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742441090 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2742441090
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2807558588
Short name T789
Test name
Test status
Simulation time 121640753 ps
CPU time 1.21 seconds
Started Jun 26 06:27:01 PM PDT 24
Finished Jun 26 06:27:03 PM PDT 24
Peak memory 219036 kb
Host smart-f12f5281-8e44-46b2-9f7d-5a3def43a891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807558588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2807558588
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1915877469
Short name T96
Test name
Test status
Simulation time 25833281 ps
CPU time 0.97 seconds
Started Jun 26 06:27:04 PM PDT 24
Finished Jun 26 06:27:06 PM PDT 24
Peak memory 216288 kb
Host smart-6f4ab774-0702-4cd3-b3d7-7c6faf9672e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915877469 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1915877469
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1869728849
Short name T796
Test name
Test status
Simulation time 69777411 ps
CPU time 0.87 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:27:17 PM PDT 24
Peak memory 207480 kb
Host smart-277a953f-e41b-4934-a3dd-63a58282bf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869728849 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1869728849
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1855668424
Short name T387
Test name
Test status
Simulation time 21138164 ps
CPU time 0.93 seconds
Started Jun 26 06:27:02 PM PDT 24
Finished Jun 26 06:27:04 PM PDT 24
Peak memory 215644 kb
Host smart-ccfde440-1f9c-4205-bdb2-c0d7ad304cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855668424 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1855668424
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.4237948406
Short name T735
Test name
Test status
Simulation time 627298102 ps
CPU time 5.33 seconds
Started Jun 26 06:27:12 PM PDT 24
Finished Jun 26 06:27:19 PM PDT 24
Peak memory 217560 kb
Host smart-20c900d0-cc58-465e-9bae-7d48e398cf24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237948406 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.4237948406
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/60.edn_alert.724820134
Short name T247
Test name
Test status
Simulation time 182079847 ps
CPU time 1.25 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:38 PM PDT 24
Peak memory 220212 kb
Host smart-d0e9a8fe-cc41-453e-bcdf-177a74525066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724820134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.724820134
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1451766961
Short name T59
Test name
Test status
Simulation time 70999137 ps
CPU time 1.05 seconds
Started Jun 26 06:28:23 PM PDT 24
Finished Jun 26 06:28:25 PM PDT 24
Peak memory 224252 kb
Host smart-57c9de69-e80c-472b-a946-34e25de7e0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451766961 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1451766961
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.668013184
Short name T304
Test name
Test status
Simulation time 375718237 ps
CPU time 4.73 seconds
Started Jun 26 06:28:17 PM PDT 24
Finished Jun 26 06:28:23 PM PDT 24
Peak memory 219508 kb
Host smart-39631fdc-e881-4aaa-b53f-e41b90e500ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668013184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.668013184
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1378363824
Short name T131
Test name
Test status
Simulation time 197285766 ps
CPU time 1.26 seconds
Started Jun 26 06:28:20 PM PDT 24
Finished Jun 26 06:28:23 PM PDT 24
Peak memory 218884 kb
Host smart-099bfa0b-7a0b-4e2c-abdf-5d25cbd75a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378363824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1378363824
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.3358446920
Short name T837
Test name
Test status
Simulation time 23493806 ps
CPU time 0.93 seconds
Started Jun 26 06:28:23 PM PDT 24
Finished Jun 26 06:28:25 PM PDT 24
Peak memory 218688 kb
Host smart-8f6b1346-40a1-4e18-b73b-fc6f2edf11fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358446920 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3358446920
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.4012154304
Short name T751
Test name
Test status
Simulation time 49944840 ps
CPU time 1.48 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:38 PM PDT 24
Peak memory 218960 kb
Host smart-803fd872-41b6-405b-ba9f-784dbe333fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012154304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.4012154304
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.1504750746
Short name T443
Test name
Test status
Simulation time 24059029 ps
CPU time 1.24 seconds
Started Jun 26 06:28:28 PM PDT 24
Finished Jun 26 06:28:31 PM PDT 24
Peak memory 218948 kb
Host smart-14ca15e1-1bdc-45d1-b58a-bb73232355f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504750746 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.1504750746
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.3875777664
Short name T891
Test name
Test status
Simulation time 21162092 ps
CPU time 1.2 seconds
Started Jun 26 06:28:23 PM PDT 24
Finished Jun 26 06:28:26 PM PDT 24
Peak memory 224248 kb
Host smart-e47ec531-a0e8-4ff3-a614-af040ca63ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875777664 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3875777664
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.4133062889
Short name T728
Test name
Test status
Simulation time 53056349 ps
CPU time 1.05 seconds
Started Jun 26 06:28:31 PM PDT 24
Finished Jun 26 06:28:35 PM PDT 24
Peak memory 217836 kb
Host smart-b9f3e688-7924-4086-8415-51196903eb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133062889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.4133062889
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.2384553992
Short name T463
Test name
Test status
Simulation time 71314670 ps
CPU time 1.2 seconds
Started Jun 26 06:28:20 PM PDT 24
Finished Jun 26 06:28:23 PM PDT 24
Peak memory 215968 kb
Host smart-d960b170-21e4-4273-b8cb-65e1053ac5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384553992 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2384553992
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.2990349924
Short name T219
Test name
Test status
Simulation time 43603580 ps
CPU time 0.82 seconds
Started Jun 26 06:28:25 PM PDT 24
Finished Jun 26 06:28:27 PM PDT 24
Peak memory 218516 kb
Host smart-8a9f0621-b9ef-44f0-bc9e-f9b0bb63d279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990349924 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2990349924
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.4227935017
Short name T598
Test name
Test status
Simulation time 146386446 ps
CPU time 1.12 seconds
Started Jun 26 06:28:17 PM PDT 24
Finished Jun 26 06:28:19 PM PDT 24
Peak memory 217668 kb
Host smart-19b444ec-394e-4e94-8276-2365ca0ac845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227935017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.4227935017
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.2309479759
Short name T737
Test name
Test status
Simulation time 43261826 ps
CPU time 1.28 seconds
Started Jun 26 06:28:18 PM PDT 24
Finished Jun 26 06:28:21 PM PDT 24
Peak memory 219512 kb
Host smart-1f26bd61-0d8e-41e3-bbf0-4b23d21788ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309479759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.2309479759
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.3739730888
Short name T104
Test name
Test status
Simulation time 27496440 ps
CPU time 1.24 seconds
Started Jun 26 06:28:18 PM PDT 24
Finished Jun 26 06:28:20 PM PDT 24
Peak memory 217800 kb
Host smart-036b5cec-35a7-48d7-9d2f-1929d0e079ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739730888 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3739730888
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.204129979
Short name T552
Test name
Test status
Simulation time 86583360 ps
CPU time 1.45 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:43 PM PDT 24
Peak memory 219280 kb
Host smart-1ade5580-bd10-43cb-bb01-ea0271f2cbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204129979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.204129979
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.1238647524
Short name T980
Test name
Test status
Simulation time 74964692 ps
CPU time 1.13 seconds
Started Jun 26 06:28:17 PM PDT 24
Finished Jun 26 06:28:19 PM PDT 24
Peak memory 220636 kb
Host smart-ff3c8780-a7ab-437e-bcdb-c4936de54e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238647524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.1238647524
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.3972856641
Short name T679
Test name
Test status
Simulation time 23904641 ps
CPU time 1.3 seconds
Started Jun 26 06:28:20 PM PDT 24
Finished Jun 26 06:28:22 PM PDT 24
Peak memory 224248 kb
Host smart-5c5aec4f-cfc4-4a4b-8fb5-c238a480d05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972856641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3972856641
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.6107320
Short name T650
Test name
Test status
Simulation time 66111518 ps
CPU time 1.31 seconds
Started Jun 26 06:28:29 PM PDT 24
Finished Jun 26 06:28:33 PM PDT 24
Peak memory 219248 kb
Host smart-92b77e08-a8a5-4fb6-be53-9a0f773b40e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6107320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.6107320
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.1785711011
Short name T451
Test name
Test status
Simulation time 27367552 ps
CPU time 1.29 seconds
Started Jun 26 06:28:31 PM PDT 24
Finished Jun 26 06:28:34 PM PDT 24
Peak memory 220192 kb
Host smart-d47bcacd-3f32-4b7d-927b-cb05bef92c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785711011 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.1785711011
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1219415126
Short name T140
Test name
Test status
Simulation time 26983994 ps
CPU time 1.01 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:39 PM PDT 24
Peak memory 220080 kb
Host smart-8229ceaf-8870-4278-a80c-28086e06b935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219415126 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1219415126
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3018838362
Short name T987
Test name
Test status
Simulation time 78587980 ps
CPU time 1.37 seconds
Started Jun 26 06:28:31 PM PDT 24
Finished Jun 26 06:28:35 PM PDT 24
Peak memory 218964 kb
Host smart-3d9ebc44-711e-4e17-94b7-828325044712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018838362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3018838362
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.2957165509
Short name T623
Test name
Test status
Simulation time 23583562 ps
CPU time 1.25 seconds
Started Jun 26 06:28:34 PM PDT 24
Finished Jun 26 06:28:39 PM PDT 24
Peak memory 220824 kb
Host smart-a3937e1c-b7f2-4f21-ac71-09002c2e8db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957165509 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.2957165509
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.2529338232
Short name T152
Test name
Test status
Simulation time 24882155 ps
CPU time 1.03 seconds
Started Jun 26 06:28:25 PM PDT 24
Finished Jun 26 06:28:27 PM PDT 24
Peak memory 218844 kb
Host smart-c2bec676-9af8-45b4-9519-ea0ade86bb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529338232 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2529338232
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2156629038
Short name T619
Test name
Test status
Simulation time 129287014 ps
CPU time 1.13 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:37 PM PDT 24
Peak memory 217724 kb
Host smart-5eec564a-458b-48cc-b37a-4e1e982716cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156629038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2156629038
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.2229313961
Short name T222
Test name
Test status
Simulation time 29186774 ps
CPU time 1.2 seconds
Started Jun 26 06:28:18 PM PDT 24
Finished Jun 26 06:28:21 PM PDT 24
Peak memory 219532 kb
Host smart-0359c54a-f087-4464-99cc-4cfd3fd5042a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229313961 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.2229313961
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.492428880
Short name T782
Test name
Test status
Simulation time 20072014 ps
CPU time 1.13 seconds
Started Jun 26 06:28:26 PM PDT 24
Finished Jun 26 06:28:29 PM PDT 24
Peak memory 219964 kb
Host smart-e865fd8f-3f5c-4da8-9439-2587f169feb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492428880 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.492428880
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2990186823
Short name T362
Test name
Test status
Simulation time 69398497 ps
CPU time 1.72 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:40 PM PDT 24
Peak memory 218984 kb
Host smart-c95755af-ca23-4b3e-9943-f65032a77f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990186823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2990186823
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.2762180546
Short name T274
Test name
Test status
Simulation time 90205459 ps
CPU time 1.09 seconds
Started Jun 26 06:28:23 PM PDT 24
Finished Jun 26 06:28:26 PM PDT 24
Peak memory 219012 kb
Host smart-55765212-c09a-4469-8378-9d2b05630346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762180546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.2762180546
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.2145547225
Short name T160
Test name
Test status
Simulation time 46201864 ps
CPU time 1.23 seconds
Started Jun 26 06:28:22 PM PDT 24
Finished Jun 26 06:28:25 PM PDT 24
Peak memory 226080 kb
Host smart-ad42e77f-2dc6-467e-be03-c02ccd2556f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145547225 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2145547225
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2693281237
Short name T834
Test name
Test status
Simulation time 65464057 ps
CPU time 1.48 seconds
Started Jun 26 06:28:19 PM PDT 24
Finished Jun 26 06:28:22 PM PDT 24
Peak memory 219160 kb
Host smart-cbee9a4b-0eac-4c33-ac55-9b89fa92988d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693281237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2693281237
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3238004081
Short name T776
Test name
Test status
Simulation time 27290127 ps
CPU time 1.24 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:27:18 PM PDT 24
Peak memory 220028 kb
Host smart-8e81cca4-7f46-4a21-bbec-8a3a0b4fe4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238004081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3238004081
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1846483774
Short name T849
Test name
Test status
Simulation time 59808104 ps
CPU time 0.99 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:27:19 PM PDT 24
Peak memory 215396 kb
Host smart-d64b8173-945a-409b-b68a-842eca991af1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846483774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1846483774
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1240437509
Short name T687
Test name
Test status
Simulation time 18372542 ps
CPU time 0.87 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:24 PM PDT 24
Peak memory 215780 kb
Host smart-ba129379-86d6-48f4-a040-1cd0638f375a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240437509 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1240437509
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1217157471
Short name T125
Test name
Test status
Simulation time 79608051 ps
CPU time 1.2 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:24 PM PDT 24
Peak memory 217232 kb
Host smart-23ebbc2a-ef01-439d-aae5-1e15a06d8d24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217157471 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1217157471
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1944412283
Short name T194
Test name
Test status
Simulation time 22768011 ps
CPU time 1.08 seconds
Started Jun 26 06:27:13 PM PDT 24
Finished Jun 26 06:27:15 PM PDT 24
Peak memory 229880 kb
Host smart-ed342c6f-4230-4cfb-bb92-f6396a72a694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944412283 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1944412283
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2463511556
Short name T830
Test name
Test status
Simulation time 46934421 ps
CPU time 1.75 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:27:18 PM PDT 24
Peak memory 218820 kb
Host smart-8a2d9273-e27f-4f48-a9db-51f4233f1a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463511556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2463511556
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1673746915
Short name T478
Test name
Test status
Simulation time 35957841 ps
CPU time 0.94 seconds
Started Jun 26 06:27:19 PM PDT 24
Finished Jun 26 06:27:25 PM PDT 24
Peak memory 215748 kb
Host smart-fbeab963-46af-48d5-b0d0-1066db0156ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673746915 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1673746915
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.713840850
Short name T24
Test name
Test status
Simulation time 16152946 ps
CPU time 1.03 seconds
Started Jun 26 06:27:12 PM PDT 24
Finished Jun 26 06:27:14 PM PDT 24
Peak memory 207404 kb
Host smart-07751ea7-fda5-43a3-9e0d-0aae9157dc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713840850 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.713840850
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3660925188
Short name T901
Test name
Test status
Simulation time 14794971 ps
CPU time 0.98 seconds
Started Jun 26 06:27:04 PM PDT 24
Finished Jun 26 06:27:06 PM PDT 24
Peak memory 215604 kb
Host smart-f903bcef-bf81-4f76-bb43-89908bc5a466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660925188 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3660925188
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1614578831
Short name T291
Test name
Test status
Simulation time 770349883 ps
CPU time 4.65 seconds
Started Jun 26 06:27:12 PM PDT 24
Finished Jun 26 06:27:18 PM PDT 24
Peak memory 217740 kb
Host smart-d072a2d7-601a-421c-9393-9c7da1a2292e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614578831 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1614578831
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1236011764
Short name T599
Test name
Test status
Simulation time 212760193086 ps
CPU time 2658.52 seconds
Started Jun 26 06:27:01 PM PDT 24
Finished Jun 26 07:11:21 PM PDT 24
Peak memory 233824 kb
Host smart-a370e5dc-c370-4d39-a276-16f3bc285b02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236011764 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1236011764
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.3164308170
Short name T49
Test name
Test status
Simulation time 87033197 ps
CPU time 1.1 seconds
Started Jun 26 06:28:34 PM PDT 24
Finished Jun 26 06:28:39 PM PDT 24
Peak memory 218816 kb
Host smart-386c6cf5-2399-4e4f-8072-6048fda828e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164308170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.3164308170
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.309518625
Short name T161
Test name
Test status
Simulation time 19863451 ps
CPU time 1.17 seconds
Started Jun 26 06:28:19 PM PDT 24
Finished Jun 26 06:28:22 PM PDT 24
Peak memory 218704 kb
Host smart-814bac99-7968-4574-9d59-724401c1fec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309518625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.309518625
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.781328352
Short name T329
Test name
Test status
Simulation time 19940747 ps
CPU time 1.09 seconds
Started Jun 26 06:28:18 PM PDT 24
Finished Jun 26 06:28:20 PM PDT 24
Peak memory 218036 kb
Host smart-82865273-51ff-4679-a324-fd11f23a239f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781328352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.781328352
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.1544827003
Short name T162
Test name
Test status
Simulation time 19550337 ps
CPU time 1.2 seconds
Started Jun 26 06:28:28 PM PDT 24
Finished Jun 26 06:28:31 PM PDT 24
Peak memory 224336 kb
Host smart-dadecc49-65a5-40d0-be2d-ad04acd11eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544827003 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1544827003
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3639427644
Short name T897
Test name
Test status
Simulation time 106615938 ps
CPU time 0.93 seconds
Started Jun 26 06:28:18 PM PDT 24
Finished Jun 26 06:28:20 PM PDT 24
Peak memory 217768 kb
Host smart-d90377d9-c863-4309-976e-3a7306225767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639427644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3639427644
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.65922287
Short name T414
Test name
Test status
Simulation time 71315125 ps
CPU time 1.1 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:37 PM PDT 24
Peak memory 219400 kb
Host smart-b91a5ad3-ed25-4cec-aa4b-37201b2db4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65922287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.65922287
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.905089720
Short name T200
Test name
Test status
Simulation time 24081961 ps
CPU time 1.16 seconds
Started Jun 26 06:28:36 PM PDT 24
Finished Jun 26 06:28:42 PM PDT 24
Peak memory 218812 kb
Host smart-8cffaf8e-15e9-4780-b065-4536dd67881d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905089720 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.905089720
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.366993052
Short name T311
Test name
Test status
Simulation time 49460799 ps
CPU time 1.75 seconds
Started Jun 26 06:28:36 PM PDT 24
Finished Jun 26 06:28:42 PM PDT 24
Peak memory 220628 kb
Host smart-efb1df05-7e2f-4e40-9a44-37bdc2b00f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366993052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.366993052
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.2619627918
Short name T667
Test name
Test status
Simulation time 102351461 ps
CPU time 1.36 seconds
Started Jun 26 06:28:34 PM PDT 24
Finished Jun 26 06:28:40 PM PDT 24
Peak memory 215976 kb
Host smart-fdf1492e-4160-424d-97ed-8dd210f6f570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619627918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2619627918
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.613107602
Short name T941
Test name
Test status
Simulation time 33082530 ps
CPU time 1.32 seconds
Started Jun 26 06:28:34 PM PDT 24
Finished Jun 26 06:28:49 PM PDT 24
Peak memory 225868 kb
Host smart-ad4338bc-8c38-4ab5-a4f0-79e30ed97c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613107602 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.613107602
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1697226395
Short name T466
Test name
Test status
Simulation time 74209867 ps
CPU time 2.69 seconds
Started Jun 26 06:28:26 PM PDT 24
Finished Jun 26 06:28:30 PM PDT 24
Peak memory 220460 kb
Host smart-3a56a591-801a-48e5-957e-29d899d0f67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697226395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1697226395
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.1545504780
Short name T605
Test name
Test status
Simulation time 42482530 ps
CPU time 1.11 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:38 PM PDT 24
Peak memory 219112 kb
Host smart-68e8966a-e1c5-46b0-aad5-d8b2d3a70011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545504780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.1545504780
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2795879538
Short name T114
Test name
Test status
Simulation time 55291276 ps
CPU time 0.93 seconds
Started Jun 26 06:28:26 PM PDT 24
Finished Jun 26 06:28:28 PM PDT 24
Peak memory 219940 kb
Host smart-f5db9e70-f250-4371-ad1d-9acd6d7bb564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795879538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2795879538
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3612393887
Short name T715
Test name
Test status
Simulation time 53509328 ps
CPU time 1.32 seconds
Started Jun 26 06:28:30 PM PDT 24
Finished Jun 26 06:28:34 PM PDT 24
Peak memory 219112 kb
Host smart-73e79c06-063a-4818-9064-a990c0525cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612393887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3612393887
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.408219899
Short name T874
Test name
Test status
Simulation time 31017604 ps
CPU time 1.39 seconds
Started Jun 26 06:28:27 PM PDT 24
Finished Jun 26 06:28:30 PM PDT 24
Peak memory 216056 kb
Host smart-6f3fa62d-0ead-4da6-8912-84b0680a6bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408219899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.408219899
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.3604795732
Short name T658
Test name
Test status
Simulation time 25365737 ps
CPU time 0.9 seconds
Started Jun 26 06:28:28 PM PDT 24
Finished Jun 26 06:28:31 PM PDT 24
Peak memory 218596 kb
Host smart-3d62bede-52e8-4311-9076-a437a9ad8266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604795732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3604795732
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.4010176818
Short name T1
Test name
Test status
Simulation time 40738194 ps
CPU time 1.14 seconds
Started Jun 26 06:28:26 PM PDT 24
Finished Jun 26 06:28:29 PM PDT 24
Peak memory 219044 kb
Host smart-c1b59af2-fd0d-45e6-affd-2866b1cf746f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010176818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.4010176818
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.3810997975
Short name T470
Test name
Test status
Simulation time 106573219 ps
CPU time 1.26 seconds
Started Jun 26 06:28:25 PM PDT 24
Finished Jun 26 06:28:27 PM PDT 24
Peak memory 219924 kb
Host smart-19af741e-b74c-462c-9862-292dfbd707a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810997975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.3810997975
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.984662761
Short name T167
Test name
Test status
Simulation time 24970011 ps
CPU time 0.96 seconds
Started Jun 26 06:28:34 PM PDT 24
Finished Jun 26 06:28:40 PM PDT 24
Peak memory 218828 kb
Host smart-c8cd23a1-296c-4397-9e6b-f74731147d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984662761 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.984662761
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3645786685
Short name T884
Test name
Test status
Simulation time 59546875 ps
CPU time 1.72 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:38 PM PDT 24
Peak memory 218648 kb
Host smart-647e85b2-f80b-4c6e-8248-6596b815b2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645786685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3645786685
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.4274945316
Short name T879
Test name
Test status
Simulation time 123548844 ps
CPU time 1.21 seconds
Started Jun 26 06:28:25 PM PDT 24
Finished Jun 26 06:28:28 PM PDT 24
Peak memory 219332 kb
Host smart-13d51deb-e520-4b66-b8ad-847ff019562c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274945316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.4274945316
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.3573239759
Short name T115
Test name
Test status
Simulation time 30381454 ps
CPU time 1.19 seconds
Started Jun 26 06:28:35 PM PDT 24
Finished Jun 26 06:28:40 PM PDT 24
Peak memory 229916 kb
Host smart-6241fc21-d561-4ee7-a1c8-c0e7e7f442fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573239759 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3573239759
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1366271417
Short name T635
Test name
Test status
Simulation time 89816299 ps
CPU time 1.15 seconds
Started Jun 26 06:28:23 PM PDT 24
Finished Jun 26 06:28:26 PM PDT 24
Peak memory 217708 kb
Host smart-a557d64e-4d5e-418f-895a-4cd88a1b922d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366271417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1366271417
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.3945312316
Short name T432
Test name
Test status
Simulation time 81035388 ps
CPU time 1.15 seconds
Started Jun 26 06:28:32 PM PDT 24
Finished Jun 26 06:28:37 PM PDT 24
Peak memory 219964 kb
Host smart-c7148c08-435c-4f7d-b879-5398851e4a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945312316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.3945312316
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.522665383
Short name T365
Test name
Test status
Simulation time 50048501 ps
CPU time 0.96 seconds
Started Jun 26 06:28:36 PM PDT 24
Finished Jun 26 06:28:42 PM PDT 24
Peak memory 218824 kb
Host smart-afe1846b-415b-4d36-af46-80afbf412a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522665383 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.522665383
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.671964944
Short name T553
Test name
Test status
Simulation time 165735561 ps
CPU time 1.3 seconds
Started Jun 26 06:28:40 PM PDT 24
Finished Jun 26 06:28:45 PM PDT 24
Peak memory 219380 kb
Host smart-fbf5d3a3-779e-4816-8c6f-73ffb0f53343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671964944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.671964944
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.2845972325
Short name T142
Test name
Test status
Simulation time 68808526 ps
CPU time 1.13 seconds
Started Jun 26 06:28:32 PM PDT 24
Finished Jun 26 06:28:37 PM PDT 24
Peak memory 220232 kb
Host smart-53725338-b591-4acb-b88b-3179f9099dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845972325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.2845972325
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.2624213637
Short name T218
Test name
Test status
Simulation time 32764592 ps
CPU time 1.21 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:37 PM PDT 24
Peak memory 219732 kb
Host smart-6643eb7d-8e8c-4957-8e30-1f498666cd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624213637 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2624213637
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1985489541
Short name T45
Test name
Test status
Simulation time 45300702 ps
CPU time 1.64 seconds
Started Jun 26 06:28:35 PM PDT 24
Finished Jun 26 06:28:41 PM PDT 24
Peak memory 217872 kb
Host smart-699ee1ff-c4cd-44e8-b544-61d5872ca6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985489541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1985489541
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3808560608
Short name T179
Test name
Test status
Simulation time 25433941 ps
CPU time 1.2 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:23 PM PDT 24
Peak memory 219904 kb
Host smart-b7048a5c-1e2f-4e3a-8c1c-1b5baf3c944f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808560608 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3808560608
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2440345977
Short name T759
Test name
Test status
Simulation time 17246331 ps
CPU time 0.99 seconds
Started Jun 26 06:27:15 PM PDT 24
Finished Jun 26 06:27:20 PM PDT 24
Peak memory 215412 kb
Host smart-f7ca38b8-0ce9-49d2-8689-009b57d42299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440345977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2440345977
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.427398031
Short name T576
Test name
Test status
Simulation time 80488078 ps
CPU time 0.83 seconds
Started Jun 26 06:27:16 PM PDT 24
Finished Jun 26 06:27:21 PM PDT 24
Peak memory 215780 kb
Host smart-60701720-b8e3-44ce-ba3a-c48fec32f066
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427398031 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.427398031
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.884317455
Short name T280
Test name
Test status
Simulation time 33083571 ps
CPU time 0.99 seconds
Started Jun 26 06:27:11 PM PDT 24
Finished Jun 26 06:27:12 PM PDT 24
Peak memory 217076 kb
Host smart-59e9bec5-e923-4488-b291-c84e25a70163
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884317455 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.884317455
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3225934985
Short name T530
Test name
Test status
Simulation time 32844971 ps
CPU time 1.1 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:23 PM PDT 24
Peak memory 229888 kb
Host smart-5b422181-4f74-4774-9f87-7c28adb64acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225934985 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3225934985
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.538717993
Short name T52
Test name
Test status
Simulation time 55844309 ps
CPU time 1.38 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:24 PM PDT 24
Peak memory 218820 kb
Host smart-c0d2c582-5bfe-48ed-ab17-2b2486e67bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538717993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.538717993
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.89247056
Short name T594
Test name
Test status
Simulation time 21938445 ps
CPU time 1.11 seconds
Started Jun 26 06:27:20 PM PDT 24
Finished Jun 26 06:27:26 PM PDT 24
Peak memory 215868 kb
Host smart-b1c6acd8-af53-49b6-a8eb-982f12ca773e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89247056 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.89247056
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.667474256
Short name T865
Test name
Test status
Simulation time 48541242 ps
CPU time 0.97 seconds
Started Jun 26 06:27:12 PM PDT 24
Finished Jun 26 06:27:15 PM PDT 24
Peak memory 207444 kb
Host smart-7d30e742-9ae1-4d15-8d49-84998b1cf154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667474256 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.667474256
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.980502896
Short name T661
Test name
Test status
Simulation time 34686923 ps
CPU time 0.98 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:23 PM PDT 24
Peak memory 215652 kb
Host smart-53118821-82b7-4609-97e6-99a9c4173196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980502896 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.980502896
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1852153069
Short name T780
Test name
Test status
Simulation time 99822333 ps
CPU time 1.57 seconds
Started Jun 26 06:27:18 PM PDT 24
Finished Jun 26 06:27:25 PM PDT 24
Peak memory 218708 kb
Host smart-dc1df727-4cd3-45fa-be02-9f8fca873e9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852153069 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1852153069
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.693283581
Short name T232
Test name
Test status
Simulation time 25820135312 ps
CPU time 282.44 seconds
Started Jun 26 06:27:14 PM PDT 24
Finished Jun 26 06:32:00 PM PDT 24
Peak memory 218296 kb
Host smart-62d27edc-b1c3-4880-ad88-8a58bd279f6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693283581 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.693283581
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.2212672862
Short name T748
Test name
Test status
Simulation time 40352281 ps
CPU time 1.18 seconds
Started Jun 26 06:28:29 PM PDT 24
Finished Jun 26 06:28:32 PM PDT 24
Peak memory 218804 kb
Host smart-f9edff12-405b-4da1-8e65-62500bf880c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212672862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2212672862
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.2964747537
Short name T551
Test name
Test status
Simulation time 25682823 ps
CPU time 0.92 seconds
Started Jun 26 06:28:25 PM PDT 24
Finished Jun 26 06:28:28 PM PDT 24
Peak memory 215532 kb
Host smart-f2400f37-b23f-4703-8954-b0fa3ab2d3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964747537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2964747537
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2050439637
Short name T848
Test name
Test status
Simulation time 29071044 ps
CPU time 1.19 seconds
Started Jun 26 06:28:24 PM PDT 24
Finished Jun 26 06:28:26 PM PDT 24
Peak memory 217632 kb
Host smart-28f0f88f-9417-4d95-80a1-483d7a8a6dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050439637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2050439637
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1184370568
Short name T724
Test name
Test status
Simulation time 48817290 ps
CPU time 1.23 seconds
Started Jun 26 06:28:32 PM PDT 24
Finished Jun 26 06:28:37 PM PDT 24
Peak memory 218992 kb
Host smart-2f168ce2-b58c-453a-98d5-e473efc0ce66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184370568 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1184370568
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.2168672683
Short name T839
Test name
Test status
Simulation time 123445711 ps
CPU time 1.17 seconds
Started Jun 26 06:28:29 PM PDT 24
Finished Jun 26 06:28:32 PM PDT 24
Peak memory 224292 kb
Host smart-05c20940-a026-4db4-98eb-d57ad4760ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168672683 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2168672683
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1591655084
Short name T313
Test name
Test status
Simulation time 83345018 ps
CPU time 1.53 seconds
Started Jun 26 06:28:26 PM PDT 24
Finished Jun 26 06:28:29 PM PDT 24
Peak memory 217900 kb
Host smart-3b933cf1-7af1-44d6-9974-4a099a73dd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591655084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1591655084
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.1719884077
Short name T166
Test name
Test status
Simulation time 100814453 ps
CPU time 1.12 seconds
Started Jun 26 06:28:29 PM PDT 24
Finished Jun 26 06:28:32 PM PDT 24
Peak memory 219836 kb
Host smart-00602e24-6103-44c2-9b82-8719e44b24ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719884077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.1719884077
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.3863426533
Short name T130
Test name
Test status
Simulation time 74297508 ps
CPU time 1.03 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:37 PM PDT 24
Peak memory 229848 kb
Host smart-e427238a-5374-43d9-88d5-b27b2ee66f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863426533 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3863426533
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.868125558
Short name T325
Test name
Test status
Simulation time 43953574 ps
CPU time 1.88 seconds
Started Jun 26 06:28:35 PM PDT 24
Finished Jun 26 06:28:41 PM PDT 24
Peak memory 219028 kb
Host smart-1a114105-f542-4230-aaae-b5c4cd5b4234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868125558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.868125558
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.925631876
Short name T155
Test name
Test status
Simulation time 30820089 ps
CPU time 1.01 seconds
Started Jun 26 06:28:30 PM PDT 24
Finished Jun 26 06:28:33 PM PDT 24
Peak memory 224124 kb
Host smart-98786951-0827-4bee-94db-6f43c30ca398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925631876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.925631876
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1525677205
Short name T627
Test name
Test status
Simulation time 199429388 ps
CPU time 1.09 seconds
Started Jun 26 06:28:24 PM PDT 24
Finished Jun 26 06:28:26 PM PDT 24
Peak memory 217788 kb
Host smart-a19ee179-18e0-4628-8e34-2a1fcb4cab41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525677205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1525677205
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.1649461278
Short name T942
Test name
Test status
Simulation time 33574181 ps
CPU time 1.35 seconds
Started Jun 26 06:28:24 PM PDT 24
Finished Jun 26 06:28:27 PM PDT 24
Peak memory 216012 kb
Host smart-7546ce0b-d823-4c76-bf75-779edce3ea10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649461278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.1649461278
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.443932064
Short name T214
Test name
Test status
Simulation time 55682786 ps
CPU time 1.38 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:39 PM PDT 24
Peak memory 226084 kb
Host smart-0385baaf-f01c-445a-96ce-fbd3c9e59c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443932064 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.443932064
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.709479861
Short name T696
Test name
Test status
Simulation time 76841693 ps
CPU time 1.25 seconds
Started Jun 26 06:28:38 PM PDT 24
Finished Jun 26 06:28:43 PM PDT 24
Peak memory 219368 kb
Host smart-38d74033-9265-47c7-82dc-68d3683a4897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709479861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.709479861
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.1680669300
Short name T731
Test name
Test status
Simulation time 28467552 ps
CPU time 1.12 seconds
Started Jun 26 06:28:28 PM PDT 24
Finished Jun 26 06:28:30 PM PDT 24
Peak memory 218992 kb
Host smart-659b1e24-2308-47ca-968f-d936c11f66fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680669300 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.1680669300
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.3296812600
Short name T156
Test name
Test status
Simulation time 30862877 ps
CPU time 0.87 seconds
Started Jun 26 06:28:23 PM PDT 24
Finished Jun 26 06:28:25 PM PDT 24
Peak memory 218516 kb
Host smart-fd4139f7-c0a1-4a10-afda-03370d3225d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296812600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3296812600
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1884687247
Short name T503
Test name
Test status
Simulation time 42252884 ps
CPU time 1.39 seconds
Started Jun 26 06:28:28 PM PDT 24
Finished Jun 26 06:28:31 PM PDT 24
Peak memory 218708 kb
Host smart-329d90fa-d15d-430b-a4dc-8088f9f6d1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884687247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1884687247
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.1885906824
Short name T701
Test name
Test status
Simulation time 25222856 ps
CPU time 1.19 seconds
Started Jun 26 06:28:31 PM PDT 24
Finished Jun 26 06:28:35 PM PDT 24
Peak memory 220948 kb
Host smart-ce6d289f-8f6b-4663-93d9-1dd265daea84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885906824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1885906824
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.3491946586
Short name T5
Test name
Test status
Simulation time 22933931 ps
CPU time 1.24 seconds
Started Jun 26 06:28:31 PM PDT 24
Finished Jun 26 06:28:35 PM PDT 24
Peak memory 224268 kb
Host smart-57b9389f-769d-4b4d-9106-42dbb12edd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491946586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3491946586
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2568469121
Short name T871
Test name
Test status
Simulation time 53639998 ps
CPU time 1.69 seconds
Started Jun 26 06:28:28 PM PDT 24
Finished Jun 26 06:28:31 PM PDT 24
Peak memory 218912 kb
Host smart-ab404a91-0ac6-4a38-87fd-d96645f47e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568469121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2568469121
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.3477485672
Short name T880
Test name
Test status
Simulation time 31799053 ps
CPU time 1.33 seconds
Started Jun 26 06:28:34 PM PDT 24
Finished Jun 26 06:28:40 PM PDT 24
Peak memory 216044 kb
Host smart-87798d08-db2a-4e70-8f26-c94109850b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477485672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.3477485672
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.2675100188
Short name T418
Test name
Test status
Simulation time 20351293 ps
CPU time 0.96 seconds
Started Jun 26 06:28:24 PM PDT 24
Finished Jun 26 06:28:32 PM PDT 24
Peak memory 218544 kb
Host smart-6be9b45f-8ac5-4a77-aa2d-fad34f85874e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675100188 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2675100188
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.454376985
Short name T893
Test name
Test status
Simulation time 34377735 ps
CPU time 1.1 seconds
Started Jun 26 06:28:35 PM PDT 24
Finished Jun 26 06:28:40 PM PDT 24
Peak memory 217700 kb
Host smart-e873c997-aa6e-4afe-ab01-c562bde9e7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454376985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.454376985
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.2702232925
Short name T843
Test name
Test status
Simulation time 41386623 ps
CPU time 1.22 seconds
Started Jun 26 06:28:36 PM PDT 24
Finished Jun 26 06:28:42 PM PDT 24
Peak memory 221416 kb
Host smart-8c8cb2d1-3788-4e82-9e4d-e04ef228dc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702232925 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.2702232925
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.2229343914
Short name T413
Test name
Test status
Simulation time 73845648 ps
CPU time 1.19 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:39 PM PDT 24
Peak memory 225996 kb
Host smart-c6cac0d7-e6ca-41fd-bb17-cb3b4f07eaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229343914 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2229343914
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3128353443
Short name T511
Test name
Test status
Simulation time 127315877 ps
CPU time 2.78 seconds
Started Jun 26 06:28:31 PM PDT 24
Finished Jun 26 06:28:36 PM PDT 24
Peak memory 218988 kb
Host smart-460ba7fb-83c9-4cd4-9ac6-8be50bb898de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128353443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3128353443
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.464066377
Short name T844
Test name
Test status
Simulation time 137880741 ps
CPU time 1.07 seconds
Started Jun 26 06:28:46 PM PDT 24
Finished Jun 26 06:28:51 PM PDT 24
Peak memory 218708 kb
Host smart-11297fff-4223-4f91-99a4-3d4301129a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464066377 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.464066377
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.3407471955
Short name T913
Test name
Test status
Simulation time 26501938 ps
CPU time 1.2 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:39 PM PDT 24
Peak memory 218940 kb
Host smart-1f625ab0-59a3-40cb-935a-b62c4e9faa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407471955 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3407471955
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2965380154
Short name T444
Test name
Test status
Simulation time 48267465 ps
CPU time 1.19 seconds
Started Jun 26 06:28:36 PM PDT 24
Finished Jun 26 06:28:41 PM PDT 24
Peak memory 218804 kb
Host smart-2dd8cb17-8dec-4ebd-ba9b-d3235a3b2097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965380154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2965380154
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3227647344
Short name T866
Test name
Test status
Simulation time 82068058 ps
CPU time 1.12 seconds
Started Jun 26 06:27:13 PM PDT 24
Finished Jun 26 06:27:15 PM PDT 24
Peak memory 218752 kb
Host smart-a22f0660-7c3a-41d0-90ef-0dff4b63ab3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227647344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3227647344
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.4230296802
Short name T675
Test name
Test status
Simulation time 13761324 ps
CPU time 0.91 seconds
Started Jun 26 06:27:15 PM PDT 24
Finished Jun 26 06:27:20 PM PDT 24
Peak memory 207076 kb
Host smart-b8223cd3-b6b3-4b09-acca-8b51c32757d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230296802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.4230296802
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.28534204
Short name T169
Test name
Test status
Simulation time 27156677 ps
CPU time 0.84 seconds
Started Jun 26 06:27:13 PM PDT 24
Finished Jun 26 06:27:16 PM PDT 24
Peak memory 216612 kb
Host smart-1b0ba6ab-22db-4eaa-a003-6e20b914ef70
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28534204 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.28534204
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.233720177
Short name T969
Test name
Test status
Simulation time 46957152 ps
CPU time 1.05 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:24 PM PDT 24
Peak memory 217232 kb
Host smart-85850405-daca-4188-9efe-d3466299b6f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233720177 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.233720177
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.2849943744
Short name T846
Test name
Test status
Simulation time 22636478 ps
CPU time 1.13 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:23 PM PDT 24
Peak memory 224216 kb
Host smart-9b6847bd-223f-44da-9396-6e7fecea27dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849943744 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2849943744
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1911053881
Short name T822
Test name
Test status
Simulation time 30007702 ps
CPU time 1.53 seconds
Started Jun 26 06:27:19 PM PDT 24
Finished Jun 26 06:27:26 PM PDT 24
Peak memory 218788 kb
Host smart-6efe2646-9f10-4f25-89e6-db88151c2636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911053881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1911053881
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_regwen.829421457
Short name T802
Test name
Test status
Simulation time 80600950 ps
CPU time 0.95 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:27:24 PM PDT 24
Peak memory 207420 kb
Host smart-f0e5cc29-f6ae-435a-84cb-3710f382e5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829421457 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.829421457
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1434799929
Short name T670
Test name
Test status
Simulation time 17814136 ps
CPU time 1.03 seconds
Started Jun 26 06:27:11 PM PDT 24
Finished Jun 26 06:27:13 PM PDT 24
Peak memory 215668 kb
Host smart-3dd661ea-fa5a-4c47-bfbd-1789ab6f71bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434799929 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1434799929
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3900378784
Short name T673
Test name
Test status
Simulation time 34537569 ps
CPU time 1.1 seconds
Started Jun 26 06:27:11 PM PDT 24
Finished Jun 26 06:27:13 PM PDT 24
Peak memory 215612 kb
Host smart-eabd5694-a77d-4be4-8364-4d42d812d3e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900378784 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3900378784
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2462261749
Short name T662
Test name
Test status
Simulation time 45601350672 ps
CPU time 899.34 seconds
Started Jun 26 06:27:17 PM PDT 24
Finished Jun 26 06:42:22 PM PDT 24
Peak memory 224028 kb
Host smart-e77e5a38-7755-42da-ad54-30d8edfe333b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462261749 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2462261749
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.2752454687
Short name T656
Test name
Test status
Simulation time 26808610 ps
CPU time 1.3 seconds
Started Jun 26 06:28:35 PM PDT 24
Finished Jun 26 06:28:41 PM PDT 24
Peak memory 220824 kb
Host smart-347c1898-4923-4827-8698-c784211a6ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752454687 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.2752454687
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.78572816
Short name T121
Test name
Test status
Simulation time 47661737 ps
CPU time 1.1 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:39 PM PDT 24
Peak memory 229944 kb
Host smart-e1320441-39e7-48c4-9736-185286ad199a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78572816 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.78572816
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.513519509
Short name T508
Test name
Test status
Simulation time 52593753 ps
CPU time 1.22 seconds
Started Jun 26 06:28:35 PM PDT 24
Finished Jun 26 06:28:40 PM PDT 24
Peak memory 217608 kb
Host smart-b21d5679-f9f9-4672-bbb0-b5d7db4b646a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513519509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.513519509
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.478880745
Short name T112
Test name
Test status
Simulation time 38170264 ps
CPU time 1.01 seconds
Started Jun 26 06:28:25 PM PDT 24
Finished Jun 26 06:28:27 PM PDT 24
Peak memory 220148 kb
Host smart-c1d370c3-5cab-43b0-a7a3-24f6a47586c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478880745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.478880745
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1786793826
Short name T66
Test name
Test status
Simulation time 21850017 ps
CPU time 1.12 seconds
Started Jun 26 06:28:34 PM PDT 24
Finished Jun 26 06:28:40 PM PDT 24
Peak memory 220072 kb
Host smart-c1802512-9e03-4e91-aa33-14274e27cf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786793826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1786793826
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.533746427
Short name T588
Test name
Test status
Simulation time 26743291 ps
CPU time 1.14 seconds
Started Jun 26 06:28:38 PM PDT 24
Finished Jun 26 06:28:43 PM PDT 24
Peak memory 218880 kb
Host smart-8b1a4773-2870-4be2-b9d4-f572ded4117a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533746427 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.533746427
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1453016478
Short name T685
Test name
Test status
Simulation time 41557821 ps
CPU time 1.22 seconds
Started Jun 26 06:28:38 PM PDT 24
Finished Jun 26 06:28:44 PM PDT 24
Peak memory 218892 kb
Host smart-a684ed32-1615-4636-9bbf-7c8e09748c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453016478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1453016478
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.2606266976
Short name T573
Test name
Test status
Simulation time 233817467 ps
CPU time 1.01 seconds
Started Jun 26 06:28:38 PM PDT 24
Finished Jun 26 06:28:43 PM PDT 24
Peak memory 218788 kb
Host smart-8d22a1e7-37df-4b0b-a0b1-089e95cd0e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606266976 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.2606266976
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.3975041090
Short name T449
Test name
Test status
Simulation time 40955408 ps
CPU time 0.91 seconds
Started Jun 26 06:28:25 PM PDT 24
Finished Jun 26 06:28:28 PM PDT 24
Peak memory 218488 kb
Host smart-9baa2b4a-e5ee-4177-98a9-24e07fbc452d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975041090 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3975041090
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1447005285
Short name T12
Test name
Test status
Simulation time 80069166 ps
CPU time 1.35 seconds
Started Jun 26 06:28:38 PM PDT 24
Finished Jun 26 06:28:44 PM PDT 24
Peak memory 220560 kb
Host smart-80245595-d3a1-495a-bc58-3bab28a8531b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447005285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1447005285
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1112953217
Short name T816
Test name
Test status
Simulation time 27221737 ps
CPU time 1.22 seconds
Started Jun 26 06:28:25 PM PDT 24
Finished Jun 26 06:28:28 PM PDT 24
Peak memory 219020 kb
Host smart-3adb4999-724d-4af0-a7fe-9df5f784dccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112953217 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1112953217
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.48710144
Short name T917
Test name
Test status
Simulation time 77183443 ps
CPU time 0.89 seconds
Started Jun 26 06:28:36 PM PDT 24
Finished Jun 26 06:28:42 PM PDT 24
Peak memory 219612 kb
Host smart-9c76c958-381e-4acc-ab0e-6afa8bf63913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48710144 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.48710144
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3945698310
Short name T577
Test name
Test status
Simulation time 98184409 ps
CPU time 1.29 seconds
Started Jun 26 06:28:36 PM PDT 24
Finished Jun 26 06:28:42 PM PDT 24
Peak memory 220224 kb
Host smart-59256c29-4512-405f-9fc9-1039527b334d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945698310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3945698310
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.77233558
Short name T395
Test name
Test status
Simulation time 31164858 ps
CPU time 1.39 seconds
Started Jun 26 06:28:36 PM PDT 24
Finished Jun 26 06:28:42 PM PDT 24
Peak memory 216044 kb
Host smart-f76ce8d9-5dd6-4845-86cb-1cfa14430608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77233558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.77233558
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.3471884167
Short name T740
Test name
Test status
Simulation time 18587711 ps
CPU time 1.07 seconds
Started Jun 26 06:28:27 PM PDT 24
Finished Jun 26 06:28:30 PM PDT 24
Peak memory 218940 kb
Host smart-bdef07fd-9d86-4d43-bbb2-e748176cb895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471884167 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3471884167
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2755148909
Short name T743
Test name
Test status
Simulation time 39807010 ps
CPU time 1.62 seconds
Started Jun 26 06:28:36 PM PDT 24
Finished Jun 26 06:28:42 PM PDT 24
Peak memory 218828 kb
Host smart-f9085523-90e5-45a7-b1f7-a8411624c241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755148909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2755148909
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1238466697
Short name T319
Test name
Test status
Simulation time 35953813 ps
CPU time 1.08 seconds
Started Jun 26 06:28:32 PM PDT 24
Finished Jun 26 06:28:37 PM PDT 24
Peak memory 216044 kb
Host smart-699ff57e-1a46-4731-b273-dfeeb7c27536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238466697 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1238466697
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.905193232
Short name T994
Test name
Test status
Simulation time 18568869 ps
CPU time 1.07 seconds
Started Jun 26 06:28:30 PM PDT 24
Finished Jun 26 06:28:33 PM PDT 24
Peak memory 218944 kb
Host smart-410515f1-6bda-48a0-9f3f-b632ca2d1d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905193232 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.905193232
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1091534370
Short name T722
Test name
Test status
Simulation time 66817145 ps
CPU time 2.46 seconds
Started Jun 26 06:28:37 PM PDT 24
Finished Jun 26 06:28:44 PM PDT 24
Peak memory 220512 kb
Host smart-1b46db56-cbc9-46e8-baf6-2796bd5ee9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091534370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1091534370
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.4061137078
Short name T974
Test name
Test status
Simulation time 65699096 ps
CPU time 1.31 seconds
Started Jun 26 06:28:31 PM PDT 24
Finished Jun 26 06:28:34 PM PDT 24
Peak memory 216244 kb
Host smart-741f129a-9fbe-4034-8ec8-de1e7961b3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061137078 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.4061137078
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.1698512385
Short name T122
Test name
Test status
Simulation time 65735813 ps
CPU time 0.96 seconds
Started Jun 26 06:28:33 PM PDT 24
Finished Jun 26 06:28:38 PM PDT 24
Peak memory 229676 kb
Host smart-a5db45bc-3b9b-4c7d-b29a-3c71e9b1b220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698512385 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1698512385
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1754875756
Short name T911
Test name
Test status
Simulation time 35087482 ps
CPU time 1.34 seconds
Started Jun 26 06:28:36 PM PDT 24
Finished Jun 26 06:28:42 PM PDT 24
Peak memory 218856 kb
Host smart-1af04c1c-f1f0-419f-83e1-4cc8d6dbc07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754875756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1754875756
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.349956907
Short name T636
Test name
Test status
Simulation time 30979388 ps
CPU time 1.15 seconds
Started Jun 26 06:28:38 PM PDT 24
Finished Jun 26 06:28:43 PM PDT 24
Peak memory 219992 kb
Host smart-45e60c86-ef26-4407-bdb7-edaca96dffb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349956907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.349956907
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_genbits.2010077542
Short name T778
Test name
Test status
Simulation time 82281043 ps
CPU time 1.23 seconds
Started Jun 26 06:28:29 PM PDT 24
Finished Jun 26 06:28:33 PM PDT 24
Peak memory 217540 kb
Host smart-65553f6b-4975-4e35-a514-6af2919851fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010077542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2010077542
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.135843352
Short name T147
Test name
Test status
Simulation time 24778665 ps
CPU time 1.18 seconds
Started Jun 26 06:28:36 PM PDT 24
Finished Jun 26 06:28:42 PM PDT 24
Peak memory 219940 kb
Host smart-4adc5552-b2e0-47cf-adb9-656e7be67452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135843352 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.135843352
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.3877199709
Short name T579
Test name
Test status
Simulation time 24360795 ps
CPU time 0.98 seconds
Started Jun 26 06:28:30 PM PDT 24
Finished Jun 26 06:28:33 PM PDT 24
Peak memory 220176 kb
Host smart-a9f4abc6-0d65-43cd-a356-eca42a102ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877199709 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3877199709
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2245829070
Short name T720
Test name
Test status
Simulation time 45676660 ps
CPU time 1.17 seconds
Started Jun 26 06:28:36 PM PDT 24
Finished Jun 26 06:28:42 PM PDT 24
Peak memory 215616 kb
Host smart-42eeaf17-39ab-4dd8-91c0-7b70def22f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245829070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2245829070
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%