Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.73 98.25 93.97 97.02 92.44 96.37 99.77 92.28


Total test records in report: 1129
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T274 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3053788324 Jun 27 06:26:20 PM PDT 24 Jun 27 06:26:27 PM PDT 24 35413300 ps
T307 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3319498429 Jun 27 06:26:15 PM PDT 24 Jun 27 06:26:20 PM PDT 24 174058721 ps
T1017 /workspace/coverage/cover_reg_top/4.edn_csr_rw.777969317 Jun 27 06:26:07 PM PDT 24 Jun 27 06:26:13 PM PDT 24 14410483 ps
T1018 /workspace/coverage/cover_reg_top/41.edn_intr_test.1627587416 Jun 27 06:26:18 PM PDT 24 Jun 27 06:26:22 PM PDT 24 13107074 ps
T1019 /workspace/coverage/cover_reg_top/8.edn_csr_rw.2331263140 Jun 27 06:26:05 PM PDT 24 Jun 27 06:26:11 PM PDT 24 50539844 ps
T1020 /workspace/coverage/cover_reg_top/16.edn_intr_test.524354812 Jun 27 06:26:21 PM PDT 24 Jun 27 06:26:28 PM PDT 24 16385510 ps
T275 /workspace/coverage/cover_reg_top/9.edn_csr_rw.901224175 Jun 27 06:26:18 PM PDT 24 Jun 27 06:26:22 PM PDT 24 38026060 ps
T1021 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2838827313 Jun 27 06:26:19 PM PDT 24 Jun 27 06:26:24 PM PDT 24 778006049 ps
T289 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1728598817 Jun 27 06:26:19 PM PDT 24 Jun 27 06:26:24 PM PDT 24 74967711 ps
T276 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1017219436 Jun 27 06:26:04 PM PDT 24 Jun 27 06:26:11 PM PDT 24 23268517 ps
T1022 /workspace/coverage/cover_reg_top/15.edn_intr_test.3496675550 Jun 27 06:26:22 PM PDT 24 Jun 27 06:26:31 PM PDT 24 12788419 ps
T308 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.519444529 Jun 27 06:26:22 PM PDT 24 Jun 27 06:26:32 PM PDT 24 95232062 ps
T1023 /workspace/coverage/cover_reg_top/37.edn_intr_test.3716729211 Jun 27 06:26:21 PM PDT 24 Jun 27 06:26:28 PM PDT 24 41947118 ps
T290 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2202548976 Jun 27 06:26:19 PM PDT 24 Jun 27 06:26:23 PM PDT 24 19390494 ps
T1024 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.4026475129 Jun 27 06:26:04 PM PDT 24 Jun 27 06:26:11 PM PDT 24 100372045 ps
T1025 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1036904716 Jun 27 06:26:09 PM PDT 24 Jun 27 06:26:15 PM PDT 24 15272182 ps
T277 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3409814359 Jun 27 06:26:19 PM PDT 24 Jun 27 06:26:25 PM PDT 24 17130363 ps
T310 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3073814973 Jun 27 06:26:00 PM PDT 24 Jun 27 06:26:08 PM PDT 24 93650749 ps
T1026 /workspace/coverage/cover_reg_top/26.edn_intr_test.109172764 Jun 27 06:26:20 PM PDT 24 Jun 27 06:26:27 PM PDT 24 20722649 ps
T1027 /workspace/coverage/cover_reg_top/14.edn_intr_test.2936905726 Jun 27 06:26:13 PM PDT 24 Jun 27 06:26:18 PM PDT 24 38353357 ps
T1028 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2360756536 Jun 27 06:26:23 PM PDT 24 Jun 27 06:26:32 PM PDT 24 64923941 ps
T1029 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.551260701 Jun 27 06:26:10 PM PDT 24 Jun 27 06:26:18 PM PDT 24 506906232 ps
T1030 /workspace/coverage/cover_reg_top/34.edn_intr_test.649718803 Jun 27 06:26:22 PM PDT 24 Jun 27 06:26:29 PM PDT 24 40274334 ps
T1031 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2621177258 Jun 27 06:26:15 PM PDT 24 Jun 27 06:26:19 PM PDT 24 13027206 ps
T311 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4270146531 Jun 27 06:26:23 PM PDT 24 Jun 27 06:26:33 PM PDT 24 166370276 ps
T1032 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3908461580 Jun 27 06:26:07 PM PDT 24 Jun 27 06:26:14 PM PDT 24 79742788 ps
T1033 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1054862926 Jun 27 06:26:00 PM PDT 24 Jun 27 06:26:06 PM PDT 24 67159582 ps
T1034 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3591151743 Jun 27 06:26:07 PM PDT 24 Jun 27 06:26:15 PM PDT 24 126326675 ps
T309 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3197688056 Jun 27 06:26:16 PM PDT 24 Jun 27 06:26:22 PM PDT 24 477743904 ps
T1035 /workspace/coverage/cover_reg_top/10.edn_intr_test.1091133890 Jun 27 06:26:14 PM PDT 24 Jun 27 06:26:18 PM PDT 24 28814296 ps
T1036 /workspace/coverage/cover_reg_top/23.edn_intr_test.3693912014 Jun 27 06:26:23 PM PDT 24 Jun 27 06:26:32 PM PDT 24 48695197 ps
T1037 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2905130105 Jun 27 06:26:08 PM PDT 24 Jun 27 06:26:15 PM PDT 24 93257703 ps
T1038 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1985877497 Jun 27 06:26:04 PM PDT 24 Jun 27 06:26:11 PM PDT 24 19569508 ps
T1039 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2536720107 Jun 27 06:26:04 PM PDT 24 Jun 27 06:26:11 PM PDT 24 84250398 ps
T1040 /workspace/coverage/cover_reg_top/29.edn_intr_test.2876319522 Jun 27 06:26:18 PM PDT 24 Jun 27 06:26:22 PM PDT 24 14276121 ps
T1041 /workspace/coverage/cover_reg_top/0.edn_intr_test.1965018670 Jun 27 06:25:50 PM PDT 24 Jun 27 06:25:55 PM PDT 24 11737149 ps
T1042 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4100939595 Jun 27 06:26:22 PM PDT 24 Jun 27 06:26:31 PM PDT 24 339637772 ps
T1043 /workspace/coverage/cover_reg_top/40.edn_intr_test.3943259651 Jun 27 06:26:22 PM PDT 24 Jun 27 06:26:30 PM PDT 24 38264886 ps
T1044 /workspace/coverage/cover_reg_top/17.edn_intr_test.3376884763 Jun 27 06:26:20 PM PDT 24 Jun 27 06:26:27 PM PDT 24 14548898 ps
T1045 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2789566292 Jun 27 06:26:19 PM PDT 24 Jun 27 06:26:25 PM PDT 24 19696088 ps
T1046 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3522073000 Jun 27 06:26:07 PM PDT 24 Jun 27 06:26:16 PM PDT 24 87472472 ps
T1047 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3884927526 Jun 27 06:26:14 PM PDT 24 Jun 27 06:26:18 PM PDT 24 17361804 ps
T1048 /workspace/coverage/cover_reg_top/49.edn_intr_test.3108034170 Jun 27 06:26:20 PM PDT 24 Jun 27 06:26:27 PM PDT 24 13722879 ps
T1049 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1315099973 Jun 27 06:25:48 PM PDT 24 Jun 27 06:25:53 PM PDT 24 580483626 ps
T1050 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3209336309 Jun 27 06:26:20 PM PDT 24 Jun 27 06:26:27 PM PDT 24 22292483 ps
T1051 /workspace/coverage/cover_reg_top/4.edn_intr_test.1732832581 Jun 27 06:26:01 PM PDT 24 Jun 27 06:26:07 PM PDT 24 21444755 ps
T1052 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3523569582 Jun 27 06:25:59 PM PDT 24 Jun 27 06:26:06 PM PDT 24 22134938 ps
T1053 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3849808347 Jun 27 06:25:51 PM PDT 24 Jun 27 06:25:57 PM PDT 24 22769373 ps
T1054 /workspace/coverage/cover_reg_top/19.edn_intr_test.2483297257 Jun 27 06:26:16 PM PDT 24 Jun 27 06:26:20 PM PDT 24 26705563 ps
T1055 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4079801754 Jun 27 06:26:14 PM PDT 24 Jun 27 06:26:19 PM PDT 24 48721030 ps
T1056 /workspace/coverage/cover_reg_top/4.edn_tl_errors.525434449 Jun 27 06:26:05 PM PDT 24 Jun 27 06:26:13 PM PDT 24 50590501 ps
T1057 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3252967777 Jun 27 06:26:07 PM PDT 24 Jun 27 06:26:14 PM PDT 24 66062623 ps
T1058 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.4160901735 Jun 27 06:26:06 PM PDT 24 Jun 27 06:26:12 PM PDT 24 126755724 ps
T1059 /workspace/coverage/cover_reg_top/46.edn_intr_test.1975835044 Jun 27 06:26:20 PM PDT 24 Jun 27 06:26:25 PM PDT 24 31537092 ps
T1060 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3691994517 Jun 27 06:26:16 PM PDT 24 Jun 27 06:26:20 PM PDT 24 45459342 ps
T1061 /workspace/coverage/cover_reg_top/43.edn_intr_test.2483600623 Jun 27 06:26:21 PM PDT 24 Jun 27 06:26:28 PM PDT 24 14555493 ps
T1062 /workspace/coverage/cover_reg_top/13.edn_intr_test.3824358046 Jun 27 06:26:13 PM PDT 24 Jun 27 06:26:18 PM PDT 24 13926934 ps
T1063 /workspace/coverage/cover_reg_top/12.edn_intr_test.2771387540 Jun 27 06:26:06 PM PDT 24 Jun 27 06:26:13 PM PDT 24 17740503 ps
T1064 /workspace/coverage/cover_reg_top/5.edn_intr_test.974325160 Jun 27 06:26:07 PM PDT 24 Jun 27 06:26:13 PM PDT 24 28338240 ps
T1065 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1351898955 Jun 27 06:26:18 PM PDT 24 Jun 27 06:26:24 PM PDT 24 97401000 ps
T1066 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1179002103 Jun 27 06:26:15 PM PDT 24 Jun 27 06:26:20 PM PDT 24 49635228 ps
T278 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3871521900 Jun 27 06:26:14 PM PDT 24 Jun 27 06:26:18 PM PDT 24 43244257 ps
T279 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2280887055 Jun 27 06:25:53 PM PDT 24 Jun 27 06:26:00 PM PDT 24 28992206 ps
T1067 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2098087795 Jun 27 06:26:14 PM PDT 24 Jun 27 06:26:19 PM PDT 24 117024281 ps
T1068 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2515275294 Jun 27 06:26:09 PM PDT 24 Jun 27 06:26:18 PM PDT 24 119390323 ps
T1069 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3773120105 Jun 27 06:26:05 PM PDT 24 Jun 27 06:26:13 PM PDT 24 334285979 ps
T1070 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3860820634 Jun 27 06:26:03 PM PDT 24 Jun 27 06:26:10 PM PDT 24 17886447 ps
T1071 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1644452133 Jun 27 06:26:19 PM PDT 24 Jun 27 06:26:24 PM PDT 24 32622348 ps
T280 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1381695204 Jun 27 06:26:23 PM PDT 24 Jun 27 06:26:31 PM PDT 24 69447114 ps
T1072 /workspace/coverage/cover_reg_top/31.edn_intr_test.3673545923 Jun 27 06:26:27 PM PDT 24 Jun 27 06:26:34 PM PDT 24 49413646 ps
T1073 /workspace/coverage/cover_reg_top/25.edn_intr_test.972120197 Jun 27 06:26:19 PM PDT 24 Jun 27 06:26:25 PM PDT 24 46471832 ps
T1074 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.657137945 Jun 27 06:26:14 PM PDT 24 Jun 27 06:26:20 PM PDT 24 207593998 ps
T1075 /workspace/coverage/cover_reg_top/38.edn_intr_test.3013545465 Jun 27 06:26:23 PM PDT 24 Jun 27 06:26:31 PM PDT 24 37278159 ps
T281 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3109509668 Jun 27 06:25:53 PM PDT 24 Jun 27 06:26:00 PM PDT 24 128335879 ps
T1076 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3963493470 Jun 27 06:26:18 PM PDT 24 Jun 27 06:26:23 PM PDT 24 34954950 ps
T1077 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1636305608 Jun 27 06:25:49 PM PDT 24 Jun 27 06:25:54 PM PDT 24 49872219 ps
T1078 /workspace/coverage/cover_reg_top/47.edn_intr_test.640090635 Jun 27 06:26:29 PM PDT 24 Jun 27 06:26:35 PM PDT 24 95601654 ps
T1079 /workspace/coverage/cover_reg_top/3.edn_intr_test.3857505935 Jun 27 06:26:04 PM PDT 24 Jun 27 06:26:11 PM PDT 24 103565413 ps
T1080 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2857542892 Jun 27 06:26:15 PM PDT 24 Jun 27 06:26:19 PM PDT 24 98167206 ps
T1081 /workspace/coverage/cover_reg_top/1.edn_intr_test.36106758 Jun 27 06:26:02 PM PDT 24 Jun 27 06:26:08 PM PDT 24 20517377 ps
T1082 /workspace/coverage/cover_reg_top/22.edn_intr_test.1067304407 Jun 27 06:26:21 PM PDT 24 Jun 27 06:26:28 PM PDT 24 14313714 ps
T1083 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3919505091 Jun 27 06:26:20 PM PDT 24 Jun 27 06:26:26 PM PDT 24 75353122 ps
T1084 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1772115593 Jun 27 06:25:53 PM PDT 24 Jun 27 06:26:02 PM PDT 24 181968660 ps
T1085 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.957540551 Jun 27 06:25:54 PM PDT 24 Jun 27 06:26:01 PM PDT 24 41364405 ps
T1086 /workspace/coverage/cover_reg_top/18.edn_csr_rw.436639972 Jun 27 06:26:27 PM PDT 24 Jun 27 06:26:34 PM PDT 24 17930006 ps
T1087 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4195719191 Jun 27 06:26:19 PM PDT 24 Jun 27 06:26:26 PM PDT 24 161914277 ps
T1088 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2318742448 Jun 27 06:26:23 PM PDT 24 Jun 27 06:26:32 PM PDT 24 21051973 ps
T1089 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3038542164 Jun 27 06:26:10 PM PDT 24 Jun 27 06:26:17 PM PDT 24 155280076 ps
T1090 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.895189558 Jun 27 06:26:20 PM PDT 24 Jun 27 06:26:29 PM PDT 24 154202673 ps
T1091 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1036763064 Jun 27 06:26:21 PM PDT 24 Jun 27 06:26:28 PM PDT 24 11497599 ps
T1092 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4121010897 Jun 27 06:26:13 PM PDT 24 Jun 27 06:26:18 PM PDT 24 62488626 ps
T1093 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2318702640 Jun 27 06:26:14 PM PDT 24 Jun 27 06:26:19 PM PDT 24 23887997 ps
T282 /workspace/coverage/cover_reg_top/0.edn_csr_rw.1358886603 Jun 27 06:26:01 PM PDT 24 Jun 27 06:26:07 PM PDT 24 14976356 ps
T1094 /workspace/coverage/cover_reg_top/19.edn_tl_errors.664191262 Jun 27 06:26:22 PM PDT 24 Jun 27 06:26:31 PM PDT 24 153726821 ps
T1095 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2127048212 Jun 27 06:26:08 PM PDT 24 Jun 27 06:26:14 PM PDT 24 26452869 ps
T1096 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.299296294 Jun 27 06:26:15 PM PDT 24 Jun 27 06:26:20 PM PDT 24 43641041 ps
T1097 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1608412548 Jun 27 06:26:15 PM PDT 24 Jun 27 06:26:19 PM PDT 24 143321354 ps
T1098 /workspace/coverage/cover_reg_top/48.edn_intr_test.3003132843 Jun 27 06:26:22 PM PDT 24 Jun 27 06:26:30 PM PDT 24 24369622 ps
T1099 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3160179100 Jun 27 06:26:07 PM PDT 24 Jun 27 06:26:16 PM PDT 24 130105307 ps
T1100 /workspace/coverage/cover_reg_top/9.edn_tl_errors.938631809 Jun 27 06:26:07 PM PDT 24 Jun 27 06:26:15 PM PDT 24 42425707 ps
T1101 /workspace/coverage/cover_reg_top/8.edn_tl_errors.4289564781 Jun 27 06:26:06 PM PDT 24 Jun 27 06:26:14 PM PDT 24 371309287 ps
T1102 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3847137445 Jun 27 06:26:17 PM PDT 24 Jun 27 06:26:24 PM PDT 24 119802780 ps
T1103 /workspace/coverage/cover_reg_top/20.edn_intr_test.470768290 Jun 27 06:26:23 PM PDT 24 Jun 27 06:26:31 PM PDT 24 15522576 ps
T1104 /workspace/coverage/cover_reg_top/24.edn_intr_test.1655955710 Jun 27 06:26:24 PM PDT 24 Jun 27 06:26:32 PM PDT 24 24852462 ps
T1105 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3557798190 Jun 27 06:26:03 PM PDT 24 Jun 27 06:26:10 PM PDT 24 78028502 ps
T1106 /workspace/coverage/cover_reg_top/16.edn_tl_errors.623219895 Jun 27 06:26:21 PM PDT 24 Jun 27 06:26:29 PM PDT 24 39947310 ps
T1107 /workspace/coverage/cover_reg_top/12.edn_csr_rw.3379219568 Jun 27 06:26:15 PM PDT 24 Jun 27 06:26:19 PM PDT 24 11973760 ps
T1108 /workspace/coverage/cover_reg_top/32.edn_intr_test.3633147655 Jun 27 06:26:22 PM PDT 24 Jun 27 06:26:30 PM PDT 24 43886854 ps
T1109 /workspace/coverage/cover_reg_top/18.edn_intr_test.2033852650 Jun 27 06:26:16 PM PDT 24 Jun 27 06:26:20 PM PDT 24 65039448 ps
T1110 /workspace/coverage/cover_reg_top/5.edn_csr_rw.410646779 Jun 27 06:26:17 PM PDT 24 Jun 27 06:26:21 PM PDT 24 52287161 ps
T1111 /workspace/coverage/cover_reg_top/2.edn_intr_test.1153255689 Jun 27 06:26:03 PM PDT 24 Jun 27 06:26:09 PM PDT 24 17248012 ps
T1112 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1557842831 Jun 27 06:26:22 PM PDT 24 Jun 27 06:26:30 PM PDT 24 204911927 ps
T1113 /workspace/coverage/cover_reg_top/35.edn_intr_test.1948976924 Jun 27 06:26:22 PM PDT 24 Jun 27 06:26:30 PM PDT 24 34278791 ps
T1114 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3186904416 Jun 27 06:26:05 PM PDT 24 Jun 27 06:26:11 PM PDT 24 55205718 ps
T1115 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3947141190 Jun 27 06:26:03 PM PDT 24 Jun 27 06:26:10 PM PDT 24 19595163 ps
T1116 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3989234260 Jun 27 06:26:02 PM PDT 24 Jun 27 06:26:08 PM PDT 24 91548482 ps
T1117 /workspace/coverage/cover_reg_top/27.edn_intr_test.3060681505 Jun 27 06:26:20 PM PDT 24 Jun 27 06:26:27 PM PDT 24 19560236 ps
T1118 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4279877164 Jun 27 06:26:02 PM PDT 24 Jun 27 06:26:08 PM PDT 24 49860370 ps
T1119 /workspace/coverage/cover_reg_top/6.edn_tl_errors.4081607038 Jun 27 06:26:04 PM PDT 24 Jun 27 06:26:13 PM PDT 24 121555252 ps
T1120 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1068870044 Jun 27 06:26:20 PM PDT 24 Jun 27 06:26:28 PM PDT 24 52295958 ps
T1121 /workspace/coverage/cover_reg_top/28.edn_intr_test.4170902893 Jun 27 06:26:20 PM PDT 24 Jun 27 06:26:25 PM PDT 24 22774345 ps
T1122 /workspace/coverage/cover_reg_top/44.edn_intr_test.3824678254 Jun 27 06:26:29 PM PDT 24 Jun 27 06:26:35 PM PDT 24 42905778 ps
T1123 /workspace/coverage/cover_reg_top/39.edn_intr_test.895583390 Jun 27 06:26:20 PM PDT 24 Jun 27 06:26:27 PM PDT 24 20341003 ps
T1124 /workspace/coverage/cover_reg_top/33.edn_intr_test.565435654 Jun 27 06:26:20 PM PDT 24 Jun 27 06:26:27 PM PDT 24 24707094 ps
T1125 /workspace/coverage/cover_reg_top/30.edn_intr_test.1201301155 Jun 27 06:26:22 PM PDT 24 Jun 27 06:26:29 PM PDT 24 43789623 ps
T1126 /workspace/coverage/cover_reg_top/6.edn_intr_test.2480132617 Jun 27 06:26:05 PM PDT 24 Jun 27 06:26:11 PM PDT 24 155316566 ps
T1127 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.222539207 Jun 27 06:26:22 PM PDT 24 Jun 27 06:26:30 PM PDT 24 89597881 ps
T1128 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.655795007 Jun 27 06:26:22 PM PDT 24 Jun 27 06:26:31 PM PDT 24 111547494 ps
T1129 /workspace/coverage/cover_reg_top/3.edn_tl_errors.4268062084 Jun 27 06:26:19 PM PDT 24 Jun 27 06:26:27 PM PDT 24 201505783 ps

Test location /workspace/coverage/default/226.edn_genbits.4119552995
Short name T3
Test name
Test status
Simulation time 49795669 ps
CPU time 1.61 seconds
Started Jun 27 06:33:20 PM PDT 24
Finished Jun 27 06:33:27 PM PDT 24
Peak memory 219772 kb
Host smart-dc338f22-f74e-4d55-ba9a-c2fd7ca4121f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119552995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.4119552995
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2529733357
Short name T31
Test name
Test status
Simulation time 14040920095 ps
CPU time 354.52 seconds
Started Jun 27 06:30:54 PM PDT 24
Finished Jun 27 06:36:57 PM PDT 24
Peak memory 224052 kb
Host smart-1f4a8344-a8d2-408b-81ad-e077fc4fd2c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529733357 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2529733357
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.edn_err.1620120957
Short name T4
Test name
Test status
Simulation time 47463378 ps
CPU time 0.86 seconds
Started Jun 27 06:32:23 PM PDT 24
Finished Jun 27 06:32:32 PM PDT 24
Peak memory 218508 kb
Host smart-5f6152e6-3744-435a-802e-b5f0fb410c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620120957 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1620120957
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/3.edn_sec_cm.4099212301
Short name T16
Test name
Test status
Simulation time 3341341272 ps
CPU time 8.96 seconds
Started Jun 27 06:29:49 PM PDT 24
Finished Jun 27 06:30:05 PM PDT 24
Peak memory 238408 kb
Host smart-4c5c6f61-26c0-456c-9712-9424bf90b39e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099212301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.4099212301
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/141.edn_alert.1831826180
Short name T105
Test name
Test status
Simulation time 23453026 ps
CPU time 1.15 seconds
Started Jun 27 06:32:41 PM PDT 24
Finished Jun 27 06:32:45 PM PDT 24
Peak memory 219656 kb
Host smart-0a9940c9-59c7-4401-a807-9696555f1c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831826180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.1831826180
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/32.edn_disable.537118625
Short name T174
Test name
Test status
Simulation time 17071397 ps
CPU time 0.86 seconds
Started Jun 27 06:31:02 PM PDT 24
Finished Jun 27 06:31:07 PM PDT 24
Peak memory 216560 kb
Host smart-00a10654-f4a7-406d-8f27-354d38bf6257
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537118625 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.537118625
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2547618412
Short name T64
Test name
Test status
Simulation time 81421175 ps
CPU time 1.06 seconds
Started Jun 27 06:31:12 PM PDT 24
Finished Jun 27 06:31:16 PM PDT 24
Peak memory 217280 kb
Host smart-ff194d91-f510-4d84-86cb-7ffccd71e889
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547618412 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2547618412
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/113.edn_alert.807262106
Short name T9
Test name
Test status
Simulation time 56392066 ps
CPU time 1.31 seconds
Started Jun 27 06:32:58 PM PDT 24
Finished Jun 27 06:33:02 PM PDT 24
Peak memory 215996 kb
Host smart-46ae949d-d5b1-40fb-8523-67f0d6121dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807262106 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.807262106
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/78.edn_genbits.1189217252
Short name T19
Test name
Test status
Simulation time 49585759 ps
CPU time 1.62 seconds
Started Jun 27 06:32:17 PM PDT 24
Finished Jun 27 06:32:29 PM PDT 24
Peak memory 220560 kb
Host smart-f31c346a-ea00-4998-9965-dca867e9e43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189217252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1189217252
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3053514379
Short name T97
Test name
Test status
Simulation time 27677133201 ps
CPU time 585.85 seconds
Started Jun 27 06:31:06 PM PDT 24
Finished Jun 27 06:40:55 PM PDT 24
Peak memory 218904 kb
Host smart-d820722c-c015-41c2-b72e-ec8ef7d2053c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053514379 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3053514379
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/178.edn_alert.1718264301
Short name T291
Test name
Test status
Simulation time 29813409 ps
CPU time 1.26 seconds
Started Jun 27 06:33:20 PM PDT 24
Finished Jun 27 06:33:28 PM PDT 24
Peak memory 218820 kb
Host smart-15cd4622-55d2-484f-b316-314fb5e162eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718264301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.1718264301
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/2.edn_regwen.3882837718
Short name T22
Test name
Test status
Simulation time 18448364 ps
CPU time 1 seconds
Started Jun 27 06:29:45 PM PDT 24
Finished Jun 27 06:29:52 PM PDT 24
Peak memory 207396 kb
Host smart-977cd013-97b7-430c-a20a-3d2c7e34a3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882837718 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3882837718
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/121.edn_alert.4231385924
Short name T75
Test name
Test status
Simulation time 88480904 ps
CPU time 1.31 seconds
Started Jun 27 06:32:37 PM PDT 24
Finished Jun 27 06:32:43 PM PDT 24
Peak memory 220584 kb
Host smart-0119991c-c38e-456e-aea7-de1c37c81886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231385924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.4231385924
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/18.edn_disable.957109699
Short name T34
Test name
Test status
Simulation time 17161474 ps
CPU time 0.91 seconds
Started Jun 27 06:30:35 PM PDT 24
Finished Jun 27 06:30:39 PM PDT 24
Peak memory 216500 kb
Host smart-126fd519-689a-4d93-943e-b6b78e5caeeb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957109699 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.957109699
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1320268924
Short name T300
Test name
Test status
Simulation time 231583084 ps
CPU time 2.86 seconds
Started Jun 27 06:25:48 PM PDT 24
Finished Jun 27 06:25:54 PM PDT 24
Peak memory 215048 kb
Host smart-8ccc8654-edf2-4600-8bad-c964edf74b9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320268924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1320268924
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/79.edn_err.4175742296
Short name T14
Test name
Test status
Simulation time 48300897 ps
CPU time 0.91 seconds
Started Jun 27 06:32:16 PM PDT 24
Finished Jun 27 06:32:28 PM PDT 24
Peak memory 229364 kb
Host smart-c0b48d82-484f-4e73-9ae5-a839dae0e911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175742296 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.4175742296
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/50.edn_alert.3316851090
Short name T104
Test name
Test status
Simulation time 66572858 ps
CPU time 1.14 seconds
Started Jun 27 06:32:09 PM PDT 24
Finished Jun 27 06:32:11 PM PDT 24
Peak memory 219336 kb
Host smart-59971f68-828c-428b-b038-04fac315fbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316851090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.3316851090
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable.1343321149
Short name T596
Test name
Test status
Simulation time 21950720 ps
CPU time 0.88 seconds
Started Jun 27 06:29:42 PM PDT 24
Finished Jun 27 06:29:45 PM PDT 24
Peak memory 216516 kb
Host smart-50133667-c185-489e-a0b1-ae4f31b7c5de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343321149 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1343321149
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable.1282845761
Short name T83
Test name
Test status
Simulation time 26108690 ps
CPU time 0.81 seconds
Started Jun 27 06:30:40 PM PDT 24
Finished Jun 27 06:30:43 PM PDT 24
Peak memory 215660 kb
Host smart-c68f3f1c-3f28-4bb0-a202-dfc16ce935be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282845761 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1282845761
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2868899101
Short name T204
Test name
Test status
Simulation time 56091641 ps
CPU time 1.14 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:30:57 PM PDT 24
Peak memory 217264 kb
Host smart-117ad30e-f408-4f72-a190-772da673414a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868899101 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2868899101
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.56503491
Short name T85
Test name
Test status
Simulation time 36922644 ps
CPU time 1.3 seconds
Started Jun 27 06:30:00 PM PDT 24
Finished Jun 27 06:30:06 PM PDT 24
Peak memory 217092 kb
Host smart-8bb99b2e-039f-4e42-a887-29960e3ada25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56503491 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disa
ble_auto_req_mode.56503491
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.228364018
Short name T272
Test name
Test status
Simulation time 68198823 ps
CPU time 1.27 seconds
Started Jun 27 06:25:51 PM PDT 24
Finished Jun 27 06:25:58 PM PDT 24
Peak memory 207208 kb
Host smart-99b8e16a-96c5-4e2f-82c4-8d497e22cf46
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228364018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.228364018
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/default/124.edn_alert.2989539095
Short name T25
Test name
Test status
Simulation time 26347939 ps
CPU time 1.19 seconds
Started Jun 27 06:32:26 PM PDT 24
Finished Jun 27 06:32:35 PM PDT 24
Peak memory 218932 kb
Host smart-d50a42b8-fe88-4425-97dc-ce88823615dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989539095 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.2989539095
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/128.edn_alert.2723709989
Short name T117
Test name
Test status
Simulation time 38787724 ps
CPU time 1.11 seconds
Started Jun 27 06:32:32 PM PDT 24
Finished Jun 27 06:32:38 PM PDT 24
Peak memory 218908 kb
Host smart-314facd7-3006-48d7-a47d-e97eb400a891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723709989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.2723709989
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert.840838119
Short name T148
Test name
Test status
Simulation time 45151851 ps
CPU time 1.19 seconds
Started Jun 27 06:31:03 PM PDT 24
Finished Jun 27 06:31:08 PM PDT 24
Peak memory 219440 kb
Host smart-b294ae7e-6c1b-4b3a-98a4-0aa0ef637b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840838119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.840838119
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3716942472
Short name T67
Test name
Test status
Simulation time 44536114 ps
CPU time 1.32 seconds
Started Jun 27 06:30:17 PM PDT 24
Finished Jun 27 06:30:19 PM PDT 24
Peak memory 218796 kb
Host smart-3e053739-ef58-4c8a-a68d-918666978cc4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716942472 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3716942472
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/225.edn_genbits.3976607995
Short name T332
Test name
Test status
Simulation time 162222568 ps
CPU time 1.97 seconds
Started Jun 27 06:33:20 PM PDT 24
Finished Jun 27 06:33:29 PM PDT 24
Peak memory 220028 kb
Host smart-97af1f01-0578-47f3-8acb-3d956e2baac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976607995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3976607995
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.3151118038
Short name T187
Test name
Test status
Simulation time 37390236 ps
CPU time 1.17 seconds
Started Jun 27 06:32:34 PM PDT 24
Finished Jun 27 06:32:40 PM PDT 24
Peak memory 220300 kb
Host smart-bb2c617b-6c78-4d70-a75a-7e5933a6367f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151118038 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.3151118038
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/137.edn_alert.1804845710
Short name T182
Test name
Test status
Simulation time 23937466 ps
CPU time 1.21 seconds
Started Jun 27 06:32:41 PM PDT 24
Finished Jun 27 06:32:46 PM PDT 24
Peak memory 220320 kb
Host smart-5f74ed3f-42dd-4294-9c20-f82a5590d105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804845710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.1804845710
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert.1134696800
Short name T123
Test name
Test status
Simulation time 70937698 ps
CPU time 1.23 seconds
Started Jun 27 06:31:23 PM PDT 24
Finished Jun 27 06:31:27 PM PDT 24
Peak memory 218992 kb
Host smart-c18dc0ee-99bb-42a1-b41d-ca57c105df2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134696800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1134696800
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/123.edn_alert.1286504563
Short name T258
Test name
Test status
Simulation time 87231825 ps
CPU time 1.12 seconds
Started Jun 27 06:32:31 PM PDT 24
Finished Jun 27 06:32:37 PM PDT 24
Peak memory 218688 kb
Host smart-8172eac4-633d-4c9e-afc8-e6300eec3e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286504563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.1286504563
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/135.edn_alert.456388866
Short name T661
Test name
Test status
Simulation time 53313929 ps
CPU time 1.23 seconds
Started Jun 27 06:32:37 PM PDT 24
Finished Jun 27 06:32:43 PM PDT 24
Peak memory 219960 kb
Host smart-a8c216a7-c1ad-4bc9-a872-091f158584d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456388866 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.456388866
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/147.edn_alert.2314693310
Short name T714
Test name
Test status
Simulation time 59855906 ps
CPU time 1.04 seconds
Started Jun 27 06:33:00 PM PDT 24
Finished Jun 27 06:33:05 PM PDT 24
Peak memory 219884 kb
Host smart-39e6670b-3166-447e-a311-4f1e344038e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314693310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.2314693310
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/30.edn_intr.1375847730
Short name T1
Test name
Test status
Simulation time 28574472 ps
CPU time 0.97 seconds
Started Jun 27 06:30:54 PM PDT 24
Finished Jun 27 06:31:03 PM PDT 24
Peak memory 216196 kb
Host smart-a4d5c9a8-b3c1-4cd6-aea9-f42dcaa1ac9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375847730 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1375847730
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/10.edn_disable.3911012768
Short name T750
Test name
Test status
Simulation time 22437618 ps
CPU time 0.91 seconds
Started Jun 27 06:30:07 PM PDT 24
Finished Jun 27 06:30:13 PM PDT 24
Peak memory 216836 kb
Host smart-af0a26fb-4a1c-4e9f-ae56-acfbbe1871d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911012768 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3911012768
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/21.edn_intr.3847332397
Short name T90
Test name
Test status
Simulation time 26563330 ps
CPU time 0.89 seconds
Started Jun 27 06:30:40 PM PDT 24
Finished Jun 27 06:30:43 PM PDT 24
Peak memory 215840 kb
Host smart-f21dcb39-81c1-42cd-92ed-559eb826b2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847332397 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3847332397
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/1.edn_alert.1210316503
Short name T168
Test name
Test status
Simulation time 67508734 ps
CPU time 1.05 seconds
Started Jun 27 06:29:45 PM PDT 24
Finished Jun 27 06:29:51 PM PDT 24
Peak memory 220404 kb
Host smart-34fa2e4e-6c2f-41d1-b5ae-39970c58bcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210316503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1210316503
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/101.edn_alert.711256566
Short name T703
Test name
Test status
Simulation time 28053694 ps
CPU time 1.2 seconds
Started Jun 27 06:32:15 PM PDT 24
Finished Jun 27 06:32:26 PM PDT 24
Peak memory 215988 kb
Host smart-16ab29d4-6c98-4720-b706-7f45862e9174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711256566 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.711256566
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable.3600659873
Short name T153
Test name
Test status
Simulation time 13642860 ps
CPU time 0.95 seconds
Started Jun 27 06:30:08 PM PDT 24
Finished Jun 27 06:30:13 PM PDT 24
Peak memory 215968 kb
Host smart-21bdf3fd-df88-4137-94f0-ad4c8c15a2a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600659873 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3600659873
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable.1675973980
Short name T20
Test name
Test status
Simulation time 45234248 ps
CPU time 0.88 seconds
Started Jun 27 06:30:20 PM PDT 24
Finished Jun 27 06:30:24 PM PDT 24
Peak memory 216508 kb
Host smart-785111af-c51c-46ea-9e65-1c46f4708627
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675973980 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1675973980
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2431758011
Short name T71
Test name
Test status
Simulation time 272231236 ps
CPU time 1.2 seconds
Started Jun 27 06:30:34 PM PDT 24
Finished Jun 27 06:30:37 PM PDT 24
Peak memory 217664 kb
Host smart-22fbb465-5126-467f-ab12-6bc9e95e6c8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431758011 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2431758011
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.285967631
Short name T190
Test name
Test status
Simulation time 26171715 ps
CPU time 1.05 seconds
Started Jun 27 06:30:51 PM PDT 24
Finished Jun 27 06:31:00 PM PDT 24
Peak memory 224212 kb
Host smart-be9b60cd-3c06-4778-acce-6ba9935b12c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285967631 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.285967631
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/39.edn_disable.1010046728
Short name T209
Test name
Test status
Simulation time 12786296 ps
CPU time 0.9 seconds
Started Jun 27 06:31:25 PM PDT 24
Finished Jun 27 06:31:30 PM PDT 24
Peak memory 216776 kb
Host smart-c878f3d8-a50b-49dc-90ba-330d4362927b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010046728 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1010046728
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable.2788065820
Short name T74
Test name
Test status
Simulation time 12724735 ps
CPU time 0.92 seconds
Started Jun 27 06:31:27 PM PDT 24
Finished Jun 27 06:31:31 PM PDT 24
Peak memory 216720 kb
Host smart-75fc4dc7-8cfd-4b74-82ec-79314469be84
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788065820 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2788065820
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/59.edn_err.399044023
Short name T179
Test name
Test status
Simulation time 19313364 ps
CPU time 1.05 seconds
Started Jun 27 06:32:11 PM PDT 24
Finished Jun 27 06:32:17 PM PDT 24
Peak memory 218704 kb
Host smart-d73d2657-4a13-44c8-80a4-c567bdd7893a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399044023 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.399044023
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/251.edn_genbits.3709058653
Short name T39
Test name
Test status
Simulation time 48554453 ps
CPU time 1.46 seconds
Started Jun 27 06:33:36 PM PDT 24
Finished Jun 27 06:33:40 PM PDT 24
Peak memory 219356 kb
Host smart-a8c5f958-1c5a-473f-8c38-b04a59d10cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709058653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3709058653
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.3770812007
Short name T318
Test name
Test status
Simulation time 101606641 ps
CPU time 1.23 seconds
Started Jun 27 06:32:42 PM PDT 24
Finished Jun 27 06:32:46 PM PDT 24
Peak memory 219632 kb
Host smart-38fd9638-83e2-491b-a65f-06c3fe146173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770812007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3770812007
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2513120052
Short name T347
Test name
Test status
Simulation time 69282200 ps
CPU time 2.5 seconds
Started Jun 27 06:33:33 PM PDT 24
Finished Jun 27 06:33:38 PM PDT 24
Peak memory 219156 kb
Host smart-53996843-b45e-41f6-a0c9-f50cd89f4ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513120052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2513120052
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.2076156514
Short name T191
Test name
Test status
Simulation time 91583132 ps
CPU time 1.24 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:23 PM PDT 24
Peak memory 219852 kb
Host smart-3703018e-1851-4d9e-b15b-a9d2aacf394d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076156514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.2076156514
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1594079127
Short name T68
Test name
Test status
Simulation time 21629963 ps
CPU time 0.92 seconds
Started Jun 27 06:30:40 PM PDT 24
Finished Jun 27 06:30:44 PM PDT 24
Peak memory 206984 kb
Host smart-8c21243d-0300-4f0f-9138-fa2e5cc7301b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594079127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1594079127
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1179490258
Short name T225
Test name
Test status
Simulation time 23892679442 ps
CPU time 557.29 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:40:12 PM PDT 24
Peak memory 220624 kb
Host smart-5656a5bb-d896-4671-8f50-c9098b9cc10e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179490258 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1179490258
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.edn_genbits.524879027
Short name T52
Test name
Test status
Simulation time 40818742 ps
CPU time 1.4 seconds
Started Jun 27 06:32:08 PM PDT 24
Finished Jun 27 06:32:10 PM PDT 24
Peak memory 217480 kb
Host smart-987b3d2e-7373-4559-8b66-7e07d1b85ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524879027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.524879027
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.730580502
Short name T28
Test name
Test status
Simulation time 24673369 ps
CPU time 1 seconds
Started Jun 27 06:31:04 PM PDT 24
Finished Jun 27 06:31:09 PM PDT 24
Peak memory 216464 kb
Host smart-3cb415da-fe2d-448a-8e6d-bcdaf243597b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730580502 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.730580502
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/139.edn_genbits.2900251551
Short name T35
Test name
Test status
Simulation time 55742828 ps
CPU time 1.37 seconds
Started Jun 27 06:32:39 PM PDT 24
Finished Jun 27 06:32:45 PM PDT 24
Peak memory 218972 kb
Host smart-1e5a7d4d-17ed-4cb7-98a8-e7e0b1b58a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900251551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2900251551
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3623544199
Short name T287
Test name
Test status
Simulation time 43907126 ps
CPU time 1.12 seconds
Started Jun 27 06:26:02 PM PDT 24
Finished Jun 27 06:26:08 PM PDT 24
Peak memory 206964 kb
Host smart-90e4ea36-59c1-4593-82ff-be67d9ac1462
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623544199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3623544199
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1608412548
Short name T1097
Test name
Test status
Simulation time 143321354 ps
CPU time 1.44 seconds
Started Jun 27 06:26:15 PM PDT 24
Finished Jun 27 06:26:19 PM PDT 24
Peak memory 206932 kb
Host smart-b8b11c21-6e07-4a86-a470-537ef3b4f3b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608412548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1608412548
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_regwen.602328556
Short name T838
Test name
Test status
Simulation time 82222475 ps
CPU time 0.89 seconds
Started Jun 27 06:29:47 PM PDT 24
Finished Jun 27 06:29:54 PM PDT 24
Peak memory 207324 kb
Host smart-398f6ee5-762b-48fc-b28c-828f9244d775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602328556 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.602328556
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/100.edn_genbits.4258344769
Short name T945
Test name
Test status
Simulation time 61881442 ps
CPU time 1 seconds
Started Jun 27 06:32:16 PM PDT 24
Finished Jun 27 06:32:28 PM PDT 24
Peak memory 217684 kb
Host smart-3988046c-bb63-4df3-9c3b-d48d3d9e92a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258344769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.4258344769
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.3686095363
Short name T150
Test name
Test status
Simulation time 246538695 ps
CPU time 1.32 seconds
Started Jun 27 06:32:35 PM PDT 24
Finished Jun 27 06:32:41 PM PDT 24
Peak memory 218820 kb
Host smart-8ddab1a4-1de5-465f-b817-52376d88979b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686095363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.3686095363
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/12.edn_stress_all.3583265997
Short name T323
Test name
Test status
Simulation time 171028225 ps
CPU time 3.83 seconds
Started Jun 27 06:30:04 PM PDT 24
Finished Jun 27 06:30:13 PM PDT 24
Peak memory 217528 kb
Host smart-7a0124c1-9cad-4319-a915-64ae2838ddef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583265997 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3583265997
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/138.edn_genbits.317379209
Short name T805
Test name
Test status
Simulation time 195473455 ps
CPU time 1.11 seconds
Started Jun 27 06:32:37 PM PDT 24
Finished Jun 27 06:32:43 PM PDT 24
Peak memory 217544 kb
Host smart-2dc34aea-94f7-4058-a739-f034c5106a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317379209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.317379209
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1915074037
Short name T305
Test name
Test status
Simulation time 30486178 ps
CPU time 1 seconds
Started Jun 27 06:30:22 PM PDT 24
Finished Jun 27 06:30:26 PM PDT 24
Peak memory 215880 kb
Host smart-db07dd1c-c2b4-4abb-866c-c9f428352853
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915074037 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1915074037
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/199.edn_genbits.3469819099
Short name T96
Test name
Test status
Simulation time 86636965 ps
CPU time 0.99 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:28 PM PDT 24
Peak memory 217668 kb
Host smart-e903643a-a374-4321-9eac-ea5e1f573f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469819099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3469819099
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.601221393
Short name T879
Test name
Test status
Simulation time 47680967 ps
CPU time 1.64 seconds
Started Jun 27 06:33:20 PM PDT 24
Finished Jun 27 06:33:28 PM PDT 24
Peak memory 217640 kb
Host smart-68b1aaca-35a7-42f5-82e7-b036c0972d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601221393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.601221393
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1844853423
Short name T325
Test name
Test status
Simulation time 115990566 ps
CPU time 1.51 seconds
Started Jun 27 06:33:20 PM PDT 24
Finished Jun 27 06:33:28 PM PDT 24
Peak memory 218864 kb
Host smart-1ff3207f-ef9a-4c5d-ad77-e76017809089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844853423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1844853423
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3553328422
Short name T322
Test name
Test status
Simulation time 36181650 ps
CPU time 1.52 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:30 PM PDT 24
Peak memory 218936 kb
Host smart-b665142a-9abd-481e-89fe-bea93d4fc1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553328422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3553328422
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2979461945
Short name T335
Test name
Test status
Simulation time 67441189 ps
CPU time 1.14 seconds
Started Jun 27 06:33:32 PM PDT 24
Finished Jun 27 06:33:35 PM PDT 24
Peak memory 219032 kb
Host smart-b642d451-cf72-4ef9-991c-78ce3b7929ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979461945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2979461945
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/290.edn_genbits.2078541555
Short name T338
Test name
Test status
Simulation time 103512622 ps
CPU time 1.88 seconds
Started Jun 27 06:33:34 PM PDT 24
Finished Jun 27 06:33:38 PM PDT 24
Peak memory 220496 kb
Host smart-85508d3f-559d-4af6-9fa6-56e349ce9caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078541555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2078541555
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.4094222391
Short name T801
Test name
Test status
Simulation time 26408063 ps
CPU time 0.88 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:30:57 PM PDT 24
Peak memory 215940 kb
Host smart-88cc3c81-f6f6-4e88-a155-870a1df02a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094222391 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.4094222391
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/144.edn_alert.1931525060
Short name T848
Test name
Test status
Simulation time 94920487 ps
CPU time 1.24 seconds
Started Jun 27 06:32:39 PM PDT 24
Finished Jun 27 06:32:44 PM PDT 24
Peak memory 219296 kb
Host smart-34d5d0e2-feca-4390-b54d-d4f74f24d007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931525060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.1931525060
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/75.edn_alert.3386137396
Short name T110
Test name
Test status
Simulation time 406872807 ps
CPU time 1.56 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:24 PM PDT 24
Peak memory 218756 kb
Host smart-14a6d58c-cae1-46b4-bf7d-2c39fd1d50f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386137396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.3386137396
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.1228588844
Short name T473
Test name
Test status
Simulation time 124016942 ps
CPU time 1.61 seconds
Started Jun 27 06:32:22 PM PDT 24
Finished Jun 27 06:32:32 PM PDT 24
Peak memory 217684 kb
Host smart-70391a29-b731-40a9-b7da-7223289931b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228588844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1228588844
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_err.48575923
Short name T49
Test name
Test status
Simulation time 33431246 ps
CPU time 1.23 seconds
Started Jun 27 06:30:35 PM PDT 24
Finished Jun 27 06:30:38 PM PDT 24
Peak memory 224324 kb
Host smart-908ade13-c127-4900-912c-5c14fd91648e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48575923 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.48575923
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1315099973
Short name T1049
Test name
Test status
Simulation time 580483626 ps
CPU time 3.22 seconds
Started Jun 27 06:25:48 PM PDT 24
Finished Jun 27 06:25:53 PM PDT 24
Peak memory 206888 kb
Host smart-75409736-a6b7-40e6-b9f2-7df1edb9b755
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315099973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1315099973
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3109509668
Short name T281
Test name
Test status
Simulation time 128335879 ps
CPU time 0.96 seconds
Started Jun 27 06:25:53 PM PDT 24
Finished Jun 27 06:26:00 PM PDT 24
Peak memory 206908 kb
Host smart-6561bb51-c6fc-45e4-ae47-ae1977099ece
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109509668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3109509668
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3363385275
Short name T1000
Test name
Test status
Simulation time 152031215 ps
CPU time 1.13 seconds
Started Jun 27 06:25:51 PM PDT 24
Finished Jun 27 06:25:57 PM PDT 24
Peak memory 215148 kb
Host smart-436d115d-0c5b-47be-b8bd-6e89a30f34f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363385275 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3363385275
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1358886603
Short name T282
Test name
Test status
Simulation time 14976356 ps
CPU time 0.92 seconds
Started Jun 27 06:26:01 PM PDT 24
Finished Jun 27 06:26:07 PM PDT 24
Peak memory 206928 kb
Host smart-c3295de9-9383-47f4-960d-2df681639cff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358886603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1358886603
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1965018670
Short name T1041
Test name
Test status
Simulation time 11737149 ps
CPU time 0.86 seconds
Started Jun 27 06:25:50 PM PDT 24
Finished Jun 27 06:25:55 PM PDT 24
Peak memory 206908 kb
Host smart-63052d5f-a59e-41e0-ac53-9bdf49622e2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965018670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1965018670
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.957540551
Short name T1085
Test name
Test status
Simulation time 41364405 ps
CPU time 1.13 seconds
Started Jun 27 06:25:54 PM PDT 24
Finished Jun 27 06:26:01 PM PDT 24
Peak memory 207016 kb
Host smart-d761d2c0-218b-4222-b0c7-79aa153b75fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957540551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.957540551
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3849808347
Short name T1053
Test name
Test status
Simulation time 22769373 ps
CPU time 1.65 seconds
Started Jun 27 06:25:51 PM PDT 24
Finished Jun 27 06:25:57 PM PDT 24
Peak memory 215380 kb
Host smart-f7ddd039-cedb-4e8e-9106-330af42b554c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849808347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3849808347
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3073814973
Short name T310
Test name
Test status
Simulation time 93650749 ps
CPU time 2.76 seconds
Started Jun 27 06:26:00 PM PDT 24
Finished Jun 27 06:26:08 PM PDT 24
Peak memory 207160 kb
Host smart-2da34e75-0b1f-456b-b27c-68e049370b98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073814973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3073814973
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1754928821
Short name T1005
Test name
Test status
Simulation time 21505460 ps
CPU time 1.15 seconds
Started Jun 27 06:25:53 PM PDT 24
Finished Jun 27 06:26:00 PM PDT 24
Peak memory 206912 kb
Host smart-55a84edc-dc44-4dec-9107-90839839bcfa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754928821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1754928821
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1772115593
Short name T1084
Test name
Test status
Simulation time 181968660 ps
CPU time 2.86 seconds
Started Jun 27 06:25:53 PM PDT 24
Finished Jun 27 06:26:02 PM PDT 24
Peak memory 206912 kb
Host smart-4a8dc684-7572-4915-9ae8-e9da43d9bae0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772115593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1772115593
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1636305608
Short name T1077
Test name
Test status
Simulation time 49872219 ps
CPU time 0.94 seconds
Started Jun 27 06:25:49 PM PDT 24
Finished Jun 27 06:25:54 PM PDT 24
Peak memory 207156 kb
Host smart-a249ecaf-48ec-4511-99ff-e606c58afab1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636305608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1636305608
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2536720107
Short name T1039
Test name
Test status
Simulation time 84250398 ps
CPU time 1.49 seconds
Started Jun 27 06:26:04 PM PDT 24
Finished Jun 27 06:26:11 PM PDT 24
Peak memory 215260 kb
Host smart-d861ff84-f901-4236-ba4a-ee1f371076b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536720107 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2536720107
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2280887055
Short name T279
Test name
Test status
Simulation time 28992206 ps
CPU time 0.76 seconds
Started Jun 27 06:25:53 PM PDT 24
Finished Jun 27 06:26:00 PM PDT 24
Peak memory 206740 kb
Host smart-90cda4e9-c2b9-4230-af7b-a3c5d8abbfc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280887055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2280887055
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.36106758
Short name T1081
Test name
Test status
Simulation time 20517377 ps
CPU time 0.82 seconds
Started Jun 27 06:26:02 PM PDT 24
Finished Jun 27 06:26:08 PM PDT 24
Peak memory 206668 kb
Host smart-62d70561-3621-4359-8109-df8a62a2a19e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36106758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.36106758
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3523569582
Short name T1052
Test name
Test status
Simulation time 22134938 ps
CPU time 1.66 seconds
Started Jun 27 06:25:59 PM PDT 24
Finished Jun 27 06:26:06 PM PDT 24
Peak memory 215184 kb
Host smart-76914b6b-b656-41f2-bcea-0c292f4b98cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523569582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3523569582
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3498565003
Short name T998
Test name
Test status
Simulation time 103407097 ps
CPU time 1.42 seconds
Started Jun 27 06:26:05 PM PDT 24
Finished Jun 27 06:26:12 PM PDT 24
Peak memory 215248 kb
Host smart-ac862545-de99-450f-9f10-03f56f90bdbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498565003 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3498565003
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2621177258
Short name T1031
Test name
Test status
Simulation time 13027206 ps
CPU time 0.89 seconds
Started Jun 27 06:26:15 PM PDT 24
Finished Jun 27 06:26:19 PM PDT 24
Peak memory 206944 kb
Host smart-a4c56045-b215-4bcb-b752-43794e54c52a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621177258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2621177258
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1091133890
Short name T1035
Test name
Test status
Simulation time 28814296 ps
CPU time 0.75 seconds
Started Jun 27 06:26:14 PM PDT 24
Finished Jun 27 06:26:18 PM PDT 24
Peak memory 206704 kb
Host smart-ef63e53c-490e-4d29-be3c-106b4026c397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091133890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1091133890
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2857542892
Short name T1080
Test name
Test status
Simulation time 98167206 ps
CPU time 1.09 seconds
Started Jun 27 06:26:15 PM PDT 24
Finished Jun 27 06:26:19 PM PDT 24
Peak memory 206940 kb
Host smart-ac17583a-7e54-4f34-b68b-0acea6899716
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857542892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2857542892
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2622488616
Short name T1003
Test name
Test status
Simulation time 62573018 ps
CPU time 1.3 seconds
Started Jun 27 06:26:19 PM PDT 24
Finished Jun 27 06:26:24 PM PDT 24
Peak memory 215280 kb
Host smart-c93c9a4c-a061-4d35-902b-5e2cfee6b0b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622488616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2622488616
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.900046116
Short name T1011
Test name
Test status
Simulation time 29974750 ps
CPU time 1.11 seconds
Started Jun 27 06:26:02 PM PDT 24
Finished Jun 27 06:26:08 PM PDT 24
Peak memory 216892 kb
Host smart-8fbbf61a-eb79-49de-8231-dfb504b8f45f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900046116 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.900046116
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2202548976
Short name T290
Test name
Test status
Simulation time 19390494 ps
CPU time 0.83 seconds
Started Jun 27 06:26:19 PM PDT 24
Finished Jun 27 06:26:23 PM PDT 24
Peak memory 206700 kb
Host smart-59e78ffa-5875-4e1e-a97f-43716cebbe81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202548976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2202548976
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1698524701
Short name T996
Test name
Test status
Simulation time 17118805 ps
CPU time 0.89 seconds
Started Jun 27 06:26:02 PM PDT 24
Finished Jun 27 06:26:08 PM PDT 24
Peak memory 206784 kb
Host smart-9496792a-e3c3-4867-a404-5384ef86e309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698524701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1698524701
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.4026475129
Short name T1024
Test name
Test status
Simulation time 100372045 ps
CPU time 1.32 seconds
Started Jun 27 06:26:04 PM PDT 24
Finished Jun 27 06:26:11 PM PDT 24
Peak memory 206892 kb
Host smart-df5334d8-9e19-4ace-8fa8-7aa053146497
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026475129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.4026475129
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2515275294
Short name T1068
Test name
Test status
Simulation time 119390323 ps
CPU time 4.12 seconds
Started Jun 27 06:26:09 PM PDT 24
Finished Jun 27 06:26:18 PM PDT 24
Peak memory 215196 kb
Host smart-5a653235-76df-4448-8955-badf98a931e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515275294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2515275294
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3754484405
Short name T299
Test name
Test status
Simulation time 107665346 ps
CPU time 2.26 seconds
Started Jun 27 06:26:08 PM PDT 24
Finished Jun 27 06:26:15 PM PDT 24
Peak memory 206932 kb
Host smart-8bae1173-5c0b-4532-b05e-4df62a461590
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754484405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3754484405
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2098087795
Short name T1067
Test name
Test status
Simulation time 117024281 ps
CPU time 1.37 seconds
Started Jun 27 06:26:14 PM PDT 24
Finished Jun 27 06:26:19 PM PDT 24
Peak memory 215276 kb
Host smart-3e0bdf5d-0472-41bd-9ca8-115a6e0fd550
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098087795 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2098087795
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3379219568
Short name T1107
Test name
Test status
Simulation time 11973760 ps
CPU time 0.84 seconds
Started Jun 27 06:26:15 PM PDT 24
Finished Jun 27 06:26:19 PM PDT 24
Peak memory 206944 kb
Host smart-4c656eac-5c4e-44d7-81d8-992d829a70fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379219568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3379219568
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2771387540
Short name T1063
Test name
Test status
Simulation time 17740503 ps
CPU time 0.82 seconds
Started Jun 27 06:26:06 PM PDT 24
Finished Jun 27 06:26:13 PM PDT 24
Peak memory 206640 kb
Host smart-07b54b1d-f178-467e-a5cd-8170e4016d95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771387540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2771387540
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.222539207
Short name T1127
Test name
Test status
Simulation time 89597881 ps
CPU time 0.95 seconds
Started Jun 27 06:26:22 PM PDT 24
Finished Jun 27 06:26:30 PM PDT 24
Peak memory 206952 kb
Host smart-0a579471-3311-40c1-b0da-8f01810cbda9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222539207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.222539207
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3160179100
Short name T1099
Test name
Test status
Simulation time 130105307 ps
CPU time 3.11 seconds
Started Jun 27 06:26:07 PM PDT 24
Finished Jun 27 06:26:16 PM PDT 24
Peak memory 215192 kb
Host smart-7bc05ce9-38f6-4df1-8227-15cf83b6f302
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160179100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3160179100
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1351898955
Short name T1065
Test name
Test status
Simulation time 97401000 ps
CPU time 2.59 seconds
Started Jun 27 06:26:18 PM PDT 24
Finished Jun 27 06:26:24 PM PDT 24
Peak memory 206876 kb
Host smart-2c374de0-5426-463f-aa7e-9c5d938c5076
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351898955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1351898955
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2318702640
Short name T1093
Test name
Test status
Simulation time 23887997 ps
CPU time 1.6 seconds
Started Jun 27 06:26:14 PM PDT 24
Finished Jun 27 06:26:19 PM PDT 24
Peak memory 215256 kb
Host smart-fdb8fc4a-f68b-4534-9349-a11164ac035f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318702640 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2318702640
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1644452133
Short name T1071
Test name
Test status
Simulation time 32622348 ps
CPU time 0.79 seconds
Started Jun 27 06:26:19 PM PDT 24
Finished Jun 27 06:26:24 PM PDT 24
Peak memory 206756 kb
Host smart-34091fe9-5f57-4dbf-b239-41d259995823
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644452133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1644452133
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3824358046
Short name T1062
Test name
Test status
Simulation time 13926934 ps
CPU time 0.89 seconds
Started Jun 27 06:26:13 PM PDT 24
Finished Jun 27 06:26:18 PM PDT 24
Peak memory 206784 kb
Host smart-631df5be-d739-46b9-a13d-f5bdb66e7464
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824358046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3824358046
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1728598817
Short name T289
Test name
Test status
Simulation time 74967711 ps
CPU time 1.03 seconds
Started Jun 27 06:26:19 PM PDT 24
Finished Jun 27 06:26:24 PM PDT 24
Peak memory 206928 kb
Host smart-4bc43a15-075c-4cb0-9669-ad15a1dd2a79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728598817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.1728598817
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2619654590
Short name T1015
Test name
Test status
Simulation time 108267317 ps
CPU time 3.65 seconds
Started Jun 27 06:26:02 PM PDT 24
Finished Jun 27 06:26:11 PM PDT 24
Peak memory 215188 kb
Host smart-f878e240-48d2-429f-9e94-33becc01dca3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619654590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2619654590
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3197688056
Short name T309
Test name
Test status
Simulation time 477743904 ps
CPU time 2.55 seconds
Started Jun 27 06:26:16 PM PDT 24
Finished Jun 27 06:26:22 PM PDT 24
Peak memory 207084 kb
Host smart-db830b40-3383-464e-8855-383593b2904a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197688056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3197688056
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3384941255
Short name T992
Test name
Test status
Simulation time 50900461 ps
CPU time 1.26 seconds
Started Jun 27 06:26:07 PM PDT 24
Finished Jun 27 06:26:14 PM PDT 24
Peak memory 215236 kb
Host smart-2f0ac993-b067-4fcd-802f-02aa2eae8dea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384941255 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3384941255
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.108089015
Short name T1006
Test name
Test status
Simulation time 25560704 ps
CPU time 0.85 seconds
Started Jun 27 06:26:08 PM PDT 24
Finished Jun 27 06:26:14 PM PDT 24
Peak memory 206932 kb
Host smart-1fcfbc6f-197f-4803-8b11-11b19f41e02b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108089015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.108089015
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2936905726
Short name T1027
Test name
Test status
Simulation time 38353357 ps
CPU time 0.79 seconds
Started Jun 27 06:26:13 PM PDT 24
Finished Jun 27 06:26:18 PM PDT 24
Peak memory 206696 kb
Host smart-f4c14121-027e-4540-aabf-8d096f4d879f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936905726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2936905726
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3820401758
Short name T284
Test name
Test status
Simulation time 116971557 ps
CPU time 1.39 seconds
Started Jun 27 06:26:04 PM PDT 24
Finished Jun 27 06:26:11 PM PDT 24
Peak memory 207124 kb
Host smart-b01fac57-49cd-4842-b3c5-7cc02dc619dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820401758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3820401758
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1068870044
Short name T1120
Test name
Test status
Simulation time 52295958 ps
CPU time 3.33 seconds
Started Jun 27 06:26:20 PM PDT 24
Finished Jun 27 06:26:28 PM PDT 24
Peak memory 215192 kb
Host smart-90a7887c-53ec-4a40-a4f7-1653bb273137
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068870044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1068870044
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3038542164
Short name T1089
Test name
Test status
Simulation time 155280076 ps
CPU time 2.44 seconds
Started Jun 27 06:26:10 PM PDT 24
Finished Jun 27 06:26:17 PM PDT 24
Peak memory 206932 kb
Host smart-644bc776-b678-4a03-8a9d-8cfa733849f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038542164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3038542164
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2360756536
Short name T1028
Test name
Test status
Simulation time 64923941 ps
CPU time 1.23 seconds
Started Jun 27 06:26:23 PM PDT 24
Finished Jun 27 06:26:32 PM PDT 24
Peak memory 219424 kb
Host smart-53139e9b-5ff9-4d76-b9c1-e0ae968c00ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360756536 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2360756536
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1381695204
Short name T280
Test name
Test status
Simulation time 69447114 ps
CPU time 0.92 seconds
Started Jun 27 06:26:23 PM PDT 24
Finished Jun 27 06:26:31 PM PDT 24
Peak memory 206932 kb
Host smart-35319e0e-5eca-41f5-9c1b-43c20e4dc70c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381695204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1381695204
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3496675550
Short name T1022
Test name
Test status
Simulation time 12788419 ps
CPU time 0.88 seconds
Started Jun 27 06:26:22 PM PDT 24
Finished Jun 27 06:26:31 PM PDT 24
Peak memory 206828 kb
Host smart-a745a79a-e4bb-4292-b119-ba17675e813e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496675550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3496675550
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3437093948
Short name T288
Test name
Test status
Simulation time 24097881 ps
CPU time 1.13 seconds
Started Jun 27 06:26:21 PM PDT 24
Finished Jun 27 06:26:28 PM PDT 24
Peak memory 206968 kb
Host smart-0f5d9328-6839-402f-8b81-052d1a57f1e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437093948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3437093948
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3584950152
Short name T1007
Test name
Test status
Simulation time 84282355 ps
CPU time 1.74 seconds
Started Jun 27 06:26:21 PM PDT 24
Finished Jun 27 06:26:28 PM PDT 24
Peak memory 215244 kb
Host smart-707e3073-35e3-4b46-992f-045f532eeeae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584950152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3584950152
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.519444529
Short name T308
Test name
Test status
Simulation time 95232062 ps
CPU time 2.37 seconds
Started Jun 27 06:26:22 PM PDT 24
Finished Jun 27 06:26:32 PM PDT 24
Peak memory 206924 kb
Host smart-83345b1b-d762-4881-bb9f-5541518cd276
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519444529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.519444529
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4195719191
Short name T1087
Test name
Test status
Simulation time 161914277 ps
CPU time 1.78 seconds
Started Jun 27 06:26:19 PM PDT 24
Finished Jun 27 06:26:26 PM PDT 24
Peak memory 215192 kb
Host smart-3060cd53-020e-46ec-9646-fd4f3e12396b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195719191 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.4195719191
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1036763064
Short name T1091
Test name
Test status
Simulation time 11497599 ps
CPU time 0.9 seconds
Started Jun 27 06:26:21 PM PDT 24
Finished Jun 27 06:26:28 PM PDT 24
Peak memory 206912 kb
Host smart-ef84f1fc-fbc0-4a59-8dd1-006fb8cbbdd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036763064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1036763064
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.524354812
Short name T1020
Test name
Test status
Simulation time 16385510 ps
CPU time 0.98 seconds
Started Jun 27 06:26:21 PM PDT 24
Finished Jun 27 06:26:28 PM PDT 24
Peak memory 206908 kb
Host smart-6738fb80-b1fb-4b84-a0f7-c4bd7feec46f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524354812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.524354812
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1984823938
Short name T286
Test name
Test status
Simulation time 48846374 ps
CPU time 1.27 seconds
Started Jun 27 06:26:19 PM PDT 24
Finished Jun 27 06:26:25 PM PDT 24
Peak memory 206928 kb
Host smart-d7bf6975-d81b-4bf0-afd0-1e001d66f62c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984823938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1984823938
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.623219895
Short name T1106
Test name
Test status
Simulation time 39947310 ps
CPU time 1.87 seconds
Started Jun 27 06:26:21 PM PDT 24
Finished Jun 27 06:26:29 PM PDT 24
Peak memory 215440 kb
Host smart-ba4b3630-8175-4e8f-9388-16bb0c25dd0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623219895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.623219895
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4270146531
Short name T311
Test name
Test status
Simulation time 166370276 ps
CPU time 2.36 seconds
Started Jun 27 06:26:23 PM PDT 24
Finished Jun 27 06:26:33 PM PDT 24
Peak memory 215208 kb
Host smart-57b1dae9-34ff-4164-9fb2-a999083aeab1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270146531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.4270146531
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2318742448
Short name T1088
Test name
Test status
Simulation time 21051973 ps
CPU time 1.39 seconds
Started Jun 27 06:26:23 PM PDT 24
Finished Jun 27 06:26:32 PM PDT 24
Peak memory 223332 kb
Host smart-2068c8c1-49b7-409b-825a-f13a7a1a439b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318742448 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2318742448
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1744375845
Short name T1008
Test name
Test status
Simulation time 32946770 ps
CPU time 0.81 seconds
Started Jun 27 06:26:30 PM PDT 24
Finished Jun 27 06:26:35 PM PDT 24
Peak memory 206760 kb
Host smart-d0e246ae-247d-4353-92f0-ac09d995e4b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744375845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1744375845
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3376884763
Short name T1044
Test name
Test status
Simulation time 14548898 ps
CPU time 0.91 seconds
Started Jun 27 06:26:20 PM PDT 24
Finished Jun 27 06:26:27 PM PDT 24
Peak memory 206824 kb
Host smart-d239f653-39fd-4647-b3c3-53024c61ab5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376884763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3376884763
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.655795007
Short name T1128
Test name
Test status
Simulation time 111547494 ps
CPU time 1.4 seconds
Started Jun 27 06:26:22 PM PDT 24
Finished Jun 27 06:26:31 PM PDT 24
Peak memory 206920 kb
Host smart-1fb0d2fd-ba18-4106-8f98-b8dfc4327b5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655795007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.655795007
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1441198098
Short name T1012
Test name
Test status
Simulation time 108367328 ps
CPU time 3.91 seconds
Started Jun 27 06:26:15 PM PDT 24
Finished Jun 27 06:26:22 PM PDT 24
Peak memory 215164 kb
Host smart-2ca06044-c763-4be8-81c9-76595d1500b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441198098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1441198098
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1557842831
Short name T1112
Test name
Test status
Simulation time 204911927 ps
CPU time 2.23 seconds
Started Jun 27 06:26:22 PM PDT 24
Finished Jun 27 06:26:30 PM PDT 24
Peak memory 207216 kb
Host smart-e3a9c2c8-5244-4fdb-9154-e7029cc9c13e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557842831 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1557842831
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1200284503
Short name T1016
Test name
Test status
Simulation time 67080047 ps
CPU time 1.24 seconds
Started Jun 27 06:26:20 PM PDT 24
Finished Jun 27 06:26:26 PM PDT 24
Peak memory 206996 kb
Host smart-37e887a3-7101-4510-a166-5b59b8bcfbfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200284503 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1200284503
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.436639972
Short name T1086
Test name
Test status
Simulation time 17930006 ps
CPU time 0.82 seconds
Started Jun 27 06:26:27 PM PDT 24
Finished Jun 27 06:26:34 PM PDT 24
Peak memory 206796 kb
Host smart-7e82d2b8-f152-48fd-8281-acd04fe3ff2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436639972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.436639972
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2033852650
Short name T1109
Test name
Test status
Simulation time 65039448 ps
CPU time 0.87 seconds
Started Jun 27 06:26:16 PM PDT 24
Finished Jun 27 06:26:20 PM PDT 24
Peak memory 206840 kb
Host smart-e6c3fd1e-cb0d-4314-b590-fd35208f3165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033852650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2033852650
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4100939595
Short name T1042
Test name
Test status
Simulation time 339637772 ps
CPU time 1.31 seconds
Started Jun 27 06:26:22 PM PDT 24
Finished Jun 27 06:26:31 PM PDT 24
Peak memory 206980 kb
Host smart-dcdc9141-1ec0-462e-abe5-bfbedfdc5165
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100939595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.4100939595
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3847137445
Short name T1102
Test name
Test status
Simulation time 119802780 ps
CPU time 3.97 seconds
Started Jun 27 06:26:17 PM PDT 24
Finished Jun 27 06:26:24 PM PDT 24
Peak memory 215180 kb
Host smart-4ece00ce-9ade-47a7-a1c2-2590a579f293
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847137445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3847137445
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2527869745
Short name T301
Test name
Test status
Simulation time 180251413 ps
CPU time 1.98 seconds
Started Jun 27 06:26:21 PM PDT 24
Finished Jun 27 06:26:29 PM PDT 24
Peak memory 206896 kb
Host smart-5b67fd8f-2816-4fb2-b776-14d1ee0ec3c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527869745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2527869745
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3209336309
Short name T1050
Test name
Test status
Simulation time 22292483 ps
CPU time 1.09 seconds
Started Jun 27 06:26:20 PM PDT 24
Finished Jun 27 06:26:27 PM PDT 24
Peak memory 215148 kb
Host smart-477e46ae-f063-4f92-9d75-6fc0f10068a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209336309 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3209336309
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3053788324
Short name T274
Test name
Test status
Simulation time 35413300 ps
CPU time 0.82 seconds
Started Jun 27 06:26:20 PM PDT 24
Finished Jun 27 06:26:27 PM PDT 24
Peak memory 206712 kb
Host smart-8ae43cdb-ba44-414c-8e50-edd1efa71bc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053788324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3053788324
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2483297257
Short name T1054
Test name
Test status
Simulation time 26705563 ps
CPU time 0.88 seconds
Started Jun 27 06:26:16 PM PDT 24
Finished Jun 27 06:26:20 PM PDT 24
Peak memory 206852 kb
Host smart-9c3fce0b-8f6e-4220-a045-4fa0a637b100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483297257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2483297257
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3919505091
Short name T1083
Test name
Test status
Simulation time 75353122 ps
CPU time 1.04 seconds
Started Jun 27 06:26:20 PM PDT 24
Finished Jun 27 06:26:26 PM PDT 24
Peak memory 206776 kb
Host smart-ebf41376-e37f-4f78-8927-0081c813d2ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919505091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3919505091
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.664191262
Short name T1094
Test name
Test status
Simulation time 153726821 ps
CPU time 2.51 seconds
Started Jun 27 06:26:22 PM PDT 24
Finished Jun 27 06:26:31 PM PDT 24
Peak memory 215200 kb
Host smart-4961d0bc-d72c-405c-8bf3-e5297c8c7062
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664191262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.664191262
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2838827313
Short name T1021
Test name
Test status
Simulation time 778006049 ps
CPU time 1.58 seconds
Started Jun 27 06:26:19 PM PDT 24
Finished Jun 27 06:26:24 PM PDT 24
Peak memory 215168 kb
Host smart-9b9d17fd-a892-4171-8775-3bb82e255d15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838827313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2838827313
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.948371350
Short name T1014
Test name
Test status
Simulation time 25654772 ps
CPU time 1.17 seconds
Started Jun 27 06:26:03 PM PDT 24
Finished Jun 27 06:26:10 PM PDT 24
Peak memory 206892 kb
Host smart-5ade5ff8-3907-427e-95e6-3244b9c954f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948371350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.948371350
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.299296294
Short name T1096
Test name
Test status
Simulation time 43641041 ps
CPU time 2.01 seconds
Started Jun 27 06:26:15 PM PDT 24
Finished Jun 27 06:26:20 PM PDT 24
Peak memory 206992 kb
Host smart-52597ef3-a22f-4c60-ba18-30ab6907eed3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299296294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.299296294
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3186904416
Short name T1114
Test name
Test status
Simulation time 55205718 ps
CPU time 0.97 seconds
Started Jun 27 06:26:05 PM PDT 24
Finished Jun 27 06:26:11 PM PDT 24
Peak memory 206920 kb
Host smart-479fd452-4d98-45aa-a610-e79e80c1e62c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186904416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3186904416
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4279877164
Short name T1118
Test name
Test status
Simulation time 49860370 ps
CPU time 1.22 seconds
Started Jun 27 06:26:02 PM PDT 24
Finished Jun 27 06:26:08 PM PDT 24
Peak memory 215232 kb
Host smart-b70019c5-0e48-46e1-a44b-f2ec00b00a0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279877164 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.4279877164
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3409814359
Short name T277
Test name
Test status
Simulation time 17130363 ps
CPU time 0.93 seconds
Started Jun 27 06:26:19 PM PDT 24
Finished Jun 27 06:26:25 PM PDT 24
Peak memory 206932 kb
Host smart-cd67a1b4-528e-44dd-9d05-6f26fc341f20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409814359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3409814359
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1153255689
Short name T1111
Test name
Test status
Simulation time 17248012 ps
CPU time 0.92 seconds
Started Jun 27 06:26:03 PM PDT 24
Finished Jun 27 06:26:09 PM PDT 24
Peak memory 206824 kb
Host smart-134ec130-07b1-4642-8572-6e76790f8bde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153255689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1153255689
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2507788572
Short name T285
Test name
Test status
Simulation time 63420116 ps
CPU time 1.04 seconds
Started Jun 27 06:26:02 PM PDT 24
Finished Jun 27 06:26:08 PM PDT 24
Peak memory 206896 kb
Host smart-1ce049b0-d838-40f8-bb00-d74b8bb0368c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507788572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2507788572
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3773120105
Short name T1069
Test name
Test status
Simulation time 334285979 ps
CPU time 2.59 seconds
Started Jun 27 06:26:05 PM PDT 24
Finished Jun 27 06:26:13 PM PDT 24
Peak memory 215196 kb
Host smart-9d4bfa9d-847e-476a-8009-2a44724a7a07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773120105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3773120105
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3319498429
Short name T307
Test name
Test status
Simulation time 174058721 ps
CPU time 1.6 seconds
Started Jun 27 06:26:15 PM PDT 24
Finished Jun 27 06:26:20 PM PDT 24
Peak memory 207000 kb
Host smart-3e9245dc-8dd6-4ff7-b65d-655e5504b789
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319498429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3319498429
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.470768290
Short name T1103
Test name
Test status
Simulation time 15522576 ps
CPU time 0.89 seconds
Started Jun 27 06:26:23 PM PDT 24
Finished Jun 27 06:26:31 PM PDT 24
Peak memory 206832 kb
Host smart-3cc57717-2a40-4274-a75e-f9552f713538
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470768290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.470768290
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.146765360
Short name T999
Test name
Test status
Simulation time 13623616 ps
CPU time 0.86 seconds
Started Jun 27 06:26:18 PM PDT 24
Finished Jun 27 06:26:23 PM PDT 24
Peak memory 206868 kb
Host smart-f501a9cc-a536-4fae-899e-d08a990e693f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146765360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.146765360
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1067304407
Short name T1082
Test name
Test status
Simulation time 14313714 ps
CPU time 0.91 seconds
Started Jun 27 06:26:21 PM PDT 24
Finished Jun 27 06:26:28 PM PDT 24
Peak memory 206948 kb
Host smart-bd8541f0-8cb3-4185-9e19-59cb19e25e56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067304407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1067304407
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3693912014
Short name T1036
Test name
Test status
Simulation time 48695197 ps
CPU time 0.84 seconds
Started Jun 27 06:26:23 PM PDT 24
Finished Jun 27 06:26:32 PM PDT 24
Peak memory 206836 kb
Host smart-9ee948e1-be8f-4625-aabd-cf775c7ff9cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693912014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3693912014
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1655955710
Short name T1104
Test name
Test status
Simulation time 24852462 ps
CPU time 0.89 seconds
Started Jun 27 06:26:24 PM PDT 24
Finished Jun 27 06:26:32 PM PDT 24
Peak memory 206868 kb
Host smart-c3e90cf5-cdc6-4698-850c-435b490ec00c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655955710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1655955710
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.972120197
Short name T1073
Test name
Test status
Simulation time 46471832 ps
CPU time 0.87 seconds
Started Jun 27 06:26:19 PM PDT 24
Finished Jun 27 06:26:25 PM PDT 24
Peak memory 206824 kb
Host smart-78d4245f-76ed-4c75-9a5d-bf34a330457e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972120197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.972120197
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.109172764
Short name T1026
Test name
Test status
Simulation time 20722649 ps
CPU time 0.82 seconds
Started Jun 27 06:26:20 PM PDT 24
Finished Jun 27 06:26:27 PM PDT 24
Peak memory 206616 kb
Host smart-9df9aa67-c1b7-4d93-bd6b-39fdd795bb5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109172764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.109172764
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3060681505
Short name T1117
Test name
Test status
Simulation time 19560236 ps
CPU time 0.82 seconds
Started Jun 27 06:26:20 PM PDT 24
Finished Jun 27 06:26:27 PM PDT 24
Peak memory 206660 kb
Host smart-a0bf3528-bddd-4c84-93f7-104ec5a92c86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060681505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3060681505
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.4170902893
Short name T1121
Test name
Test status
Simulation time 22774345 ps
CPU time 0.81 seconds
Started Jun 27 06:26:20 PM PDT 24
Finished Jun 27 06:26:25 PM PDT 24
Peak memory 206624 kb
Host smart-bf6c18a6-d0ab-4416-b88c-4060d4b1d68d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170902893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.4170902893
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2876319522
Short name T1040
Test name
Test status
Simulation time 14276121 ps
CPU time 0.88 seconds
Started Jun 27 06:26:18 PM PDT 24
Finished Jun 27 06:26:22 PM PDT 24
Peak memory 206868 kb
Host smart-d595e47c-72a0-4aab-ac01-cd42f3e34d0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876319522 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2876319522
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2424062132
Short name T1002
Test name
Test status
Simulation time 69365121 ps
CPU time 1.59 seconds
Started Jun 27 06:26:03 PM PDT 24
Finished Jun 27 06:26:10 PM PDT 24
Peak memory 206992 kb
Host smart-f11489e1-8da0-4745-ad1e-23e696898305
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424062132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2424062132
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2265210772
Short name T1013
Test name
Test status
Simulation time 2840684443 ps
CPU time 5.4 seconds
Started Jun 27 06:26:00 PM PDT 24
Finished Jun 27 06:26:11 PM PDT 24
Peak memory 207084 kb
Host smart-791a5971-d4c2-4588-8ade-38c73804f88e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265210772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2265210772
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2752646189
Short name T995
Test name
Test status
Simulation time 14562065 ps
CPU time 0.93 seconds
Started Jun 27 06:26:06 PM PDT 24
Finished Jun 27 06:26:13 PM PDT 24
Peak memory 206968 kb
Host smart-6fd8fcf9-6c27-456b-90db-4ee71bf1fa87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752646189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2752646189
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3989234260
Short name T1116
Test name
Test status
Simulation time 91548482 ps
CPU time 1.32 seconds
Started Jun 27 06:26:02 PM PDT 24
Finished Jun 27 06:26:08 PM PDT 24
Peak memory 217940 kb
Host smart-5204412a-528f-4b9d-82c5-81403571f6f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989234260 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3989234260
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3337556188
Short name T994
Test name
Test status
Simulation time 13051313 ps
CPU time 0.9 seconds
Started Jun 27 06:26:11 PM PDT 24
Finished Jun 27 06:26:16 PM PDT 24
Peak memory 206928 kb
Host smart-9908782c-8cdb-44ed-ba00-6f43dd482539
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337556188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3337556188
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3857505935
Short name T1079
Test name
Test status
Simulation time 103565413 ps
CPU time 0.84 seconds
Started Jun 27 06:26:04 PM PDT 24
Finished Jun 27 06:26:11 PM PDT 24
Peak memory 206688 kb
Host smart-8eb12d85-9508-4e18-bab9-11b1a29e58d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857505935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3857505935
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.4160901735
Short name T1058
Test name
Test status
Simulation time 126755724 ps
CPU time 0.96 seconds
Started Jun 27 06:26:06 PM PDT 24
Finished Jun 27 06:26:12 PM PDT 24
Peak memory 206932 kb
Host smart-963551ef-fec2-461a-beff-834235824cc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160901735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.4160901735
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.4268062084
Short name T1129
Test name
Test status
Simulation time 201505783 ps
CPU time 3.28 seconds
Started Jun 27 06:26:19 PM PDT 24
Finished Jun 27 06:26:27 PM PDT 24
Peak memory 215160 kb
Host smart-102b4792-208d-427c-b1f9-9ca892f08d09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268062084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.4268062084
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3908461580
Short name T1032
Test name
Test status
Simulation time 79742788 ps
CPU time 1.5 seconds
Started Jun 27 06:26:07 PM PDT 24
Finished Jun 27 06:26:14 PM PDT 24
Peak memory 207012 kb
Host smart-536ee32d-3e9f-48e5-80f4-33b117aeea31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908461580 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3908461580
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1201301155
Short name T1125
Test name
Test status
Simulation time 43789623 ps
CPU time 0.77 seconds
Started Jun 27 06:26:22 PM PDT 24
Finished Jun 27 06:26:29 PM PDT 24
Peak memory 206700 kb
Host smart-5145f70f-1892-4c5a-8dcc-a05b3cedffdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201301155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1201301155
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3673545923
Short name T1072
Test name
Test status
Simulation time 49413646 ps
CPU time 0.77 seconds
Started Jun 27 06:26:27 PM PDT 24
Finished Jun 27 06:26:34 PM PDT 24
Peak memory 206740 kb
Host smart-42f9559f-78fb-4a31-8add-936ea77ea667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673545923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3673545923
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3633147655
Short name T1108
Test name
Test status
Simulation time 43886854 ps
CPU time 0.87 seconds
Started Jun 27 06:26:22 PM PDT 24
Finished Jun 27 06:26:30 PM PDT 24
Peak memory 206836 kb
Host smart-351a6b0f-80d2-4b9e-a914-e64f2f9255e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633147655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3633147655
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.565435654
Short name T1124
Test name
Test status
Simulation time 24707094 ps
CPU time 0.84 seconds
Started Jun 27 06:26:20 PM PDT 24
Finished Jun 27 06:26:27 PM PDT 24
Peak memory 206852 kb
Host smart-23a93b28-8f53-4ebd-bd87-8d9c8c73bfd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565435654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.565435654
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.649718803
Short name T1030
Test name
Test status
Simulation time 40274334 ps
CPU time 0.83 seconds
Started Jun 27 06:26:22 PM PDT 24
Finished Jun 27 06:26:29 PM PDT 24
Peak memory 206872 kb
Host smart-06a1de76-c7a8-4712-9ba9-6f1a80019945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649718803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.649718803
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1948976924
Short name T1113
Test name
Test status
Simulation time 34278791 ps
CPU time 0.82 seconds
Started Jun 27 06:26:22 PM PDT 24
Finished Jun 27 06:26:30 PM PDT 24
Peak memory 206636 kb
Host smart-f70c8936-d414-45af-be10-839b0eabb9de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948976924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1948976924
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1463393273
Short name T1004
Test name
Test status
Simulation time 100104672 ps
CPU time 0.88 seconds
Started Jun 27 06:26:19 PM PDT 24
Finished Jun 27 06:26:25 PM PDT 24
Peak memory 206840 kb
Host smart-755227ed-4e4c-461b-9b53-9a066aa70f2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463393273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1463393273
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3716729211
Short name T1023
Test name
Test status
Simulation time 41947118 ps
CPU time 0.87 seconds
Started Jun 27 06:26:21 PM PDT 24
Finished Jun 27 06:26:28 PM PDT 24
Peak memory 206836 kb
Host smart-e3f7c9b0-345e-4feb-8210-229289f0ffe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716729211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3716729211
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3013545465
Short name T1075
Test name
Test status
Simulation time 37278159 ps
CPU time 0.9 seconds
Started Jun 27 06:26:23 PM PDT 24
Finished Jun 27 06:26:31 PM PDT 24
Peak memory 206808 kb
Host smart-78d0f6bc-ccc1-4215-b04e-986334387c68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013545465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3013545465
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.895583390
Short name T1123
Test name
Test status
Simulation time 20341003 ps
CPU time 0.81 seconds
Started Jun 27 06:26:20 PM PDT 24
Finished Jun 27 06:26:27 PM PDT 24
Peak memory 206840 kb
Host smart-c05536c9-d5f8-44ea-b4ef-9af4f582d3f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895583390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.895583390
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3871521900
Short name T278
Test name
Test status
Simulation time 43244257 ps
CPU time 1.16 seconds
Started Jun 27 06:26:14 PM PDT 24
Finished Jun 27 06:26:18 PM PDT 24
Peak memory 206984 kb
Host smart-f9ae6e54-2f58-4f53-ab38-74ba7cbf76e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871521900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3871521900
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.551260701
Short name T1029
Test name
Test status
Simulation time 506906232 ps
CPU time 3.1 seconds
Started Jun 27 06:26:10 PM PDT 24
Finished Jun 27 06:26:18 PM PDT 24
Peak memory 207016 kb
Host smart-bd656531-ac0e-4530-bec9-01e88e74a5b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551260701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.551260701
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1017219436
Short name T276
Test name
Test status
Simulation time 23268517 ps
CPU time 0.89 seconds
Started Jun 27 06:26:04 PM PDT 24
Finished Jun 27 06:26:11 PM PDT 24
Peak memory 206916 kb
Host smart-795e1e83-5400-4d54-a261-93c3e8e43701
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017219436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1017219436
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3947141190
Short name T1115
Test name
Test status
Simulation time 19595163 ps
CPU time 1.07 seconds
Started Jun 27 06:26:03 PM PDT 24
Finished Jun 27 06:26:10 PM PDT 24
Peak memory 206948 kb
Host smart-d2373ff6-a2d8-4ff1-9082-c53c17ed85d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947141190 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3947141190
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.777969317
Short name T1017
Test name
Test status
Simulation time 14410483 ps
CPU time 0.88 seconds
Started Jun 27 06:26:07 PM PDT 24
Finished Jun 27 06:26:13 PM PDT 24
Peak memory 206936 kb
Host smart-dc0cab9f-3c9f-4080-9ecd-8bb76df873e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777969317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.777969317
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1732832581
Short name T1051
Test name
Test status
Simulation time 21444755 ps
CPU time 0.83 seconds
Started Jun 27 06:26:01 PM PDT 24
Finished Jun 27 06:26:07 PM PDT 24
Peak memory 206840 kb
Host smart-165f1d89-ad57-4ac0-a642-cac16d481d3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732832581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1732832581
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2789566292
Short name T1045
Test name
Test status
Simulation time 19696088 ps
CPU time 1.03 seconds
Started Jun 27 06:26:19 PM PDT 24
Finished Jun 27 06:26:25 PM PDT 24
Peak memory 206884 kb
Host smart-cf06fbce-efd4-4d35-a53f-4706297745df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789566292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2789566292
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.525434449
Short name T1056
Test name
Test status
Simulation time 50590501 ps
CPU time 2.03 seconds
Started Jun 27 06:26:05 PM PDT 24
Finished Jun 27 06:26:13 PM PDT 24
Peak memory 218740 kb
Host smart-57dfe1fb-42db-4bf9-98d9-5e6c6cbc3c2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525434449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.525434449
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.657137945
Short name T1074
Test name
Test status
Simulation time 207593998 ps
CPU time 2.39 seconds
Started Jun 27 06:26:14 PM PDT 24
Finished Jun 27 06:26:20 PM PDT 24
Peak memory 206932 kb
Host smart-b264193d-dfaa-48f1-88b7-b8324136182d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657137945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.657137945
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3943259651
Short name T1043
Test name
Test status
Simulation time 38264886 ps
CPU time 0.83 seconds
Started Jun 27 06:26:22 PM PDT 24
Finished Jun 27 06:26:30 PM PDT 24
Peak memory 206672 kb
Host smart-1c40c33c-da92-497a-a2e6-e0cba52c9b1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943259651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3943259651
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1627587416
Short name T1018
Test name
Test status
Simulation time 13107074 ps
CPU time 0.81 seconds
Started Jun 27 06:26:18 PM PDT 24
Finished Jun 27 06:26:22 PM PDT 24
Peak memory 206912 kb
Host smart-6cd71cfe-a58c-490d-a76c-a9e1d56fe898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627587416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1627587416
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.200923787
Short name T1010
Test name
Test status
Simulation time 13254121 ps
CPU time 0.81 seconds
Started Jun 27 06:26:30 PM PDT 24
Finished Jun 27 06:26:35 PM PDT 24
Peak memory 206808 kb
Host smart-b4d0d42c-3187-4d1f-8ac6-c2a966a2913d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200923787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.200923787
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2483600623
Short name T1061
Test name
Test status
Simulation time 14555493 ps
CPU time 0.88 seconds
Started Jun 27 06:26:21 PM PDT 24
Finished Jun 27 06:26:28 PM PDT 24
Peak memory 206840 kb
Host smart-8a5c5bea-aa8a-4fe5-9cb2-3bb6e08ef980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483600623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2483600623
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3824678254
Short name T1122
Test name
Test status
Simulation time 42905778 ps
CPU time 0.88 seconds
Started Jun 27 06:26:29 PM PDT 24
Finished Jun 27 06:26:35 PM PDT 24
Peak memory 206692 kb
Host smart-db340a19-0c01-4fde-80f7-8ac687b78d8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824678254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3824678254
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2610482377
Short name T1001
Test name
Test status
Simulation time 26295004 ps
CPU time 0.83 seconds
Started Jun 27 06:26:20 PM PDT 24
Finished Jun 27 06:26:27 PM PDT 24
Peak memory 206780 kb
Host smart-0f59d492-529c-4872-8ccc-7d8f36ace86b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610482377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2610482377
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1975835044
Short name T1059
Test name
Test status
Simulation time 31537092 ps
CPU time 0.78 seconds
Started Jun 27 06:26:20 PM PDT 24
Finished Jun 27 06:26:25 PM PDT 24
Peak memory 206520 kb
Host smart-d567c83b-882c-443a-a49c-238656e53b53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975835044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1975835044
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.640090635
Short name T1078
Test name
Test status
Simulation time 95601654 ps
CPU time 0.92 seconds
Started Jun 27 06:26:29 PM PDT 24
Finished Jun 27 06:26:35 PM PDT 24
Peak memory 206872 kb
Host smart-7c64435a-9ba6-4a13-bc71-e1ec369393c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640090635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.640090635
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3003132843
Short name T1098
Test name
Test status
Simulation time 24369622 ps
CPU time 0.88 seconds
Started Jun 27 06:26:22 PM PDT 24
Finished Jun 27 06:26:30 PM PDT 24
Peak memory 206848 kb
Host smart-d0a50f07-3dbe-4a0d-8dfe-aecb07e69e9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003132843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3003132843
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3108034170
Short name T1048
Test name
Test status
Simulation time 13722879 ps
CPU time 0.88 seconds
Started Jun 27 06:26:20 PM PDT 24
Finished Jun 27 06:26:27 PM PDT 24
Peak memory 206844 kb
Host smart-612fa366-cfac-49df-86e9-7c98819171fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108034170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3108034170
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1054862926
Short name T1033
Test name
Test status
Simulation time 67159582 ps
CPU time 1.33 seconds
Started Jun 27 06:26:00 PM PDT 24
Finished Jun 27 06:26:06 PM PDT 24
Peak memory 215280 kb
Host smart-ffd050ed-a06a-4295-9501-4e577f74f6fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054862926 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1054862926
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.410646779
Short name T1110
Test name
Test status
Simulation time 52287161 ps
CPU time 0.85 seconds
Started Jun 27 06:26:17 PM PDT 24
Finished Jun 27 06:26:21 PM PDT 24
Peak memory 206932 kb
Host smart-6185f7e5-ec97-4868-9bd4-a38a3221b434
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410646779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.410646779
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.974325160
Short name T1064
Test name
Test status
Simulation time 28338240 ps
CPU time 0.81 seconds
Started Jun 27 06:26:07 PM PDT 24
Finished Jun 27 06:26:13 PM PDT 24
Peak memory 206744 kb
Host smart-d1161408-a13a-4710-b3c2-20a9579320ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974325160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.974325160
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4121010897
Short name T1092
Test name
Test status
Simulation time 62488626 ps
CPU time 1.33 seconds
Started Jun 27 06:26:13 PM PDT 24
Finished Jun 27 06:26:18 PM PDT 24
Peak memory 206916 kb
Host smart-c5656e9a-43a7-4a0d-8f94-4c962c8fb370
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121010897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.4121010897
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3557798190
Short name T1105
Test name
Test status
Simulation time 78028502 ps
CPU time 2.93 seconds
Started Jun 27 06:26:03 PM PDT 24
Finished Jun 27 06:26:10 PM PDT 24
Peak memory 215192 kb
Host smart-cd36f38e-d383-4eac-a4f9-c57b8571bb76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557798190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3557798190
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3591151743
Short name T1034
Test name
Test status
Simulation time 126326675 ps
CPU time 3.01 seconds
Started Jun 27 06:26:07 PM PDT 24
Finished Jun 27 06:26:15 PM PDT 24
Peak memory 215116 kb
Host smart-949d6493-b2f9-4982-a0b5-780bb9422a1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591151743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3591151743
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1985877497
Short name T1038
Test name
Test status
Simulation time 19569508 ps
CPU time 1.11 seconds
Started Jun 27 06:26:04 PM PDT 24
Finished Jun 27 06:26:11 PM PDT 24
Peak memory 215160 kb
Host smart-e12f1357-0b65-427b-a6ac-1f247840f83b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985877497 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1985877497
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1770870917
Short name T273
Test name
Test status
Simulation time 24146913 ps
CPU time 0.87 seconds
Started Jun 27 06:26:07 PM PDT 24
Finished Jun 27 06:26:13 PM PDT 24
Peak memory 206884 kb
Host smart-da3940f5-0f7b-4709-9bd4-d18981a58382
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770870917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1770870917
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2480132617
Short name T1126
Test name
Test status
Simulation time 155316566 ps
CPU time 0.87 seconds
Started Jun 27 06:26:05 PM PDT 24
Finished Jun 27 06:26:11 PM PDT 24
Peak memory 206692 kb
Host smart-3e547672-f0c7-45ff-94b5-b6c4d285eb60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480132617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2480132617
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2127048212
Short name T1095
Test name
Test status
Simulation time 26452869 ps
CPU time 1.02 seconds
Started Jun 27 06:26:08 PM PDT 24
Finished Jun 27 06:26:14 PM PDT 24
Peak memory 206848 kb
Host smart-95a5daa4-25b9-4a6e-9e44-e76975acd8e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127048212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2127048212
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.4081607038
Short name T1119
Test name
Test status
Simulation time 121555252 ps
CPU time 2.61 seconds
Started Jun 27 06:26:04 PM PDT 24
Finished Jun 27 06:26:13 PM PDT 24
Peak memory 215108 kb
Host smart-13b0098d-89a7-45e5-a528-d7c00dccbac3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081607038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.4081607038
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3522073000
Short name T1046
Test name
Test status
Simulation time 87472472 ps
CPU time 2.53 seconds
Started Jun 27 06:26:07 PM PDT 24
Finished Jun 27 06:26:16 PM PDT 24
Peak memory 215080 kb
Host smart-d5563fee-0202-447a-b70e-df74b187b3c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522073000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3522073000
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2905130105
Short name T1037
Test name
Test status
Simulation time 93257703 ps
CPU time 1.7 seconds
Started Jun 27 06:26:08 PM PDT 24
Finished Jun 27 06:26:15 PM PDT 24
Peak memory 215148 kb
Host smart-d2818c84-c4b4-4ed8-ae94-b0a7fa35db7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905130105 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2905130105
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1222363778
Short name T283
Test name
Test status
Simulation time 38233129 ps
CPU time 0.76 seconds
Started Jun 27 06:26:17 PM PDT 24
Finished Jun 27 06:26:21 PM PDT 24
Peak memory 206744 kb
Host smart-b7e2c535-61c7-4afa-8ef7-5500e472ad59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222363778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1222363778
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.354303777
Short name T997
Test name
Test status
Simulation time 62103258 ps
CPU time 0.87 seconds
Started Jun 27 06:26:19 PM PDT 24
Finished Jun 27 06:26:25 PM PDT 24
Peak memory 206876 kb
Host smart-5ddd52dc-29e3-4df6-825f-ffb65110f226
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354303777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.354303777
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3860820634
Short name T1070
Test name
Test status
Simulation time 17886447 ps
CPU time 0.89 seconds
Started Jun 27 06:26:03 PM PDT 24
Finished Jun 27 06:26:10 PM PDT 24
Peak memory 206980 kb
Host smart-249c0f3b-8906-4d16-8502-0e8da1cb1dfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860820634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3860820634
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3252967777
Short name T1057
Test name
Test status
Simulation time 66062623 ps
CPU time 2.44 seconds
Started Jun 27 06:26:07 PM PDT 24
Finished Jun 27 06:26:14 PM PDT 24
Peak memory 219288 kb
Host smart-2f8fd978-982e-4545-8095-e64168ecbef0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252967777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3252967777
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3691994517
Short name T1060
Test name
Test status
Simulation time 45459342 ps
CPU time 1.53 seconds
Started Jun 27 06:26:16 PM PDT 24
Finished Jun 27 06:26:20 PM PDT 24
Peak memory 206884 kb
Host smart-c26d25e3-99e5-4836-9e48-07a4cd7a3a87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691994517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3691994517
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1179002103
Short name T1066
Test name
Test status
Simulation time 49635228 ps
CPU time 1.83 seconds
Started Jun 27 06:26:15 PM PDT 24
Finished Jun 27 06:26:20 PM PDT 24
Peak memory 215256 kb
Host smart-aa8f8532-099f-4f02-8d43-8fa44170c333
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179002103 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1179002103
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2331263140
Short name T1019
Test name
Test status
Simulation time 50539844 ps
CPU time 0.94 seconds
Started Jun 27 06:26:05 PM PDT 24
Finished Jun 27 06:26:11 PM PDT 24
Peak memory 206924 kb
Host smart-94316de7-c328-44b4-9743-e2879a4bcd92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331263140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2331263140
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.918395637
Short name T993
Test name
Test status
Simulation time 31796283 ps
CPU time 0.92 seconds
Started Jun 27 06:26:08 PM PDT 24
Finished Jun 27 06:26:14 PM PDT 24
Peak memory 206828 kb
Host smart-58cc68a1-4501-4a39-9108-c8698c11c494
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918395637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.918395637
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3884927526
Short name T1047
Test name
Test status
Simulation time 17361804 ps
CPU time 1.04 seconds
Started Jun 27 06:26:14 PM PDT 24
Finished Jun 27 06:26:18 PM PDT 24
Peak memory 206992 kb
Host smart-4130b6f5-a034-436c-9d48-35cbe428956d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884927526 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3884927526
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.4289564781
Short name T1101
Test name
Test status
Simulation time 371309287 ps
CPU time 3.02 seconds
Started Jun 27 06:26:06 PM PDT 24
Finished Jun 27 06:26:14 PM PDT 24
Peak memory 215192 kb
Host smart-680f7dff-c030-405e-9e9d-b01630475f33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289564781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.4289564781
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4079801754
Short name T1055
Test name
Test status
Simulation time 48721030 ps
CPU time 1.56 seconds
Started Jun 27 06:26:14 PM PDT 24
Finished Jun 27 06:26:19 PM PDT 24
Peak memory 206936 kb
Host smart-484b4c6c-83d1-42ab-af9b-7a354e440cab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079801754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.4079801754
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3963493470
Short name T1076
Test name
Test status
Simulation time 34954950 ps
CPU time 1.5 seconds
Started Jun 27 06:26:18 PM PDT 24
Finished Jun 27 06:26:23 PM PDT 24
Peak memory 215188 kb
Host smart-9189e5c4-aaee-4830-b64e-a4d73b926d88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963493470 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3963493470
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.901224175
Short name T275
Test name
Test status
Simulation time 38026060 ps
CPU time 0.84 seconds
Started Jun 27 06:26:18 PM PDT 24
Finished Jun 27 06:26:22 PM PDT 24
Peak memory 206852 kb
Host smart-521a379e-b375-4698-af85-104d483bce41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901224175 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.901224175
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2847030301
Short name T1009
Test name
Test status
Simulation time 35843269 ps
CPU time 0.88 seconds
Started Jun 27 06:26:07 PM PDT 24
Finished Jun 27 06:26:14 PM PDT 24
Peak memory 206808 kb
Host smart-c99e606e-1420-4ae7-ade9-6d6493f52add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847030301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2847030301
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1036904716
Short name T1025
Test name
Test status
Simulation time 15272182 ps
CPU time 0.98 seconds
Started Jun 27 06:26:09 PM PDT 24
Finished Jun 27 06:26:15 PM PDT 24
Peak memory 206848 kb
Host smart-6a77b0c4-9c5f-41f9-ab32-eb585360345c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036904716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1036904716
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.938631809
Short name T1100
Test name
Test status
Simulation time 42425707 ps
CPU time 2.75 seconds
Started Jun 27 06:26:07 PM PDT 24
Finished Jun 27 06:26:15 PM PDT 24
Peak memory 215220 kb
Host smart-63b8e6d0-e844-4f90-a4bb-754ff5e1a389
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938631809 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.938631809
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.895189558
Short name T1090
Test name
Test status
Simulation time 154202673 ps
CPU time 3.39 seconds
Started Jun 27 06:26:20 PM PDT 24
Finished Jun 27 06:26:29 PM PDT 24
Peak memory 215192 kb
Host smart-1988bcef-58e0-46e9-b566-7cb75f4a7300
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895189558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.895189558
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.534668808
Short name T760
Test name
Test status
Simulation time 55196334 ps
CPU time 1.26 seconds
Started Jun 27 06:29:41 PM PDT 24
Finished Jun 27 06:29:44 PM PDT 24
Peak memory 221028 kb
Host smart-9c8d7399-9e34-4308-90d6-0d1c75901871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534668808 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.534668808
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.3643082764
Short name T896
Test name
Test status
Simulation time 69560879 ps
CPU time 0.84 seconds
Started Jun 27 06:29:46 PM PDT 24
Finished Jun 27 06:29:53 PM PDT 24
Peak memory 215456 kb
Host smart-11971098-f3ea-4136-b6ad-bc18f6e7dce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643082764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3643082764
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2322082791
Short name T539
Test name
Test status
Simulation time 26919115 ps
CPU time 1.03 seconds
Started Jun 27 06:29:44 PM PDT 24
Finished Jun 27 06:29:49 PM PDT 24
Peak memory 217084 kb
Host smart-c38ff566-bbac-4fff-9897-d70a03d838e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322082791 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2322082791
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.3170449981
Short name T712
Test name
Test status
Simulation time 31348954 ps
CPU time 0.92 seconds
Started Jun 27 06:29:42 PM PDT 24
Finished Jun 27 06:29:45 PM PDT 24
Peak memory 218704 kb
Host smart-911ceebe-d818-4b96-a460-3d1edf6fc345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170449981 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3170449981
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.4111387673
Short name T898
Test name
Test status
Simulation time 132112211 ps
CPU time 1.57 seconds
Started Jun 27 06:29:47 PM PDT 24
Finished Jun 27 06:29:55 PM PDT 24
Peak memory 219264 kb
Host smart-74cd4056-64d8-4ffd-9987-08892f9ebd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111387673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.4111387673
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1742542173
Short name T605
Test name
Test status
Simulation time 19658202 ps
CPU time 1.09 seconds
Started Jun 27 06:29:43 PM PDT 24
Finished Jun 27 06:29:47 PM PDT 24
Peak memory 216192 kb
Host smart-42aa6c78-31c4-479b-bcf1-2898f9f67c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742542173 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1742542173
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.1378447883
Short name T882
Test name
Test status
Simulation time 29081895 ps
CPU time 0.95 seconds
Started Jun 27 06:29:47 PM PDT 24
Finished Jun 27 06:29:54 PM PDT 24
Peak memory 207368 kb
Host smart-5d941e85-152f-47f6-9f7d-7d384288cf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378447883 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1378447883
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.130066365
Short name T54
Test name
Test status
Simulation time 886995044 ps
CPU time 4.33 seconds
Started Jun 27 06:29:40 PM PDT 24
Finished Jun 27 06:29:46 PM PDT 24
Peak memory 235568 kb
Host smart-7c2ad32c-6562-491b-b56e-cd8182c5ddac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130066365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.130066365
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.1166252593
Short name T560
Test name
Test status
Simulation time 27675274 ps
CPU time 0.96 seconds
Started Jun 27 06:29:41 PM PDT 24
Finished Jun 27 06:29:45 PM PDT 24
Peak memory 215640 kb
Host smart-d75e910c-9e2d-43be-bcdf-0608a5982496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166252593 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1166252593
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3697737791
Short name T974
Test name
Test status
Simulation time 322821256 ps
CPU time 3.1 seconds
Started Jun 27 06:29:41 PM PDT 24
Finished Jun 27 06:29:47 PM PDT 24
Peak memory 217844 kb
Host smart-0862108d-6c8a-4a9a-a500-9290857860f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697737791 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3697737791
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2794879912
Short name T907
Test name
Test status
Simulation time 138108493365 ps
CPU time 864.59 seconds
Started Jun 27 06:29:46 PM PDT 24
Finished Jun 27 06:44:17 PM PDT 24
Peak memory 222628 kb
Host smart-ae016eda-b51f-40f0-bc14-f0537a40d5d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794879912 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2794879912
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.3882282601
Short name T777
Test name
Test status
Simulation time 18550769 ps
CPU time 0.91 seconds
Started Jun 27 06:29:42 PM PDT 24
Finished Jun 27 06:29:46 PM PDT 24
Peak memory 206972 kb
Host smart-8585c9c6-076c-4ed6-a587-f3336f8b9363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882282601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3882282601
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.3386594665
Short name T201
Test name
Test status
Simulation time 19682390 ps
CPU time 0.88 seconds
Started Jun 27 06:29:46 PM PDT 24
Finished Jun 27 06:29:54 PM PDT 24
Peak memory 216528 kb
Host smart-60830bb0-db38-4c5a-9ce9-208d2855be4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386594665 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3386594665
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2159494117
Short name T851
Test name
Test status
Simulation time 166002290 ps
CPU time 1.19 seconds
Started Jun 27 06:29:46 PM PDT 24
Finished Jun 27 06:29:53 PM PDT 24
Peak memory 218860 kb
Host smart-77cdda66-fd50-432b-8d72-38cfd84f3adc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159494117 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2159494117
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.3308594556
Short name T573
Test name
Test status
Simulation time 19278394 ps
CPU time 1.08 seconds
Started Jun 27 06:29:44 PM PDT 24
Finished Jun 27 06:29:49 PM PDT 24
Peak memory 218568 kb
Host smart-9d585197-4045-40bb-a8a1-39c16e184a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308594556 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3308594556
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.1855994139
Short name T818
Test name
Test status
Simulation time 116834154 ps
CPU time 1.22 seconds
Started Jun 27 06:29:44 PM PDT 24
Finished Jun 27 06:29:50 PM PDT 24
Peak memory 220572 kb
Host smart-6427ca09-170c-4cc5-862b-9544f4fed4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855994139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1855994139
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2397782099
Short name T86
Test name
Test status
Simulation time 21568621 ps
CPU time 1.13 seconds
Started Jun 27 06:29:44 PM PDT 24
Finished Jun 27 06:29:50 PM PDT 24
Peak memory 216088 kb
Host smart-f2fedd36-fc28-4519-be13-11bbc9e4fad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397782099 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2397782099
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2083951964
Short name T18
Test name
Test status
Simulation time 845954834 ps
CPU time 7.17 seconds
Started Jun 27 06:29:46 PM PDT 24
Finished Jun 27 06:29:59 PM PDT 24
Peak memory 240392 kb
Host smart-5e87ec6c-a69a-4cfa-8e42-c17373f5f244
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083951964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2083951964
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1555340120
Short name T730
Test name
Test status
Simulation time 22032264 ps
CPU time 1 seconds
Started Jun 27 06:29:46 PM PDT 24
Finished Jun 27 06:29:54 PM PDT 24
Peak memory 215636 kb
Host smart-cb91be5a-a30d-491b-aaaf-5a6410e65de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555340120 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1555340120
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3960837518
Short name T404
Test name
Test status
Simulation time 236591653 ps
CPU time 4.39 seconds
Started Jun 27 06:29:43 PM PDT 24
Finished Jun 27 06:29:50 PM PDT 24
Peak memory 215648 kb
Host smart-e0c6ab36-887e-4d55-80b7-695a54c38ca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960837518 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3960837518
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1668131683
Short name T468
Test name
Test status
Simulation time 176896911084 ps
CPU time 1593.69 seconds
Started Jun 27 06:29:45 PM PDT 24
Finished Jun 27 06:56:25 PM PDT 24
Peak memory 227164 kb
Host smart-b18dfa63-211d-43e0-bcfc-9551dfdfee7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668131683 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1668131683
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.2310457816
Short name T625
Test name
Test status
Simulation time 36152373 ps
CPU time 1.09 seconds
Started Jun 27 06:30:00 PM PDT 24
Finished Jun 27 06:30:06 PM PDT 24
Peak memory 218752 kb
Host smart-84cdb2ab-f91f-468b-bf71-357fff4d98bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310457816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2310457816
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.1039932912
Short name T546
Test name
Test status
Simulation time 17177267 ps
CPU time 1 seconds
Started Jun 27 06:30:03 PM PDT 24
Finished Jun 27 06:30:08 PM PDT 24
Peak memory 207032 kb
Host smart-d192a67f-caa3-425a-8c04-a7628960e81f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039932912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1039932912
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.2787782416
Short name T212
Test name
Test status
Simulation time 82889512 ps
CPU time 1.03 seconds
Started Jun 27 06:30:05 PM PDT 24
Finished Jun 27 06:30:10 PM PDT 24
Peak memory 219804 kb
Host smart-a275c6f2-5650-4c4e-b0e7-4b58a55b3644
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787782416 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.2787782416
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.1366164419
Short name T93
Test name
Test status
Simulation time 20002471 ps
CPU time 1.08 seconds
Started Jun 27 06:30:00 PM PDT 24
Finished Jun 27 06:30:06 PM PDT 24
Peak memory 218808 kb
Host smart-d5e4b4f0-834f-462e-a7f6-2aa764b1ca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366164419 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1366164419
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.4271117268
Short name T567
Test name
Test status
Simulation time 222515166 ps
CPU time 2.08 seconds
Started Jun 27 06:29:53 PM PDT 24
Finished Jun 27 06:30:03 PM PDT 24
Peak memory 217932 kb
Host smart-3aaaa68e-fdcb-4511-b761-68e77498676c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271117268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.4271117268
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3276012708
Short name T389
Test name
Test status
Simulation time 33591945 ps
CPU time 0.92 seconds
Started Jun 27 06:29:59 PM PDT 24
Finished Jun 27 06:30:05 PM PDT 24
Peak memory 215728 kb
Host smart-5899982a-1064-4b9c-8a3a-1fc57ddacb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276012708 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3276012708
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3607010733
Short name T390
Test name
Test status
Simulation time 15413716 ps
CPU time 0.99 seconds
Started Jun 27 06:29:58 PM PDT 24
Finished Jun 27 06:30:05 PM PDT 24
Peak memory 215596 kb
Host smart-bdf736f0-98b5-4fa9-b2f4-57023ffbed3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607010733 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3607010733
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2255563310
Short name T662
Test name
Test status
Simulation time 406473456 ps
CPU time 4.48 seconds
Started Jun 27 06:30:00 PM PDT 24
Finished Jun 27 06:30:09 PM PDT 24
Peak memory 217656 kb
Host smart-2fe22d30-1ec1-4721-b8e4-d5054378275b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255563310 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2255563310
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3721733993
Short name T234
Test name
Test status
Simulation time 69328678267 ps
CPU time 751.63 seconds
Started Jun 27 06:29:58 PM PDT 24
Finished Jun 27 06:42:36 PM PDT 24
Peak memory 219312 kb
Host smart-fe9f0807-a237-44fa-ab07-a1ecc6273cfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721733993 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3721733993
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.2462120053
Short name T188
Test name
Test status
Simulation time 27020134 ps
CPU time 1.18 seconds
Started Jun 27 06:32:15 PM PDT 24
Finished Jun 27 06:32:26 PM PDT 24
Peak memory 219132 kb
Host smart-db405014-21ac-4416-94ec-31d27576cd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462120053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.2462120053
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.851721505
Short name T657
Test name
Test status
Simulation time 114465295 ps
CPU time 1.1 seconds
Started Jun 27 06:32:10 PM PDT 24
Finished Jun 27 06:32:14 PM PDT 24
Peak memory 217628 kb
Host smart-74e5e54e-555a-4da0-aebe-414ab0e82ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851721505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.851721505
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.1628546009
Short name T312
Test name
Test status
Simulation time 22312853 ps
CPU time 1.17 seconds
Started Jun 27 06:32:14 PM PDT 24
Finished Jun 27 06:32:25 PM PDT 24
Peak memory 219092 kb
Host smart-187be2d2-5461-4beb-8947-f904d2648ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628546009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.1628546009
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.2576395329
Short name T865
Test name
Test status
Simulation time 28057307 ps
CPU time 1.29 seconds
Started Jun 27 06:32:11 PM PDT 24
Finished Jun 27 06:32:18 PM PDT 24
Peak memory 220032 kb
Host smart-38d56f40-a0be-4826-b091-ee612d46578b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576395329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2576395329
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.3068235348
Short name T774
Test name
Test status
Simulation time 23715885 ps
CPU time 1.2 seconds
Started Jun 27 06:32:35 PM PDT 24
Finished Jun 27 06:32:40 PM PDT 24
Peak memory 219908 kb
Host smart-193b1fd7-e34b-42f0-8088-308c77914f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068235348 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.3068235348
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.2701101447
Short name T99
Test name
Test status
Simulation time 39188692 ps
CPU time 1.34 seconds
Started Jun 27 06:32:14 PM PDT 24
Finished Jun 27 06:32:25 PM PDT 24
Peak memory 218916 kb
Host smart-db354cbf-1c9e-49ff-90bb-b2323fc72c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701101447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2701101447
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.2280497367
Short name T710
Test name
Test status
Simulation time 28792467 ps
CPU time 1.28 seconds
Started Jun 27 06:32:36 PM PDT 24
Finished Jun 27 06:32:41 PM PDT 24
Peak memory 221220 kb
Host smart-ba73d10f-b03c-4078-bc22-c5ed73c42c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280497367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.2280497367
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.880371151
Short name T734
Test name
Test status
Simulation time 62444427 ps
CPU time 0.98 seconds
Started Jun 27 06:32:32 PM PDT 24
Finished Jun 27 06:32:38 PM PDT 24
Peak memory 217692 kb
Host smart-aaaab567-8906-443a-bd30-21eed4b22693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880371151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.880371151
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.4108044762
Short name T628
Test name
Test status
Simulation time 83545811 ps
CPU time 1.12 seconds
Started Jun 27 06:32:34 PM PDT 24
Finished Jun 27 06:32:39 PM PDT 24
Peak memory 220896 kb
Host smart-ef15e6d2-6f66-4c56-bd9d-1cde2b8ad36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108044762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.4108044762
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.3392242580
Short name T676
Test name
Test status
Simulation time 44696318 ps
CPU time 1.64 seconds
Started Jun 27 06:32:28 PM PDT 24
Finished Jun 27 06:32:36 PM PDT 24
Peak memory 218792 kb
Host smart-29e2799b-b411-4f30-a73e-06c7c6eaaed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392242580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3392242580
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.1719703631
Short name T828
Test name
Test status
Simulation time 48610159 ps
CPU time 1.22 seconds
Started Jun 27 06:32:22 PM PDT 24
Finished Jun 27 06:32:32 PM PDT 24
Peak memory 216012 kb
Host smart-3c5e8ae5-0d7b-4bab-986e-a7bcd3476b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719703631 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.1719703631
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.2214473091
Short name T694
Test name
Test status
Simulation time 107858725 ps
CPU time 1.43 seconds
Started Jun 27 06:32:23 PM PDT 24
Finished Jun 27 06:32:33 PM PDT 24
Peak memory 219344 kb
Host smart-f98672bc-7949-4905-bb46-2a5865006b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214473091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2214473091
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.3197834125
Short name T660
Test name
Test status
Simulation time 44451645 ps
CPU time 1.09 seconds
Started Jun 27 06:32:25 PM PDT 24
Finished Jun 27 06:32:34 PM PDT 24
Peak memory 220432 kb
Host smart-2aeace86-7b81-4146-83f7-babc936b1db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197834125 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.3197834125
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.2227461013
Short name T360
Test name
Test status
Simulation time 42982450 ps
CPU time 1.22 seconds
Started Jun 27 06:32:35 PM PDT 24
Finished Jun 27 06:32:40 PM PDT 24
Peak memory 217760 kb
Host smart-65b13317-e03f-4819-9167-ea50f338c5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227461013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2227461013
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.1617325465
Short name T181
Test name
Test status
Simulation time 37004643 ps
CPU time 1.16 seconds
Started Jun 27 06:32:23 PM PDT 24
Finished Jun 27 06:32:33 PM PDT 24
Peak memory 219184 kb
Host smart-0fe374a3-70c1-4a50-8cc9-7ff0f01f772d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617325465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.1617325465
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.2640777450
Short name T12
Test name
Test status
Simulation time 60801021 ps
CPU time 1.28 seconds
Started Jun 27 06:32:22 PM PDT 24
Finished Jun 27 06:32:32 PM PDT 24
Peak memory 220200 kb
Host smart-64073f4d-b848-43a8-b84e-1a51942530f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640777450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2640777450
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.661242184
Short name T855
Test name
Test status
Simulation time 87853320 ps
CPU time 1.23 seconds
Started Jun 27 06:32:28 PM PDT 24
Finished Jun 27 06:32:35 PM PDT 24
Peak memory 215960 kb
Host smart-f714dadf-4b3b-44f2-aa8a-86e4ec5f0b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661242184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.661242184
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.1413505542
Short name T979
Test name
Test status
Simulation time 200992948 ps
CPU time 1.01 seconds
Started Jun 27 06:32:34 PM PDT 24
Finished Jun 27 06:32:40 PM PDT 24
Peak memory 217580 kb
Host smart-0484eaff-f57b-42a6-bfb9-ca4cf528c1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413505542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1413505542
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.3489011414
Short name T315
Test name
Test status
Simulation time 38035510 ps
CPU time 1.15 seconds
Started Jun 27 06:30:05 PM PDT 24
Finished Jun 27 06:30:10 PM PDT 24
Peak memory 220072 kb
Host smart-0e48911c-cf05-4d46-9dc0-a30123f9073a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489011414 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3489011414
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.2471014856
Short name T495
Test name
Test status
Simulation time 25657905 ps
CPU time 0.97 seconds
Started Jun 27 06:30:02 PM PDT 24
Finished Jun 27 06:30:07 PM PDT 24
Peak memory 207072 kb
Host smart-f05f5c08-5723-4cf9-b887-56ac37eb9531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471014856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2471014856
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.399129327
Short name T989
Test name
Test status
Simulation time 42228186 ps
CPU time 0.85 seconds
Started Jun 27 06:30:06 PM PDT 24
Finished Jun 27 06:30:11 PM PDT 24
Peak memory 216272 kb
Host smart-0966ec6e-8d39-4790-82a9-f23b8ba956cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399129327 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.399129327
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1764288960
Short name T958
Test name
Test status
Simulation time 61700660 ps
CPU time 0.99 seconds
Started Jun 27 06:30:04 PM PDT 24
Finished Jun 27 06:30:09 PM PDT 24
Peak memory 218584 kb
Host smart-b58e735c-54fd-4244-acff-b6a356c71f5c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764288960 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1764288960
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.2084080300
Short name T863
Test name
Test status
Simulation time 32385465 ps
CPU time 1.09 seconds
Started Jun 27 06:30:04 PM PDT 24
Finished Jun 27 06:30:10 PM PDT 24
Peak memory 218884 kb
Host smart-deecb8ee-744f-40ef-b9f0-16ebd5c1c4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084080300 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2084080300
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.671303168
Short name T587
Test name
Test status
Simulation time 63882061 ps
CPU time 1.35 seconds
Started Jun 27 06:30:04 PM PDT 24
Finished Jun 27 06:30:10 PM PDT 24
Peak memory 220184 kb
Host smart-37e30218-2e7d-4ff6-9398-b0b2b68dd7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671303168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.671303168
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.752352194
Short name T638
Test name
Test status
Simulation time 30330941 ps
CPU time 0.95 seconds
Started Jun 27 06:30:06 PM PDT 24
Finished Jun 27 06:30:12 PM PDT 24
Peak memory 215780 kb
Host smart-3866c237-4502-460f-b075-5a34de1d53d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752352194 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.752352194
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.4077161475
Short name T944
Test name
Test status
Simulation time 35429620 ps
CPU time 0.88 seconds
Started Jun 27 06:30:05 PM PDT 24
Finished Jun 27 06:30:11 PM PDT 24
Peak memory 215572 kb
Host smart-939fd3f9-d988-44e2-ab33-9899ac2364ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077161475 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.4077161475
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.4014893815
Short name T715
Test name
Test status
Simulation time 195228644 ps
CPU time 2.79 seconds
Started Jun 27 06:30:05 PM PDT 24
Finished Jun 27 06:30:12 PM PDT 24
Peak memory 217596 kb
Host smart-bb52d50d-ee63-4db7-8bb6-8ed5ce0910e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014893815 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.4014893815
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1368715154
Short name T821
Test name
Test status
Simulation time 73517860208 ps
CPU time 574.69 seconds
Started Jun 27 06:30:03 PM PDT 24
Finished Jun 27 06:39:43 PM PDT 24
Peak memory 219068 kb
Host smart-bb47ff50-4774-42ac-af1a-18c4717994be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368715154 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1368715154
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.1852182253
Short name T170
Test name
Test status
Simulation time 25633321 ps
CPU time 1.16 seconds
Started Jun 27 06:32:35 PM PDT 24
Finished Jun 27 06:32:41 PM PDT 24
Peak memory 221044 kb
Host smart-d89dbe9f-0d95-42e9-89b9-b0a790b8e40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852182253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.1852182253
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.4073670842
Short name T406
Test name
Test status
Simulation time 82708480 ps
CPU time 1.08 seconds
Started Jun 27 06:32:35 PM PDT 24
Finished Jun 27 06:32:40 PM PDT 24
Peak memory 217684 kb
Host smart-9e126f2c-ac47-4ad1-8c85-139a3aa68221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073670842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.4073670842
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.2968627765
Short name T525
Test name
Test status
Simulation time 148683990 ps
CPU time 2.08 seconds
Started Jun 27 06:32:32 PM PDT 24
Finished Jun 27 06:32:40 PM PDT 24
Peak memory 218956 kb
Host smart-4a839654-bbaf-4c5c-a2bc-e602ced2edaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968627765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2968627765
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3761383400
Short name T759
Test name
Test status
Simulation time 57072203 ps
CPU time 1.22 seconds
Started Jun 27 06:32:33 PM PDT 24
Finished Jun 27 06:32:39 PM PDT 24
Peak memory 215956 kb
Host smart-c8a5cdd8-b30d-46a5-8170-32329dd1d80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761383400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3761383400
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.746765627
Short name T472
Test name
Test status
Simulation time 33723428 ps
CPU time 1.29 seconds
Started Jun 27 06:32:33 PM PDT 24
Finished Jun 27 06:32:39 PM PDT 24
Peak memory 215532 kb
Host smart-18bfbbf0-c1ee-4550-9f1e-08f5dd6b3236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746765627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.746765627
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.61358553
Short name T306
Test name
Test status
Simulation time 119072614 ps
CPU time 1.24 seconds
Started Jun 27 06:32:32 PM PDT 24
Finished Jun 27 06:32:38 PM PDT 24
Peak memory 217676 kb
Host smart-8398790e-c215-4f4d-ae7e-48feea78cf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61358553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.61358553
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.644401169
Short name T904
Test name
Test status
Simulation time 141606003 ps
CPU time 1.18 seconds
Started Jun 27 06:32:31 PM PDT 24
Finished Jun 27 06:32:37 PM PDT 24
Peak memory 218740 kb
Host smart-2e8bf601-cf02-4ef9-b24c-933f2ea8f797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644401169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.644401169
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.2673890852
Short name T409
Test name
Test status
Simulation time 36586513 ps
CPU time 1.15 seconds
Started Jun 27 06:32:31 PM PDT 24
Finished Jun 27 06:32:37 PM PDT 24
Peak memory 218856 kb
Host smart-ed02afd5-8698-47e5-976a-30e852941a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673890852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2673890852
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.3432636460
Short name T180
Test name
Test status
Simulation time 125027812 ps
CPU time 1.22 seconds
Started Jun 27 06:32:23 PM PDT 24
Finished Jun 27 06:32:33 PM PDT 24
Peak memory 220016 kb
Host smart-d9fca8f9-e522-44f3-82a0-54f5e7c1159d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432636460 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.3432636460
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.1805316505
Short name T932
Test name
Test status
Simulation time 68906686 ps
CPU time 1.27 seconds
Started Jun 27 06:32:37 PM PDT 24
Finished Jun 27 06:32:43 PM PDT 24
Peak memory 219124 kb
Host smart-3b7238ca-9e40-4676-8a64-fe358f3d093f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805316505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1805316505
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.3713847870
Short name T549
Test name
Test status
Simulation time 52769836 ps
CPU time 1.23 seconds
Started Jun 27 06:32:31 PM PDT 24
Finished Jun 27 06:32:38 PM PDT 24
Peak memory 216008 kb
Host smart-9997795a-6607-429f-aa0f-2e31b41bcef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713847870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.3713847870
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.2753396132
Short name T955
Test name
Test status
Simulation time 63034688 ps
CPU time 1.35 seconds
Started Jun 27 06:32:31 PM PDT 24
Finished Jun 27 06:32:38 PM PDT 24
Peak memory 218800 kb
Host smart-218a9693-f17e-4daf-bd34-6b293fa53e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753396132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2753396132
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.1113966288
Short name T59
Test name
Test status
Simulation time 23938668 ps
CPU time 1.16 seconds
Started Jun 27 06:32:34 PM PDT 24
Finished Jun 27 06:32:39 PM PDT 24
Peak memory 216024 kb
Host smart-5add5004-1f0b-4cae-99fc-26d56e4ca2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113966288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1113966288
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.99295676
Short name T442
Test name
Test status
Simulation time 82351743 ps
CPU time 1.34 seconds
Started Jun 27 06:32:33 PM PDT 24
Finished Jun 27 06:32:40 PM PDT 24
Peak memory 218892 kb
Host smart-7d257c2c-11e3-4bbe-9841-6fd0d56d0121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99295676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.99295676
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.1294990375
Short name T986
Test name
Test status
Simulation time 31725320 ps
CPU time 1.2 seconds
Started Jun 27 06:32:34 PM PDT 24
Finished Jun 27 06:32:39 PM PDT 24
Peak memory 218776 kb
Host smart-4f01ec78-6291-42ad-bfab-629fc66c33f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294990375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1294990375
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.457936568
Short name T519
Test name
Test status
Simulation time 70410415 ps
CPU time 1.07 seconds
Started Jun 27 06:32:23 PM PDT 24
Finished Jun 27 06:32:33 PM PDT 24
Peak memory 217644 kb
Host smart-9c94361c-de17-4a32-88e6-20b5eb693eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457936568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.457936568
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.472278654
Short name T713
Test name
Test status
Simulation time 140646794 ps
CPU time 1.11 seconds
Started Jun 27 06:32:23 PM PDT 24
Finished Jun 27 06:32:33 PM PDT 24
Peak memory 220032 kb
Host smart-586b4d4c-428c-40b4-b670-c4efb9b7875b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472278654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.472278654
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.2114236391
Short name T380
Test name
Test status
Simulation time 40690076 ps
CPU time 1.36 seconds
Started Jun 27 06:32:32 PM PDT 24
Finished Jun 27 06:32:38 PM PDT 24
Peak memory 217672 kb
Host smart-c10d0bf5-d4cf-4d0e-a5ba-bccbd927fb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114236391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2114236391
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.3161532249
Short name T2
Test name
Test status
Simulation time 36565284 ps
CPU time 1.17 seconds
Started Jun 27 06:30:06 PM PDT 24
Finished Jun 27 06:30:12 PM PDT 24
Peak memory 221096 kb
Host smart-4454a1a3-c333-4461-95d8-ba7adc577a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161532249 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3161532249
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2770649888
Short name T723
Test name
Test status
Simulation time 10919236 ps
CPU time 0.83 seconds
Started Jun 27 06:30:07 PM PDT 24
Finished Jun 27 06:30:12 PM PDT 24
Peak memory 207108 kb
Host smart-23172960-015a-4c58-adbb-bdd22e68c681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770649888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2770649888
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.4227967889
Short name T972
Test name
Test status
Simulation time 106887627 ps
CPU time 1.13 seconds
Started Jun 27 06:30:06 PM PDT 24
Finished Jun 27 06:30:12 PM PDT 24
Peak memory 217124 kb
Host smart-fe53d133-7f0a-49dd-90cb-758c1c776569
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227967889 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.4227967889
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.2915435781
Short name T214
Test name
Test status
Simulation time 43171727 ps
CPU time 1.02 seconds
Started Jun 27 06:30:03 PM PDT 24
Finished Jun 27 06:30:08 PM PDT 24
Peak memory 224060 kb
Host smart-b066d047-2502-4961-9295-5025f99623d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915435781 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2915435781
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2857178453
Short name T918
Test name
Test status
Simulation time 43538489 ps
CPU time 1.48 seconds
Started Jun 27 06:30:04 PM PDT 24
Finished Jun 27 06:30:11 PM PDT 24
Peak memory 218840 kb
Host smart-55db43e3-d445-4e57-8cd7-c5de8f13e76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857178453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2857178453
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.651784939
Short name T469
Test name
Test status
Simulation time 20238060 ps
CPU time 1.08 seconds
Started Jun 27 06:30:07 PM PDT 24
Finished Jun 27 06:30:13 PM PDT 24
Peak memory 216188 kb
Host smart-df60dda8-3bf8-458b-8989-5490a551e62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651784939 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.651784939
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.3775065013
Short name T607
Test name
Test status
Simulation time 43460195 ps
CPU time 0.88 seconds
Started Jun 27 06:30:06 PM PDT 24
Finished Jun 27 06:30:11 PM PDT 24
Peak memory 215576 kb
Host smart-b0e91f58-3af2-421b-b5f7-4a2f616776c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775065013 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3775065013
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.996881704
Short name T33
Test name
Test status
Simulation time 76178490406 ps
CPU time 484.09 seconds
Started Jun 27 06:30:04 PM PDT 24
Finished Jun 27 06:38:13 PM PDT 24
Peak memory 219692 kb
Host smart-04364424-002a-4fec-a335-94cc206f040e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996881704 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.996881704
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.320148113
Short name T177
Test name
Test status
Simulation time 40933679 ps
CPU time 1.09 seconds
Started Jun 27 06:32:35 PM PDT 24
Finished Jun 27 06:32:40 PM PDT 24
Peak memory 219000 kb
Host smart-3555f650-7c73-4c01-85a6-e7cfcd6e9a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320148113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.320148113
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.467188465
Short name T893
Test name
Test status
Simulation time 35611291 ps
CPU time 1.41 seconds
Started Jun 27 06:32:25 PM PDT 24
Finished Jun 27 06:32:34 PM PDT 24
Peak memory 217580 kb
Host smart-6e458b00-a9ca-42ab-b061-ca7b5a2e3e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467188465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.467188465
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.317252253
Short name T490
Test name
Test status
Simulation time 87028244 ps
CPU time 1.39 seconds
Started Jun 27 06:32:35 PM PDT 24
Finished Jun 27 06:32:41 PM PDT 24
Peak memory 218980 kb
Host smart-908c84f9-b8ed-4394-9c21-b89aa446e77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317252253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.317252253
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.3348472005
Short name T924
Test name
Test status
Simulation time 64604047 ps
CPU time 1.97 seconds
Started Jun 27 06:32:36 PM PDT 24
Finished Jun 27 06:32:43 PM PDT 24
Peak memory 220488 kb
Host smart-e1abe589-3ed8-413a-989f-65b63f571703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348472005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3348472005
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.2593907908
Short name T839
Test name
Test status
Simulation time 68846389 ps
CPU time 1.21 seconds
Started Jun 27 06:32:33 PM PDT 24
Finished Jun 27 06:32:39 PM PDT 24
Peak memory 220280 kb
Host smart-5c00b21a-aaac-4bb1-bdbb-9d5ba94e3c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593907908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2593907908
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.78523480
Short name T544
Test name
Test status
Simulation time 53056412 ps
CPU time 1.21 seconds
Started Jun 27 06:32:33 PM PDT 24
Finished Jun 27 06:32:39 PM PDT 24
Peak memory 220552 kb
Host smart-b714be4d-22b8-4323-90da-46fdcb13949f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78523480 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.78523480
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.1524245586
Short name T800
Test name
Test status
Simulation time 148346548 ps
CPU time 3.17 seconds
Started Jun 27 06:32:34 PM PDT 24
Finished Jun 27 06:32:42 PM PDT 24
Peak memory 219996 kb
Host smart-680ded18-ed24-427e-8939-69c3e48bfed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524245586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1524245586
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.3724006984
Short name T80
Test name
Test status
Simulation time 205126864 ps
CPU time 1.19 seconds
Started Jun 27 06:32:32 PM PDT 24
Finished Jun 27 06:32:38 PM PDT 24
Peak memory 219952 kb
Host smart-622a2792-a315-41d1-b0dc-761b62d97e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724006984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.3724006984
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.3693263067
Short name T861
Test name
Test status
Simulation time 4011339546 ps
CPU time 82.72 seconds
Started Jun 27 06:32:33 PM PDT 24
Finished Jun 27 06:34:01 PM PDT 24
Peak memory 220224 kb
Host smart-7e6d2183-a6d5-4a41-b3bf-671cd28e72bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693263067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3693263067
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.4116346460
Short name T668
Test name
Test status
Simulation time 33097258 ps
CPU time 1.19 seconds
Started Jun 27 06:32:24 PM PDT 24
Finished Jun 27 06:32:34 PM PDT 24
Peak memory 219928 kb
Host smart-0b2a3c28-7744-4454-9351-981a2886afff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116346460 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.4116346460
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.3054563383
Short name T331
Test name
Test status
Simulation time 70386738 ps
CPU time 1.77 seconds
Started Jun 27 06:32:35 PM PDT 24
Finished Jun 27 06:32:41 PM PDT 24
Peak memory 220288 kb
Host smart-9630fce8-2c54-48e3-ba6e-0c1cb79311e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054563383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3054563383
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.1814186983
Short name T302
Test name
Test status
Simulation time 97187877 ps
CPU time 1.14 seconds
Started Jun 27 06:32:34 PM PDT 24
Finished Jun 27 06:32:40 PM PDT 24
Peak memory 217576 kb
Host smart-437ea93e-0cce-43ba-b8bc-56c93dee2ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814186983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1814186983
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.2625922338
Short name T807
Test name
Test status
Simulation time 111305802 ps
CPU time 1.13 seconds
Started Jun 27 06:32:32 PM PDT 24
Finished Jun 27 06:32:39 PM PDT 24
Peak memory 220628 kb
Host smart-36b0edce-daec-4039-a283-b8f89d8c68bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625922338 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.2625922338
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.3215116491
Short name T568
Test name
Test status
Simulation time 34820592 ps
CPU time 1.35 seconds
Started Jun 27 06:32:36 PM PDT 24
Finished Jun 27 06:32:42 PM PDT 24
Peak memory 220020 kb
Host smart-167ec8d1-9527-44ee-8f1d-10d26dd0f14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215116491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3215116491
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.679237668
Short name T841
Test name
Test status
Simulation time 45500518 ps
CPU time 1.1 seconds
Started Jun 27 06:30:05 PM PDT 24
Finished Jun 27 06:30:11 PM PDT 24
Peak memory 219836 kb
Host smart-d11f2ff2-9d22-4a76-b070-7680a64b2946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679237668 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.679237668
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3983714981
Short name T831
Test name
Test status
Simulation time 20456563 ps
CPU time 0.82 seconds
Started Jun 27 06:30:05 PM PDT 24
Finished Jun 27 06:30:11 PM PDT 24
Peak memory 207024 kb
Host smart-ed75b28c-085d-41e2-8796-c21fe1621abd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983714981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3983714981
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.2806626416
Short name T850
Test name
Test status
Simulation time 40559613 ps
CPU time 0.9 seconds
Started Jun 27 06:30:03 PM PDT 24
Finished Jun 27 06:30:09 PM PDT 24
Peak memory 216524 kb
Host smart-3ab6768a-6f49-475b-a829-cd2f5b9cb58b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806626416 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2806626416
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.368409449
Short name T666
Test name
Test status
Simulation time 77357049 ps
CPU time 1.04 seconds
Started Jun 27 06:30:06 PM PDT 24
Finished Jun 27 06:30:12 PM PDT 24
Peak memory 218636 kb
Host smart-da2afad6-fa4f-4a0f-b02d-ae4c3c27f7fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368409449 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.368409449
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.4207341743
Short name T558
Test name
Test status
Simulation time 41375641 ps
CPU time 0.85 seconds
Started Jun 27 06:30:03 PM PDT 24
Finished Jun 27 06:30:08 PM PDT 24
Peak memory 218560 kb
Host smart-722b6e98-b6d6-40ed-9cfd-31f92e099b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207341743 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.4207341743
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1425950237
Short name T967
Test name
Test status
Simulation time 35096548 ps
CPU time 1.37 seconds
Started Jun 27 06:30:06 PM PDT 24
Finished Jun 27 06:30:12 PM PDT 24
Peak memory 218764 kb
Host smart-b505de2c-9adc-4488-aceb-94d5338e80d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425950237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1425950237
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.670162018
Short name T611
Test name
Test status
Simulation time 35791701 ps
CPU time 0.86 seconds
Started Jun 27 06:30:03 PM PDT 24
Finished Jun 27 06:30:09 PM PDT 24
Peak memory 215536 kb
Host smart-861b54fc-9ce1-46db-bb17-f6245a0246e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670162018 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.670162018
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2308859030
Short name T238
Test name
Test status
Simulation time 25785114 ps
CPU time 0.92 seconds
Started Jun 27 06:30:04 PM PDT 24
Finished Jun 27 06:30:10 PM PDT 24
Peak memory 215648 kb
Host smart-2f39021e-4a7b-41b8-9624-b8fb83982076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308859030 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2308859030
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3899477736
Short name T194
Test name
Test status
Simulation time 77137619 ps
CPU time 2.03 seconds
Started Jun 27 06:30:03 PM PDT 24
Finished Jun 27 06:30:10 PM PDT 24
Peak memory 215560 kb
Host smart-d0638e0a-03cb-4e8c-ac68-029c42bf9e68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899477736 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3899477736
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.4087781453
Short name T867
Test name
Test status
Simulation time 173030644276 ps
CPU time 290.11 seconds
Started Jun 27 06:30:04 PM PDT 24
Finished Jun 27 06:34:59 PM PDT 24
Peak memory 224164 kb
Host smart-f10acce0-add1-4a55-8d9c-bf0cfbf6e660
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087781453 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.4087781453
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.2694328524
Short name T425
Test name
Test status
Simulation time 42941620 ps
CPU time 1.14 seconds
Started Jun 27 06:32:34 PM PDT 24
Finished Jun 27 06:32:40 PM PDT 24
Peak memory 219716 kb
Host smart-36029740-3b1b-4a6a-b0f4-20d5fa590e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694328524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2694328524
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.1114393207
Short name T946
Test name
Test status
Simulation time 44133438 ps
CPU time 1.11 seconds
Started Jun 27 06:32:34 PM PDT 24
Finished Jun 27 06:32:40 PM PDT 24
Peak memory 217876 kb
Host smart-ebc882e9-7f24-4531-8670-fe54933fd614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114393207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1114393207
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.3326849513
Short name T60
Test name
Test status
Simulation time 23238367 ps
CPU time 1.11 seconds
Started Jun 27 06:32:31 PM PDT 24
Finished Jun 27 06:32:38 PM PDT 24
Peak memory 220332 kb
Host smart-d53ffff4-c536-4cff-8c1b-6dcd02eba5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326849513 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.3326849513
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.118589133
Short name T926
Test name
Test status
Simulation time 140141154 ps
CPU time 1.62 seconds
Started Jun 27 06:32:33 PM PDT 24
Finished Jun 27 06:32:40 PM PDT 24
Peak memory 218552 kb
Host smart-7eda8504-6a80-40a5-aead-c53bc262de84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118589133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.118589133
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.3043859897
Short name T262
Test name
Test status
Simulation time 30891543 ps
CPU time 1.24 seconds
Started Jun 27 06:32:35 PM PDT 24
Finished Jun 27 06:32:41 PM PDT 24
Peak memory 220704 kb
Host smart-1bc14a28-eede-40ac-916c-3131106a30bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043859897 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.3043859897
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.978749653
Short name T716
Test name
Test status
Simulation time 31498909 ps
CPU time 1.47 seconds
Started Jun 27 06:32:34 PM PDT 24
Finished Jun 27 06:32:40 PM PDT 24
Peak memory 218836 kb
Host smart-05a59738-be30-4531-b47a-07df0be7ad00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978749653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.978749653
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.2269958367
Short name T785
Test name
Test status
Simulation time 54806280 ps
CPU time 1.08 seconds
Started Jun 27 06:33:08 PM PDT 24
Finished Jun 27 06:33:11 PM PDT 24
Peak memory 221004 kb
Host smart-3ba087c7-386b-4eb5-a215-0835a2900471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269958367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.2269958367
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.4201364476
Short name T506
Test name
Test status
Simulation time 66913067 ps
CPU time 1.46 seconds
Started Jun 27 06:32:34 PM PDT 24
Finished Jun 27 06:32:40 PM PDT 24
Peak memory 218604 kb
Host smart-2ab4d52a-1292-4a09-969f-4b84cfd2e5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201364476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.4201364476
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.1843887429
Short name T298
Test name
Test status
Simulation time 29353702 ps
CPU time 1.34 seconds
Started Jun 27 06:32:41 PM PDT 24
Finished Jun 27 06:32:46 PM PDT 24
Peak memory 219780 kb
Host smart-94d9b84a-9500-492e-b039-9bc9a8eb872b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843887429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1843887429
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.4010120928
Short name T350
Test name
Test status
Simulation time 69281790 ps
CPU time 1.41 seconds
Started Jun 27 06:32:41 PM PDT 24
Finished Jun 27 06:32:46 PM PDT 24
Peak memory 218528 kb
Host smart-876f9500-1cb2-4f9a-ba0b-62a74c798d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010120928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.4010120928
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.3025147527
Short name T646
Test name
Test status
Simulation time 26748063 ps
CPU time 1.28 seconds
Started Jun 27 06:32:40 PM PDT 24
Finished Jun 27 06:32:45 PM PDT 24
Peak memory 219960 kb
Host smart-bfbd3583-14a9-4b6a-a078-3fc97ed1c735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025147527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3025147527
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.710769404
Short name T371
Test name
Test status
Simulation time 63304826 ps
CPU time 1.11 seconds
Started Jun 27 06:32:38 PM PDT 24
Finished Jun 27 06:32:43 PM PDT 24
Peak memory 218960 kb
Host smart-3a0ba9b3-8528-45e5-83a2-a712962d7fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710769404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.710769404
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.4259525272
Short name T954
Test name
Test status
Simulation time 49638506 ps
CPU time 1.15 seconds
Started Jun 27 06:32:38 PM PDT 24
Finished Jun 27 06:32:44 PM PDT 24
Peak memory 217660 kb
Host smart-83251f0f-fb9f-4121-b46b-a09ed25d82d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259525272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.4259525272
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1115300795
Short name T13
Test name
Test status
Simulation time 80740248 ps
CPU time 1.49 seconds
Started Jun 27 06:32:41 PM PDT 24
Finished Jun 27 06:32:46 PM PDT 24
Peak memory 215628 kb
Host smart-d20f5f87-af04-46fa-9d56-4a36f7338395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115300795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1115300795
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.572752803
Short name T743
Test name
Test status
Simulation time 22327419 ps
CPU time 1.13 seconds
Started Jun 27 06:32:37 PM PDT 24
Finished Jun 27 06:32:42 PM PDT 24
Peak memory 218804 kb
Host smart-eae870ff-dcca-449e-8425-5c7a503da5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572752803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.572752803
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/139.edn_alert.1091866453
Short name T317
Test name
Test status
Simulation time 27748236 ps
CPU time 1.21 seconds
Started Jun 27 06:32:40 PM PDT 24
Finished Jun 27 06:32:45 PM PDT 24
Peak memory 220672 kb
Host smart-045d5556-379b-46bc-a08a-782d687ac485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091866453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.1091866453
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert.2340184107
Short name T897
Test name
Test status
Simulation time 74330861 ps
CPU time 1.1 seconds
Started Jun 27 06:30:18 PM PDT 24
Finished Jun 27 06:30:21 PM PDT 24
Peak memory 219264 kb
Host smart-1bee5a89-f1c1-4b30-ab80-730ed1db1435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340184107 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2340184107
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.2886374681
Short name T588
Test name
Test status
Simulation time 32582241 ps
CPU time 0.87 seconds
Started Jun 27 06:30:21 PM PDT 24
Finished Jun 27 06:30:26 PM PDT 24
Peak memory 207144 kb
Host smart-4645c2fd-f079-4d2d-b162-f909ec89cd03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886374681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2886374681
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1974194022
Short name T242
Test name
Test status
Simulation time 50924178 ps
CPU time 1.51 seconds
Started Jun 27 06:30:19 PM PDT 24
Finished Jun 27 06:30:22 PM PDT 24
Peak memory 217216 kb
Host smart-309dd71a-da94-438d-bd96-afdf856595e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974194022 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1974194022
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.541657260
Short name T158
Test name
Test status
Simulation time 38769866 ps
CPU time 0.88 seconds
Started Jun 27 06:30:21 PM PDT 24
Finished Jun 27 06:30:25 PM PDT 24
Peak memory 218568 kb
Host smart-cba9b922-4346-4543-87fc-863871d0f2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541657260 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.541657260
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2108582313
Short name T883
Test name
Test status
Simulation time 140223074 ps
CPU time 2.08 seconds
Started Jun 27 06:30:06 PM PDT 24
Finished Jun 27 06:30:12 PM PDT 24
Peak memory 220304 kb
Host smart-db2e5792-65d6-41c5-8646-56997745d4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108582313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2108582313
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3788794257
Short name T835
Test name
Test status
Simulation time 38767174 ps
CPU time 1 seconds
Started Jun 27 06:30:18 PM PDT 24
Finished Jun 27 06:30:20 PM PDT 24
Peak memory 224108 kb
Host smart-671d4dd1-fa53-45e6-a8ef-34e884baf2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788794257 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3788794257
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.302167284
Short name T579
Test name
Test status
Simulation time 13891695 ps
CPU time 0.96 seconds
Started Jun 27 06:30:04 PM PDT 24
Finished Jun 27 06:30:10 PM PDT 24
Peak memory 215620 kb
Host smart-65d7f735-e1f6-4446-a8b5-7fab055edab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302167284 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.302167284
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2840752620
Short name T43
Test name
Test status
Simulation time 226396140 ps
CPU time 2.77 seconds
Started Jun 27 06:30:06 PM PDT 24
Finished Jun 27 06:30:13 PM PDT 24
Peak memory 215576 kb
Host smart-71b24734-e821-40ed-b385-dde84f8b0c36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840752620 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2840752620
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.379016298
Short name T985
Test name
Test status
Simulation time 7353473536 ps
CPU time 164.23 seconds
Started Jun 27 06:30:05 PM PDT 24
Finished Jun 27 06:32:54 PM PDT 24
Peak memory 217456 kb
Host smart-136b6c1b-6957-408a-bc0b-308cbfeb5f2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379016298 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.379016298
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.809084341
Short name T720
Test name
Test status
Simulation time 60124395 ps
CPU time 1.16 seconds
Started Jun 27 06:32:40 PM PDT 24
Finished Jun 27 06:32:45 PM PDT 24
Peak memory 219116 kb
Host smart-a129e92a-2708-4a09-a3d3-b4cf0d31728a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809084341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.809084341
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.3331251689
Short name T552
Test name
Test status
Simulation time 77280613 ps
CPU time 1.56 seconds
Started Jun 27 06:32:41 PM PDT 24
Finished Jun 27 06:32:46 PM PDT 24
Peak memory 218924 kb
Host smart-84039735-2128-4672-8dd9-f75d22150ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331251689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3331251689
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.3110557724
Short name T736
Test name
Test status
Simulation time 62539256 ps
CPU time 1.07 seconds
Started Jun 27 06:32:39 PM PDT 24
Finished Jun 27 06:32:45 PM PDT 24
Peak memory 220148 kb
Host smart-c97fa026-bcbc-43e7-8480-a97f195214ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110557724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3110557724
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.4063607670
Short name T393
Test name
Test status
Simulation time 67012196 ps
CPU time 1.17 seconds
Started Jun 27 06:32:42 PM PDT 24
Finished Jun 27 06:32:46 PM PDT 24
Peak memory 218776 kb
Host smart-88b1e64b-8a5e-4fa6-9820-f0a27cf37bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063607670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.4063607670
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.1922849888
Short name T216
Test name
Test status
Simulation time 81656323 ps
CPU time 1.13 seconds
Started Jun 27 06:32:40 PM PDT 24
Finished Jun 27 06:32:45 PM PDT 24
Peak memory 219536 kb
Host smart-0fd40b8c-4421-4847-8adf-dc2235a78a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922849888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1922849888
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.1112333760
Short name T753
Test name
Test status
Simulation time 38902861 ps
CPU time 1.62 seconds
Started Jun 27 06:32:39 PM PDT 24
Finished Jun 27 06:32:44 PM PDT 24
Peak memory 218816 kb
Host smart-de6af21e-e0bc-467d-9eb4-155647a37f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112333760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1112333760
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.438255867
Short name T739
Test name
Test status
Simulation time 25116415 ps
CPU time 1.16 seconds
Started Jun 27 06:32:37 PM PDT 24
Finished Jun 27 06:32:42 PM PDT 24
Peak memory 217692 kb
Host smart-b6553782-d1ac-485d-8bb9-041dc6ad7d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438255867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.438255867
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.4221039044
Short name T862
Test name
Test status
Simulation time 29091239 ps
CPU time 1.24 seconds
Started Jun 27 06:32:39 PM PDT 24
Finished Jun 27 06:32:45 PM PDT 24
Peak memory 218816 kb
Host smart-54f9b9bc-dbdd-4671-9c53-f3e14ea9cf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221039044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.4221039044
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.928246730
Short name T271
Test name
Test status
Simulation time 131879996 ps
CPU time 1.64 seconds
Started Jun 27 06:32:38 PM PDT 24
Finished Jun 27 06:32:44 PM PDT 24
Peak memory 220408 kb
Host smart-01367029-5678-45b8-b99b-c74b7b7a18b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928246730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.928246730
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.1408963909
Short name T765
Test name
Test status
Simulation time 76373687 ps
CPU time 1.19 seconds
Started Jun 27 06:32:41 PM PDT 24
Finished Jun 27 06:32:46 PM PDT 24
Peak memory 220144 kb
Host smart-0e2a21bb-b626-4e8a-8ebe-8f32eb006c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408963909 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.1408963909
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2389590241
Short name T824
Test name
Test status
Simulation time 96857164 ps
CPU time 1.32 seconds
Started Jun 27 06:32:42 PM PDT 24
Finished Jun 27 06:32:46 PM PDT 24
Peak memory 218996 kb
Host smart-d47344a4-77c2-4749-8195-bb9bf80ad167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389590241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2389590241
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.2443096831
Short name T551
Test name
Test status
Simulation time 36419837 ps
CPU time 1.4 seconds
Started Jun 27 06:32:41 PM PDT 24
Finished Jun 27 06:32:46 PM PDT 24
Peak memory 219032 kb
Host smart-5f4337f3-5541-4444-b81c-4f0c1014faf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443096831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2443096831
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.3338813412
Short name T467
Test name
Test status
Simulation time 24159959 ps
CPU time 1.13 seconds
Started Jun 27 06:33:01 PM PDT 24
Finished Jun 27 06:33:05 PM PDT 24
Peak memory 221028 kb
Host smart-e6911da8-8a24-4108-965d-9c42dcd737b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338813412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.3338813412
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.897119986
Short name T481
Test name
Test status
Simulation time 32545511 ps
CPU time 1.25 seconds
Started Jun 27 06:32:57 PM PDT 24
Finished Jun 27 06:33:01 PM PDT 24
Peak memory 217576 kb
Host smart-dbf3535f-99e3-4b59-9070-8cbb0ef087fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897119986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.897119986
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.3042723881
Short name T164
Test name
Test status
Simulation time 125479979 ps
CPU time 1.04 seconds
Started Jun 27 06:33:02 PM PDT 24
Finished Jun 27 06:33:06 PM PDT 24
Peak memory 219816 kb
Host smart-e8a6b62f-8c25-4b20-b9b0-eeb7d5d5e6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042723881 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.3042723881
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.926194660
Short name T948
Test name
Test status
Simulation time 30665661 ps
CPU time 1.28 seconds
Started Jun 27 06:32:57 PM PDT 24
Finished Jun 27 06:33:00 PM PDT 24
Peak memory 217640 kb
Host smart-baaaf733-5599-4bf1-a550-ae90f58720c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926194660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.926194660
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.608162122
Short name T256
Test name
Test status
Simulation time 144472954 ps
CPU time 1.33 seconds
Started Jun 27 06:30:23 PM PDT 24
Finished Jun 27 06:30:28 PM PDT 24
Peak memory 220840 kb
Host smart-c35ec686-fdd7-4157-a0db-a8019c68ef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608162122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.608162122
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.917947273
Short name T604
Test name
Test status
Simulation time 38172205 ps
CPU time 0.95 seconds
Started Jun 27 06:30:22 PM PDT 24
Finished Jun 27 06:30:26 PM PDT 24
Peak memory 207048 kb
Host smart-78c4a283-cd7f-4aba-a030-5741896e89b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917947273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.917947273
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3179015979
Short name T799
Test name
Test status
Simulation time 13268460 ps
CPU time 0.91 seconds
Started Jun 27 06:30:19 PM PDT 24
Finished Jun 27 06:30:22 PM PDT 24
Peak memory 216828 kb
Host smart-b66f1b7f-c059-4a3c-a34b-a0a40a6e2897
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179015979 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3179015979
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.1403422805
Short name T590
Test name
Test status
Simulation time 23651111 ps
CPU time 0.93 seconds
Started Jun 27 06:30:19 PM PDT 24
Finished Jun 27 06:30:22 PM PDT 24
Peak memory 218832 kb
Host smart-f7601f45-e2b8-401a-83bb-c332d50c0eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403422805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1403422805
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1031775594
Short name T635
Test name
Test status
Simulation time 29102493 ps
CPU time 1.24 seconds
Started Jun 27 06:30:21 PM PDT 24
Finished Jun 27 06:30:26 PM PDT 24
Peak memory 217652 kb
Host smart-0e9d5c8c-be7d-4e91-83ef-d7c7f44d3f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031775594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1031775594
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.803542515
Short name T548
Test name
Test status
Simulation time 23509238 ps
CPU time 1.05 seconds
Started Jun 27 06:30:21 PM PDT 24
Finished Jun 27 06:30:25 PM PDT 24
Peak memory 215904 kb
Host smart-dadfb542-61bf-4adc-8c13-40e494417887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803542515 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.803542515
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.281296670
Short name T887
Test name
Test status
Simulation time 20674592 ps
CPU time 0.99 seconds
Started Jun 27 06:30:18 PM PDT 24
Finished Jun 27 06:30:20 PM PDT 24
Peak memory 215612 kb
Host smart-40cba2b8-d619-4eec-8c4e-6b083daaf71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281296670 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.281296670
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1244530469
Short name T494
Test name
Test status
Simulation time 837821256 ps
CPU time 3.91 seconds
Started Jun 27 06:30:19 PM PDT 24
Finished Jun 27 06:30:25 PM PDT 24
Peak memory 215544 kb
Host smart-ca00879d-327f-46f7-bcd9-2987c3cf68eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244530469 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1244530469
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.4287633833
Short name T417
Test name
Test status
Simulation time 31573708708 ps
CPU time 404.32 seconds
Started Jun 27 06:30:22 PM PDT 24
Finished Jun 27 06:37:10 PM PDT 24
Peak memory 218720 kb
Host smart-e9c3cc5f-2c2d-494c-88b7-d13baa72ab06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287633833 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.4287633833
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.848479511
Short name T103
Test name
Test status
Simulation time 59330570 ps
CPU time 1.26 seconds
Started Jun 27 06:32:56 PM PDT 24
Finished Jun 27 06:32:59 PM PDT 24
Peak memory 219732 kb
Host smart-56ad495b-3bc4-49dd-b98e-80e438ce2275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848479511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.848479511
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.2039616477
Short name T339
Test name
Test status
Simulation time 38441487 ps
CPU time 1.56 seconds
Started Jun 27 06:32:56 PM PDT 24
Finished Jun 27 06:32:59 PM PDT 24
Peak memory 218824 kb
Host smart-9fbf557f-ae13-4645-bc4d-4460a31b7669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039616477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2039616477
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.406816904
Short name T808
Test name
Test status
Simulation time 26663796 ps
CPU time 1.3 seconds
Started Jun 27 06:32:56 PM PDT 24
Finished Jun 27 06:32:59 PM PDT 24
Peak memory 219896 kb
Host smart-5db8ff81-37c3-4400-b698-f7ec00066382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406816904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.406816904
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.2004006055
Short name T304
Test name
Test status
Simulation time 120099314 ps
CPU time 1.52 seconds
Started Jun 27 06:32:57 PM PDT 24
Finished Jun 27 06:33:01 PM PDT 24
Peak memory 218932 kb
Host smart-774e7afe-d4cf-4f6c-a1da-0326096e16e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004006055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2004006055
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.4120690002
Short name T398
Test name
Test status
Simulation time 146908732 ps
CPU time 1.25 seconds
Started Jun 27 06:32:56 PM PDT 24
Finished Jun 27 06:32:59 PM PDT 24
Peak memory 215980 kb
Host smart-ec5734dc-2336-4960-9c9b-6d1fd6b8786f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120690002 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.4120690002
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.869874618
Short name T82
Test name
Test status
Simulation time 93388371 ps
CPU time 1.37 seconds
Started Jun 27 06:32:59 PM PDT 24
Finished Jun 27 06:33:04 PM PDT 24
Peak memory 220344 kb
Host smart-0b7956f3-1b55-46e5-875e-74aaa4ef62e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869874618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.869874618
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.3775126752
Short name T163
Test name
Test status
Simulation time 151059857 ps
CPU time 1.16 seconds
Started Jun 27 06:32:58 PM PDT 24
Finished Jun 27 06:33:02 PM PDT 24
Peak memory 219920 kb
Host smart-14460eea-d0c3-402d-9db9-1f39c0ddb88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775126752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.3775126752
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.1335015480
Short name T503
Test name
Test status
Simulation time 58237764 ps
CPU time 1.21 seconds
Started Jun 27 06:32:59 PM PDT 24
Finished Jun 27 06:33:03 PM PDT 24
Peak memory 219220 kb
Host smart-dfde98ac-a13e-45d8-99f4-7e7f15dde693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335015480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1335015480
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.2182406159
Short name T415
Test name
Test status
Simulation time 25403822 ps
CPU time 1.22 seconds
Started Jun 27 06:32:57 PM PDT 24
Finished Jun 27 06:33:01 PM PDT 24
Peak memory 221184 kb
Host smart-7518bece-80d3-42d6-84fd-2ce768417588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182406159 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.2182406159
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.2011753059
Short name T937
Test name
Test status
Simulation time 44265107 ps
CPU time 1.51 seconds
Started Jun 27 06:32:59 PM PDT 24
Finished Jun 27 06:33:04 PM PDT 24
Peak memory 215608 kb
Host smart-efad07b8-69cd-4d70-9634-27d5dcd7e663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011753059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2011753059
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.3860795586
Short name T263
Test name
Test status
Simulation time 106387327 ps
CPU time 1.22 seconds
Started Jun 27 06:32:56 PM PDT 24
Finished Jun 27 06:32:59 PM PDT 24
Peak memory 219080 kb
Host smart-2d5ad18a-93c7-4d85-b247-148822dbd083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860795586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.3860795586
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.815443696
Short name T779
Test name
Test status
Simulation time 75378028 ps
CPU time 1.17 seconds
Started Jun 27 06:32:58 PM PDT 24
Finished Jun 27 06:33:01 PM PDT 24
Peak memory 220352 kb
Host smart-b85c3d5d-ee5d-44f3-aaed-5c1879ab1e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815443696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.815443696
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.3590046193
Short name T454
Test name
Test status
Simulation time 75186746 ps
CPU time 1.22 seconds
Started Jun 27 06:33:00 PM PDT 24
Finished Jun 27 06:33:04 PM PDT 24
Peak memory 219956 kb
Host smart-eca3d248-54bb-46f2-86e2-c6f2368a404b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590046193 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.3590046193
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.2990836103
Short name T909
Test name
Test status
Simulation time 32343224 ps
CPU time 1.34 seconds
Started Jun 27 06:32:59 PM PDT 24
Finished Jun 27 06:33:04 PM PDT 24
Peak memory 220208 kb
Host smart-686ce1c2-c2b5-4fb7-85b7-236b03c8a751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990836103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2990836103
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.751948040
Short name T770
Test name
Test status
Simulation time 28121440 ps
CPU time 1.46 seconds
Started Jun 27 06:32:58 PM PDT 24
Finished Jun 27 06:33:03 PM PDT 24
Peak memory 219028 kb
Host smart-94e380dd-e375-4b1f-a2c0-3755810db118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751948040 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.751948040
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.170382980
Short name T691
Test name
Test status
Simulation time 46004945 ps
CPU time 1.14 seconds
Started Jun 27 06:32:55 PM PDT 24
Finished Jun 27 06:32:57 PM PDT 24
Peak memory 217508 kb
Host smart-ee1ec398-a30b-4a16-ae95-74d4d9cecc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170382980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.170382980
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.2321309175
Short name T547
Test name
Test status
Simulation time 50638248 ps
CPU time 1.25 seconds
Started Jun 27 06:32:58 PM PDT 24
Finished Jun 27 06:33:02 PM PDT 24
Peak memory 220756 kb
Host smart-7ee08393-ea3b-439c-b5f8-4ce57f8b57c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321309175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.2321309175
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.2590782331
Short name T719
Test name
Test status
Simulation time 49641356 ps
CPU time 1.36 seconds
Started Jun 27 06:33:02 PM PDT 24
Finished Jun 27 06:33:06 PM PDT 24
Peak memory 218852 kb
Host smart-4e7653fb-161f-476f-bb62-2b72ec7b9223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590782331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2590782331
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.884458048
Short name T761
Test name
Test status
Simulation time 49753911 ps
CPU time 1.2 seconds
Started Jun 27 06:32:58 PM PDT 24
Finished Jun 27 06:33:02 PM PDT 24
Peak memory 218916 kb
Host smart-2ecc988b-4184-40ab-95d4-4bc01fd022b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884458048 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.884458048
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.3563326005
Short name T396
Test name
Test status
Simulation time 50063870 ps
CPU time 1.85 seconds
Started Jun 27 06:32:58 PM PDT 24
Finished Jun 27 06:33:02 PM PDT 24
Peak memory 218808 kb
Host smart-3a90871e-b2bd-4bad-ab7d-35e5f11f4ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563326005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3563326005
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.801412588
Short name T623
Test name
Test status
Simulation time 107941789 ps
CPU time 1.18 seconds
Started Jun 27 06:30:21 PM PDT 24
Finished Jun 27 06:30:25 PM PDT 24
Peak memory 218888 kb
Host smart-7f75cacc-1216-46cf-b300-b8a775de19f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801412588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.801412588
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.855711503
Short name T407
Test name
Test status
Simulation time 32772404 ps
CPU time 1.19 seconds
Started Jun 27 06:30:19 PM PDT 24
Finished Jun 27 06:30:22 PM PDT 24
Peak memory 207084 kb
Host smart-a9a64908-b516-41bd-9ca3-50106330b5fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855711503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.855711503
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.4110936195
Short name T51
Test name
Test status
Simulation time 29785126 ps
CPU time 0.87 seconds
Started Jun 27 06:30:20 PM PDT 24
Finished Jun 27 06:30:24 PM PDT 24
Peak memory 216512 kb
Host smart-d0e865d6-da4a-4a5b-ad79-9b5803a31515
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110936195 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.4110936195
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2665171462
Short name T576
Test name
Test status
Simulation time 32749432 ps
CPU time 1.28 seconds
Started Jun 27 06:30:18 PM PDT 24
Finished Jun 27 06:30:21 PM PDT 24
Peak memory 217236 kb
Host smart-114979f5-6858-427f-8071-d5720b392ab9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665171462 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2665171462
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3919732316
Short name T193
Test name
Test status
Simulation time 24319268 ps
CPU time 0.96 seconds
Started Jun 27 06:30:21 PM PDT 24
Finished Jun 27 06:30:25 PM PDT 24
Peak memory 219048 kb
Host smart-ff93c673-8c05-4ed7-9d1a-267c611873d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919732316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3919732316
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.1879141469
Short name T594
Test name
Test status
Simulation time 100261436 ps
CPU time 2.44 seconds
Started Jun 27 06:30:21 PM PDT 24
Finished Jun 27 06:30:27 PM PDT 24
Peak memory 218992 kb
Host smart-6629e852-bafc-4ea9-be15-a9ec6cbacc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879141469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1879141469
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3314096106
Short name T725
Test name
Test status
Simulation time 20754061 ps
CPU time 1.08 seconds
Started Jun 27 06:30:19 PM PDT 24
Finished Jun 27 06:30:23 PM PDT 24
Peak memory 215876 kb
Host smart-1a10e4c5-9299-43da-ba04-72941b0e2df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314096106 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3314096106
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.4261669
Short name T457
Test name
Test status
Simulation time 20971917 ps
CPU time 0.97 seconds
Started Jun 27 06:30:19 PM PDT 24
Finished Jun 27 06:30:23 PM PDT 24
Peak memory 215636 kb
Host smart-c2361793-7d65-4423-9739-da7ec0426f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261669 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.4261669
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1215384284
Short name T900
Test name
Test status
Simulation time 188817979 ps
CPU time 4.08 seconds
Started Jun 27 06:30:18 PM PDT 24
Finished Jun 27 06:30:23 PM PDT 24
Peak memory 215588 kb
Host smart-de0ba22d-78c1-4b12-ae2c-914fce7c8516
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215384284 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1215384284
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2177964624
Short name T608
Test name
Test status
Simulation time 179169668145 ps
CPU time 901.69 seconds
Started Jun 27 06:30:22 PM PDT 24
Finished Jun 27 06:45:27 PM PDT 24
Peak memory 222572 kb
Host smart-7db9a582-80e8-4afd-80eb-4ce9baa0a35d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177964624 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2177964624
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.3157755202
Short name T126
Test name
Test status
Simulation time 124782189 ps
CPU time 1.29 seconds
Started Jun 27 06:32:57 PM PDT 24
Finished Jun 27 06:33:00 PM PDT 24
Peak memory 215988 kb
Host smart-224af69f-ac6f-40c3-9bbc-24925a3dd7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157755202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3157755202
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.3369109478
Short name T819
Test name
Test status
Simulation time 139194798 ps
CPU time 1.7 seconds
Started Jun 27 06:32:55 PM PDT 24
Finished Jun 27 06:32:58 PM PDT 24
Peak memory 219388 kb
Host smart-4a543f7b-871a-419b-9a75-44399af5bafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369109478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3369109478
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.3997077352
Short name T931
Test name
Test status
Simulation time 23169931 ps
CPU time 1.18 seconds
Started Jun 27 06:32:59 PM PDT 24
Finished Jun 27 06:33:03 PM PDT 24
Peak memory 219844 kb
Host smart-b58afb86-215f-468c-b76c-14447deda21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997077352 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.3997077352
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.163076312
Short name T609
Test name
Test status
Simulation time 103561169 ps
CPU time 1.24 seconds
Started Jun 27 06:32:57 PM PDT 24
Finished Jun 27 06:33:01 PM PDT 24
Peak memory 217764 kb
Host smart-784f375d-ded8-42c5-a8a2-c3548e889b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163076312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.163076312
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.3619605299
Short name T963
Test name
Test status
Simulation time 47208135 ps
CPU time 1.26 seconds
Started Jun 27 06:32:58 PM PDT 24
Finished Jun 27 06:33:03 PM PDT 24
Peak memory 220504 kb
Host smart-8ef68853-1b21-483a-a300-c27b4f0620c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619605299 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.3619605299
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.2266026076
Short name T379
Test name
Test status
Simulation time 83354561 ps
CPU time 1.4 seconds
Started Jun 27 06:33:00 PM PDT 24
Finished Jun 27 06:33:05 PM PDT 24
Peak memory 219340 kb
Host smart-4b7f7b08-80db-46f3-b70d-68db1a61a3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266026076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2266026076
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.1934179068
Short name T118
Test name
Test status
Simulation time 113952311 ps
CPU time 1.26 seconds
Started Jun 27 06:32:58 PM PDT 24
Finished Jun 27 06:33:01 PM PDT 24
Peak memory 219084 kb
Host smart-eedd643e-e757-4111-b0ae-144e7a0cf7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934179068 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1934179068
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.2927582099
Short name T817
Test name
Test status
Simulation time 80932448 ps
CPU time 1.37 seconds
Started Jun 27 06:32:59 PM PDT 24
Finished Jun 27 06:33:03 PM PDT 24
Peak memory 217892 kb
Host smart-bf81c29c-39c4-4b88-b756-567cc5d98b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927582099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2927582099
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.958756072
Short name T217
Test name
Test status
Simulation time 68704338 ps
CPU time 1.32 seconds
Started Jun 27 06:33:01 PM PDT 24
Finished Jun 27 06:33:06 PM PDT 24
Peak memory 218904 kb
Host smart-34587424-832e-4cc8-9c16-85ed6662cb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958756072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.958756072
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.1840696284
Short name T340
Test name
Test status
Simulation time 27690012 ps
CPU time 1.28 seconds
Started Jun 27 06:32:57 PM PDT 24
Finished Jun 27 06:33:01 PM PDT 24
Peak memory 218600 kb
Host smart-8b3ec1e6-611a-4f52-a0c3-7c53f9a6f5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840696284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1840696284
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.1654873981
Short name T134
Test name
Test status
Simulation time 28269319 ps
CPU time 1.27 seconds
Started Jun 27 06:32:59 PM PDT 24
Finished Jun 27 06:33:03 PM PDT 24
Peak memory 221000 kb
Host smart-13482599-376d-4de2-9bfe-e8fde99dfab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654873981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.1654873981
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1495487295
Short name T901
Test name
Test status
Simulation time 112688511 ps
CPU time 1.07 seconds
Started Jun 27 06:32:53 PM PDT 24
Finished Jun 27 06:32:55 PM PDT 24
Peak memory 217512 kb
Host smart-80bf704e-7d82-4e52-9615-db5644bcd89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495487295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1495487295
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.4017715039
Short name T968
Test name
Test status
Simulation time 50700828 ps
CPU time 1.25 seconds
Started Jun 27 06:33:00 PM PDT 24
Finished Jun 27 06:33:04 PM PDT 24
Peak memory 216020 kb
Host smart-a190824c-f68c-417f-906d-9906a859386c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017715039 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.4017715039
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.1750121847
Short name T798
Test name
Test status
Simulation time 186572588 ps
CPU time 2.88 seconds
Started Jun 27 06:32:58 PM PDT 24
Finished Jun 27 06:33:03 PM PDT 24
Peak memory 220288 kb
Host smart-6f6ca0f7-1789-4f6b-8e49-1df5c0629abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750121847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1750121847
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1268548058
Short name T149
Test name
Test status
Simulation time 22991992 ps
CPU time 1.24 seconds
Started Jun 27 06:32:59 PM PDT 24
Finished Jun 27 06:33:03 PM PDT 24
Peak memory 218844 kb
Host smart-274c8101-a091-4b0e-9108-d066373ebb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268548058 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1268548058
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.1570571412
Short name T439
Test name
Test status
Simulation time 52330310 ps
CPU time 1.3 seconds
Started Jun 27 06:33:01 PM PDT 24
Finished Jun 27 06:33:06 PM PDT 24
Peak memory 219048 kb
Host smart-bbaed117-1a7a-475b-8de8-6b1c5fac84fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570571412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1570571412
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.2844894328
Short name T316
Test name
Test status
Simulation time 29690880 ps
CPU time 1.3 seconds
Started Jun 27 06:32:58 PM PDT 24
Finished Jun 27 06:33:02 PM PDT 24
Peak memory 220144 kb
Host smart-431d97cb-4f9d-4735-b5af-a3958fd5c1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844894328 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.2844894328
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.2682917504
Short name T836
Test name
Test status
Simulation time 31900611 ps
CPU time 1.3 seconds
Started Jun 27 06:32:59 PM PDT 24
Finished Jun 27 06:33:03 PM PDT 24
Peak memory 218720 kb
Host smart-1992f55a-14f3-4030-bca6-0e35f3a7219a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682917504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2682917504
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.3009442800
Short name T81
Test name
Test status
Simulation time 65008776 ps
CPU time 1.34 seconds
Started Jun 27 06:32:58 PM PDT 24
Finished Jun 27 06:33:03 PM PDT 24
Peak memory 219124 kb
Host smart-3b23c57b-dce5-4584-bc1a-bc82d37b4205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009442800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.3009442800
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.3054310995
Short name T763
Test name
Test status
Simulation time 99804917 ps
CPU time 1.21 seconds
Started Jun 27 06:32:59 PM PDT 24
Finished Jun 27 06:33:04 PM PDT 24
Peak memory 217528 kb
Host smart-8c484e06-a11b-4319-9400-465af1b93ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054310995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3054310995
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.654275819
Short name T221
Test name
Test status
Simulation time 27913267 ps
CPU time 1.28 seconds
Started Jun 27 06:30:20 PM PDT 24
Finished Jun 27 06:30:25 PM PDT 24
Peak memory 219184 kb
Host smart-ab370f79-6572-4f21-bec4-aa232de73ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654275819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.654275819
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.752498462
Short name T479
Test name
Test status
Simulation time 19374218 ps
CPU time 0.91 seconds
Started Jun 27 06:30:20 PM PDT 24
Finished Jun 27 06:30:23 PM PDT 24
Peak memory 207216 kb
Host smart-45f32b0f-65d6-438d-9fe3-7f9e97e02057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752498462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.752498462
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3853017506
Short name T672
Test name
Test status
Simulation time 33228489 ps
CPU time 0.89 seconds
Started Jun 27 06:30:22 PM PDT 24
Finished Jun 27 06:30:26 PM PDT 24
Peak memory 215772 kb
Host smart-9d3bdf7c-9b9f-4621-ad23-0a91c3661bf3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853017506 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3853017506
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.1342163649
Short name T528
Test name
Test status
Simulation time 33088519 ps
CPU time 0.96 seconds
Started Jun 27 06:30:19 PM PDT 24
Finished Jun 27 06:30:22 PM PDT 24
Peak memory 218964 kb
Host smart-cc2e22e3-9003-4a08-987e-05dc357b200b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342163649 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1342163649
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2946079353
Short name T405
Test name
Test status
Simulation time 164432555 ps
CPU time 1.27 seconds
Started Jun 27 06:30:20 PM PDT 24
Finished Jun 27 06:30:25 PM PDT 24
Peak memory 217828 kb
Host smart-b7c7bdcd-c50e-49a9-90fb-06e53777edac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946079353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2946079353
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3597464843
Short name T95
Test name
Test status
Simulation time 38086325 ps
CPU time 0.84 seconds
Started Jun 27 06:30:20 PM PDT 24
Finished Jun 27 06:30:23 PM PDT 24
Peak memory 215900 kb
Host smart-356b6b7e-99f2-4056-8a58-24208de7d184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597464843 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3597464843
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.4200168089
Short name T938
Test name
Test status
Simulation time 50167565 ps
CPU time 0.95 seconds
Started Jun 27 06:30:23 PM PDT 24
Finished Jun 27 06:30:28 PM PDT 24
Peak memory 215496 kb
Host smart-f8897295-1d83-467c-892d-481752fed03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200168089 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.4200168089
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.459421672
Short name T521
Test name
Test status
Simulation time 113782407 ps
CPU time 1.89 seconds
Started Jun 27 06:30:21 PM PDT 24
Finished Jun 27 06:30:26 PM PDT 24
Peak memory 218756 kb
Host smart-8deeb078-a85d-4ba5-9655-490985276a44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459421672 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.459421672
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.121569453
Short name T227
Test name
Test status
Simulation time 174693824419 ps
CPU time 1116.48 seconds
Started Jun 27 06:30:23 PM PDT 24
Finished Jun 27 06:49:03 PM PDT 24
Peak memory 223408 kb
Host smart-651b6fef-221c-41a2-a3cd-f269bf50474b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121569453 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.121569453
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.2115011178
Short name T569
Test name
Test status
Simulation time 28262109 ps
CPU time 1.26 seconds
Started Jun 27 06:33:02 PM PDT 24
Finished Jun 27 06:33:06 PM PDT 24
Peak memory 221080 kb
Host smart-07e7021b-acff-4b6f-9b03-462836b318ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115011178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.2115011178
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.2744285528
Short name T847
Test name
Test status
Simulation time 49994938 ps
CPU time 1.28 seconds
Started Jun 27 06:33:00 PM PDT 24
Finished Jun 27 06:33:05 PM PDT 24
Peak memory 220128 kb
Host smart-0ada73ec-50cb-4c17-8e2c-9c67bdc0e9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744285528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2744285528
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.2990462726
Short name T914
Test name
Test status
Simulation time 27999496 ps
CPU time 1.25 seconds
Started Jun 27 06:32:57 PM PDT 24
Finished Jun 27 06:33:01 PM PDT 24
Peak memory 220432 kb
Host smart-ec6f1680-540a-43ab-9f92-dc5a84bb176f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990462726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.2990462726
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.460019646
Short name T634
Test name
Test status
Simulation time 68788551 ps
CPU time 1.22 seconds
Started Jun 27 06:32:58 PM PDT 24
Finished Jun 27 06:33:03 PM PDT 24
Peak memory 219084 kb
Host smart-0f8fab07-4a61-469f-9985-00edaf20aaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460019646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.460019646
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1269074941
Short name T912
Test name
Test status
Simulation time 27088792 ps
CPU time 1.35 seconds
Started Jun 27 06:33:00 PM PDT 24
Finished Jun 27 06:33:05 PM PDT 24
Peak memory 218784 kb
Host smart-5f9553b9-b247-4068-8423-a9acd6869bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269074941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1269074941
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.1943078384
Short name T589
Test name
Test status
Simulation time 140500695 ps
CPU time 1.48 seconds
Started Jun 27 06:32:57 PM PDT 24
Finished Jun 27 06:33:01 PM PDT 24
Peak memory 220260 kb
Host smart-2588507d-bf14-43e6-8a07-77ecf0409b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943078384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1943078384
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.11981146
Short name T962
Test name
Test status
Simulation time 27777411 ps
CPU time 1.29 seconds
Started Jun 27 06:32:58 PM PDT 24
Finished Jun 27 06:33:02 PM PDT 24
Peak memory 218888 kb
Host smart-e349f35e-d2dc-4392-8a0f-93d2bd33f7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11981146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.11981146
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.3956069045
Short name T433
Test name
Test status
Simulation time 95488776 ps
CPU time 1.27 seconds
Started Jun 27 06:33:00 PM PDT 24
Finished Jun 27 06:33:05 PM PDT 24
Peak memory 218772 kb
Host smart-8556fdac-2d94-4050-b47b-d416ba345840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956069045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3956069045
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.894992738
Short name T133
Test name
Test status
Simulation time 69584981 ps
CPU time 1.24 seconds
Started Jun 27 06:32:58 PM PDT 24
Finished Jun 27 06:33:01 PM PDT 24
Peak memory 220060 kb
Host smart-e30e5722-168c-46c7-8976-022d52be39f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894992738 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.894992738
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.3979677099
Short name T600
Test name
Test status
Simulation time 45573792 ps
CPU time 1.25 seconds
Started Jun 27 06:32:59 PM PDT 24
Finished Jun 27 06:33:04 PM PDT 24
Peak memory 219060 kb
Host smart-58c377da-9273-465f-adcd-885660939ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979677099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3979677099
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.1106735266
Short name T624
Test name
Test status
Simulation time 244021810 ps
CPU time 1.32 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:24 PM PDT 24
Peak memory 218960 kb
Host smart-8aa392df-b3e6-44b0-abf5-26e6efc00e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106735266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.1106735266
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.970891173
Short name T369
Test name
Test status
Simulation time 58140571 ps
CPU time 2.29 seconds
Started Jun 27 06:33:00 PM PDT 24
Finished Jun 27 06:33:06 PM PDT 24
Peak memory 220544 kb
Host smart-96bbd746-7f94-4e55-99d1-9e8007c50696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970891173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.970891173
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.2927788760
Short name T426
Test name
Test status
Simulation time 93155332 ps
CPU time 1.17 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:24 PM PDT 24
Peak memory 218808 kb
Host smart-3a83af70-8e19-434f-b9b7-5d25b5074aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927788760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2927788760
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.2618074264
Short name T788
Test name
Test status
Simulation time 89726524 ps
CPU time 1.78 seconds
Started Jun 27 06:33:14 PM PDT 24
Finished Jun 27 06:33:17 PM PDT 24
Peak memory 220852 kb
Host smart-58f1a265-89d5-4e17-a70c-21b1cf7f3316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618074264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2618074264
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.1432613895
Short name T176
Test name
Test status
Simulation time 40546357 ps
CPU time 1.08 seconds
Started Jun 27 06:33:15 PM PDT 24
Finished Jun 27 06:33:17 PM PDT 24
Peak memory 218680 kb
Host smart-94d0b4e8-4e67-4d2a-b9fd-28ae86b92b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432613895 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.1432613895
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.4230962146
Short name T969
Test name
Test status
Simulation time 53328678 ps
CPU time 1.26 seconds
Started Jun 27 06:33:17 PM PDT 24
Finished Jun 27 06:33:19 PM PDT 24
Peak memory 220568 kb
Host smart-bdd0f5c6-41e6-4e66-b703-1cbd8b21ebdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230962146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.4230962146
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.877992896
Short name T844
Test name
Test status
Simulation time 55082461 ps
CPU time 1.28 seconds
Started Jun 27 06:33:19 PM PDT 24
Finished Jun 27 06:33:25 PM PDT 24
Peak memory 219776 kb
Host smart-8ec7e301-3ce3-405c-84b5-4ed0ed5092a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877992896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.877992896
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.3532058189
Short name T257
Test name
Test status
Simulation time 34628475 ps
CPU time 1.29 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:22 PM PDT 24
Peak memory 219716 kb
Host smart-befa0a82-829f-47ce-b17b-9a14e8bf05cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532058189 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3532058189
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.3214392274
Short name T669
Test name
Test status
Simulation time 57131179 ps
CPU time 1.36 seconds
Started Jun 27 06:33:13 PM PDT 24
Finished Jun 27 06:33:15 PM PDT 24
Peak memory 218724 kb
Host smart-41ef0331-3085-4bb8-a9f9-ff49527d7356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214392274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3214392274
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3897752322
Short name T218
Test name
Test status
Simulation time 219297437 ps
CPU time 1.35 seconds
Started Jun 27 06:30:36 PM PDT 24
Finished Jun 27 06:30:40 PM PDT 24
Peak memory 215984 kb
Host smart-ae79a826-22a9-461e-a999-5dc9d31b5b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897752322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3897752322
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_err.3675639100
Short name T111
Test name
Test status
Simulation time 20525376 ps
CPU time 1.28 seconds
Started Jun 27 06:30:33 PM PDT 24
Finished Jun 27 06:30:36 PM PDT 24
Peak memory 229936 kb
Host smart-0eca83f6-50b5-40c8-8ac3-efa37caa2040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675639100 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3675639100
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1015397753
Short name T413
Test name
Test status
Simulation time 66549750 ps
CPU time 1.06 seconds
Started Jun 27 06:30:19 PM PDT 24
Finished Jun 27 06:30:23 PM PDT 24
Peak memory 217556 kb
Host smart-f3387aa0-9e7c-4f9f-a8e4-53e7a327a205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015397753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1015397753
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2668102071
Short name T699
Test name
Test status
Simulation time 22726721 ps
CPU time 0.97 seconds
Started Jun 27 06:30:35 PM PDT 24
Finished Jun 27 06:30:38 PM PDT 24
Peak memory 216124 kb
Host smart-57aed5a2-8946-45bf-b9c4-f0cfbc289609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668102071 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2668102071
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1063642454
Short name T72
Test name
Test status
Simulation time 16114442 ps
CPU time 1 seconds
Started Jun 27 06:30:23 PM PDT 24
Finished Jun 27 06:30:28 PM PDT 24
Peak memory 207304 kb
Host smart-d735b92a-c272-4be9-afa3-1e2d520c143e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063642454 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1063642454
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3059867057
Short name T613
Test name
Test status
Simulation time 855049061 ps
CPU time 5.22 seconds
Started Jun 27 06:30:20 PM PDT 24
Finished Jun 27 06:30:28 PM PDT 24
Peak memory 215528 kb
Host smart-faf82bad-7019-42dc-8170-8dfaaea2f19b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059867057 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3059867057
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3153741319
Short name T226
Test name
Test status
Simulation time 77486964950 ps
CPU time 447.25 seconds
Started Jun 27 06:30:20 PM PDT 24
Finished Jun 27 06:37:51 PM PDT 24
Peak memory 223964 kb
Host smart-0161d9d0-6bea-49a3-b7dc-358cb510036a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153741319 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3153741319
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.2512639690
Short name T84
Test name
Test status
Simulation time 278410512 ps
CPU time 1.11 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:23 PM PDT 24
Peak memory 218732 kb
Host smart-0aa1f970-ea36-4e75-bee0-a6d95ffc8256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512639690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.2512639690
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.3784764298
Short name T606
Test name
Test status
Simulation time 2211214800 ps
CPU time 73.02 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:34:36 PM PDT 24
Peak memory 220588 kb
Host smart-cc8d4366-e875-45a7-b0fb-5bc0ab55d2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784764298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3784764298
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.3816616007
Short name T686
Test name
Test status
Simulation time 25972771 ps
CPU time 1.27 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:24 PM PDT 24
Peak memory 219712 kb
Host smart-96aa6594-90a9-4ec9-952e-80d14ac3b29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816616007 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.3816616007
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.324010347
Short name T348
Test name
Test status
Simulation time 119249083 ps
CPU time 2.56 seconds
Started Jun 27 06:33:14 PM PDT 24
Finished Jun 27 06:33:18 PM PDT 24
Peak memory 220504 kb
Host smart-9bc3d356-1579-4014-9059-fa603fd2725a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324010347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.324010347
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.2455727051
Short name T757
Test name
Test status
Simulation time 43860649 ps
CPU time 1.17 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:22 PM PDT 24
Peak memory 219036 kb
Host smart-fa2ae9d9-6248-455b-8f77-ba479d935d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455727051 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2455727051
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.1408051226
Short name T402
Test name
Test status
Simulation time 27937814 ps
CPU time 1.21 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:22 PM PDT 24
Peak memory 217560 kb
Host smart-800053b1-c442-4a19-b349-796fbbc4315d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408051226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1408051226
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.1338158951
Short name T585
Test name
Test status
Simulation time 21780584 ps
CPU time 1.14 seconds
Started Jun 27 06:33:15 PM PDT 24
Finished Jun 27 06:33:17 PM PDT 24
Peak memory 220192 kb
Host smart-02a65d84-ee4c-411b-a64b-c1ea8103f9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338158951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1338158951
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.2467736685
Short name T639
Test name
Test status
Simulation time 41230363 ps
CPU time 1.67 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:23 PM PDT 24
Peak memory 217476 kb
Host smart-2d553f35-e723-4685-975c-6b63e96b3879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467736685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2467736685
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.3298390415
Short name T571
Test name
Test status
Simulation time 34971961 ps
CPU time 1.32 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:22 PM PDT 24
Peak memory 215976 kb
Host smart-565a5806-cfec-4b71-881a-4c771cb5d903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298390415 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.3298390415
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.986151111
Short name T541
Test name
Test status
Simulation time 45059398 ps
CPU time 1.44 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:23 PM PDT 24
Peak memory 218664 kb
Host smart-cd9afb4a-9eb3-4a0c-9efa-6c2c9b00b612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986151111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.986151111
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.4029865078
Short name T265
Test name
Test status
Simulation time 136059683 ps
CPU time 1.1 seconds
Started Jun 27 06:33:16 PM PDT 24
Finished Jun 27 06:33:18 PM PDT 24
Peak memory 220496 kb
Host smart-a9c93584-41e2-4702-8421-c52db384775a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029865078 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.4029865078
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.3140011064
Short name T941
Test name
Test status
Simulation time 71814859 ps
CPU time 2.41 seconds
Started Jun 27 06:33:15 PM PDT 24
Finished Jun 27 06:33:18 PM PDT 24
Peak memory 220420 kb
Host smart-69fb6db4-34c3-4a61-ae28-300cf6ee99fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140011064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3140011064
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.2872270282
Short name T292
Test name
Test status
Simulation time 251562003 ps
CPU time 1.3 seconds
Started Jun 27 06:33:14 PM PDT 24
Finished Jun 27 06:33:16 PM PDT 24
Peak memory 218796 kb
Host smart-09e5a8fd-b6b4-43b9-b98a-e7d39989d2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872270282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2872270282
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.3964137272
Short name T796
Test name
Test status
Simulation time 43041368 ps
CPU time 1.23 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:22 PM PDT 24
Peak memory 219960 kb
Host smart-d38413b4-84e3-4847-a4a9-a94748f39694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964137272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3964137272
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.1012268729
Short name T429
Test name
Test status
Simulation time 22200157 ps
CPU time 1.12 seconds
Started Jun 27 06:33:17 PM PDT 24
Finished Jun 27 06:33:21 PM PDT 24
Peak memory 218996 kb
Host smart-89b25eb0-ceb9-44df-ad52-e80486905100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012268729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1012268729
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.1954844656
Short name T868
Test name
Test status
Simulation time 85055151 ps
CPU time 1.18 seconds
Started Jun 27 06:33:16 PM PDT 24
Finished Jun 27 06:33:18 PM PDT 24
Peak memory 217980 kb
Host smart-d66f224f-deec-4275-b561-a94255d220de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954844656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1954844656
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.2051546901
Short name T923
Test name
Test status
Simulation time 98086733 ps
CPU time 1.13 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:22 PM PDT 24
Peak memory 219268 kb
Host smart-b3fb32b2-ce69-473a-accb-a2607aa091c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051546901 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2051546901
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.3574653664
Short name T375
Test name
Test status
Simulation time 55316358 ps
CPU time 1.44 seconds
Started Jun 27 06:33:15 PM PDT 24
Finished Jun 27 06:33:18 PM PDT 24
Peak memory 218880 kb
Host smart-6cbf0977-e2af-4164-80ca-1fdfecd48f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574653664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3574653664
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.1369068311
Short name T837
Test name
Test status
Simulation time 35773497 ps
CPU time 1.17 seconds
Started Jun 27 06:33:19 PM PDT 24
Finished Jun 27 06:33:26 PM PDT 24
Peak memory 220000 kb
Host smart-3e32e081-b842-4a23-8b04-24e8483c81e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369068311 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.1369068311
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2178738845
Short name T793
Test name
Test status
Simulation time 69993699 ps
CPU time 1.08 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:22 PM PDT 24
Peak memory 219268 kb
Host smart-9e308d8e-daef-48f2-b012-b3dd7c3a89c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178738845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2178738845
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.4059944946
Short name T62
Test name
Test status
Simulation time 68447802 ps
CPU time 1.22 seconds
Started Jun 27 06:30:36 PM PDT 24
Finished Jun 27 06:30:40 PM PDT 24
Peak memory 220984 kb
Host smart-79539522-12b4-4b97-9d02-b505463fe494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059944946 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.4059944946
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2308628619
Short name T400
Test name
Test status
Simulation time 27068078 ps
CPU time 0.9 seconds
Started Jun 27 06:30:37 PM PDT 24
Finished Jun 27 06:30:41 PM PDT 24
Peak memory 207004 kb
Host smart-d6f715a4-363b-4120-ad45-20ac38a9cc08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308628619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2308628619
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1118472731
Short name T146
Test name
Test status
Simulation time 306516465 ps
CPU time 1.08 seconds
Started Jun 27 06:30:34 PM PDT 24
Finished Jun 27 06:30:37 PM PDT 24
Peak memory 217208 kb
Host smart-3249dd00-21e0-47db-8ef9-908c53d595e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118472731 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1118472731
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.881128638
Short name T208
Test name
Test status
Simulation time 33118857 ps
CPU time 1 seconds
Started Jun 27 06:30:36 PM PDT 24
Finished Jun 27 06:30:40 PM PDT 24
Peak memory 229656 kb
Host smart-bac518ca-8076-41a1-a215-7a36a97c6579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881128638 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.881128638
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2167411602
Short name T804
Test name
Test status
Simulation time 158317423 ps
CPU time 1.14 seconds
Started Jun 27 06:30:33 PM PDT 24
Finished Jun 27 06:30:35 PM PDT 24
Peak memory 217672 kb
Host smart-817b4bdc-a078-429a-a76f-62020103aa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167411602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2167411602
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1870811695
Short name T517
Test name
Test status
Simulation time 20989381 ps
CPU time 1.02 seconds
Started Jun 27 06:30:40 PM PDT 24
Finished Jun 27 06:30:44 PM PDT 24
Peak memory 216088 kb
Host smart-36e6b2e2-28b1-45d6-8b79-abf6dec19a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870811695 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1870811695
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3311636089
Short name T542
Test name
Test status
Simulation time 30654077 ps
CPU time 1 seconds
Started Jun 27 06:30:36 PM PDT 24
Finished Jun 27 06:30:41 PM PDT 24
Peak memory 215556 kb
Host smart-ccc04901-3c46-4c72-aadf-34405919e0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311636089 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3311636089
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.766239359
Short name T756
Test name
Test status
Simulation time 135918331 ps
CPU time 3.37 seconds
Started Jun 27 06:30:33 PM PDT 24
Finished Jun 27 06:30:39 PM PDT 24
Peak memory 217616 kb
Host smart-0083961d-a33b-411d-879f-abca2af6d38a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766239359 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.766239359
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.772484333
Short name T565
Test name
Test status
Simulation time 15095833671 ps
CPU time 337.04 seconds
Started Jun 27 06:30:36 PM PDT 24
Finished Jun 27 06:36:16 PM PDT 24
Peak memory 222372 kb
Host smart-6c7c9050-00ed-4b28-9357-ec8cdbf658ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772484333 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.772484333
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.231235261
Short name T449
Test name
Test status
Simulation time 35351740 ps
CPU time 1.07 seconds
Started Jun 27 06:33:19 PM PDT 24
Finished Jun 27 06:33:26 PM PDT 24
Peak memory 220300 kb
Host smart-11210d5f-f578-49f6-abc3-f9a912ff5f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231235261 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.231235261
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.1743830090
Short name T510
Test name
Test status
Simulation time 49758014 ps
CPU time 1.26 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:23 PM PDT 24
Peak memory 218892 kb
Host smart-37972c17-a42b-41b0-b158-d8465172c930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743830090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1743830090
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.1326037994
Short name T169
Test name
Test status
Simulation time 21656705 ps
CPU time 1.13 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:22 PM PDT 24
Peak memory 219980 kb
Host smart-57bdd2a2-7871-4f60-be0a-8dccea016841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326037994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.1326037994
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.916006782
Short name T363
Test name
Test status
Simulation time 23967417 ps
CPU time 1.13 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:22 PM PDT 24
Peak memory 217704 kb
Host smart-5b83ca8f-0123-475c-a008-4cf6a8f004f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916006782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.916006782
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.2150876641
Short name T487
Test name
Test status
Simulation time 42063813 ps
CPU time 1.18 seconds
Started Jun 27 06:33:17 PM PDT 24
Finished Jun 27 06:33:22 PM PDT 24
Peak memory 219860 kb
Host smart-fd49b04a-00a9-4056-b8ab-f49a5ca3698e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150876641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2150876641
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.3417910097
Short name T792
Test name
Test status
Simulation time 72086361 ps
CPU time 1.25 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:23 PM PDT 24
Peak memory 219136 kb
Host smart-a2772e63-0186-4aed-a100-ee9d8122780c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417910097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3417910097
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.2137010864
Short name T124
Test name
Test status
Simulation time 26551828 ps
CPU time 1.3 seconds
Started Jun 27 06:33:19 PM PDT 24
Finished Jun 27 06:33:26 PM PDT 24
Peak memory 220216 kb
Host smart-c24d8dea-11f4-49b4-92d3-008992b57165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137010864 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.2137010864
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.793742199
Short name T361
Test name
Test status
Simulation time 74583997 ps
CPU time 1.3 seconds
Started Jun 27 06:33:17 PM PDT 24
Finished Jun 27 06:33:21 PM PDT 24
Peak memory 218952 kb
Host smart-47cbd0a8-5970-45cd-bbbe-2f8e2016cb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793742199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.793742199
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.4267234650
Short name T98
Test name
Test status
Simulation time 49379095 ps
CPU time 1.15 seconds
Started Jun 27 06:33:17 PM PDT 24
Finished Jun 27 06:33:21 PM PDT 24
Peak memory 221184 kb
Host smart-d0652e31-b898-4912-bdc3-3ff7703ff8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267234650 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.4267234650
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.3397974299
Short name T461
Test name
Test status
Simulation time 86018835 ps
CPU time 1.87 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:23 PM PDT 24
Peak memory 217984 kb
Host smart-ce53f0d3-cd61-4902-a6df-1687978ba438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397974299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3397974299
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.565879044
Short name T642
Test name
Test status
Simulation time 24342663 ps
CPU time 1.18 seconds
Started Jun 27 06:33:19 PM PDT 24
Finished Jun 27 06:33:26 PM PDT 24
Peak memory 219908 kb
Host smart-b03915f5-355f-4093-b562-8dc6c7f5f7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565879044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.565879044
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.2634194736
Short name T270
Test name
Test status
Simulation time 95895124 ps
CPU time 1.29 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:24 PM PDT 24
Peak memory 219204 kb
Host smart-c93e9e75-6a0f-42af-9172-2eeae92d8344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634194736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2634194736
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.588288182
Short name T553
Test name
Test status
Simulation time 97784997 ps
CPU time 1.19 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:29 PM PDT 24
Peak memory 215932 kb
Host smart-dbc72f32-1c03-4592-91da-bfb24a1beb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588288182 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.588288182
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.2983922018
Short name T570
Test name
Test status
Simulation time 22184382 ps
CPU time 1.12 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:23 PM PDT 24
Peak memory 217644 kb
Host smart-f439d963-397b-483f-9d8a-c9aa024a138a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983922018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2983922018
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.2774598556
Short name T764
Test name
Test status
Simulation time 88598436 ps
CPU time 1.22 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:24 PM PDT 24
Peak memory 219740 kb
Host smart-93c5af71-45db-4775-a9b8-4a4a6fb0881d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774598556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.2774598556
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.1711346634
Short name T324
Test name
Test status
Simulation time 83287394 ps
CPU time 1.3 seconds
Started Jun 27 06:33:19 PM PDT 24
Finished Jun 27 06:33:26 PM PDT 24
Peak memory 217600 kb
Host smart-5a310252-6588-497c-8fcd-ee1ad131375b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711346634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1711346634
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.3769687328
Short name T780
Test name
Test status
Simulation time 29505613 ps
CPU time 1.22 seconds
Started Jun 27 06:33:22 PM PDT 24
Finished Jun 27 06:33:30 PM PDT 24
Peak memory 220144 kb
Host smart-da150e84-1813-4ba9-9361-c98209614124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769687328 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.3769687328
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.1232902413
Short name T984
Test name
Test status
Simulation time 93783317 ps
CPU time 1.14 seconds
Started Jun 27 06:33:19 PM PDT 24
Finished Jun 27 06:33:26 PM PDT 24
Peak memory 218972 kb
Host smart-19adf9f2-352d-4cff-8fd6-2341ac751649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232902413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1232902413
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.60248368
Short name T488
Test name
Test status
Simulation time 38230983 ps
CPU time 1.07 seconds
Started Jun 27 06:33:23 PM PDT 24
Finished Jun 27 06:33:31 PM PDT 24
Peak memory 218884 kb
Host smart-bdfea0dc-f185-43f1-a63f-4d70049804ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60248368 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.60248368
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert.2418704941
Short name T959
Test name
Test status
Simulation time 76440943 ps
CPU time 1.1 seconds
Started Jun 27 06:29:42 PM PDT 24
Finished Jun 27 06:29:46 PM PDT 24
Peak memory 218892 kb
Host smart-b551417d-a8d2-4f97-bc5b-c886043ddba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418704941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2418704941
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2279775099
Short name T754
Test name
Test status
Simulation time 18069116 ps
CPU time 1 seconds
Started Jun 27 06:29:43 PM PDT 24
Finished Jun 27 06:29:47 PM PDT 24
Peak memory 206976 kb
Host smart-708ed830-693e-43c3-8217-24c48f1f6efc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279775099 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2279775099
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3888333097
Short name T559
Test name
Test status
Simulation time 40487430 ps
CPU time 0.88 seconds
Started Jun 27 06:29:48 PM PDT 24
Finished Jun 27 06:29:57 PM PDT 24
Peak memory 216492 kb
Host smart-38f63679-f074-4e74-82ba-91625835635f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888333097 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3888333097
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2857992466
Short name T527
Test name
Test status
Simulation time 56032436 ps
CPU time 1.27 seconds
Started Jun 27 06:29:46 PM PDT 24
Finished Jun 27 06:29:53 PM PDT 24
Peak memory 217280 kb
Host smart-634b93d5-d36d-4b16-8663-54a2430db919
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857992466 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2857992466
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3707735193
Short name T675
Test name
Test status
Simulation time 24004031 ps
CPU time 1.15 seconds
Started Jun 27 06:29:46 PM PDT 24
Finished Jun 27 06:29:54 PM PDT 24
Peak memory 220348 kb
Host smart-acaba8ca-bd2d-42a4-b9a4-7535cc363267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707735193 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3707735193
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3575647621
Short name T247
Test name
Test status
Simulation time 33638141 ps
CPU time 1 seconds
Started Jun 27 06:29:45 PM PDT 24
Finished Jun 27 06:29:50 PM PDT 24
Peak memory 217808 kb
Host smart-f5800137-89de-49d3-9b8e-cdd30833f50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575647621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3575647621
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.982528640
Short name T254
Test name
Test status
Simulation time 38811234 ps
CPU time 0.98 seconds
Started Jun 27 06:29:42 PM PDT 24
Finished Jun 27 06:29:46 PM PDT 24
Peak memory 224060 kb
Host smart-1a87cc41-b93a-45e3-99e2-2cb344553385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982528640 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.982528640
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.644019417
Short name T17
Test name
Test status
Simulation time 237748802 ps
CPU time 4.12 seconds
Started Jun 27 06:29:44 PM PDT 24
Finished Jun 27 06:29:51 PM PDT 24
Peak memory 235568 kb
Host smart-2d2d13b1-00fb-4f11-87f1-e3d66ed4d59f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644019417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.644019417
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1552034454
Short name T870
Test name
Test status
Simulation time 29893121 ps
CPU time 0.95 seconds
Started Jun 27 06:29:41 PM PDT 24
Finished Jun 27 06:29:45 PM PDT 24
Peak memory 215584 kb
Host smart-8659b7f5-b6d5-4cd5-8bb0-621a0eb6878d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552034454 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1552034454
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2782765287
Short name T627
Test name
Test status
Simulation time 284765484 ps
CPU time 3.53 seconds
Started Jun 27 06:29:46 PM PDT 24
Finished Jun 27 06:29:57 PM PDT 24
Peak memory 215652 kb
Host smart-72fef28c-6cb7-4d4a-a899-4cfad80c0e6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782765287 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2782765287
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3025978906
Short name T486
Test name
Test status
Simulation time 15342476025 ps
CPU time 332.78 seconds
Started Jun 27 06:29:46 PM PDT 24
Finished Jun 27 06:35:25 PM PDT 24
Peak memory 223496 kb
Host smart-d3f9d090-2b89-4e4b-aceb-6009d3ad8a3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025978906 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3025978906
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.200780578
Short name T102
Test name
Test status
Simulation time 289804845 ps
CPU time 1.41 seconds
Started Jun 27 06:30:33 PM PDT 24
Finished Jun 27 06:30:37 PM PDT 24
Peak memory 219932 kb
Host smart-79a60594-29dc-4a01-881a-79be05556df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200780578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.200780578
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1299718228
Short name T663
Test name
Test status
Simulation time 43947740 ps
CPU time 0.86 seconds
Started Jun 27 06:30:34 PM PDT 24
Finished Jun 27 06:30:37 PM PDT 24
Peak memory 206996 kb
Host smart-9137bf6d-cb33-4dce-b2bc-30f40bfa19ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299718228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1299718228
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.291625420
Short name T266
Test name
Test status
Simulation time 18298496 ps
CPU time 0.87 seconds
Started Jun 27 06:30:33 PM PDT 24
Finished Jun 27 06:30:35 PM PDT 24
Peak memory 216288 kb
Host smart-4fc85304-28a7-4d6b-a7ab-8c275fad9c6b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291625420 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.291625420
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3425052576
Short name T706
Test name
Test status
Simulation time 301217654 ps
CPU time 1.21 seconds
Started Jun 27 06:30:34 PM PDT 24
Finished Jun 27 06:30:37 PM PDT 24
Peak memory 215896 kb
Host smart-7b5fcbfe-9de3-4686-9b53-e74a0468bd84
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425052576 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3425052576
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2790976530
Short name T160
Test name
Test status
Simulation time 44193684 ps
CPU time 1.21 seconds
Started Jun 27 06:30:34 PM PDT 24
Finished Jun 27 06:30:37 PM PDT 24
Peak memory 219932 kb
Host smart-d5d9f61f-51d4-4c93-9c17-6a6d01a56fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790976530 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2790976530
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.340153231
Short name T10
Test name
Test status
Simulation time 84591330 ps
CPU time 1.71 seconds
Started Jun 27 06:30:35 PM PDT 24
Finished Jun 27 06:30:40 PM PDT 24
Peak memory 219020 kb
Host smart-176454a6-dbc6-476d-b722-e9c35357ef73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340153231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.340153231
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.55942614
Short name T91
Test name
Test status
Simulation time 39247058 ps
CPU time 0.88 seconds
Started Jun 27 06:30:36 PM PDT 24
Finished Jun 27 06:30:40 PM PDT 24
Peak memory 216040 kb
Host smart-d93adefe-a182-464d-b957-0df815bcc748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55942614 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.55942614
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3906034626
Short name T853
Test name
Test status
Simulation time 22339761 ps
CPU time 0.96 seconds
Started Jun 27 06:30:36 PM PDT 24
Finished Jun 27 06:30:40 PM PDT 24
Peak memory 215572 kb
Host smart-d6acd83a-3dca-4bd2-b109-90ce8647081e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906034626 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3906034626
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.919821734
Short name T248
Test name
Test status
Simulation time 204842868 ps
CPU time 4.07 seconds
Started Jun 27 06:30:33 PM PDT 24
Finished Jun 27 06:30:38 PM PDT 24
Peak memory 217636 kb
Host smart-baef4985-75ed-4b29-af9e-4498fb4cd96b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919821734 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.919821734
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.622867956
Short name T228
Test name
Test status
Simulation time 133553810709 ps
CPU time 738.26 seconds
Started Jun 27 06:30:34 PM PDT 24
Finished Jun 27 06:42:54 PM PDT 24
Peak memory 221600 kb
Host smart-ad746d8c-9fe5-48ef-9e5e-c37fa3f5baa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622867956 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.622867956
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3379212568
Short name T319
Test name
Test status
Simulation time 47956720 ps
CPU time 1.18 seconds
Started Jun 27 06:33:23 PM PDT 24
Finished Jun 27 06:33:31 PM PDT 24
Peak memory 218932 kb
Host smart-fdaf6509-baa7-4c53-9d87-d9fb92edcbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379212568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3379212568
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.858714935
Short name T674
Test name
Test status
Simulation time 23120798 ps
CPU time 1.13 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:29 PM PDT 24
Peak memory 217616 kb
Host smart-7771a4db-d73f-489c-a3c1-a72a6a385eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858714935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.858714935
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1316645676
Short name T563
Test name
Test status
Simulation time 113349087 ps
CPU time 1.35 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:28 PM PDT 24
Peak memory 220376 kb
Host smart-7d91dc25-b38e-451f-b763-6f39f482273a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316645676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1316645676
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.419316641
Short name T802
Test name
Test status
Simulation time 25043922 ps
CPU time 1.36 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:30 PM PDT 24
Peak memory 219060 kb
Host smart-b4e8c396-d148-4994-a9b4-83725c20a06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419316641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.419316641
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1181790096
Short name T683
Test name
Test status
Simulation time 47834730 ps
CPU time 1.12 seconds
Started Jun 27 06:33:22 PM PDT 24
Finished Jun 27 06:33:30 PM PDT 24
Peak memory 217636 kb
Host smart-8da60ec0-9b74-4164-a4e1-13261819730c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181790096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1181790096
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3850001227
Short name T957
Test name
Test status
Simulation time 35603833 ps
CPU time 1.38 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:29 PM PDT 24
Peak memory 217748 kb
Host smart-a88a730a-9d56-43d9-b9c3-ac36923d124e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850001227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3850001227
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1710717220
Short name T476
Test name
Test status
Simulation time 208006695 ps
CPU time 1.72 seconds
Started Jun 27 06:33:22 PM PDT 24
Finished Jun 27 06:33:31 PM PDT 24
Peak memory 219308 kb
Host smart-7c5c90f7-13f7-42d3-8840-765cca278107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710717220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1710717220
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1274657002
Short name T555
Test name
Test status
Simulation time 43020434 ps
CPU time 1.35 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:29 PM PDT 24
Peak memory 219104 kb
Host smart-edcde4fe-9f59-494a-b771-eb7787af86d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274657002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1274657002
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2672337229
Short name T532
Test name
Test status
Simulation time 931521521 ps
CPU time 7.37 seconds
Started Jun 27 06:33:22 PM PDT 24
Finished Jun 27 06:33:36 PM PDT 24
Peak memory 219780 kb
Host smart-ecbe672c-222c-466d-b0e5-3ebb2b3a7dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672337229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2672337229
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3610507531
Short name T860
Test name
Test status
Simulation time 25584073 ps
CPU time 1.15 seconds
Started Jun 27 06:30:37 PM PDT 24
Finished Jun 27 06:30:41 PM PDT 24
Peak memory 218644 kb
Host smart-e0647a4b-9624-419a-a643-196f74241caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610507531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3610507531
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1019980069
Short name T69
Test name
Test status
Simulation time 21181432 ps
CPU time 0.87 seconds
Started Jun 27 06:30:35 PM PDT 24
Finished Jun 27 06:30:39 PM PDT 24
Peak memory 207016 kb
Host smart-dfbf1a01-6328-4a12-a0f8-af448d44fbbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019980069 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1019980069
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3218682886
Short name T213
Test name
Test status
Simulation time 21950050 ps
CPU time 0.87 seconds
Started Jun 27 06:30:39 PM PDT 24
Finished Jun 27 06:30:43 PM PDT 24
Peak memory 216564 kb
Host smart-9ca2e5f6-091f-458e-9e53-6a85df95bd08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218682886 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3218682886
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3207984330
Short name T441
Test name
Test status
Simulation time 32145376 ps
CPU time 1.25 seconds
Started Jun 27 06:30:36 PM PDT 24
Finished Jun 27 06:30:41 PM PDT 24
Peak memory 217076 kb
Host smart-63010868-e291-4120-9f46-a7fbf0005193
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207984330 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3207984330
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_genbits.1571492872
Short name T578
Test name
Test status
Simulation time 88022307 ps
CPU time 1.44 seconds
Started Jun 27 06:30:36 PM PDT 24
Finished Jun 27 06:30:41 PM PDT 24
Peak memory 217660 kb
Host smart-2ff281bb-f457-4ad2-b717-0eafdd8e261c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571492872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1571492872
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_smoke.3465096821
Short name T367
Test name
Test status
Simulation time 33806875 ps
CPU time 0.99 seconds
Started Jun 27 06:30:36 PM PDT 24
Finished Jun 27 06:30:40 PM PDT 24
Peak memory 215592 kb
Host smart-08f6e34a-1524-4eaf-bde3-cc39bb3ed43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465096821 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3465096821
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2328485388
Short name T735
Test name
Test status
Simulation time 350405128 ps
CPU time 1.58 seconds
Started Jun 27 06:30:35 PM PDT 24
Finished Jun 27 06:30:39 PM PDT 24
Peak memory 217704 kb
Host smart-c9cbbcf3-259e-4a2a-bdd0-5c4fd6601f98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328485388 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2328485388
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1705906274
Short name T622
Test name
Test status
Simulation time 51137787617 ps
CPU time 1126.63 seconds
Started Jun 27 06:30:37 PM PDT 24
Finished Jun 27 06:49:27 PM PDT 24
Peak memory 224020 kb
Host smart-24b6b4a5-0970-4524-8e8b-fc8312b0aa30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705906274 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1705906274
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.855077068
Short name T615
Test name
Test status
Simulation time 38233650 ps
CPU time 1.35 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:30 PM PDT 24
Peak memory 218988 kb
Host smart-5117a0fa-0157-47c3-ab1e-eaaae5222d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855077068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.855077068
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1273406648
Short name T514
Test name
Test status
Simulation time 53273158 ps
CPU time 1.64 seconds
Started Jun 27 06:33:22 PM PDT 24
Finished Jun 27 06:33:31 PM PDT 24
Peak memory 214944 kb
Host smart-e13173eb-ca94-4f0c-89cc-c4826a184488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273406648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1273406648
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.719748815
Short name T939
Test name
Test status
Simulation time 142203197 ps
CPU time 2.92 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:30 PM PDT 24
Peak memory 219264 kb
Host smart-3b38f4fb-bae1-4569-8ae3-b160eec246e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719748815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.719748815
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.298360086
Short name T670
Test name
Test status
Simulation time 48314382 ps
CPU time 1.74 seconds
Started Jun 27 06:33:22 PM PDT 24
Finished Jun 27 06:33:31 PM PDT 24
Peak memory 218888 kb
Host smart-f954fd78-dcf3-47f0-8d57-d97dc5b26fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298360086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.298360086
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1458309427
Short name T832
Test name
Test status
Simulation time 26496853 ps
CPU time 1.12 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:29 PM PDT 24
Peak memory 220120 kb
Host smart-7d4a0b33-575f-4c8b-a1c2-16dac94683a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458309427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1458309427
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.826315903
Short name T466
Test name
Test status
Simulation time 59083494 ps
CPU time 1.26 seconds
Started Jun 27 06:33:22 PM PDT 24
Finished Jun 27 06:33:30 PM PDT 24
Peak memory 218944 kb
Host smart-ae254457-9cdc-4d6d-b68b-b45e7aa188a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826315903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.826315903
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.461579235
Short name T245
Test name
Test status
Simulation time 9182484423 ps
CPU time 127.39 seconds
Started Jun 27 06:33:20 PM PDT 24
Finished Jun 27 06:35:33 PM PDT 24
Peak memory 219292 kb
Host smart-13b41b81-c4af-4ae2-af61-ebb0e1757b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461579235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.461579235
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1327414670
Short name T629
Test name
Test status
Simulation time 134098831 ps
CPU time 1.03 seconds
Started Jun 27 06:33:19 PM PDT 24
Finished Jun 27 06:33:25 PM PDT 24
Peak memory 217560 kb
Host smart-88d165b3-4ead-4a48-84c6-457002e90efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327414670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1327414670
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1697955869
Short name T964
Test name
Test status
Simulation time 55078741 ps
CPU time 1.23 seconds
Started Jun 27 06:33:20 PM PDT 24
Finished Jun 27 06:33:28 PM PDT 24
Peak memory 220396 kb
Host smart-a74c4cbc-cc45-4b82-b3c7-cb37613d5fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697955869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1697955869
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.917710364
Short name T334
Test name
Test status
Simulation time 74687928 ps
CPU time 1.34 seconds
Started Jun 27 06:33:17 PM PDT 24
Finished Jun 27 06:33:22 PM PDT 24
Peak memory 218804 kb
Host smart-0e96a034-3222-4411-b032-3c8d2cfdec34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917710364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.917710364
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2506894245
Short name T557
Test name
Test status
Simulation time 145263368 ps
CPU time 1.29 seconds
Started Jun 27 06:30:35 PM PDT 24
Finished Jun 27 06:30:39 PM PDT 24
Peak memory 220028 kb
Host smart-a925a08e-81ba-4456-9e35-d491f1f4fae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506894245 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2506894245
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.386404396
Short name T478
Test name
Test status
Simulation time 59976070 ps
CPU time 0.87 seconds
Started Jun 27 06:30:51 PM PDT 24
Finished Jun 27 06:31:00 PM PDT 24
Peak memory 207020 kb
Host smart-a70fc691-2484-4216-88ec-00bc814a89b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386404396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.386404396
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3606689812
Short name T240
Test name
Test status
Simulation time 15260999 ps
CPU time 0.83 seconds
Started Jun 27 06:30:38 PM PDT 24
Finished Jun 27 06:30:42 PM PDT 24
Peak memory 216200 kb
Host smart-f91af826-4d17-4590-9b92-64ee686e8a28
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606689812 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3606689812
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.751106036
Short name T496
Test name
Test status
Simulation time 44116896 ps
CPU time 1 seconds
Started Jun 27 06:30:33 PM PDT 24
Finished Jun 27 06:30:36 PM PDT 24
Peak memory 218336 kb
Host smart-ef789f5d-de9e-4481-9932-02044c51741a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751106036 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_di
sable_auto_req_mode.751106036
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1682032015
Short name T48
Test name
Test status
Simulation time 70545901 ps
CPU time 1.14 seconds
Started Jun 27 06:30:34 PM PDT 24
Finished Jun 27 06:30:38 PM PDT 24
Peak memory 225764 kb
Host smart-3d63758d-3671-4eec-90e1-69377c40beb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682032015 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1682032015
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1196070574
Short name T384
Test name
Test status
Simulation time 107620204 ps
CPU time 1.18 seconds
Started Jun 27 06:30:36 PM PDT 24
Finished Jun 27 06:30:40 PM PDT 24
Peak memory 217560 kb
Host smart-4a4f4af1-4b75-42de-82c9-78afee4f492d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196070574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1196070574
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2848391449
Short name T930
Test name
Test status
Simulation time 28889055 ps
CPU time 1.08 seconds
Started Jun 27 06:30:36 PM PDT 24
Finished Jun 27 06:30:40 PM PDT 24
Peak memory 224332 kb
Host smart-8a772a72-c0be-4596-ba20-3cdf8157ee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848391449 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2848391449
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3375016869
Short name T474
Test name
Test status
Simulation time 15561640 ps
CPU time 0.99 seconds
Started Jun 27 06:30:37 PM PDT 24
Finished Jun 27 06:30:41 PM PDT 24
Peak memory 207352 kb
Host smart-4db87544-87e5-46f4-8897-5b401e0f3017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375016869 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3375016869
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1457328204
Short name T269
Test name
Test status
Simulation time 412210052 ps
CPU time 4.32 seconds
Started Jun 27 06:30:38 PM PDT 24
Finished Jun 27 06:30:46 PM PDT 24
Peak memory 217512 kb
Host smart-95ae9626-e7ed-4e73-9944-82f5f61032d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457328204 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1457328204
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.4222281611
Short name T237
Test name
Test status
Simulation time 83243711776 ps
CPU time 908.95 seconds
Started Jun 27 06:30:38 PM PDT 24
Finished Jun 27 06:45:50 PM PDT 24
Peak memory 223964 kb
Host smart-72580146-fa29-482b-ae29-b71b80b1be57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222281611 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.4222281611
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.634692003
Short name T697
Test name
Test status
Simulation time 85806119 ps
CPU time 1.27 seconds
Started Jun 27 06:33:22 PM PDT 24
Finished Jun 27 06:33:30 PM PDT 24
Peak memory 217652 kb
Host smart-dbde8305-c9ea-4d1e-8974-63b41a6ab54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634692003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.634692003
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.571824316
Short name T471
Test name
Test status
Simulation time 93078891 ps
CPU time 1.17 seconds
Started Jun 27 06:33:20 PM PDT 24
Finished Jun 27 06:33:28 PM PDT 24
Peak memory 219424 kb
Host smart-ceb028f8-2bfd-4e3f-a824-22adfc3d42d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571824316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.571824316
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3382392173
Short name T864
Test name
Test status
Simulation time 155823255 ps
CPU time 2.63 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:30 PM PDT 24
Peak memory 220380 kb
Host smart-5a2d6e5e-5580-496c-923f-58b4efac28a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382392173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3382392173
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3429864864
Short name T502
Test name
Test status
Simulation time 49656639 ps
CPU time 0.98 seconds
Started Jun 27 06:33:20 PM PDT 24
Finished Jun 27 06:33:27 PM PDT 24
Peak memory 217744 kb
Host smart-5ecdb947-a267-4a89-ae5d-5d611f174e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429864864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3429864864
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1920480775
Short name T320
Test name
Test status
Simulation time 56921995 ps
CPU time 1.33 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:28 PM PDT 24
Peak memory 218892 kb
Host smart-54a2e25b-2cf2-468b-a7fb-88c6ece3c67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920480775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1920480775
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.4095702779
Short name T771
Test name
Test status
Simulation time 78664707 ps
CPU time 1.48 seconds
Started Jun 27 06:33:19 PM PDT 24
Finished Jun 27 06:33:26 PM PDT 24
Peak memory 218852 kb
Host smart-cfac1562-9044-4277-ac09-4807424b838f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095702779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.4095702779
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1730806368
Short name T554
Test name
Test status
Simulation time 71127193 ps
CPU time 1.23 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:29 PM PDT 24
Peak memory 217540 kb
Host smart-e74a7310-1bba-46ed-be0c-cfac9131f0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730806368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1730806368
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.576320455
Short name T649
Test name
Test status
Simulation time 25486879 ps
CPU time 1.2 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:30:56 PM PDT 24
Peak memory 218976 kb
Host smart-2cadfd8d-1469-477c-8784-64eb743a5376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576320455 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.576320455
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.939687101
Short name T987
Test name
Test status
Simulation time 51013031 ps
CPU time 0.88 seconds
Started Jun 27 06:30:48 PM PDT 24
Finished Jun 27 06:30:53 PM PDT 24
Peak memory 206960 kb
Host smart-b05eccb7-4e34-476c-92b3-8f7bd443e39f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939687101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.939687101
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3863246044
Short name T685
Test name
Test status
Simulation time 10605724 ps
CPU time 0.81 seconds
Started Jun 27 06:30:51 PM PDT 24
Finished Jun 27 06:31:00 PM PDT 24
Peak memory 216640 kb
Host smart-1c4ffaa2-be1f-4351-b9e5-68e189749da0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863246044 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3863246044
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1553090997
Short name T70
Test name
Test status
Simulation time 38038665 ps
CPU time 1.08 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:30:56 PM PDT 24
Peak memory 217164 kb
Host smart-840d99b5-81b2-4362-9979-2945d988be3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553090997 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1553090997
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.370965252
Short name T357
Test name
Test status
Simulation time 32682089 ps
CPU time 0.88 seconds
Started Jun 27 06:30:51 PM PDT 24
Finished Jun 27 06:31:00 PM PDT 24
Peak memory 218536 kb
Host smart-d88de05f-3723-4d29-a0a6-443d320181fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370965252 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.370965252
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1681770318
Short name T321
Test name
Test status
Simulation time 70687298 ps
CPU time 1.17 seconds
Started Jun 27 06:30:48 PM PDT 24
Finished Jun 27 06:30:53 PM PDT 24
Peak memory 220304 kb
Host smart-13f7f740-36e2-4371-9bd4-bebbcbe693b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681770318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1681770318
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2411321512
Short name T94
Test name
Test status
Simulation time 24713894 ps
CPU time 0.9 seconds
Started Jun 27 06:30:51 PM PDT 24
Finished Jun 27 06:30:59 PM PDT 24
Peak memory 215844 kb
Host smart-93d1b45e-6a48-41c3-a9c4-9017724039eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411321512 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2411321512
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2589288610
Short name T766
Test name
Test status
Simulation time 72956623 ps
CPU time 0.92 seconds
Started Jun 27 06:30:50 PM PDT 24
Finished Jun 27 06:30:58 PM PDT 24
Peak memory 215592 kb
Host smart-eb33c1c3-99f3-4071-9ecc-55763f3aed38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589288610 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2589288610
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2885773869
Short name T520
Test name
Test status
Simulation time 281825600 ps
CPU time 1.35 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:30:57 PM PDT 24
Peak memory 217472 kb
Host smart-5b76e7bc-f9db-4667-9549-41411d9a1cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885773869 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2885773869
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.995856074
Short name T922
Test name
Test status
Simulation time 184541140349 ps
CPU time 585.24 seconds
Started Jun 27 06:30:53 PM PDT 24
Finished Jun 27 06:40:48 PM PDT 24
Peak memory 220860 kb
Host smart-6444426c-1195-41d6-9835-3690c34e43c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995856074 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.995856074
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.76245698
Short name T377
Test name
Test status
Simulation time 44994008 ps
CPU time 1.67 seconds
Started Jun 27 06:33:19 PM PDT 24
Finished Jun 27 06:33:27 PM PDT 24
Peak memory 215628 kb
Host smart-458be763-f370-4198-bb24-77640cb5f14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76245698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.76245698
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2669495386
Short name T368
Test name
Test status
Simulation time 47699228 ps
CPU time 1.2 seconds
Started Jun 27 06:33:19 PM PDT 24
Finished Jun 27 06:33:24 PM PDT 24
Peak memory 220000 kb
Host smart-55b3316b-4efa-4159-a8f5-d008f23fad30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669495386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2669495386
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.4238160839
Short name T953
Test name
Test status
Simulation time 48423750 ps
CPU time 1.06 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:28 PM PDT 24
Peak memory 217772 kb
Host smart-e7f415b1-df1c-46c0-a21d-80e5ec3c0442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238160839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.4238160839
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3703656925
Short name T351
Test name
Test status
Simulation time 46536115 ps
CPU time 1.2 seconds
Started Jun 27 06:33:19 PM PDT 24
Finished Jun 27 06:33:26 PM PDT 24
Peak memory 220052 kb
Host smart-58d4582f-71e6-4614-8ae7-a7f6986c5911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703656925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3703656925
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.116488045
Short name T919
Test name
Test status
Simulation time 35117273 ps
CPU time 1.5 seconds
Started Jun 27 06:33:20 PM PDT 24
Finished Jun 27 06:33:28 PM PDT 24
Peak memory 219992 kb
Host smart-1ae28795-087d-4ccb-a8cd-9add49d4212c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116488045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.116488045
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2839486518
Short name T470
Test name
Test status
Simulation time 70661947 ps
CPU time 1.08 seconds
Started Jun 27 06:33:19 PM PDT 24
Finished Jun 27 06:33:26 PM PDT 24
Peak memory 217624 kb
Host smart-fad96ce1-ade3-4a24-be65-32dee7d7219d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839486518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2839486518
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3513364470
Short name T949
Test name
Test status
Simulation time 115261382 ps
CPU time 1.27 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:22 PM PDT 24
Peak memory 217696 kb
Host smart-3e3e3d33-ed36-4700-beb7-1aa68977f3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513364470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3513364470
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.231636840
Short name T854
Test name
Test status
Simulation time 83145534 ps
CPU time 1.49 seconds
Started Jun 27 06:33:19 PM PDT 24
Finished Jun 27 06:33:26 PM PDT 24
Peak memory 218748 kb
Host smart-4ee381c7-79db-4cbd-93bc-3de9c7849906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231636840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.231636840
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1856803895
Short name T423
Test name
Test status
Simulation time 104695949 ps
CPU time 1.16 seconds
Started Jun 27 06:33:18 PM PDT 24
Finished Jun 27 06:33:23 PM PDT 24
Peak memory 220372 kb
Host smart-f01a13f8-c2df-4011-9580-4bb1a3b0f662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856803895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1856803895
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2016766953
Short name T296
Test name
Test status
Simulation time 80230901 ps
CPU time 1.17 seconds
Started Jun 27 06:30:48 PM PDT 24
Finished Jun 27 06:30:54 PM PDT 24
Peak memory 219664 kb
Host smart-cafd1d89-628c-46aa-9ad8-ca0f8d63d535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016766953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2016766953
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3391760454
Short name T358
Test name
Test status
Simulation time 31089753 ps
CPU time 1.03 seconds
Started Jun 27 06:30:52 PM PDT 24
Finished Jun 27 06:31:02 PM PDT 24
Peak memory 206812 kb
Host smart-3e4805e3-1780-4319-9916-c43f49e08b1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391760454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3391760454
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2608404413
Short name T267
Test name
Test status
Simulation time 12319728 ps
CPU time 0.96 seconds
Started Jun 27 06:30:51 PM PDT 24
Finished Jun 27 06:30:59 PM PDT 24
Peak memory 216796 kb
Host smart-b574bb1d-3b54-412c-8b19-4b740ca912a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608404413 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2608404413
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.276617180
Short name T460
Test name
Test status
Simulation time 54741099 ps
CPU time 1.21 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:30:56 PM PDT 24
Peak memory 217216 kb
Host smart-6c528318-769a-4976-977e-23a3d931be82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276617180 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.276617180
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.774314635
Short name T727
Test name
Test status
Simulation time 19375749 ps
CPU time 1.16 seconds
Started Jun 27 06:30:52 PM PDT 24
Finished Jun 27 06:31:02 PM PDT 24
Peak memory 218896 kb
Host smart-b208a924-84a1-4f2e-bf73-e6374aebfd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774314635 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.774314635
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1009687389
Short name T533
Test name
Test status
Simulation time 72633894 ps
CPU time 1.59 seconds
Started Jun 27 06:30:50 PM PDT 24
Finished Jun 27 06:30:58 PM PDT 24
Peak memory 218800 kb
Host smart-6c70342e-1bf8-4262-8938-a9b0e45ab0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009687389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1009687389
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2465027066
Short name T895
Test name
Test status
Simulation time 21762961 ps
CPU time 1.13 seconds
Started Jun 27 06:30:50 PM PDT 24
Finished Jun 27 06:30:59 PM PDT 24
Peak memory 215812 kb
Host smart-fac07c24-d6f8-47ef-a06f-a2cfde80f7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465027066 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2465027066
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.4011438241
Short name T397
Test name
Test status
Simulation time 17084749 ps
CPU time 0.96 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:30:56 PM PDT 24
Peak memory 215600 kb
Host smart-7e731f3c-28dd-4713-8f9d-d1ff9affb41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011438241 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.4011438241
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1944566793
Short name T746
Test name
Test status
Simulation time 358422409 ps
CPU time 4.1 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:31:00 PM PDT 24
Peak memory 217368 kb
Host smart-7b68b0ab-30a8-44c7-9e2e-5cf5ab35f01a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944566793 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1944566793
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2371474494
Short name T981
Test name
Test status
Simulation time 292107697005 ps
CPU time 1622.08 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:57:57 PM PDT 24
Peak memory 227324 kb
Host smart-befb0b4f-c62d-4ec7-819a-bd954a0fd951
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371474494 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2371474494
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.723685403
Short name T443
Test name
Test status
Simulation time 128440910 ps
CPU time 2.31 seconds
Started Jun 27 06:33:19 PM PDT 24
Finished Jun 27 06:33:27 PM PDT 24
Peak memory 220224 kb
Host smart-6092aa8c-a673-4950-be0f-f2517f4f91fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723685403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.723685403
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1630310879
Short name T509
Test name
Test status
Simulation time 90133735 ps
CPU time 1.12 seconds
Started Jun 27 06:33:20 PM PDT 24
Finished Jun 27 06:33:27 PM PDT 24
Peak memory 218604 kb
Host smart-2ef76c37-5568-4da0-80c7-a3d7bb754cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630310879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1630310879
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2096569832
Short name T742
Test name
Test status
Simulation time 44742877 ps
CPU time 1.41 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:29 PM PDT 24
Peak memory 217556 kb
Host smart-4a46e75b-1f45-4814-bb58-8f8376d7ee30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096569832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2096569832
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2364005780
Short name T512
Test name
Test status
Simulation time 78812071 ps
CPU time 1.09 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:28 PM PDT 24
Peak memory 217484 kb
Host smart-7e4866ef-3aa6-4391-ad40-f0f5535bc32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364005780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2364005780
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1259890198
Short name T388
Test name
Test status
Simulation time 42480712 ps
CPU time 1.39 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:29 PM PDT 24
Peak memory 219576 kb
Host smart-73cd4909-2963-4ee5-9655-d97e786403cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259890198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1259890198
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2357283420
Short name T794
Test name
Test status
Simulation time 69992575 ps
CPU time 1.16 seconds
Started Jun 27 06:33:22 PM PDT 24
Finished Jun 27 06:33:30 PM PDT 24
Peak memory 217712 kb
Host smart-ed8ca8be-251e-4572-b8fb-76a711f97bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357283420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2357283420
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.141742838
Short name T814
Test name
Test status
Simulation time 23607446 ps
CPU time 1.34 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:29 PM PDT 24
Peak memory 217696 kb
Host smart-dedbddfd-b64a-4de3-9189-54e7f5dab2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141742838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.141742838
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3138949721
Short name T988
Test name
Test status
Simulation time 65673819 ps
CPU time 1.68 seconds
Started Jun 27 06:33:22 PM PDT 24
Finished Jun 27 06:33:31 PM PDT 24
Peak memory 218876 kb
Host smart-41a3a19a-92f2-4c79-8c51-158ad2267b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138949721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3138949721
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2119667744
Short name T680
Test name
Test status
Simulation time 76973647 ps
CPU time 1.15 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:29 PM PDT 24
Peak memory 217544 kb
Host smart-9756bddf-c1c1-46d5-90fe-36ff1e4a8737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119667744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2119667744
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.279967475
Short name T653
Test name
Test status
Simulation time 155916839 ps
CPU time 1.58 seconds
Started Jun 27 06:33:21 PM PDT 24
Finished Jun 27 06:33:29 PM PDT 24
Peak memory 219096 kb
Host smart-2a8cff91-e2d7-47a0-9316-9e3ff0a1e0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279967475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.279967475
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.960898857
Short name T159
Test name
Test status
Simulation time 85434339 ps
CPU time 1.19 seconds
Started Jun 27 06:30:52 PM PDT 24
Finished Jun 27 06:31:02 PM PDT 24
Peak memory 219032 kb
Host smart-ac86c2c9-7f12-41f7-9e8c-9b3d940b4560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960898857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.960898857
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2125355553
Short name T636
Test name
Test status
Simulation time 18879276 ps
CPU time 1.06 seconds
Started Jun 27 06:30:50 PM PDT 24
Finished Jun 27 06:30:58 PM PDT 24
Peak memory 207108 kb
Host smart-6e81cbc8-e145-4bdb-a7fe-c10f0ea33c17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125355553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2125355553
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3399961757
Short name T650
Test name
Test status
Simulation time 39156025 ps
CPU time 0.83 seconds
Started Jun 27 06:30:47 PM PDT 24
Finished Jun 27 06:30:49 PM PDT 24
Peak memory 216184 kb
Host smart-00aaee96-4522-49eb-a69c-24d47b09fd22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399961757 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3399961757
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3528521617
Short name T529
Test name
Test status
Simulation time 136980827 ps
CPU time 1.15 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:30:56 PM PDT 24
Peak memory 218924 kb
Host smart-7191fceb-f17f-4120-8e64-28d3fd2d4ff0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528521617 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3528521617
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.193981078
Short name T165
Test name
Test status
Simulation time 18191361 ps
CPU time 1.08 seconds
Started Jun 27 06:30:51 PM PDT 24
Finished Jun 27 06:30:59 PM PDT 24
Peak memory 218960 kb
Host smart-1daf107b-a583-45c8-b1fe-66b01134627a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193981078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.193981078
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2672829216
Short name T598
Test name
Test status
Simulation time 45423456 ps
CPU time 1.48 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:30:57 PM PDT 24
Peak memory 219092 kb
Host smart-4f85c0bf-79f4-4b29-a0fa-dd7620b91656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672829216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2672829216
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1596760634
Short name T395
Test name
Test status
Simulation time 37561588 ps
CPU time 0.93 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:30:55 PM PDT 24
Peak memory 215612 kb
Host smart-39902015-270d-48e3-85d2-e9da704d3616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596760634 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1596760634
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.760649060
Short name T698
Test name
Test status
Simulation time 18746652 ps
CPU time 1.02 seconds
Started Jun 27 06:30:51 PM PDT 24
Finished Jun 27 06:31:00 PM PDT 24
Peak memory 215612 kb
Host smart-71527c8f-8f34-419a-81b9-978da11159bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760649060 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.760649060
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.386340350
Short name T195
Test name
Test status
Simulation time 126138526 ps
CPU time 1.86 seconds
Started Jun 27 06:30:52 PM PDT 24
Finished Jun 27 06:31:02 PM PDT 24
Peak memory 215556 kb
Host smart-e2f80ed0-3aa5-494e-9260-9d3992de7777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386340350 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.386340350
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/250.edn_genbits.3346641814
Short name T667
Test name
Test status
Simulation time 41331112 ps
CPU time 1.21 seconds
Started Jun 27 06:33:37 PM PDT 24
Finished Jun 27 06:33:42 PM PDT 24
Peak memory 219708 kb
Host smart-9b05fc9c-07be-424b-a8d1-b9b8c2513156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346641814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3346641814
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2224847024
Short name T264
Test name
Test status
Simulation time 84250768 ps
CPU time 1.05 seconds
Started Jun 27 06:33:30 PM PDT 24
Finished Jun 27 06:33:34 PM PDT 24
Peak memory 217676 kb
Host smart-e5bca557-d5fa-443b-b9f3-c2f6c34f0c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224847024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2224847024
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.4239799395
Short name T752
Test name
Test status
Simulation time 139032802 ps
CPU time 1.2 seconds
Started Jun 27 06:33:32 PM PDT 24
Finished Jun 27 06:33:36 PM PDT 24
Peak memory 217800 kb
Host smart-cf726db1-674f-41bf-b8a4-cf9b8d5785ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239799395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.4239799395
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2752881022
Short name T641
Test name
Test status
Simulation time 40277152 ps
CPU time 1.36 seconds
Started Jun 27 06:33:32 PM PDT 24
Finished Jun 27 06:33:36 PM PDT 24
Peak memory 218768 kb
Host smart-f3752cf4-00af-49c8-98ce-ab1534bb88fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752881022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2752881022
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3385890033
Short name T419
Test name
Test status
Simulation time 116139792 ps
CPU time 2.47 seconds
Started Jun 27 06:33:33 PM PDT 24
Finished Jun 27 06:33:38 PM PDT 24
Peak memory 220228 kb
Host smart-0f647d9d-97b1-49c6-baaf-4a53cf496689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385890033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3385890033
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.306500356
Short name T465
Test name
Test status
Simulation time 180857090 ps
CPU time 1.86 seconds
Started Jun 27 06:33:32 PM PDT 24
Finished Jun 27 06:33:36 PM PDT 24
Peak memory 219016 kb
Host smart-1f2b9cb3-6436-4d62-b859-c93a6716f58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306500356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.306500356
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.563299338
Short name T328
Test name
Test status
Simulation time 40008771 ps
CPU time 1.11 seconds
Started Jun 27 06:33:31 PM PDT 24
Finished Jun 27 06:33:35 PM PDT 24
Peak memory 218888 kb
Host smart-a3e6dbca-7c64-42cf-b22c-b235657ac2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563299338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.563299338
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3432049120
Short name T537
Test name
Test status
Simulation time 174870495 ps
CPU time 1.83 seconds
Started Jun 27 06:33:31 PM PDT 24
Finished Jun 27 06:33:35 PM PDT 24
Peak memory 219336 kb
Host smart-99aa8151-6150-44cf-b8aa-1e58e7aca81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432049120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3432049120
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3879900526
Short name T888
Test name
Test status
Simulation time 46793420 ps
CPU time 1.2 seconds
Started Jun 27 06:30:52 PM PDT 24
Finished Jun 27 06:31:02 PM PDT 24
Peak memory 221180 kb
Host smart-ce56a7f6-b02f-4f36-85b8-f3c72604b341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879900526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3879900526
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.4151478605
Short name T833
Test name
Test status
Simulation time 28729849 ps
CPU time 0.84 seconds
Started Jun 27 06:30:54 PM PDT 24
Finished Jun 27 06:31:03 PM PDT 24
Peak memory 206892 kb
Host smart-41b6cf93-239f-4b50-bc4b-2f8b1a71c3ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151478605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.4151478605
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.4252278019
Short name T498
Test name
Test status
Simulation time 48367273 ps
CPU time 0.85 seconds
Started Jun 27 06:30:51 PM PDT 24
Finished Jun 27 06:31:01 PM PDT 24
Peak memory 216208 kb
Host smart-9a8e96e2-46f0-499f-aef1-6fcb95e10968
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252278019 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.4252278019
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1171230793
Short name T550
Test name
Test status
Simulation time 105609376 ps
CPU time 1.16 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:30:56 PM PDT 24
Peak memory 217104 kb
Host smart-e70fb6e3-168e-4741-bafd-58515edccc94
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171230793 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1171230793
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.4132378260
Short name T866
Test name
Test status
Simulation time 28870128 ps
CPU time 1.3 seconds
Started Jun 27 06:30:50 PM PDT 24
Finished Jun 27 06:30:59 PM PDT 24
Peak memory 225868 kb
Host smart-23ca886c-5b4c-45cd-8c8b-06ad44cd404b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132378260 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.4132378260
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2818482458
Short name T434
Test name
Test status
Simulation time 38126628 ps
CPU time 1.45 seconds
Started Jun 27 06:30:50 PM PDT 24
Finished Jun 27 06:30:59 PM PDT 24
Peak memory 218948 kb
Host smart-78d1db84-0d43-4706-ae3d-8b5efcf1ae4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818482458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2818482458
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_smoke.3121356757
Short name T917
Test name
Test status
Simulation time 49930032 ps
CPU time 0.93 seconds
Started Jun 27 06:30:50 PM PDT 24
Finished Jun 27 06:30:59 PM PDT 24
Peak memory 215612 kb
Host smart-1ab06673-6c31-4c29-aa4a-226e229ef166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121356757 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3121356757
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3610837017
Short name T991
Test name
Test status
Simulation time 386752440 ps
CPU time 4.11 seconds
Started Jun 27 06:30:51 PM PDT 24
Finished Jun 27 06:31:03 PM PDT 24
Peak memory 215600 kb
Host smart-8dc208c4-deee-4bca-a564-982df7d1ebdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610837017 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3610837017
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.906714513
Short name T601
Test name
Test status
Simulation time 28441276870 ps
CPU time 612.73 seconds
Started Jun 27 06:30:50 PM PDT 24
Finished Jun 27 06:41:11 PM PDT 24
Peak memory 217964 kb
Host smart-7a6040ab-c164-4162-99ca-653398e8d49f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906714513 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.906714513
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3948597290
Short name T584
Test name
Test status
Simulation time 47458124 ps
CPU time 1.63 seconds
Started Jun 27 06:33:31 PM PDT 24
Finished Jun 27 06:33:35 PM PDT 24
Peak memory 219040 kb
Host smart-7205ea0d-12e5-49a3-9760-a986ecfb4afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948597290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3948597290
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3722890861
Short name T679
Test name
Test status
Simulation time 53890762 ps
CPU time 1.44 seconds
Started Jun 27 06:33:36 PM PDT 24
Finished Jun 27 06:33:39 PM PDT 24
Peak memory 219192 kb
Host smart-49466d20-da5d-4db9-8a9a-7a444da67d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722890861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3722890861
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2309337484
Short name T100
Test name
Test status
Simulation time 117159859 ps
CPU time 1.63 seconds
Started Jun 27 06:33:34 PM PDT 24
Finished Jun 27 06:33:38 PM PDT 24
Peak memory 219468 kb
Host smart-647cfe9d-597a-4866-ab09-0f168f3f62fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309337484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2309337484
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.500112562
Short name T447
Test name
Test status
Simulation time 111794763 ps
CPU time 1.48 seconds
Started Jun 27 06:33:31 PM PDT 24
Finished Jun 27 06:33:35 PM PDT 24
Peak memory 219040 kb
Host smart-b476d123-2c0a-4430-830c-fa1498fa775b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500112562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.500112562
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.290752244
Short name T659
Test name
Test status
Simulation time 238895107 ps
CPU time 1.97 seconds
Started Jun 27 06:33:42 PM PDT 24
Finished Jun 27 06:33:48 PM PDT 24
Peak memory 219288 kb
Host smart-951c086b-77be-4c23-a49c-7cd6d5178f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290752244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.290752244
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3946545640
Short name T480
Test name
Test status
Simulation time 43735631 ps
CPU time 1.48 seconds
Started Jun 27 06:33:37 PM PDT 24
Finished Jun 27 06:33:41 PM PDT 24
Peak memory 217620 kb
Host smart-205b94d4-24d9-4062-81fb-14cad918f5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946545640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3946545640
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2668221975
Short name T11
Test name
Test status
Simulation time 45827264 ps
CPU time 1.49 seconds
Started Jun 27 06:33:33 PM PDT 24
Finished Jun 27 06:33:37 PM PDT 24
Peak memory 220128 kb
Host smart-9a16afa8-ecaf-431e-b1db-b3be83ba570d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668221975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2668221975
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2777455306
Short name T689
Test name
Test status
Simulation time 84449686 ps
CPU time 3 seconds
Started Jun 27 06:33:33 PM PDT 24
Finished Jun 27 06:33:38 PM PDT 24
Peak memory 218944 kb
Host smart-1b46c9b3-8430-4858-95ab-9159523929b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777455306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2777455306
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1040949438
Short name T341
Test name
Test status
Simulation time 178282614 ps
CPU time 1.37 seconds
Started Jun 27 06:33:33 PM PDT 24
Finished Jun 27 06:33:37 PM PDT 24
Peak memory 219220 kb
Host smart-58071293-98e9-4e23-8fc7-d4f0cce67e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040949438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1040949438
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3440553888
Short name T523
Test name
Test status
Simulation time 64789812 ps
CPU time 1.53 seconds
Started Jun 27 06:33:37 PM PDT 24
Finished Jun 27 06:33:42 PM PDT 24
Peak memory 219024 kb
Host smart-32c92e0b-4169-4dc1-bf97-9caef0059878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440553888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3440553888
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1842590095
Short name T524
Test name
Test status
Simulation time 31485859 ps
CPU time 1.32 seconds
Started Jun 27 06:30:48 PM PDT 24
Finished Jun 27 06:30:53 PM PDT 24
Peak memory 216004 kb
Host smart-b714c7ad-fedd-45a5-bca2-be8308faa093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842590095 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1842590095
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3275416647
Short name T241
Test name
Test status
Simulation time 42751239 ps
CPU time 0.86 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:30:55 PM PDT 24
Peak memory 207092 kb
Host smart-f3c37f26-2580-4c95-a432-b697a300a681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275416647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3275416647
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3473451743
Short name T166
Test name
Test status
Simulation time 26654353 ps
CPU time 0.86 seconds
Started Jun 27 06:30:51 PM PDT 24
Finished Jun 27 06:30:59 PM PDT 24
Peak memory 216548 kb
Host smart-6cc3393a-1d7a-4490-b368-3d661aaf4a77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473451743 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3473451743
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.2083712850
Short name T172
Test name
Test status
Simulation time 41067671 ps
CPU time 0.98 seconds
Started Jun 27 06:30:52 PM PDT 24
Finished Jun 27 06:31:02 PM PDT 24
Peak memory 224048 kb
Host smart-96472b89-f104-4f32-ae09-850e1e890a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083712850 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2083712850
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.492720822
Short name T693
Test name
Test status
Simulation time 56940471 ps
CPU time 1.67 seconds
Started Jun 27 06:30:51 PM PDT 24
Finished Jun 27 06:31:00 PM PDT 24
Peak memory 218676 kb
Host smart-cb3d88f6-0e23-44aa-b0cb-6b0a08cb84d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492720822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.492720822
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.4179988702
Short name T485
Test name
Test status
Simulation time 36808860 ps
CPU time 0.89 seconds
Started Jun 27 06:30:50 PM PDT 24
Finished Jun 27 06:30:59 PM PDT 24
Peak memory 215620 kb
Host smart-e32162d3-fe38-4c2f-9bbc-ae99c1121fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179988702 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.4179988702
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.554395591
Short name T873
Test name
Test status
Simulation time 23412332 ps
CPU time 0.94 seconds
Started Jun 27 06:30:50 PM PDT 24
Finished Jun 27 06:30:58 PM PDT 24
Peak memory 215596 kb
Host smart-3306b12b-4f8e-45fa-b945-27db605dd806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554395591 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.554395591
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2783709985
Short name T809
Test name
Test status
Simulation time 276436374 ps
CPU time 5.05 seconds
Started Jun 27 06:30:47 PM PDT 24
Finished Jun 27 06:30:54 PM PDT 24
Peak memory 215592 kb
Host smart-5e163a6d-4974-429e-98a5-d78926ac7a59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783709985 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2783709985
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2097481710
Short name T891
Test name
Test status
Simulation time 269502593465 ps
CPU time 1458 seconds
Started Jun 27 06:30:50 PM PDT 24
Finished Jun 27 06:55:16 PM PDT 24
Peak memory 226900 kb
Host smart-3e9b46f4-539c-44a2-92a5-4873280e9192
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097481710 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2097481710
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3953401268
Short name T582
Test name
Test status
Simulation time 96581949 ps
CPU time 1.27 seconds
Started Jun 27 06:33:31 PM PDT 24
Finished Jun 27 06:33:35 PM PDT 24
Peak memory 220216 kb
Host smart-13156a60-14cc-4436-8674-776c3bfc1786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953401268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3953401268
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.642838838
Short name T773
Test name
Test status
Simulation time 31835790 ps
CPU time 1.3 seconds
Started Jun 27 06:33:34 PM PDT 24
Finished Jun 27 06:33:37 PM PDT 24
Peak memory 217812 kb
Host smart-0f8aef4d-b914-4507-8190-6d5d8b8c5d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642838838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.642838838
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.180670430
Short name T453
Test name
Test status
Simulation time 68460556 ps
CPU time 1.92 seconds
Started Jun 27 06:33:38 PM PDT 24
Finished Jun 27 06:33:43 PM PDT 24
Peak memory 218684 kb
Host smart-2f60425c-0db6-4564-8ab7-d4047e125fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180670430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.180670430
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1107361505
Short name T445
Test name
Test status
Simulation time 52707219 ps
CPU time 1.19 seconds
Started Jun 27 06:33:33 PM PDT 24
Finished Jun 27 06:33:36 PM PDT 24
Peak memory 217572 kb
Host smart-0d249923-515b-4818-9fbb-89aeca299ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107361505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1107361505
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3108537054
Short name T344
Test name
Test status
Simulation time 71297524 ps
CPU time 1.23 seconds
Started Jun 27 06:33:42 PM PDT 24
Finished Jun 27 06:33:48 PM PDT 24
Peak memory 217472 kb
Host smart-a8a0cb67-5dcb-4b6e-b890-b184324d5db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108537054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3108537054
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.838793720
Short name T581
Test name
Test status
Simulation time 429334773 ps
CPU time 4.1 seconds
Started Jun 27 06:33:36 PM PDT 24
Finished Jun 27 06:33:42 PM PDT 24
Peak memory 220332 kb
Host smart-d6920042-a752-4c47-bead-fcb31e343911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838793720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.838793720
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2206852404
Short name T391
Test name
Test status
Simulation time 105325007 ps
CPU time 1.33 seconds
Started Jun 27 06:33:31 PM PDT 24
Finished Jun 27 06:33:35 PM PDT 24
Peak memory 219612 kb
Host smart-c500b0ee-b326-4022-9dbe-6c3e940203d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206852404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2206852404
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2272888572
Short name T823
Test name
Test status
Simulation time 185266742 ps
CPU time 1.52 seconds
Started Jun 27 06:33:36 PM PDT 24
Finished Jun 27 06:33:40 PM PDT 24
Peak memory 219304 kb
Host smart-6c961a80-4f57-4ee7-9aaa-91ac518948a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272888572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2272888572
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3956692403
Short name T772
Test name
Test status
Simulation time 75407576 ps
CPU time 1.27 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:44 PM PDT 24
Peak memory 217648 kb
Host smart-74dad76b-d7c9-4804-b632-33aec9086837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956692403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3956692403
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1299487431
Short name T136
Test name
Test status
Simulation time 34063189 ps
CPU time 1.25 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:30:56 PM PDT 24
Peak memory 220108 kb
Host smart-17ad0e4d-12ad-4750-9265-1e2e2550e096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299487431 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1299487431
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.4252854961
Short name T762
Test name
Test status
Simulation time 23221906 ps
CPU time 0.86 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:30:57 PM PDT 24
Peak memory 206796 kb
Host smart-6e8d0d39-6383-4283-9cf2-cc83c6ffb6f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252854961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.4252854961
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2105906683
Short name T673
Test name
Test status
Simulation time 36658309 ps
CPU time 1.23 seconds
Started Jun 27 06:30:53 PM PDT 24
Finished Jun 27 06:31:03 PM PDT 24
Peak memory 218548 kb
Host smart-284d14b3-b032-49fa-bcd6-a18d24623f0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105906683 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2105906683
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1164368710
Short name T144
Test name
Test status
Simulation time 61505192 ps
CPU time 0.98 seconds
Started Jun 27 06:30:50 PM PDT 24
Finished Jun 27 06:30:59 PM PDT 24
Peak memory 220012 kb
Host smart-d4dc98b3-626d-46df-a8ab-3d8fcd90635c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164368710 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1164368710
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2673180001
Short name T892
Test name
Test status
Simulation time 55804954 ps
CPU time 1.49 seconds
Started Jun 27 06:30:53 PM PDT 24
Finished Jun 27 06:31:03 PM PDT 24
Peak memory 219024 kb
Host smart-5b75b6a5-022d-48dc-a274-4dfb1dce48b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673180001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2673180001
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3392573993
Short name T644
Test name
Test status
Simulation time 41474523 ps
CPU time 0.85 seconds
Started Jun 27 06:30:48 PM PDT 24
Finished Jun 27 06:30:53 PM PDT 24
Peak memory 215484 kb
Host smart-562e093c-ccfc-4293-9296-d3cc8a43141c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392573993 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3392573993
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.631892610
Short name T401
Test name
Test status
Simulation time 44283933 ps
CPU time 0.95 seconds
Started Jun 27 06:30:52 PM PDT 24
Finished Jun 27 06:31:02 PM PDT 24
Peak memory 215668 kb
Host smart-4cae3830-82d2-4278-b9d4-8dfec40f0307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631892610 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.631892610
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1051244916
Short name T787
Test name
Test status
Simulation time 64084693 ps
CPU time 1.26 seconds
Started Jun 27 06:30:47 PM PDT 24
Finished Jun 27 06:30:51 PM PDT 24
Peak memory 215664 kb
Host smart-655eec1a-e697-49aa-89b6-7f3c05aba495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051244916 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1051244916
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.4026103863
Short name T586
Test name
Test status
Simulation time 311376011384 ps
CPU time 959.14 seconds
Started Jun 27 06:30:48 PM PDT 24
Finished Jun 27 06:46:51 PM PDT 24
Peak memory 224048 kb
Host smart-4be976e8-386a-4715-b209-b134555c66ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026103863 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.4026103863
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3116646260
Short name T244
Test name
Test status
Simulation time 42792279 ps
CPU time 1.45 seconds
Started Jun 27 06:33:32 PM PDT 24
Finished Jun 27 06:33:36 PM PDT 24
Peak memory 215576 kb
Host smart-79589aa5-3bbb-4e03-9eec-a3a48e7d05f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116646260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3116646260
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.986356135
Short name T418
Test name
Test status
Simulation time 41120336 ps
CPU time 1.45 seconds
Started Jun 27 06:33:30 PM PDT 24
Finished Jun 27 06:33:34 PM PDT 24
Peak memory 218752 kb
Host smart-61921a00-27dc-454e-bb62-b66bcf596b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986356135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.986356135
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2014306246
Short name T632
Test name
Test status
Simulation time 145979053 ps
CPU time 1.56 seconds
Started Jun 27 06:33:32 PM PDT 24
Finished Jun 27 06:33:36 PM PDT 24
Peak memory 219248 kb
Host smart-85b70a1d-4d89-4bd4-9059-e227c1c469ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014306246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2014306246
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2260237482
Short name T902
Test name
Test status
Simulation time 80898198 ps
CPU time 1.32 seconds
Started Jun 27 06:33:37 PM PDT 24
Finished Jun 27 06:33:41 PM PDT 24
Peak memory 220308 kb
Host smart-9f67870f-7ec2-4d98-af64-7c5ece391b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260237482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2260237482
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3714579883
Short name T701
Test name
Test status
Simulation time 106627289 ps
CPU time 2.79 seconds
Started Jun 27 06:33:37 PM PDT 24
Finished Jun 27 06:33:42 PM PDT 24
Peak memory 220724 kb
Host smart-4e62ad80-e8fa-403e-8602-46846df40505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714579883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3714579883
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3744716627
Short name T843
Test name
Test status
Simulation time 65948129 ps
CPU time 1.27 seconds
Started Jun 27 06:33:36 PM PDT 24
Finished Jun 27 06:33:40 PM PDT 24
Peak memory 217760 kb
Host smart-48a6018a-6563-4954-8bb9-355dee2cc7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744716627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3744716627
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3688984458
Short name T484
Test name
Test status
Simulation time 39677985 ps
CPU time 1.54 seconds
Started Jun 27 06:33:33 PM PDT 24
Finished Jun 27 06:33:37 PM PDT 24
Peak memory 220264 kb
Host smart-b646ac7d-7be2-493e-a652-2889c526de50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688984458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3688984458
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2860639793
Short name T612
Test name
Test status
Simulation time 99262688 ps
CPU time 1.36 seconds
Started Jun 27 06:33:33 PM PDT 24
Finished Jun 27 06:33:36 PM PDT 24
Peak memory 219004 kb
Host smart-1c638ef1-157a-46c5-a9b7-4adcb76e6176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860639793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2860639793
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.926051838
Short name T758
Test name
Test status
Simulation time 64343221 ps
CPU time 1.18 seconds
Started Jun 27 06:33:42 PM PDT 24
Finished Jun 27 06:33:47 PM PDT 24
Peak memory 218724 kb
Host smart-5fdd4f6b-bd88-41b5-a18e-6a03690dfdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926051838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.926051838
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1473445135
Short name T437
Test name
Test status
Simulation time 75485556 ps
CPU time 1.44 seconds
Started Jun 27 06:33:35 PM PDT 24
Finished Jun 27 06:33:38 PM PDT 24
Peak memory 217656 kb
Host smart-53c81947-9cc8-4f22-b0b0-c5ed503b47cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473445135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1473445135
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.630007332
Short name T811
Test name
Test status
Simulation time 42360740 ps
CPU time 1.09 seconds
Started Jun 27 06:30:48 PM PDT 24
Finished Jun 27 06:30:55 PM PDT 24
Peak memory 218824 kb
Host smart-c7ccbb1f-58ed-4ade-a3c1-39ea57627dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630007332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.630007332
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3592298731
Short name T717
Test name
Test status
Simulation time 57934101 ps
CPU time 0.9 seconds
Started Jun 27 06:30:50 PM PDT 24
Finished Jun 27 06:30:59 PM PDT 24
Peak memory 215164 kb
Host smart-6868db31-9856-4d64-8072-9d08f48033e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592298731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3592298731
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1288579227
Short name T220
Test name
Test status
Simulation time 33586510 ps
CPU time 0.89 seconds
Started Jun 27 06:30:51 PM PDT 24
Finished Jun 27 06:30:59 PM PDT 24
Peak memory 216616 kb
Host smart-46284a74-8c7b-4f5d-8d13-0b50eb67aa79
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288579227 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1288579227
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.445044749
Short name T876
Test name
Test status
Simulation time 35304623 ps
CPU time 1.08 seconds
Started Jun 27 06:30:48 PM PDT 24
Finished Jun 27 06:30:54 PM PDT 24
Peak memory 218596 kb
Host smart-23b32130-0d87-4cb3-a9ac-14219f291d84
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445044749 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.445044749
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_genbits.1709358182
Short name T940
Test name
Test status
Simulation time 50832753 ps
CPU time 1.68 seconds
Started Jun 27 06:30:48 PM PDT 24
Finished Jun 27 06:30:56 PM PDT 24
Peak memory 219088 kb
Host smart-99790ce3-9314-45ab-ace5-954e7f17da7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709358182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1709358182
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.330823617
Short name T696
Test name
Test status
Simulation time 22801582 ps
CPU time 1.11 seconds
Started Jun 27 06:30:52 PM PDT 24
Finished Jun 27 06:31:02 PM PDT 24
Peak memory 215856 kb
Host smart-27b47301-6329-4faf-b1b3-705486bd6169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330823617 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.330823617
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3248445262
Short name T383
Test name
Test status
Simulation time 25753654 ps
CPU time 0.96 seconds
Started Jun 27 06:30:50 PM PDT 24
Finished Jun 27 06:30:58 PM PDT 24
Peak memory 215612 kb
Host smart-a7a4162a-e6c3-446d-98fa-dab4ef75003d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248445262 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3248445262
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2824104128
Short name T243
Test name
Test status
Simulation time 316368091 ps
CPU time 3.51 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:30:58 PM PDT 24
Peak memory 220252 kb
Host smart-3aba9d58-95a2-4bc0-919f-afa2146aaccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824104128 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2824104128
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/291.edn_genbits.2728224480
Short name T499
Test name
Test status
Simulation time 37423918 ps
CPU time 1.08 seconds
Started Jun 27 06:33:35 PM PDT 24
Finished Jun 27 06:33:38 PM PDT 24
Peak memory 219900 kb
Host smart-2d75d69c-4ff1-4f86-a938-2a1e30bcb309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728224480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2728224480
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.4052322547
Short name T79
Test name
Test status
Simulation time 73548650 ps
CPU time 2.71 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:45 PM PDT 24
Peak memory 218032 kb
Host smart-56dc64d4-898f-4b5e-b170-b87568bc919d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052322547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.4052322547
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1167838835
Short name T475
Test name
Test status
Simulation time 93464103 ps
CPU time 1.44 seconds
Started Jun 27 06:33:38 PM PDT 24
Finished Jun 27 06:33:43 PM PDT 24
Peak memory 219076 kb
Host smart-3bb97c79-8eb3-4ef0-83ef-6304539ecbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167838835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1167838835
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3916025726
Short name T652
Test name
Test status
Simulation time 102183852 ps
CPU time 1.09 seconds
Started Jun 27 06:33:42 PM PDT 24
Finished Jun 27 06:33:48 PM PDT 24
Peak memory 217536 kb
Host smart-0cab7d8c-510f-4a76-aa1c-43bde366720a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916025726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3916025726
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2056736819
Short name T885
Test name
Test status
Simulation time 60658012 ps
CPU time 1.33 seconds
Started Jun 27 06:33:42 PM PDT 24
Finished Jun 27 06:33:48 PM PDT 24
Peak memory 220072 kb
Host smart-7d6f10c2-90a5-4cc3-bd09-4c4764ef6cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056736819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2056736819
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.871238125
Short name T422
Test name
Test status
Simulation time 68202330 ps
CPU time 2.93 seconds
Started Jun 27 06:33:40 PM PDT 24
Finished Jun 27 06:33:47 PM PDT 24
Peak memory 218240 kb
Host smart-254d095b-3d50-4e1c-bbf0-93cd297896e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871238125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.871238125
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2750609367
Short name T342
Test name
Test status
Simulation time 120314520 ps
CPU time 1.24 seconds
Started Jun 27 06:33:40 PM PDT 24
Finished Jun 27 06:33:45 PM PDT 24
Peak memory 220316 kb
Host smart-5d32d09e-be9e-4e8c-a5a3-7a60eb706e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750609367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2750609367
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3586678524
Short name T435
Test name
Test status
Simulation time 33330280 ps
CPU time 1.56 seconds
Started Jun 27 06:33:40 PM PDT 24
Finished Jun 27 06:33:46 PM PDT 24
Peak memory 218956 kb
Host smart-6ebac65b-563d-45e7-8bd0-fcd2ecad2695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586678524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3586678524
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2473538277
Short name T658
Test name
Test status
Simulation time 172074261 ps
CPU time 1.04 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:43 PM PDT 24
Peak memory 217572 kb
Host smart-1669bb9b-e538-4546-841c-c40427b8d1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473538277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2473538277
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.75313693
Short name T222
Test name
Test status
Simulation time 61342500 ps
CPU time 1.32 seconds
Started Jun 27 06:29:49 PM PDT 24
Finished Jun 27 06:29:57 PM PDT 24
Peak memory 215896 kb
Host smart-d8e1d785-575c-41d6-9dee-1127cd237844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75313693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.75313693
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2991811745
Short name T458
Test name
Test status
Simulation time 64313192 ps
CPU time 0.81 seconds
Started Jun 27 06:29:47 PM PDT 24
Finished Jun 27 06:29:55 PM PDT 24
Peak memory 206876 kb
Host smart-87b33cca-988d-4fa0-b051-204d8b8321ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991811745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2991811745
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2460958750
Short name T726
Test name
Test status
Simulation time 11854255 ps
CPU time 0.88 seconds
Started Jun 27 06:29:49 PM PDT 24
Finished Jun 27 06:29:57 PM PDT 24
Peak memory 216444 kb
Host smart-828f35d1-f3da-46e1-9c89-21794e6a8f3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460958750 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2460958750
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.449773324
Short name T370
Test name
Test status
Simulation time 32705677 ps
CPU time 1.14 seconds
Started Jun 27 06:29:45 PM PDT 24
Finished Jun 27 06:29:51 PM PDT 24
Peak memory 217332 kb
Host smart-402e85fe-08b4-4c12-938c-b76487c68b56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449773324 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.449773324
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2756398844
Short name T130
Test name
Test status
Simulation time 20332948 ps
CPU time 1.2 seconds
Started Jun 27 06:29:47 PM PDT 24
Finished Jun 27 06:29:55 PM PDT 24
Peak memory 229792 kb
Host smart-afbb4c32-6531-477f-a1da-faab07b57508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756398844 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2756398844
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3287003150
Short name T618
Test name
Test status
Simulation time 91159107 ps
CPU time 1.45 seconds
Started Jun 27 06:29:43 PM PDT 24
Finished Jun 27 06:29:48 PM PDT 24
Peak memory 218948 kb
Host smart-64a3e1e8-1873-41c0-b63d-f9256429dc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287003150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3287003150
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.276774584
Short name T421
Test name
Test status
Simulation time 22445130 ps
CPU time 1.08 seconds
Started Jun 27 06:29:48 PM PDT 24
Finished Jun 27 06:29:57 PM PDT 24
Peak memory 215772 kb
Host smart-1f3bc72a-2aed-4b43-aac0-8576d651238e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276774584 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.276774584
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.2060874356
Short name T859
Test name
Test status
Simulation time 41444016 ps
CPU time 0.9 seconds
Started Jun 27 06:29:45 PM PDT 24
Finished Jun 27 06:29:52 PM PDT 24
Peak memory 207456 kb
Host smart-7d941a4d-07af-4a65-8694-4495f545fd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060874356 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2060874356
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.805033774
Short name T702
Test name
Test status
Simulation time 16496367 ps
CPU time 0.95 seconds
Started Jun 27 06:29:42 PM PDT 24
Finished Jun 27 06:29:46 PM PDT 24
Peak memory 215596 kb
Host smart-df4b6cd1-c742-4674-8709-fa589b215487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805033774 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.805033774
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2802967462
Short name T345
Test name
Test status
Simulation time 757273736 ps
CPU time 5.17 seconds
Started Jun 27 06:29:47 PM PDT 24
Finished Jun 27 06:29:59 PM PDT 24
Peak memory 215536 kb
Host smart-cea510e3-b88a-40cd-8c27-409a8ef4b7bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802967462 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2802967462
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1387021755
Short name T619
Test name
Test status
Simulation time 21473383592 ps
CPU time 494.6 seconds
Started Jun 27 06:29:47 PM PDT 24
Finished Jun 27 06:38:09 PM PDT 24
Peak memory 223940 kb
Host smart-b704ec65-2f5f-4976-8122-a130dd9133d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387021755 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1387021755
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.421467180
Short name T903
Test name
Test status
Simulation time 28727950 ps
CPU time 1.31 seconds
Started Jun 27 06:30:52 PM PDT 24
Finished Jun 27 06:31:02 PM PDT 24
Peak memory 221260 kb
Host smart-3d9ba490-1b24-4ce2-b06a-f4c1c90e28c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421467180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.421467180
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1214991733
Short name T825
Test name
Test status
Simulation time 29590058 ps
CPU time 0.93 seconds
Started Jun 27 06:30:52 PM PDT 24
Finished Jun 27 06:31:02 PM PDT 24
Peak memory 207036 kb
Host smart-cd88604a-1dff-408f-8bdc-2b02efbeb134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214991733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1214991733
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1902234026
Short name T745
Test name
Test status
Simulation time 16668033 ps
CPU time 0.84 seconds
Started Jun 27 06:30:52 PM PDT 24
Finished Jun 27 06:31:01 PM PDT 24
Peak memory 216564 kb
Host smart-05ebb527-25d9-495a-9c7a-7bffa9d63336
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902234026 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1902234026
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3805104356
Short name T784
Test name
Test status
Simulation time 83070981 ps
CPU time 1.23 seconds
Started Jun 27 06:30:52 PM PDT 24
Finished Jun 27 06:31:02 PM PDT 24
Peak memory 217372 kb
Host smart-9d72ef62-e8df-43d5-ab24-727529078f62
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805104356 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3805104356
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3133281036
Short name T162
Test name
Test status
Simulation time 18496435 ps
CPU time 1.04 seconds
Started Jun 27 06:30:51 PM PDT 24
Finished Jun 27 06:31:00 PM PDT 24
Peak memory 218732 kb
Host smart-0c88c09f-8094-4906-a70d-8c20704c9a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133281036 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3133281036
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2782088486
Short name T781
Test name
Test status
Simulation time 72555348 ps
CPU time 1.02 seconds
Started Jun 27 06:30:54 PM PDT 24
Finished Jun 27 06:31:04 PM PDT 24
Peak memory 217588 kb
Host smart-a26193ff-3871-40d6-a6c0-f7d3b075b95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782088486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2782088486
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_smoke.2798608678
Short name T602
Test name
Test status
Simulation time 30064770 ps
CPU time 0.94 seconds
Started Jun 27 06:30:50 PM PDT 24
Finished Jun 27 06:30:58 PM PDT 24
Peak memory 215532 kb
Host smart-03a13e65-ae96-4ade-bac7-999174e00a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798608678 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2798608678
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2032451281
Short name T791
Test name
Test status
Simulation time 131199853 ps
CPU time 2.87 seconds
Started Jun 27 06:30:50 PM PDT 24
Finished Jun 27 06:31:00 PM PDT 24
Peak memory 217344 kb
Host smart-52fab7bd-c81c-423d-8374-8fa375db9bd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032451281 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2032451281
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2102907809
Short name T235
Test name
Test status
Simulation time 101045801283 ps
CPU time 1321.69 seconds
Started Jun 27 06:30:52 PM PDT 24
Finished Jun 27 06:53:03 PM PDT 24
Peak memory 222888 kb
Host smart-92438f41-50c7-47d6-9edc-a49b8129fa75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102907809 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2102907809
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2691757612
Short name T106
Test name
Test status
Simulation time 39220662 ps
CPU time 1.19 seconds
Started Jun 27 06:30:53 PM PDT 24
Finished Jun 27 06:31:02 PM PDT 24
Peak memory 220644 kb
Host smart-c73442dc-34ef-4e3b-8b9c-09f356d748b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691757612 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2691757612
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.883289542
Short name T806
Test name
Test status
Simulation time 50175126 ps
CPU time 0.95 seconds
Started Jun 27 06:30:52 PM PDT 24
Finished Jun 27 06:31:02 PM PDT 24
Peak memory 215188 kb
Host smart-ecdf0132-f18d-480a-857c-d4439c9f5fc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883289542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.883289542
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.257194692
Short name T728
Test name
Test status
Simulation time 11983737 ps
CPU time 0.92 seconds
Started Jun 27 06:30:54 PM PDT 24
Finished Jun 27 06:31:03 PM PDT 24
Peak memory 215768 kb
Host smart-3ac92b6c-1c80-48d1-9f06-5a989e97deb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257194692 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.257194692
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.293755818
Short name T147
Test name
Test status
Simulation time 126581917 ps
CPU time 1.17 seconds
Started Jun 27 06:30:51 PM PDT 24
Finished Jun 27 06:31:00 PM PDT 24
Peak memory 217280 kb
Host smart-1252339f-e79c-44e4-adcd-60d31b1d7956
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293755818 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.293755818
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2653838675
Short name T15
Test name
Test status
Simulation time 30960505 ps
CPU time 1.08 seconds
Started Jun 27 06:30:53 PM PDT 24
Finished Jun 27 06:31:02 PM PDT 24
Peak memory 224080 kb
Host smart-9b471a9c-bc5e-4533-8ab3-f482b6f9d4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653838675 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2653838675
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3634147070
Short name T56
Test name
Test status
Simulation time 244522888 ps
CPU time 1.42 seconds
Started Jun 27 06:30:52 PM PDT 24
Finished Jun 27 06:31:02 PM PDT 24
Peak memory 217516 kb
Host smart-2ee2e96a-21e8-43d9-b1cc-2a6db4ef0347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634147070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3634147070
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3325281838
Short name T57
Test name
Test status
Simulation time 23890704 ps
CPU time 0.94 seconds
Started Jun 27 06:30:49 PM PDT 24
Finished Jun 27 06:30:57 PM PDT 24
Peak memory 216268 kb
Host smart-778df27d-7775-46c6-af07-c95db029da12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325281838 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3325281838
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1242401481
Short name T535
Test name
Test status
Simulation time 66509053 ps
CPU time 0.89 seconds
Started Jun 27 06:30:50 PM PDT 24
Finished Jun 27 06:30:59 PM PDT 24
Peak memory 215608 kb
Host smart-6d552562-553d-49ba-a90f-57176b214ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242401481 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1242401481
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1673769905
Short name T483
Test name
Test status
Simulation time 218913372 ps
CPU time 4.6 seconds
Started Jun 27 06:30:52 PM PDT 24
Finished Jun 27 06:31:06 PM PDT 24
Peak memory 217604 kb
Host smart-54a4fea6-3647-489d-a7e7-51f8ab9477f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673769905 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1673769905
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1933099281
Short name T414
Test name
Test status
Simulation time 190584107836 ps
CPU time 2412.05 seconds
Started Jun 27 06:30:53 PM PDT 24
Finished Jun 27 07:11:14 PM PDT 24
Peak memory 229484 kb
Host smart-758ff1f9-1de9-4822-8d1d-b42d49da8098
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933099281 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1933099281
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2037125218
Short name T450
Test name
Test status
Simulation time 75207641 ps
CPU time 1.19 seconds
Started Jun 27 06:31:01 PM PDT 24
Finished Jun 27 06:31:07 PM PDT 24
Peak memory 220616 kb
Host smart-d6c12fc8-a094-49aa-a8d3-508bf814c793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037125218 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2037125218
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.697481193
Short name T580
Test name
Test status
Simulation time 38388577 ps
CPU time 0.98 seconds
Started Jun 27 06:31:04 PM PDT 24
Finished Jun 27 06:31:08 PM PDT 24
Peak memory 206988 kb
Host smart-6c36bce4-354c-4737-b0a0-8fafecee7af0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697481193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.697481193
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1684762149
Short name T131
Test name
Test status
Simulation time 58200059 ps
CPU time 1.11 seconds
Started Jun 27 06:31:11 PM PDT 24
Finished Jun 27 06:31:16 PM PDT 24
Peak memory 217052 kb
Host smart-bf4c6e02-58d7-4d28-b206-84a4070c311a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684762149 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1684762149
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3105605382
Short name T207
Test name
Test status
Simulation time 76553451 ps
CPU time 1.21 seconds
Started Jun 27 06:31:04 PM PDT 24
Finished Jun 27 06:31:09 PM PDT 24
Peak memory 225848 kb
Host smart-04ed9ef3-4f36-4ebe-bc48-7112f47d7534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105605382 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3105605382
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.4279771126
Short name T687
Test name
Test status
Simulation time 36221896 ps
CPU time 1.4 seconds
Started Jun 27 06:31:09 PM PDT 24
Finished Jun 27 06:31:13 PM PDT 24
Peak memory 218668 kb
Host smart-afa1224c-b262-404d-989c-d04d00a25a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279771126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.4279771126
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.812637354
Short name T829
Test name
Test status
Simulation time 22021037 ps
CPU time 1.18 seconds
Started Jun 27 06:31:08 PM PDT 24
Finished Jun 27 06:31:12 PM PDT 24
Peak memory 225168 kb
Host smart-d554bf8f-cbd9-42b3-9ee2-6962331e1032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812637354 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.812637354
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.46749075
Short name T504
Test name
Test status
Simulation time 18805123 ps
CPU time 1.02 seconds
Started Jun 27 06:31:04 PM PDT 24
Finished Jun 27 06:31:08 PM PDT 24
Peak memory 215612 kb
Host smart-e6d80d43-2d62-44ac-aee2-a83f838411c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46749075 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.46749075
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1492064931
Short name T101
Test name
Test status
Simulation time 246523253 ps
CPU time 3.03 seconds
Started Jun 27 06:31:02 PM PDT 24
Finished Jun 27 06:31:09 PM PDT 24
Peak memory 217544 kb
Host smart-90c8640d-3c77-40b5-a860-60fa374f6915
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492064931 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1492064931
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.977321588
Short name T704
Test name
Test status
Simulation time 67048451887 ps
CPU time 858.87 seconds
Started Jun 27 06:31:03 PM PDT 24
Finished Jun 27 06:45:25 PM PDT 24
Peak memory 224012 kb
Host smart-9fdddfaf-0895-40e2-b12f-a2563b64a0fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977321588 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.977321588
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3945154372
Short name T381
Test name
Test status
Simulation time 29588074 ps
CPU time 1.35 seconds
Started Jun 27 06:31:06 PM PDT 24
Finished Jun 27 06:31:11 PM PDT 24
Peak memory 220248 kb
Host smart-21d568a9-683d-4a2e-b8bc-4c42c900bbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945154372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3945154372
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2384991689
Short name T63
Test name
Test status
Simulation time 26099631 ps
CPU time 1.12 seconds
Started Jun 27 06:31:09 PM PDT 24
Finished Jun 27 06:31:13 PM PDT 24
Peak memory 215228 kb
Host smart-36793da8-df8a-4259-a76c-c05c956b19cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384991689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2384991689
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.901425778
Short name T219
Test name
Test status
Simulation time 26178334 ps
CPU time 0.82 seconds
Started Jun 27 06:31:03 PM PDT 24
Finished Jun 27 06:31:07 PM PDT 24
Peak memory 215692 kb
Host smart-48a3cd8b-9947-455a-acfc-c49058931045
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901425778 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.901425778
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3468838362
Short name T197
Test name
Test status
Simulation time 214943656 ps
CPU time 1 seconds
Started Jun 27 06:31:12 PM PDT 24
Finished Jun 27 06:31:16 PM PDT 24
Peak memory 217088 kb
Host smart-53955f01-014b-40b2-872a-b63b717ccb0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468838362 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3468838362
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1394321956
Short name T45
Test name
Test status
Simulation time 18020476 ps
CPU time 1.14 seconds
Started Jun 27 06:31:03 PM PDT 24
Finished Jun 27 06:31:08 PM PDT 24
Peak memory 224212 kb
Host smart-18cd443a-a3d7-463e-b6e9-89ffe25b7159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394321956 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1394321956
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2463848057
Short name T352
Test name
Test status
Simulation time 71438640 ps
CPU time 2.73 seconds
Started Jun 27 06:31:09 PM PDT 24
Finished Jun 27 06:31:15 PM PDT 24
Peak memory 220524 kb
Host smart-40850e79-835d-4d1b-9086-760dad85f22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463848057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2463848057
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2635909908
Short name T721
Test name
Test status
Simulation time 30540256 ps
CPU time 0.87 seconds
Started Jun 27 06:31:11 PM PDT 24
Finished Jun 27 06:31:16 PM PDT 24
Peak memory 215676 kb
Host smart-4105ee58-50b9-4145-990f-1f9269166e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635909908 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2635909908
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3628933099
Short name T497
Test name
Test status
Simulation time 54211786 ps
CPU time 0.91 seconds
Started Jun 27 06:31:09 PM PDT 24
Finished Jun 27 06:31:13 PM PDT 24
Peak memory 215532 kb
Host smart-42112990-c3d8-47b4-932e-224520e37761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628933099 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3628933099
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3402639624
Short name T857
Test name
Test status
Simulation time 312074477 ps
CPU time 2.35 seconds
Started Jun 27 06:31:03 PM PDT 24
Finished Jun 27 06:31:09 PM PDT 24
Peak memory 217536 kb
Host smart-7310ab34-96d7-4c4a-ab84-60539ebc0227
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402639624 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3402639624
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3454658951
Short name T933
Test name
Test status
Simulation time 86450240924 ps
CPU time 1825.11 seconds
Started Jun 27 06:31:03 PM PDT 24
Finished Jun 27 07:01:32 PM PDT 24
Peak memory 228836 kb
Host smart-2a3bdb33-f90a-4041-9f1d-e208faa725c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454658951 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3454658951
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.4227008547
Short name T137
Test name
Test status
Simulation time 35820231 ps
CPU time 1.06 seconds
Started Jun 27 06:31:03 PM PDT 24
Finished Jun 27 06:31:07 PM PDT 24
Peak memory 220948 kb
Host smart-fa5de4f0-a07e-4c4f-9e5b-ab2af4802fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227008547 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.4227008547
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2554917115
Short name T755
Test name
Test status
Simulation time 22447661 ps
CPU time 0.9 seconds
Started Jun 27 06:31:04 PM PDT 24
Finished Jun 27 06:31:08 PM PDT 24
Peak memory 207028 kb
Host smart-a3ec5032-0562-4f75-a364-eca38fcfbbac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554917115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2554917115
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2996686086
Short name T511
Test name
Test status
Simulation time 38055740 ps
CPU time 0.88 seconds
Started Jun 27 06:31:04 PM PDT 24
Finished Jun 27 06:31:08 PM PDT 24
Peak memory 215688 kb
Host smart-57bce955-4d38-4460-8ac5-bd80eb47d1cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996686086 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2996686086
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3821467550
Short name T492
Test name
Test status
Simulation time 102861743 ps
CPU time 1.21 seconds
Started Jun 27 06:31:09 PM PDT 24
Finished Jun 27 06:31:13 PM PDT 24
Peak memory 217120 kb
Host smart-ef08d692-553f-4595-af68-9cf6d421cbe0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821467550 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3821467550
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3582933893
Short name T591
Test name
Test status
Simulation time 33053627 ps
CPU time 1.05 seconds
Started Jun 27 06:31:04 PM PDT 24
Finished Jun 27 06:31:09 PM PDT 24
Peak memory 224284 kb
Host smart-e754e49b-579b-4824-9eed-872ef0ed2cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582933893 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3582933893
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3236701123
Short name T815
Test name
Test status
Simulation time 43246073 ps
CPU time 1.7 seconds
Started Jun 27 06:31:07 PM PDT 24
Finished Jun 27 06:31:12 PM PDT 24
Peak memory 220412 kb
Host smart-e33b48a5-3366-4304-808c-4804a086cb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236701123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3236701123
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1353772173
Short name T648
Test name
Test status
Simulation time 32406539 ps
CPU time 0.99 seconds
Started Jun 27 06:31:06 PM PDT 24
Finished Jun 27 06:31:10 PM PDT 24
Peak memory 224200 kb
Host smart-ba0d4768-dc29-4467-973b-db75db3b99e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353772173 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1353772173
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1629473693
Short name T654
Test name
Test status
Simulation time 132021775 ps
CPU time 0.92 seconds
Started Jun 27 06:31:12 PM PDT 24
Finished Jun 27 06:31:16 PM PDT 24
Peak memory 215552 kb
Host smart-1b419550-6abe-421f-a9b5-cc8934073c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629473693 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1629473693
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.570478640
Short name T617
Test name
Test status
Simulation time 827793046 ps
CPU time 4.16 seconds
Started Jun 27 06:31:06 PM PDT 24
Finished Jun 27 06:31:14 PM PDT 24
Peak memory 215648 kb
Host smart-b2decfd7-07c6-43d1-8205-8c0badd76ec6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570478640 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.570478640
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3959247893
Short name T231
Test name
Test status
Simulation time 397553039595 ps
CPU time 1095 seconds
Started Jun 27 06:31:03 PM PDT 24
Finished Jun 27 06:49:21 PM PDT 24
Peak memory 222192 kb
Host smart-90aad701-3124-41d2-af7a-4029041b9721
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959247893 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3959247893
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert_test.1879500152
Short name T820
Test name
Test status
Simulation time 31682005 ps
CPU time 0.96 seconds
Started Jun 27 06:31:08 PM PDT 24
Finished Jun 27 06:31:12 PM PDT 24
Peak memory 207048 kb
Host smart-8befca66-99b8-410b-b435-7a0dc2b6c3bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879500152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1879500152
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1367681821
Short name T464
Test name
Test status
Simulation time 113349105 ps
CPU time 0.85 seconds
Started Jun 27 06:31:09 PM PDT 24
Finished Jun 27 06:31:13 PM PDT 24
Peak memory 216496 kb
Host smart-fb879a80-efc6-4afa-824c-79db0a191acd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367681821 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1367681821
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_err.3909071454
Short name T107
Test name
Test status
Simulation time 46920581 ps
CPU time 0.96 seconds
Started Jun 27 06:31:09 PM PDT 24
Finished Jun 27 06:31:13 PM PDT 24
Peak memory 220160 kb
Host smart-cf88d44a-a383-4316-977f-f12e7adbbeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909071454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3909071454
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3887243287
Short name T327
Test name
Test status
Simulation time 64372205 ps
CPU time 1.13 seconds
Started Jun 27 06:31:11 PM PDT 24
Finished Jun 27 06:31:16 PM PDT 24
Peak memory 217620 kb
Host smart-6a70adea-d304-4cdf-b4e2-4422b5e824c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887243287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3887243287
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3671665134
Short name T737
Test name
Test status
Simulation time 25064849 ps
CPU time 0.96 seconds
Started Jun 27 06:31:04 PM PDT 24
Finished Jun 27 06:31:08 PM PDT 24
Peak memory 215852 kb
Host smart-629af6c1-867e-4d3a-ab16-3e976006b780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671665134 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3671665134
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2887688316
Short name T852
Test name
Test status
Simulation time 60521200 ps
CPU time 0.92 seconds
Started Jun 27 06:31:09 PM PDT 24
Finished Jun 27 06:31:13 PM PDT 24
Peak memory 215616 kb
Host smart-3e5706d9-196c-47be-8b60-f8e8d78c6c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887688316 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2887688316
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2138324793
Short name T438
Test name
Test status
Simulation time 554442928 ps
CPU time 4.25 seconds
Started Jun 27 06:31:03 PM PDT 24
Finished Jun 27 06:31:11 PM PDT 24
Peak memory 215668 kb
Host smart-50dc3dd8-f826-4df7-b208-164356913ea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138324793 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2138324793
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3157618119
Short name T224
Test name
Test status
Simulation time 63727494788 ps
CPU time 717.32 seconds
Started Jun 27 06:31:10 PM PDT 24
Finished Jun 27 06:43:11 PM PDT 24
Peak memory 224064 kb
Host smart-38d3df1e-0099-482f-b58d-9b07f3ea6d70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157618119 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3157618119
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1896300547
Short name T522
Test name
Test status
Simulation time 22274882 ps
CPU time 1.15 seconds
Started Jun 27 06:31:07 PM PDT 24
Finished Jun 27 06:31:12 PM PDT 24
Peak memory 220884 kb
Host smart-9a2440e1-88bd-486e-b8f6-0193cc6a2f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896300547 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1896300547
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.4122175958
Short name T424
Test name
Test status
Simulation time 79450816 ps
CPU time 0.98 seconds
Started Jun 27 06:31:06 PM PDT 24
Finished Jun 27 06:31:10 PM PDT 24
Peak memory 207104 kb
Host smart-408699ee-5186-42bb-9407-ce640ecb8877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122175958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.4122175958
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3776191055
Short name T155
Test name
Test status
Simulation time 35528823 ps
CPU time 0.91 seconds
Started Jun 27 06:31:02 PM PDT 24
Finished Jun 27 06:31:07 PM PDT 24
Peak memory 215696 kb
Host smart-d15ae702-a9b9-427d-8686-e953a59a0ffa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776191055 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3776191055
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.976279127
Short name T140
Test name
Test status
Simulation time 26588040 ps
CPU time 1.14 seconds
Started Jun 27 06:31:07 PM PDT 24
Finished Jun 27 06:31:11 PM PDT 24
Peak memory 217092 kb
Host smart-71f75625-8063-4aee-a135-145ea2a19d8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976279127 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.976279127
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1768461955
Short name T196
Test name
Test status
Simulation time 23469724 ps
CPU time 0.94 seconds
Started Jun 27 06:31:03 PM PDT 24
Finished Jun 27 06:31:07 PM PDT 24
Peak memory 218728 kb
Host smart-d70bd973-ef42-4dba-acea-3e6cc00ad1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768461955 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1768461955
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.223613244
Short name T776
Test name
Test status
Simulation time 84338934 ps
CPU time 1.25 seconds
Started Jun 27 06:31:03 PM PDT 24
Finished Jun 27 06:31:08 PM PDT 24
Peak memory 219344 kb
Host smart-b2547e80-0b93-45ee-950e-fd2391340875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223613244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.223613244
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_smoke.3483435191
Short name T768
Test name
Test status
Simulation time 34024922 ps
CPU time 0.97 seconds
Started Jun 27 06:31:02 PM PDT 24
Finished Jun 27 06:31:07 PM PDT 24
Peak memory 215604 kb
Host smart-f4d87d1d-d6e1-475b-bd31-99f06f28dba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483435191 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3483435191
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1335744061
Short name T253
Test name
Test status
Simulation time 436993833 ps
CPU time 4.47 seconds
Started Jun 27 06:31:11 PM PDT 24
Finished Jun 27 06:31:19 PM PDT 24
Peak memory 217440 kb
Host smart-06f42009-c558-452e-9eae-2e3140ce201c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335744061 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1335744061
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.269219414
Short name T236
Test name
Test status
Simulation time 373860884062 ps
CPU time 2211.79 seconds
Started Jun 27 06:31:06 PM PDT 24
Finished Jun 27 07:08:02 PM PDT 24
Peak memory 227048 kb
Host smart-d94b2c65-3a2d-44e5-ae27-9cb438f25bd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269219414 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.269219414
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3570876943
Short name T41
Test name
Test status
Simulation time 47695669 ps
CPU time 1.21 seconds
Started Jun 27 06:31:12 PM PDT 24
Finished Jun 27 06:31:16 PM PDT 24
Peak memory 218928 kb
Host smart-77822cfa-2906-496e-9d0a-b56b913847c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570876943 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3570876943
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3999296970
Short name T374
Test name
Test status
Simulation time 28352114 ps
CPU time 0.9 seconds
Started Jun 27 06:31:12 PM PDT 24
Finished Jun 27 06:31:16 PM PDT 24
Peak memory 215480 kb
Host smart-db8b56d6-97b5-4cd8-9dcc-a8c09bb3d718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999296970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3999296970
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.958525302
Short name T729
Test name
Test status
Simulation time 33834549 ps
CPU time 0.88 seconds
Started Jun 27 06:31:07 PM PDT 24
Finished Jun 27 06:31:11 PM PDT 24
Peak memory 216624 kb
Host smart-da5d7f7f-7da3-4948-a42c-4c9eab0cd912
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958525302 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.958525302
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.656737125
Short name T681
Test name
Test status
Simulation time 26580304 ps
CPU time 1.05 seconds
Started Jun 27 06:31:11 PM PDT 24
Finished Jun 27 06:31:16 PM PDT 24
Peak memory 218660 kb
Host smart-24dfc4fe-80e0-4a0a-b731-f5d10d387812
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656737125 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.656737125
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2636015741
Short name T7
Test name
Test status
Simulation time 56847503 ps
CPU time 1.09 seconds
Started Jun 27 06:31:08 PM PDT 24
Finished Jun 27 06:31:12 PM PDT 24
Peak memory 232476 kb
Host smart-50e168dc-afa1-45f3-82b4-d5f2cfd78a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636015741 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2636015741
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2015551210
Short name T690
Test name
Test status
Simulation time 272890117 ps
CPU time 1.27 seconds
Started Jun 27 06:31:08 PM PDT 24
Finished Jun 27 06:31:12 PM PDT 24
Peak memory 219644 kb
Host smart-14631fe5-a1ce-4313-bf23-cd54005930a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015551210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2015551210
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1685654984
Short name T420
Test name
Test status
Simulation time 35150569 ps
CPU time 0.85 seconds
Started Jun 27 06:31:08 PM PDT 24
Finished Jun 27 06:31:12 PM PDT 24
Peak memory 215648 kb
Host smart-eba51f76-582b-49c3-8cd1-46eb8e565786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685654984 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1685654984
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.4018182516
Short name T362
Test name
Test status
Simulation time 24896050 ps
CPU time 0.93 seconds
Started Jun 27 06:31:08 PM PDT 24
Finished Jun 27 06:31:12 PM PDT 24
Peak memory 215336 kb
Host smart-f4314326-b842-4076-8039-02fd41e3930f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018182516 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.4018182516
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1934964537
Short name T477
Test name
Test status
Simulation time 383268758 ps
CPU time 3.68 seconds
Started Jun 27 06:31:11 PM PDT 24
Finished Jun 27 06:31:18 PM PDT 24
Peak memory 215548 kb
Host smart-90506b6b-57bb-492f-a62d-b81dbfc0c86c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934964537 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1934964537
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_alert.3370720714
Short name T875
Test name
Test status
Simulation time 24608942 ps
CPU time 1.12 seconds
Started Jun 27 06:31:12 PM PDT 24
Finished Jun 27 06:31:16 PM PDT 24
Peak memory 219812 kb
Host smart-445e7946-90ba-4337-bd02-0473dadc42b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370720714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3370720714
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.4083651297
Short name T751
Test name
Test status
Simulation time 15509257 ps
CPU time 0.92 seconds
Started Jun 27 06:31:28 PM PDT 24
Finished Jun 27 06:31:31 PM PDT 24
Peak memory 207024 kb
Host smart-8ebbc1da-b263-449f-b626-adb0a0c547ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083651297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.4083651297
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.395372675
Short name T692
Test name
Test status
Simulation time 33809418 ps
CPU time 0.84 seconds
Started Jun 27 06:31:08 PM PDT 24
Finished Jun 27 06:31:12 PM PDT 24
Peak memory 216516 kb
Host smart-42ebcd6c-1421-4f69-b55b-f1b3f5a67c10
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395372675 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.395372675
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1213770368
Short name T132
Test name
Test status
Simulation time 26072563 ps
CPU time 1.07 seconds
Started Jun 27 06:31:25 PM PDT 24
Finished Jun 27 06:31:30 PM PDT 24
Peak memory 220064 kb
Host smart-5e036014-7a73-4830-9ae0-4c8f6df4c58c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213770368 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1213770368
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.2274910745
Short name T538
Test name
Test status
Simulation time 22242122 ps
CPU time 1.16 seconds
Started Jun 27 06:31:09 PM PDT 24
Finished Jun 27 06:31:13 PM PDT 24
Peak memory 218712 kb
Host smart-12ea6b2e-3913-4d28-88a3-fb925c25ff9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274910745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2274910745
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2441310826
Short name T293
Test name
Test status
Simulation time 8201916762 ps
CPU time 113.37 seconds
Started Jun 27 06:31:12 PM PDT 24
Finished Jun 27 06:33:08 PM PDT 24
Peak memory 221156 kb
Host smart-fc34d4fe-b56a-452f-bd5a-24495bd4f525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441310826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2441310826
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3727529445
Short name T29
Test name
Test status
Simulation time 46167174 ps
CPU time 0.88 seconds
Started Jun 27 06:31:09 PM PDT 24
Finished Jun 27 06:31:13 PM PDT 24
Peak memory 215956 kb
Host smart-a03054cc-28a2-4897-b059-f750c053625f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727529445 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3727529445
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.4169131935
Short name T385
Test name
Test status
Simulation time 25226677 ps
CPU time 0.96 seconds
Started Jun 27 06:31:09 PM PDT 24
Finished Jun 27 06:31:13 PM PDT 24
Peak memory 215608 kb
Host smart-c13031c8-468f-41ee-99dd-b3cba3638eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169131935 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.4169131935
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2415925944
Short name T250
Test name
Test status
Simulation time 835377782 ps
CPU time 5.76 seconds
Started Jun 27 06:31:08 PM PDT 24
Finished Jun 27 06:31:17 PM PDT 24
Peak memory 217420 kb
Host smart-1e21df32-2946-4c20-bb5b-41bbea34f959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415925944 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2415925944
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.808990808
Short name T936
Test name
Test status
Simulation time 53860847526 ps
CPU time 1161.94 seconds
Started Jun 27 06:31:09 PM PDT 24
Finished Jun 27 06:50:34 PM PDT 24
Peak memory 221800 kb
Host smart-e023ce76-d8e7-49b3-b1dd-934a47919dcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808990808 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.808990808
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert_test.3390330964
Short name T364
Test name
Test status
Simulation time 192722692 ps
CPU time 1.05 seconds
Started Jun 27 06:31:34 PM PDT 24
Finished Jun 27 06:31:36 PM PDT 24
Peak memory 215520 kb
Host smart-92f97bea-2407-43d2-92ed-b2806b36daef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390330964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3390330964
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1121307615
Short name T115
Test name
Test status
Simulation time 73570145 ps
CPU time 1.1 seconds
Started Jun 27 06:31:25 PM PDT 24
Finished Jun 27 06:31:30 PM PDT 24
Peak memory 217148 kb
Host smart-f64ba70a-b58b-46c5-98a5-9bdc740f5fb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121307615 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1121307615
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2072403715
Short name T908
Test name
Test status
Simulation time 56179797 ps
CPU time 0.9 seconds
Started Jun 27 06:31:23 PM PDT 24
Finished Jun 27 06:31:26 PM PDT 24
Peak memory 220296 kb
Host smart-bd925369-a28a-46d9-80a3-b9486414bd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072403715 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2072403715
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.924180930
Short name T920
Test name
Test status
Simulation time 71698984 ps
CPU time 1.6 seconds
Started Jun 27 06:31:24 PM PDT 24
Finished Jun 27 06:31:28 PM PDT 24
Peak memory 218948 kb
Host smart-52e7662d-38b1-4b26-ae13-0ac5b8e171ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924180930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.924180930
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.855070447
Short name T990
Test name
Test status
Simulation time 31347081 ps
CPU time 0.81 seconds
Started Jun 27 06:31:25 PM PDT 24
Finished Jun 27 06:31:30 PM PDT 24
Peak memory 215936 kb
Host smart-5c638e81-fd11-4c74-b2a0-687d8306f006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855070447 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.855070447
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2475150661
Short name T448
Test name
Test status
Simulation time 17563541 ps
CPU time 1.02 seconds
Started Jun 27 06:31:32 PM PDT 24
Finished Jun 27 06:31:34 PM PDT 24
Peak memory 215668 kb
Host smart-943f5a20-49c5-41da-92a8-ccdf2d800fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475150661 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2475150661
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2802369306
Short name T252
Test name
Test status
Simulation time 546056626 ps
CPU time 3.14 seconds
Started Jun 27 06:31:25 PM PDT 24
Finished Jun 27 06:31:32 PM PDT 24
Peak memory 217532 kb
Host smart-b1292705-a172-4aed-be96-ede74911e544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802369306 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2802369306
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2449442044
Short name T230
Test name
Test status
Simulation time 52024022989 ps
CPU time 878.7 seconds
Started Jun 27 06:31:34 PM PDT 24
Finished Jun 27 06:46:13 PM PDT 24
Peak memory 218804 kb
Host smart-7e4d7cd1-c726-4368-a064-931629f9adde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449442044 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2449442044
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1490977153
Short name T462
Test name
Test status
Simulation time 55564868 ps
CPU time 1.24 seconds
Started Jun 27 06:29:51 PM PDT 24
Finished Jun 27 06:29:59 PM PDT 24
Peak memory 220028 kb
Host smart-2534e07e-521c-4898-92b2-0bc890676e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490977153 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1490977153
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2774024067
Short name T446
Test name
Test status
Simulation time 18382599 ps
CPU time 0.89 seconds
Started Jun 27 06:29:47 PM PDT 24
Finished Jun 27 06:29:55 PM PDT 24
Peak memory 215128 kb
Host smart-f2befb5f-7556-4e36-b14c-39853a2213f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774024067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2774024067
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2684347484
Short name T356
Test name
Test status
Simulation time 31846654 ps
CPU time 0.84 seconds
Started Jun 27 06:29:47 PM PDT 24
Finished Jun 27 06:29:54 PM PDT 24
Peak memory 216388 kb
Host smart-e80f1b2a-6104-4c59-8501-1e452c12d146
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684347484 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2684347484
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1198645179
Short name T782
Test name
Test status
Simulation time 47935955 ps
CPU time 1.35 seconds
Started Jun 27 06:29:48 PM PDT 24
Finished Jun 27 06:29:56 PM PDT 24
Peak memory 217232 kb
Host smart-ac5c2fa3-5244-439c-b018-708bd47901d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198645179 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1198645179
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.696670043
Short name T112
Test name
Test status
Simulation time 31141065 ps
CPU time 1.25 seconds
Started Jun 27 06:29:51 PM PDT 24
Finished Jun 27 06:30:00 PM PDT 24
Peak memory 229884 kb
Host smart-ba270600-d4d9-4a55-9460-f3c64fc5a5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696670043 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.696670043
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.483354972
Short name T935
Test name
Test status
Simulation time 34504465 ps
CPU time 1.45 seconds
Started Jun 27 06:29:47 PM PDT 24
Finished Jun 27 06:29:55 PM PDT 24
Peak memory 218732 kb
Host smart-8d62a146-9813-41d2-ab13-8e7a3a2c2967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483354972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.483354972
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2338543734
Short name T456
Test name
Test status
Simulation time 22665936 ps
CPU time 1.05 seconds
Started Jun 27 06:29:47 PM PDT 24
Finished Jun 27 06:29:55 PM PDT 24
Peak memory 215872 kb
Host smart-61f9397d-deb5-4338-890a-d28f689eb287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338543734 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2338543734
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.4006134777
Short name T842
Test name
Test status
Simulation time 16634878 ps
CPU time 0.97 seconds
Started Jun 27 06:29:51 PM PDT 24
Finished Jun 27 06:29:59 PM PDT 24
Peak memory 207296 kb
Host smart-45f08fc6-545e-476e-a362-90e926448713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006134777 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.4006134777
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3382436690
Short name T53
Test name
Test status
Simulation time 250385131 ps
CPU time 4.44 seconds
Started Jun 27 06:29:48 PM PDT 24
Finished Jun 27 06:29:59 PM PDT 24
Peak memory 235668 kb
Host smart-5ef0c438-92df-4a15-b175-7eee010320db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382436690 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3382436690
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.345779181
Short name T916
Test name
Test status
Simulation time 27107760 ps
CPU time 0.93 seconds
Started Jun 27 06:29:50 PM PDT 24
Finished Jun 27 06:29:59 PM PDT 24
Peak memory 215612 kb
Host smart-ebd0ed81-b856-4777-a355-5653818d462e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345779181 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.345779181
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.706473196
Short name T711
Test name
Test status
Simulation time 992301959 ps
CPU time 4.81 seconds
Started Jun 27 06:29:48 PM PDT 24
Finished Jun 27 06:30:00 PM PDT 24
Peak memory 217752 kb
Host smart-b689cdbc-5424-490d-aec2-3de506b19a29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706473196 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.706473196
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.4103812100
Short name T886
Test name
Test status
Simulation time 24092733123 ps
CPU time 471.11 seconds
Started Jun 27 06:29:50 PM PDT 24
Finished Jun 27 06:37:49 PM PDT 24
Peak memory 224104 kb
Host smart-31851bfc-4219-470b-8097-2fbba814cbed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103812100 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.4103812100
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.3056422850
Short name T822
Test name
Test status
Simulation time 25821666 ps
CPU time 1.23 seconds
Started Jun 27 06:31:24 PM PDT 24
Finished Jun 27 06:31:27 PM PDT 24
Peak memory 219688 kb
Host smart-71bfb73b-4d8a-4d21-9b1d-fecd477333c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056422850 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3056422850
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3808216836
Short name T966
Test name
Test status
Simulation time 13499036 ps
CPU time 0.92 seconds
Started Jun 27 06:31:22 PM PDT 24
Finished Jun 27 06:31:24 PM PDT 24
Peak memory 215344 kb
Host smart-f5a1fabd-7d74-4b1d-9735-7b0d0b9b0b1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808216836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3808216836
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3467382689
Short name T167
Test name
Test status
Simulation time 32129237 ps
CPU time 0.84 seconds
Started Jun 27 06:31:24 PM PDT 24
Finished Jun 27 06:31:27 PM PDT 24
Peak memory 216552 kb
Host smart-da096c3d-c1b5-4507-a91c-0d5969693579
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467382689 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3467382689
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3227878256
Short name T595
Test name
Test status
Simulation time 33424864 ps
CPU time 1.2 seconds
Started Jun 27 06:31:30 PM PDT 24
Finished Jun 27 06:31:32 PM PDT 24
Peak memory 217300 kb
Host smart-0ea67b68-50e9-45b9-b016-4e64efa17e6b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227878256 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3227878256
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2247733466
Short name T121
Test name
Test status
Simulation time 68128014 ps
CPU time 1 seconds
Started Jun 27 06:31:31 PM PDT 24
Finished Jun 27 06:31:32 PM PDT 24
Peak memory 220916 kb
Host smart-7333a382-d7a9-4200-bd83-43b6ba9a7edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247733466 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2247733466
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1025906971
Short name T775
Test name
Test status
Simulation time 46079246 ps
CPU time 1.5 seconds
Started Jun 27 06:31:24 PM PDT 24
Finished Jun 27 06:31:28 PM PDT 24
Peak memory 220536 kb
Host smart-734a8618-1c62-4a60-b4e1-78087f97cedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025906971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1025906971
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1100510997
Short name T26
Test name
Test status
Simulation time 20057099 ps
CPU time 1.07 seconds
Started Jun 27 06:31:27 PM PDT 24
Finished Jun 27 06:31:30 PM PDT 24
Peak memory 216248 kb
Host smart-bc758994-41da-49ec-a4af-82011768ae70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100510997 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1100510997
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3345475056
Short name T597
Test name
Test status
Simulation time 42419006 ps
CPU time 0.88 seconds
Started Jun 27 06:31:23 PM PDT 24
Finished Jun 27 06:31:25 PM PDT 24
Peak memory 215588 kb
Host smart-0a44cd6e-d1d7-4b89-8324-e0af58565dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345475056 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3345475056
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3460655079
Short name T738
Test name
Test status
Simulation time 92100295 ps
CPU time 1.04 seconds
Started Jun 27 06:31:25 PM PDT 24
Finished Jun 27 06:31:30 PM PDT 24
Peak memory 215572 kb
Host smart-0747df04-d5e6-4472-b2f0-a5eb3259c5a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460655079 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3460655079
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1284217246
Short name T32
Test name
Test status
Simulation time 128747622909 ps
CPU time 830.59 seconds
Started Jun 27 06:31:25 PM PDT 24
Finished Jun 27 06:45:19 PM PDT 24
Peak memory 223988 kb
Host smart-e1d74173-723d-471f-bd1c-105b4a57ff95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284217246 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1284217246
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3957457040
Short name T942
Test name
Test status
Simulation time 39886565 ps
CPU time 1.19 seconds
Started Jun 27 06:31:32 PM PDT 24
Finished Jun 27 06:31:34 PM PDT 24
Peak memory 218976 kb
Host smart-be90b6c7-5fdd-42e7-94d7-32c36b9b2200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957457040 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3957457040
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2296146144
Short name T572
Test name
Test status
Simulation time 51553517 ps
CPU time 0.93 seconds
Started Jun 27 06:31:25 PM PDT 24
Finished Jun 27 06:31:29 PM PDT 24
Peak memory 207000 kb
Host smart-bd4210b2-49de-43b9-bc8d-ff4e86e8d641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296146144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2296146144
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1683808670
Short name T173
Test name
Test status
Simulation time 17367039 ps
CPU time 0.83 seconds
Started Jun 27 06:31:23 PM PDT 24
Finished Jun 27 06:31:26 PM PDT 24
Peak memory 216520 kb
Host smart-1bac580b-8df7-4669-809b-2ff17accfbc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683808670 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1683808670
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2525512587
Short name T684
Test name
Test status
Simulation time 88701957 ps
CPU time 1.11 seconds
Started Jun 27 06:31:24 PM PDT 24
Finished Jun 27 06:31:28 PM PDT 24
Peak memory 218540 kb
Host smart-35974a92-206c-48ed-9bc5-6744408b143c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525512587 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2525512587
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2360873709
Short name T8
Test name
Test status
Simulation time 29678153 ps
CPU time 1.29 seconds
Started Jun 27 06:31:27 PM PDT 24
Finished Jun 27 06:31:31 PM PDT 24
Peak memory 220100 kb
Host smart-4b1586c6-f1ed-4e78-bd1b-61bff17838a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360873709 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2360873709
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.308970336
Short name T682
Test name
Test status
Simulation time 34355442 ps
CPU time 1.29 seconds
Started Jun 27 06:31:25 PM PDT 24
Finished Jun 27 06:31:30 PM PDT 24
Peak memory 217604 kb
Host smart-f188f935-c41b-497b-9551-e393a94a7a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308970336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.308970336
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1835701164
Short name T89
Test name
Test status
Simulation time 26149995 ps
CPU time 0.88 seconds
Started Jun 27 06:31:23 PM PDT 24
Finished Jun 27 06:31:26 PM PDT 24
Peak memory 215888 kb
Host smart-e63d3c17-544c-4ace-ba8b-bbd39e2264cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835701164 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1835701164
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1166885192
Short name T436
Test name
Test status
Simulation time 36093575 ps
CPU time 0.88 seconds
Started Jun 27 06:31:23 PM PDT 24
Finished Jun 27 06:31:26 PM PDT 24
Peak memory 207428 kb
Host smart-615465aa-2448-4bfd-accd-df79f6674d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166885192 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1166885192
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3254860793
Short name T880
Test name
Test status
Simulation time 80713007 ps
CPU time 1.4 seconds
Started Jun 27 06:31:32 PM PDT 24
Finished Jun 27 06:31:35 PM PDT 24
Peak memory 215604 kb
Host smart-919541e5-7562-4101-ae14-4995e3901a4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254860793 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3254860793
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2930047654
Short name T233
Test name
Test status
Simulation time 192706101547 ps
CPU time 1628.06 seconds
Started Jun 27 06:31:33 PM PDT 24
Finished Jun 27 06:58:42 PM PDT 24
Peak memory 225288 kb
Host smart-0062b203-c5ff-426b-bddd-7843532c234a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930047654 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2930047654
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.27554032
Short name T76
Test name
Test status
Simulation time 29396028 ps
CPU time 1.21 seconds
Started Jun 27 06:31:25 PM PDT 24
Finished Jun 27 06:31:30 PM PDT 24
Peak memory 221564 kb
Host smart-6e1547c0-5435-4b85-81f1-b4c7ec58c0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27554032 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.27554032
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.103382915
Short name T950
Test name
Test status
Simulation time 17963632 ps
CPU time 1 seconds
Started Jun 27 06:31:34 PM PDT 24
Finished Jun 27 06:31:36 PM PDT 24
Peak memory 215504 kb
Host smart-7c2c1e3a-b863-4714-86aa-12375c48030c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103382915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.103382915
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2020282233
Short name T202
Test name
Test status
Simulation time 39876260 ps
CPU time 0.96 seconds
Started Jun 27 06:31:23 PM PDT 24
Finished Jun 27 06:31:26 PM PDT 24
Peak memory 217232 kb
Host smart-864c5b60-421f-4801-a8a6-b8cccb01f50e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020282233 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2020282233
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1533632529
Short name T976
Test name
Test status
Simulation time 27351289 ps
CPU time 0.89 seconds
Started Jun 27 06:31:27 PM PDT 24
Finished Jun 27 06:31:31 PM PDT 24
Peak memory 219804 kb
Host smart-d9a8db49-b592-4697-9834-2cc8aef18ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533632529 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1533632529
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3768245496
Short name T455
Test name
Test status
Simulation time 46872326 ps
CPU time 1.76 seconds
Started Jun 27 06:31:24 PM PDT 24
Finished Jun 27 06:31:29 PM PDT 24
Peak memory 218928 kb
Host smart-b5c30a92-b726-46a0-8588-87efbfb9bdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768245496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3768245496
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1322980204
Short name T881
Test name
Test status
Simulation time 24402904 ps
CPU time 1.09 seconds
Started Jun 27 06:31:22 PM PDT 24
Finished Jun 27 06:31:25 PM PDT 24
Peak memory 224284 kb
Host smart-e5fda3c7-1977-4c94-b930-a9140ee5ae38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322980204 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1322980204
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.308776307
Short name T354
Test name
Test status
Simulation time 39355941 ps
CPU time 0.91 seconds
Started Jun 27 06:31:22 PM PDT 24
Finished Jun 27 06:31:25 PM PDT 24
Peak memory 215568 kb
Host smart-18a9a73e-fbe1-4c80-a471-9b5480ab3ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308776307 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.308776307
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.4251095419
Short name T577
Test name
Test status
Simulation time 63034120 ps
CPU time 0.92 seconds
Started Jun 27 06:31:26 PM PDT 24
Finished Jun 27 06:31:30 PM PDT 24
Peak memory 206840 kb
Host smart-17ff9de7-334e-4ef4-aeda-e54cf9f5d006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251095419 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.4251095419
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1437498556
Short name T561
Test name
Test status
Simulation time 153575883355 ps
CPU time 1001.58 seconds
Started Jun 27 06:31:23 PM PDT 24
Finished Jun 27 06:48:06 PM PDT 24
Peak memory 221928 kb
Host smart-2238df87-1fc1-4786-a1dc-289c0eacb2e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437498556 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1437498556
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2239477537
Short name T965
Test name
Test status
Simulation time 83210903 ps
CPU time 1.18 seconds
Started Jun 27 06:31:55 PM PDT 24
Finished Jun 27 06:32:00 PM PDT 24
Peak memory 221740 kb
Host smart-938280e0-4630-4612-9a0f-97d99787b523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239477537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2239477537
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3969087902
Short name T518
Test name
Test status
Simulation time 18945935 ps
CPU time 0.98 seconds
Started Jun 27 06:31:52 PM PDT 24
Finished Jun 27 06:31:58 PM PDT 24
Peak memory 206980 kb
Host smart-3282270e-efd1-4ca0-8296-c83b2a59ae22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969087902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3969087902
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3064976280
Short name T355
Test name
Test status
Simulation time 12831030 ps
CPU time 0.86 seconds
Started Jun 27 06:31:49 PM PDT 24
Finished Jun 27 06:31:52 PM PDT 24
Peak memory 216252 kb
Host smart-a6303abb-5c7d-4cdb-9ee1-4fb5cd0f319a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064976280 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3064976280
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3696346209
Short name T66
Test name
Test status
Simulation time 54277840 ps
CPU time 1.51 seconds
Started Jun 27 06:31:51 PM PDT 24
Finished Jun 27 06:31:56 PM PDT 24
Peak memory 217204 kb
Host smart-56f2d40a-3f22-49b7-b905-59cb40a7a1d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696346209 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3696346209
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1159804833
Short name T810
Test name
Test status
Simulation time 67768437 ps
CPU time 1.05 seconds
Started Jun 27 06:31:48 PM PDT 24
Finished Jun 27 06:31:50 PM PDT 24
Peak memory 229864 kb
Host smart-f02f7205-9bbe-43d7-bb3e-4ea747bb1d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159804833 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1159804833
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2370139516
Short name T37
Test name
Test status
Simulation time 245327888 ps
CPU time 1.57 seconds
Started Jun 27 06:31:24 PM PDT 24
Finished Jun 27 06:31:28 PM PDT 24
Peak memory 219092 kb
Host smart-9e2228bd-11e5-4d96-abcb-d8658cfac03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370139516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2370139516
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2287307228
Short name T92
Test name
Test status
Simulation time 27739203 ps
CPU time 0.94 seconds
Started Jun 27 06:31:50 PM PDT 24
Finished Jun 27 06:31:55 PM PDT 24
Peak memory 216232 kb
Host smart-0c3a2caf-4724-4496-83e2-a0cb25fbdd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287307228 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2287307228
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3010895179
Short name T246
Test name
Test status
Simulation time 42969121 ps
CPU time 0.91 seconds
Started Jun 27 06:31:24 PM PDT 24
Finished Jun 27 06:31:27 PM PDT 24
Peak memory 215548 kb
Host smart-ba66a7f3-056a-43b5-bf85-13d3309573ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010895179 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3010895179
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1150526119
Short name T677
Test name
Test status
Simulation time 256934610 ps
CPU time 2.3 seconds
Started Jun 27 06:31:22 PM PDT 24
Finished Jun 27 06:31:26 PM PDT 24
Peak memory 217576 kb
Host smart-bb093647-5e06-4647-9313-69d3bbd103ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150526119 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1150526119
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1709193415
Short name T540
Test name
Test status
Simulation time 47769274566 ps
CPU time 615.54 seconds
Started Jun 27 06:31:32 PM PDT 24
Finished Jun 27 06:41:49 PM PDT 24
Peak memory 219584 kb
Host smart-536591dd-db32-465d-ae6d-278fa2a9114a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709193415 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1709193415
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3962367527
Short name T790
Test name
Test status
Simulation time 92440413 ps
CPU time 1.24 seconds
Started Jun 27 06:31:50 PM PDT 24
Finished Jun 27 06:31:53 PM PDT 24
Peak memory 219988 kb
Host smart-e36f6005-abf6-4588-8d8a-3288abbd311f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962367527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3962367527
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2946399047
Short name T678
Test name
Test status
Simulation time 37860552 ps
CPU time 0.86 seconds
Started Jun 27 06:31:49 PM PDT 24
Finished Jun 27 06:31:51 PM PDT 24
Peak memory 206864 kb
Host smart-b856d612-b398-45d6-b48e-c9c74f23d865
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946399047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2946399047
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3003532873
Short name T200
Test name
Test status
Simulation time 136842160 ps
CPU time 0.9 seconds
Started Jun 27 06:31:52 PM PDT 24
Finished Jun 27 06:31:58 PM PDT 24
Peak memory 216544 kb
Host smart-6f9ce5ee-5b22-437e-8424-e84408d81049
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003532873 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3003532873
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1261937910
Short name T114
Test name
Test status
Simulation time 219163810 ps
CPU time 1.16 seconds
Started Jun 27 06:31:48 PM PDT 24
Finished Jun 27 06:31:50 PM PDT 24
Peak memory 217080 kb
Host smart-fb53ae1a-004d-4621-b056-4cd454ced1fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261937910 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1261937910
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.555813896
Short name T198
Test name
Test status
Simulation time 24497746 ps
CPU time 0.97 seconds
Started Jun 27 06:31:50 PM PDT 24
Finished Jun 27 06:31:53 PM PDT 24
Peak memory 219060 kb
Host smart-90f7628f-b64c-4e1f-bfd1-58633f6c7709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555813896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.555813896
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.901953297
Short name T911
Test name
Test status
Simulation time 37802189 ps
CPU time 1.52 seconds
Started Jun 27 06:31:51 PM PDT 24
Finished Jun 27 06:31:56 PM PDT 24
Peak memory 217928 kb
Host smart-46949bfd-a98f-4130-9ab4-e569f17437f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901953297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.901953297
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1251900780
Short name T431
Test name
Test status
Simulation time 40549355 ps
CPU time 0.91 seconds
Started Jun 27 06:31:54 PM PDT 24
Finished Jun 27 06:31:59 PM PDT 24
Peak memory 215864 kb
Host smart-0f888c74-7516-4492-a2c9-e7eb2adcce8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251900780 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1251900780
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1667754174
Short name T840
Test name
Test status
Simulation time 18420505 ps
CPU time 1 seconds
Started Jun 27 06:31:51 PM PDT 24
Finished Jun 27 06:31:55 PM PDT 24
Peak memory 215580 kb
Host smart-766e601a-6c25-4f5e-88c2-ffc47cd6c9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667754174 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1667754174
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2961754410
Short name T349
Test name
Test status
Simulation time 192484297 ps
CPU time 2.7 seconds
Started Jun 27 06:31:53 PM PDT 24
Finished Jun 27 06:32:00 PM PDT 24
Peak memory 215596 kb
Host smart-42ee3257-e93a-4991-ad6c-5e3925681bea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961754410 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2961754410
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2168258498
Short name T960
Test name
Test status
Simulation time 37928441674 ps
CPU time 477.44 seconds
Started Jun 27 06:31:50 PM PDT 24
Finished Jun 27 06:39:51 PM PDT 24
Peak memory 218280 kb
Host smart-01b015ce-fb93-4b4c-a466-6ea583032892
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168258498 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2168258498
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1753946136
Short name T812
Test name
Test status
Simulation time 47473939 ps
CPU time 1.25 seconds
Started Jun 27 06:31:49 PM PDT 24
Finished Jun 27 06:31:53 PM PDT 24
Peak memory 218956 kb
Host smart-66dadc64-42b4-4e60-8540-a3597ff68edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753946136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1753946136
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2974667582
Short name T500
Test name
Test status
Simulation time 24281405 ps
CPU time 1.1 seconds
Started Jun 27 06:31:50 PM PDT 24
Finished Jun 27 06:31:54 PM PDT 24
Peak memory 207044 kb
Host smart-0c31bbd7-2dd3-4550-9c78-6a65430586a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974667582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2974667582
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2666246892
Short name T154
Test name
Test status
Simulation time 17472305 ps
CPU time 0.86 seconds
Started Jun 27 06:31:51 PM PDT 24
Finished Jun 27 06:31:56 PM PDT 24
Peak memory 215672 kb
Host smart-5a42bc68-344b-4574-acdb-540942e30877
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666246892 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2666246892
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1758435590
Short name T928
Test name
Test status
Simulation time 129235892 ps
CPU time 1.26 seconds
Started Jun 27 06:31:50 PM PDT 24
Finished Jun 27 06:31:54 PM PDT 24
Peak memory 217228 kb
Host smart-c9cea904-fe3f-413e-8b8a-cd1cdb95738b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758435590 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1758435590
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.936726621
Short name T491
Test name
Test status
Simulation time 27005189 ps
CPU time 1 seconds
Started Jun 27 06:31:49 PM PDT 24
Finished Jun 27 06:31:51 PM PDT 24
Peak memory 219060 kb
Host smart-0babe1d5-76e9-4162-a53b-124f0bb937d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936726621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.936726621
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2081297373
Short name T343
Test name
Test status
Simulation time 113762685 ps
CPU time 1.37 seconds
Started Jun 27 06:31:48 PM PDT 24
Finished Jun 27 06:31:50 PM PDT 24
Peak memory 215644 kb
Host smart-d71bf5e2-a1aa-4613-9917-8923bc81f4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081297373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2081297373
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3661781690
Short name T27
Test name
Test status
Simulation time 23419237 ps
CPU time 1.07 seconds
Started Jun 27 06:31:52 PM PDT 24
Finished Jun 27 06:31:58 PM PDT 24
Peak memory 216060 kb
Host smart-2c0aeea1-e95f-4a11-afb0-b1efc753a566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661781690 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3661781690
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1747361205
Short name T566
Test name
Test status
Simulation time 47487594 ps
CPU time 0.92 seconds
Started Jun 27 06:31:50 PM PDT 24
Finished Jun 27 06:31:53 PM PDT 24
Peak memory 215572 kb
Host smart-f8cecab0-2e4a-4076-8b7b-4b5069d738fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747361205 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1747361205
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3008327443
Short name T733
Test name
Test status
Simulation time 200286972 ps
CPU time 3.15 seconds
Started Jun 27 06:31:50 PM PDT 24
Finished Jun 27 06:31:56 PM PDT 24
Peak memory 215752 kb
Host smart-9f9dc25a-c3a9-4b2c-b129-ec23417a6e62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008327443 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3008327443
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3214067744
Short name T268
Test name
Test status
Simulation time 230479290011 ps
CPU time 1722.86 seconds
Started Jun 27 06:31:52 PM PDT 24
Finished Jun 27 07:00:38 PM PDT 24
Peak memory 228044 kb
Host smart-706c0f86-c116-4292-9193-f51dea4acfcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214067744 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3214067744
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2617405809
Short name T122
Test name
Test status
Simulation time 90808285 ps
CPU time 1.3 seconds
Started Jun 27 06:31:51 PM PDT 24
Finished Jun 27 06:31:55 PM PDT 24
Peak memory 220168 kb
Host smart-0e92d7de-98e3-4991-97c2-e31f66fe1508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617405809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2617405809
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1715460307
Short name T656
Test name
Test status
Simulation time 26345982 ps
CPU time 0.91 seconds
Started Jun 27 06:31:50 PM PDT 24
Finished Jun 27 06:31:53 PM PDT 24
Peak memory 215484 kb
Host smart-231cc11c-a607-4ee0-b656-99d9c755c682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715460307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1715460307
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1865234342
Short name T921
Test name
Test status
Simulation time 92140055 ps
CPU time 0.89 seconds
Started Jun 27 06:31:51 PM PDT 24
Finished Jun 27 06:31:55 PM PDT 24
Peak memory 216644 kb
Host smart-722c9e6b-08d8-46a8-9451-c2ea55795c50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865234342 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1865234342
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1838841779
Short name T786
Test name
Test status
Simulation time 142938777 ps
CPU time 1.14 seconds
Started Jun 27 06:31:51 PM PDT 24
Finished Jun 27 06:31:55 PM PDT 24
Peak memory 216012 kb
Host smart-1bcc9a83-0f0b-4686-ba5d-5f4775c8d8b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838841779 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1838841779
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.924247483
Short name T135
Test name
Test status
Simulation time 19587985 ps
CPU time 1.12 seconds
Started Jun 27 06:31:51 PM PDT 24
Finished Jun 27 06:31:56 PM PDT 24
Peak memory 218940 kb
Host smart-aba8c803-10be-45e8-99b1-804b582f0939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924247483 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.924247483
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.3248247687
Short name T620
Test name
Test status
Simulation time 46729747 ps
CPU time 1.41 seconds
Started Jun 27 06:31:49 PM PDT 24
Finished Jun 27 06:31:53 PM PDT 24
Peak memory 218928 kb
Host smart-746b2418-00db-4c5f-b852-9b04ec9cf28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248247687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3248247687
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1448398556
Short name T507
Test name
Test status
Simulation time 49618345 ps
CPU time 0.86 seconds
Started Jun 27 06:31:51 PM PDT 24
Finished Jun 27 06:31:56 PM PDT 24
Peak memory 215484 kb
Host smart-972de19d-5d8e-440c-872d-54f324dc47e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448398556 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1448398556
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2674064613
Short name T229
Test name
Test status
Simulation time 15646795 ps
CPU time 0.97 seconds
Started Jun 27 06:31:48 PM PDT 24
Finished Jun 27 06:31:50 PM PDT 24
Peak memory 215596 kb
Host smart-44c0b5e1-f86f-4283-bafe-72b218da0824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674064613 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2674064613
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.919423510
Short name T430
Test name
Test status
Simulation time 274560332 ps
CPU time 1.58 seconds
Started Jun 27 06:31:52 PM PDT 24
Finished Jun 27 06:31:57 PM PDT 24
Peak memory 215468 kb
Host smart-16a0312b-faa4-4077-9701-bc8ffde78bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919423510 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.919423510
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.4103362280
Short name T830
Test name
Test status
Simulation time 53659608758 ps
CPU time 1351.4 seconds
Started Jun 27 06:31:50 PM PDT 24
Finished Jun 27 06:54:25 PM PDT 24
Peak memory 222600 kb
Host smart-ca4cdc3d-de57-4d8f-89be-af2e42876cdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103362280 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.4103362280
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1087515434
Short name T769
Test name
Test status
Simulation time 21166872 ps
CPU time 1.18 seconds
Started Jun 27 06:31:51 PM PDT 24
Finished Jun 27 06:31:56 PM PDT 24
Peak memory 219756 kb
Host smart-b1222113-2fbf-4f62-a804-2c5d3f7f1e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087515434 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1087515434
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.164553194
Short name T294
Test name
Test status
Simulation time 15479115 ps
CPU time 0.93 seconds
Started Jun 27 06:31:53 PM PDT 24
Finished Jun 27 06:31:58 PM PDT 24
Peak memory 206952 kb
Host smart-f941348b-7755-4dfa-bc1b-bc17c70101ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164553194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.164553194
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1674868163
Short name T849
Test name
Test status
Simulation time 18156103 ps
CPU time 0.88 seconds
Started Jun 27 06:31:52 PM PDT 24
Finished Jun 27 06:31:56 PM PDT 24
Peak memory 216652 kb
Host smart-cb9d7f2d-1a3d-47fd-92fb-6fd2b19f8db2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674868163 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1674868163
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1903209773
Short name T255
Test name
Test status
Simulation time 73115706 ps
CPU time 1.09 seconds
Started Jun 27 06:31:49 PM PDT 24
Finished Jun 27 06:31:51 PM PDT 24
Peak memory 217088 kb
Host smart-db7fde18-fc24-4db9-897c-6da4fbd2af2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903209773 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1903209773
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2992604812
Short name T125
Test name
Test status
Simulation time 20460821 ps
CPU time 1.15 seconds
Started Jun 27 06:31:50 PM PDT 24
Finished Jun 27 06:31:53 PM PDT 24
Peak memory 219848 kb
Host smart-a4d694a6-fd4c-4603-b0f8-687c4d846b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992604812 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2992604812
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.603291030
Short name T970
Test name
Test status
Simulation time 76297098 ps
CPU time 2.37 seconds
Started Jun 27 06:31:51 PM PDT 24
Finished Jun 27 06:31:58 PM PDT 24
Peak memory 220248 kb
Host smart-f07a54e8-3067-4bf4-bdaa-04c7ec307bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603291030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.603291030
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.3444919389
Short name T508
Test name
Test status
Simulation time 67837727 ps
CPU time 0.86 seconds
Started Jun 27 06:31:50 PM PDT 24
Finished Jun 27 06:31:53 PM PDT 24
Peak memory 215520 kb
Host smart-24f0e129-e9c2-421c-85c6-1ecc1c23165a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444919389 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3444919389
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2868611894
Short name T452
Test name
Test status
Simulation time 25426936 ps
CPU time 0.91 seconds
Started Jun 27 06:31:52 PM PDT 24
Finished Jun 27 06:31:56 PM PDT 24
Peak memory 215552 kb
Host smart-8b4f9319-f6a9-481a-80c7-235a6f6e1f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868611894 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2868611894
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2583989272
Short name T878
Test name
Test status
Simulation time 24174968 ps
CPU time 1.05 seconds
Started Jun 27 06:31:49 PM PDT 24
Finished Jun 27 06:31:53 PM PDT 24
Peak memory 207016 kb
Host smart-b67c0d04-871c-4175-a40f-318d59d7565a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583989272 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2583989272
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2878241903
Short name T223
Test name
Test status
Simulation time 73053247509 ps
CPU time 1865.57 seconds
Started Jun 27 06:31:47 PM PDT 24
Finished Jun 27 07:02:53 PM PDT 24
Peak memory 227932 kb
Host smart-d03cd66c-4bf9-4b39-8840-2dc74178fdee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878241903 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2878241903
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.548806942
Short name T411
Test name
Test status
Simulation time 30041687 ps
CPU time 1.14 seconds
Started Jun 27 06:31:52 PM PDT 24
Finished Jun 27 06:31:56 PM PDT 24
Peak memory 215964 kb
Host smart-0e3742f4-54ab-49df-8d8d-a7127d4efe85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548806942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.548806942
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.471523910
Short name T816
Test name
Test status
Simulation time 25084452 ps
CPU time 1.11 seconds
Started Jun 27 06:31:53 PM PDT 24
Finished Jun 27 06:31:58 PM PDT 24
Peak memory 206988 kb
Host smart-fd5027c3-1e66-4722-b365-43febc7661e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471523910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.471523910
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2092054350
Short name T621
Test name
Test status
Simulation time 14079640 ps
CPU time 0.9 seconds
Started Jun 27 06:31:52 PM PDT 24
Finished Jun 27 06:31:57 PM PDT 24
Peak memory 215716 kb
Host smart-3b750b6f-1ef2-47ca-8c87-e18ddea3d994
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092054350 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2092054350
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3575641024
Short name T65
Test name
Test status
Simulation time 32078710 ps
CPU time 1.27 seconds
Started Jun 27 06:31:52 PM PDT 24
Finished Jun 27 06:31:58 PM PDT 24
Peak memory 217208 kb
Host smart-9675cd08-b8ae-4b91-8763-823905144b2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575641024 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3575641024
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2166203056
Short name T562
Test name
Test status
Simulation time 41138466 ps
CPU time 0.86 seconds
Started Jun 27 06:31:51 PM PDT 24
Finished Jun 27 06:31:55 PM PDT 24
Peak memory 218492 kb
Host smart-ff755626-11f2-4189-8492-5accc64c9bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166203056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2166203056
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.745508988
Short name T359
Test name
Test status
Simulation time 53941360 ps
CPU time 1.08 seconds
Started Jun 27 06:31:51 PM PDT 24
Finished Jun 27 06:31:55 PM PDT 24
Peak memory 217516 kb
Host smart-85521f8e-1c48-41b2-9e97-c56d513c4df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745508988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.745508988
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3834449171
Short name T30
Test name
Test status
Simulation time 19727092 ps
CPU time 1.07 seconds
Started Jun 27 06:31:54 PM PDT 24
Finished Jun 27 06:31:59 PM PDT 24
Peak memory 216204 kb
Host smart-d1596dad-1110-4cb2-b6a0-c5b7d052c250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834449171 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3834449171
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2940882692
Short name T655
Test name
Test status
Simulation time 52234593 ps
CPU time 0.97 seconds
Started Jun 27 06:31:52 PM PDT 24
Finished Jun 27 06:31:58 PM PDT 24
Peak memory 215596 kb
Host smart-6a95f4c1-d8ea-4373-94b0-f0d347f3c225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940882692 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2940882692
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3697718556
Short name T249
Test name
Test status
Simulation time 18873182 ps
CPU time 1.03 seconds
Started Jun 27 06:31:53 PM PDT 24
Finished Jun 27 06:31:58 PM PDT 24
Peak memory 206908 kb
Host smart-450f18ee-459e-4349-aa47-21ce037c2cbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697718556 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3697718556
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.804094050
Short name T493
Test name
Test status
Simulation time 107562178991 ps
CPU time 1344.78 seconds
Started Jun 27 06:31:54 PM PDT 24
Finished Jun 27 06:54:23 PM PDT 24
Peak memory 226480 kb
Host smart-9b150ea7-fba5-46c3-940f-d9bae3f56155
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804094050 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.804094050
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1972230952
Short name T38
Test name
Test status
Simulation time 23565442 ps
CPU time 1.17 seconds
Started Jun 27 06:31:52 PM PDT 24
Finished Jun 27 06:31:57 PM PDT 24
Peak memory 215956 kb
Host smart-a7782369-dba0-40c8-afd5-6bab81ad36be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972230952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1972230952
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1701799636
Short name T858
Test name
Test status
Simulation time 21063165 ps
CPU time 0.81 seconds
Started Jun 27 06:31:52 PM PDT 24
Finished Jun 27 06:31:57 PM PDT 24
Peak memory 206976 kb
Host smart-96e9d189-ddd5-4c1d-b0ae-373c4b2cba5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701799636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1701799636
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.222057574
Short name T845
Test name
Test status
Simulation time 23457697 ps
CPU time 0.89 seconds
Started Jun 27 06:31:49 PM PDT 24
Finished Jun 27 06:31:52 PM PDT 24
Peak memory 216724 kb
Host smart-6c6e6777-e8bd-48f3-8177-3011ba26c0e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222057574 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.222057574
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2131630463
Short name T206
Test name
Test status
Simulation time 61542131 ps
CPU time 1.19 seconds
Started Jun 27 06:31:51 PM PDT 24
Finished Jun 27 06:31:56 PM PDT 24
Peak memory 217840 kb
Host smart-a3f0c790-71d7-4ab3-a730-99037fb46195
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131630463 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2131630463
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2561787206
Short name T120
Test name
Test status
Simulation time 35624351 ps
CPU time 0.93 seconds
Started Jun 27 06:31:52 PM PDT 24
Finished Jun 27 06:31:57 PM PDT 24
Peak memory 220100 kb
Host smart-1eefd2c0-277e-4271-9b25-f097c51866ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561787206 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2561787206
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2237121008
Short name T372
Test name
Test status
Simulation time 27055424 ps
CPU time 1.21 seconds
Started Jun 27 06:31:50 PM PDT 24
Finished Jun 27 06:31:54 PM PDT 24
Peak memory 218860 kb
Host smart-ed479178-944b-41ca-ae4b-57f8630e1c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237121008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2237121008
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3186168166
Short name T906
Test name
Test status
Simulation time 20841731 ps
CPU time 1.27 seconds
Started Jun 27 06:31:50 PM PDT 24
Finished Jun 27 06:31:53 PM PDT 24
Peak memory 224288 kb
Host smart-f64402f8-bba0-42d8-9e8c-fbbba3bfa124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186168166 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3186168166
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1081131374
Short name T353
Test name
Test status
Simulation time 16341936 ps
CPU time 1.05 seconds
Started Jun 27 06:31:52 PM PDT 24
Finished Jun 27 06:31:58 PM PDT 24
Peak memory 215532 kb
Host smart-3a87fbe9-2b78-40a4-a38f-7a4cf64d6093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081131374 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1081131374
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2399776963
Short name T251
Test name
Test status
Simulation time 240329983 ps
CPU time 4.35 seconds
Started Jun 27 06:31:52 PM PDT 24
Finished Jun 27 06:32:01 PM PDT 24
Peak memory 217640 kb
Host smart-e871a5e1-a878-4e80-b944-cfdd67d468c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399776963 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2399776963
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.254431620
Short name T482
Test name
Test status
Simulation time 243923237469 ps
CPU time 1625.63 seconds
Started Jun 27 06:31:49 PM PDT 24
Finished Jun 27 06:58:56 PM PDT 24
Peak memory 233200 kb
Host smart-ed3e7679-4156-47ff-9764-5c2a4ac4a7a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254431620 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.254431620
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.196223314
Short name T956
Test name
Test status
Simulation time 26576709 ps
CPU time 1.27 seconds
Started Jun 27 06:29:51 PM PDT 24
Finished Jun 27 06:29:59 PM PDT 24
Peak memory 220716 kb
Host smart-c4b7d25f-21e0-4aec-af09-11978b6854ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196223314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.196223314
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.189410841
Short name T767
Test name
Test status
Simulation time 26453844 ps
CPU time 0.9 seconds
Started Jun 27 06:29:50 PM PDT 24
Finished Jun 27 06:29:59 PM PDT 24
Peak memory 207020 kb
Host smart-7e84fbe5-46a6-4e24-b42d-7886f162b28f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189410841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.189410841
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3886508545
Short name T982
Test name
Test status
Simulation time 10704905 ps
CPU time 0.87 seconds
Started Jun 27 06:29:51 PM PDT 24
Finished Jun 27 06:30:00 PM PDT 24
Peak memory 216500 kb
Host smart-8b154d89-e936-4319-b58c-dd1bb0675c4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886508545 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3886508545
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2714962384
Short name T427
Test name
Test status
Simulation time 58285181 ps
CPU time 1.23 seconds
Started Jun 27 06:29:51 PM PDT 24
Finished Jun 27 06:30:00 PM PDT 24
Peak memory 217156 kb
Host smart-91f37d84-b188-4265-a359-fc78ac0a30f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714962384 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2714962384
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.820638329
Short name T199
Test name
Test status
Simulation time 34756864 ps
CPU time 1.46 seconds
Started Jun 27 06:29:51 PM PDT 24
Finished Jun 27 06:30:01 PM PDT 24
Peak memory 225820 kb
Host smart-df9e6ea2-8cee-4610-9ce0-49c6680f802c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820638329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.820638329
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.4142448140
Short name T78
Test name
Test status
Simulation time 60335384 ps
CPU time 1.2 seconds
Started Jun 27 06:29:52 PM PDT 24
Finished Jun 27 06:30:01 PM PDT 24
Peak memory 220208 kb
Host smart-d14f2fe5-ec6a-43ae-9160-1c3539238bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142448140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.4142448140
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3914559992
Short name T44
Test name
Test status
Simulation time 29272541 ps
CPU time 0.97 seconds
Started Jun 27 06:29:47 PM PDT 24
Finished Jun 27 06:29:55 PM PDT 24
Peak memory 224336 kb
Host smart-b891e7f0-6e92-46c1-b271-0816c4b5904c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914559992 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3914559992
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1122854407
Short name T889
Test name
Test status
Simulation time 49908621 ps
CPU time 0.94 seconds
Started Jun 27 06:29:48 PM PDT 24
Finished Jun 27 06:29:57 PM PDT 24
Peak memory 207440 kb
Host smart-43b496be-142d-476a-b4f7-e6eab62e8ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122854407 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1122854407
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2153785859
Short name T722
Test name
Test status
Simulation time 26792075 ps
CPU time 0.91 seconds
Started Jun 27 06:29:51 PM PDT 24
Finished Jun 27 06:29:59 PM PDT 24
Peak memory 207420 kb
Host smart-99a237d5-b47a-4076-a69a-79b0372e18a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153785859 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2153785859
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3607361206
Short name T749
Test name
Test status
Simulation time 834703135 ps
CPU time 4.78 seconds
Started Jun 27 06:29:51 PM PDT 24
Finished Jun 27 06:30:03 PM PDT 24
Peak memory 217580 kb
Host smart-e4a03707-f0c4-4c12-969a-e0972c3eae87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607361206 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3607361206
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.851135571
Short name T232
Test name
Test status
Simulation time 69496182926 ps
CPU time 1500.25 seconds
Started Jun 27 06:29:52 PM PDT 24
Finished Jun 27 06:55:00 PM PDT 24
Peak memory 223732 kb
Host smart-9add92eb-39ae-4aac-a82c-c4e750d5ac45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851135571 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.851135571
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.2061437301
Short name T46
Test name
Test status
Simulation time 21502397 ps
CPU time 1 seconds
Started Jun 27 06:32:10 PM PDT 24
Finished Jun 27 06:32:15 PM PDT 24
Peak memory 224296 kb
Host smart-5bb9359e-4f6a-44fe-aa42-b7d2ca9c5c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061437301 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2061437301
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1734475335
Short name T732
Test name
Test status
Simulation time 31142744 ps
CPU time 1.28 seconds
Started Jun 27 06:32:14 PM PDT 24
Finished Jun 27 06:32:25 PM PDT 24
Peak memory 218724 kb
Host smart-525efd52-af54-4249-8274-d7a4527dc832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734475335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1734475335
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.358003049
Short name T303
Test name
Test status
Simulation time 28510293 ps
CPU time 1.25 seconds
Started Jun 27 06:32:11 PM PDT 24
Finished Jun 27 06:32:17 PM PDT 24
Peak memory 220128 kb
Host smart-9f9e9cd1-c17d-4702-a15b-a55d6a012416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358003049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.358003049
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.3896772981
Short name T128
Test name
Test status
Simulation time 98966436 ps
CPU time 0.87 seconds
Started Jun 27 06:32:09 PM PDT 24
Finished Jun 27 06:32:12 PM PDT 24
Peak memory 219668 kb
Host smart-ba302638-bd9d-4370-b80c-bacae558358c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896772981 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3896772981
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1103847685
Short name T382
Test name
Test status
Simulation time 35474894 ps
CPU time 1.34 seconds
Started Jun 27 06:32:14 PM PDT 24
Finished Jun 27 06:32:24 PM PDT 24
Peak memory 218784 kb
Host smart-c4cfd6e0-c1f8-4fdb-b156-ce560e96f983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103847685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1103847685
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.3941371565
Short name T178
Test name
Test status
Simulation time 62314224 ps
CPU time 1 seconds
Started Jun 27 06:32:08 PM PDT 24
Finished Jun 27 06:32:11 PM PDT 24
Peak memory 218836 kb
Host smart-e5708753-b139-4d6a-9635-5da8f21593dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941371565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.3941371565
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.1881649452
Short name T55
Test name
Test status
Simulation time 24297097 ps
CPU time 0.97 seconds
Started Jun 27 06:32:10 PM PDT 24
Finished Jun 27 06:32:13 PM PDT 24
Peak memory 219968 kb
Host smart-a0dda1fc-5954-4e77-ba5f-f16a6fce23a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881649452 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1881649452
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2019796612
Short name T688
Test name
Test status
Simulation time 143852793 ps
CPU time 2.16 seconds
Started Jun 27 06:32:09 PM PDT 24
Finished Jun 27 06:32:14 PM PDT 24
Peak memory 220476 kb
Host smart-3ceadfe9-9213-4c7d-9854-2f920e76d82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019796612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2019796612
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.3138941949
Short name T58
Test name
Test status
Simulation time 28201643 ps
CPU time 1.23 seconds
Started Jun 27 06:32:08 PM PDT 24
Finished Jun 27 06:32:11 PM PDT 24
Peak memory 221360 kb
Host smart-b6c33ee5-82b0-4665-b469-23567f4b97e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138941949 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.3138941949
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.1244745526
Short name T826
Test name
Test status
Simulation time 73893078 ps
CPU time 1.07 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:24 PM PDT 24
Peak memory 219892 kb
Host smart-03d0f69c-e45a-4242-8dd8-ddf5903b0967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244745526 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1244745526
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1360456407
Short name T366
Test name
Test status
Simulation time 44525679 ps
CPU time 1.17 seconds
Started Jun 27 06:32:09 PM PDT 24
Finished Jun 27 06:32:12 PM PDT 24
Peak memory 218884 kb
Host smart-4d2047e5-0518-40ee-9343-594f53bed21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360456407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1360456407
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.915474848
Short name T261
Test name
Test status
Simulation time 89855335 ps
CPU time 1.16 seconds
Started Jun 27 06:32:10 PM PDT 24
Finished Jun 27 06:32:14 PM PDT 24
Peak memory 220020 kb
Host smart-838f4996-061a-408a-afab-acc27fc39fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915474848 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.915474848
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.335458829
Short name T205
Test name
Test status
Simulation time 24586905 ps
CPU time 0.96 seconds
Started Jun 27 06:32:14 PM PDT 24
Finished Jun 27 06:32:24 PM PDT 24
Peak memory 218840 kb
Host smart-a82cbe8a-9a72-438a-84ae-28d20cf8af51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335458829 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.335458829
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1137581427
Short name T884
Test name
Test status
Simulation time 100487165 ps
CPU time 1.29 seconds
Started Jun 27 06:32:10 PM PDT 24
Finished Jun 27 06:32:15 PM PDT 24
Peak memory 217992 kb
Host smart-a8dfc2bf-ce68-4bfc-b751-41606f3dd913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137581427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1137581427
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.1909969417
Short name T408
Test name
Test status
Simulation time 331051121 ps
CPU time 1.21 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:22 PM PDT 24
Peak memory 219684 kb
Host smart-ca3a7a13-de0b-492b-93ab-94973c5837e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909969417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.1909969417
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.3968114324
Short name T386
Test name
Test status
Simulation time 21681590 ps
CPU time 1.07 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:23 PM PDT 24
Peak memory 218760 kb
Host smart-81c81b0f-0479-4e5c-9192-26bb57e88ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968114324 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3968114324
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2804136475
Short name T592
Test name
Test status
Simulation time 218443607 ps
CPU time 1.96 seconds
Started Jun 27 06:32:10 PM PDT 24
Finished Jun 27 06:32:17 PM PDT 24
Peak memory 219432 kb
Host smart-a93f868f-f05d-4c9f-9740-fab6e129c910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804136475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2804136475
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.2593519810
Short name T6
Test name
Test status
Simulation time 33831044 ps
CPU time 1 seconds
Started Jun 27 06:32:14 PM PDT 24
Finished Jun 27 06:32:25 PM PDT 24
Peak memory 220244 kb
Host smart-e954a47f-fd42-47d2-b324-4976d9c0d42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593519810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2593519810
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/57.edn_alert.950744922
Short name T633
Test name
Test status
Simulation time 40720963 ps
CPU time 1.1 seconds
Started Jun 27 06:32:11 PM PDT 24
Finished Jun 27 06:32:19 PM PDT 24
Peak memory 220188 kb
Host smart-268d76b6-30ea-4924-b266-2ec0f5915ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950744922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.950744922
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.1867012914
Short name T108
Test name
Test status
Simulation time 36122354 ps
CPU time 1.08 seconds
Started Jun 27 06:32:08 PM PDT 24
Finished Jun 27 06:32:10 PM PDT 24
Peak memory 220208 kb
Host smart-9209b7e5-6878-4ae2-b1e7-97c958b3bbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867012914 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1867012914
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3375176121
Short name T337
Test name
Test status
Simulation time 126135429 ps
CPU time 1.61 seconds
Started Jun 27 06:32:12 PM PDT 24
Finished Jun 27 06:32:21 PM PDT 24
Peak memory 220372 kb
Host smart-ab91480a-b73c-4d9d-aa41-b83c26d21839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375176121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3375176121
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.996071042
Short name T626
Test name
Test status
Simulation time 25880499 ps
CPU time 1.19 seconds
Started Jun 27 06:32:09 PM PDT 24
Finished Jun 27 06:32:13 PM PDT 24
Peak memory 221148 kb
Host smart-f81756c4-c2e9-416c-85ea-02774aaa0db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996071042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.996071042
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.1047850844
Short name T913
Test name
Test status
Simulation time 38374413 ps
CPU time 0.83 seconds
Started Jun 27 06:32:10 PM PDT 24
Finished Jun 27 06:32:15 PM PDT 24
Peak memory 218460 kb
Host smart-e04ee8d4-cf48-4ade-bc12-0e49c27e034a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047850844 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1047850844
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.4223091268
Short name T515
Test name
Test status
Simulation time 30895447 ps
CPU time 1.32 seconds
Started Jun 27 06:32:10 PM PDT 24
Finished Jun 27 06:32:17 PM PDT 24
Peak memory 219952 kb
Host smart-8f05f20d-448b-4a99-8351-940c064ab01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223091268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.4223091268
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.1529948016
Short name T42
Test name
Test status
Simulation time 45483126 ps
CPU time 1.18 seconds
Started Jun 27 06:32:11 PM PDT 24
Finished Jun 27 06:32:17 PM PDT 24
Peak memory 218808 kb
Host smart-4d948a3c-f3fe-4321-9979-58da58a5471b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529948016 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.1529948016
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_genbits.565992273
Short name T874
Test name
Test status
Simulation time 79306423 ps
CPU time 1.87 seconds
Started Jun 27 06:32:11 PM PDT 24
Finished Jun 27 06:32:19 PM PDT 24
Peak memory 217824 kb
Host smart-29a020a5-0ebb-447e-a514-350f1ed7363b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565992273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.565992273
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.600754935
Short name T260
Test name
Test status
Simulation time 76956257 ps
CPU time 1.26 seconds
Started Jun 27 06:29:50 PM PDT 24
Finished Jun 27 06:29:59 PM PDT 24
Peak memory 218756 kb
Host smart-48231211-5d01-4faa-835d-ddd313b3ad49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600754935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.600754935
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3602411954
Short name T610
Test name
Test status
Simulation time 56221289 ps
CPU time 0.9 seconds
Started Jun 27 06:29:52 PM PDT 24
Finished Jun 27 06:30:01 PM PDT 24
Peak memory 207004 kb
Host smart-4063205b-b0f9-4690-a4ef-a82782d903a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602411954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3602411954
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3224397688
Short name T378
Test name
Test status
Simulation time 16770723 ps
CPU time 0.87 seconds
Started Jun 27 06:29:52 PM PDT 24
Finished Jun 27 06:30:01 PM PDT 24
Peak memory 216236 kb
Host smart-67d34899-ab56-42b0-903a-fc6d9d722233
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224397688 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3224397688
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.655619288
Short name T116
Test name
Test status
Simulation time 39843004 ps
CPU time 1.33 seconds
Started Jun 27 06:29:51 PM PDT 24
Finished Jun 27 06:30:01 PM PDT 24
Peak memory 217168 kb
Host smart-0954ec2b-4e87-4cd1-92a8-b48c44212c8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655619288 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.655619288
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1963144852
Short name T740
Test name
Test status
Simulation time 66312011 ps
CPU time 1.12 seconds
Started Jun 27 06:29:53 PM PDT 24
Finished Jun 27 06:30:02 PM PDT 24
Peak memory 220912 kb
Host smart-be4e44c1-f5d2-4195-802d-4d04e157466f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963144852 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1963144852
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1549049594
Short name T410
Test name
Test status
Simulation time 117590870 ps
CPU time 1.36 seconds
Started Jun 27 06:29:49 PM PDT 24
Finished Jun 27 06:29:58 PM PDT 24
Peak memory 220080 kb
Host smart-26547f7b-bcda-4ea8-8d55-628d035a398b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549049594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1549049594
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2856174952
Short name T109
Test name
Test status
Simulation time 30755086 ps
CPU time 1.19 seconds
Started Jun 27 06:29:51 PM PDT 24
Finished Jun 27 06:30:00 PM PDT 24
Peak memory 217016 kb
Host smart-487e7385-4912-4582-8a0d-5488145281d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856174952 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2856174952
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.2736969045
Short name T313
Test name
Test status
Simulation time 18425764 ps
CPU time 1.01 seconds
Started Jun 27 06:29:51 PM PDT 24
Finished Jun 27 06:29:59 PM PDT 24
Peak memory 207408 kb
Host smart-c5921a8c-8030-4fde-b267-99c3a7bc35a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736969045 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2736969045
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3119476195
Short name T947
Test name
Test status
Simulation time 15731508 ps
CPU time 1.08 seconds
Started Jun 27 06:29:51 PM PDT 24
Finished Jun 27 06:29:59 PM PDT 24
Peak memory 215580 kb
Host smart-a5e24902-f0db-494a-8878-df6432983100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119476195 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3119476195
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3644369144
Short name T983
Test name
Test status
Simulation time 134735478 ps
CPU time 1.35 seconds
Started Jun 27 06:29:59 PM PDT 24
Finished Jun 27 06:30:06 PM PDT 24
Peak memory 217640 kb
Host smart-bd40679e-ad14-4e40-8cb8-b82e7015d40c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644369144 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3644369144
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1170303764
Short name T614
Test name
Test status
Simulation time 45627870632 ps
CPU time 995.12 seconds
Started Jun 27 06:29:51 PM PDT 24
Finished Jun 27 06:46:34 PM PDT 24
Peak memory 219252 kb
Host smart-63d5e20a-d596-46cf-8d5f-42caa4fb6e86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170303764 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1170303764
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.2560704722
Short name T444
Test name
Test status
Simulation time 86226136 ps
CPU time 1.16 seconds
Started Jun 27 06:32:11 PM PDT 24
Finished Jun 27 06:32:19 PM PDT 24
Peak memory 215948 kb
Host smart-3904510c-0dc1-4b44-bbe1-d0a258deefa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560704722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.2560704722
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1113927244
Short name T748
Test name
Test status
Simulation time 28765580 ps
CPU time 1.29 seconds
Started Jun 27 06:32:11 PM PDT 24
Finished Jun 27 06:32:17 PM PDT 24
Peak memory 225960 kb
Host smart-1cb5d989-b1fb-4cfc-932e-31cab9e73233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113927244 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1113927244
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3012596519
Short name T21
Test name
Test status
Simulation time 92594819 ps
CPU time 1.34 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:23 PM PDT 24
Peak memory 219420 kb
Host smart-6871ddf2-cd34-4040-936b-2537f3aefea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012596519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3012596519
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.3761482014
Short name T789
Test name
Test status
Simulation time 70651216 ps
CPU time 1.21 seconds
Started Jun 27 06:32:14 PM PDT 24
Finished Jun 27 06:32:25 PM PDT 24
Peak memory 219100 kb
Host smart-780db249-20c4-4dd0-acbe-bbb6f8b216c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761482014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.3761482014
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.2921364727
Short name T603
Test name
Test status
Simulation time 34573592 ps
CPU time 0.95 seconds
Started Jun 27 06:32:10 PM PDT 24
Finished Jun 27 06:32:16 PM PDT 24
Peak memory 219620 kb
Host smart-3f52e0fa-01eb-49b7-a244-f8bb3d783587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921364727 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2921364727
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.589200934
Short name T616
Test name
Test status
Simulation time 50477064 ps
CPU time 1.86 seconds
Started Jun 27 06:32:12 PM PDT 24
Finished Jun 27 06:32:22 PM PDT 24
Peak memory 218884 kb
Host smart-c33d6c4a-5d0a-41c5-b25f-60915e30ece7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589200934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.589200934
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.3449109643
Short name T593
Test name
Test status
Simulation time 86248727 ps
CPU time 1.14 seconds
Started Jun 27 06:32:09 PM PDT 24
Finished Jun 27 06:32:13 PM PDT 24
Peak memory 218768 kb
Host smart-83bdc9ba-7041-4cad-81c3-f1942ecc07cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449109643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.3449109643
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.2984210950
Short name T119
Test name
Test status
Simulation time 48300182 ps
CPU time 0.97 seconds
Started Jun 27 06:32:12 PM PDT 24
Finished Jun 27 06:32:20 PM PDT 24
Peak memory 219856 kb
Host smart-ed2cc735-4477-48e1-b1e0-fb4e59d6b83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984210950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2984210950
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2444343303
Short name T428
Test name
Test status
Simulation time 180470644 ps
CPU time 1.06 seconds
Started Jun 27 06:32:10 PM PDT 24
Finished Jun 27 06:32:15 PM PDT 24
Peak memory 217440 kb
Host smart-ad0f1785-7321-42b1-889b-a397050ce9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444343303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2444343303
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.2192514723
Short name T297
Test name
Test status
Simulation time 51666685 ps
CPU time 1.22 seconds
Started Jun 27 06:32:10 PM PDT 24
Finished Jun 27 06:32:16 PM PDT 24
Peak memory 218896 kb
Host smart-ee74d73f-c456-4d3e-800f-4102ef4130a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192514723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2192514723
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.1419343277
Short name T171
Test name
Test status
Simulation time 19578528 ps
CPU time 1.07 seconds
Started Jun 27 06:32:12 PM PDT 24
Finished Jun 27 06:32:20 PM PDT 24
Peak memory 224236 kb
Host smart-32398743-4118-4db9-9d7d-424eaec16e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419343277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1419343277
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.436953300
Short name T329
Test name
Test status
Simulation time 51294859 ps
CPU time 1.33 seconds
Started Jun 27 06:32:11 PM PDT 24
Finished Jun 27 06:32:18 PM PDT 24
Peak memory 218924 kb
Host smart-d9bcefce-4075-4918-a3e5-ba7487ad0582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436953300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.436953300
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.1714570922
Short name T394
Test name
Test status
Simulation time 36943680 ps
CPU time 1.16 seconds
Started Jun 27 06:32:10 PM PDT 24
Finished Jun 27 06:32:15 PM PDT 24
Peak memory 221128 kb
Host smart-b43dbedf-81f8-457f-b92b-d00cad03f834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714570922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.1714570922
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.1435355295
Short name T113
Test name
Test status
Simulation time 21511822 ps
CPU time 1.39 seconds
Started Jun 27 06:32:10 PM PDT 24
Finished Jun 27 06:32:16 PM PDT 24
Peak memory 230192 kb
Host smart-ece0f856-4e3e-4d21-9210-19ead5a18c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435355295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1435355295
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2556203324
Short name T36
Test name
Test status
Simulation time 40462450 ps
CPU time 1.7 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:22 PM PDT 24
Peak memory 218688 kb
Host smart-1dde5449-1d6f-43de-8071-9e5d46cc7418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556203324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2556203324
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.1721989657
Short name T705
Test name
Test status
Simulation time 31404959 ps
CPU time 1.33 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:22 PM PDT 24
Peak memory 220356 kb
Host smart-5d5a428a-8927-49f7-bae7-412b8b109c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721989657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.1721989657
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.3379617818
Short name T129
Test name
Test status
Simulation time 28914285 ps
CPU time 1.25 seconds
Started Jun 27 06:32:12 PM PDT 24
Finished Jun 27 06:32:20 PM PDT 24
Peak memory 220820 kb
Host smart-ffb3a2cb-bc75-419b-93d0-4ca0f1eae4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379617818 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3379617818
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1402903758
Short name T50
Test name
Test status
Simulation time 258822068 ps
CPU time 1.11 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:23 PM PDT 24
Peak memory 217524 kb
Host smart-e7335d3b-9512-432e-9ec3-d678f8b72384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402903758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1402903758
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.1802632
Short name T505
Test name
Test status
Simulation time 49155992 ps
CPU time 1.17 seconds
Started Jun 27 06:32:12 PM PDT 24
Finished Jun 27 06:32:20 PM PDT 24
Peak memory 216068 kb
Host smart-c91cab5e-eec9-46e4-aec6-9b2ab5b2e664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.1802632
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.2154949358
Short name T185
Test name
Test status
Simulation time 20409249 ps
CPU time 1.21 seconds
Started Jun 27 06:32:12 PM PDT 24
Finished Jun 27 06:32:19 PM PDT 24
Peak memory 224272 kb
Host smart-5334c787-c187-429b-b334-16d2cbcb5514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154949358 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2154949358
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3336115177
Short name T346
Test name
Test status
Simulation time 73865905 ps
CPU time 1.45 seconds
Started Jun 27 06:32:10 PM PDT 24
Finished Jun 27 06:32:14 PM PDT 24
Peak memory 219164 kb
Host smart-c05a62f0-cbfd-460a-888f-a4fd714fbbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336115177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3336115177
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.691707880
Short name T87
Test name
Test status
Simulation time 50074942 ps
CPU time 1.36 seconds
Started Jun 27 06:32:11 PM PDT 24
Finished Jun 27 06:32:18 PM PDT 24
Peak memory 216004 kb
Host smart-475289ed-47c4-4658-82a6-b43bb744f25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691707880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.691707880
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1240272964
Short name T631
Test name
Test status
Simulation time 21354238 ps
CPU time 1.18 seconds
Started Jun 27 06:32:11 PM PDT 24
Finished Jun 27 06:32:17 PM PDT 24
Peak memory 224212 kb
Host smart-f12a4fb6-7298-4bec-bb41-0ddb3b17fda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240272964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1240272964
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3975308982
Short name T545
Test name
Test status
Simulation time 52125429 ps
CPU time 1.88 seconds
Started Jun 27 06:32:12 PM PDT 24
Finished Jun 27 06:32:21 PM PDT 24
Peak memory 218724 kb
Host smart-fe111996-0c82-4359-acd4-ea804d54e014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975308982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3975308982
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.272321130
Short name T314
Test name
Test status
Simulation time 74507606 ps
CPU time 1.22 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:23 PM PDT 24
Peak memory 221312 kb
Host smart-93065a9e-7eee-42a1-abdf-0f304a1296c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272321130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.272321130
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.3964317529
Short name T412
Test name
Test status
Simulation time 25445144 ps
CPU time 0.92 seconds
Started Jun 27 06:32:11 PM PDT 24
Finished Jun 27 06:32:18 PM PDT 24
Peak memory 218512 kb
Host smart-a93c1988-5fe0-40ab-8b47-149bf18b6484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964317529 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3964317529
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2283122285
Short name T709
Test name
Test status
Simulation time 86441799 ps
CPU time 1.48 seconds
Started Jun 27 06:32:08 PM PDT 24
Finished Jun 27 06:32:11 PM PDT 24
Peak memory 219180 kb
Host smart-2d2e8da9-49ba-4ff6-af60-e9046071d6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283122285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2283122285
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.4236459962
Short name T643
Test name
Test status
Simulation time 94350565 ps
CPU time 1.29 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:23 PM PDT 24
Peak memory 218920 kb
Host smart-1db07065-77bb-4c85-b5b2-9c1071160e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236459962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.4236459962
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.3210168787
Short name T980
Test name
Test status
Simulation time 43447829 ps
CPU time 0.83 seconds
Started Jun 27 06:32:12 PM PDT 24
Finished Jun 27 06:32:21 PM PDT 24
Peak memory 218636 kb
Host smart-bc2ee00f-db39-4c74-bd7a-52ae40182e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210168787 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3210168787
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1165282614
Short name T599
Test name
Test status
Simulation time 395224589 ps
CPU time 3.95 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:26 PM PDT 24
Peak memory 219144 kb
Host smart-93752f09-8f2b-4084-b767-f4b27b8dfc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165282614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1165282614
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.211930804
Short name T416
Test name
Test status
Simulation time 105618579 ps
CPU time 1.24 seconds
Started Jun 27 06:29:59 PM PDT 24
Finished Jun 27 06:30:06 PM PDT 24
Peak memory 215784 kb
Host smart-13b02acc-0954-4c86-9848-e796723bb086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211930804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.211930804
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2910776745
Short name T451
Test name
Test status
Simulation time 21810557 ps
CPU time 0.76 seconds
Started Jun 27 06:29:59 PM PDT 24
Finished Jun 27 06:30:05 PM PDT 24
Peak memory 206660 kb
Host smart-294ee9bd-a4b7-4c88-84df-914706797c21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910776745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2910776745
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1746440714
Short name T531
Test name
Test status
Simulation time 12469516 ps
CPU time 0.89 seconds
Started Jun 27 06:30:00 PM PDT 24
Finished Jun 27 06:30:06 PM PDT 24
Peak memory 216796 kb
Host smart-949b4e57-6fa9-41e5-a5fb-4860793c7b9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746440714 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1746440714
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.707428508
Short name T399
Test name
Test status
Simulation time 76373231 ps
CPU time 1.01 seconds
Started Jun 27 06:29:50 PM PDT 24
Finished Jun 27 06:29:58 PM PDT 24
Peak memory 217020 kb
Host smart-fa364dd7-1bb0-4333-8fd3-212b50d3a283
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707428508 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.707428508
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3463944094
Short name T161
Test name
Test status
Simulation time 21121740 ps
CPU time 1.19 seconds
Started Jun 27 06:29:59 PM PDT 24
Finished Jun 27 06:30:06 PM PDT 24
Peak memory 224248 kb
Host smart-2085d1e7-c18a-4a2f-a1e5-2b5b037934ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463944094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3463944094
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3737991264
Short name T463
Test name
Test status
Simulation time 119287219 ps
CPU time 1.86 seconds
Started Jun 27 06:29:49 PM PDT 24
Finished Jun 27 06:29:58 PM PDT 24
Peak memory 219108 kb
Host smart-d1c00f6c-437b-422d-bf19-ca06810de1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737991264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3737991264
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3550074515
Short name T899
Test name
Test status
Simulation time 20838215 ps
CPU time 1.15 seconds
Started Jun 27 06:29:50 PM PDT 24
Finished Jun 27 06:29:58 PM PDT 24
Peak memory 215780 kb
Host smart-2cf3c656-330b-4be4-8083-5e1393f30d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550074515 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3550074515
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.42748764
Short name T24
Test name
Test status
Simulation time 28000915 ps
CPU time 0.95 seconds
Started Jun 27 06:30:00 PM PDT 24
Finished Jun 27 06:30:06 PM PDT 24
Peak memory 207400 kb
Host smart-6abdc383-ac3c-42c6-89c3-204ac043853f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42748764 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.42748764
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1164130097
Short name T910
Test name
Test status
Simulation time 22941204 ps
CPU time 0.94 seconds
Started Jun 27 06:29:51 PM PDT 24
Finished Jun 27 06:29:59 PM PDT 24
Peak memory 215596 kb
Host smart-5b20db1b-df5b-47f4-b918-7e30db94c909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164130097 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1164130097
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3542508975
Short name T392
Test name
Test status
Simulation time 301628675 ps
CPU time 6.3 seconds
Started Jun 27 06:29:59 PM PDT 24
Finished Jun 27 06:30:10 PM PDT 24
Peak memory 219812 kb
Host smart-d1f51f7e-0204-4072-980f-25069e545adc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542508975 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3542508975
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1349286700
Short name T637
Test name
Test status
Simulation time 360355655839 ps
CPU time 2119.1 seconds
Started Jun 27 06:29:48 PM PDT 24
Finished Jun 27 07:05:15 PM PDT 24
Peak memory 227568 kb
Host smart-2f7705cf-9509-41fb-91a0-e18b28abb324
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349286700 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1349286700
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.2642433475
Short name T975
Test name
Test status
Simulation time 134723510 ps
CPU time 1.14 seconds
Started Jun 27 06:32:11 PM PDT 24
Finished Jun 27 06:32:17 PM PDT 24
Peak memory 220096 kb
Host smart-c5a903da-f64c-425e-81da-0c9e27788e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642433475 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.2642433475
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.1645626094
Short name T872
Test name
Test status
Simulation time 43619169 ps
CPU time 0.84 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:23 PM PDT 24
Peak memory 218508 kb
Host smart-dfcfa916-ace2-4ba6-b3df-bcc4a1c33da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645626094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1645626094
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3199998580
Short name T516
Test name
Test status
Simulation time 35735812 ps
CPU time 1.6 seconds
Started Jun 27 06:32:14 PM PDT 24
Finished Jun 27 06:32:24 PM PDT 24
Peak memory 218748 kb
Host smart-e097ea1b-38a9-4eec-aa02-55725f72151b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199998580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3199998580
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.3290139904
Short name T574
Test name
Test status
Simulation time 43822456 ps
CPU time 1.11 seconds
Started Jun 27 06:32:14 PM PDT 24
Finished Jun 27 06:32:25 PM PDT 24
Peak memory 219024 kb
Host smart-4c25c0d9-9471-41a2-b632-bf7ee203a8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290139904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.3290139904
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.4186929707
Short name T138
Test name
Test status
Simulation time 79397227 ps
CPU time 0.97 seconds
Started Jun 27 06:32:12 PM PDT 24
Finished Jun 27 06:32:21 PM PDT 24
Peak memory 220080 kb
Host smart-34e0bbad-6f12-4df5-9fa1-9aa130badcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186929707 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.4186929707
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1317274410
Short name T543
Test name
Test status
Simulation time 65656093 ps
CPU time 1.23 seconds
Started Jun 27 06:32:14 PM PDT 24
Finished Jun 27 06:32:24 PM PDT 24
Peak memory 217704 kb
Host smart-f3ea78c8-acd8-4ed1-97b1-1175b26405b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317274410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1317274410
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.2574433270
Short name T373
Test name
Test status
Simulation time 24589422 ps
CPU time 1.16 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:23 PM PDT 24
Peak memory 219996 kb
Host smart-d237413b-2e21-46e4-b83c-23468394336d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574433270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.2574433270
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3070100745
Short name T210
Test name
Test status
Simulation time 89742838 ps
CPU time 1.06 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:23 PM PDT 24
Peak memory 219908 kb
Host smart-902d0ea7-30b8-4762-b74f-29ae3a6163de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070100745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3070100745
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2801084083
Short name T432
Test name
Test status
Simulation time 45139189 ps
CPU time 1.68 seconds
Started Jun 27 06:32:12 PM PDT 24
Finished Jun 27 06:32:21 PM PDT 24
Peak memory 218848 kb
Host smart-c913df9c-0dc9-46ce-823a-9a6a2371cd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801084083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2801084083
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.3525633287
Short name T142
Test name
Test status
Simulation time 27273688 ps
CPU time 1.26 seconds
Started Jun 27 06:32:12 PM PDT 24
Finished Jun 27 06:32:20 PM PDT 24
Peak memory 218804 kb
Host smart-57bbdf47-6bdd-4762-b9d9-66b57df2e03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525633287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.3525633287
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.3572026885
Short name T797
Test name
Test status
Simulation time 29555159 ps
CPU time 0.88 seconds
Started Jun 27 06:32:15 PM PDT 24
Finished Jun 27 06:32:25 PM PDT 24
Peak memory 218476 kb
Host smart-ddc51741-7321-4f65-9649-3144a84b656f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572026885 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3572026885
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.490109604
Short name T977
Test name
Test status
Simulation time 117269815 ps
CPU time 1.55 seconds
Started Jun 27 06:32:14 PM PDT 24
Finished Jun 27 06:32:25 PM PDT 24
Peak memory 219108 kb
Host smart-bd999029-5738-4317-a9a3-81c0e76536da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490109604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.490109604
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.2984123653
Short name T700
Test name
Test status
Simulation time 25820525 ps
CPU time 1.19 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:23 PM PDT 24
Peak memory 219744 kb
Host smart-72854feb-2ee3-44e1-8258-ff1063ba785a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984123653 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.2984123653
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.4037449355
Short name T744
Test name
Test status
Simulation time 30185890 ps
CPU time 1.26 seconds
Started Jun 27 06:32:12 PM PDT 24
Finished Jun 27 06:32:19 PM PDT 24
Peak memory 215776 kb
Host smart-a2b523e1-b82c-4b87-a0cc-6698d444e006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037449355 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.4037449355
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2871591901
Short name T929
Test name
Test status
Simulation time 69838034 ps
CPU time 1.24 seconds
Started Jun 27 06:32:12 PM PDT 24
Finished Jun 27 06:32:20 PM PDT 24
Peak memory 219088 kb
Host smart-17f008e4-1ee4-483c-af4f-968c7a234843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871591901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2871591901
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.3725848122
Short name T184
Test name
Test status
Simulation time 48883321 ps
CPU time 0.83 seconds
Started Jun 27 06:32:16 PM PDT 24
Finished Jun 27 06:32:28 PM PDT 24
Peak memory 218744 kb
Host smart-954a229b-e808-40b7-a0a0-f0e784a520ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725848122 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3725848122
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.983402383
Short name T336
Test name
Test status
Simulation time 132482751 ps
CPU time 1.44 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:24 PM PDT 24
Peak memory 218948 kb
Host smart-2363cdbb-0d60-48c1-bf45-8aa43decf511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983402383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.983402383
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.2384081353
Short name T88
Test name
Test status
Simulation time 307073926 ps
CPU time 1.24 seconds
Started Jun 27 06:32:16 PM PDT 24
Finished Jun 27 06:32:28 PM PDT 24
Peak memory 220084 kb
Host smart-24c8d903-9deb-4b36-bd16-f126bcfce4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384081353 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.2384081353
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.1814240781
Short name T156
Test name
Test status
Simulation time 18440472 ps
CPU time 1.06 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:23 PM PDT 24
Peak memory 218652 kb
Host smart-dad23619-db3a-4313-974d-1c38fe706835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814240781 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1814240781
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.785340089
Short name T664
Test name
Test status
Simulation time 83446030 ps
CPU time 1.09 seconds
Started Jun 27 06:32:14 PM PDT 24
Finished Jun 27 06:32:25 PM PDT 24
Peak memory 216744 kb
Host smart-b1bdc8e7-4aa7-41e0-a2a9-ae1bc23311aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785340089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.785340089
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.3042268824
Short name T259
Test name
Test status
Simulation time 102666683 ps
CPU time 1.27 seconds
Started Jun 27 06:32:14 PM PDT 24
Finished Jun 27 06:32:24 PM PDT 24
Peak memory 220388 kb
Host smart-348682b8-986c-4ca2-9bf5-3fc540af516a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042268824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.3042268824
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.3881548094
Short name T708
Test name
Test status
Simulation time 56346749 ps
CPU time 1.37 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:23 PM PDT 24
Peak memory 226036 kb
Host smart-c1df4be6-6f8f-4dc7-8e71-ec2ad275a90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881548094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3881548094
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.870114584
Short name T330
Test name
Test status
Simulation time 55260221 ps
CPU time 1.33 seconds
Started Jun 27 06:32:18 PM PDT 24
Finished Jun 27 06:32:30 PM PDT 24
Peak memory 218800 kb
Host smart-632fe4f4-c29d-4705-807f-7ff86fd08097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870114584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.870114584
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.3917398487
Short name T501
Test name
Test status
Simulation time 147700081 ps
CPU time 1.12 seconds
Started Jun 27 06:32:17 PM PDT 24
Finished Jun 27 06:32:29 PM PDT 24
Peak memory 219936 kb
Host smart-28d50433-c143-4cd1-b411-5c4144b16298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917398487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.3917398487
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.3174124024
Short name T834
Test name
Test status
Simulation time 19868272 ps
CPU time 1.09 seconds
Started Jun 27 06:32:17 PM PDT 24
Finished Jun 27 06:32:29 PM PDT 24
Peak memory 219696 kb
Host smart-d1dd5672-5ec3-42cd-b3d2-0a79973437d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174124024 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3174124024
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/79.edn_alert.2741988627
Short name T215
Test name
Test status
Simulation time 27022351 ps
CPU time 1.33 seconds
Started Jun 27 06:32:18 PM PDT 24
Finished Jun 27 06:32:30 PM PDT 24
Peak memory 218984 kb
Host smart-c7eebaef-4f79-4d51-84d9-d1ce60f2cbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741988627 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.2741988627
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_genbits.4038333271
Short name T513
Test name
Test status
Simulation time 27735318 ps
CPU time 1.16 seconds
Started Jun 27 06:32:16 PM PDT 24
Finished Jun 27 06:32:28 PM PDT 24
Peak memory 219992 kb
Host smart-44f0a16c-65a5-49f2-8223-fa46b0be76e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038333271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.4038333271
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.672231123
Short name T927
Test name
Test status
Simulation time 30989583 ps
CPU time 1.39 seconds
Started Jun 27 06:29:49 PM PDT 24
Finished Jun 27 06:29:58 PM PDT 24
Peak memory 215980 kb
Host smart-73a38b66-706d-4c19-ba66-0242207f4be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672231123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.672231123
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.4164254913
Short name T387
Test name
Test status
Simulation time 30389548 ps
CPU time 0.94 seconds
Started Jun 27 06:30:00 PM PDT 24
Finished Jun 27 06:30:06 PM PDT 24
Peak memory 215208 kb
Host smart-cdb6f5b8-ffe1-4111-8cd9-82674912ba55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164254913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.4164254913
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2005355364
Short name T175
Test name
Test status
Simulation time 101104336 ps
CPU time 0.85 seconds
Started Jun 27 06:29:50 PM PDT 24
Finished Jun 27 06:29:59 PM PDT 24
Peak memory 216528 kb
Host smart-29851bfb-1943-4adb-9bac-7cb11e411fb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005355364 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2005355364
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3748709964
Short name T139
Test name
Test status
Simulation time 55262244 ps
CPU time 1.13 seconds
Started Jun 27 06:29:49 PM PDT 24
Finished Jun 27 06:29:57 PM PDT 24
Peak memory 217064 kb
Host smart-859db1d1-7a11-4a48-b473-e14640c3dc9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748709964 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3748709964
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.367083557
Short name T143
Test name
Test status
Simulation time 22683512 ps
CPU time 1.1 seconds
Started Jun 27 06:30:00 PM PDT 24
Finished Jun 27 06:30:06 PM PDT 24
Peak memory 219960 kb
Host smart-c749acc9-1a35-43fd-9bcd-a9c1a9b29ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367083557 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.367083557
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1156669627
Short name T934
Test name
Test status
Simulation time 35353866 ps
CPU time 1.22 seconds
Started Jun 27 06:29:59 PM PDT 24
Finished Jun 27 06:30:06 PM PDT 24
Peak memory 219132 kb
Host smart-4b2c3f20-c79c-4c6c-af66-e84252085894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156669627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1156669627
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2629933666
Short name T5
Test name
Test status
Simulation time 26968679 ps
CPU time 0.86 seconds
Started Jun 27 06:30:00 PM PDT 24
Finished Jun 27 06:30:06 PM PDT 24
Peak memory 215732 kb
Host smart-0d39692c-3fc6-4651-ace6-fc919ef939c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629933666 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2629933666
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.75944740
Short name T961
Test name
Test status
Simulation time 15988282 ps
CPU time 0.98 seconds
Started Jun 27 06:29:51 PM PDT 24
Finished Jun 27 06:30:01 PM PDT 24
Peak memory 207332 kb
Host smart-0d33ff49-990a-45f0-8258-c011d23d078a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75944740 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.75944740
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3635900412
Short name T795
Test name
Test status
Simulation time 40894035 ps
CPU time 0.9 seconds
Started Jun 27 06:29:50 PM PDT 24
Finished Jun 27 06:29:58 PM PDT 24
Peak memory 215584 kb
Host smart-4481e99f-d158-42fe-9d31-d7d7b700c004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635900412 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3635900412
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1738596248
Short name T534
Test name
Test status
Simulation time 336137480 ps
CPU time 3.9 seconds
Started Jun 27 06:29:52 PM PDT 24
Finished Jun 27 06:30:04 PM PDT 24
Peak memory 217660 kb
Host smart-d808ba45-4dd4-47f9-8f5c-5303555135ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738596248 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1738596248
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1499966432
Short name T489
Test name
Test status
Simulation time 53886015136 ps
CPU time 835.31 seconds
Started Jun 27 06:29:49 PM PDT 24
Finished Jun 27 06:43:52 PM PDT 24
Peak memory 224132 kb
Host smart-c50826f7-29b2-438f-ac4b-5442adb52e65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499966432 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1499966432
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.3450338438
Short name T877
Test name
Test status
Simulation time 41446612 ps
CPU time 1.22 seconds
Started Jun 27 06:32:09 PM PDT 24
Finished Jun 27 06:32:11 PM PDT 24
Peak memory 216008 kb
Host smart-fba94c66-13b2-4c6e-b605-d8693c2b8802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450338438 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.3450338438
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.407117871
Short name T915
Test name
Test status
Simulation time 21412237 ps
CPU time 1.02 seconds
Started Jun 27 06:32:20 PM PDT 24
Finished Jun 27 06:32:31 PM PDT 24
Peak memory 218808 kb
Host smart-f28bbce5-8090-4211-ae02-d1a2ffa30e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407117871 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.407117871
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.4118688682
Short name T695
Test name
Test status
Simulation time 166016164 ps
CPU time 1.23 seconds
Started Jun 27 06:32:18 PM PDT 24
Finished Jun 27 06:32:30 PM PDT 24
Peak memory 217676 kb
Host smart-6858a937-9084-4f6f-aa0f-fdd0398ceba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118688682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.4118688682
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.957476055
Short name T630
Test name
Test status
Simulation time 23505675 ps
CPU time 1.22 seconds
Started Jun 27 06:32:18 PM PDT 24
Finished Jun 27 06:32:30 PM PDT 24
Peak memory 220984 kb
Host smart-37ef5a86-a269-4af8-a654-05696969ef61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957476055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.957476055
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.4225584533
Short name T827
Test name
Test status
Simulation time 47746415 ps
CPU time 1.05 seconds
Started Jun 27 06:32:16 PM PDT 24
Finished Jun 27 06:32:28 PM PDT 24
Peak memory 224256 kb
Host smart-af1231bc-4871-4587-9a8a-e9c02af3e7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225584533 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.4225584533
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.397274797
Short name T856
Test name
Test status
Simulation time 23326545 ps
CPU time 1.21 seconds
Started Jun 27 06:32:17 PM PDT 24
Finished Jun 27 06:32:29 PM PDT 24
Peak memory 219752 kb
Host smart-ca721b09-f10d-417c-a6ed-8222481dbbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397274797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.397274797
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.1874504225
Short name T239
Test name
Test status
Simulation time 46310667 ps
CPU time 1.24 seconds
Started Jun 27 06:32:16 PM PDT 24
Finished Jun 27 06:32:28 PM PDT 24
Peak memory 216008 kb
Host smart-bbc609dc-f993-4b65-8bfc-ff9a36a82a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874504225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.1874504225
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.4172758173
Short name T203
Test name
Test status
Simulation time 40069604 ps
CPU time 1.1 seconds
Started Jun 27 06:32:17 PM PDT 24
Finished Jun 27 06:32:29 PM PDT 24
Peak memory 219828 kb
Host smart-f206440d-b794-4e97-b30f-dbd7618baf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172758173 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.4172758173
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2201658895
Short name T333
Test name
Test status
Simulation time 29241455 ps
CPU time 1.22 seconds
Started Jun 27 06:32:16 PM PDT 24
Finished Jun 27 06:32:27 PM PDT 24
Peak memory 217488 kb
Host smart-eb7cb026-35ef-482b-b9ff-7d5e0c510017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201658895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2201658895
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.2516822272
Short name T645
Test name
Test status
Simulation time 98661513 ps
CPU time 1.17 seconds
Started Jun 27 06:32:19 PM PDT 24
Finished Jun 27 06:32:31 PM PDT 24
Peak memory 216004 kb
Host smart-7207456d-4225-4fe7-942e-1003391bf286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516822272 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.2516822272
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.3919841592
Short name T151
Test name
Test status
Simulation time 34231130 ps
CPU time 0.97 seconds
Started Jun 27 06:32:20 PM PDT 24
Finished Jun 27 06:32:31 PM PDT 24
Peak memory 224104 kb
Host smart-a28fc131-5b35-45a2-965a-ec32676e2e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919841592 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3919841592
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.4101096960
Short name T783
Test name
Test status
Simulation time 36771295 ps
CPU time 1.32 seconds
Started Jun 27 06:32:23 PM PDT 24
Finished Jun 27 06:32:33 PM PDT 24
Peak memory 219008 kb
Host smart-b7c8d452-6cd1-4a31-bd33-675a6803a97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101096960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.4101096960
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.3046229913
Short name T741
Test name
Test status
Simulation time 109041038 ps
CPU time 1.29 seconds
Started Jun 27 06:32:10 PM PDT 24
Finished Jun 27 06:32:15 PM PDT 24
Peak memory 218860 kb
Host smart-fdb7c1df-3c9e-407b-a24b-d01afe8d7744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046229913 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.3046229913
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.3450652865
Short name T556
Test name
Test status
Simulation time 24979466 ps
CPU time 1.19 seconds
Started Jun 27 06:32:16 PM PDT 24
Finished Jun 27 06:32:28 PM PDT 24
Peak memory 218840 kb
Host smart-1ce83516-074f-4d9f-8486-bc429ab0402f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450652865 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3450652865
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3068597201
Short name T978
Test name
Test status
Simulation time 44418062 ps
CPU time 1.55 seconds
Started Jun 27 06:32:23 PM PDT 24
Finished Jun 27 06:32:33 PM PDT 24
Peak memory 215616 kb
Host smart-fed360fa-6235-42f3-ba12-296cde46629b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068597201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3068597201
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.2394357188
Short name T564
Test name
Test status
Simulation time 29127801 ps
CPU time 1.19 seconds
Started Jun 27 06:32:15 PM PDT 24
Finished Jun 27 06:32:26 PM PDT 24
Peak memory 218748 kb
Host smart-530795b9-bf94-402e-b030-64e30bb3037d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394357188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.2394357188
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_genbits.2912715238
Short name T40
Test name
Test status
Simulation time 40043773 ps
CPU time 1.17 seconds
Started Jun 27 06:32:15 PM PDT 24
Finished Jun 27 06:32:26 PM PDT 24
Peak memory 217576 kb
Host smart-d12213a0-0df7-497d-8f4d-e66518490904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912715238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2912715238
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.964172601
Short name T526
Test name
Test status
Simulation time 120636529 ps
CPU time 1.11 seconds
Started Jun 27 06:32:15 PM PDT 24
Finished Jun 27 06:32:25 PM PDT 24
Peak memory 219596 kb
Host smart-6b916adc-1a1f-434a-8e7c-a33e161ca351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964172601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.964172601
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.4066378738
Short name T707
Test name
Test status
Simulation time 19837450 ps
CPU time 1.05 seconds
Started Jun 27 06:32:15 PM PDT 24
Finished Jun 27 06:32:26 PM PDT 24
Peak memory 219724 kb
Host smart-a52674e7-300b-4eed-96f0-160a7c66c9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066378738 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.4066378738
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.4199677556
Short name T869
Test name
Test status
Simulation time 51774667 ps
CPU time 1.85 seconds
Started Jun 27 06:32:23 PM PDT 24
Finished Jun 27 06:32:33 PM PDT 24
Peak memory 219044 kb
Host smart-173f29cf-3b02-4de6-9c9b-45fb4d448fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199677556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.4199677556
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.1555074803
Short name T778
Test name
Test status
Simulation time 32483921 ps
CPU time 1.22 seconds
Started Jun 27 06:32:15 PM PDT 24
Finished Jun 27 06:32:26 PM PDT 24
Peak memory 219788 kb
Host smart-c8ae9919-34b1-462d-9cb9-fcaf9cf455bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555074803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.1555074803
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.4048295633
Short name T183
Test name
Test status
Simulation time 44618275 ps
CPU time 1.03 seconds
Started Jun 27 06:32:23 PM PDT 24
Finished Jun 27 06:32:33 PM PDT 24
Peak memory 224124 kb
Host smart-e9d392f5-4dee-4aac-a82d-d39718fa9d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048295633 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.4048295633
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.591989535
Short name T925
Test name
Test status
Simulation time 52038558 ps
CPU time 1.37 seconds
Started Jun 27 06:32:10 PM PDT 24
Finished Jun 27 06:32:16 PM PDT 24
Peak memory 218900 kb
Host smart-757d82cd-3046-4aa0-971b-3ef8f440362e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591989535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.591989535
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.510154610
Short name T61
Test name
Test status
Simulation time 119913551 ps
CPU time 1.27 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:22 PM PDT 24
Peak memory 219972 kb
Host smart-1f765015-a382-4e45-9e35-9ae873d9d7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510154610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.510154610
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.787778091
Short name T871
Test name
Test status
Simulation time 24807104 ps
CPU time 1 seconds
Started Jun 27 06:32:14 PM PDT 24
Finished Jun 27 06:32:24 PM PDT 24
Peak memory 220120 kb
Host smart-5432230b-c634-4dea-88cf-76947abf5021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787778091 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.787778091
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.608374242
Short name T671
Test name
Test status
Simulation time 41051748 ps
CPU time 1.14 seconds
Started Jun 27 06:32:14 PM PDT 24
Finished Jun 27 06:32:24 PM PDT 24
Peak memory 217624 kb
Host smart-5b54e9de-3a4f-4d3d-a3e5-9c75597a3528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608374242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.608374242
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.803241498
Short name T952
Test name
Test status
Simulation time 41806700 ps
CPU time 1.16 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:23 PM PDT 24
Peak memory 218836 kb
Host smart-b2b8ab36-c9d9-4ba3-9969-495bb45997ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803241498 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.803241498
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.1800962968
Short name T152
Test name
Test status
Simulation time 18847893 ps
CPU time 1.16 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:23 PM PDT 24
Peak memory 224296 kb
Host smart-fe95ebb2-2eca-4d9e-9e16-8fd289d09721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800962968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1800962968
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3943830348
Short name T326
Test name
Test status
Simulation time 157001520 ps
CPU time 1.24 seconds
Started Jun 27 06:32:14 PM PDT 24
Finished Jun 27 06:32:25 PM PDT 24
Peak memory 220388 kb
Host smart-3e85c9f6-830e-461d-9005-110a178f62a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943830348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3943830348
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1641654808
Short name T905
Test name
Test status
Simulation time 79757649 ps
CPU time 1.16 seconds
Started Jun 27 06:29:52 PM PDT 24
Finished Jun 27 06:30:01 PM PDT 24
Peak memory 218712 kb
Host smart-cac20e47-252a-4260-968f-d772cdf2dd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641654808 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1641654808
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2627309448
Short name T376
Test name
Test status
Simulation time 42152284 ps
CPU time 0.89 seconds
Started Jun 27 06:29:53 PM PDT 24
Finished Jun 27 06:30:02 PM PDT 24
Peak memory 207128 kb
Host smart-661190b0-2d1b-4d75-b321-a84c8d87c869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627309448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2627309448
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1883795513
Short name T186
Test name
Test status
Simulation time 10733813 ps
CPU time 0.9 seconds
Started Jun 27 06:29:53 PM PDT 24
Finished Jun 27 06:30:01 PM PDT 24
Peak memory 216576 kb
Host smart-bd474e2e-dfa9-473e-a919-d42103e465d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883795513 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1883795513
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_err.1212876647
Short name T724
Test name
Test status
Simulation time 79028170 ps
CPU time 0.83 seconds
Started Jun 27 06:29:59 PM PDT 24
Finished Jun 27 06:30:05 PM PDT 24
Peak memory 218688 kb
Host smart-c330a1d5-f74d-4579-8591-a1282250c58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212876647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1212876647
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3404281998
Short name T894
Test name
Test status
Simulation time 235108525 ps
CPU time 1.51 seconds
Started Jun 27 06:29:48 PM PDT 24
Finished Jun 27 06:29:57 PM PDT 24
Peak memory 219476 kb
Host smart-8e283576-b401-46ab-8b7c-7416c8d0edb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404281998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3404281998
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2404442018
Short name T583
Test name
Test status
Simulation time 44272204 ps
CPU time 0.86 seconds
Started Jun 27 06:29:49 PM PDT 24
Finished Jun 27 06:29:57 PM PDT 24
Peak memory 215672 kb
Host smart-cb1ced14-61e1-4e4a-9eae-a9ef9457eb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404442018 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2404442018
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3341478593
Short name T23
Test name
Test status
Simulation time 22437337 ps
CPU time 0.95 seconds
Started Jun 27 06:29:51 PM PDT 24
Finished Jun 27 06:29:59 PM PDT 24
Peak memory 207392 kb
Host smart-e792894e-94e4-40b8-a084-368b80ecd1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341478593 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3341478593
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.4118711456
Short name T747
Test name
Test status
Simulation time 41898812 ps
CPU time 0.86 seconds
Started Jun 27 06:29:58 PM PDT 24
Finished Jun 27 06:30:05 PM PDT 24
Peak memory 215604 kb
Host smart-04081fa5-197c-429f-85e2-996c75b2a241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118711456 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.4118711456
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1612855378
Short name T403
Test name
Test status
Simulation time 380353526 ps
CPU time 7.36 seconds
Started Jun 27 06:29:52 PM PDT 24
Finished Jun 27 06:30:07 PM PDT 24
Peak memory 215612 kb
Host smart-c49da9a7-f352-48f8-a3aa-1187a2eea924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612855378 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1612855378
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2219797181
Short name T973
Test name
Test status
Simulation time 153351028522 ps
CPU time 883.26 seconds
Started Jun 27 06:29:59 PM PDT 24
Finished Jun 27 06:44:48 PM PDT 24
Peak memory 223996 kb
Host smart-48bcca59-3413-4db6-b426-dcd217853c05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219797181 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2219797181
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.997252203
Short name T141
Test name
Test status
Simulation time 164804641 ps
CPU time 1.36 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:24 PM PDT 24
Peak memory 218872 kb
Host smart-9bc084fc-44d1-4fd9-8fb7-b72175f4ac39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997252203 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.997252203
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.4146832101
Short name T440
Test name
Test status
Simulation time 73962741 ps
CPU time 0.95 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:23 PM PDT 24
Peak memory 224136 kb
Host smart-92762577-952d-4b22-b48e-7ab68f6c1ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146832101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.4146832101
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2822164298
Short name T890
Test name
Test status
Simulation time 64777143 ps
CPU time 1.1 seconds
Started Jun 27 06:32:11 PM PDT 24
Finished Jun 27 06:32:18 PM PDT 24
Peak memory 217644 kb
Host smart-fe305422-37d1-4f0e-8fb2-b39aa77d5d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822164298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2822164298
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.2862293444
Short name T846
Test name
Test status
Simulation time 40338225 ps
CPU time 1.13 seconds
Started Jun 27 06:32:17 PM PDT 24
Finished Jun 27 06:32:29 PM PDT 24
Peak memory 220028 kb
Host smart-18b22b84-1fa5-4cd5-bba2-770608fa7e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862293444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.2862293444
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.3808191294
Short name T665
Test name
Test status
Simulation time 33716713 ps
CPU time 0.83 seconds
Started Jun 27 06:32:17 PM PDT 24
Finished Jun 27 06:32:28 PM PDT 24
Peak memory 218396 kb
Host smart-7e0bef1b-3ffe-463e-94e8-ae607bbd346a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808191294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3808191294
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3681081697
Short name T647
Test name
Test status
Simulation time 51799415 ps
CPU time 1.19 seconds
Started Jun 27 06:32:14 PM PDT 24
Finished Jun 27 06:32:24 PM PDT 24
Peak memory 218956 kb
Host smart-0f537338-5e0e-4bcc-a258-884e3acf35e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681081697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3681081697
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.258279308
Short name T971
Test name
Test status
Simulation time 42631066 ps
CPU time 1.14 seconds
Started Jun 27 06:32:14 PM PDT 24
Finished Jun 27 06:32:25 PM PDT 24
Peak memory 217912 kb
Host smart-1e767df2-f0b5-461b-b538-8cabd22e1c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258279308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.258279308
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.257665225
Short name T145
Test name
Test status
Simulation time 61184609 ps
CPU time 1.11 seconds
Started Jun 27 06:32:17 PM PDT 24
Finished Jun 27 06:32:28 PM PDT 24
Peak memory 229992 kb
Host smart-49239fd2-3159-411d-820f-4c1072e3683a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257665225 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.257665225
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1826676965
Short name T295
Test name
Test status
Simulation time 66385374 ps
CPU time 1.38 seconds
Started Jun 27 06:32:12 PM PDT 24
Finished Jun 27 06:32:21 PM PDT 24
Peak memory 218772 kb
Host smart-e9a6d8c8-5a38-423b-a3f9-48550c8c96cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826676965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1826676965
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.1551568651
Short name T189
Test name
Test status
Simulation time 45356995 ps
CPU time 1.25 seconds
Started Jun 27 06:32:11 PM PDT 24
Finished Jun 27 06:32:18 PM PDT 24
Peak memory 220392 kb
Host smart-1859ed85-36aa-40d2-88a6-179080f7646d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551568651 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.1551568651
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.3793699817
Short name T73
Test name
Test status
Simulation time 17926219 ps
CPU time 0.99 seconds
Started Jun 27 06:32:17 PM PDT 24
Finished Jun 27 06:32:29 PM PDT 24
Peak memory 218632 kb
Host smart-ffcb9b29-81ef-43d9-98c3-51409c032152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793699817 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3793699817
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2789073814
Short name T951
Test name
Test status
Simulation time 39507101 ps
CPU time 1.34 seconds
Started Jun 27 06:32:17 PM PDT 24
Finished Jun 27 06:32:29 PM PDT 24
Peak memory 217480 kb
Host smart-37f12c90-b73d-49c1-bfed-9b755b20604e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789073814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2789073814
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.2444863862
Short name T731
Test name
Test status
Simulation time 53312397 ps
CPU time 1.23 seconds
Started Jun 27 06:32:17 PM PDT 24
Finished Jun 27 06:32:29 PM PDT 24
Peak memory 221272 kb
Host smart-21ef486b-abb3-4808-bfb5-72c324b10fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444863862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.2444863862
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1415131380
Short name T575
Test name
Test status
Simulation time 34359631 ps
CPU time 0.83 seconds
Started Jun 27 06:32:16 PM PDT 24
Finished Jun 27 06:32:28 PM PDT 24
Peak memory 218756 kb
Host smart-e1549d94-a6ee-424d-b78f-15463dba72bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415131380 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1415131380
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1386131640
Short name T536
Test name
Test status
Simulation time 61325943 ps
CPU time 1.05 seconds
Started Jun 27 06:32:17 PM PDT 24
Finished Jun 27 06:32:29 PM PDT 24
Peak memory 220276 kb
Host smart-46056f80-689b-4f90-ab1e-c1058c1ec6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386131640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1386131640
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.2183171419
Short name T813
Test name
Test status
Simulation time 62347866 ps
CPU time 1.09 seconds
Started Jun 27 06:32:17 PM PDT 24
Finished Jun 27 06:32:29 PM PDT 24
Peak memory 219720 kb
Host smart-d1ef8bdc-f37f-4d63-878b-5b3228fa3d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183171419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.2183171419
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.853569187
Short name T157
Test name
Test status
Simulation time 20196112 ps
CPU time 1.08 seconds
Started Jun 27 06:32:18 PM PDT 24
Finished Jun 27 06:32:30 PM PDT 24
Peak memory 218800 kb
Host smart-305c4868-ad63-489d-b9f7-0d9d41bdeb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853569187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.853569187
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.4288994359
Short name T718
Test name
Test status
Simulation time 60631916 ps
CPU time 1.46 seconds
Started Jun 27 06:32:16 PM PDT 24
Finished Jun 27 06:32:28 PM PDT 24
Peak memory 219128 kb
Host smart-23870b93-b889-45b5-a389-182485a0e1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288994359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.4288994359
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1665257616
Short name T365
Test name
Test status
Simulation time 53163475 ps
CPU time 1.06 seconds
Started Jun 27 06:32:20 PM PDT 24
Finished Jun 27 06:32:31 PM PDT 24
Peak memory 220640 kb
Host smart-ce9e165d-73d1-4d82-9c5e-da7b12d5bcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665257616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1665257616
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.3065811001
Short name T803
Test name
Test status
Simulation time 63508516 ps
CPU time 1.11 seconds
Started Jun 27 06:32:20 PM PDT 24
Finished Jun 27 06:32:31 PM PDT 24
Peak memory 220976 kb
Host smart-2860ea00-e955-4b4d-8639-31a682440977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065811001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3065811001
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3304189943
Short name T651
Test name
Test status
Simulation time 54783946 ps
CPU time 1.22 seconds
Started Jun 27 06:32:13 PM PDT 24
Finished Jun 27 06:32:21 PM PDT 24
Peak memory 218748 kb
Host smart-4c101f11-60e6-48cd-8468-0d05f57eee2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304189943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3304189943
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.475380186
Short name T530
Test name
Test status
Simulation time 54972560 ps
CPU time 1.22 seconds
Started Jun 27 06:32:16 PM PDT 24
Finished Jun 27 06:32:26 PM PDT 24
Peak memory 220000 kb
Host smart-aaa2ccb7-bd85-4a55-a295-1ee1ce82969f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475380186 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.475380186
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.3658187633
Short name T192
Test name
Test status
Simulation time 31302654 ps
CPU time 0.98 seconds
Started Jun 27 06:32:12 PM PDT 24
Finished Jun 27 06:32:20 PM PDT 24
Peak memory 229620 kb
Host smart-14631648-3a75-4d91-a3dd-c640ca6ad691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658187633 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3658187633
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.550364828
Short name T943
Test name
Test status
Simulation time 42943235 ps
CPU time 1.56 seconds
Started Jun 27 06:32:20 PM PDT 24
Finished Jun 27 06:32:31 PM PDT 24
Peak memory 220288 kb
Host smart-fcc1690a-a0bb-4a85-bb72-d7a42f0a99b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550364828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.550364828
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.985696441
Short name T127
Test name
Test status
Simulation time 28891333 ps
CPU time 1.3 seconds
Started Jun 27 06:32:15 PM PDT 24
Finished Jun 27 06:32:26 PM PDT 24
Peak memory 218808 kb
Host smart-f5a541ac-c619-4cf7-84df-5e8c35ab4805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985696441 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.985696441
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.2545909556
Short name T47
Test name
Test status
Simulation time 23900627 ps
CPU time 1.08 seconds
Started Jun 27 06:32:15 PM PDT 24
Finished Jun 27 06:32:26 PM PDT 24
Peak memory 229796 kb
Host smart-353fe535-5f3f-44aa-ae60-65b0e92e45cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545909556 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2545909556
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.4185208464
Short name T77
Test name
Test status
Simulation time 574225019 ps
CPU time 5.23 seconds
Started Jun 27 06:32:20 PM PDT 24
Finished Jun 27 06:32:35 PM PDT 24
Peak memory 219368 kb
Host smart-5a0ff0b8-085e-4535-8a2f-4a72c1fcd606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185208464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.4185208464
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.1594199838
Short name T640
Test name
Test status
Simulation time 101068002 ps
CPU time 1.12 seconds
Started Jun 27 06:32:23 PM PDT 24
Finished Jun 27 06:32:33 PM PDT 24
Peak memory 216052 kb
Host smart-8623ba2b-9d46-4b32-bf9d-a869e606ed61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594199838 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.1594199838
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.4054078006
Short name T211
Test name
Test status
Simulation time 39976668 ps
CPU time 0.86 seconds
Started Jun 27 06:32:24 PM PDT 24
Finished Jun 27 06:32:33 PM PDT 24
Peak memory 218848 kb
Host smart-338fd30c-2393-44f6-b4c2-54a4db3be904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054078006 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.4054078006
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2485426954
Short name T459
Test name
Test status
Simulation time 34989153 ps
CPU time 1.11 seconds
Started Jun 27 06:32:16 PM PDT 24
Finished Jun 27 06:32:28 PM PDT 24
Peak memory 217700 kb
Host smart-8ab8777f-7f7e-4d99-8b39-1eb458be1766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485426954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2485426954
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%