Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.53 98.25 93.97 97.02 91.28 96.37 99.77 92.08


Total test records in report: 1130
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1024 /workspace/coverage/cover_reg_top/33.edn_intr_test.2107238128 Jun 28 06:00:30 PM PDT 24 Jun 28 06:00:41 PM PDT 24 16222264 ps
T1025 /workspace/coverage/cover_reg_top/16.edn_tl_errors.872566026 Jun 28 06:00:22 PM PDT 24 Jun 28 06:00:31 PM PDT 24 230715227 ps
T1026 /workspace/coverage/cover_reg_top/34.edn_intr_test.1932541832 Jun 28 06:00:28 PM PDT 24 Jun 28 06:00:39 PM PDT 24 39443107 ps
T284 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1488676893 Jun 28 06:00:11 PM PDT 24 Jun 28 06:00:16 PM PDT 24 37929966 ps
T1027 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3588777294 Jun 28 06:00:10 PM PDT 24 Jun 28 06:00:15 PM PDT 24 42653566 ps
T301 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2163024121 Jun 28 06:00:22 PM PDT 24 Jun 28 06:00:30 PM PDT 24 90518217 ps
T285 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2154039379 Jun 28 06:00:23 PM PDT 24 Jun 28 06:00:30 PM PDT 24 13419089 ps
T1028 /workspace/coverage/cover_reg_top/35.edn_intr_test.1043807160 Jun 28 06:00:28 PM PDT 24 Jun 28 06:00:40 PM PDT 24 46144829 ps
T1029 /workspace/coverage/cover_reg_top/37.edn_intr_test.569363367 Jun 28 06:00:28 PM PDT 24 Jun 28 06:00:40 PM PDT 24 66823253 ps
T286 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2613663517 Jun 28 06:00:07 PM PDT 24 Jun 28 06:00:10 PM PDT 24 124535416 ps
T263 /workspace/coverage/cover_reg_top/17.edn_csr_rw.711206224 Jun 28 06:00:23 PM PDT 24 Jun 28 06:00:30 PM PDT 24 15419340 ps
T1030 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.194010585 Jun 28 06:00:19 PM PDT 24 Jun 28 06:00:23 PM PDT 24 74290876 ps
T1031 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2373729529 Jun 28 06:00:12 PM PDT 24 Jun 28 06:00:19 PM PDT 24 291196443 ps
T303 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.425656174 Jun 28 06:00:19 PM PDT 24 Jun 28 06:00:24 PM PDT 24 49752205 ps
T1032 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.188020550 Jun 28 06:00:18 PM PDT 24 Jun 28 06:00:22 PM PDT 24 19907870 ps
T1033 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2745664810 Jun 28 06:00:09 PM PDT 24 Jun 28 06:00:13 PM PDT 24 50732586 ps
T1034 /workspace/coverage/cover_reg_top/41.edn_intr_test.3933625062 Jun 28 06:00:27 PM PDT 24 Jun 28 06:00:37 PM PDT 24 46910896 ps
T1035 /workspace/coverage/cover_reg_top/46.edn_intr_test.2346023343 Jun 28 06:00:25 PM PDT 24 Jun 28 06:00:35 PM PDT 24 56879489 ps
T1036 /workspace/coverage/cover_reg_top/17.edn_intr_test.3300088809 Jun 28 06:00:24 PM PDT 24 Jun 28 06:00:33 PM PDT 24 56845869 ps
T1037 /workspace/coverage/cover_reg_top/16.edn_csr_rw.2875466740 Jun 28 06:00:23 PM PDT 24 Jun 28 06:00:29 PM PDT 24 12828707 ps
T1038 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1880090142 Jun 28 06:00:25 PM PDT 24 Jun 28 06:00:34 PM PDT 24 31104867 ps
T1039 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.584557543 Jun 28 06:00:25 PM PDT 24 Jun 28 06:00:34 PM PDT 24 20516704 ps
T1040 /workspace/coverage/cover_reg_top/23.edn_intr_test.2518133053 Jun 28 06:00:25 PM PDT 24 Jun 28 06:00:35 PM PDT 24 14598332 ps
T264 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3101662787 Jun 28 06:00:24 PM PDT 24 Jun 28 06:00:31 PM PDT 24 24269236 ps
T1041 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3865353833 Jun 28 06:00:28 PM PDT 24 Jun 28 06:00:39 PM PDT 24 94376178 ps
T1042 /workspace/coverage/cover_reg_top/18.edn_intr_test.2111888579 Jun 28 06:00:28 PM PDT 24 Jun 28 06:00:39 PM PDT 24 12960959 ps
T1043 /workspace/coverage/cover_reg_top/44.edn_intr_test.1859768778 Jun 28 06:00:23 PM PDT 24 Jun 28 06:00:30 PM PDT 24 120337737 ps
T1044 /workspace/coverage/cover_reg_top/24.edn_intr_test.4040133994 Jun 28 06:00:19 PM PDT 24 Jun 28 06:00:23 PM PDT 24 36894148 ps
T1045 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.777337386 Jun 28 06:00:09 PM PDT 24 Jun 28 06:00:14 PM PDT 24 160984435 ps
T1046 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2870332694 Jun 28 06:00:10 PM PDT 24 Jun 28 06:00:16 PM PDT 24 41303714 ps
T1047 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1394187799 Jun 28 06:00:23 PM PDT 24 Jun 28 06:00:31 PM PDT 24 165503275 ps
T265 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1732868864 Jun 28 06:00:11 PM PDT 24 Jun 28 06:00:16 PM PDT 24 22920343 ps
T1048 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4040392364 Jun 28 06:00:12 PM PDT 24 Jun 28 06:00:18 PM PDT 24 32231069 ps
T271 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2269758767 Jun 28 06:00:08 PM PDT 24 Jun 28 06:00:12 PM PDT 24 49713373 ps
T1049 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.176303866 Jun 28 06:00:09 PM PDT 24 Jun 28 06:00:15 PM PDT 24 94745617 ps
T1050 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.4273912947 Jun 28 06:00:17 PM PDT 24 Jun 28 06:00:21 PM PDT 24 142226134 ps
T1051 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.808354661 Jun 28 06:00:20 PM PDT 24 Jun 28 06:00:24 PM PDT 24 64934371 ps
T304 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2716050495 Jun 28 06:00:23 PM PDT 24 Jun 28 06:00:34 PM PDT 24 234004211 ps
T1052 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2970433273 Jun 28 06:00:07 PM PDT 24 Jun 28 06:00:10 PM PDT 24 87966766 ps
T1053 /workspace/coverage/cover_reg_top/47.edn_intr_test.2832367907 Jun 28 06:00:26 PM PDT 24 Jun 28 06:00:37 PM PDT 24 45150169 ps
T1054 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1457194976 Jun 28 06:00:24 PM PDT 24 Jun 28 06:00:31 PM PDT 24 300301709 ps
T1055 /workspace/coverage/cover_reg_top/8.edn_intr_test.1145027806 Jun 28 06:00:22 PM PDT 24 Jun 28 06:00:28 PM PDT 24 14744605 ps
T1056 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.965610067 Jun 28 06:00:25 PM PDT 24 Jun 28 06:00:37 PM PDT 24 389134577 ps
T1057 /workspace/coverage/cover_reg_top/7.edn_intr_test.3551853936 Jun 28 06:00:22 PM PDT 24 Jun 28 06:00:29 PM PDT 24 26223438 ps
T266 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3455683805 Jun 28 06:00:08 PM PDT 24 Jun 28 06:00:12 PM PDT 24 30467801 ps
T1058 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.832201959 Jun 28 06:00:12 PM PDT 24 Jun 28 06:00:17 PM PDT 24 71991873 ps
T1059 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3311447771 Jun 28 06:00:09 PM PDT 24 Jun 28 06:00:13 PM PDT 24 33387643 ps
T1060 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2590639455 Jun 28 06:00:19 PM PDT 24 Jun 28 06:00:24 PM PDT 24 385209365 ps
T1061 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1449580201 Jun 28 06:00:23 PM PDT 24 Jun 28 06:00:30 PM PDT 24 51504290 ps
T1062 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3514121181 Jun 28 06:00:30 PM PDT 24 Jun 28 06:00:42 PM PDT 24 44754407 ps
T267 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1704717042 Jun 28 06:00:24 PM PDT 24 Jun 28 06:00:31 PM PDT 24 20022340 ps
T1063 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3799958083 Jun 28 06:00:08 PM PDT 24 Jun 28 06:00:15 PM PDT 24 420943059 ps
T1064 /workspace/coverage/cover_reg_top/28.edn_intr_test.1989995208 Jun 28 06:00:23 PM PDT 24 Jun 28 06:00:30 PM PDT 24 15601087 ps
T1065 /workspace/coverage/cover_reg_top/38.edn_intr_test.3298476780 Jun 28 06:00:26 PM PDT 24 Jun 28 06:00:36 PM PDT 24 56746790 ps
T1066 /workspace/coverage/cover_reg_top/15.edn_tl_errors.795947720 Jun 28 06:00:21 PM PDT 24 Jun 28 06:00:28 PM PDT 24 68174369 ps
T1067 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4049113929 Jun 28 06:00:23 PM PDT 24 Jun 28 06:00:29 PM PDT 24 33870022 ps
T1068 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.650698194 Jun 28 06:00:09 PM PDT 24 Jun 28 06:00:13 PM PDT 24 85469100 ps
T305 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3956415563 Jun 28 06:00:23 PM PDT 24 Jun 28 06:00:29 PM PDT 24 473718001 ps
T1069 /workspace/coverage/cover_reg_top/48.edn_intr_test.2985287247 Jun 28 06:00:25 PM PDT 24 Jun 28 06:00:35 PM PDT 24 12155813 ps
T1070 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2439077341 Jun 28 06:00:24 PM PDT 24 Jun 28 06:00:32 PM PDT 24 121770451 ps
T1071 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2356035753 Jun 28 06:00:12 PM PDT 24 Jun 28 06:00:17 PM PDT 24 23437082 ps
T268 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2790398830 Jun 28 06:00:15 PM PDT 24 Jun 28 06:00:20 PM PDT 24 18074445 ps
T302 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3163725679 Jun 28 06:00:24 PM PDT 24 Jun 28 06:00:33 PM PDT 24 102420222 ps
T269 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1868834612 Jun 28 06:00:12 PM PDT 24 Jun 28 06:00:18 PM PDT 24 20408673 ps
T1072 /workspace/coverage/cover_reg_top/4.edn_tl_errors.554214224 Jun 28 06:00:10 PM PDT 24 Jun 28 06:00:16 PM PDT 24 32790098 ps
T1073 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2099207989 Jun 28 06:00:08 PM PDT 24 Jun 28 06:00:11 PM PDT 24 18598801 ps
T1074 /workspace/coverage/cover_reg_top/12.edn_tl_errors.2846719439 Jun 28 06:00:17 PM PDT 24 Jun 28 06:00:21 PM PDT 24 46564025 ps
T1075 /workspace/coverage/cover_reg_top/27.edn_intr_test.3978378924 Jun 28 06:00:21 PM PDT 24 Jun 28 06:00:26 PM PDT 24 25595178 ps
T1076 /workspace/coverage/cover_reg_top/19.edn_intr_test.128465022 Jun 28 06:00:20 PM PDT 24 Jun 28 06:00:24 PM PDT 24 33176551 ps
T1077 /workspace/coverage/cover_reg_top/36.edn_intr_test.4185126226 Jun 28 06:00:27 PM PDT 24 Jun 28 06:00:38 PM PDT 24 27137679 ps
T1078 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1837811376 Jun 28 06:00:11 PM PDT 24 Jun 28 06:00:18 PM PDT 24 234551504 ps
T1079 /workspace/coverage/cover_reg_top/31.edn_intr_test.1888644273 Jun 28 06:00:25 PM PDT 24 Jun 28 06:00:35 PM PDT 24 24881568 ps
T270 /workspace/coverage/cover_reg_top/13.edn_csr_rw.858361896 Jun 28 06:00:23 PM PDT 24 Jun 28 06:00:29 PM PDT 24 46302203 ps
T1080 /workspace/coverage/cover_reg_top/6.edn_intr_test.3783325736 Jun 28 06:00:11 PM PDT 24 Jun 28 06:00:17 PM PDT 24 16433127 ps
T1081 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1658970684 Jun 28 06:00:09 PM PDT 24 Jun 28 06:00:16 PM PDT 24 96576982 ps
T1082 /workspace/coverage/cover_reg_top/19.edn_tl_errors.292593458 Jun 28 06:00:27 PM PDT 24 Jun 28 06:00:41 PM PDT 24 123646723 ps
T272 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.4103852033 Jun 28 06:00:11 PM PDT 24 Jun 28 06:00:17 PM PDT 24 33784305 ps
T1083 /workspace/coverage/cover_reg_top/21.edn_intr_test.1173681576 Jun 28 06:00:26 PM PDT 24 Jun 28 06:00:37 PM PDT 24 15458966 ps
T1084 /workspace/coverage/cover_reg_top/15.edn_intr_test.794025721 Jun 28 06:00:27 PM PDT 24 Jun 28 06:00:38 PM PDT 24 31709627 ps
T1085 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.578844484 Jun 28 06:00:22 PM PDT 24 Jun 28 06:00:29 PM PDT 24 30373120 ps
T1086 /workspace/coverage/cover_reg_top/13.edn_intr_test.3897692987 Jun 28 06:00:24 PM PDT 24 Jun 28 06:00:31 PM PDT 24 22981661 ps
T1087 /workspace/coverage/cover_reg_top/2.edn_intr_test.1494393744 Jun 28 06:00:07 PM PDT 24 Jun 28 06:00:10 PM PDT 24 14314991 ps
T1088 /workspace/coverage/cover_reg_top/13.edn_tl_errors.4203818435 Jun 28 06:00:29 PM PDT 24 Jun 28 06:00:41 PM PDT 24 206501112 ps
T1089 /workspace/coverage/cover_reg_top/20.edn_intr_test.288898855 Jun 28 06:00:21 PM PDT 24 Jun 28 06:00:27 PM PDT 24 37646597 ps
T1090 /workspace/coverage/cover_reg_top/5.edn_tl_errors.243656038 Jun 28 06:00:08 PM PDT 24 Jun 28 06:00:13 PM PDT 24 50417950 ps
T1091 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1276433344 Jun 28 06:00:12 PM PDT 24 Jun 28 06:00:21 PM PDT 24 229158296 ps
T306 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1746413374 Jun 28 06:00:10 PM PDT 24 Jun 28 06:00:16 PM PDT 24 89528587 ps
T1092 /workspace/coverage/cover_reg_top/5.edn_csr_rw.166427776 Jun 28 06:00:05 PM PDT 24 Jun 28 06:00:08 PM PDT 24 117252925 ps
T1093 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1212979209 Jun 28 06:00:19 PM PDT 24 Jun 28 06:00:22 PM PDT 24 112818295 ps
T1094 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.855248574 Jun 28 06:00:12 PM PDT 24 Jun 28 06:00:18 PM PDT 24 40213150 ps
T1095 /workspace/coverage/cover_reg_top/1.edn_intr_test.3672798511 Jun 28 06:00:07 PM PDT 24 Jun 28 06:00:11 PM PDT 24 42379343 ps
T1096 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1654237807 Jun 28 06:00:23 PM PDT 24 Jun 28 06:00:30 PM PDT 24 124885371 ps
T1097 /workspace/coverage/cover_reg_top/49.edn_intr_test.1929661730 Jun 28 06:00:29 PM PDT 24 Jun 28 06:00:40 PM PDT 24 24496560 ps
T1098 /workspace/coverage/cover_reg_top/1.edn_tl_errors.2790412658 Jun 28 06:00:05 PM PDT 24 Jun 28 06:00:12 PM PDT 24 106442547 ps
T1099 /workspace/coverage/cover_reg_top/4.edn_intr_test.2092200698 Jun 28 06:00:05 PM PDT 24 Jun 28 06:00:08 PM PDT 24 41833982 ps
T1100 /workspace/coverage/cover_reg_top/15.edn_csr_rw.4101450138 Jun 28 06:00:23 PM PDT 24 Jun 28 06:00:29 PM PDT 24 15559085 ps
T1101 /workspace/coverage/cover_reg_top/25.edn_intr_test.772565021 Jun 28 06:00:26 PM PDT 24 Jun 28 06:00:35 PM PDT 24 37014115 ps
T273 /workspace/coverage/cover_reg_top/18.edn_csr_rw.3627985842 Jun 28 06:00:23 PM PDT 24 Jun 28 06:00:31 PM PDT 24 29274010 ps
T1102 /workspace/coverage/cover_reg_top/9.edn_tl_errors.4148358260 Jun 28 06:00:24 PM PDT 24 Jun 28 06:00:35 PM PDT 24 551754557 ps
T1103 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1451401036 Jun 28 06:00:04 PM PDT 24 Jun 28 06:00:08 PM PDT 24 23598466 ps
T1104 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1991531796 Jun 28 06:00:22 PM PDT 24 Jun 28 06:00:30 PM PDT 24 95850439 ps
T1105 /workspace/coverage/cover_reg_top/9.edn_intr_test.3080366751 Jun 28 06:00:22 PM PDT 24 Jun 28 06:00:29 PM PDT 24 26283453 ps
T1106 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.554750023 Jun 28 06:00:12 PM PDT 24 Jun 28 06:00:21 PM PDT 24 244268496 ps
T276 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1558480809 Jun 28 06:00:19 PM PDT 24 Jun 28 06:00:22 PM PDT 24 16437255 ps
T1107 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2786493392 Jun 28 06:00:22 PM PDT 24 Jun 28 06:00:29 PM PDT 24 44213595 ps
T274 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1535413393 Jun 28 06:00:09 PM PDT 24 Jun 28 06:00:13 PM PDT 24 43899114 ps
T1108 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1369183595 Jun 28 06:00:22 PM PDT 24 Jun 28 06:00:29 PM PDT 24 135226644 ps
T1109 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3246501153 Jun 28 06:00:11 PM PDT 24 Jun 28 06:00:16 PM PDT 24 90681993 ps
T275 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1243406615 Jun 28 06:00:12 PM PDT 24 Jun 28 06:00:17 PM PDT 24 35185396 ps
T1110 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3004830455 Jun 28 06:00:12 PM PDT 24 Jun 28 06:00:17 PM PDT 24 25431307 ps
T1111 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1104001854 Jun 28 06:00:22 PM PDT 24 Jun 28 06:00:30 PM PDT 24 782244101 ps
T1112 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3034392204 Jun 28 06:00:09 PM PDT 24 Jun 28 06:00:14 PM PDT 24 30022918 ps
T1113 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1287145489 Jun 28 06:00:10 PM PDT 24 Jun 28 06:00:16 PM PDT 24 170365895 ps
T1114 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1963260374 Jun 28 06:00:24 PM PDT 24 Jun 28 06:00:32 PM PDT 24 138954982 ps
T1115 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.802281211 Jun 28 06:00:12 PM PDT 24 Jun 28 06:00:17 PM PDT 24 94942000 ps
T1116 /workspace/coverage/cover_reg_top/39.edn_intr_test.3905237531 Jun 28 06:00:26 PM PDT 24 Jun 28 06:00:35 PM PDT 24 23342622 ps
T1117 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1465606163 Jun 28 06:00:24 PM PDT 24 Jun 28 06:00:31 PM PDT 24 41019145 ps
T1118 /workspace/coverage/cover_reg_top/40.edn_intr_test.31766523 Jun 28 06:00:25 PM PDT 24 Jun 28 06:00:35 PM PDT 24 14662011 ps
T1119 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2581376280 Jun 28 06:00:12 PM PDT 24 Jun 28 06:00:22 PM PDT 24 235600552 ps
T1120 /workspace/coverage/cover_reg_top/45.edn_intr_test.2821241121 Jun 28 06:00:26 PM PDT 24 Jun 28 06:00:35 PM PDT 24 16542876 ps
T1121 /workspace/coverage/cover_reg_top/10.edn_tl_errors.539906624 Jun 28 06:00:24 PM PDT 24 Jun 28 06:00:35 PM PDT 24 129040676 ps
T1122 /workspace/coverage/cover_reg_top/0.edn_intr_test.1547918547 Jun 28 06:00:12 PM PDT 24 Jun 28 06:00:17 PM PDT 24 29056617 ps
T1123 /workspace/coverage/cover_reg_top/16.edn_intr_test.3590152860 Jun 28 06:00:24 PM PDT 24 Jun 28 06:00:33 PM PDT 24 26984593 ps
T1124 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2395781224 Jun 28 06:00:07 PM PDT 24 Jun 28 06:00:11 PM PDT 24 15124094 ps
T1125 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3042609877 Jun 28 06:00:09 PM PDT 24 Jun 28 06:00:19 PM PDT 24 509664479 ps
T1126 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3257358134 Jun 28 06:00:09 PM PDT 24 Jun 28 06:00:14 PM PDT 24 44532356 ps
T1127 /workspace/coverage/cover_reg_top/10.edn_intr_test.1306219677 Jun 28 06:00:24 PM PDT 24 Jun 28 06:00:31 PM PDT 24 26663511 ps
T1128 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1244163801 Jun 28 06:00:17 PM PDT 24 Jun 28 06:00:20 PM PDT 24 20693979 ps
T1129 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3634589851 Jun 28 06:00:28 PM PDT 24 Jun 28 06:00:42 PM PDT 24 91829532 ps
T1130 /workspace/coverage/cover_reg_top/43.edn_intr_test.337833268 Jun 28 06:00:26 PM PDT 24 Jun 28 06:00:37 PM PDT 24 39006501 ps

Test location /workspace/coverage/default/163.edn_genbits.3134302565
Short name T7
Test name
Test status
Simulation time 49027068 ps
CPU time 1.61 seconds
Started Jun 28 06:03:19 PM PDT 24
Finished Jun 28 06:03:28 PM PDT 24
Peak memory 218932 kb
Host smart-a7936ccf-1176-4f3a-88d4-254bba736475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134302565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3134302565
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_alert.1730778525
Short name T33
Test name
Test status
Simulation time 92784155 ps
CPU time 1.22 seconds
Started Jun 28 06:01:41 PM PDT 24
Finished Jun 28 06:01:48 PM PDT 24
Peak memory 220540 kb
Host smart-347cad24-8c02-4a2d-a632-7b6e9ee52c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730778525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1730778525
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/0.edn_sec_cm.732218935
Short name T13
Test name
Test status
Simulation time 587661838 ps
CPU time 4.54 seconds
Started Jun 28 06:01:22 PM PDT 24
Finished Jun 28 06:01:30 PM PDT 24
Peak memory 236316 kb
Host smart-2e94adb0-9045-4c98-b521-dc0f63aa2c23
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732218935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.732218935
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2412018270
Short name T34
Test name
Test status
Simulation time 112237221801 ps
CPU time 755.38 seconds
Started Jun 28 06:01:43 PM PDT 24
Finished Jun 28 06:14:24 PM PDT 24
Peak memory 224284 kb
Host smart-2ca570c3-d94c-48b6-9709-fa33102594b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412018270 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2412018270
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.edn_err.2188676962
Short name T4
Test name
Test status
Simulation time 26635864 ps
CPU time 1.19 seconds
Started Jun 28 06:01:49 PM PDT 24
Finished Jun 28 06:01:55 PM PDT 24
Peak memory 220964 kb
Host smart-db25d752-6c5a-4a41-a7c1-2fa04c8afa69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188676962 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2188676962
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/143.edn_genbits.2231510335
Short name T17
Test name
Test status
Simulation time 77798927 ps
CPU time 1.24 seconds
Started Jun 28 06:03:13 PM PDT 24
Finished Jun 28 06:03:23 PM PDT 24
Peak memory 220312 kb
Host smart-446bcade-f289-43cd-978e-1860be31f740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231510335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2231510335
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_stress_all.2551307939
Short name T53
Test name
Test status
Simulation time 169777944 ps
CPU time 3.36 seconds
Started Jun 28 06:01:57 PM PDT 24
Finished Jun 28 06:02:10 PM PDT 24
Peak memory 215680 kb
Host smart-e8c61bf3-ac57-467b-8718-9c4fe88d2155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551307939 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2551307939
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_disable.2198853283
Short name T183
Test name
Test status
Simulation time 22776292 ps
CPU time 0.92 seconds
Started Jun 28 06:01:16 PM PDT 24
Finished Jun 28 06:01:18 PM PDT 24
Peak memory 216544 kb
Host smart-69e777d4-9d5f-4e6a-9146-75b3d3278f26
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198853283 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2198853283
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/117.edn_alert.3706428279
Short name T72
Test name
Test status
Simulation time 40706164 ps
CPU time 1.12 seconds
Started Jun 28 06:03:06 PM PDT 24
Finished Jun 28 06:03:16 PM PDT 24
Peak memory 218888 kb
Host smart-5dcfef25-af1e-4fbf-92cb-ff247b7dcb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706428279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.3706428279
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/123.edn_alert.4117680769
Short name T69
Test name
Test status
Simulation time 38571642 ps
CPU time 1.29 seconds
Started Jun 28 06:03:11 PM PDT 24
Finished Jun 28 06:03:21 PM PDT 24
Peak memory 220224 kb
Host smart-99279080-26ec-49e6-9877-af6f593378ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117680769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.4117680769
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/98.edn_alert.3508108453
Short name T114
Test name
Test status
Simulation time 32653796 ps
CPU time 1.37 seconds
Started Jun 28 06:03:07 PM PDT 24
Finished Jun 28 06:03:16 PM PDT 24
Peak memory 215956 kb
Host smart-6ec0a2d9-fb2b-4158-9a7c-3f8d81271262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508108453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.3508108453
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/0.edn_regwen.1638752464
Short name T25
Test name
Test status
Simulation time 35830310 ps
CPU time 0.91 seconds
Started Jun 28 06:01:19 PM PDT 24
Finished Jun 28 06:01:22 PM PDT 24
Peak memory 207356 kb
Host smart-2e19d177-a9d3-4b4c-be2a-d2ac83bd8c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638752464 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1638752464
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/28.edn_disable.1803838141
Short name T99
Test name
Test status
Simulation time 10102401 ps
CPU time 0.84 seconds
Started Jun 28 06:02:04 PM PDT 24
Finished Jun 28 06:02:14 PM PDT 24
Peak memory 216476 kb
Host smart-9563fb97-437d-49be-bdb7-1a8f8bc4306c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803838141 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1803838141
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/112.edn_alert.1981908976
Short name T109
Test name
Test status
Simulation time 85437436 ps
CPU time 1.23 seconds
Started Jun 28 06:03:06 PM PDT 24
Finished Jun 28 06:03:15 PM PDT 24
Peak memory 219240 kb
Host smart-bbbab98f-e722-41b6-ac9d-f235ac7d8a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981908976 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.1981908976
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert.1424697349
Short name T38
Test name
Test status
Simulation time 81058615 ps
CPU time 1.18 seconds
Started Jun 28 06:02:11 PM PDT 24
Finished Jun 28 06:02:20 PM PDT 24
Peak memory 221752 kb
Host smart-1e0f3fe3-9a46-4bb5-85b4-31ce4d19da8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424697349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1424697349
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2163024121
Short name T301
Test name
Test status
Simulation time 90518217 ps
CPU time 2.53 seconds
Started Jun 28 06:00:22 PM PDT 24
Finished Jun 28 06:00:30 PM PDT 24
Peak memory 207068 kb
Host smart-6de5eba2-67fd-46c0-9aa2-aba7141018c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163024121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2163024121
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1068579128
Short name T3
Test name
Test status
Simulation time 435765464 ps
CPU time 1.17 seconds
Started Jun 28 06:02:06 PM PDT 24
Finished Jun 28 06:02:16 PM PDT 24
Peak memory 217204 kb
Host smart-8487316d-1be4-42ce-93d0-48dc6ba7ce24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068579128 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1068579128
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.993596371
Short name T224
Test name
Test status
Simulation time 245803296256 ps
CPU time 2633.49 seconds
Started Jun 28 06:02:13 PM PDT 24
Finished Jun 28 06:46:13 PM PDT 24
Peak memory 229276 kb
Host smart-bbc674b8-d8a9-467d-91e3-f08f51081705
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993596371 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.993596371
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_disable.350290830
Short name T189
Test name
Test status
Simulation time 19000913 ps
CPU time 0.9 seconds
Started Jun 28 06:02:31 PM PDT 24
Finished Jun 28 06:02:36 PM PDT 24
Peak memory 216840 kb
Host smart-5a638402-791c-4fba-a335-878c548d5961
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350290830 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.350290830
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable.929162444
Short name T84
Test name
Test status
Simulation time 27766939 ps
CPU time 0.84 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:01:59 PM PDT 24
Peak memory 215784 kb
Host smart-70807b6e-65a7-40fa-8a37-a2f2ccd7b397
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929162444 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.929162444
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable.1889444211
Short name T212
Test name
Test status
Simulation time 26835848 ps
CPU time 0.88 seconds
Started Jun 28 06:01:40 PM PDT 24
Finished Jun 28 06:01:47 PM PDT 24
Peak memory 216544 kb
Host smart-4d1c6216-22cb-46ac-9fcf-591b0beb008b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889444211 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1889444211
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1131334851
Short name T126
Test name
Test status
Simulation time 45924400 ps
CPU time 1.44 seconds
Started Jun 28 06:02:29 PM PDT 24
Finished Jun 28 06:02:34 PM PDT 24
Peak memory 217252 kb
Host smart-81da0b04-b527-4e80-808a-d7609a66cdca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131334851 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1131334851
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_alert.2878354085
Short name T195
Test name
Test status
Simulation time 24837495 ps
CPU time 1.12 seconds
Started Jun 28 06:01:12 PM PDT 24
Finished Jun 28 06:01:15 PM PDT 24
Peak memory 221116 kb
Host smart-dff559d3-0780-4683-a0bc-2954c45df075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878354085 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2878354085
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2790398830
Short name T268
Test name
Test status
Simulation time 18074445 ps
CPU time 1.03 seconds
Started Jun 28 06:00:15 PM PDT 24
Finished Jun 28 06:00:20 PM PDT 24
Peak memory 206900 kb
Host smart-dc2afc46-1d32-4ce8-9b80-c1d8c654d4fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790398830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2790398830
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/default/141.edn_alert.3539685873
Short name T22
Test name
Test status
Simulation time 62099042 ps
CPU time 1.1 seconds
Started Jun 28 06:03:19 PM PDT 24
Finished Jun 28 06:03:28 PM PDT 24
Peak memory 220400 kb
Host smart-819aca29-5c70-49f1-a120-b494a3f49346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539685873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.3539685873
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/92.edn_alert.4004848519
Short name T193
Test name
Test status
Simulation time 69147401 ps
CPU time 1.11 seconds
Started Jun 28 06:03:03 PM PDT 24
Finished Jun 28 06:03:11 PM PDT 24
Peak memory 220052 kb
Host smart-4548c167-fe33-4847-84aa-dd55e522ab70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004848519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.4004848519
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert.2246683457
Short name T138
Test name
Test status
Simulation time 25230986 ps
CPU time 1.31 seconds
Started Jun 28 06:02:18 PM PDT 24
Finished Jun 28 06:02:26 PM PDT 24
Peak memory 220168 kb
Host smart-b59c106f-c8ab-478e-a50b-e46dfb0bdfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246683457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2246683457
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/75.edn_genbits.862210376
Short name T323
Test name
Test status
Simulation time 76390521 ps
CPU time 1.28 seconds
Started Jun 28 06:02:42 PM PDT 24
Finished Jun 28 06:02:48 PM PDT 24
Peak memory 220272 kb
Host smart-089f74f8-311f-4fc3-b5d4-98bd4a2d3402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862210376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.862210376
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.252682645
Short name T128
Test name
Test status
Simulation time 147829190 ps
CPU time 1.19 seconds
Started Jun 28 06:03:12 PM PDT 24
Finished Jun 28 06:03:22 PM PDT 24
Peak memory 218916 kb
Host smart-3a68e2ed-8495-423f-96d2-4e1053533948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252682645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.252682645
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/48.edn_intr.2405878506
Short name T26
Test name
Test status
Simulation time 21227971 ps
CPU time 1.09 seconds
Started Jun 28 06:02:38 PM PDT 24
Finished Jun 28 06:02:43 PM PDT 24
Peak memory 216188 kb
Host smart-6ec04570-5746-4cec-a30a-a614d6e6f412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405878506 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2405878506
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2123344351
Short name T220
Test name
Test status
Simulation time 191328995968 ps
CPU time 1990.82 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:34:55 PM PDT 24
Peak memory 230488 kb
Host smart-0d09f0fc-1e08-4469-ab98-8f075979c862
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123344351 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2123344351
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.4081054453
Short name T152
Test name
Test status
Simulation time 24937429 ps
CPU time 1.25 seconds
Started Jun 28 06:01:44 PM PDT 24
Finished Jun 28 06:01:50 PM PDT 24
Peak memory 220016 kb
Host smart-dc129a24-09c8-4f7d-9baa-9ae7fa6a2b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081054453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.4081054453
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/107.edn_alert.3664473830
Short name T144
Test name
Test status
Simulation time 108140452 ps
CPU time 1.19 seconds
Started Jun 28 06:03:02 PM PDT 24
Finished Jun 28 06:03:10 PM PDT 24
Peak memory 219640 kb
Host smart-7fe3c747-2a68-4a43-a660-d96b77d575ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664473830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.3664473830
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert.2943778178
Short name T563
Test name
Test status
Simulation time 29910539 ps
CPU time 1.11 seconds
Started Jun 28 06:01:57 PM PDT 24
Finished Jun 28 06:02:08 PM PDT 24
Peak memory 220040 kb
Host smart-c796c0ca-c9b8-4d7d-b89f-40a4dde02fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943778178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2943778178
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/62.edn_alert.2574000428
Short name T163
Test name
Test status
Simulation time 23983355 ps
CPU time 1.24 seconds
Started Jun 28 06:02:44 PM PDT 24
Finished Jun 28 06:02:51 PM PDT 24
Peak memory 218856 kb
Host smart-868d2aa3-e1d4-4050-99c3-132c1b166626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574000428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.2574000428
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable.1426816351
Short name T215
Test name
Test status
Simulation time 97270517 ps
CPU time 0.87 seconds
Started Jun 28 06:01:48 PM PDT 24
Finished Jun 28 06:01:53 PM PDT 24
Peak memory 215628 kb
Host smart-5a19169b-1762-41e6-b218-084192868785
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426816351 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1426816351
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/10.edn_intr.327508987
Short name T89
Test name
Test status
Simulation time 23771504 ps
CPU time 1 seconds
Started Jun 28 06:01:40 PM PDT 24
Finished Jun 28 06:01:47 PM PDT 24
Peak memory 216128 kb
Host smart-6a615508-9e51-4e12-a4b8-d86ca998026b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327508987 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.327508987
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/101.edn_alert.3483578372
Short name T599
Test name
Test status
Simulation time 35746439 ps
CPU time 1.09 seconds
Started Jun 28 06:03:08 PM PDT 24
Finished Jun 28 06:03:17 PM PDT 24
Peak memory 218804 kb
Host smart-844295dc-c60c-4264-aa2c-3031665890b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483578372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.3483578372
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/11.edn_err.1533248462
Short name T198
Test name
Test status
Simulation time 20510938 ps
CPU time 1.21 seconds
Started Jun 28 06:01:35 PM PDT 24
Finished Jun 28 06:01:39 PM PDT 24
Peak memory 229824 kb
Host smart-acf9ad62-cf8c-450e-9d12-c6155cdeb70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533248462 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1533248462
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/124.edn_alert.286043634
Short name T731
Test name
Test status
Simulation time 23685215 ps
CPU time 1.17 seconds
Started Jun 28 06:03:08 PM PDT 24
Finished Jun 28 06:03:18 PM PDT 24
Peak memory 219788 kb
Host smart-876cea7d-8caf-4e91-9a8f-2826cbc6f097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286043634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.286043634
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.657081127
Short name T148
Test name
Test status
Simulation time 27690620 ps
CPU time 1.03 seconds
Started Jun 28 06:01:55 PM PDT 24
Finished Jun 28 06:02:05 PM PDT 24
Peak memory 217112 kb
Host smart-57840969-4950-4e1d-a5e6-ca1803461dc6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657081127 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.657081127
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.177189803
Short name T135
Test name
Test status
Simulation time 376036200 ps
CPU time 1.22 seconds
Started Jun 28 06:01:54 PM PDT 24
Finished Jun 28 06:02:08 PM PDT 24
Peak memory 217340 kb
Host smart-0a82de1b-0c3b-4373-819e-56ba395a4222
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177189803 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.177189803
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2237584303
Short name T209
Test name
Test status
Simulation time 35197997 ps
CPU time 0.98 seconds
Started Jun 28 06:01:51 PM PDT 24
Finished Jun 28 06:01:57 PM PDT 24
Peak memory 217276 kb
Host smart-26509624-1a04-4ab6-9536-39734cf31b65
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237584303 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2237584303
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_disable.332608173
Short name T199
Test name
Test status
Simulation time 36044427 ps
CPU time 0.85 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:02 PM PDT 24
Peak memory 216464 kb
Host smart-2e28cb95-16b9-4b99-833c-2580011e58bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332608173 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.332608173
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1712583834
Short name T158
Test name
Test status
Simulation time 52219613 ps
CPU time 1.1 seconds
Started Jun 28 06:02:11 PM PDT 24
Finished Jun 28 06:02:20 PM PDT 24
Peak memory 220056 kb
Host smart-39ac2ae7-ed9c-423d-b273-52f1f45c3486
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712583834 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1712583834
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.524078345
Short name T1
Test name
Test status
Simulation time 38169072 ps
CPU time 0.89 seconds
Started Jun 28 06:02:26 PM PDT 24
Finished Jun 28 06:02:31 PM PDT 24
Peak memory 218504 kb
Host smart-8db549ad-e563-49f5-9acf-ada4f84ea97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524078345 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.524078345
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/37.edn_disable.1940185998
Short name T190
Test name
Test status
Simulation time 11823426 ps
CPU time 0.94 seconds
Started Jun 28 06:02:14 PM PDT 24
Finished Jun 28 06:02:22 PM PDT 24
Peak memory 216540 kb
Host smart-40e646d8-9b6a-45a1-99f2-88412dc22954
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940185998 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1940185998
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/134.edn_genbits.133357017
Short name T106
Test name
Test status
Simulation time 48424058 ps
CPU time 1.86 seconds
Started Jun 28 06:03:16 PM PDT 24
Finished Jun 28 06:03:27 PM PDT 24
Peak memory 218800 kb
Host smart-8872e640-3de9-4205-a367-7f9aa7a2fbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133357017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.133357017
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.4013696309
Short name T324
Test name
Test status
Simulation time 97877214 ps
CPU time 2.23 seconds
Started Jun 28 06:03:22 PM PDT 24
Finished Jun 28 06:03:31 PM PDT 24
Peak memory 219240 kb
Host smart-ae56f386-450a-4d0a-ade0-768062dee8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013696309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.4013696309
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_alert_test.1728361959
Short name T67
Test name
Test status
Simulation time 52519112 ps
CPU time 1.41 seconds
Started Jun 28 06:02:24 PM PDT 24
Finished Jun 28 06:02:30 PM PDT 24
Peak memory 215276 kb
Host smart-f8651b1f-2215-4378-a5d1-7bafa53a8339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728361959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1728361959
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/193.edn_genbits.1355229433
Short name T74
Test name
Test status
Simulation time 131614783 ps
CPU time 2.57 seconds
Started Jun 28 06:03:33 PM PDT 24
Finished Jun 28 06:03:43 PM PDT 24
Peak memory 220536 kb
Host smart-4115c6c1-1db0-4f93-8cc4-a2707fdd50da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355229433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1355229433
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.940204039
Short name T230
Test name
Test status
Simulation time 70147652 ps
CPU time 1.28 seconds
Started Jun 28 06:03:28 PM PDT 24
Finished Jun 28 06:03:36 PM PDT 24
Peak memory 217644 kb
Host smart-be28a6e3-b9f4-430d-8dce-8e77fca08821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940204039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.940204039
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2473095405
Short name T29
Test name
Test status
Simulation time 21050506 ps
CPU time 1.1 seconds
Started Jun 28 06:02:33 PM PDT 24
Finished Jun 28 06:02:40 PM PDT 24
Peak memory 216128 kb
Host smart-84666d9b-3f28-4d27-b96e-77666e155297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473095405 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2473095405
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1488676893
Short name T284
Test name
Test status
Simulation time 37929966 ps
CPU time 1.05 seconds
Started Jun 28 06:00:11 PM PDT 24
Finished Jun 28 06:00:16 PM PDT 24
Peak memory 206932 kb
Host smart-c30fede4-2d72-42db-9053-9d762fba3821
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488676893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1488676893
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1465606163
Short name T1117
Test name
Test status
Simulation time 41019145 ps
CPU time 1.47 seconds
Started Jun 28 06:00:24 PM PDT 24
Finished Jun 28 06:00:31 PM PDT 24
Peak memory 206980 kb
Host smart-542b6e46-a789-483e-b7d0-9db9544ec512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465606163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1465606163
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/default/10.edn_err.3456592246
Short name T6
Test name
Test status
Simulation time 71295576 ps
CPU time 1.19 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:47 PM PDT 24
Peak memory 226112 kb
Host smart-6d2e3369-90d2-4df7-887e-fd4cfbbb8b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456592246 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3456592246
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/103.edn_genbits.2859499024
Short name T348
Test name
Test status
Simulation time 71402841 ps
CPU time 1.62 seconds
Started Jun 28 06:03:02 PM PDT 24
Finished Jun 28 06:03:10 PM PDT 24
Peak memory 219064 kb
Host smart-4899b937-441e-483c-b327-c1d6f394a52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859499024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2859499024
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1529417114
Short name T833
Test name
Test status
Simulation time 31203254 ps
CPU time 1.21 seconds
Started Jun 28 06:02:59 PM PDT 24
Finished Jun 28 06:03:05 PM PDT 24
Peak memory 217736 kb
Host smart-cec363e2-01e2-4a18-91f8-be9f23eb8722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529417114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1529417114
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1187842064
Short name T75
Test name
Test status
Simulation time 65601015 ps
CPU time 1.37 seconds
Started Jun 28 06:03:00 PM PDT 24
Finished Jun 28 06:03:08 PM PDT 24
Peak memory 217536 kb
Host smart-c898ccdb-7d2b-499f-9557-b25d3b0664c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187842064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1187842064
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.3388872940
Short name T329
Test name
Test status
Simulation time 42957588 ps
CPU time 1.5 seconds
Started Jun 28 06:03:11 PM PDT 24
Finished Jun 28 06:03:21 PM PDT 24
Peak memory 218772 kb
Host smart-3101ca61-a1f7-4782-9e82-0fd626e109d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388872940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3388872940
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.2970262093
Short name T389
Test name
Test status
Simulation time 157264563 ps
CPU time 1.25 seconds
Started Jun 28 06:03:14 PM PDT 24
Finished Jun 28 06:03:24 PM PDT 24
Peak memory 219488 kb
Host smart-6958ec84-954c-4ac1-8c32-c90d7da8e6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970262093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2970262093
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.3451886242
Short name T335
Test name
Test status
Simulation time 72936377 ps
CPU time 1.27 seconds
Started Jun 28 06:03:12 PM PDT 24
Finished Jun 28 06:03:22 PM PDT 24
Peak memory 219220 kb
Host smart-48a0094b-d40c-4b89-90c4-26c7db99fbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451886242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3451886242
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.1356789811
Short name T781
Test name
Test status
Simulation time 77434361 ps
CPU time 1.24 seconds
Started Jun 28 06:03:18 PM PDT 24
Finished Jun 28 06:03:28 PM PDT 24
Peak memory 217664 kb
Host smart-8eac0117-a480-42b2-a18b-fc542b827e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356789811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1356789811
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.2979711967
Short name T342
Test name
Test status
Simulation time 50716739 ps
CPU time 1.38 seconds
Started Jun 28 06:03:24 PM PDT 24
Finished Jun 28 06:03:32 PM PDT 24
Peak memory 219040 kb
Host smart-adccca6b-86d2-46f7-9594-a7fb9be78eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979711967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2979711967
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.1882774949
Short name T332
Test name
Test status
Simulation time 46575660 ps
CPU time 1.48 seconds
Started Jun 28 06:03:23 PM PDT 24
Finished Jun 28 06:03:31 PM PDT 24
Peak memory 220068 kb
Host smart-c39446dd-b86a-4c2f-915a-f1482af869f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882774949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1882774949
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.4096846140
Short name T947
Test name
Test status
Simulation time 53482152 ps
CPU time 1.21 seconds
Started Jun 28 06:03:33 PM PDT 24
Finished Jun 28 06:03:41 PM PDT 24
Peak memory 217560 kb
Host smart-1a2dbe12-da33-426b-be5f-6d05ead6f814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096846140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.4096846140
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2725502662
Short name T325
Test name
Test status
Simulation time 118145962 ps
CPU time 1.5 seconds
Started Jun 28 06:03:35 PM PDT 24
Finished Jun 28 06:03:43 PM PDT 24
Peak memory 219008 kb
Host smart-b402f7d2-1ca2-47dd-8395-fd69d17c17e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725502662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2725502662
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.3961349479
Short name T90
Test name
Test status
Simulation time 24124123 ps
CPU time 1 seconds
Started Jun 28 06:01:36 PM PDT 24
Finished Jun 28 06:01:40 PM PDT 24
Peak memory 216088 kb
Host smart-89c69cca-9210-4e84-99e6-19dd1837408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961349479 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3961349479
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/110.edn_alert.2304494408
Short name T437
Test name
Test status
Simulation time 43191675 ps
CPU time 1.11 seconds
Started Jun 28 06:03:02 PM PDT 24
Finished Jun 28 06:03:09 PM PDT 24
Peak memory 218848 kb
Host smart-65874c35-a7b7-42db-a181-6e9a9b9056e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304494408 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.2304494408
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/127.edn_alert.917184608
Short name T119
Test name
Test status
Simulation time 106236509 ps
CPU time 1.29 seconds
Started Jun 28 06:03:02 PM PDT 24
Finished Jun 28 06:03:09 PM PDT 24
Peak memory 215968 kb
Host smart-661de0fc-4b47-4a98-a294-dd7913ea2bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917184608 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.917184608
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/32.edn_disable.2845251672
Short name T40
Test name
Test status
Simulation time 19781420 ps
CPU time 0.9 seconds
Started Jun 28 06:02:07 PM PDT 24
Finished Jun 28 06:02:16 PM PDT 24
Peak memory 215716 kb
Host smart-bbe68902-d295-4231-81cc-d6d18df80343
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845251672 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2845251672
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/189.edn_genbits.2986784239
Short name T355
Test name
Test status
Simulation time 411254151 ps
CPU time 1.56 seconds
Started Jun 28 06:03:36 PM PDT 24
Finished Jun 28 06:03:44 PM PDT 24
Peak memory 218032 kb
Host smart-4556c599-f205-4893-aeef-9d9212ba1b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986784239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2986784239
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.4103852033
Short name T272
Test name
Test status
Simulation time 33784305 ps
CPU time 1.16 seconds
Started Jun 28 06:00:11 PM PDT 24
Finished Jun 28 06:00:17 PM PDT 24
Peak memory 206944 kb
Host smart-d7f1bc43-a6c9-49d9-9796-16c435514528
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103852033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.4103852033
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2269758767
Short name T271
Test name
Test status
Simulation time 49713373 ps
CPU time 2.03 seconds
Started Jun 28 06:00:08 PM PDT 24
Finished Jun 28 06:00:12 PM PDT 24
Peak memory 206900 kb
Host smart-8faeea22-e6bc-43c9-a7e1-f6ce997a4445
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269758767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2269758767
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1880170384
Short name T254
Test name
Test status
Simulation time 14660765 ps
CPU time 0.93 seconds
Started Jun 28 06:00:11 PM PDT 24
Finished Jun 28 06:00:16 PM PDT 24
Peak memory 206912 kb
Host smart-d0ea785f-d9f9-4457-ac26-a357c977eaaf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880170384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1880170384
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3246501153
Short name T1109
Test name
Test status
Simulation time 90681993 ps
CPU time 1.5 seconds
Started Jun 28 06:00:11 PM PDT 24
Finished Jun 28 06:00:16 PM PDT 24
Peak memory 215188 kb
Host smart-c5c9b367-e2df-4ce3-8d53-6e30b43d81ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246501153 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3246501153
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2970433273
Short name T1052
Test name
Test status
Simulation time 87966766 ps
CPU time 0.9 seconds
Started Jun 28 06:00:07 PM PDT 24
Finished Jun 28 06:00:10 PM PDT 24
Peak memory 206920 kb
Host smart-856db521-74bc-4d37-80a5-1d23630e4cfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970433273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2970433273
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1547918547
Short name T1122
Test name
Test status
Simulation time 29056617 ps
CPU time 0.92 seconds
Started Jun 28 06:00:12 PM PDT 24
Finished Jun 28 06:00:17 PM PDT 24
Peak memory 206824 kb
Host smart-f405593e-b60a-49b3-b513-140f5de49261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547918547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1547918547
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3034392204
Short name T1112
Test name
Test status
Simulation time 30022918 ps
CPU time 1.17 seconds
Started Jun 28 06:00:09 PM PDT 24
Finished Jun 28 06:00:14 PM PDT 24
Peak memory 207100 kb
Host smart-bc01449b-31dc-451d-b3b7-49f47b2653e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034392204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3034392204
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1658970684
Short name T1081
Test name
Test status
Simulation time 96576982 ps
CPU time 3.68 seconds
Started Jun 28 06:00:09 PM PDT 24
Finished Jun 28 06:00:16 PM PDT 24
Peak memory 215244 kb
Host smart-94bdd664-68fa-4dba-8b86-00b73bfb460a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658970684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1658970684
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1287145489
Short name T1113
Test name
Test status
Simulation time 170365895 ps
CPU time 1.57 seconds
Started Jun 28 06:00:10 PM PDT 24
Finished Jun 28 06:00:16 PM PDT 24
Peak memory 207056 kb
Host smart-1a91f351-c677-4d39-a547-57c78947b6c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287145489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1287145489
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1732868864
Short name T265
Test name
Test status
Simulation time 22920343 ps
CPU time 1.04 seconds
Started Jun 28 06:00:11 PM PDT 24
Finished Jun 28 06:00:16 PM PDT 24
Peak memory 206932 kb
Host smart-87b87270-86c1-4d8c-9e5f-9f25b8ebb857
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732868864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1732868864
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.554750023
Short name T1106
Test name
Test status
Simulation time 244268496 ps
CPU time 4.9 seconds
Started Jun 28 06:00:12 PM PDT 24
Finished Jun 28 06:00:21 PM PDT 24
Peak memory 206984 kb
Host smart-f80774ff-273c-4b89-95e8-54bcb04f3061
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554750023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.554750023
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1243406615
Short name T275
Test name
Test status
Simulation time 35185396 ps
CPU time 0.85 seconds
Started Jun 28 06:00:12 PM PDT 24
Finished Jun 28 06:00:17 PM PDT 24
Peak memory 206728 kb
Host smart-14970b68-8641-4911-857c-9785f4c7c524
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243406615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1243406615
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2870332694
Short name T1046
Test name
Test status
Simulation time 41303714 ps
CPU time 1.19 seconds
Started Jun 28 06:00:10 PM PDT 24
Finished Jun 28 06:00:16 PM PDT 24
Peak memory 215196 kb
Host smart-1a221129-ebb9-41e5-8516-8e74c08fee8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870332694 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2870332694
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2099207989
Short name T1073
Test name
Test status
Simulation time 18598801 ps
CPU time 0.86 seconds
Started Jun 28 06:00:08 PM PDT 24
Finished Jun 28 06:00:11 PM PDT 24
Peak memory 206740 kb
Host smart-70318eba-2aa7-47d5-807d-c6bd59c8efea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099207989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2099207989
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3672798511
Short name T1095
Test name
Test status
Simulation time 42379343 ps
CPU time 0.92 seconds
Started Jun 28 06:00:07 PM PDT 24
Finished Jun 28 06:00:11 PM PDT 24
Peak memory 206836 kb
Host smart-c9a4ac10-ffb3-46e1-abfb-4c877347631d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672798511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3672798511
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2790412658
Short name T1098
Test name
Test status
Simulation time 106442547 ps
CPU time 4.16 seconds
Started Jun 28 06:00:05 PM PDT 24
Finished Jun 28 06:00:12 PM PDT 24
Peak memory 215180 kb
Host smart-14cea982-6668-4594-a955-ed3685d3eb78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790412658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2790412658
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3799958083
Short name T1063
Test name
Test status
Simulation time 420943059 ps
CPU time 2.69 seconds
Started Jun 28 06:00:08 PM PDT 24
Finished Jun 28 06:00:15 PM PDT 24
Peak memory 206888 kb
Host smart-d9a7ed0a-74ba-458c-8060-8c4e00d93b7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799958083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3799958083
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2301729437
Short name T1014
Test name
Test status
Simulation time 22307912 ps
CPU time 1.41 seconds
Started Jun 28 06:00:29 PM PDT 24
Finished Jun 28 06:00:41 PM PDT 24
Peak memory 215140 kb
Host smart-91c53714-218b-42b6-943a-20fd6a9b004d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301729437 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2301729437
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1704717042
Short name T267
Test name
Test status
Simulation time 20022340 ps
CPU time 0.83 seconds
Started Jun 28 06:00:24 PM PDT 24
Finished Jun 28 06:00:31 PM PDT 24
Peak memory 206680 kb
Host smart-dfc89e7b-d14f-42b6-a243-5ac940b9ca9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704717042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1704717042
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1306219677
Short name T1127
Test name
Test status
Simulation time 26663511 ps
CPU time 0.81 seconds
Started Jun 28 06:00:24 PM PDT 24
Finished Jun 28 06:00:31 PM PDT 24
Peak memory 206680 kb
Host smart-4033c214-8dd5-4b99-aa2a-2014bd79bd83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306219677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1306219677
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.808354661
Short name T1051
Test name
Test status
Simulation time 64934371 ps
CPU time 1.07 seconds
Started Jun 28 06:00:20 PM PDT 24
Finished Jun 28 06:00:24 PM PDT 24
Peak memory 206924 kb
Host smart-5b1143e5-d617-40e6-9c46-889ba5f88cee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808354661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.808354661
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.539906624
Short name T1121
Test name
Test status
Simulation time 129040676 ps
CPU time 2.49 seconds
Started Jun 28 06:00:24 PM PDT 24
Finished Jun 28 06:00:35 PM PDT 24
Peak memory 215188 kb
Host smart-13497fdd-b3ec-48e4-83ad-866c18017c1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539906624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.539906624
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.4273912947
Short name T1050
Test name
Test status
Simulation time 142226134 ps
CPU time 1.55 seconds
Started Jun 28 06:00:17 PM PDT 24
Finished Jun 28 06:00:21 PM PDT 24
Peak memory 215192 kb
Host smart-a21da525-3cfb-416c-be3e-4d86f238dd94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273912947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.4273912947
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2143891672
Short name T1020
Test name
Test status
Simulation time 42686401 ps
CPU time 1.25 seconds
Started Jun 28 06:00:24 PM PDT 24
Finished Jun 28 06:00:33 PM PDT 24
Peak memory 215188 kb
Host smart-0e5ea78f-e695-4bff-b683-ca9d607162a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143891672 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2143891672
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1558480809
Short name T276
Test name
Test status
Simulation time 16437255 ps
CPU time 0.98 seconds
Started Jun 28 06:00:19 PM PDT 24
Finished Jun 28 06:00:22 PM PDT 24
Peak memory 206848 kb
Host smart-0c1e904d-2e01-429f-8241-cf1b3bb24439
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558480809 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1558480809
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2038006744
Short name T1002
Test name
Test status
Simulation time 43436777 ps
CPU time 0.9 seconds
Started Jun 28 06:00:18 PM PDT 24
Finished Jun 28 06:00:21 PM PDT 24
Peak memory 206856 kb
Host smart-e2627b80-2387-4739-a24c-2f7f87b92b83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038006744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2038006744
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1963260374
Short name T1114
Test name
Test status
Simulation time 138954982 ps
CPU time 1.42 seconds
Started Jun 28 06:00:24 PM PDT 24
Finished Jun 28 06:00:32 PM PDT 24
Peak memory 206852 kb
Host smart-c2f6d874-bb31-490e-b234-1c2174a1875b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963260374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1963260374
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1104001854
Short name T1111
Test name
Test status
Simulation time 782244101 ps
CPU time 2.83 seconds
Started Jun 28 06:00:22 PM PDT 24
Finished Jun 28 06:00:30 PM PDT 24
Peak memory 215188 kb
Host smart-6f50eb61-108a-4582-9e5d-8ee33a2b4725
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104001854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1104001854
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1880090142
Short name T1038
Test name
Test status
Simulation time 31104867 ps
CPU time 1.41 seconds
Started Jun 28 06:00:25 PM PDT 24
Finished Jun 28 06:00:34 PM PDT 24
Peak memory 215172 kb
Host smart-d30b9216-f116-4e31-8459-6da9d790f494
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880090142 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1880090142
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2154039379
Short name T285
Test name
Test status
Simulation time 13419089 ps
CPU time 0.94 seconds
Started Jun 28 06:00:23 PM PDT 24
Finished Jun 28 06:00:30 PM PDT 24
Peak memory 206936 kb
Host smart-f3b0358f-b626-4fd8-a009-35cd8f2ff970
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154039379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2154039379
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1104794319
Short name T1008
Test name
Test status
Simulation time 16639689 ps
CPU time 0.96 seconds
Started Jun 28 06:00:31 PM PDT 24
Finished Jun 28 06:00:42 PM PDT 24
Peak memory 206828 kb
Host smart-27ca78e2-5ad3-4f5a-8968-501da4b4a642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104794319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1104794319
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1409990516
Short name T280
Test name
Test status
Simulation time 36839826 ps
CPU time 1.39 seconds
Started Jun 28 06:00:26 PM PDT 24
Finished Jun 28 06:00:37 PM PDT 24
Peak memory 206916 kb
Host smart-a3b54e9e-acb2-4241-9d5a-1ff06e7702ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409990516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1409990516
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2846719439
Short name T1074
Test name
Test status
Simulation time 46564025 ps
CPU time 1.75 seconds
Started Jun 28 06:00:17 PM PDT 24
Finished Jun 28 06:00:21 PM PDT 24
Peak memory 215164 kb
Host smart-9e549cc0-2e83-4b16-bb11-b6c82db7f449
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846719439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2846719439
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3163725679
Short name T302
Test name
Test status
Simulation time 102420222 ps
CPU time 2.64 seconds
Started Jun 28 06:00:24 PM PDT 24
Finished Jun 28 06:00:33 PM PDT 24
Peak memory 206964 kb
Host smart-8bf3e2b6-6cf9-4f48-96b5-c3457befa591
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163725679 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3163725679
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.578844484
Short name T1085
Test name
Test status
Simulation time 30373120 ps
CPU time 1.36 seconds
Started Jun 28 06:00:22 PM PDT 24
Finished Jun 28 06:00:29 PM PDT 24
Peak memory 218564 kb
Host smart-a7a50364-3fa1-437d-aa15-9c01be13e725
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578844484 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.578844484
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.858361896
Short name T270
Test name
Test status
Simulation time 46302203 ps
CPU time 0.86 seconds
Started Jun 28 06:00:23 PM PDT 24
Finished Jun 28 06:00:29 PM PDT 24
Peak memory 206924 kb
Host smart-2d522310-2b0c-4921-af30-f138d654f8d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858361896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.858361896
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3897692987
Short name T1086
Test name
Test status
Simulation time 22981661 ps
CPU time 0.75 seconds
Started Jun 28 06:00:24 PM PDT 24
Finished Jun 28 06:00:31 PM PDT 24
Peak memory 206616 kb
Host smart-919823ee-64d9-4ea2-b493-47c1fca12e24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897692987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3897692987
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.949141564
Short name T283
Test name
Test status
Simulation time 32218211 ps
CPU time 1.13 seconds
Started Jun 28 06:00:29 PM PDT 24
Finished Jun 28 06:00:40 PM PDT 24
Peak memory 206936 kb
Host smart-b2513a5c-a48a-4bca-9e66-8c4667bdfa7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949141564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.949141564
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.4203818435
Short name T1088
Test name
Test status
Simulation time 206501112 ps
CPU time 2.34 seconds
Started Jun 28 06:00:29 PM PDT 24
Finished Jun 28 06:00:41 PM PDT 24
Peak memory 215404 kb
Host smart-b3e7bf37-4052-4fdd-a13b-fe469c51fda0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203818435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.4203818435
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.425656174
Short name T303
Test name
Test status
Simulation time 49752205 ps
CPU time 1.68 seconds
Started Jun 28 06:00:19 PM PDT 24
Finished Jun 28 06:00:24 PM PDT 24
Peak memory 206920 kb
Host smart-a09b66df-98ca-4710-86d5-cc46ab3c213f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425656174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.425656174
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4049113929
Short name T1067
Test name
Test status
Simulation time 33870022 ps
CPU time 1.5 seconds
Started Jun 28 06:00:23 PM PDT 24
Finished Jun 28 06:00:29 PM PDT 24
Peak memory 215184 kb
Host smart-4681e4e5-6008-47ac-94b1-5fe2d0e8fe52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049113929 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.4049113929
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2176484540
Short name T1009
Test name
Test status
Simulation time 14583705 ps
CPU time 0.87 seconds
Started Jun 28 06:00:23 PM PDT 24
Finished Jun 28 06:00:30 PM PDT 24
Peak memory 206872 kb
Host smart-11390841-1018-48bb-a0a4-fa016bc50fba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176484540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2176484540
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2439077341
Short name T1070
Test name
Test status
Simulation time 121770451 ps
CPU time 1.4 seconds
Started Jun 28 06:00:24 PM PDT 24
Finished Jun 28 06:00:32 PM PDT 24
Peak memory 206996 kb
Host smart-f959613d-e0dd-4b35-aaca-56e3bd1e0072
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439077341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2439077341
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1369183595
Short name T1108
Test name
Test status
Simulation time 135226644 ps
CPU time 2.42 seconds
Started Jun 28 06:00:22 PM PDT 24
Finished Jun 28 06:00:29 PM PDT 24
Peak memory 215240 kb
Host smart-1044f975-ef79-46a7-bd8e-ae92dd4ddfc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369183595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1369183595
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2716050495
Short name T304
Test name
Test status
Simulation time 234004211 ps
CPU time 4.5 seconds
Started Jun 28 06:00:23 PM PDT 24
Finished Jun 28 06:00:34 PM PDT 24
Peak memory 215048 kb
Host smart-a9260af6-37f8-4ef2-aa3d-b5c9ce386bf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716050495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2716050495
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1654237807
Short name T1096
Test name
Test status
Simulation time 124885371 ps
CPU time 1.32 seconds
Started Jun 28 06:00:23 PM PDT 24
Finished Jun 28 06:00:30 PM PDT 24
Peak memory 215176 kb
Host smart-5d93366b-bbb6-4144-9f37-9eb5cc8da07f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654237807 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1654237807
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.4101450138
Short name T1100
Test name
Test status
Simulation time 15559085 ps
CPU time 0.89 seconds
Started Jun 28 06:00:23 PM PDT 24
Finished Jun 28 06:00:29 PM PDT 24
Peak memory 206884 kb
Host smart-d5e03ce0-4f33-4fa0-9852-a3562d656d8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101450138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.4101450138
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.794025721
Short name T1084
Test name
Test status
Simulation time 31709627 ps
CPU time 0.85 seconds
Started Jun 28 06:00:27 PM PDT 24
Finished Jun 28 06:00:38 PM PDT 24
Peak memory 206856 kb
Host smart-1252b771-a42e-4abb-a72a-fa2b1c83ae08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794025721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.794025721
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2273933682
Short name T277
Test name
Test status
Simulation time 22442809 ps
CPU time 0.94 seconds
Started Jun 28 06:00:20 PM PDT 24
Finished Jun 28 06:00:25 PM PDT 24
Peak memory 206984 kb
Host smart-a483637d-104b-4b24-9125-608df6b83a5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273933682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2273933682
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.795947720
Short name T1066
Test name
Test status
Simulation time 68174369 ps
CPU time 2.64 seconds
Started Jun 28 06:00:21 PM PDT 24
Finished Jun 28 06:00:28 PM PDT 24
Peak memory 215236 kb
Host smart-f40ed078-786a-46c9-8a16-302b6d3102cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795947720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.795947720
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2786493392
Short name T1107
Test name
Test status
Simulation time 44213595 ps
CPU time 1.18 seconds
Started Jun 28 06:00:22 PM PDT 24
Finished Jun 28 06:00:29 PM PDT 24
Peak memory 215184 kb
Host smart-709ec1dc-2f03-4aa0-97e3-6447f1cf48b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786493392 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2786493392
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2875466740
Short name T1037
Test name
Test status
Simulation time 12828707 ps
CPU time 0.89 seconds
Started Jun 28 06:00:23 PM PDT 24
Finished Jun 28 06:00:29 PM PDT 24
Peak memory 206884 kb
Host smart-392c8751-0849-48a8-8ed9-508457d77ca1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875466740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2875466740
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3590152860
Short name T1123
Test name
Test status
Simulation time 26984593 ps
CPU time 0.91 seconds
Started Jun 28 06:00:24 PM PDT 24
Finished Jun 28 06:00:33 PM PDT 24
Peak memory 206868 kb
Host smart-3625b333-aea6-4f90-a192-5a42602c34c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590152860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3590152860
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.188020550
Short name T1032
Test name
Test status
Simulation time 19907870 ps
CPU time 1.2 seconds
Started Jun 28 06:00:18 PM PDT 24
Finished Jun 28 06:00:22 PM PDT 24
Peak memory 206884 kb
Host smart-7da5fbf8-0b28-46b7-ba5c-8e9b7377a48a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188020550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_ou
tstanding.188020550
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.872566026
Short name T1025
Test name
Test status
Simulation time 230715227 ps
CPU time 4.26 seconds
Started Jun 28 06:00:22 PM PDT 24
Finished Jun 28 06:00:31 PM PDT 24
Peak memory 215236 kb
Host smart-0673c486-2802-4ca7-8b92-878ebd431563
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872566026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.872566026
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.965610067
Short name T1056
Test name
Test status
Simulation time 389134577 ps
CPU time 2.41 seconds
Started Jun 28 06:00:25 PM PDT 24
Finished Jun 28 06:00:37 PM PDT 24
Peak memory 215112 kb
Host smart-94bd7b00-fa44-4f8a-9642-75281403477b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965610067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.965610067
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1218790876
Short name T1015
Test name
Test status
Simulation time 30658755 ps
CPU time 1.5 seconds
Started Jun 28 06:00:26 PM PDT 24
Finished Jun 28 06:00:38 PM PDT 24
Peak memory 215044 kb
Host smart-1857c545-acaf-47c7-aaf1-40bd29d5aefe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218790876 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1218790876
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.711206224
Short name T263
Test name
Test status
Simulation time 15419340 ps
CPU time 0.93 seconds
Started Jun 28 06:00:23 PM PDT 24
Finished Jun 28 06:00:30 PM PDT 24
Peak memory 206916 kb
Host smart-4c5d36ed-128b-4e6f-8584-fc990bd1e391
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711206224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.711206224
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3300088809
Short name T1036
Test name
Test status
Simulation time 56845869 ps
CPU time 0.87 seconds
Started Jun 28 06:00:24 PM PDT 24
Finished Jun 28 06:00:33 PM PDT 24
Peak memory 206868 kb
Host smart-bc0aac33-33c6-4adc-a86a-c05032459ab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300088809 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3300088809
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3865353833
Short name T1041
Test name
Test status
Simulation time 94376178 ps
CPU time 1.07 seconds
Started Jun 28 06:00:28 PM PDT 24
Finished Jun 28 06:00:39 PM PDT 24
Peak memory 206912 kb
Host smart-14e8c6ac-6d25-468b-887e-900dfaf6e8b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865353833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3865353833
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1991531796
Short name T1104
Test name
Test status
Simulation time 95850439 ps
CPU time 3.33 seconds
Started Jun 28 06:00:22 PM PDT 24
Finished Jun 28 06:00:30 PM PDT 24
Peak memory 215320 kb
Host smart-811ff9cf-9aad-421f-bd3f-4dfa146a507e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991531796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1991531796
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3510489527
Short name T293
Test name
Test status
Simulation time 603648511 ps
CPU time 1.66 seconds
Started Jun 28 06:00:17 PM PDT 24
Finished Jun 28 06:00:21 PM PDT 24
Peak memory 215292 kb
Host smart-69d77f14-666d-4625-bb86-78580d7518f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510489527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3510489527
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.584557543
Short name T1039
Test name
Test status
Simulation time 20516704 ps
CPU time 1.11 seconds
Started Jun 28 06:00:25 PM PDT 24
Finished Jun 28 06:00:34 PM PDT 24
Peak memory 216288 kb
Host smart-b4d4ae0d-e9be-479b-a871-27575d570a99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584557543 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.584557543
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3627985842
Short name T273
Test name
Test status
Simulation time 29274010 ps
CPU time 0.81 seconds
Started Jun 28 06:00:23 PM PDT 24
Finished Jun 28 06:00:31 PM PDT 24
Peak memory 206748 kb
Host smart-68a365af-0edc-4c1c-8420-8864d0c667c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627985842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3627985842
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2111888579
Short name T1042
Test name
Test status
Simulation time 12960959 ps
CPU time 0.87 seconds
Started Jun 28 06:00:28 PM PDT 24
Finished Jun 28 06:00:39 PM PDT 24
Peak memory 206856 kb
Host smart-91510714-43f2-45c4-8f02-317dd13909f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111888579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2111888579
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1457194976
Short name T1054
Test name
Test status
Simulation time 300301709 ps
CPU time 1.11 seconds
Started Jun 28 06:00:24 PM PDT 24
Finished Jun 28 06:00:31 PM PDT 24
Peak memory 207000 kb
Host smart-63ab2cf9-1b48-4ac8-94da-ed42a6f4c7c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457194976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1457194976
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3634589851
Short name T1129
Test name
Test status
Simulation time 91829532 ps
CPU time 3.32 seconds
Started Jun 28 06:00:28 PM PDT 24
Finished Jun 28 06:00:42 PM PDT 24
Peak memory 215260 kb
Host smart-0bed9e1a-fe96-4375-b812-1c91faab396b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634589851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3634589851
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1394187799
Short name T1047
Test name
Test status
Simulation time 165503275 ps
CPU time 1.62 seconds
Started Jun 28 06:00:23 PM PDT 24
Finished Jun 28 06:00:31 PM PDT 24
Peak memory 207004 kb
Host smart-4394da7e-a78b-48be-997b-cc895b45f092
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394187799 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1394187799
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3814552778
Short name T1021
Test name
Test status
Simulation time 38473805 ps
CPU time 1.13 seconds
Started Jun 28 06:00:25 PM PDT 24
Finished Jun 28 06:00:35 PM PDT 24
Peak memory 215208 kb
Host smart-c562d242-6c80-4142-8db1-20a0d91c8cab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814552778 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3814552778
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3981129251
Short name T1022
Test name
Test status
Simulation time 62084366 ps
CPU time 0.9 seconds
Started Jun 28 06:00:24 PM PDT 24
Finished Jun 28 06:00:31 PM PDT 24
Peak memory 206924 kb
Host smart-da1eb8bf-006b-48ba-ad0e-46006d59c2a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981129251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3981129251
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.128465022
Short name T1076
Test name
Test status
Simulation time 33176551 ps
CPU time 0.82 seconds
Started Jun 28 06:00:20 PM PDT 24
Finished Jun 28 06:00:24 PM PDT 24
Peak memory 206860 kb
Host smart-f1ebe8bb-3c5d-4445-944b-e77138c10b60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128465022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.128465022
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4191820144
Short name T282
Test name
Test status
Simulation time 67951134 ps
CPU time 1.3 seconds
Started Jun 28 06:00:25 PM PDT 24
Finished Jun 28 06:00:35 PM PDT 24
Peak memory 206952 kb
Host smart-2cef9576-e9e0-46d2-a009-fc7ee8393b78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191820144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.4191820144
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.292593458
Short name T1082
Test name
Test status
Simulation time 123646723 ps
CPU time 3.98 seconds
Started Jun 28 06:00:27 PM PDT 24
Finished Jun 28 06:00:41 PM PDT 24
Peak memory 215164 kb
Host smart-2caa8e47-5026-4352-ab61-2731659a355b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292593458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.292593458
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1079831197
Short name T300
Test name
Test status
Simulation time 120313486 ps
CPU time 1.81 seconds
Started Jun 28 06:00:24 PM PDT 24
Finished Jun 28 06:00:34 PM PDT 24
Peak memory 206916 kb
Host smart-43e36923-339c-4ae8-b0dc-aa3187bccdfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079831197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1079831197
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1535413393
Short name T274
Test name
Test status
Simulation time 43899114 ps
CPU time 1.56 seconds
Started Jun 28 06:00:09 PM PDT 24
Finished Jun 28 06:00:13 PM PDT 24
Peak memory 206896 kb
Host smart-e43d4948-283d-471a-a1fe-20dccc80e3b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535413393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1535413393
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2581376280
Short name T1119
Test name
Test status
Simulation time 235600552 ps
CPU time 5.09 seconds
Started Jun 28 06:00:12 PM PDT 24
Finished Jun 28 06:00:22 PM PDT 24
Peak memory 206908 kb
Host smart-205df414-d07f-41d6-b5a5-16bf9d07bd82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581376280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2581376280
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2356035753
Short name T1071
Test name
Test status
Simulation time 23437082 ps
CPU time 0.98 seconds
Started Jun 28 06:00:12 PM PDT 24
Finished Jun 28 06:00:17 PM PDT 24
Peak memory 206916 kb
Host smart-6b522a7b-8676-4540-aca9-5ed414dc3ce7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356035753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2356035753
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4040392364
Short name T1048
Test name
Test status
Simulation time 32231069 ps
CPU time 1.51 seconds
Started Jun 28 06:00:12 PM PDT 24
Finished Jun 28 06:00:18 PM PDT 24
Peak memory 215168 kb
Host smart-551fd34d-19e3-4e69-b896-d7169acdf132
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040392364 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.4040392364
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2395781224
Short name T1124
Test name
Test status
Simulation time 15124094 ps
CPU time 0.92 seconds
Started Jun 28 06:00:07 PM PDT 24
Finished Jun 28 06:00:11 PM PDT 24
Peak memory 207092 kb
Host smart-2ab23214-b2bf-4e60-aa84-ca221a01447f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395781224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2395781224
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1494393744
Short name T1087
Test name
Test status
Simulation time 14314991 ps
CPU time 0.87 seconds
Started Jun 28 06:00:07 PM PDT 24
Finished Jun 28 06:00:10 PM PDT 24
Peak memory 206868 kb
Host smart-dae39fba-d7f9-4391-bd09-806c295d941b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494393744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1494393744
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1523123812
Short name T281
Test name
Test status
Simulation time 25622627 ps
CPU time 1.21 seconds
Started Jun 28 06:00:09 PM PDT 24
Finished Jun 28 06:00:13 PM PDT 24
Peak memory 207064 kb
Host smart-aa68967d-401f-42e3-a022-7266e6d58e9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523123812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1523123812
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3892477419
Short name T1018
Test name
Test status
Simulation time 226486155 ps
CPU time 2.42 seconds
Started Jun 28 06:00:11 PM PDT 24
Finished Jun 28 06:00:17 PM PDT 24
Peak memory 219152 kb
Host smart-55672d5f-cca9-4110-80b1-00af198cf2da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892477419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3892477419
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.604065839
Short name T295
Test name
Test status
Simulation time 123454814 ps
CPU time 2.45 seconds
Started Jun 28 06:00:08 PM PDT 24
Finished Jun 28 06:00:13 PM PDT 24
Peak memory 215120 kb
Host smart-7977c935-9543-4766-aade-37e500b4eb22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604065839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.604065839
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.288898855
Short name T1089
Test name
Test status
Simulation time 37646597 ps
CPU time 0.8 seconds
Started Jun 28 06:00:21 PM PDT 24
Finished Jun 28 06:00:27 PM PDT 24
Peak memory 206676 kb
Host smart-585964e2-bbf4-49ca-8702-ecebc9d32c3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288898855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.288898855
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1173681576
Short name T1083
Test name
Test status
Simulation time 15458966 ps
CPU time 0.93 seconds
Started Jun 28 06:00:26 PM PDT 24
Finished Jun 28 06:00:37 PM PDT 24
Peak memory 206784 kb
Host smart-12320247-4315-4602-a65e-b5fc25c30ec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173681576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1173681576
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2829500044
Short name T1010
Test name
Test status
Simulation time 17042401 ps
CPU time 0.86 seconds
Started Jun 28 06:00:25 PM PDT 24
Finished Jun 28 06:00:34 PM PDT 24
Peak memory 206836 kb
Host smart-bec6bf01-0d64-4aba-9629-b740c9208ffe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829500044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2829500044
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2518133053
Short name T1040
Test name
Test status
Simulation time 14598332 ps
CPU time 0.86 seconds
Started Jun 28 06:00:25 PM PDT 24
Finished Jun 28 06:00:35 PM PDT 24
Peak memory 206832 kb
Host smart-1085162c-0092-4874-a3e8-c2f2f8081b99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518133053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2518133053
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.4040133994
Short name T1044
Test name
Test status
Simulation time 36894148 ps
CPU time 0.82 seconds
Started Jun 28 06:00:19 PM PDT 24
Finished Jun 28 06:00:23 PM PDT 24
Peak memory 206708 kb
Host smart-e6889725-6678-466e-81bf-1626aac7c6b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040133994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.4040133994
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.772565021
Short name T1101
Test name
Test status
Simulation time 37014115 ps
CPU time 0.79 seconds
Started Jun 28 06:00:26 PM PDT 24
Finished Jun 28 06:00:35 PM PDT 24
Peak memory 206604 kb
Host smart-1794fceb-9f87-4ee4-bafd-8107c2ee460a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772565021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.772565021
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.572660277
Short name T1017
Test name
Test status
Simulation time 25638771 ps
CPU time 0.8 seconds
Started Jun 28 06:00:25 PM PDT 24
Finished Jun 28 06:00:35 PM PDT 24
Peak memory 206688 kb
Host smart-ec30784f-d9cc-4957-b04f-782fe0bc4d6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572660277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.572660277
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3978378924
Short name T1075
Test name
Test status
Simulation time 25595178 ps
CPU time 0.88 seconds
Started Jun 28 06:00:21 PM PDT 24
Finished Jun 28 06:00:26 PM PDT 24
Peak memory 206860 kb
Host smart-8da0ee90-1a66-4661-beb7-618487c7e7d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978378924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3978378924
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1989995208
Short name T1064
Test name
Test status
Simulation time 15601087 ps
CPU time 0.89 seconds
Started Jun 28 06:00:23 PM PDT 24
Finished Jun 28 06:00:30 PM PDT 24
Peak memory 206864 kb
Host smart-1fad9e5b-f995-4a95-9345-a3ad1e4e20c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989995208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1989995208
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.840283178
Short name T1019
Test name
Test status
Simulation time 53883589 ps
CPU time 0.86 seconds
Started Jun 28 06:00:24 PM PDT 24
Finished Jun 28 06:00:33 PM PDT 24
Peak memory 206864 kb
Host smart-bd98bb33-4dbf-4f18-a7f2-bfb8f26a2ce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840283178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.840283178
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.650698194
Short name T1068
Test name
Test status
Simulation time 85469100 ps
CPU time 1.19 seconds
Started Jun 28 06:00:09 PM PDT 24
Finished Jun 28 06:00:13 PM PDT 24
Peak memory 206988 kb
Host smart-66ba80bc-aa58-4e3d-b49a-5ba5805c418b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650698194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.650698194
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3042609877
Short name T1125
Test name
Test status
Simulation time 509664479 ps
CPU time 6.58 seconds
Started Jun 28 06:00:09 PM PDT 24
Finished Jun 28 06:00:19 PM PDT 24
Peak memory 206904 kb
Host smart-fe183a03-bb70-4d83-866a-4b1aaea729a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042609877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3042609877
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.832201959
Short name T1058
Test name
Test status
Simulation time 71991873 ps
CPU time 0.88 seconds
Started Jun 28 06:00:12 PM PDT 24
Finished Jun 28 06:00:17 PM PDT 24
Peak memory 207072 kb
Host smart-0825ac11-ed5f-4472-8788-43f97e582180
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832201959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.832201959
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.855248574
Short name T1094
Test name
Test status
Simulation time 40213150 ps
CPU time 1.15 seconds
Started Jun 28 06:00:12 PM PDT 24
Finished Jun 28 06:00:18 PM PDT 24
Peak memory 217260 kb
Host smart-0e33ad4b-d9ee-4eb8-8c67-32d61d0658f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855248574 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.855248574
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1451401036
Short name T1103
Test name
Test status
Simulation time 23598466 ps
CPU time 1.09 seconds
Started Jun 28 06:00:04 PM PDT 24
Finished Jun 28 06:00:08 PM PDT 24
Peak memory 207128 kb
Host smart-993a55d8-214a-44d0-8392-30bc681bf1fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451401036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1451401036
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2947835169
Short name T1023
Test name
Test status
Simulation time 56586407 ps
CPU time 0.88 seconds
Started Jun 28 06:00:09 PM PDT 24
Finished Jun 28 06:00:13 PM PDT 24
Peak memory 206864 kb
Host smart-741e6d9c-6e13-4887-9369-76decad398ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947835169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2947835169
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2745664810
Short name T1033
Test name
Test status
Simulation time 50732586 ps
CPU time 1.04 seconds
Started Jun 28 06:00:09 PM PDT 24
Finished Jun 28 06:00:13 PM PDT 24
Peak memory 206840 kb
Host smart-fc68b1a2-ee35-4155-af71-eb650a4810fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745664810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2745664810
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1276433344
Short name T1091
Test name
Test status
Simulation time 229158296 ps
CPU time 3.86 seconds
Started Jun 28 06:00:12 PM PDT 24
Finished Jun 28 06:00:21 PM PDT 24
Peak memory 215264 kb
Host smart-517e97d4-2254-4039-bacc-227d77b4a8b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276433344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1276433344
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.383186584
Short name T294
Test name
Test status
Simulation time 120900498 ps
CPU time 1.4 seconds
Started Jun 28 06:00:11 PM PDT 24
Finished Jun 28 06:00:17 PM PDT 24
Peak memory 206924 kb
Host smart-ec3e31fb-1a47-41d8-a0a3-b59fc322d141
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383186584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.383186584
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2655438337
Short name T1004
Test name
Test status
Simulation time 23006343 ps
CPU time 0.83 seconds
Started Jun 28 06:00:26 PM PDT 24
Finished Jun 28 06:00:37 PM PDT 24
Peak memory 206868 kb
Host smart-428b0df6-f571-417a-812b-d762227632cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655438337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2655438337
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1888644273
Short name T1079
Test name
Test status
Simulation time 24881568 ps
CPU time 0.85 seconds
Started Jun 28 06:00:25 PM PDT 24
Finished Jun 28 06:00:35 PM PDT 24
Peak memory 206876 kb
Host smart-4f57f4b4-a2c5-4f63-a3e1-8eb26057efb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888644273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1888644273
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.4116548263
Short name T1011
Test name
Test status
Simulation time 34470259 ps
CPU time 0.83 seconds
Started Jun 28 06:00:24 PM PDT 24
Finished Jun 28 06:00:34 PM PDT 24
Peak memory 206692 kb
Host smart-93547bc6-c8e7-4870-b8df-361815fc3fc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116548263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.4116548263
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2107238128
Short name T1024
Test name
Test status
Simulation time 16222264 ps
CPU time 0.94 seconds
Started Jun 28 06:00:30 PM PDT 24
Finished Jun 28 06:00:41 PM PDT 24
Peak memory 206828 kb
Host smart-51adc64e-454a-4b14-8625-d061b0bdb22d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107238128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2107238128
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1932541832
Short name T1026
Test name
Test status
Simulation time 39443107 ps
CPU time 0.81 seconds
Started Jun 28 06:00:28 PM PDT 24
Finished Jun 28 06:00:39 PM PDT 24
Peak memory 206688 kb
Host smart-3df3bd1d-28f9-4fbd-b416-8848adb47e57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932541832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1932541832
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1043807160
Short name T1028
Test name
Test status
Simulation time 46144829 ps
CPU time 0.82 seconds
Started Jun 28 06:00:28 PM PDT 24
Finished Jun 28 06:00:40 PM PDT 24
Peak memory 206864 kb
Host smart-520fe975-252d-4b97-8427-f9f0950c9cc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043807160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1043807160
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.4185126226
Short name T1077
Test name
Test status
Simulation time 27137679 ps
CPU time 0.89 seconds
Started Jun 28 06:00:27 PM PDT 24
Finished Jun 28 06:00:38 PM PDT 24
Peak memory 206864 kb
Host smart-2ad0c325-4f3f-4f4e-97e8-445293698ea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185126226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.4185126226
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.569363367
Short name T1029
Test name
Test status
Simulation time 66823253 ps
CPU time 0.83 seconds
Started Jun 28 06:00:28 PM PDT 24
Finished Jun 28 06:00:40 PM PDT 24
Peak memory 206860 kb
Host smart-ac95d34f-1206-4c8f-88ef-e249c10eb022
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569363367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.569363367
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3298476780
Short name T1065
Test name
Test status
Simulation time 56746790 ps
CPU time 0.81 seconds
Started Jun 28 06:00:26 PM PDT 24
Finished Jun 28 06:00:36 PM PDT 24
Peak memory 206656 kb
Host smart-40ed16c4-1cf3-4292-b928-03a554e43dc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298476780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3298476780
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3905237531
Short name T1116
Test name
Test status
Simulation time 23342622 ps
CPU time 0.83 seconds
Started Jun 28 06:00:26 PM PDT 24
Finished Jun 28 06:00:35 PM PDT 24
Peak memory 206836 kb
Host smart-688fa3fc-bb9c-4bd9-b68c-7247d8d3a139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905237531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3905237531
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2443568693
Short name T253
Test name
Test status
Simulation time 179952750 ps
CPU time 1.17 seconds
Started Jun 28 06:00:11 PM PDT 24
Finished Jun 28 06:00:17 PM PDT 24
Peak memory 207148 kb
Host smart-57f4c075-6c8a-491f-9a3d-e4028e35da93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443568693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2443568693
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1837811376
Short name T1078
Test name
Test status
Simulation time 234551504 ps
CPU time 3.31 seconds
Started Jun 28 06:00:11 PM PDT 24
Finished Jun 28 06:00:18 PM PDT 24
Peak memory 206932 kb
Host smart-6566fa71-945b-479f-a63b-a598867b6ba0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837811376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1837811376
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3004830455
Short name T1110
Test name
Test status
Simulation time 25431307 ps
CPU time 0.86 seconds
Started Jun 28 06:00:12 PM PDT 24
Finished Jun 28 06:00:17 PM PDT 24
Peak memory 206892 kb
Host smart-6ce0e7a2-e09f-476f-a944-3a8ab0debca7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004830455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3004830455
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3588777294
Short name T1027
Test name
Test status
Simulation time 42653566 ps
CPU time 1.49 seconds
Started Jun 28 06:00:10 PM PDT 24
Finished Jun 28 06:00:15 PM PDT 24
Peak memory 215152 kb
Host smart-c8458ede-88e3-467b-a3b3-0b1ca06fc4ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588777294 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3588777294
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3455683805
Short name T266
Test name
Test status
Simulation time 30467801 ps
CPU time 0.84 seconds
Started Jun 28 06:00:08 PM PDT 24
Finished Jun 28 06:00:12 PM PDT 24
Peak memory 206712 kb
Host smart-f85282b7-e329-4641-8dc6-5ce514021a0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455683805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3455683805
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2092200698
Short name T1099
Test name
Test status
Simulation time 41833982 ps
CPU time 0.83 seconds
Started Jun 28 06:00:05 PM PDT 24
Finished Jun 28 06:00:08 PM PDT 24
Peak memory 206688 kb
Host smart-d64eeac7-e624-4f71-8e7d-c120884612d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092200698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2092200698
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3257358134
Short name T1126
Test name
Test status
Simulation time 44532356 ps
CPU time 0.92 seconds
Started Jun 28 06:00:09 PM PDT 24
Finished Jun 28 06:00:14 PM PDT 24
Peak memory 206916 kb
Host smart-46952d37-5743-414f-a8a7-bf5458345ea8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257358134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3257358134
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.554214224
Short name T1072
Test name
Test status
Simulation time 32790098 ps
CPU time 2.32 seconds
Started Jun 28 06:00:10 PM PDT 24
Finished Jun 28 06:00:16 PM PDT 24
Peak memory 215288 kb
Host smart-01aebee8-e72a-41d9-a2f9-af47a8148aad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554214224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.554214224
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2373729529
Short name T1031
Test name
Test status
Simulation time 291196443 ps
CPU time 2.39 seconds
Started Jun 28 06:00:12 PM PDT 24
Finished Jun 28 06:00:19 PM PDT 24
Peak memory 215268 kb
Host smart-d09f1e7a-267f-43bf-8a9e-d54330881b99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373729529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2373729529
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.31766523
Short name T1118
Test name
Test status
Simulation time 14662011 ps
CPU time 0.88 seconds
Started Jun 28 06:00:25 PM PDT 24
Finished Jun 28 06:00:35 PM PDT 24
Peak memory 206876 kb
Host smart-0fc92f08-29d4-4039-b78b-5b5c0a923cd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31766523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.31766523
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3933625062
Short name T1034
Test name
Test status
Simulation time 46910896 ps
CPU time 0.83 seconds
Started Jun 28 06:00:27 PM PDT 24
Finished Jun 28 06:00:37 PM PDT 24
Peak memory 206860 kb
Host smart-54028375-5ac2-4876-bb8c-86f9ac3f3161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933625062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3933625062
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3178421094
Short name T1006
Test name
Test status
Simulation time 40518301 ps
CPU time 0.8 seconds
Started Jun 28 06:00:23 PM PDT 24
Finished Jun 28 06:00:30 PM PDT 24
Peak memory 206868 kb
Host smart-113a605c-6e50-4783-bf2d-38660aa63ef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178421094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3178421094
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.337833268
Short name T1130
Test name
Test status
Simulation time 39006501 ps
CPU time 0.87 seconds
Started Jun 28 06:00:26 PM PDT 24
Finished Jun 28 06:00:37 PM PDT 24
Peak memory 206828 kb
Host smart-84a97da9-a563-4207-ac14-730a35baa058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337833268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.337833268
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1859768778
Short name T1043
Test name
Test status
Simulation time 120337737 ps
CPU time 0.88 seconds
Started Jun 28 06:00:23 PM PDT 24
Finished Jun 28 06:00:30 PM PDT 24
Peak memory 206820 kb
Host smart-441be7c9-a5bd-4ba1-9466-246ab2eefab4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859768778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1859768778
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2821241121
Short name T1120
Test name
Test status
Simulation time 16542876 ps
CPU time 0.89 seconds
Started Jun 28 06:00:26 PM PDT 24
Finished Jun 28 06:00:35 PM PDT 24
Peak memory 206836 kb
Host smart-96440290-5627-48d2-949e-49959fc1088a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821241121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2821241121
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2346023343
Short name T1035
Test name
Test status
Simulation time 56879489 ps
CPU time 0.86 seconds
Started Jun 28 06:00:25 PM PDT 24
Finished Jun 28 06:00:35 PM PDT 24
Peak memory 206836 kb
Host smart-082bc037-6b7d-40bc-a0e1-268483b638f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346023343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2346023343
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2832367907
Short name T1053
Test name
Test status
Simulation time 45150169 ps
CPU time 0.88 seconds
Started Jun 28 06:00:26 PM PDT 24
Finished Jun 28 06:00:37 PM PDT 24
Peak memory 206836 kb
Host smart-0e270cd6-0543-468a-a0c0-1627d0dd0ec8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832367907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2832367907
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2985287247
Short name T1069
Test name
Test status
Simulation time 12155813 ps
CPU time 0.86 seconds
Started Jun 28 06:00:25 PM PDT 24
Finished Jun 28 06:00:35 PM PDT 24
Peak memory 206876 kb
Host smart-be518819-84b0-41aa-acc2-bc010d8950b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985287247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2985287247
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1929661730
Short name T1097
Test name
Test status
Simulation time 24496560 ps
CPU time 0.85 seconds
Started Jun 28 06:00:29 PM PDT 24
Finished Jun 28 06:00:40 PM PDT 24
Peak memory 206828 kb
Host smart-0e431133-304e-4c8b-8ee0-596111b9873f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929661730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1929661730
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3311447771
Short name T1059
Test name
Test status
Simulation time 33387643 ps
CPU time 1.1 seconds
Started Jun 28 06:00:09 PM PDT 24
Finished Jun 28 06:00:13 PM PDT 24
Peak memory 215136 kb
Host smart-99fa739c-e775-4781-8672-0515b29e40ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311447771 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3311447771
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.166427776
Short name T1092
Test name
Test status
Simulation time 117252925 ps
CPU time 0.94 seconds
Started Jun 28 06:00:05 PM PDT 24
Finished Jun 28 06:00:08 PM PDT 24
Peak memory 206748 kb
Host smart-48638aaf-e2b5-4970-90b7-5d8c77a2bd92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166427776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.166427776
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2452706617
Short name T1005
Test name
Test status
Simulation time 44540911 ps
CPU time 0.81 seconds
Started Jun 28 06:00:11 PM PDT 24
Finished Jun 28 06:00:16 PM PDT 24
Peak memory 206604 kb
Host smart-a7c8e669-1805-4120-9868-21d94beec2a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452706617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2452706617
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2613663517
Short name T286
Test name
Test status
Simulation time 124535416 ps
CPU time 1.44 seconds
Started Jun 28 06:00:07 PM PDT 24
Finished Jun 28 06:00:10 PM PDT 24
Peak memory 206984 kb
Host smart-6c929987-35eb-4de5-bf47-5042d0a5a0ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613663517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2613663517
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.243656038
Short name T1090
Test name
Test status
Simulation time 50417950 ps
CPU time 1.96 seconds
Started Jun 28 06:00:08 PM PDT 24
Finished Jun 28 06:00:13 PM PDT 24
Peak memory 218964 kb
Host smart-6e64bd86-877c-44a7-ac2b-21f9fc8a4c50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243656038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.243656038
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.176303866
Short name T1049
Test name
Test status
Simulation time 94745617 ps
CPU time 1.67 seconds
Started Jun 28 06:00:09 PM PDT 24
Finished Jun 28 06:00:15 PM PDT 24
Peak memory 207016 kb
Host smart-17b8e94c-77b2-4e24-8d14-24233e89066a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176303866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.176303866
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.802281211
Short name T1115
Test name
Test status
Simulation time 94942000 ps
CPU time 1.37 seconds
Started Jun 28 06:00:12 PM PDT 24
Finished Jun 28 06:00:17 PM PDT 24
Peak memory 218088 kb
Host smart-574eb6b0-7b16-4545-8935-9ea0c27a500d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802281211 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.802281211
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1868834612
Short name T269
Test name
Test status
Simulation time 20408673 ps
CPU time 0.93 seconds
Started Jun 28 06:00:12 PM PDT 24
Finished Jun 28 06:00:18 PM PDT 24
Peak memory 206920 kb
Host smart-a8dc7c47-6f87-441c-97fe-cdb1fc193b68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868834612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1868834612
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3783325736
Short name T1080
Test name
Test status
Simulation time 16433127 ps
CPU time 0.81 seconds
Started Jun 28 06:00:11 PM PDT 24
Finished Jun 28 06:00:17 PM PDT 24
Peak memory 206688 kb
Host smart-57d49022-6a3c-46f0-b3b8-6de2385996a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783325736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3783325736
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.777337386
Short name T1045
Test name
Test status
Simulation time 160984435 ps
CPU time 1.5 seconds
Started Jun 28 06:00:09 PM PDT 24
Finished Jun 28 06:00:14 PM PDT 24
Peak memory 206928 kb
Host smart-95072317-1ac7-471b-a0aa-70e954158788
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777337386 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.777337386
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3424888289
Short name T1013
Test name
Test status
Simulation time 61496936 ps
CPU time 1.76 seconds
Started Jun 28 06:00:12 PM PDT 24
Finished Jun 28 06:00:19 PM PDT 24
Peak memory 215156 kb
Host smart-53aa6bd2-324b-497d-a02c-a4887df42b65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424888289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3424888289
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1746413374
Short name T306
Test name
Test status
Simulation time 89528587 ps
CPU time 2.47 seconds
Started Jun 28 06:00:10 PM PDT 24
Finished Jun 28 06:00:16 PM PDT 24
Peak memory 206968 kb
Host smart-3693ee96-c7f0-4194-98e6-8e283d68c611
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746413374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1746413374
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1282099548
Short name T1016
Test name
Test status
Simulation time 35996242 ps
CPU time 1.66 seconds
Started Jun 28 06:00:25 PM PDT 24
Finished Jun 28 06:00:35 PM PDT 24
Peak memory 215188 kb
Host smart-263e9974-cfde-410a-b2f7-f54817a3a749
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282099548 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1282099548
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1244163801
Short name T1128
Test name
Test status
Simulation time 20693979 ps
CPU time 0.82 seconds
Started Jun 28 06:00:17 PM PDT 24
Finished Jun 28 06:00:20 PM PDT 24
Peak memory 206720 kb
Host smart-ffc72664-a85d-4414-8e39-84d8f511f49a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244163801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1244163801
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3551853936
Short name T1057
Test name
Test status
Simulation time 26223438 ps
CPU time 0.89 seconds
Started Jun 28 06:00:22 PM PDT 24
Finished Jun 28 06:00:29 PM PDT 24
Peak memory 206868 kb
Host smart-0e68deab-8178-4e8e-91ff-21b6c0187bc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551853936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3551853936
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1326781338
Short name T279
Test name
Test status
Simulation time 20486849 ps
CPU time 1.14 seconds
Started Jun 28 06:00:18 PM PDT 24
Finished Jun 28 06:00:22 PM PDT 24
Peak memory 206840 kb
Host smart-eeed4c02-2a54-48d6-b62e-44fec6c16183
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326781338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1326781338
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3789752229
Short name T1012
Test name
Test status
Simulation time 50571684 ps
CPU time 2.01 seconds
Started Jun 28 06:00:09 PM PDT 24
Finished Jun 28 06:00:14 PM PDT 24
Peak memory 215352 kb
Host smart-f2b328cb-d671-49c5-a79c-ba95fd21ca17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789752229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3789752229
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.194010585
Short name T1030
Test name
Test status
Simulation time 74290876 ps
CPU time 1.48 seconds
Started Jun 28 06:00:19 PM PDT 24
Finished Jun 28 06:00:23 PM PDT 24
Peak memory 215200 kb
Host smart-b9c0f311-f164-484e-bafc-2e6d9720ed30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194010585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.194010585
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3514121181
Short name T1062
Test name
Test status
Simulation time 44754407 ps
CPU time 1.65 seconds
Started Jun 28 06:00:30 PM PDT 24
Finished Jun 28 06:00:42 PM PDT 24
Peak memory 215224 kb
Host smart-60240c2b-4af3-403d-8662-816bf53d02bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514121181 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3514121181
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1259302831
Short name T1007
Test name
Test status
Simulation time 25819354 ps
CPU time 0.89 seconds
Started Jun 28 06:00:23 PM PDT 24
Finished Jun 28 06:00:30 PM PDT 24
Peak memory 206856 kb
Host smart-c05bd4a5-60d5-4fae-bb2f-c2783ed945e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259302831 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1259302831
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1145027806
Short name T1055
Test name
Test status
Simulation time 14744605 ps
CPU time 0.91 seconds
Started Jun 28 06:00:22 PM PDT 24
Finished Jun 28 06:00:28 PM PDT 24
Peak memory 206860 kb
Host smart-125bbf8d-97ff-429b-9b78-44eabed113d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145027806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1145027806
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1449580201
Short name T1061
Test name
Test status
Simulation time 51504290 ps
CPU time 1.11 seconds
Started Jun 28 06:00:23 PM PDT 24
Finished Jun 28 06:00:30 PM PDT 24
Peak memory 206880 kb
Host smart-54f507a3-a557-4d6e-8d25-8f7dbcf46b3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449580201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1449580201
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.901493573
Short name T1003
Test name
Test status
Simulation time 446947909 ps
CPU time 4.07 seconds
Started Jun 28 06:00:20 PM PDT 24
Finished Jun 28 06:00:27 PM PDT 24
Peak memory 215336 kb
Host smart-b2e9f775-4ca3-4a51-a655-a25b5f612136
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901493573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.901493573
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3956415563
Short name T305
Test name
Test status
Simulation time 473718001 ps
CPU time 1.68 seconds
Started Jun 28 06:00:23 PM PDT 24
Finished Jun 28 06:00:29 PM PDT 24
Peak memory 215120 kb
Host smart-1f1399dc-6b9e-4b28-b39f-44f58e3b5da2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956415563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3956415563
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1212979209
Short name T1093
Test name
Test status
Simulation time 112818295 ps
CPU time 1.35 seconds
Started Jun 28 06:00:19 PM PDT 24
Finished Jun 28 06:00:22 PM PDT 24
Peak memory 215100 kb
Host smart-9df1361c-3f9c-4fe4-88e4-59592d62ab67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212979209 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1212979209
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3101662787
Short name T264
Test name
Test status
Simulation time 24269236 ps
CPU time 0.87 seconds
Started Jun 28 06:00:24 PM PDT 24
Finished Jun 28 06:00:31 PM PDT 24
Peak memory 206932 kb
Host smart-9eda4700-4ae4-4ab5-93dc-b50da03a39ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101662787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3101662787
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3080366751
Short name T1105
Test name
Test status
Simulation time 26283453 ps
CPU time 0.9 seconds
Started Jun 28 06:00:22 PM PDT 24
Finished Jun 28 06:00:29 PM PDT 24
Peak memory 206864 kb
Host smart-5dfe6fb9-31e1-4db1-a89a-88a2c23a5c6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080366751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3080366751
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1836646636
Short name T278
Test name
Test status
Simulation time 34374524 ps
CPU time 1.02 seconds
Started Jun 28 06:00:21 PM PDT 24
Finished Jun 28 06:00:27 PM PDT 24
Peak memory 207048 kb
Host smart-6e024def-e8ca-4544-af6a-18586fda4da3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836646636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1836646636
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.4148358260
Short name T1102
Test name
Test status
Simulation time 551754557 ps
CPU time 2.75 seconds
Started Jun 28 06:00:24 PM PDT 24
Finished Jun 28 06:00:35 PM PDT 24
Peak memory 215184 kb
Host smart-c8adc592-ab29-46c8-b7ec-4b14f3aebfcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148358260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.4148358260
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2590639455
Short name T1060
Test name
Test status
Simulation time 385209365 ps
CPU time 2.47 seconds
Started Jun 28 06:00:19 PM PDT 24
Finished Jun 28 06:00:24 PM PDT 24
Peak memory 207324 kb
Host smart-0454b08f-b259-4c6d-9f2c-657ec0250970
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590639455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2590639455
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.888552181
Short name T903
Test name
Test status
Simulation time 247282642 ps
CPU time 1.37 seconds
Started Jun 28 06:01:23 PM PDT 24
Finished Jun 28 06:01:27 PM PDT 24
Peak memory 219268 kb
Host smart-d4eb4c76-b5d0-49a5-92b5-0889f03b3acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888552181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.888552181
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.482108396
Short name T65
Test name
Test status
Simulation time 18147606 ps
CPU time 1.02 seconds
Started Jun 28 06:01:22 PM PDT 24
Finished Jun 28 06:01:26 PM PDT 24
Peak memory 207032 kb
Host smart-1ec78bbf-2c21-4f0c-bf49-b362282cb97a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482108396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.482108396
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.362623604
Short name T944
Test name
Test status
Simulation time 12109969 ps
CPU time 0.95 seconds
Started Jun 28 06:01:17 PM PDT 24
Finished Jun 28 06:01:19 PM PDT 24
Peak memory 216744 kb
Host smart-783a7a82-0819-4297-8138-b223eee5623e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362623604 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.362623604
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2856840898
Short name T878
Test name
Test status
Simulation time 39629847 ps
CPU time 1.04 seconds
Started Jun 28 06:01:18 PM PDT 24
Finished Jun 28 06:01:22 PM PDT 24
Peak memory 217320 kb
Host smart-c62e6f1b-8635-4eb4-8433-e2a81c9d85f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856840898 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2856840898
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1695362145
Short name T371
Test name
Test status
Simulation time 26297507 ps
CPU time 1.2 seconds
Started Jun 28 06:01:22 PM PDT 24
Finished Jun 28 06:01:26 PM PDT 24
Peak memory 219064 kb
Host smart-f1c23a54-7a35-40cd-84eb-9533e22401c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695362145 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1695362145
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.991773704
Short name T255
Test name
Test status
Simulation time 77241704 ps
CPU time 1.29 seconds
Started Jun 28 06:01:19 PM PDT 24
Finished Jun 28 06:01:24 PM PDT 24
Peak memory 217612 kb
Host smart-2d230301-9af1-48d7-ba91-086c3768df8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991773704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.991773704
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.3247942956
Short name T766
Test name
Test status
Simulation time 22433908 ps
CPU time 1.29 seconds
Started Jun 28 06:01:19 PM PDT 24
Finished Jun 28 06:01:24 PM PDT 24
Peak memory 224292 kb
Host smart-b76d9325-2606-43bb-81c1-99f14a58d1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247942956 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3247942956
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_smoke.986353289
Short name T390
Test name
Test status
Simulation time 46416338 ps
CPU time 1.01 seconds
Started Jun 28 06:01:20 PM PDT 24
Finished Jun 28 06:01:24 PM PDT 24
Peak memory 215792 kb
Host smart-21ddd7c0-eb19-4834-af42-7b677a599704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986353289 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.986353289
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1553175481
Short name T248
Test name
Test status
Simulation time 443178032 ps
CPU time 8.01 seconds
Started Jun 28 06:01:16 PM PDT 24
Finished Jun 28 06:01:25 PM PDT 24
Peak memory 217552 kb
Host smart-706196a1-1827-4341-9df7-3ba61069b589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553175481 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1553175481
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3181255347
Short name T791
Test name
Test status
Simulation time 110019465043 ps
CPU time 864.35 seconds
Started Jun 28 06:01:18 PM PDT 24
Finished Jun 28 06:15:45 PM PDT 24
Peak memory 222296 kb
Host smart-278d51b0-2880-4645-bcb7-36fa128b45a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181255347 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3181255347
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.295977457
Short name T872
Test name
Test status
Simulation time 125573203 ps
CPU time 0.85 seconds
Started Jun 28 06:01:20 PM PDT 24
Finished Jun 28 06:01:24 PM PDT 24
Peak memory 215288 kb
Host smart-1789558a-fccb-4a95-a6e7-f246504d4990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295977457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.295977457
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2308527217
Short name T8
Test name
Test status
Simulation time 64745551 ps
CPU time 1.28 seconds
Started Jun 28 06:01:16 PM PDT 24
Finished Jun 28 06:01:19 PM PDT 24
Peak memory 217024 kb
Host smart-b06b5597-bdee-4ddc-9af9-b85021d8a7fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308527217 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2308527217
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.3267500419
Short name T663
Test name
Test status
Simulation time 37188063 ps
CPU time 1.19 seconds
Started Jun 28 06:01:21 PM PDT 24
Finished Jun 28 06:01:25 PM PDT 24
Peak memory 221088 kb
Host smart-e1658912-95f3-4083-a6a5-1f0826634b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267500419 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3267500419
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2494201625
Short name T405
Test name
Test status
Simulation time 80719930 ps
CPU time 1.17 seconds
Started Jun 28 06:01:18 PM PDT 24
Finished Jun 28 06:01:22 PM PDT 24
Peak memory 220280 kb
Host smart-17f33f79-9471-4ee6-9daa-0df64b52f092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494201625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2494201625
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2946953588
Short name T226
Test name
Test status
Simulation time 25656931 ps
CPU time 1 seconds
Started Jun 28 06:01:13 PM PDT 24
Finished Jun 28 06:01:15 PM PDT 24
Peak memory 215728 kb
Host smart-bc44fb12-72d6-466e-a2de-b99ca2c94702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946953588 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2946953588
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.1758257085
Short name T893
Test name
Test status
Simulation time 18273523 ps
CPU time 1.1 seconds
Started Jun 28 06:01:17 PM PDT 24
Finished Jun 28 06:01:20 PM PDT 24
Peak memory 207408 kb
Host smart-561936d2-23b7-418c-a736-fa5199874150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758257085 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1758257085
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3201568560
Short name T11
Test name
Test status
Simulation time 1009661411 ps
CPU time 7.77 seconds
Started Jun 28 06:01:12 PM PDT 24
Finished Jun 28 06:01:21 PM PDT 24
Peak memory 237444 kb
Host smart-97e8e242-c02c-4f77-8886-bfcefd98ae9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201568560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3201568560
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.3948030686
Short name T578
Test name
Test status
Simulation time 41954822 ps
CPU time 0.93 seconds
Started Jun 28 06:01:18 PM PDT 24
Finished Jun 28 06:01:21 PM PDT 24
Peak memory 215608 kb
Host smart-e7b6dfac-8448-4e12-a97a-0e777dff225d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948030686 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3948030686
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.57005352
Short name T736
Test name
Test status
Simulation time 482948833 ps
CPU time 5.07 seconds
Started Jun 28 06:01:18 PM PDT 24
Finished Jun 28 06:01:26 PM PDT 24
Peak memory 215620 kb
Host smart-f901b174-f8fd-4e86-ad83-8ed655271ffe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57005352 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.57005352
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1886993087
Short name T235
Test name
Test status
Simulation time 31405615677 ps
CPU time 159.21 seconds
Started Jun 28 06:01:19 PM PDT 24
Finished Jun 28 06:04:01 PM PDT 24
Peak memory 222916 kb
Host smart-c33dfe4a-b2b3-4c88-ab96-518d8cf9237f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886993087 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1886993087
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.616253443
Short name T367
Test name
Test status
Simulation time 98280750 ps
CPU time 0.95 seconds
Started Jun 28 06:01:38 PM PDT 24
Finished Jun 28 06:01:44 PM PDT 24
Peak memory 215464 kb
Host smart-2487760f-7b42-49af-b2d0-e9513a2f7c59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616253443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.616253443
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.780246667
Short name T98
Test name
Test status
Simulation time 90022675 ps
CPU time 0.85 seconds
Started Jun 28 06:01:38 PM PDT 24
Finished Jun 28 06:01:43 PM PDT 24
Peak memory 216488 kb
Host smart-915d1cd7-8ba9-4329-948d-5190e3b8f94e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780246667 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.780246667
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1132855502
Short name T789
Test name
Test status
Simulation time 57820686 ps
CPU time 1.05 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:45 PM PDT 24
Peak memory 218584 kb
Host smart-3b100000-be89-4ea2-a4f7-e009aa012db8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132855502 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1132855502
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_genbits.494952303
Short name T458
Test name
Test status
Simulation time 36463327 ps
CPU time 1.35 seconds
Started Jun 28 06:01:51 PM PDT 24
Finished Jun 28 06:01:59 PM PDT 24
Peak memory 218788 kb
Host smart-8a0f198d-a6f5-4fb7-aaf1-6fea573b308b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494952303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.494952303
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.1796428632
Short name T522
Test name
Test status
Simulation time 81757929 ps
CPU time 0.96 seconds
Started Jun 28 06:01:47 PM PDT 24
Finished Jun 28 06:01:52 PM PDT 24
Peak memory 215600 kb
Host smart-6a1fdb9b-63a3-4c3a-bc0a-d045151c23dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796428632 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1796428632
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2318833642
Short name T770
Test name
Test status
Simulation time 63460797 ps
CPU time 1.76 seconds
Started Jun 28 06:01:51 PM PDT 24
Finished Jun 28 06:01:59 PM PDT 24
Peak memory 218652 kb
Host smart-91b94dbd-ac45-4326-8a21-18aa6bb35e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318833642 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2318833642
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1677015402
Short name T333
Test name
Test status
Simulation time 424066957596 ps
CPU time 1615.72 seconds
Started Jun 28 06:01:44 PM PDT 24
Finished Jun 28 06:28:44 PM PDT 24
Peak memory 224132 kb
Host smart-6cf3b9fa-e0c9-4a00-a057-7bccbb1c979e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677015402 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1677015402
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.2556080334
Short name T555
Test name
Test status
Simulation time 36825940 ps
CPU time 1.1 seconds
Started Jun 28 06:02:57 PM PDT 24
Finished Jun 28 06:03:04 PM PDT 24
Peak memory 219980 kb
Host smart-9eeef173-3035-44d4-b45a-2218652d68b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556080334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.2556080334
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.1303150645
Short name T461
Test name
Test status
Simulation time 43730763 ps
CPU time 1.49 seconds
Started Jun 28 06:03:03 PM PDT 24
Finished Jun 28 06:03:12 PM PDT 24
Peak memory 218668 kb
Host smart-b8846c33-a798-4d2e-ae3b-e307c9bdb53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303150645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1303150645
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.3618232165
Short name T366
Test name
Test status
Simulation time 37200297 ps
CPU time 1.38 seconds
Started Jun 28 06:02:57 PM PDT 24
Finished Jun 28 06:03:03 PM PDT 24
Peak memory 218712 kb
Host smart-b10b5fe6-300c-4721-9053-471db929b9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618232165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3618232165
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.83671123
Short name T188
Test name
Test status
Simulation time 176542667 ps
CPU time 1.29 seconds
Started Jun 28 06:02:59 PM PDT 24
Finished Jun 28 06:03:06 PM PDT 24
Peak memory 215992 kb
Host smart-a57fdb1a-5df6-41a7-9089-ddea7ba3ab2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83671123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.83671123
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.487207402
Short name T548
Test name
Test status
Simulation time 35147748 ps
CPU time 1.44 seconds
Started Jun 28 06:03:06 PM PDT 24
Finished Jun 28 06:03:16 PM PDT 24
Peak memory 218816 kb
Host smart-262e54de-5f58-4775-b66c-81ad04d0b5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487207402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.487207402
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.1052814955
Short name T772
Test name
Test status
Simulation time 96303608 ps
CPU time 1.11 seconds
Started Jun 28 06:03:06 PM PDT 24
Finished Jun 28 06:03:15 PM PDT 24
Peak memory 218684 kb
Host smart-ad59992d-a416-4617-86e8-21f989d54de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052814955 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1052814955
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/104.edn_alert.904099347
Short name T844
Test name
Test status
Simulation time 27544214 ps
CPU time 1.22 seconds
Started Jun 28 06:03:01 PM PDT 24
Finished Jun 28 06:03:08 PM PDT 24
Peak memory 220596 kb
Host smart-6fca74b2-7970-442a-acb0-3f72ab8b4d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904099347 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.904099347
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/105.edn_alert.142847762
Short name T320
Test name
Test status
Simulation time 28792915 ps
CPU time 1.22 seconds
Started Jun 28 06:03:08 PM PDT 24
Finished Jun 28 06:03:17 PM PDT 24
Peak memory 220112 kb
Host smart-26f09d2d-2d8b-45ce-9514-cb431931babb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142847762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.142847762
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.1055536068
Short name T727
Test name
Test status
Simulation time 104641384 ps
CPU time 1.3 seconds
Started Jun 28 06:03:02 PM PDT 24
Finished Jun 28 06:03:11 PM PDT 24
Peak memory 218840 kb
Host smart-a23c8339-3942-4c4c-a056-5b69c5115579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055536068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1055536068
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.3981340202
Short name T251
Test name
Test status
Simulation time 90692399 ps
CPU time 1.27 seconds
Started Jun 28 06:03:07 PM PDT 24
Finished Jun 28 06:03:17 PM PDT 24
Peak memory 216000 kb
Host smart-a35d6a69-6896-457e-a521-9ef9440f6ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981340202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3981340202
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.3567826515
Short name T743
Test name
Test status
Simulation time 31158187 ps
CPU time 1.3 seconds
Started Jun 28 06:03:03 PM PDT 24
Finished Jun 28 06:03:12 PM PDT 24
Peak memory 220168 kb
Host smart-bd0e40fe-fd61-4561-87e3-f95d6a88348f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567826515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3567826515
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.3509362073
Short name T899
Test name
Test status
Simulation time 79370546 ps
CPU time 1.15 seconds
Started Jun 28 06:03:00 PM PDT 24
Finished Jun 28 06:03:07 PM PDT 24
Peak memory 219336 kb
Host smart-72f078b6-5b25-4949-9ddb-02ad77a7c696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509362073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.3509362073
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.3476049907
Short name T584
Test name
Test status
Simulation time 113851905 ps
CPU time 1.54 seconds
Started Jun 28 06:03:02 PM PDT 24
Finished Jun 28 06:03:11 PM PDT 24
Peak memory 219272 kb
Host smart-e720d6d1-d001-4fe5-8047-074bcfe1b228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476049907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3476049907
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.933636474
Short name T544
Test name
Test status
Simulation time 49496103 ps
CPU time 1.24 seconds
Started Jun 28 06:03:02 PM PDT 24
Finished Jun 28 06:03:11 PM PDT 24
Peak memory 220016 kb
Host smart-92e350a2-ce1f-4b2e-b9f1-840d88b0ed61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933636474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.933636474
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.2144906537
Short name T363
Test name
Test status
Simulation time 31117476 ps
CPU time 1.27 seconds
Started Jun 28 06:03:02 PM PDT 24
Finished Jun 28 06:03:11 PM PDT 24
Peak memory 218672 kb
Host smart-6d511cbe-b3c2-4330-9635-8bab63320ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144906537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2144906537
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.355147962
Short name T169
Test name
Test status
Simulation time 27562055 ps
CPU time 1.27 seconds
Started Jun 28 06:01:40 PM PDT 24
Finished Jun 28 06:01:47 PM PDT 24
Peak memory 216184 kb
Host smart-897d4120-5f6b-43e7-ad2c-03f6a74d54bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355147962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.355147962
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.1133370319
Short name T241
Test name
Test status
Simulation time 21633842 ps
CPU time 0.86 seconds
Started Jun 28 06:01:44 PM PDT 24
Finished Jun 28 06:01:50 PM PDT 24
Peak memory 206824 kb
Host smart-61b30250-6841-404e-b0b4-446ddf9a52f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133370319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1133370319
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.626777251
Short name T490
Test name
Test status
Simulation time 37175055 ps
CPU time 1.28 seconds
Started Jun 28 06:01:38 PM PDT 24
Finished Jun 28 06:01:44 PM PDT 24
Peak memory 218620 kb
Host smart-fc9b7ea2-6808-4cb2-9c6c-bcd560355e12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626777251 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.626777251
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_genbits.1843353209
Short name T998
Test name
Test status
Simulation time 89891609 ps
CPU time 3.27 seconds
Started Jun 28 06:01:38 PM PDT 24
Finished Jun 28 06:01:46 PM PDT 24
Peak memory 220540 kb
Host smart-8ad78d72-fd64-4d3d-add0-70d619d75fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843353209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1843353209
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.3430348845
Short name T398
Test name
Test status
Simulation time 16814209 ps
CPU time 1.11 seconds
Started Jun 28 06:01:35 PM PDT 24
Finished Jun 28 06:01:38 PM PDT 24
Peak memory 215616 kb
Host smart-253e76ef-e07d-402c-b217-f0485b176d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430348845 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3430348845
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.661633790
Short name T246
Test name
Test status
Simulation time 366171217 ps
CPU time 4.12 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:49 PM PDT 24
Peak memory 217528 kb
Host smart-e1e574e6-59f2-404d-b9c6-f5da32f78dc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661633790 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.661633790
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.91452415
Short name T102
Test name
Test status
Simulation time 111839600516 ps
CPU time 719.61 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:13:45 PM PDT 24
Peak memory 221628 kb
Host smart-3d89598d-9dc4-4348-83cf-6975cbfe2ceb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91452415 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.91452415
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.634540556
Short name T954
Test name
Test status
Simulation time 90425970 ps
CPU time 1.4 seconds
Started Jun 28 06:03:01 PM PDT 24
Finished Jun 28 06:03:08 PM PDT 24
Peak memory 218808 kb
Host smart-86f00a05-edf3-4ffd-b4ea-a6699469f1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634540556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.634540556
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.4290501054
Short name T19
Test name
Test status
Simulation time 82550525 ps
CPU time 1.15 seconds
Started Jun 28 06:02:59 PM PDT 24
Finished Jun 28 06:03:05 PM PDT 24
Peak memory 218732 kb
Host smart-40d1b55f-27bb-4af8-9703-755f2d6d629b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290501054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.4290501054
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.541320029
Short name T485
Test name
Test status
Simulation time 54249151 ps
CPU time 1.65 seconds
Started Jun 28 06:03:05 PM PDT 24
Finished Jun 28 06:03:14 PM PDT 24
Peak memory 218796 kb
Host smart-a273a933-81fc-4fe0-ac3b-c517bdafe6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541320029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.541320029
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2567949803
Short name T811
Test name
Test status
Simulation time 105089598 ps
CPU time 1.24 seconds
Started Jun 28 06:03:01 PM PDT 24
Finished Jun 28 06:03:09 PM PDT 24
Peak memory 217476 kb
Host smart-053944ab-33b7-43f2-a2f9-9f4bc7efcc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567949803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2567949803
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.4235090902
Short name T194
Test name
Test status
Simulation time 50573652 ps
CPU time 1.14 seconds
Started Jun 28 06:03:10 PM PDT 24
Finished Jun 28 06:03:20 PM PDT 24
Peak memory 220888 kb
Host smart-85d62636-0495-44db-9418-83eeeb5f58b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235090902 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.4235090902
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.3846421980
Short name T394
Test name
Test status
Simulation time 32528281 ps
CPU time 1.31 seconds
Started Jun 28 06:03:04 PM PDT 24
Finished Jun 28 06:03:13 PM PDT 24
Peak memory 218792 kb
Host smart-139d8beb-139d-4b9a-aa4d-55e8dff34892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846421980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3846421980
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.1783194788
Short name T698
Test name
Test status
Simulation time 42093948 ps
CPU time 1.15 seconds
Started Jun 28 06:03:08 PM PDT 24
Finished Jun 28 06:03:17 PM PDT 24
Peak memory 220124 kb
Host smart-f4186d72-5669-4fd0-abf1-fb6bf8e70c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783194788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.1783194788
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.3772533184
Short name T20
Test name
Test status
Simulation time 91476917 ps
CPU time 1.12 seconds
Started Jun 28 06:03:08 PM PDT 24
Finished Jun 28 06:03:17 PM PDT 24
Peak memory 217624 kb
Host smart-63c7bf90-2211-4c32-872d-aaa934c649a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772533184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3772533184
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.3839137180
Short name T289
Test name
Test status
Simulation time 83424581 ps
CPU time 1.21 seconds
Started Jun 28 06:02:58 PM PDT 24
Finished Jun 28 06:03:04 PM PDT 24
Peak memory 220764 kb
Host smart-b5225fae-057a-44a3-82b9-977ee9baec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839137180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.3839137180
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.468578400
Short name T672
Test name
Test status
Simulation time 83416758 ps
CPU time 1.25 seconds
Started Jun 28 06:02:59 PM PDT 24
Finished Jun 28 06:03:06 PM PDT 24
Peak memory 220176 kb
Host smart-d6b154cb-d48a-4f02-934a-652a51a73d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468578400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.468578400
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.305209347
Short name T799
Test name
Test status
Simulation time 129796752 ps
CPU time 1.19 seconds
Started Jun 28 06:03:07 PM PDT 24
Finished Jun 28 06:03:16 PM PDT 24
Peak memory 218828 kb
Host smart-a011f412-cbcd-4955-bc62-ef06bdba50a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305209347 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.305209347
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.129800437
Short name T694
Test name
Test status
Simulation time 56280194 ps
CPU time 1.33 seconds
Started Jun 28 06:03:05 PM PDT 24
Finished Jun 28 06:03:14 PM PDT 24
Peak memory 218816 kb
Host smart-fe666873-7efb-493f-be22-bffd8cf2ae6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129800437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.129800437
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.3617323879
Short name T337
Test name
Test status
Simulation time 73710081 ps
CPU time 1.09 seconds
Started Jun 28 06:02:58 PM PDT 24
Finished Jun 28 06:03:04 PM PDT 24
Peak memory 217488 kb
Host smart-bb3d4014-83d5-4c77-b2b3-7c9f50aeb624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617323879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3617323879
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.2480228582
Short name T825
Test name
Test status
Simulation time 33897361 ps
CPU time 1.36 seconds
Started Jun 28 06:03:09 PM PDT 24
Finished Jun 28 06:03:18 PM PDT 24
Peak memory 219668 kb
Host smart-c84a084a-b6e3-4845-bd03-940e92b0aa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480228582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.2480228582
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.697939611
Short name T626
Test name
Test status
Simulation time 17812068 ps
CPU time 1.09 seconds
Started Jun 28 06:03:04 PM PDT 24
Finished Jun 28 06:03:13 PM PDT 24
Peak memory 217532 kb
Host smart-dc885aff-3a77-4f27-88de-9b78270d84d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697939611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.697939611
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.1502764689
Short name T466
Test name
Test status
Simulation time 27638501 ps
CPU time 1.18 seconds
Started Jun 28 06:03:03 PM PDT 24
Finished Jun 28 06:03:11 PM PDT 24
Peak memory 218936 kb
Host smart-1224f571-205f-4b99-8ee2-36a40c3ce55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502764689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1502764689
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.3832063474
Short name T452
Test name
Test status
Simulation time 96453282 ps
CPU time 1.23 seconds
Started Jun 28 06:03:00 PM PDT 24
Finished Jun 28 06:03:07 PM PDT 24
Peak memory 219096 kb
Host smart-407f047e-778e-4985-9ae4-8e6608198cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832063474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3832063474
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2251696323
Short name T290
Test name
Test status
Simulation time 27343179 ps
CPU time 1.27 seconds
Started Jun 28 06:01:50 PM PDT 24
Finished Jun 28 06:01:57 PM PDT 24
Peak memory 219060 kb
Host smart-5d0d78b1-3137-40f6-8a52-46407d1b8db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251696323 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2251696323
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.4168808232
Short name T60
Test name
Test status
Simulation time 12366828 ps
CPU time 0.9 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:02:00 PM PDT 24
Peak memory 207244 kb
Host smart-e31176a3-857d-4e73-a1d8-62f4f9fff843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168808232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.4168808232
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.487885841
Short name T207
Test name
Test status
Simulation time 12467164 ps
CPU time 0.9 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:00 PM PDT 24
Peak memory 216832 kb
Host smart-6530ef1b-bf59-41bd-9ad6-712e8c13a050
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487885841 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.487885841
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3036299894
Short name T127
Test name
Test status
Simulation time 43175369 ps
CPU time 1.11 seconds
Started Jun 28 06:01:51 PM PDT 24
Finished Jun 28 06:01:59 PM PDT 24
Peak memory 217196 kb
Host smart-4a5852b0-2fcd-40a6-937e-362a493f5a54
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036299894 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3036299894
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.4111852391
Short name T999
Test name
Test status
Simulation time 35931901 ps
CPU time 0.98 seconds
Started Jun 28 06:01:48 PM PDT 24
Finished Jun 28 06:01:54 PM PDT 24
Peak memory 219940 kb
Host smart-45730fb0-8318-4ff6-b497-ce452d6e2493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111852391 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.4111852391
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3143425323
Short name T738
Test name
Test status
Simulation time 153533928 ps
CPU time 3.15 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:03 PM PDT 24
Peak memory 220612 kb
Host smart-795517b0-7500-4839-8f48-71c7cc78b1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143425323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3143425323
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3719614623
Short name T725
Test name
Test status
Simulation time 37059051 ps
CPU time 0.87 seconds
Started Jun 28 06:01:51 PM PDT 24
Finished Jun 28 06:01:57 PM PDT 24
Peak memory 215812 kb
Host smart-17631f8a-0e72-44ef-ab45-8221459ebeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719614623 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3719614623
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.3635506417
Short name T992
Test name
Test status
Simulation time 64227652 ps
CPU time 0.94 seconds
Started Jun 28 06:01:51 PM PDT 24
Finished Jun 28 06:01:59 PM PDT 24
Peak memory 207376 kb
Host smart-fad33101-a588-45ff-b50b-23cd341ef57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635506417 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3635506417
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2242732520
Short name T834
Test name
Test status
Simulation time 204684980 ps
CPU time 4.18 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:02:03 PM PDT 24
Peak memory 215620 kb
Host smart-520ec232-0c90-4e50-a74f-72de422fa42e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242732520 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2242732520
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1786792193
Short name T232
Test name
Test status
Simulation time 210663080303 ps
CPU time 1151.98 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:21:10 PM PDT 24
Peak memory 223312 kb
Host smart-d6587c00-5c5c-4d60-9e63-49e8aff1f1f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786792193 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1786792193
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.3965159296
Short name T592
Test name
Test status
Simulation time 24454142 ps
CPU time 1.26 seconds
Started Jun 28 06:03:03 PM PDT 24
Finished Jun 28 06:03:12 PM PDT 24
Peak memory 219848 kb
Host smart-d0e9967f-bd32-4c72-a2db-40329d585f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965159296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.3965159296
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.622364535
Short name T79
Test name
Test status
Simulation time 89073668 ps
CPU time 3.2 seconds
Started Jun 28 06:03:02 PM PDT 24
Finished Jun 28 06:03:11 PM PDT 24
Peak memory 220612 kb
Host smart-459d2422-f7e8-4426-9d80-abd3fb63b6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622364535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.622364535
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.191065828
Short name T315
Test name
Test status
Simulation time 101779133 ps
CPU time 1.17 seconds
Started Jun 28 06:03:11 PM PDT 24
Finished Jun 28 06:03:21 PM PDT 24
Peak memory 220000 kb
Host smart-875bb123-bf98-4863-bea1-e7d76def272b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191065828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.191065828
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.1837231422
Short name T776
Test name
Test status
Simulation time 14504942911 ps
CPU time 169.28 seconds
Started Jun 28 06:02:58 PM PDT 24
Finished Jun 28 06:05:52 PM PDT 24
Peak memory 217920 kb
Host smart-83025cab-8c37-4f1e-a19d-995dfee4a09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837231422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1837231422
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.65244370
Short name T895
Test name
Test status
Simulation time 203197315 ps
CPU time 1.18 seconds
Started Jun 28 06:03:02 PM PDT 24
Finished Jun 28 06:03:10 PM PDT 24
Peak memory 219348 kb
Host smart-3485e856-54c2-4eec-8c25-d748a8426f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65244370 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.65244370
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.3376342241
Short name T51
Test name
Test status
Simulation time 71906487 ps
CPU time 1.37 seconds
Started Jun 28 06:03:04 PM PDT 24
Finished Jun 28 06:03:13 PM PDT 24
Peak memory 217384 kb
Host smart-bf7b768c-1108-42ac-aae3-e62bd4f15c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376342241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3376342241
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.898589740
Short name T377
Test name
Test status
Simulation time 130902138 ps
CPU time 1.17 seconds
Started Jun 28 06:03:07 PM PDT 24
Finished Jun 28 06:03:16 PM PDT 24
Peak memory 220040 kb
Host smart-95e2be6f-f34d-4698-b814-7703d9d70725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898589740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.898589740
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.3697034169
Short name T700
Test name
Test status
Simulation time 52103898 ps
CPU time 1.23 seconds
Started Jun 28 06:03:10 PM PDT 24
Finished Jun 28 06:03:20 PM PDT 24
Peak memory 217364 kb
Host smart-c9046c72-312c-4abb-b52b-ce1ceaf15941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697034169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3697034169
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.644452150
Short name T252
Test name
Test status
Simulation time 461446169 ps
CPU time 1.29 seconds
Started Jun 28 06:03:06 PM PDT 24
Finished Jun 28 06:03:15 PM PDT 24
Peak memory 221420 kb
Host smart-f5961fee-5864-4659-af3b-ac91fa44026b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644452150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.644452150
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.1179043454
Short name T906
Test name
Test status
Simulation time 34667765 ps
CPU time 1.35 seconds
Started Jun 28 06:03:08 PM PDT 24
Finished Jun 28 06:03:18 PM PDT 24
Peak memory 217676 kb
Host smart-112d6960-65e7-46ba-a6a5-ccaefb9771d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179043454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1179043454
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.2179389435
Short name T822
Test name
Test status
Simulation time 30811945 ps
CPU time 1.33 seconds
Started Jun 28 06:03:07 PM PDT 24
Finished Jun 28 06:03:16 PM PDT 24
Peak memory 216200 kb
Host smart-78242e93-7925-4a3a-93c6-60746a0f1b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179389435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.2179389435
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.2977859146
Short name T911
Test name
Test status
Simulation time 39174394 ps
CPU time 1.66 seconds
Started Jun 28 06:03:04 PM PDT 24
Finished Jun 28 06:03:13 PM PDT 24
Peak memory 217756 kb
Host smart-a545505f-9e20-46f9-bf52-8921a34f1a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977859146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2977859146
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.1854965784
Short name T372
Test name
Test status
Simulation time 247380986 ps
CPU time 3.66 seconds
Started Jun 28 06:03:06 PM PDT 24
Finished Jun 28 06:03:17 PM PDT 24
Peak memory 219088 kb
Host smart-5cbbb95f-3213-4229-9e82-08ca003047b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854965784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1854965784
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.619495964
Short name T602
Test name
Test status
Simulation time 46966941 ps
CPU time 1.23 seconds
Started Jun 28 06:03:07 PM PDT 24
Finished Jun 28 06:03:16 PM PDT 24
Peak memory 219180 kb
Host smart-0bdb4858-4235-4083-966d-a326c3354e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619495964 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.619495964
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.260459018
Short name T742
Test name
Test status
Simulation time 319485964 ps
CPU time 4.01 seconds
Started Jun 28 06:03:02 PM PDT 24
Finished Jun 28 06:03:13 PM PDT 24
Peak memory 219224 kb
Host smart-63b149b4-cd13-4135-abe9-1f70b19f8992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260459018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.260459018
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.245900248
Short name T866
Test name
Test status
Simulation time 74529306 ps
CPU time 1.13 seconds
Started Jun 28 06:03:07 PM PDT 24
Finished Jun 28 06:03:17 PM PDT 24
Peak memory 219072 kb
Host smart-3d96e12f-d8ab-4083-96cb-1c630430be1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245900248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.245900248
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.2727673755
Short name T836
Test name
Test status
Simulation time 73014785 ps
CPU time 1.22 seconds
Started Jun 28 06:03:02 PM PDT 24
Finished Jun 28 06:03:10 PM PDT 24
Peak memory 219160 kb
Host smart-6e219c4c-3658-4784-9470-1434a811dcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727673755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2727673755
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2007804317
Short name T932
Test name
Test status
Simulation time 27749823 ps
CPU time 1.22 seconds
Started Jun 28 06:01:56 PM PDT 24
Finished Jun 28 06:02:06 PM PDT 24
Peak memory 215992 kb
Host smart-a74268fd-3233-4bd4-9180-501cbc063cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007804317 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2007804317
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.1017314298
Short name T759
Test name
Test status
Simulation time 18347587 ps
CPU time 0.98 seconds
Started Jun 28 06:01:50 PM PDT 24
Finished Jun 28 06:01:56 PM PDT 24
Peak memory 207232 kb
Host smart-a17cb51d-1027-4cff-9007-73a5d94550ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017314298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1017314298
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2011858425
Short name T66
Test name
Test status
Simulation time 85206599 ps
CPU time 1.09 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:01 PM PDT 24
Peak memory 217088 kb
Host smart-7312f217-9ed9-4ba0-aa2f-bfdb93fec20b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011858425 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2011858425
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2030246568
Short name T170
Test name
Test status
Simulation time 18385176 ps
CPU time 1.02 seconds
Started Jun 28 06:01:51 PM PDT 24
Finished Jun 28 06:01:58 PM PDT 24
Peak memory 218808 kb
Host smart-33cfea8d-d832-4bd2-840e-a2c8628abac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030246568 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2030246568
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2881427878
Short name T444
Test name
Test status
Simulation time 78536031 ps
CPU time 1.41 seconds
Started Jun 28 06:01:50 PM PDT 24
Finished Jun 28 06:01:57 PM PDT 24
Peak memory 218700 kb
Host smart-1f21025a-9a49-4fcd-83d9-e3e583dbee68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881427878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2881427878
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3565467633
Short name T837
Test name
Test status
Simulation time 22188200 ps
CPU time 1.09 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:02:00 PM PDT 24
Peak memory 215820 kb
Host smart-4892e301-411d-409b-8010-aaa9237ca3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565467633 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3565467633
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2940214123
Short name T402
Test name
Test status
Simulation time 142184336 ps
CPU time 0.88 seconds
Started Jun 28 06:01:50 PM PDT 24
Finished Jun 28 06:01:57 PM PDT 24
Peak memory 215380 kb
Host smart-350f86fb-c180-4365-9cba-43d0b4144e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940214123 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2940214123
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2980133320
Short name T560
Test name
Test status
Simulation time 32537509 ps
CPU time 1.33 seconds
Started Jun 28 06:01:49 PM PDT 24
Finished Jun 28 06:01:55 PM PDT 24
Peak memory 207488 kb
Host smart-db53a882-2537-42d8-9d9e-dc4351a2ec6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980133320 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2980133320
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3611747509
Short name T426
Test name
Test status
Simulation time 39756180425 ps
CPU time 512.34 seconds
Started Jun 28 06:01:47 PM PDT 24
Finished Jun 28 06:10:24 PM PDT 24
Peak memory 224004 kb
Host smart-4b8001f5-5bd6-45e4-bcfc-7506d38ccacf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611747509 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3611747509
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.3415043649
Short name T655
Test name
Test status
Simulation time 85032180 ps
CPU time 1.19 seconds
Started Jun 28 06:03:06 PM PDT 24
Finished Jun 28 06:03:15 PM PDT 24
Peak memory 216192 kb
Host smart-6b8d8e01-ad73-4aed-a4d6-0f2d29a331dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415043649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.3415043649
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.248136954
Short name T957
Test name
Test status
Simulation time 57084816 ps
CPU time 1.45 seconds
Started Jun 28 06:03:00 PM PDT 24
Finished Jun 28 06:03:07 PM PDT 24
Peak memory 218924 kb
Host smart-8ebb0aa6-773c-4ac7-9e2d-bd5c9db26630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248136954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.248136954
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.3690406065
Short name T291
Test name
Test status
Simulation time 95244172 ps
CPU time 1.22 seconds
Started Jun 28 06:03:07 PM PDT 24
Finished Jun 28 06:03:16 PM PDT 24
Peak memory 221236 kb
Host smart-339d0af9-4566-484e-8012-8970fd13756c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690406065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.3690406065
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.2466255900
Short name T724
Test name
Test status
Simulation time 249673906 ps
CPU time 3.47 seconds
Started Jun 28 06:03:01 PM PDT 24
Finished Jun 28 06:03:11 PM PDT 24
Peak memory 220048 kb
Host smart-7969d26e-473b-4772-91ba-612767925fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466255900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2466255900
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.2770559386
Short name T498
Test name
Test status
Simulation time 52115362 ps
CPU time 1.19 seconds
Started Jun 28 06:03:15 PM PDT 24
Finished Jun 28 06:03:24 PM PDT 24
Peak memory 220556 kb
Host smart-7beb51e6-855c-48c0-95bc-58027887c1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770559386 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.2770559386
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.2028365153
Short name T821
Test name
Test status
Simulation time 252234473 ps
CPU time 1.16 seconds
Started Jun 28 06:03:11 PM PDT 24
Finished Jun 28 06:03:20 PM PDT 24
Peak memory 217656 kb
Host smart-5d7a1f34-55a9-4b33-9356-01b2f17db9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028365153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2028365153
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.550518405
Short name T774
Test name
Test status
Simulation time 26018954 ps
CPU time 1.19 seconds
Started Jun 28 06:03:22 PM PDT 24
Finished Jun 28 06:03:30 PM PDT 24
Peak memory 220044 kb
Host smart-e9084b5c-adcb-4388-b131-842ecaa2f738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550518405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.550518405
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.1235233639
Short name T679
Test name
Test status
Simulation time 137290606 ps
CPU time 1.59 seconds
Started Jun 28 06:03:22 PM PDT 24
Finished Jun 28 06:03:30 PM PDT 24
Peak memory 218924 kb
Host smart-8f0cd9b1-62c9-44af-afc3-a27c88fcdc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235233639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1235233639
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.2153666423
Short name T185
Test name
Test status
Simulation time 92692743 ps
CPU time 1.26 seconds
Started Jun 28 06:03:14 PM PDT 24
Finished Jun 28 06:03:24 PM PDT 24
Peak memory 219868 kb
Host smart-93ed5d6e-86d6-4997-8691-a0c19e1ff162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153666423 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.2153666423
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/135.edn_alert.2248739031
Short name T154
Test name
Test status
Simulation time 29148487 ps
CPU time 1.25 seconds
Started Jun 28 06:03:09 PM PDT 24
Finished Jun 28 06:03:19 PM PDT 24
Peak memory 221100 kb
Host smart-a843b492-cbdf-4a75-ac5a-4798adb5bce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248739031 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.2248739031
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.3999449812
Short name T752
Test name
Test status
Simulation time 163109249 ps
CPU time 1.21 seconds
Started Jun 28 06:03:14 PM PDT 24
Finished Jun 28 06:03:24 PM PDT 24
Peak memory 217644 kb
Host smart-5d49bf6d-fec0-4334-aa15-93a710e168f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999449812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3999449812
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.281839053
Short name T137
Test name
Test status
Simulation time 43976467 ps
CPU time 1.21 seconds
Started Jun 28 06:03:15 PM PDT 24
Finished Jun 28 06:03:25 PM PDT 24
Peak memory 219452 kb
Host smart-aa6f9b7f-0ed6-4cfe-98e1-7d49685141a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281839053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.281839053
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.2385401691
Short name T381
Test name
Test status
Simulation time 130722848 ps
CPU time 1.1 seconds
Started Jun 28 06:03:17 PM PDT 24
Finished Jun 28 06:03:27 PM PDT 24
Peak memory 217604 kb
Host smart-4d1d0b89-9f2b-4be7-8b32-24f7c2e2ec1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385401691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2385401691
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.2028531855
Short name T636
Test name
Test status
Simulation time 77105461 ps
CPU time 1.12 seconds
Started Jun 28 06:03:16 PM PDT 24
Finished Jun 28 06:03:25 PM PDT 24
Peak memory 218936 kb
Host smart-9ab705ee-3306-4ed6-a82f-d5db6a77c6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028531855 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.2028531855
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.3569459184
Short name T713
Test name
Test status
Simulation time 37408068 ps
CPU time 1.32 seconds
Started Jun 28 06:03:10 PM PDT 24
Finished Jun 28 06:03:20 PM PDT 24
Peak memory 219044 kb
Host smart-b612b013-49a0-40f9-860f-ca8d02c19463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569459184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3569459184
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.1007570516
Short name T49
Test name
Test status
Simulation time 100985819 ps
CPU time 1.09 seconds
Started Jun 28 06:03:14 PM PDT 24
Finished Jun 28 06:03:24 PM PDT 24
Peak memory 220520 kb
Host smart-366eb7cd-0aac-42c9-8153-498759640f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007570516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.1007570516
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.3745652034
Short name T775
Test name
Test status
Simulation time 129927449 ps
CPU time 1.04 seconds
Started Jun 28 06:03:16 PM PDT 24
Finished Jun 28 06:03:26 PM PDT 24
Peak memory 217748 kb
Host smart-15c29445-7ae5-4e09-aefa-31a8a64c2892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745652034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3745652034
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.3551178142
Short name T828
Test name
Test status
Simulation time 62785822 ps
CPU time 1.02 seconds
Started Jun 28 06:03:14 PM PDT 24
Finished Jun 28 06:03:24 PM PDT 24
Peak memory 220092 kb
Host smart-fc2472a3-36b0-4dd2-b447-b20186271a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551178142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.3551178142
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.1084933620
Short name T70
Test name
Test status
Simulation time 126472706 ps
CPU time 2.77 seconds
Started Jun 28 06:03:11 PM PDT 24
Finished Jun 28 06:03:22 PM PDT 24
Peak memory 218896 kb
Host smart-52e20c4b-a803-48c2-af97-4ec9dbbe1950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084933620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1084933620
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1744280210
Short name T496
Test name
Test status
Simulation time 45870401 ps
CPU time 1.27 seconds
Started Jun 28 06:01:48 PM PDT 24
Finished Jun 28 06:01:53 PM PDT 24
Peak memory 219828 kb
Host smart-a6539c0d-c36a-4862-94cf-65a14fc75102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744280210 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1744280210
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3103716558
Short name T659
Test name
Test status
Simulation time 41111326 ps
CPU time 0.86 seconds
Started Jun 28 06:01:54 PM PDT 24
Finished Jun 28 06:02:04 PM PDT 24
Peak memory 206992 kb
Host smart-ff6a32e9-e1b7-4611-8fd3-3f0812b8caec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103716558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3103716558
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.461168105
Short name T171
Test name
Test status
Simulation time 33117778 ps
CPU time 0.85 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:02 PM PDT 24
Peak memory 216556 kb
Host smart-1f8b5899-d253-464c-9c5e-9e53d4cf7030
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461168105 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.461168105
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.57516384
Short name T202
Test name
Test status
Simulation time 70537766 ps
CPU time 1.05 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:03 PM PDT 24
Peak memory 218652 kb
Host smart-058fa1e5-cf3f-4970-b20d-62c4bb26ba8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57516384 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_dis
able_auto_req_mode.57516384
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2986926778
Short name T968
Test name
Test status
Simulation time 136096816 ps
CPU time 1.21 seconds
Started Jun 28 06:01:48 PM PDT 24
Finished Jun 28 06:01:53 PM PDT 24
Peak memory 224368 kb
Host smart-9b9f82c7-f32f-4b37-86aa-690ca173e044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986926778 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2986926778
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1747133398
Short name T261
Test name
Test status
Simulation time 60181061 ps
CPU time 1.26 seconds
Started Jun 28 06:01:55 PM PDT 24
Finished Jun 28 06:02:05 PM PDT 24
Peak memory 218888 kb
Host smart-87f4b407-dad2-4ce9-8eba-601da0f649b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747133398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1747133398
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1655324911
Short name T519
Test name
Test status
Simulation time 24807585 ps
CPU time 1.03 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:02:00 PM PDT 24
Peak memory 215820 kb
Host smart-6a9750b5-520c-4b8a-856b-442159996b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655324911 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1655324911
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.533740678
Short name T528
Test name
Test status
Simulation time 108347493 ps
CPU time 0.92 seconds
Started Jun 28 06:01:49 PM PDT 24
Finished Jun 28 06:01:54 PM PDT 24
Peak memory 215692 kb
Host smart-fccd7eef-ebdf-4fab-a7af-0f29f993f066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533740678 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.533740678
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3324809852
Short name T401
Test name
Test status
Simulation time 634747082 ps
CPU time 3.98 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:04 PM PDT 24
Peak memory 215584 kb
Host smart-404157e6-4145-4e10-bf65-2926033be3d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324809852 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3324809852
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.4115434016
Short name T237
Test name
Test status
Simulation time 305124103123 ps
CPU time 1320.21 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:23:59 PM PDT 24
Peak memory 224060 kb
Host smart-31a90902-7942-4830-9324-b9c25881cc36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115434016 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.4115434016
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.1928921516
Short name T296
Test name
Test status
Simulation time 26167428 ps
CPU time 1.18 seconds
Started Jun 28 06:03:11 PM PDT 24
Finished Jun 28 06:03:21 PM PDT 24
Peak memory 216012 kb
Host smart-5a620b62-f855-4acc-8753-41d30d14d105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928921516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.1928921516
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.2816174296
Short name T642
Test name
Test status
Simulation time 97507173 ps
CPU time 1.27 seconds
Started Jun 28 06:03:22 PM PDT 24
Finished Jun 28 06:03:30 PM PDT 24
Peak memory 220516 kb
Host smart-a6edb3f4-6f3b-4781-938f-57d71333dd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816174296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2816174296
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.4269449875
Short name T93
Test name
Test status
Simulation time 45879870 ps
CPU time 1.26 seconds
Started Jun 28 06:03:13 PM PDT 24
Finished Jun 28 06:03:23 PM PDT 24
Peak memory 215620 kb
Host smart-c760781d-81ab-440d-b67f-a21c04fae0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269449875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.4269449875
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.1963387753
Short name T668
Test name
Test status
Simulation time 41132288 ps
CPU time 1.15 seconds
Started Jun 28 06:03:12 PM PDT 24
Finished Jun 28 06:03:22 PM PDT 24
Peak memory 218908 kb
Host smart-59b7fd2b-66d9-4a54-abfb-0df270a5d620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963387753 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.1963387753
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/143.edn_alert.32127168
Short name T545
Test name
Test status
Simulation time 45276108 ps
CPU time 1.3 seconds
Started Jun 28 06:03:10 PM PDT 24
Finished Jun 28 06:03:19 PM PDT 24
Peak memory 220044 kb
Host smart-9d4de9bf-b285-40a3-b619-1ff345e4d313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32127168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.32127168
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/144.edn_alert.4056520340
Short name T77
Test name
Test status
Simulation time 79001014 ps
CPU time 1.16 seconds
Started Jun 28 06:03:15 PM PDT 24
Finished Jun 28 06:03:25 PM PDT 24
Peak memory 218644 kb
Host smart-195b5012-0721-4cfa-8ad2-d0334341ed94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056520340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.4056520340
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.2655963621
Short name T47
Test name
Test status
Simulation time 35341669 ps
CPU time 1.32 seconds
Started Jun 28 06:03:22 PM PDT 24
Finished Jun 28 06:03:30 PM PDT 24
Peak memory 217588 kb
Host smart-b5bdc01a-c3d0-4a22-9744-4462111a4861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655963621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2655963621
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.973438720
Short name T612
Test name
Test status
Simulation time 222260391 ps
CPU time 1.45 seconds
Started Jun 28 06:03:16 PM PDT 24
Finished Jun 28 06:03:26 PM PDT 24
Peak memory 219832 kb
Host smart-f3f722ee-1f48-4562-93ca-a51d7a8b3c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973438720 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.973438720
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.1632928596
Short name T358
Test name
Test status
Simulation time 109472008 ps
CPU time 1.21 seconds
Started Jun 28 06:03:10 PM PDT 24
Finished Jun 28 06:03:20 PM PDT 24
Peak memory 218908 kb
Host smart-7ea68d82-a21c-49a7-8fbe-0016512d4deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632928596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1632928596
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.78663764
Short name T704
Test name
Test status
Simulation time 36939696 ps
CPU time 1.19 seconds
Started Jun 28 06:03:11 PM PDT 24
Finished Jun 28 06:03:21 PM PDT 24
Peak memory 220180 kb
Host smart-a5fe8887-b630-411a-88d8-f5c100378693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78663764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.78663764
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3080469902
Short name T949
Test name
Test status
Simulation time 39767166 ps
CPU time 1.69 seconds
Started Jun 28 06:03:19 PM PDT 24
Finished Jun 28 06:03:28 PM PDT 24
Peak memory 218800 kb
Host smart-d668c3bb-fd2b-4046-9bbf-2b57df4a49a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080469902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3080469902
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.1722702099
Short name T192
Test name
Test status
Simulation time 49175544 ps
CPU time 1.24 seconds
Started Jun 28 06:03:11 PM PDT 24
Finished Jun 28 06:03:21 PM PDT 24
Peak memory 221252 kb
Host smart-bdd932c1-516a-4aa2-81af-52cf5ac02a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722702099 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.1722702099
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.4273818349
Short name T538
Test name
Test status
Simulation time 35786536 ps
CPU time 1.38 seconds
Started Jun 28 06:03:13 PM PDT 24
Finished Jun 28 06:03:23 PM PDT 24
Peak memory 220312 kb
Host smart-4be69cb7-09ed-4a29-b28b-bf4f9052dd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273818349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.4273818349
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.3273585093
Short name T678
Test name
Test status
Simulation time 23051063 ps
CPU time 1.16 seconds
Started Jun 28 06:03:22 PM PDT 24
Finished Jun 28 06:03:30 PM PDT 24
Peak memory 215924 kb
Host smart-07b326f1-55c0-4057-9476-5588bce682fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273585093 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.3273585093
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert.1433332082
Short name T321
Test name
Test status
Simulation time 26414066 ps
CPU time 1.28 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:01 PM PDT 24
Peak memory 219772 kb
Host smart-663a9e35-3fbf-4f74-88e1-8b93921f0697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433332082 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1433332082
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1937807606
Short name T897
Test name
Test status
Simulation time 25508980 ps
CPU time 0.84 seconds
Started Jun 28 06:01:51 PM PDT 24
Finished Jun 28 06:01:58 PM PDT 24
Peak memory 207040 kb
Host smart-5191e8ad-2ddb-40a5-aa1c-758128c2d73b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937807606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1937807606
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2020550258
Short name T735
Test name
Test status
Simulation time 23234616 ps
CPU time 0.87 seconds
Started Jun 28 06:01:48 PM PDT 24
Finished Jun 28 06:01:53 PM PDT 24
Peak memory 215688 kb
Host smart-98090412-4994-4d21-a310-90a972a92bbf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020550258 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2020550258
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1805280240
Short name T708
Test name
Test status
Simulation time 29028253 ps
CPU time 1.14 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:02 PM PDT 24
Peak memory 217384 kb
Host smart-fbc8b07a-c8f7-4ab7-94b2-546da3a83536
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805280240 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1805280240
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.3052786003
Short name T734
Test name
Test status
Simulation time 22548509 ps
CPU time 1.04 seconds
Started Jun 28 06:01:48 PM PDT 24
Finished Jun 28 06:01:54 PM PDT 24
Peak memory 219944 kb
Host smart-b1a0bbff-d823-4b41-8dbd-e3673f342d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052786003 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3052786003
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1985717503
Short name T971
Test name
Test status
Simulation time 61500627 ps
CPU time 1.1 seconds
Started Jun 28 06:01:50 PM PDT 24
Finished Jun 28 06:01:57 PM PDT 24
Peak memory 217744 kb
Host smart-85f29af1-d0ca-4834-aa9e-7835ee5df9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985717503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1985717503
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.210761421
Short name T361
Test name
Test status
Simulation time 22425325 ps
CPU time 1.15 seconds
Started Jun 28 06:01:51 PM PDT 24
Finished Jun 28 06:01:57 PM PDT 24
Peak memory 215656 kb
Host smart-39536ed8-5291-4aae-8937-903b20bf4bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210761421 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.210761421
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3134191760
Short name T729
Test name
Test status
Simulation time 41601105 ps
CPU time 0.92 seconds
Started Jun 28 06:01:47 PM PDT 24
Finished Jun 28 06:01:52 PM PDT 24
Peak memory 215600 kb
Host smart-e8afd43b-9706-471f-ae2b-d946a5c2f1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134191760 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3134191760
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3519853724
Short name T399
Test name
Test status
Simulation time 320804217 ps
CPU time 2.26 seconds
Started Jun 28 06:01:50 PM PDT 24
Finished Jun 28 06:01:58 PM PDT 24
Peak memory 217592 kb
Host smart-91a03c09-bc04-4811-8ce7-a034579c9392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519853724 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3519853724
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1318885150
Short name T233
Test name
Test status
Simulation time 232924961953 ps
CPU time 1485.31 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:26:45 PM PDT 24
Peak memory 223976 kb
Host smart-5712df78-4847-418a-85b8-17bbb2a9bdb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318885150 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1318885150
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.4285443048
Short name T753
Test name
Test status
Simulation time 51256834 ps
CPU time 1.24 seconds
Started Jun 28 06:03:16 PM PDT 24
Finished Jun 28 06:03:25 PM PDT 24
Peak memory 219016 kb
Host smart-33aa5c8d-a2f6-4dc8-ad91-32e095ad26c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285443048 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.4285443048
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.1459976762
Short name T649
Test name
Test status
Simulation time 54108783 ps
CPU time 1.27 seconds
Started Jun 28 06:03:15 PM PDT 24
Finished Jun 28 06:03:24 PM PDT 24
Peak memory 218840 kb
Host smart-3833d4a5-afc1-405d-ae27-a7c5730b6587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459976762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1459976762
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.2037725546
Short name T703
Test name
Test status
Simulation time 60738505 ps
CPU time 1.23 seconds
Started Jun 28 06:03:16 PM PDT 24
Finished Jun 28 06:03:25 PM PDT 24
Peak memory 218832 kb
Host smart-c035d38b-231c-4233-ab16-0370d458c610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037725546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.2037725546
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.2157117498
Short name T880
Test name
Test status
Simulation time 47822550 ps
CPU time 1.8 seconds
Started Jun 28 06:03:16 PM PDT 24
Finished Jun 28 06:03:27 PM PDT 24
Peak memory 218752 kb
Host smart-78bfaf91-6b50-4139-a16a-f491d3d32a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157117498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2157117498
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.82452730
Short name T925
Test name
Test status
Simulation time 45262895 ps
CPU time 1.13 seconds
Started Jun 28 06:03:12 PM PDT 24
Finished Jun 28 06:03:22 PM PDT 24
Peak memory 218652 kb
Host smart-cfdabc26-71e6-4937-b926-a5224d04070c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82452730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.82452730
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.4026890417
Short name T39
Test name
Test status
Simulation time 177681924 ps
CPU time 1.24 seconds
Started Jun 28 06:03:22 PM PDT 24
Finished Jun 28 06:03:30 PM PDT 24
Peak memory 217464 kb
Host smart-dba635bb-aba3-49e1-950d-ccfb41a55bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026890417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.4026890417
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.660152829
Short name T835
Test name
Test status
Simulation time 88900498 ps
CPU time 1.18 seconds
Started Jun 28 06:03:15 PM PDT 24
Finished Jun 28 06:03:25 PM PDT 24
Peak memory 218916 kb
Host smart-83fdbc08-f3e3-4f87-9f46-5e843aca19d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660152829 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.660152829
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.372521867
Short name T634
Test name
Test status
Simulation time 41112869 ps
CPU time 1.65 seconds
Started Jun 28 06:03:16 PM PDT 24
Finished Jun 28 06:03:26 PM PDT 24
Peak memory 218864 kb
Host smart-1d5bae8f-0ce5-46aa-b051-fa3b1c96fe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372521867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.372521867
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.249557665
Short name T629
Test name
Test status
Simulation time 27125692 ps
CPU time 1.22 seconds
Started Jun 28 06:03:16 PM PDT 24
Finished Jun 28 06:03:26 PM PDT 24
Peak memory 219176 kb
Host smart-23ca3bed-3048-4348-ae2f-da2870f3cc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249557665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.249557665
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.2837629510
Short name T804
Test name
Test status
Simulation time 46767767 ps
CPU time 1.86 seconds
Started Jun 28 06:03:16 PM PDT 24
Finished Jun 28 06:03:27 PM PDT 24
Peak memory 218912 kb
Host smart-585a1935-aa25-47ec-b52b-0cdd108446a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837629510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2837629510
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.1938639021
Short name T318
Test name
Test status
Simulation time 38403402 ps
CPU time 1.1 seconds
Started Jun 28 06:03:16 PM PDT 24
Finished Jun 28 06:03:25 PM PDT 24
Peak memory 215932 kb
Host smart-44234ae4-560b-4840-ac1f-52c11b6f51cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938639021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.1938639021
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.2961505104
Short name T411
Test name
Test status
Simulation time 47148751 ps
CPU time 1.68 seconds
Started Jun 28 06:03:16 PM PDT 24
Finished Jun 28 06:03:27 PM PDT 24
Peak memory 218764 kb
Host smart-ec1f8bd8-4cc6-4a8b-8d1a-29e0283c2a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961505104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2961505104
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.3841471786
Short name T628
Test name
Test status
Simulation time 39053541 ps
CPU time 1.1 seconds
Started Jun 28 06:03:17 PM PDT 24
Finished Jun 28 06:03:27 PM PDT 24
Peak memory 219068 kb
Host smart-2dafc823-ad2e-4da6-8cf0-229e5a3beb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841471786 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.3841471786
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.3326442247
Short name T838
Test name
Test status
Simulation time 77863485 ps
CPU time 1.13 seconds
Started Jun 28 06:03:18 PM PDT 24
Finished Jun 28 06:03:27 PM PDT 24
Peak memory 219912 kb
Host smart-32f52126-15ff-45bb-b217-29b58da3e9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326442247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3326442247
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.3837574617
Short name T539
Test name
Test status
Simulation time 66084993 ps
CPU time 1.1 seconds
Started Jun 28 06:03:15 PM PDT 24
Finished Jun 28 06:03:24 PM PDT 24
Peak memory 218672 kb
Host smart-d36305e0-d183-46b9-98f9-878d98ac09b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837574617 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.3837574617
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.135064231
Short name T37
Test name
Test status
Simulation time 68498087 ps
CPU time 1.36 seconds
Started Jun 28 06:03:16 PM PDT 24
Finished Jun 28 06:03:26 PM PDT 24
Peak memory 219824 kb
Host smart-8ff38afa-92a3-417f-ad75-339005b66552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135064231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.135064231
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.3920998933
Short name T438
Test name
Test status
Simulation time 44855174 ps
CPU time 1.24 seconds
Started Jun 28 06:03:18 PM PDT 24
Finished Jun 28 06:03:27 PM PDT 24
Peak memory 219744 kb
Host smart-aee74471-0fd3-4d7b-b0fa-e335d66392b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920998933 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.3920998933
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.216513182
Short name T840
Test name
Test status
Simulation time 70244036 ps
CPU time 1.12 seconds
Started Jun 28 06:03:14 PM PDT 24
Finished Jun 28 06:03:23 PM PDT 24
Peak memory 217708 kb
Host smart-970904fd-8c02-4686-a4fb-037b804dad98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216513182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.216513182
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.3662131695
Short name T677
Test name
Test status
Simulation time 43270606 ps
CPU time 1.2 seconds
Started Jun 28 06:03:27 PM PDT 24
Finished Jun 28 06:03:34 PM PDT 24
Peak memory 219520 kb
Host smart-ab49c556-f218-42f7-b2e7-7a0f43a59b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662131695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.3662131695
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.2361771258
Short name T573
Test name
Test status
Simulation time 52184144 ps
CPU time 1.43 seconds
Started Jun 28 06:03:13 PM PDT 24
Finished Jun 28 06:03:23 PM PDT 24
Peak memory 218964 kb
Host smart-0b73fc6d-e08d-47fe-a362-edd7874f6150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361771258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2361771258
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1442757986
Short name T616
Test name
Test status
Simulation time 151716235 ps
CPU time 1.12 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:01:59 PM PDT 24
Peak memory 219892 kb
Host smart-d0b25629-92ad-418a-b62e-6ede653341b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442757986 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1442757986
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2138753031
Short name T624
Test name
Test status
Simulation time 60687980 ps
CPU time 0.96 seconds
Started Jun 28 06:01:54 PM PDT 24
Finished Jun 28 06:02:04 PM PDT 24
Peak memory 215468 kb
Host smart-1341b902-ca6a-4d94-b915-bf732b83041d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138753031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2138753031
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.502902456
Short name T407
Test name
Test status
Simulation time 35573054 ps
CPU time 0.85 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:02 PM PDT 24
Peak memory 216744 kb
Host smart-75a35c6a-5877-4266-928f-2fcab07c6c76
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502902456 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.502902456
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1990371201
Short name T375
Test name
Test status
Simulation time 118767233 ps
CPU time 1.3 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:02:01 PM PDT 24
Peak memory 218668 kb
Host smart-8ce80c3b-39ac-4672-9a3c-cdc4886ed102
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990371201 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1990371201
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_genbits.1307800948
Short name T298
Test name
Test status
Simulation time 77554924 ps
CPU time 1.53 seconds
Started Jun 28 06:01:55 PM PDT 24
Finished Jun 28 06:02:05 PM PDT 24
Peak memory 219072 kb
Host smart-c953c9f6-906f-42f6-b128-eee3bd994d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307800948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1307800948
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.528766167
Short name T751
Test name
Test status
Simulation time 26192310 ps
CPU time 1.29 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:03 PM PDT 24
Peak memory 224352 kb
Host smart-292beb95-325a-49e5-9361-4491ab2216af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528766167 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.528766167
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1948427801
Short name T423
Test name
Test status
Simulation time 60820106 ps
CPU time 0.94 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:01 PM PDT 24
Peak memory 215600 kb
Host smart-b810e8ef-90d8-4165-a738-55cb8a2cff5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948427801 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1948427801
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.434347595
Short name T662
Test name
Test status
Simulation time 1896745873 ps
CPU time 4.25 seconds
Started Jun 28 06:01:50 PM PDT 24
Finished Jun 28 06:02:00 PM PDT 24
Peak memory 215580 kb
Host smart-7d494d30-4eca-4e1b-8b58-0dfd9773dc9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434347595 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.434347595
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1512774130
Short name T542
Test name
Test status
Simulation time 19811051818 ps
CPU time 505.85 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:10:26 PM PDT 24
Peak memory 218632 kb
Host smart-184232d1-7bc6-4525-a6e7-3b4cfe5caf21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512774130 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1512774130
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.761068025
Short name T917
Test name
Test status
Simulation time 89765804 ps
CPU time 1.23 seconds
Started Jun 28 06:03:27 PM PDT 24
Finished Jun 28 06:03:34 PM PDT 24
Peak memory 219196 kb
Host smart-000829e4-736f-4887-9779-42491caf1503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761068025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.761068025
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1181865571
Short name T457
Test name
Test status
Simulation time 40003769 ps
CPU time 1.55 seconds
Started Jun 28 06:03:18 PM PDT 24
Finished Jun 28 06:03:28 PM PDT 24
Peak memory 219028 kb
Host smart-efd17b4d-3270-4ba9-8ca6-97c95a60523e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181865571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1181865571
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.850733042
Short name T710
Test name
Test status
Simulation time 53263266 ps
CPU time 1.13 seconds
Started Jun 28 06:03:18 PM PDT 24
Finished Jun 28 06:03:27 PM PDT 24
Peak memory 218956 kb
Host smart-49393586-9a1b-443f-8cfe-b82d0c9911c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850733042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.850733042
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.1731898864
Short name T780
Test name
Test status
Simulation time 86489461 ps
CPU time 1.21 seconds
Started Jun 28 06:03:21 PM PDT 24
Finished Jun 28 06:03:30 PM PDT 24
Peak memory 218828 kb
Host smart-7b64dd52-a505-4c8e-ad1d-1e40e6b29cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731898864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1731898864
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.687248434
Short name T586
Test name
Test status
Simulation time 70939023 ps
CPU time 1.24 seconds
Started Jun 28 06:03:25 PM PDT 24
Finished Jun 28 06:03:32 PM PDT 24
Peak memory 220164 kb
Host smart-e2810176-b1d8-425a-804d-f6f5c2e743cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687248434 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.687248434
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/163.edn_alert.2958910194
Short name T937
Test name
Test status
Simulation time 171961156 ps
CPU time 1.24 seconds
Started Jun 28 06:03:25 PM PDT 24
Finished Jun 28 06:03:32 PM PDT 24
Peak memory 220508 kb
Host smart-7a16ada1-f0be-4286-8185-f18e2cd2e90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958910194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.2958910194
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/164.edn_alert.861819966
Short name T633
Test name
Test status
Simulation time 44181618 ps
CPU time 1.2 seconds
Started Jun 28 06:03:17 PM PDT 24
Finished Jun 28 06:03:27 PM PDT 24
Peak memory 219036 kb
Host smart-32676c0c-9574-45f9-aaa0-7d76b47a6f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861819966 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.861819966
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.1828070824
Short name T797
Test name
Test status
Simulation time 239869774 ps
CPU time 1.38 seconds
Started Jun 28 06:03:17 PM PDT 24
Finished Jun 28 06:03:27 PM PDT 24
Peak memory 217820 kb
Host smart-248c1756-500d-4863-bd41-c0a7c7cc5fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828070824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1828070824
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.3112163740
Short name T111
Test name
Test status
Simulation time 36907935 ps
CPU time 1.09 seconds
Started Jun 28 06:03:22 PM PDT 24
Finished Jun 28 06:03:30 PM PDT 24
Peak memory 218940 kb
Host smart-4a3e057f-3bc0-4ca1-9851-898163e2e593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112163740 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.3112163740
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.2213054179
Short name T330
Test name
Test status
Simulation time 61385651 ps
CPU time 1.19 seconds
Started Jun 28 06:03:19 PM PDT 24
Finished Jun 28 06:03:28 PM PDT 24
Peak memory 219304 kb
Host smart-5796c682-33b5-4744-b0da-37a35317c6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213054179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2213054179
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.1281610388
Short name T143
Test name
Test status
Simulation time 113690633 ps
CPU time 1.23 seconds
Started Jun 28 06:03:27 PM PDT 24
Finished Jun 28 06:03:34 PM PDT 24
Peak memory 216004 kb
Host smart-207d7c73-4543-4978-bbf4-36d12e0857d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281610388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.1281610388
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/167.edn_alert.1223700012
Short name T312
Test name
Test status
Simulation time 36299672 ps
CPU time 1.1 seconds
Started Jun 28 06:03:28 PM PDT 24
Finished Jun 28 06:03:35 PM PDT 24
Peak memory 218740 kb
Host smart-f3fc15b1-961a-4f49-abd7-aef1803c38e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223700012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1223700012
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.2580985587
Short name T570
Test name
Test status
Simulation time 65544349 ps
CPU time 1.07 seconds
Started Jun 28 06:03:22 PM PDT 24
Finished Jun 28 06:03:30 PM PDT 24
Peak memory 219900 kb
Host smart-21da7467-f011-4b59-98e8-c070a363d140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580985587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2580985587
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.3639424548
Short name T160
Test name
Test status
Simulation time 93100294 ps
CPU time 1.22 seconds
Started Jun 28 06:03:18 PM PDT 24
Finished Jun 28 06:03:27 PM PDT 24
Peak memory 218936 kb
Host smart-9364fb91-6456-4ea6-a8c7-06c9364dc433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639424548 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.3639424548
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.3610487684
Short name T928
Test name
Test status
Simulation time 51291458 ps
CPU time 1.18 seconds
Started Jun 28 06:03:23 PM PDT 24
Finished Jun 28 06:03:31 PM PDT 24
Peak memory 217640 kb
Host smart-edf86a5b-0845-45da-96ce-49b40b85f77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610487684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3610487684
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.3655790550
Short name T86
Test name
Test status
Simulation time 29966793 ps
CPU time 1.28 seconds
Started Jun 28 06:03:22 PM PDT 24
Finished Jun 28 06:03:30 PM PDT 24
Peak memory 220852 kb
Host smart-b8e946d9-7d6f-4d5e-9a5e-6c27fd3b0fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655790550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.3655790550
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.3083131749
Short name T661
Test name
Test status
Simulation time 91212332 ps
CPU time 1.32 seconds
Started Jun 28 06:03:14 PM PDT 24
Finished Jun 28 06:03:24 PM PDT 24
Peak memory 217556 kb
Host smart-e389b874-5b09-40e2-9d8a-4f2a289c3f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083131749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3083131749
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.647869852
Short name T530
Test name
Test status
Simulation time 27860982 ps
CPU time 1.24 seconds
Started Jun 28 06:01:55 PM PDT 24
Finished Jun 28 06:02:05 PM PDT 24
Peak memory 220104 kb
Host smart-77bb4632-cc23-4eea-9283-c3233675e919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647869852 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.647869852
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3140882964
Short name T647
Test name
Test status
Simulation time 16715580 ps
CPU time 0.94 seconds
Started Jun 28 06:01:55 PM PDT 24
Finished Jun 28 06:02:05 PM PDT 24
Peak memory 215204 kb
Host smart-ee7a16e3-fd8b-4451-a2b8-26aeabddf0d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140882964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3140882964
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3944813810
Short name T97
Test name
Test status
Simulation time 43712460 ps
CPU time 0.95 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:01 PM PDT 24
Peak memory 215716 kb
Host smart-0c69fc82-20b0-4960-a4cd-2b6f302a6352
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944813810 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3944813810
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2704408348
Short name T990
Test name
Test status
Simulation time 27731499 ps
CPU time 1.08 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:01:59 PM PDT 24
Peak memory 218808 kb
Host smart-ffb4e700-51f5-4794-bff2-4c7963436f53
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704408348 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2704408348
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.2088622157
Short name T693
Test name
Test status
Simulation time 19264858 ps
CPU time 1.05 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:01 PM PDT 24
Peak memory 218956 kb
Host smart-c9add483-64a4-45c5-952c-00e50bde92c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088622157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2088622157
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3120389926
Short name T695
Test name
Test status
Simulation time 50081123 ps
CPU time 1.3 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:01:59 PM PDT 24
Peak memory 218624 kb
Host smart-c9a16b1d-922d-4b15-a1d8-616caad28cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120389926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3120389926
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.723741009
Short name T117
Test name
Test status
Simulation time 21557973 ps
CPU time 1.13 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:01 PM PDT 24
Peak memory 216192 kb
Host smart-5e4f0d2d-2ffc-4bab-a4a3-d3503ded230d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723741009 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.723741009
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1070557109
Short name T357
Test name
Test status
Simulation time 17734422 ps
CPU time 1.02 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:02:08 PM PDT 24
Peak memory 215600 kb
Host smart-e878de88-613c-4008-89e1-726c9f0080b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070557109 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1070557109
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.4004895204
Short name T620
Test name
Test status
Simulation time 398115007 ps
CPU time 2.69 seconds
Started Jun 28 06:01:54 PM PDT 24
Finished Jun 28 06:02:05 PM PDT 24
Peak memory 217512 kb
Host smart-fe7a06ec-3353-4fb1-b36e-5fe546cf090e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004895204 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.4004895204
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.448835697
Short name T474
Test name
Test status
Simulation time 54274121099 ps
CPU time 669.51 seconds
Started Jun 28 06:01:51 PM PDT 24
Finished Jun 28 06:13:06 PM PDT 24
Peak memory 220136 kb
Host smart-aa3c9ee3-22c5-4b23-8b25-1d19ac3f3bbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448835697 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.448835697
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.3942350565
Short name T319
Test name
Test status
Simulation time 23269533 ps
CPU time 1.14 seconds
Started Jun 28 06:03:21 PM PDT 24
Finished Jun 28 06:03:29 PM PDT 24
Peak memory 219052 kb
Host smart-7933b427-1efb-4131-a8ad-6ab83d2ce0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942350565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.3942350565
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.4039022514
Short name T920
Test name
Test status
Simulation time 56207346 ps
CPU time 1.96 seconds
Started Jun 28 06:03:16 PM PDT 24
Finished Jun 28 06:03:27 PM PDT 24
Peak memory 219156 kb
Host smart-f110627c-3813-4fc9-b1c5-ceb9dc3f67bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039022514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.4039022514
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.114848423
Short name T317
Test name
Test status
Simulation time 44697836 ps
CPU time 1.07 seconds
Started Jun 28 06:03:23 PM PDT 24
Finished Jun 28 06:03:31 PM PDT 24
Peak memory 220096 kb
Host smart-b360f3b0-9b41-4549-baf4-d7f7583fd35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114848423 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.114848423
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.15736358
Short name T576
Test name
Test status
Simulation time 90372525 ps
CPU time 1.13 seconds
Started Jun 28 06:03:21 PM PDT 24
Finished Jun 28 06:03:29 PM PDT 24
Peak memory 217644 kb
Host smart-579ba7b1-f222-4e76-bf8b-9486dd421263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15736358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.15736358
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1577523054
Short name T806
Test name
Test status
Simulation time 83651606 ps
CPU time 1.19 seconds
Started Jun 28 06:03:30 PM PDT 24
Finished Jun 28 06:03:38 PM PDT 24
Peak memory 219964 kb
Host smart-737df1d8-7fcd-4a54-8a5e-4ac6894f137c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577523054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1577523054
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.2703844706
Short name T470
Test name
Test status
Simulation time 27476420 ps
CPU time 1.27 seconds
Started Jun 28 06:03:23 PM PDT 24
Finished Jun 28 06:03:31 PM PDT 24
Peak memory 217892 kb
Host smart-1e328eb3-5c3c-4777-a60a-4f8bae8a7d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703844706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2703844706
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.372850780
Short name T601
Test name
Test status
Simulation time 22409055 ps
CPU time 1.15 seconds
Started Jun 28 06:03:15 PM PDT 24
Finished Jun 28 06:03:24 PM PDT 24
Peak memory 219088 kb
Host smart-bc33b9ff-5086-4559-a2e8-74da2a8bb9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372850780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.372850780
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/174.edn_alert.1637453034
Short name T288
Test name
Test status
Simulation time 74531915 ps
CPU time 1.16 seconds
Started Jun 28 06:03:30 PM PDT 24
Finished Jun 28 06:03:38 PM PDT 24
Peak memory 218840 kb
Host smart-b42a5957-81d0-4d06-bd28-35ab86bf091d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637453034 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.1637453034
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/175.edn_alert.1042652533
Short name T603
Test name
Test status
Simulation time 57355073 ps
CPU time 1.32 seconds
Started Jun 28 06:03:28 PM PDT 24
Finished Jun 28 06:03:36 PM PDT 24
Peak memory 220440 kb
Host smart-d6a3a2ea-ef59-4fd0-9ef7-65bf94a983bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042652533 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.1042652533
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.2141610388
Short name T744
Test name
Test status
Simulation time 87917979 ps
CPU time 1.33 seconds
Started Jun 28 06:03:33 PM PDT 24
Finished Jun 28 06:03:40 PM PDT 24
Peak memory 218988 kb
Host smart-35fa1bbc-29ad-48fb-a8f0-2e78edaa9d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141610388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2141610388
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.2109200224
Short name T596
Test name
Test status
Simulation time 79648820 ps
CPU time 1.16 seconds
Started Jun 28 06:03:32 PM PDT 24
Finished Jun 28 06:03:40 PM PDT 24
Peak memory 220112 kb
Host smart-baf477e4-0695-49cb-a6c6-1492a6c5540e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109200224 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2109200224
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.1896346693
Short name T492
Test name
Test status
Simulation time 49852559 ps
CPU time 1.33 seconds
Started Jun 28 06:03:33 PM PDT 24
Finished Jun 28 06:03:40 PM PDT 24
Peak memory 218896 kb
Host smart-3e737eef-eb5d-4223-9ea3-f5130121bb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896346693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1896346693
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.3779023620
Short name T187
Test name
Test status
Simulation time 26770735 ps
CPU time 1.25 seconds
Started Jun 28 06:03:32 PM PDT 24
Finished Jun 28 06:03:40 PM PDT 24
Peak memory 220212 kb
Host smart-30bd729a-c47a-4fd7-a230-e834d0d3b9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779023620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.3779023620
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.4016239757
Short name T981
Test name
Test status
Simulation time 41710458 ps
CPU time 1.58 seconds
Started Jun 28 06:03:34 PM PDT 24
Finished Jun 28 06:03:42 PM PDT 24
Peak memory 218636 kb
Host smart-a30c6418-0495-440a-a988-a2ad9456ae3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016239757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.4016239757
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.3750141362
Short name T258
Test name
Test status
Simulation time 103557844 ps
CPU time 1.17 seconds
Started Jun 28 06:03:27 PM PDT 24
Finished Jun 28 06:03:34 PM PDT 24
Peak memory 220140 kb
Host smart-03ab528c-2e3b-418c-99d6-4a9e08ae434a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750141362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.3750141362
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3443729356
Short name T996
Test name
Test status
Simulation time 53502233 ps
CPU time 1.16 seconds
Started Jun 28 06:03:28 PM PDT 24
Finished Jun 28 06:03:35 PM PDT 24
Peak memory 217612 kb
Host smart-02e73315-6ffd-4dc6-8fe0-570c8afa011f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443729356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3443729356
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.338142527
Short name T482
Test name
Test status
Simulation time 90867983 ps
CPU time 1.22 seconds
Started Jun 28 06:03:33 PM PDT 24
Finished Jun 28 06:03:41 PM PDT 24
Peak memory 218840 kb
Host smart-09be48e0-e269-4140-b461-9416e1bebc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338142527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.338142527
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.363740927
Short name T384
Test name
Test status
Simulation time 39483770 ps
CPU time 1.54 seconds
Started Jun 28 06:03:28 PM PDT 24
Finished Jun 28 06:03:36 PM PDT 24
Peak memory 218868 kb
Host smart-9efc6c39-d4c6-4d72-8e45-51cf94f2c542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363740927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.363740927
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3746464525
Short name T42
Test name
Test status
Simulation time 22851974 ps
CPU time 1.11 seconds
Started Jun 28 06:01:54 PM PDT 24
Finished Jun 28 06:02:04 PM PDT 24
Peak memory 219856 kb
Host smart-ae448850-bd9c-4a44-89fa-b5c956072afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746464525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3746464525
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1834288105
Short name T984
Test name
Test status
Simulation time 19595175 ps
CPU time 0.96 seconds
Started Jun 28 06:01:55 PM PDT 24
Finished Jun 28 06:02:05 PM PDT 24
Peak memory 207048 kb
Host smart-62c5dfdd-fad0-493c-ab85-a1399a41ad69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834288105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1834288105
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.454245374
Short name T832
Test name
Test status
Simulation time 14465884 ps
CPU time 0.93 seconds
Started Jun 28 06:01:58 PM PDT 24
Finished Jun 28 06:02:09 PM PDT 24
Peak memory 216780 kb
Host smart-fb2d4c44-5e99-4fcc-ae21-d8b8a9bc6a46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454245374 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.454245374
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.581031635
Short name T527
Test name
Test status
Simulation time 23325391 ps
CPU time 1 seconds
Started Jun 28 06:01:58 PM PDT 24
Finished Jun 28 06:02:09 PM PDT 24
Peak memory 224020 kb
Host smart-dc3ea1ef-75bf-4af0-9411-1e9081b4e5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581031635 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.581031635
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3538422290
Short name T373
Test name
Test status
Simulation time 51284739 ps
CPU time 1.28 seconds
Started Jun 28 06:01:58 PM PDT 24
Finished Jun 28 06:02:09 PM PDT 24
Peak memory 219808 kb
Host smart-6d79171e-18bb-45e9-a2c2-472a0f62abf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538422290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3538422290
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.634441163
Short name T657
Test name
Test status
Simulation time 25980920 ps
CPU time 0.93 seconds
Started Jun 28 06:01:51 PM PDT 24
Finished Jun 28 06:01:58 PM PDT 24
Peak memory 215804 kb
Host smart-7f93d737-99a5-4518-81f9-e6ca2c556440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634441163 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.634441163
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2621391256
Short name T605
Test name
Test status
Simulation time 17213613 ps
CPU time 1.02 seconds
Started Jun 28 06:01:55 PM PDT 24
Finished Jun 28 06:02:05 PM PDT 24
Peak memory 215624 kb
Host smart-b0d02159-c866-4768-b8a3-a0f93e736dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621391256 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2621391256
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3714034017
Short name T338
Test name
Test status
Simulation time 413372158 ps
CPU time 7.17 seconds
Started Jun 28 06:01:58 PM PDT 24
Finished Jun 28 06:02:15 PM PDT 24
Peak memory 215640 kb
Host smart-d2cda783-8358-4818-9720-05c13f464ff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714034017 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3714034017
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1704474321
Short name T824
Test name
Test status
Simulation time 52995155286 ps
CPU time 1285.33 seconds
Started Jun 28 06:01:58 PM PDT 24
Finished Jun 28 06:23:33 PM PDT 24
Peak memory 223880 kb
Host smart-78f70dd1-8c97-4217-842f-51a87e29c1c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704474321 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1704474321
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.260405436
Short name T934
Test name
Test status
Simulation time 39343224 ps
CPU time 1.16 seconds
Started Jun 28 06:03:32 PM PDT 24
Finished Jun 28 06:03:40 PM PDT 24
Peak memory 218892 kb
Host smart-ce85f2a6-9da3-4512-b01e-b4e2564ed599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260405436 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.260405436
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.3845272610
Short name T931
Test name
Test status
Simulation time 80025465 ps
CPU time 1.81 seconds
Started Jun 28 06:03:27 PM PDT 24
Finished Jun 28 06:03:35 PM PDT 24
Peak memory 220472 kb
Host smart-7534617e-b66e-424f-9bbc-61b30eca6035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845272610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3845272610
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.3619012382
Short name T854
Test name
Test status
Simulation time 23283063 ps
CPU time 1.16 seconds
Started Jun 28 06:03:29 PM PDT 24
Finished Jun 28 06:03:36 PM PDT 24
Peak memory 221140 kb
Host smart-168b8f56-db89-49f1-a023-42996c0f5a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619012382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.3619012382
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.4277195117
Short name T783
Test name
Test status
Simulation time 46757671 ps
CPU time 1.21 seconds
Started Jun 28 06:03:33 PM PDT 24
Finished Jun 28 06:03:41 PM PDT 24
Peak memory 217800 kb
Host smart-59c35baa-8748-4a05-9971-ff18b28bc354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277195117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.4277195117
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.2053039319
Short name T21
Test name
Test status
Simulation time 28809898 ps
CPU time 1.24 seconds
Started Jun 28 06:03:32 PM PDT 24
Finished Jun 28 06:03:40 PM PDT 24
Peak memory 218984 kb
Host smart-c0cd7c6e-4910-4944-95bf-cd0bf5f83111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053039319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2053039319
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.796365028
Short name T888
Test name
Test status
Simulation time 92570937 ps
CPU time 1.16 seconds
Started Jun 28 06:03:32 PM PDT 24
Finished Jun 28 06:03:40 PM PDT 24
Peak memory 217800 kb
Host smart-e79a49ef-2998-407c-930a-b72b66110084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796365028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.796365028
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.3534137143
Short name T314
Test name
Test status
Simulation time 72986141 ps
CPU time 1.14 seconds
Started Jun 28 06:03:33 PM PDT 24
Finished Jun 28 06:03:41 PM PDT 24
Peak memory 220028 kb
Host smart-22e47eff-7cad-46b0-8df9-c2e2be230911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534137143 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.3534137143
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.4073073846
Short name T472
Test name
Test status
Simulation time 207928583 ps
CPU time 1.58 seconds
Started Jun 28 06:03:46 PM PDT 24
Finished Jun 28 06:03:54 PM PDT 24
Peak memory 220548 kb
Host smart-e5ec3394-7f23-477d-bd18-cdcea428f668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073073846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.4073073846
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.3005314146
Short name T112
Test name
Test status
Simulation time 178138937 ps
CPU time 1.11 seconds
Started Jun 28 06:03:30 PM PDT 24
Finished Jun 28 06:03:38 PM PDT 24
Peak memory 218988 kb
Host smart-abeb8855-d32e-480c-bc0a-2a2fd439b3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005314146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.3005314146
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.2998673024
Short name T886
Test name
Test status
Simulation time 352103922 ps
CPU time 1.26 seconds
Started Jun 28 06:03:28 PM PDT 24
Finished Jun 28 06:03:35 PM PDT 24
Peak memory 217676 kb
Host smart-702b28c5-4da8-4e58-9229-101308684f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998673024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2998673024
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.1104731487
Short name T669
Test name
Test status
Simulation time 49537484 ps
CPU time 1.25 seconds
Started Jun 28 06:03:37 PM PDT 24
Finished Jun 28 06:03:45 PM PDT 24
Peak memory 220408 kb
Host smart-0078eb97-b92e-4f38-9f34-43487db63141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104731487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.1104731487
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.1506542019
Short name T848
Test name
Test status
Simulation time 92147716 ps
CPU time 1.17 seconds
Started Jun 28 06:03:26 PM PDT 24
Finished Jun 28 06:03:33 PM PDT 24
Peak memory 220324 kb
Host smart-a0203c4f-edce-42ed-808c-91cb558467cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506542019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1506542019
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.3976606329
Short name T153
Test name
Test status
Simulation time 25717796 ps
CPU time 1.16 seconds
Started Jun 28 06:03:35 PM PDT 24
Finished Jun 28 06:03:42 PM PDT 24
Peak memory 221040 kb
Host smart-af69b55a-31c6-4f4b-a29f-0d3fe6be0d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976606329 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.3976606329
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.3434202242
Short name T513
Test name
Test status
Simulation time 428602284 ps
CPU time 3.51 seconds
Started Jun 28 06:03:27 PM PDT 24
Finished Jun 28 06:03:37 PM PDT 24
Peak memory 220656 kb
Host smart-562758df-c6ee-432f-a948-971def9e787a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434202242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3434202242
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.3939394214
Short name T881
Test name
Test status
Simulation time 60112551 ps
CPU time 1.2 seconds
Started Jun 28 06:03:34 PM PDT 24
Finished Jun 28 06:03:42 PM PDT 24
Peak memory 220220 kb
Host smart-cb7481f1-0bd9-409e-9048-aa3a2ad41218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939394214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.3939394214
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.2655368404
Short name T392
Test name
Test status
Simulation time 56423758 ps
CPU time 1.31 seconds
Started Jun 28 06:03:27 PM PDT 24
Finished Jun 28 06:03:34 PM PDT 24
Peak memory 218700 kb
Host smart-a03b17c4-ca89-4bf9-ac4a-c9a437ad5e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655368404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2655368404
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.2655096760
Short name T568
Test name
Test status
Simulation time 28670368 ps
CPU time 1.3 seconds
Started Jun 28 06:03:29 PM PDT 24
Finished Jun 28 06:03:36 PM PDT 24
Peak memory 220204 kb
Host smart-30efbd97-fa13-46cf-ab88-81a835c9871f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655096760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2655096760
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.3935317329
Short name T640
Test name
Test status
Simulation time 100628595 ps
CPU time 1.05 seconds
Started Jun 28 06:03:47 PM PDT 24
Finished Jun 28 06:03:55 PM PDT 24
Peak memory 217716 kb
Host smart-ee934c65-e939-4d58-b9f1-ad26bfd3bdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935317329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3935317329
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.324406416
Short name T491
Test name
Test status
Simulation time 48917501 ps
CPU time 1.22 seconds
Started Jun 28 06:03:29 PM PDT 24
Finished Jun 28 06:03:37 PM PDT 24
Peak memory 220356 kb
Host smart-03e35d28-ad49-4cbc-ab95-74c2d5570dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324406416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.324406416
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert.3042216053
Short name T606
Test name
Test status
Simulation time 26010419 ps
CPU time 1.17 seconds
Started Jun 28 06:01:59 PM PDT 24
Finished Jun 28 06:02:09 PM PDT 24
Peak memory 220252 kb
Host smart-1df69934-ac99-49f1-9335-9840a9d47487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042216053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3042216053
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1497858083
Short name T396
Test name
Test status
Simulation time 72311117 ps
CPU time 0.94 seconds
Started Jun 28 06:01:58 PM PDT 24
Finished Jun 28 06:02:09 PM PDT 24
Peak memory 215208 kb
Host smart-31b4cf67-5d95-476a-a454-1209b5155280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497858083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1497858083
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1332444721
Short name T214
Test name
Test status
Simulation time 27845489 ps
CPU time 0.83 seconds
Started Jun 28 06:01:54 PM PDT 24
Finished Jun 28 06:02:03 PM PDT 24
Peak memory 215716 kb
Host smart-bbb60007-ead3-4d8e-b9a4-743784ec7580
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332444721 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1332444721
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.3768705619
Short name T58
Test name
Test status
Simulation time 34838746 ps
CPU time 0.98 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:02:00 PM PDT 24
Peak memory 224080 kb
Host smart-b8c11cfe-c13c-4756-8527-22d81b8fd771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768705619 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3768705619
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2053541273
Short name T635
Test name
Test status
Simulation time 51654788 ps
CPU time 1.27 seconds
Started Jun 28 06:01:59 PM PDT 24
Finished Jun 28 06:02:09 PM PDT 24
Peak memory 218848 kb
Host smart-9ac84881-eb7b-4ff5-8d08-ee71a8718e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053541273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2053541273
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3752987874
Short name T469
Test name
Test status
Simulation time 29783272 ps
CPU time 1.05 seconds
Started Jun 28 06:01:59 PM PDT 24
Finished Jun 28 06:02:10 PM PDT 24
Peak memory 224404 kb
Host smart-ccde61f5-9510-41ec-9d95-0a8e3677d4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752987874 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3752987874
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1030924429
Short name T385
Test name
Test status
Simulation time 17061187 ps
CPU time 0.99 seconds
Started Jun 28 06:01:58 PM PDT 24
Finished Jun 28 06:02:14 PM PDT 24
Peak memory 215592 kb
Host smart-3b8869a1-2110-468e-bc5a-680b4bd28611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030924429 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1030924429
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3554671296
Short name T782
Test name
Test status
Simulation time 212164142436 ps
CPU time 2479.09 seconds
Started Jun 28 06:02:00 PM PDT 24
Finished Jun 28 06:43:29 PM PDT 24
Peak memory 229284 kb
Host smart-c0ec6906-334e-4096-ab8e-b349cd3ce5c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554671296 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3554671296
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.3797961591
Short name T823
Test name
Test status
Simulation time 29125217 ps
CPU time 1.25 seconds
Started Jun 28 06:03:30 PM PDT 24
Finished Jun 28 06:03:38 PM PDT 24
Peak memory 218928 kb
Host smart-9a379682-8b79-4fe0-80e7-02060d8929d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797961591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.3797961591
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.179740458
Short name T453
Test name
Test status
Simulation time 203140644 ps
CPU time 0.97 seconds
Started Jun 28 06:03:28 PM PDT 24
Finished Jun 28 06:03:34 PM PDT 24
Peak memory 217712 kb
Host smart-b895ce47-f955-4bd0-9354-4569b46cd694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179740458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.179740458
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.3711834884
Short name T892
Test name
Test status
Simulation time 90634667 ps
CPU time 1.3 seconds
Started Jun 28 06:03:34 PM PDT 24
Finished Jun 28 06:03:42 PM PDT 24
Peak memory 218980 kb
Host smart-ec4e32f2-c3b0-4b08-a510-0e78a74c792e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711834884 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.3711834884
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.3263736287
Short name T852
Test name
Test status
Simulation time 129019171 ps
CPU time 1.38 seconds
Started Jun 28 06:03:29 PM PDT 24
Finished Jun 28 06:03:37 PM PDT 24
Peak memory 217796 kb
Host smart-c1f2b2f5-8f19-485a-bf25-243978e3c995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263736287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3263736287
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.3121627889
Short name T676
Test name
Test status
Simulation time 150421289 ps
CPU time 1.15 seconds
Started Jun 28 06:03:36 PM PDT 24
Finished Jun 28 06:03:44 PM PDT 24
Peak memory 221312 kb
Host smart-a817f995-bf33-4739-a8a5-f93b8f7e9865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121627889 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3121627889
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.3871176955
Short name T85
Test name
Test status
Simulation time 62830915 ps
CPU time 1.22 seconds
Started Jun 28 06:03:35 PM PDT 24
Finished Jun 28 06:03:43 PM PDT 24
Peak memory 218916 kb
Host smart-354ec452-5186-4937-93ad-b4455e8dd288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871176955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3871176955
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.529621389
Short name T721
Test name
Test status
Simulation time 75792663 ps
CPU time 1.12 seconds
Started Jun 28 06:03:29 PM PDT 24
Finished Jun 28 06:03:36 PM PDT 24
Peak memory 219880 kb
Host smart-6e1c0db9-9de1-4f20-8337-dc6a6b2296a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529621389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.529621389
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/194.edn_alert.2785974942
Short name T575
Test name
Test status
Simulation time 98339065 ps
CPU time 1.12 seconds
Started Jun 28 06:03:36 PM PDT 24
Finished Jun 28 06:03:44 PM PDT 24
Peak memory 219936 kb
Host smart-18fb8cf7-c64f-4698-b51e-061e770a86ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785974942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.2785974942
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.462380921
Short name T691
Test name
Test status
Simulation time 58500518 ps
CPU time 1.31 seconds
Started Jun 28 06:03:35 PM PDT 24
Finished Jun 28 06:03:43 PM PDT 24
Peak memory 219048 kb
Host smart-1674e53f-8a46-4cc0-9a56-f4ba313e8fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462380921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.462380921
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.1451962695
Short name T756
Test name
Test status
Simulation time 120327239 ps
CPU time 1.15 seconds
Started Jun 28 06:03:44 PM PDT 24
Finished Jun 28 06:03:51 PM PDT 24
Peak memory 220980 kb
Host smart-8fce752e-31a7-4503-a5ce-b24016cd0c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451962695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.1451962695
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.1565092613
Short name T532
Test name
Test status
Simulation time 159832530 ps
CPU time 1.06 seconds
Started Jun 28 06:03:40 PM PDT 24
Finished Jun 28 06:03:47 PM PDT 24
Peak memory 217728 kb
Host smart-21e9373a-a790-49aa-b697-67357c10c973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565092613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1565092613
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.1307094158
Short name T139
Test name
Test status
Simulation time 31719531 ps
CPU time 1.37 seconds
Started Jun 28 06:03:45 PM PDT 24
Finished Jun 28 06:03:53 PM PDT 24
Peak memory 215984 kb
Host smart-f9590204-6bb9-489a-a1ae-545b52abb4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307094158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.1307094158
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/197.edn_alert.623014976
Short name T980
Test name
Test status
Simulation time 67929810 ps
CPU time 1.14 seconds
Started Jun 28 06:03:28 PM PDT 24
Finished Jun 28 06:03:35 PM PDT 24
Peak memory 218852 kb
Host smart-40a2dd9a-effa-476f-92c0-82818d21d02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623014976 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.623014976
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.3843242818
Short name T310
Test name
Test status
Simulation time 39338444 ps
CPU time 1.49 seconds
Started Jun 28 06:03:35 PM PDT 24
Finished Jun 28 06:03:43 PM PDT 24
Peak memory 217668 kb
Host smart-07b94664-04a1-474c-8fe6-87ff21b08468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843242818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3843242818
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.1077606222
Short name T690
Test name
Test status
Simulation time 83004627 ps
CPU time 1.18 seconds
Started Jun 28 06:03:29 PM PDT 24
Finished Jun 28 06:03:36 PM PDT 24
Peak memory 220376 kb
Host smart-af2c160b-4308-4534-914e-756a53c3317d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077606222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.1077606222
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.1212209990
Short name T549
Test name
Test status
Simulation time 120660469 ps
CPU time 1.53 seconds
Started Jun 28 06:03:27 PM PDT 24
Finished Jun 28 06:03:34 PM PDT 24
Peak memory 219360 kb
Host smart-8da4ff64-c2b6-4eaa-b154-c8737a78a2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212209990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1212209990
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.2702249891
Short name T939
Test name
Test status
Simulation time 25243265 ps
CPU time 1.21 seconds
Started Jun 28 06:03:40 PM PDT 24
Finished Jun 28 06:03:47 PM PDT 24
Peak memory 220836 kb
Host smart-4fc6125d-c6b7-439c-9442-39574e392e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702249891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.2702249891
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.1389400946
Short name T855
Test name
Test status
Simulation time 89106568 ps
CPU time 1.11 seconds
Started Jun 28 06:03:29 PM PDT 24
Finished Jun 28 06:03:37 PM PDT 24
Peak memory 218800 kb
Host smart-53f35de1-763b-42b0-9fac-fbc9d774197b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389400946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1389400946
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.4050223026
Short name T43
Test name
Test status
Simulation time 40280652 ps
CPU time 1.1 seconds
Started Jun 28 06:01:22 PM PDT 24
Finished Jun 28 06:01:26 PM PDT 24
Peak memory 219960 kb
Host smart-9ed1cb4d-21ba-4699-8419-954850146840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050223026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.4050223026
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.1777753030
Short name T487
Test name
Test status
Simulation time 24958097 ps
CPU time 0.79 seconds
Started Jun 28 06:01:35 PM PDT 24
Finished Jun 28 06:01:38 PM PDT 24
Peak memory 207068 kb
Host smart-553263aa-a6ae-4660-a032-4cdcb807e456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777753030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1777753030
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1390530455
Short name T718
Test name
Test status
Simulation time 18491212 ps
CPU time 0.88 seconds
Started Jun 28 06:01:34 PM PDT 24
Finished Jun 28 06:01:37 PM PDT 24
Peak memory 216560 kb
Host smart-191c55f6-e06d-4f93-a21c-98c23cf52c39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390530455 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1390530455
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1211235397
Short name T486
Test name
Test status
Simulation time 110214616 ps
CPU time 1.26 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:47 PM PDT 24
Peak memory 217324 kb
Host smart-edd0a05a-a674-4adf-a5a2-acd1c30206e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211235397 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1211235397
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.2539452041
Short name T107
Test name
Test status
Simulation time 19699523 ps
CPU time 1.07 seconds
Started Jun 28 06:01:19 PM PDT 24
Finished Jun 28 06:01:24 PM PDT 24
Peak memory 218880 kb
Host smart-5eee4b83-a700-46b1-b628-64bb28e29916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539452041 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2539452041
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.4072700719
Short name T964
Test name
Test status
Simulation time 61575278 ps
CPU time 1.39 seconds
Started Jun 28 06:01:23 PM PDT 24
Finished Jun 28 06:01:27 PM PDT 24
Peak memory 220384 kb
Host smart-c39d6224-23ed-43c9-9ce9-43d33bd82d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072700719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.4072700719
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2635475617
Short name T477
Test name
Test status
Simulation time 23259113 ps
CPU time 1.09 seconds
Started Jun 28 06:01:23 PM PDT 24
Finished Jun 28 06:01:27 PM PDT 24
Peak memory 215744 kb
Host smart-eb333566-02f2-46c8-91da-b623eaee64ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635475617 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2635475617
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3011727889
Short name T309
Test name
Test status
Simulation time 40687519 ps
CPU time 0.86 seconds
Started Jun 28 06:01:13 PM PDT 24
Finished Jun 28 06:01:15 PM PDT 24
Peak memory 207388 kb
Host smart-df8096aa-04bf-4dc4-a119-eddef9d23acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011727889 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3011727889
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2483821390
Short name T14
Test name
Test status
Simulation time 1737327754 ps
CPU time 6.85 seconds
Started Jun 28 06:01:35 PM PDT 24
Finished Jun 28 06:01:43 PM PDT 24
Peak memory 236176 kb
Host smart-a177a958-00be-4e44-a8c7-0b3b527bd027
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483821390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2483821390
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3489376177
Short name T229
Test name
Test status
Simulation time 14633132 ps
CPU time 0.99 seconds
Started Jun 28 06:01:23 PM PDT 24
Finished Jun 28 06:01:27 PM PDT 24
Peak memory 215636 kb
Host smart-6dcc9966-0af4-48e1-9343-fbb4d3922196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489376177 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3489376177
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.606317207
Short name T422
Test name
Test status
Simulation time 962805672 ps
CPU time 5.1 seconds
Started Jun 28 06:01:21 PM PDT 24
Finished Jun 28 06:01:30 PM PDT 24
Peak memory 217564 kb
Host smart-40a52f16-c0d7-4def-86df-d212e88f25cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606317207 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.606317207
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1391258513
Short name T787
Test name
Test status
Simulation time 46387174147 ps
CPU time 550.07 seconds
Started Jun 28 06:01:23 PM PDT 24
Finished Jun 28 06:10:36 PM PDT 24
Peak memory 218068 kb
Host smart-81a15684-51e5-44d0-adaa-3c37dccb17db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391258513 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1391258513
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert_test.3819950492
Short name T764
Test name
Test status
Simulation time 15914991 ps
CPU time 0.98 seconds
Started Jun 28 06:01:50 PM PDT 24
Finished Jun 28 06:01:57 PM PDT 24
Peak memory 207016 kb
Host smart-70fe3a4c-632c-4424-af8e-40aa764c0f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819950492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3819950492
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.2506715915
Short name T200
Test name
Test status
Simulation time 33360810 ps
CPU time 0.86 seconds
Started Jun 28 06:01:51 PM PDT 24
Finished Jun 28 06:01:57 PM PDT 24
Peak memory 216556 kb
Host smart-f359357a-d318-4831-88e6-97aa517226f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506715915 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2506715915
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.439676455
Short name T1001
Test name
Test status
Simulation time 31571216 ps
CPU time 1.18 seconds
Started Jun 28 06:01:54 PM PDT 24
Finished Jun 28 06:02:04 PM PDT 24
Peak memory 220104 kb
Host smart-0fe8b12e-d0ff-4d23-8f14-cd6e94e3d3bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439676455 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.439676455
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2154348471
Short name T141
Test name
Test status
Simulation time 40045271 ps
CPU time 1.02 seconds
Started Jun 28 06:01:55 PM PDT 24
Finished Jun 28 06:02:05 PM PDT 24
Peak memory 219908 kb
Host smart-f5db93ab-b47a-466d-ace9-b8a1ebc6fbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154348471 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2154348471
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.103282930
Short name T670
Test name
Test status
Simulation time 41546063 ps
CPU time 1.26 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:02:00 PM PDT 24
Peak memory 218912 kb
Host smart-ede9a6e0-57d1-44af-939e-cfac0fd729ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103282930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.103282930
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3437505373
Short name T30
Test name
Test status
Simulation time 21884204 ps
CPU time 1.06 seconds
Started Jun 28 06:01:50 PM PDT 24
Finished Jun 28 06:01:56 PM PDT 24
Peak memory 216232 kb
Host smart-a2498b27-508a-4e0d-be57-de2156131671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437505373 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3437505373
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2617953654
Short name T523
Test name
Test status
Simulation time 17895342 ps
CPU time 1.01 seconds
Started Jun 28 06:01:58 PM PDT 24
Finished Jun 28 06:02:11 PM PDT 24
Peak memory 207400 kb
Host smart-bffc6508-bf72-49f1-bed1-2e6c9be179be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617953654 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2617953654
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2754416466
Short name T489
Test name
Test status
Simulation time 119292068 ps
CPU time 1.94 seconds
Started Jun 28 06:01:51 PM PDT 24
Finished Jun 28 06:02:00 PM PDT 24
Peak memory 218764 kb
Host smart-d3411197-fa15-4d33-bf89-ea77019766b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754416466 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2754416466
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2159550827
Short name T236
Test name
Test status
Simulation time 160219200713 ps
CPU time 898.31 seconds
Started Jun 28 06:01:58 PM PDT 24
Finished Jun 28 06:17:06 PM PDT 24
Peak memory 224060 kb
Host smart-98230f3a-8bdd-4bc4-97f8-451954339e23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159550827 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2159550827
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3592343191
Short name T547
Test name
Test status
Simulation time 37469719 ps
CPU time 1.47 seconds
Started Jun 28 06:03:26 PM PDT 24
Finished Jun 28 06:03:34 PM PDT 24
Peak memory 217696 kb
Host smart-7a89f6e8-3ce1-456b-8f03-650da8f6b837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592343191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3592343191
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1855137983
Short name T404
Test name
Test status
Simulation time 46204297 ps
CPU time 1.22 seconds
Started Jun 28 06:03:33 PM PDT 24
Finished Jun 28 06:03:41 PM PDT 24
Peak memory 217676 kb
Host smart-75a1f165-8615-40f9-8e97-f0ff3043f19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855137983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1855137983
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1200072038
Short name T260
Test name
Test status
Simulation time 27864827 ps
CPU time 1.35 seconds
Started Jun 28 06:03:30 PM PDT 24
Finished Jun 28 06:03:37 PM PDT 24
Peak memory 218776 kb
Host smart-aa00e277-63ea-4a26-9c67-2586534fa122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200072038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1200072038
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.251450948
Short name T879
Test name
Test status
Simulation time 45704352 ps
CPU time 1.46 seconds
Started Jun 28 06:03:32 PM PDT 24
Finished Jun 28 06:03:40 PM PDT 24
Peak memory 215616 kb
Host smart-82301459-98c3-45ca-8477-91ec54f806ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251450948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.251450948
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2071728562
Short name T621
Test name
Test status
Simulation time 798439153 ps
CPU time 4.11 seconds
Started Jun 28 06:03:30 PM PDT 24
Finished Jun 28 06:03:41 PM PDT 24
Peak memory 220400 kb
Host smart-6f087b71-0fdd-4f7b-9b0c-976b3f3e2482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071728562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2071728562
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.705998619
Short name T692
Test name
Test status
Simulation time 237377224 ps
CPU time 3.6 seconds
Started Jun 28 06:03:32 PM PDT 24
Finished Jun 28 06:03:41 PM PDT 24
Peak memory 219632 kb
Host smart-44f2caea-ba4c-4baa-93f6-ceb606f18ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705998619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.705998619
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.4191456306
Short name T471
Test name
Test status
Simulation time 35462332 ps
CPU time 1.33 seconds
Started Jun 28 06:03:40 PM PDT 24
Finished Jun 28 06:03:47 PM PDT 24
Peak memory 220160 kb
Host smart-03a8ea65-e71a-4608-9101-31b890df9354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191456306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.4191456306
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1874267699
Short name T898
Test name
Test status
Simulation time 144794313 ps
CPU time 1.81 seconds
Started Jun 28 06:03:28 PM PDT 24
Finished Jun 28 06:03:35 PM PDT 24
Peak memory 219448 kb
Host smart-7dd9138a-8a6e-47a0-8e8a-fe1e079bff79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874267699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1874267699
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.502632032
Short name T632
Test name
Test status
Simulation time 237385363 ps
CPU time 1.28 seconds
Started Jun 28 06:03:28 PM PDT 24
Finished Jun 28 06:03:35 PM PDT 24
Peak memory 220368 kb
Host smart-812c6006-7313-43cb-ad1b-04ca0b670428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502632032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.502632032
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1542799744
Short name T904
Test name
Test status
Simulation time 53887954 ps
CPU time 1.39 seconds
Started Jun 28 06:03:27 PM PDT 24
Finished Jun 28 06:03:35 PM PDT 24
Peak memory 218968 kb
Host smart-a4707ee1-5bc9-4963-939d-c3920bef5ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542799744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1542799744
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2644790991
Short name T313
Test name
Test status
Simulation time 46187524 ps
CPU time 1.26 seconds
Started Jun 28 06:01:58 PM PDT 24
Finished Jun 28 06:02:09 PM PDT 24
Peak memory 219064 kb
Host smart-06d3a176-a44e-420a-9308-759a44852fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644790991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2644790991
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3773120857
Short name T989
Test name
Test status
Simulation time 31990182 ps
CPU time 0.94 seconds
Started Jun 28 06:01:51 PM PDT 24
Finished Jun 28 06:02:06 PM PDT 24
Peak memory 207076 kb
Host smart-df05e352-dcf9-4e58-8935-7af30c525531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773120857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3773120857
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_err.3936420734
Short name T424
Test name
Test status
Simulation time 48791410 ps
CPU time 0.99 seconds
Started Jun 28 06:01:59 PM PDT 24
Finished Jun 28 06:02:10 PM PDT 24
Peak memory 218892 kb
Host smart-82179cd5-ea2c-45fa-8676-14ab8b1aae56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936420734 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3936420734
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3390396936
Short name T860
Test name
Test status
Simulation time 245316769 ps
CPU time 1.16 seconds
Started Jun 28 06:01:56 PM PDT 24
Finished Jun 28 06:02:07 PM PDT 24
Peak memory 217592 kb
Host smart-1dcebc14-e28e-426f-861f-7cf3713580b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390396936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3390396936
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.4251143727
Short name T92
Test name
Test status
Simulation time 20620407 ps
CPU time 1.08 seconds
Started Jun 28 06:01:55 PM PDT 24
Finished Jun 28 06:02:05 PM PDT 24
Peak memory 216072 kb
Host smart-52d51b13-f5bc-4020-8368-f309c30f2b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251143727 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.4251143727
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3885371910
Short name T480
Test name
Test status
Simulation time 85850816 ps
CPU time 0.88 seconds
Started Jun 28 06:01:56 PM PDT 24
Finished Jun 28 06:02:06 PM PDT 24
Peak memory 215592 kb
Host smart-870bedef-8245-403a-b7e2-12c045279332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885371910 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3885371910
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1834510132
Short name T637
Test name
Test status
Simulation time 288436649 ps
CPU time 4.3 seconds
Started Jun 28 06:01:51 PM PDT 24
Finished Jun 28 06:02:11 PM PDT 24
Peak memory 220648 kb
Host smart-99caf267-6ac1-4d97-b79c-e84b61b1f900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834510132 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1834510132
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.4219087323
Short name T223
Test name
Test status
Simulation time 107129157011 ps
CPU time 393.87 seconds
Started Jun 28 06:01:59 PM PDT 24
Finished Jun 28 06:08:42 PM PDT 24
Peak memory 219692 kb
Host smart-6768aa18-a4b4-4035-af3a-c1ea4c8de31f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219087323 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.4219087323
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.4005410049
Short name T908
Test name
Test status
Simulation time 65862262 ps
CPU time 1.19 seconds
Started Jun 28 06:03:35 PM PDT 24
Finished Jun 28 06:03:43 PM PDT 24
Peak memory 220228 kb
Host smart-f68775ac-152c-4d52-a310-12750befee68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005410049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.4005410049
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2082799725
Short name T353
Test name
Test status
Simulation time 73421492 ps
CPU time 1.4 seconds
Started Jun 28 06:03:28 PM PDT 24
Finished Jun 28 06:03:35 PM PDT 24
Peak memory 218896 kb
Host smart-c56d7104-46d1-4dd5-bf54-236666196189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082799725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2082799725
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3145592020
Short name T484
Test name
Test status
Simulation time 191138910 ps
CPU time 2.6 seconds
Started Jun 28 06:03:32 PM PDT 24
Finished Jun 28 06:03:41 PM PDT 24
Peak memory 220308 kb
Host smart-2483be39-93c0-4a9e-80c9-bcba24fdda7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145592020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3145592020
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.331342098
Short name T554
Test name
Test status
Simulation time 41358025 ps
CPU time 1.23 seconds
Started Jun 28 06:03:40 PM PDT 24
Finished Jun 28 06:03:47 PM PDT 24
Peak memory 217740 kb
Host smart-7dd73582-7658-492b-995f-6f12a7ac3c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331342098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.331342098
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1343266180
Short name T369
Test name
Test status
Simulation time 87702812 ps
CPU time 1.37 seconds
Started Jun 28 06:03:32 PM PDT 24
Finished Jun 28 06:03:39 PM PDT 24
Peak memory 219100 kb
Host smart-4c243916-34a3-4ddb-ac5a-2d2e593bf02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343266180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1343266180
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.331232961
Short name T541
Test name
Test status
Simulation time 30841137 ps
CPU time 1.25 seconds
Started Jun 28 06:03:29 PM PDT 24
Finished Jun 28 06:03:36 PM PDT 24
Peak memory 217632 kb
Host smart-c1d842a3-bca6-4ba3-82a2-7cf4c796832a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331232961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.331232961
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2193197177
Short name T607
Test name
Test status
Simulation time 38084345 ps
CPU time 1.6 seconds
Started Jun 28 06:03:37 PM PDT 24
Finished Jun 28 06:03:44 PM PDT 24
Peak memory 217928 kb
Host smart-157b6bc5-a141-45fd-8a7b-b394c9b0521a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193197177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2193197177
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2482774049
Short name T861
Test name
Test status
Simulation time 389530784 ps
CPU time 3.66 seconds
Started Jun 28 06:03:32 PM PDT 24
Finished Jun 28 06:03:42 PM PDT 24
Peak memory 218960 kb
Host smart-fede1f34-fe95-4dec-8f85-091f08f56cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482774049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2482774049
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.4016541303
Short name T997
Test name
Test status
Simulation time 32726128 ps
CPU time 1.33 seconds
Started Jun 28 06:03:34 PM PDT 24
Finished Jun 28 06:03:42 PM PDT 24
Peak memory 218632 kb
Host smart-c1f0a9ff-0ecb-4fbd-aed8-2cb0eada9bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016541303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.4016541303
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.4185202994
Short name T918
Test name
Test status
Simulation time 103318430 ps
CPU time 1.31 seconds
Started Jun 28 06:02:00 PM PDT 24
Finished Jun 28 06:02:11 PM PDT 24
Peak memory 215988 kb
Host smart-aed5e7c7-e746-4cf1-b434-05907c9f8c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185202994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.4185202994
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2813976946
Short name T500
Test name
Test status
Simulation time 30369705 ps
CPU time 0.93 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:01 PM PDT 24
Peak memory 215476 kb
Host smart-4067e83a-d934-4df2-993c-9587f3604540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813976946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2813976946
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3194275966
Short name T816
Test name
Test status
Simulation time 42988247 ps
CPU time 1.08 seconds
Started Jun 28 06:01:59 PM PDT 24
Finished Jun 28 06:02:10 PM PDT 24
Peak memory 215880 kb
Host smart-4befa530-e682-493e-9812-530df91e82e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194275966 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3194275966
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.326321508
Short name T446
Test name
Test status
Simulation time 25078981 ps
CPU time 1.27 seconds
Started Jun 28 06:02:00 PM PDT 24
Finished Jun 28 06:02:11 PM PDT 24
Peak memory 218876 kb
Host smart-2927ff2f-dba0-4bb7-88ce-c96d6a36803a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326321508 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.326321508
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1038322941
Short name T354
Test name
Test status
Simulation time 50782772 ps
CPU time 1.54 seconds
Started Jun 28 06:02:05 PM PDT 24
Finished Jun 28 06:02:15 PM PDT 24
Peak memory 218972 kb
Host smart-3eee419f-85d4-4e8e-bb06-5058116aab68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038322941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1038322941
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.269171853
Short name T885
Test name
Test status
Simulation time 22249486 ps
CPU time 1.19 seconds
Started Jun 28 06:01:59 PM PDT 24
Finished Jun 28 06:02:09 PM PDT 24
Peak memory 224284 kb
Host smart-0de523b0-ac20-44d6-b9e0-119eb92c4c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269171853 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.269171853
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2394995563
Short name T688
Test name
Test status
Simulation time 16485137 ps
CPU time 0.99 seconds
Started Jun 28 06:01:59 PM PDT 24
Finished Jun 28 06:02:09 PM PDT 24
Peak memory 215564 kb
Host smart-bb9e126d-cc52-444e-9a4f-b84d390b330e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394995563 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2394995563
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.63715839
Short name T529
Test name
Test status
Simulation time 499891633 ps
CPU time 1.68 seconds
Started Jun 28 06:02:00 PM PDT 24
Finished Jun 28 06:02:11 PM PDT 24
Peak memory 217696 kb
Host smart-5329dfa2-dcbf-4329-82ba-1611785c365b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63715839 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.63715839
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.4127775341
Short name T473
Test name
Test status
Simulation time 514019927609 ps
CPU time 2159.35 seconds
Started Jun 28 06:01:59 PM PDT 24
Finished Jun 28 06:38:08 PM PDT 24
Peak memory 230592 kb
Host smart-3cdeb778-f0de-4382-a730-9f781ddd22db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127775341 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.4127775341
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3255838710
Short name T352
Test name
Test status
Simulation time 32934150 ps
CPU time 1.39 seconds
Started Jun 28 06:03:30 PM PDT 24
Finished Jun 28 06:03:38 PM PDT 24
Peak memory 218860 kb
Host smart-96786646-7c0c-4d92-9108-e260e958d282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255838710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3255838710
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3053351911
Short name T643
Test name
Test status
Simulation time 36312425 ps
CPU time 1.34 seconds
Started Jun 28 06:03:33 PM PDT 24
Finished Jun 28 06:03:41 PM PDT 24
Peak memory 220200 kb
Host smart-0e7ccfce-0b16-454b-90f7-ea405cb197aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053351911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3053351911
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.575954743
Short name T331
Test name
Test status
Simulation time 60837849 ps
CPU time 1.09 seconds
Started Jun 28 06:03:38 PM PDT 24
Finished Jun 28 06:03:46 PM PDT 24
Peak memory 220204 kb
Host smart-3041a018-5ac1-4236-8d6a-d8f7d46f90c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575954743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.575954743
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.291209042
Short name T336
Test name
Test status
Simulation time 61969940 ps
CPU time 1.07 seconds
Started Jun 28 06:03:34 PM PDT 24
Finished Jun 28 06:03:42 PM PDT 24
Peak memory 220212 kb
Host smart-7f94e622-3cd5-40cd-999d-f85e6ca4bca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291209042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.291209042
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2707119251
Short name T50
Test name
Test status
Simulation time 32874038 ps
CPU time 1.32 seconds
Started Jun 28 06:03:30 PM PDT 24
Finished Jun 28 06:03:38 PM PDT 24
Peak memory 219768 kb
Host smart-5667d482-cc6e-4eab-a118-6f777087b97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707119251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2707119251
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2624756023
Short name T790
Test name
Test status
Simulation time 216814059 ps
CPU time 2.46 seconds
Started Jun 28 06:03:33 PM PDT 24
Finished Jun 28 06:03:43 PM PDT 24
Peak memory 219196 kb
Host smart-36ceed6f-dbd1-4ef0-bc77-ff440f459a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624756023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2624756023
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3299028266
Short name T656
Test name
Test status
Simulation time 39837408 ps
CPU time 1.55 seconds
Started Jun 28 06:03:34 PM PDT 24
Finished Jun 28 06:03:42 PM PDT 24
Peak memory 218824 kb
Host smart-bdc4b6ef-080b-4e48-a6ad-836f267ba8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299028266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3299028266
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3021195343
Short name T351
Test name
Test status
Simulation time 92352005 ps
CPU time 1.39 seconds
Started Jun 28 06:03:30 PM PDT 24
Finished Jun 28 06:03:38 PM PDT 24
Peak memory 219152 kb
Host smart-aea409b1-60f5-4fcc-8a70-068b88a16b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021195343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3021195343
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.141420755
Short name T648
Test name
Test status
Simulation time 70179081 ps
CPU time 1.14 seconds
Started Jun 28 06:03:32 PM PDT 24
Finished Jun 28 06:03:40 PM PDT 24
Peak memory 217672 kb
Host smart-b81c9ad0-3c39-4d6e-9a8e-a3a367871937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141420755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.141420755
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1822511455
Short name T430
Test name
Test status
Simulation time 113991921 ps
CPU time 1.2 seconds
Started Jun 28 06:03:35 PM PDT 24
Finished Jun 28 06:03:43 PM PDT 24
Peak memory 217708 kb
Host smart-13161e27-716d-4c3c-9c3c-63144955b2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822511455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1822511455
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.4127642301
Short name T316
Test name
Test status
Simulation time 52738838 ps
CPU time 1.31 seconds
Started Jun 28 06:01:55 PM PDT 24
Finished Jun 28 06:02:05 PM PDT 24
Peak memory 220248 kb
Host smart-b72f282d-ced2-40c6-a936-629da7e5dfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127642301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.4127642301
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1337938383
Short name T442
Test name
Test status
Simulation time 30977263 ps
CPU time 0.99 seconds
Started Jun 28 06:02:04 PM PDT 24
Finished Jun 28 06:02:14 PM PDT 24
Peak memory 215432 kb
Host smart-7bc812dc-623d-4737-a55f-cc891fdb16e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337938383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1337938383
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.142199641
Short name T191
Test name
Test status
Simulation time 31125701 ps
CPU time 0.82 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:02:00 PM PDT 24
Peak memory 216572 kb
Host smart-583e44f0-1838-41eb-86c4-864edf830c7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142199641 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.142199641
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2069620515
Short name T827
Test name
Test status
Simulation time 63827226 ps
CPU time 1.08 seconds
Started Jun 28 06:02:10 PM PDT 24
Finished Jun 28 06:02:19 PM PDT 24
Peak memory 219024 kb
Host smart-3d64df73-d11b-440f-9471-e48a84ae0af5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069620515 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2069620515
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1081830668
Short name T667
Test name
Test status
Simulation time 63964548 ps
CPU time 1.11 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:01:59 PM PDT 24
Peak memory 219920 kb
Host smart-752240c8-a7f6-4492-9db7-b5cdfc1b0cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081830668 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1081830668
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2796436981
Short name T436
Test name
Test status
Simulation time 55865515 ps
CPU time 1.37 seconds
Started Jun 28 06:02:11 PM PDT 24
Finished Jun 28 06:02:20 PM PDT 24
Peak memory 219048 kb
Host smart-89f2bfa2-5a30-41d0-aa42-ee0ec7215aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796436981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2796436981
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2088952077
Short name T942
Test name
Test status
Simulation time 31051454 ps
CPU time 1.1 seconds
Started Jun 28 06:02:04 PM PDT 24
Finished Jun 28 06:02:14 PM PDT 24
Peak memory 224280 kb
Host smart-bd8370ea-02db-40b2-bdc7-3a0c1ff69979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088952077 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2088952077
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.668069092
Short name T462
Test name
Test status
Simulation time 18070241 ps
CPU time 0.96 seconds
Started Jun 28 06:02:00 PM PDT 24
Finished Jun 28 06:02:10 PM PDT 24
Peak memory 215564 kb
Host smart-fe315b97-2ec3-4ade-b032-f9f8646bc72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668069092 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.668069092
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1889053904
Short name T1000
Test name
Test status
Simulation time 128563699 ps
CPU time 1.36 seconds
Started Jun 28 06:02:04 PM PDT 24
Finished Jun 28 06:02:14 PM PDT 24
Peak memory 217136 kb
Host smart-9d33b869-1884-43a9-a4a2-07a2aebb4a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889053904 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1889053904
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2094703025
Short name T785
Test name
Test status
Simulation time 48610092642 ps
CPU time 616.21 seconds
Started Jun 28 06:02:01 PM PDT 24
Finished Jun 28 06:12:26 PM PDT 24
Peak memory 219364 kb
Host smart-3b3ac9c6-dc90-4d9f-a525-57c15ae30d99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094703025 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2094703025
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.198729435
Short name T556
Test name
Test status
Simulation time 40432075 ps
CPU time 1.08 seconds
Started Jun 28 06:03:31 PM PDT 24
Finished Jun 28 06:03:38 PM PDT 24
Peak memory 217536 kb
Host smart-611c9f56-897a-4e9a-b28e-933fd31efdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198729435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.198729435
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1445441841
Short name T526
Test name
Test status
Simulation time 45487749 ps
CPU time 1.41 seconds
Started Jun 28 06:03:27 PM PDT 24
Finished Jun 28 06:03:34 PM PDT 24
Peak memory 218632 kb
Host smart-62849300-442f-49e3-a19b-eaccb514e7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445441841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1445441841
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.434198419
Short name T391
Test name
Test status
Simulation time 44831208 ps
CPU time 1.26 seconds
Started Jun 28 06:03:35 PM PDT 24
Finished Jun 28 06:03:42 PM PDT 24
Peak memory 217776 kb
Host smart-0864dff4-2212-4154-89ee-d43142d4fe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434198419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.434198419
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.854538348
Short name T419
Test name
Test status
Simulation time 36867024 ps
CPU time 1.39 seconds
Started Jun 28 06:03:31 PM PDT 24
Finished Jun 28 06:03:39 PM PDT 24
Peak memory 218760 kb
Host smart-44d55b90-7610-44ff-8b8e-f33fbd428a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854538348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.854538348
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2389284713
Short name T798
Test name
Test status
Simulation time 125794455 ps
CPU time 1.45 seconds
Started Jun 28 06:03:31 PM PDT 24
Finished Jun 28 06:03:39 PM PDT 24
Peak memory 219312 kb
Host smart-550a0930-73dd-46db-9d94-a9661c45199f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389284713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2389284713
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.225963455
Short name T741
Test name
Test status
Simulation time 111667593 ps
CPU time 2.94 seconds
Started Jun 28 06:03:36 PM PDT 24
Finished Jun 28 06:03:45 PM PDT 24
Peak memory 219580 kb
Host smart-be60d014-e349-460c-9d36-08a348b0ca14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225963455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.225963455
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3744800410
Short name T645
Test name
Test status
Simulation time 75852889 ps
CPU time 1.61 seconds
Started Jun 28 06:03:35 PM PDT 24
Finished Jun 28 06:03:43 PM PDT 24
Peak memory 219424 kb
Host smart-c90c1466-1fed-44fd-8469-aa698c4d428f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744800410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3744800410
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.181250860
Short name T509
Test name
Test status
Simulation time 39231134 ps
CPU time 1.48 seconds
Started Jun 28 06:03:30 PM PDT 24
Finished Jun 28 06:03:38 PM PDT 24
Peak memory 218108 kb
Host smart-b4e96267-e1e3-4e9c-ba9b-ed562cd57f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181250860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.181250860
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2237285530
Short name T299
Test name
Test status
Simulation time 92738719 ps
CPU time 1.15 seconds
Started Jun 28 06:03:28 PM PDT 24
Finished Jun 28 06:03:34 PM PDT 24
Peak memory 217636 kb
Host smart-84fa32f1-57a2-4fc2-ac27-47ef5cff635b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237285530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2237285530
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1378503141
Short name T689
Test name
Test status
Simulation time 85804258 ps
CPU time 1.2 seconds
Started Jun 28 06:01:58 PM PDT 24
Finished Jun 28 06:02:09 PM PDT 24
Peak memory 218828 kb
Host smart-9c2c144e-366a-49ec-89f5-97e53b214fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378503141 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1378503141
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1810461813
Short name T800
Test name
Test status
Simulation time 57297402 ps
CPU time 0.99 seconds
Started Jun 28 06:01:48 PM PDT 24
Finished Jun 28 06:01:53 PM PDT 24
Peak memory 207064 kb
Host smart-c4a68cc5-087b-4101-9873-fcfbe6a598b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810461813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1810461813
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3971415743
Short name T515
Test name
Test status
Simulation time 56250361 ps
CPU time 0.89 seconds
Started Jun 28 06:01:58 PM PDT 24
Finished Jun 28 06:02:09 PM PDT 24
Peak memory 216344 kb
Host smart-93dca99b-cee2-45ba-aa4a-692858a580a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971415743 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3971415743
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.802365024
Short name T52
Test name
Test status
Simulation time 60115105 ps
CPU time 1.56 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:03 PM PDT 24
Peak memory 217116 kb
Host smart-aeb655f2-b838-4dff-b19a-4051b9f6800d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802365024 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.802365024
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.401801219
Short name T435
Test name
Test status
Simulation time 18189667 ps
CPU time 1.14 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:03 PM PDT 24
Peak memory 218708 kb
Host smart-730ccb43-de09-42f5-ad85-2de229bded3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401801219 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.401801219
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1074565547
Short name T383
Test name
Test status
Simulation time 48504656 ps
CPU time 1.2 seconds
Started Jun 28 06:01:54 PM PDT 24
Finished Jun 28 06:02:04 PM PDT 24
Peak memory 217676 kb
Host smart-ccb04515-a015-4451-bccc-6546e2635590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074565547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1074565547
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2275652637
Short name T388
Test name
Test status
Simulation time 31065008 ps
CPU time 0.9 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:03 PM PDT 24
Peak memory 215724 kb
Host smart-af2fbf97-4c90-4e1e-a56a-9318c8304767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275652637 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2275652637
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.249648678
Short name T572
Test name
Test status
Simulation time 14815083 ps
CPU time 0.97 seconds
Started Jun 28 06:02:04 PM PDT 24
Finished Jun 28 06:02:14 PM PDT 24
Peak memory 215528 kb
Host smart-3b56f78a-a1cb-4c60-a15c-98249cc114c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249648678 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.249648678
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2899244838
Short name T701
Test name
Test status
Simulation time 739718573 ps
CPU time 4 seconds
Started Jun 28 06:02:01 PM PDT 24
Finished Jun 28 06:02:14 PM PDT 24
Peak memory 217632 kb
Host smart-3e8683bd-90bb-46ad-8534-524697e37159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899244838 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2899244838
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2820620336
Short name T894
Test name
Test status
Simulation time 80382914670 ps
CPU time 510.23 seconds
Started Jun 28 06:02:01 PM PDT 24
Finished Jun 28 06:10:40 PM PDT 24
Peak memory 219092 kb
Host smart-40af3c8a-b15d-49f4-9acc-b931b7cac3de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820620336 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2820620336
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.778085561
Short name T537
Test name
Test status
Simulation time 35360450 ps
CPU time 1.42 seconds
Started Jun 28 06:03:33 PM PDT 24
Finished Jun 28 06:03:42 PM PDT 24
Peak memory 217696 kb
Host smart-615cf8e8-ff39-4d4c-b1ca-8b84cf671fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778085561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.778085561
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2019311363
Short name T356
Test name
Test status
Simulation time 26349630 ps
CPU time 1.32 seconds
Started Jun 28 06:03:28 PM PDT 24
Finished Jun 28 06:03:35 PM PDT 24
Peak memory 220184 kb
Host smart-5647c032-9765-4a69-a637-25856fd208b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019311363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2019311363
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.768985893
Short name T901
Test name
Test status
Simulation time 51621645 ps
CPU time 1.18 seconds
Started Jun 28 06:03:37 PM PDT 24
Finished Jun 28 06:03:45 PM PDT 24
Peak memory 218844 kb
Host smart-95acbcd8-575e-4e30-8d71-7f278972eb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768985893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.768985893
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1781550072
Short name T508
Test name
Test status
Simulation time 95365047 ps
CPU time 1.16 seconds
Started Jun 28 06:03:33 PM PDT 24
Finished Jun 28 06:03:41 PM PDT 24
Peak memory 215608 kb
Host smart-b8d45817-9787-4b2d-8d80-4aa9e8b13bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781550072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1781550072
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3770228604
Short name T344
Test name
Test status
Simulation time 32423670 ps
CPU time 1.32 seconds
Started Jun 28 06:03:33 PM PDT 24
Finished Jun 28 06:03:41 PM PDT 24
Peak memory 218748 kb
Host smart-2425439f-6133-4349-a33a-f7d009a6326c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770228604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3770228604
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.944040695
Short name T771
Test name
Test status
Simulation time 42836011 ps
CPU time 1.52 seconds
Started Jun 28 06:03:35 PM PDT 24
Finished Jun 28 06:03:43 PM PDT 24
Peak memory 218772 kb
Host smart-d698274d-4cd2-486b-b774-c810fde2e117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944040695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.944040695
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.260925799
Short name T364
Test name
Test status
Simulation time 224901565 ps
CPU time 1.91 seconds
Started Jun 28 06:03:34 PM PDT 24
Finished Jun 28 06:03:43 PM PDT 24
Peak memory 220456 kb
Host smart-daa1b79e-1563-4cfc-863a-4ac170cecb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260925799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.260925799
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1448925318
Short name T991
Test name
Test status
Simulation time 41814864 ps
CPU time 1.41 seconds
Started Jun 28 06:03:31 PM PDT 24
Finished Jun 28 06:03:39 PM PDT 24
Peak memory 218960 kb
Host smart-d1ebe7e4-81e5-403c-834b-92a0e1305778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448925318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1448925318
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1690696619
Short name T598
Test name
Test status
Simulation time 58686069 ps
CPU time 1.4 seconds
Started Jun 28 06:03:36 PM PDT 24
Finished Jun 28 06:03:44 PM PDT 24
Peak memory 218732 kb
Host smart-798c08a6-8886-4b3f-b55a-7c8568f45430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690696619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1690696619
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1528038242
Short name T950
Test name
Test status
Simulation time 46098421 ps
CPU time 1.72 seconds
Started Jun 28 06:03:42 PM PDT 24
Finished Jun 28 06:03:49 PM PDT 24
Peak memory 218712 kb
Host smart-901f54cb-8895-404c-b7c5-29661c4a4d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528038242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1528038242
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.4144264044
Short name T660
Test name
Test status
Simulation time 21816792 ps
CPU time 1.2 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:03 PM PDT 24
Peak memory 220264 kb
Host smart-af6c402a-489d-4e9c-9527-871bc57558bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144264044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.4144264044
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3658777721
Short name T826
Test name
Test status
Simulation time 24506991 ps
CPU time 0.92 seconds
Started Jun 28 06:01:56 PM PDT 24
Finished Jun 28 06:02:07 PM PDT 24
Peak memory 215476 kb
Host smart-9a857234-fa74-49cc-a4a3-435f014d7bba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658777721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3658777721
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.56906662
Short name T100
Test name
Test status
Simulation time 13511575 ps
CPU time 0.91 seconds
Started Jun 28 06:01:58 PM PDT 24
Finished Jun 28 06:02:09 PM PDT 24
Peak memory 216328 kb
Host smart-f7ef077f-90e1-46cb-b23c-0d419928b877
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56906662 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.56906662
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1709143913
Short name T933
Test name
Test status
Simulation time 68828918 ps
CPU time 1.06 seconds
Started Jun 28 06:01:55 PM PDT 24
Finished Jun 28 06:02:06 PM PDT 24
Peak memory 217072 kb
Host smart-3fe47643-96a1-4bca-a915-e0e0adc81dcb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709143913 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1709143913
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1007674668
Short name T2
Test name
Test status
Simulation time 19573011 ps
CPU time 1.1 seconds
Started Jun 28 06:01:55 PM PDT 24
Finished Jun 28 06:02:05 PM PDT 24
Peak memory 218768 kb
Host smart-a2294bc0-33f7-4014-8458-eba63eb6f9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007674668 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1007674668
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3499183134
Short name T433
Test name
Test status
Simulation time 109657577 ps
CPU time 1.08 seconds
Started Jun 28 06:01:54 PM PDT 24
Finished Jun 28 06:02:03 PM PDT 24
Peak memory 217552 kb
Host smart-4f13111c-b42e-4e80-92c9-759c2306b397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499183134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3499183134
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3270912061
Short name T969
Test name
Test status
Simulation time 91806843 ps
CPU time 0.89 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:02:00 PM PDT 24
Peak memory 215812 kb
Host smart-5a98458e-c517-44ff-bf80-72c33d8203bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270912061 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3270912061
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1275539790
Short name T936
Test name
Test status
Simulation time 33261323 ps
CPU time 0.94 seconds
Started Jun 28 06:01:54 PM PDT 24
Finished Jun 28 06:02:03 PM PDT 24
Peak memory 215600 kb
Host smart-1072b3fb-7a17-4519-8610-184a790171fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275539790 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1275539790
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.976683349
Short name T478
Test name
Test status
Simulation time 990588640 ps
CPU time 3.54 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:05 PM PDT 24
Peak memory 217576 kb
Host smart-7a09f935-1127-47e8-9d6b-66576475d0e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976683349 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.976683349
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.425158829
Short name T511
Test name
Test status
Simulation time 156590605465 ps
CPU time 1078.21 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:20:00 PM PDT 24
Peak memory 224748 kb
Host smart-076bb795-f64d-455a-a078-ee25d46d5010
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425158829 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.425158829
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.276473405
Short name T406
Test name
Test status
Simulation time 174887935 ps
CPU time 2.22 seconds
Started Jun 28 06:03:36 PM PDT 24
Finished Jun 28 06:03:45 PM PDT 24
Peak memory 220656 kb
Host smart-ea8c1004-d415-425a-b1d3-4975e8120bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276473405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.276473405
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.681393134
Short name T467
Test name
Test status
Simulation time 359306691 ps
CPU time 4.85 seconds
Started Jun 28 06:03:42 PM PDT 24
Finished Jun 28 06:03:53 PM PDT 24
Peak memory 219160 kb
Host smart-1639eca9-f910-4fe0-9a3d-56bb2188f659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681393134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.681393134
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3437414035
Short name T104
Test name
Test status
Simulation time 37593059 ps
CPU time 1.11 seconds
Started Jun 28 06:03:45 PM PDT 24
Finished Jun 28 06:03:52 PM PDT 24
Peak memory 217612 kb
Host smart-468d853d-a114-42e6-9640-af620f4b71fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437414035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3437414035
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3411696235
Short name T440
Test name
Test status
Simulation time 38130796 ps
CPU time 1.46 seconds
Started Jun 28 06:03:43 PM PDT 24
Finished Jun 28 06:03:50 PM PDT 24
Peak memory 218860 kb
Host smart-d39a32e6-6116-4d35-9dbf-1d7097f32550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411696235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3411696235
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.4144988444
Short name T16
Test name
Test status
Simulation time 135800848 ps
CPU time 2.92 seconds
Started Jun 28 06:03:48 PM PDT 24
Finished Jun 28 06:03:57 PM PDT 24
Peak memory 219056 kb
Host smart-0adbcf4a-e3e4-4755-88e5-46c36364e44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144988444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.4144988444
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.824819081
Short name T376
Test name
Test status
Simulation time 78727980 ps
CPU time 1.12 seconds
Started Jun 28 06:03:46 PM PDT 24
Finished Jun 28 06:03:53 PM PDT 24
Peak memory 217716 kb
Host smart-5c6fa046-2145-4e38-bd86-389179ed4783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824819081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.824819081
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1396200020
Short name T784
Test name
Test status
Simulation time 202953424 ps
CPU time 2.57 seconds
Started Jun 28 06:03:43 PM PDT 24
Finished Jun 28 06:03:51 PM PDT 24
Peak memory 217756 kb
Host smart-e34a3ad4-5365-4e5c-9c74-7fa6815e1f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396200020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1396200020
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.355405959
Short name T327
Test name
Test status
Simulation time 51103791 ps
CPU time 1.18 seconds
Started Jun 28 06:03:48 PM PDT 24
Finished Jun 28 06:03:56 PM PDT 24
Peak memory 217496 kb
Host smart-eaa9d3b0-547b-4a4a-954a-d72795f7ee78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355405959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.355405959
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2706340769
Short name T73
Test name
Test status
Simulation time 63899680 ps
CPU time 1.33 seconds
Started Jun 28 06:03:47 PM PDT 24
Finished Jun 28 06:03:54 PM PDT 24
Peak memory 217656 kb
Host smart-d031686b-a4ff-400d-9ce6-f442663b17f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706340769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2706340769
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2147824017
Short name T819
Test name
Test status
Simulation time 208663185 ps
CPU time 2.78 seconds
Started Jun 28 06:03:47 PM PDT 24
Finished Jun 28 06:03:57 PM PDT 24
Peak memory 220228 kb
Host smart-e3ef6090-4aba-4fa7-8463-af938555a8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147824017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2147824017
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3331904912
Short name T868
Test name
Test status
Simulation time 44909878 ps
CPU time 1.19 seconds
Started Jun 28 06:02:00 PM PDT 24
Finished Jun 28 06:02:11 PM PDT 24
Peak memory 218984 kb
Host smart-6bef288c-af53-4d5b-a8b4-1240ef7ffe3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331904912 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3331904912
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.350429868
Short name T417
Test name
Test status
Simulation time 25033523 ps
CPU time 0.89 seconds
Started Jun 28 06:02:00 PM PDT 24
Finished Jun 28 06:02:10 PM PDT 24
Peak memory 206988 kb
Host smart-e556a73d-88f1-4341-b73d-e12857e32424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350429868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.350429868
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3999478682
Short name T988
Test name
Test status
Simulation time 23644515 ps
CPU time 0.84 seconds
Started Jun 28 06:01:50 PM PDT 24
Finished Jun 28 06:01:56 PM PDT 24
Peak memory 216256 kb
Host smart-0cad4f76-c5ca-4440-b354-fb932d04c7d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999478682 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3999478682
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3357250337
Short name T150
Test name
Test status
Simulation time 35481398 ps
CPU time 1.21 seconds
Started Jun 28 06:02:00 PM PDT 24
Finished Jun 28 06:02:11 PM PDT 24
Peak memory 218940 kb
Host smart-8c145c4b-05af-4f32-b625-1366d01c0247
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357250337 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3357250337
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.749172106
Short name T123
Test name
Test status
Simulation time 25678980 ps
CPU time 0.98 seconds
Started Jun 28 06:02:18 PM PDT 24
Finished Jun 28 06:02:26 PM PDT 24
Peak memory 219836 kb
Host smart-111a8546-1c0d-40d4-86ca-1807b23a83f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749172106 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.749172106
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2274751221
Short name T665
Test name
Test status
Simulation time 72360750 ps
CPU time 2.56 seconds
Started Jun 28 06:01:56 PM PDT 24
Finished Jun 28 06:02:08 PM PDT 24
Peak memory 220424 kb
Host smart-d8ea4876-036c-41a9-b24e-0c3898f86d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274751221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2274751221
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3808279786
Short name T116
Test name
Test status
Simulation time 24890077 ps
CPU time 0.91 seconds
Started Jun 28 06:01:58 PM PDT 24
Finished Jun 28 06:02:08 PM PDT 24
Peak memory 216080 kb
Host smart-8e15209c-684d-432e-b3d7-0f32f14ccfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808279786 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3808279786
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2777473491
Short name T580
Test name
Test status
Simulation time 47687614 ps
CPU time 0.96 seconds
Started Jun 28 06:01:58 PM PDT 24
Finished Jun 28 06:02:11 PM PDT 24
Peak memory 215592 kb
Host smart-14887955-ef29-47f8-b897-5dba40740fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777473491 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2777473491
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.238788881
Short name T463
Test name
Test status
Simulation time 255514725 ps
CPU time 5.01 seconds
Started Jun 28 06:02:03 PM PDT 24
Finished Jun 28 06:02:18 PM PDT 24
Peak memory 219036 kb
Host smart-1a52ba09-80d0-48ec-a41a-4aad658610bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238788881 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.238788881
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3192125919
Short name T238
Test name
Test status
Simulation time 118660661674 ps
CPU time 776.44 seconds
Started Jun 28 06:02:00 PM PDT 24
Finished Jun 28 06:15:07 PM PDT 24
Peak memory 221540 kb
Host smart-2cca4e5c-bf7f-4ed1-b395-eb30da0562e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192125919 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3192125919
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.522437684
Short name T525
Test name
Test status
Simulation time 71420014 ps
CPU time 2.49 seconds
Started Jun 28 06:04:04 PM PDT 24
Finished Jun 28 06:04:11 PM PDT 24
Peak memory 215604 kb
Host smart-f046667a-a30f-4f22-aa48-656b07dcc2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522437684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.522437684
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2028528461
Short name T769
Test name
Test status
Simulation time 39788714 ps
CPU time 1.6 seconds
Started Jun 28 06:03:43 PM PDT 24
Finished Jun 28 06:03:51 PM PDT 24
Peak memory 218932 kb
Host smart-6bb5745d-8c3c-465f-b055-b965196ed447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028528461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2028528461
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.92490602
Short name T413
Test name
Test status
Simulation time 55502846 ps
CPU time 1.11 seconds
Started Jun 28 06:03:43 PM PDT 24
Finished Jun 28 06:03:50 PM PDT 24
Peak memory 219364 kb
Host smart-43eec0f1-ce44-4799-a29e-9de0db9f8d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92490602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.92490602
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3856076314
Short name T557
Test name
Test status
Simulation time 73461626 ps
CPU time 1.37 seconds
Started Jun 28 06:03:43 PM PDT 24
Finished Jun 28 06:03:50 PM PDT 24
Peak memory 217564 kb
Host smart-94ec1383-7876-49fe-8b13-e2b86bb131a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856076314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3856076314
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.491653639
Short name T746
Test name
Test status
Simulation time 287295102 ps
CPU time 1.56 seconds
Started Jun 28 06:03:47 PM PDT 24
Finished Jun 28 06:03:55 PM PDT 24
Peak memory 220644 kb
Host smart-ed494457-5b53-4954-b268-9d2c75430c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491653639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.491653639
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3200896259
Short name T684
Test name
Test status
Simulation time 37519472 ps
CPU time 1.16 seconds
Started Jun 28 06:03:48 PM PDT 24
Finished Jun 28 06:03:56 PM PDT 24
Peak memory 218892 kb
Host smart-8e688811-f03b-4ec9-8d4b-85467d70c7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200896259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3200896259
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2830052406
Short name T794
Test name
Test status
Simulation time 110424507 ps
CPU time 1.26 seconds
Started Jun 28 06:03:43 PM PDT 24
Finished Jun 28 06:03:50 PM PDT 24
Peak memory 218756 kb
Host smart-0b597962-6655-4af5-bae8-ad8608394763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830052406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2830052406
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1570615714
Short name T985
Test name
Test status
Simulation time 38409897 ps
CPU time 1.45 seconds
Started Jun 28 06:03:36 PM PDT 24
Finished Jun 28 06:03:44 PM PDT 24
Peak memory 217892 kb
Host smart-9c1240b7-9197-471c-8f4c-389a4b6c6cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570615714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1570615714
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.4248768364
Short name T965
Test name
Test status
Simulation time 75684336 ps
CPU time 1.27 seconds
Started Jun 28 06:03:47 PM PDT 24
Finished Jun 28 06:03:55 PM PDT 24
Peak memory 217736 kb
Host smart-71cbafbd-2414-488b-bb54-506be9bba720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248768364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.4248768364
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1270609342
Short name T683
Test name
Test status
Simulation time 34292688 ps
CPU time 1.19 seconds
Started Jun 28 06:03:42 PM PDT 24
Finished Jun 28 06:03:48 PM PDT 24
Peak memory 217696 kb
Host smart-729bef9a-acaa-42c8-996a-43431e6fc377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270609342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1270609342
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.179938578
Short name T651
Test name
Test status
Simulation time 22608985 ps
CPU time 1.11 seconds
Started Jun 28 06:02:00 PM PDT 24
Finished Jun 28 06:02:11 PM PDT 24
Peak memory 218888 kb
Host smart-93fa429f-e0ee-4a7d-8aab-ff2336260537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179938578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.179938578
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2821587812
Short name T421
Test name
Test status
Simulation time 39328865 ps
CPU time 0.84 seconds
Started Jun 28 06:02:21 PM PDT 24
Finished Jun 28 06:02:27 PM PDT 24
Peak memory 207032 kb
Host smart-12987cf2-02bd-4aca-b5a8-548befe49366
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821587812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2821587812
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3553606475
Short name T951
Test name
Test status
Simulation time 35565646 ps
CPU time 0.84 seconds
Started Jun 28 06:01:59 PM PDT 24
Finished Jun 28 06:02:09 PM PDT 24
Peak memory 216528 kb
Host smart-e9ae7519-a64f-41de-ab7d-777b4d6e995c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553606475 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3553606475
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3634907129
Short name T211
Test name
Test status
Simulation time 118322262 ps
CPU time 1.14 seconds
Started Jun 28 06:02:04 PM PDT 24
Finished Jun 28 06:02:14 PM PDT 24
Peak memory 219752 kb
Host smart-f9738190-ac4f-4953-aa2e-96c55d9446a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634907129 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3634907129
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.510853378
Short name T172
Test name
Test status
Simulation time 34915006 ps
CPU time 1.02 seconds
Started Jun 28 06:02:09 PM PDT 24
Finished Jun 28 06:02:19 PM PDT 24
Peak memory 224048 kb
Host smart-e7940313-f415-4b50-a550-b21bf8d036a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510853378 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.510853378
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.596296823
Short name T757
Test name
Test status
Simulation time 37710460 ps
CPU time 1.34 seconds
Started Jun 28 06:01:51 PM PDT 24
Finished Jun 28 06:01:59 PM PDT 24
Peak memory 218812 kb
Host smart-0643df32-fea3-4918-9765-b9c4402bca54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596296823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.596296823
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2588247948
Short name T788
Test name
Test status
Simulation time 36962671 ps
CPU time 0.88 seconds
Started Jun 28 06:01:55 PM PDT 24
Finished Jun 28 06:02:05 PM PDT 24
Peak memory 215776 kb
Host smart-4ac88d6f-fd82-4648-91e0-19e5ec369bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588247948 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2588247948
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2192518929
Short name T476
Test name
Test status
Simulation time 45749810 ps
CPU time 0.91 seconds
Started Jun 28 06:01:52 PM PDT 24
Finished Jun 28 06:02:00 PM PDT 24
Peak memory 207628 kb
Host smart-2e545d14-6b37-45cf-a23e-0647d74ce2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192518929 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2192518929
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.4013287771
Short name T565
Test name
Test status
Simulation time 183232969 ps
CPU time 3.68 seconds
Started Jun 28 06:01:59 PM PDT 24
Finished Jun 28 06:02:12 PM PDT 24
Peak memory 218724 kb
Host smart-90276c91-6b5d-48fb-91bf-50394402177c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013287771 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.4013287771
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1120800247
Short name T943
Test name
Test status
Simulation time 45090151811 ps
CPU time 509.55 seconds
Started Jun 28 06:02:00 PM PDT 24
Finished Jun 28 06:10:40 PM PDT 24
Peak memory 218736 kb
Host smart-7fb82d38-8b05-448a-9033-6581b4600787
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120800247 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1120800247
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.78593733
Short name T350
Test name
Test status
Simulation time 41079282 ps
CPU time 1.39 seconds
Started Jun 28 06:03:57 PM PDT 24
Finished Jun 28 06:04:00 PM PDT 24
Peak memory 220364 kb
Host smart-394ff39c-9058-46df-b693-dee745167dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78593733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.78593733
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.964945863
Short name T719
Test name
Test status
Simulation time 289028388 ps
CPU time 1.19 seconds
Started Jun 28 06:03:47 PM PDT 24
Finished Jun 28 06:03:55 PM PDT 24
Peak memory 217680 kb
Host smart-7107dab0-1e3a-4988-b271-2130fdb2de87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964945863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.964945863
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1950126442
Short name T820
Test name
Test status
Simulation time 80753265 ps
CPU time 1.55 seconds
Started Jun 28 06:03:44 PM PDT 24
Finished Jun 28 06:03:52 PM PDT 24
Peak memory 219356 kb
Host smart-d8ec6e03-b45b-455a-9e1f-09c61ea6672f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950126442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1950126442
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3644946434
Short name T805
Test name
Test status
Simulation time 35436762 ps
CPU time 1.31 seconds
Started Jun 28 06:03:47 PM PDT 24
Finished Jun 28 06:03:55 PM PDT 24
Peak memory 217576 kb
Host smart-0a1dbd2f-c00c-41d4-b8db-9b95828a636e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644946434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3644946434
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.439716499
Short name T44
Test name
Test status
Simulation time 42292334 ps
CPU time 1.48 seconds
Started Jun 28 06:03:38 PM PDT 24
Finished Jun 28 06:03:46 PM PDT 24
Peak memory 220272 kb
Host smart-061c626c-2b95-4aa8-90a3-7b3927f542a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439716499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.439716499
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.335863244
Short name T503
Test name
Test status
Simulation time 32699926 ps
CPU time 1.52 seconds
Started Jun 28 06:03:43 PM PDT 24
Finished Jun 28 06:03:50 PM PDT 24
Peak memory 218948 kb
Host smart-c372ab50-7087-47ea-90bc-4adcdb13cfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335863244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.335863244
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.4239432833
Short name T428
Test name
Test status
Simulation time 110719040 ps
CPU time 1.58 seconds
Started Jun 28 06:03:46 PM PDT 24
Finished Jun 28 06:03:53 PM PDT 24
Peak memory 219224 kb
Host smart-5403ef6b-21fc-4efa-be76-4bf6f0438a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239432833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.4239432833
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.90639804
Short name T705
Test name
Test status
Simulation time 27316111 ps
CPU time 1.29 seconds
Started Jun 28 06:03:46 PM PDT 24
Finished Jun 28 06:03:54 PM PDT 24
Peak memory 217728 kb
Host smart-f6a9f18b-f6ba-4394-a7a9-a89c5a8aecba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90639804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.90639804
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.4067980340
Short name T846
Test name
Test status
Simulation time 95737707 ps
CPU time 1.6 seconds
Started Jun 28 06:03:45 PM PDT 24
Finished Jun 28 06:03:53 PM PDT 24
Peak memory 220672 kb
Host smart-67ac11fb-e4d1-4447-bc32-431fa6edd558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067980340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.4067980340
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3386440665
Short name T249
Test name
Test status
Simulation time 47301716 ps
CPU time 1.2 seconds
Started Jun 28 06:03:43 PM PDT 24
Finished Jun 28 06:03:50 PM PDT 24
Peak memory 217744 kb
Host smart-6ddfb4f0-e4a8-4058-8920-fd713de2be39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386440665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3386440665
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.235447285
Short name T217
Test name
Test status
Simulation time 45369804 ps
CPU time 1.16 seconds
Started Jun 28 06:02:04 PM PDT 24
Finished Jun 28 06:02:14 PM PDT 24
Peak memory 220048 kb
Host smart-69f8d17c-b2c7-429f-bbb1-3bc63cc565b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235447285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.235447285
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.242313590
Short name T382
Test name
Test status
Simulation time 23511213 ps
CPU time 0.89 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:03 PM PDT 24
Peak memory 207032 kb
Host smart-7669d511-a3a5-475a-abb9-be15ee7d7985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242313590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.242313590
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2007801005
Short name T927
Test name
Test status
Simulation time 63208238 ps
CPU time 1.21 seconds
Started Jun 28 06:02:06 PM PDT 24
Finished Jun 28 06:02:16 PM PDT 24
Peak memory 217268 kb
Host smart-0d16c701-1125-4eae-a90a-aeffad196fe8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007801005 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2007801005
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1769025296
Short name T512
Test name
Test status
Simulation time 33678990 ps
CPU time 0.87 seconds
Started Jun 28 06:02:04 PM PDT 24
Finished Jun 28 06:02:14 PM PDT 24
Peak memory 218496 kb
Host smart-095953e9-072c-4563-b10d-01e36f3910c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769025296 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1769025296
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3448632754
Short name T15
Test name
Test status
Simulation time 39574365 ps
CPU time 1.23 seconds
Started Jun 28 06:01:51 PM PDT 24
Finished Jun 28 06:01:58 PM PDT 24
Peak memory 220048 kb
Host smart-00f44776-76ca-4083-a0da-fb9eff3117eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448632754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3448632754
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.186710236
Short name T88
Test name
Test status
Simulation time 26388677 ps
CPU time 0.92 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:02:00 PM PDT 24
Peak memory 216156 kb
Host smart-0fbab0cf-fb71-4edc-8ac9-9ad18b456527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186710236 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.186710236
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.526641944
Short name T502
Test name
Test status
Simulation time 18685263 ps
CPU time 0.89 seconds
Started Jun 28 06:01:49 PM PDT 24
Finished Jun 28 06:01:55 PM PDT 24
Peak memory 215616 kb
Host smart-cb9c2ac6-0f69-438a-b72c-91e4cd0a1ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526641944 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.526641944
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.4009822289
Short name T765
Test name
Test status
Simulation time 1998088471 ps
CPU time 4.61 seconds
Started Jun 28 06:01:50 PM PDT 24
Finished Jun 28 06:02:00 PM PDT 24
Peak memory 215668 kb
Host smart-57dddb53-7cb7-45a0-b83e-127ba0a65217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009822289 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.4009822289
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3298425338
Short name T505
Test name
Test status
Simulation time 103056286152 ps
CPU time 1510.24 seconds
Started Jun 28 06:01:53 PM PDT 24
Finished Jun 28 06:27:12 PM PDT 24
Peak memory 225064 kb
Host smart-bbc1e329-a5e9-4baf-b41d-54ae079d3a9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298425338 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3298425338
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2032601980
Short name T926
Test name
Test status
Simulation time 103898787 ps
CPU time 1.17 seconds
Started Jun 28 06:03:42 PM PDT 24
Finished Jun 28 06:03:48 PM PDT 24
Peak memory 219416 kb
Host smart-8e5d25d2-e331-4f69-807c-b65d3b0c8598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032601980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2032601980
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2969628741
Short name T673
Test name
Test status
Simulation time 44244572 ps
CPU time 1.58 seconds
Started Jun 28 06:03:42 PM PDT 24
Finished Jun 28 06:03:49 PM PDT 24
Peak memory 218880 kb
Host smart-d3c0d545-11bc-4786-980c-723250806672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969628741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2969628741
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2038934696
Short name T978
Test name
Test status
Simulation time 57334661 ps
CPU time 1.28 seconds
Started Jun 28 06:03:46 PM PDT 24
Finished Jun 28 06:03:53 PM PDT 24
Peak memory 217556 kb
Host smart-321daed6-8d63-4dd0-8f61-7fda35fe8f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038934696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2038934696
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2249707739
Short name T600
Test name
Test status
Simulation time 186352168 ps
CPU time 1.44 seconds
Started Jun 28 06:03:46 PM PDT 24
Finished Jun 28 06:03:54 PM PDT 24
Peak memory 217628 kb
Host smart-e1fa0242-34d0-4587-a3bd-e7dd697d5c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249707739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2249707739
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.921881505
Short name T758
Test name
Test status
Simulation time 46924290 ps
CPU time 1.26 seconds
Started Jun 28 06:03:45 PM PDT 24
Finished Jun 28 06:03:53 PM PDT 24
Peak memory 218744 kb
Host smart-721a495f-ac38-4ed4-9a8a-611db501acc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921881505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.921881505
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1814249392
Short name T334
Test name
Test status
Simulation time 38604927 ps
CPU time 1.48 seconds
Started Jun 28 06:03:43 PM PDT 24
Finished Jun 28 06:03:49 PM PDT 24
Peak memory 218912 kb
Host smart-da40b57b-3f5f-4922-b678-596e2c4d58cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814249392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1814249392
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3332492
Short name T900
Test name
Test status
Simulation time 31119357 ps
CPU time 1.11 seconds
Started Jun 28 06:03:47 PM PDT 24
Finished Jun 28 06:03:55 PM PDT 24
Peak memory 220204 kb
Host smart-16e6a71f-23ed-49f4-a5f5-76801f7cdc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3332492
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2011502247
Short name T609
Test name
Test status
Simulation time 64683767 ps
CPU time 1.64 seconds
Started Jun 28 06:03:43 PM PDT 24
Finished Jun 28 06:03:51 PM PDT 24
Peak memory 219072 kb
Host smart-a45cd8d6-3d22-4fb4-a1cd-a8138774c0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011502247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2011502247
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.1967006514
Short name T431
Test name
Test status
Simulation time 28844254 ps
CPU time 1.37 seconds
Started Jun 28 06:03:46 PM PDT 24
Finished Jun 28 06:03:54 PM PDT 24
Peak memory 217760 kb
Host smart-76c1dd4b-9a16-4d70-aabd-1558d323b5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967006514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1967006514
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2569226575
Short name T715
Test name
Test status
Simulation time 140186692 ps
CPU time 1.37 seconds
Started Jun 28 06:03:48 PM PDT 24
Finished Jun 28 06:03:56 PM PDT 24
Peak memory 217764 kb
Host smart-02774f1d-e403-445d-9c02-9339bffde6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569226575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2569226575
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2616566958
Short name T151
Test name
Test status
Simulation time 70516929 ps
CPU time 1.11 seconds
Started Jun 28 06:02:04 PM PDT 24
Finished Jun 28 06:02:14 PM PDT 24
Peak memory 220084 kb
Host smart-562c775f-e516-43ab-a706-842b6d487379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616566958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2616566958
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.519287987
Short name T227
Test name
Test status
Simulation time 15956110 ps
CPU time 0.92 seconds
Started Jun 28 06:02:16 PM PDT 24
Finished Jun 28 06:02:24 PM PDT 24
Peak memory 215128 kb
Host smart-e19f3e19-8d42-405a-aa68-7caa9e58248a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519287987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.519287987
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.4110696034
Short name T210
Test name
Test status
Simulation time 11104628 ps
CPU time 0.87 seconds
Started Jun 28 06:02:04 PM PDT 24
Finished Jun 28 06:02:14 PM PDT 24
Peak memory 216624 kb
Host smart-2c026e7e-5624-4153-921d-05b19327d9d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110696034 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.4110696034
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.4232656074
Short name T829
Test name
Test status
Simulation time 203801374 ps
CPU time 1.08 seconds
Started Jun 28 06:02:13 PM PDT 24
Finished Jun 28 06:02:21 PM PDT 24
Peak memory 218716 kb
Host smart-5afdcf0d-1d42-4a56-af92-39a5b85252f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232656074 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.4232656074
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3676551145
Short name T588
Test name
Test status
Simulation time 40005037 ps
CPU time 1.19 seconds
Started Jun 28 06:02:14 PM PDT 24
Finished Jun 28 06:02:22 PM PDT 24
Peak memory 219832 kb
Host smart-a1991774-115f-4e06-bace-80bfd64d9a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676551145 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3676551145
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3056478495
Short name T414
Test name
Test status
Simulation time 47794761 ps
CPU time 1.56 seconds
Started Jun 28 06:02:01 PM PDT 24
Finished Jun 28 06:02:12 PM PDT 24
Peak memory 218616 kb
Host smart-3e978141-5665-448b-8a58-fa8cf3032ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056478495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3056478495
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.1639475734
Short name T448
Test name
Test status
Simulation time 29694654 ps
CPU time 0.97 seconds
Started Jun 28 06:02:32 PM PDT 24
Finished Jun 28 06:02:39 PM PDT 24
Peak memory 224124 kb
Host smart-daa9ff86-d216-4dde-8c37-358c2caa1c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639475734 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1639475734
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1406430378
Short name T432
Test name
Test status
Simulation time 44093752 ps
CPU time 0.95 seconds
Started Jun 28 06:02:11 PM PDT 24
Finished Jun 28 06:02:20 PM PDT 24
Peak memory 215620 kb
Host smart-64c1c658-89fd-4079-a97b-3e7132a08b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406430378 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1406430378
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1863404341
Short name T339
Test name
Test status
Simulation time 82901682 ps
CPU time 1.46 seconds
Started Jun 28 06:02:09 PM PDT 24
Finished Jun 28 06:02:19 PM PDT 24
Peak memory 217436 kb
Host smart-41dc00c0-ed3f-4348-8d03-1163e22ee193
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863404341 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1863404341
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1600488936
Short name T862
Test name
Test status
Simulation time 147091411596 ps
CPU time 956.61 seconds
Started Jun 28 06:02:09 PM PDT 24
Finished Jun 28 06:18:14 PM PDT 24
Peak memory 224136 kb
Host smart-66b2db87-c226-41f2-a021-bcd7a88a5d2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600488936 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1600488936
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2543152293
Short name T520
Test name
Test status
Simulation time 51484738 ps
CPU time 1.3 seconds
Started Jun 28 06:03:42 PM PDT 24
Finished Jun 28 06:03:49 PM PDT 24
Peak memory 218892 kb
Host smart-8c33dcf6-d903-41df-b448-f6ca660546a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543152293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2543152293
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1881763012
Short name T815
Test name
Test status
Simulation time 54995530 ps
CPU time 1.4 seconds
Started Jun 28 06:03:43 PM PDT 24
Finished Jun 28 06:03:50 PM PDT 24
Peak memory 217624 kb
Host smart-fd9b9f89-1140-4038-b58d-fc72b3b9ab55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881763012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1881763012
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2658354596
Short name T103
Test name
Test status
Simulation time 60738367 ps
CPU time 1.61 seconds
Started Jun 28 06:03:38 PM PDT 24
Finished Jun 28 06:03:47 PM PDT 24
Peak memory 217704 kb
Host smart-2f72bbf2-27ce-4612-9039-dbe8c526182d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658354596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2658354596
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2712714341
Short name T817
Test name
Test status
Simulation time 27384784 ps
CPU time 1.15 seconds
Started Jun 28 06:03:43 PM PDT 24
Finished Jun 28 06:03:50 PM PDT 24
Peak memory 218772 kb
Host smart-411102e6-00b0-4333-830c-8e36ed6c356a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712714341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2712714341
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.2293790585
Short name T587
Test name
Test status
Simulation time 121739378 ps
CPU time 2.96 seconds
Started Jun 28 06:03:40 PM PDT 24
Finished Jun 28 06:03:49 PM PDT 24
Peak memory 218928 kb
Host smart-6850ee5a-5197-4c7a-b735-2c18f4ed90ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293790585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2293790585
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3406705617
Short name T262
Test name
Test status
Simulation time 69355674 ps
CPU time 1.21 seconds
Started Jun 28 06:03:47 PM PDT 24
Finished Jun 28 06:03:54 PM PDT 24
Peak memory 220104 kb
Host smart-656339ed-fb82-4d25-9a9a-ea69e14cc9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406705617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3406705617
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2476897442
Short name T671
Test name
Test status
Simulation time 42272749 ps
CPU time 1.47 seconds
Started Jun 28 06:03:42 PM PDT 24
Finished Jun 28 06:03:49 PM PDT 24
Peak memory 218708 kb
Host smart-2fc6c2bf-b53c-42ac-b972-962da6b342ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476897442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2476897442
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3972136039
Short name T322
Test name
Test status
Simulation time 31994465 ps
CPU time 1.36 seconds
Started Jun 28 06:03:43 PM PDT 24
Finished Jun 28 06:03:50 PM PDT 24
Peak memory 219840 kb
Host smart-7ab2c964-51fe-47bb-8dfe-14d63fb4f36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972136039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3972136039
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2583936099
Short name T10
Test name
Test status
Simulation time 202793645 ps
CPU time 1.37 seconds
Started Jun 28 06:03:42 PM PDT 24
Finished Jun 28 06:03:49 PM PDT 24
Peak memory 219804 kb
Host smart-4cc83382-e5e5-4ced-9fae-a653e2b7a5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583936099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2583936099
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1044114902
Short name T818
Test name
Test status
Simulation time 60568065 ps
CPU time 1.15 seconds
Started Jun 28 06:03:48 PM PDT 24
Finished Jun 28 06:03:56 PM PDT 24
Peak memory 220252 kb
Host smart-39651d87-d0c6-4d16-8e51-457db1bbeca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044114902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1044114902
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2470015723
Short name T960
Test name
Test status
Simulation time 42100587 ps
CPU time 1.18 seconds
Started Jun 28 06:01:36 PM PDT 24
Finished Jun 28 06:01:40 PM PDT 24
Peak memory 218876 kb
Host smart-1bec3782-64f6-4956-863a-a1dcf21ab3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470015723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2470015723
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3357601558
Short name T615
Test name
Test status
Simulation time 64278583 ps
CPU time 0.85 seconds
Started Jun 28 06:01:38 PM PDT 24
Finished Jun 28 06:01:43 PM PDT 24
Peak memory 207076 kb
Host smart-b67fbe8d-ac78-4dc6-b8f2-6a33eeb1e169
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357601558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3357601558
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1814342882
Short name T907
Test name
Test status
Simulation time 36061889 ps
CPU time 0.87 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:45 PM PDT 24
Peak memory 216260 kb
Host smart-a4de436f-12ad-4ed8-8cb3-87d32ca1a810
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814342882 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1814342882
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3988968811
Short name T510
Test name
Test status
Simulation time 80513242 ps
CPU time 1.13 seconds
Started Jun 28 06:01:38 PM PDT 24
Finished Jun 28 06:01:43 PM PDT 24
Peak memory 218900 kb
Host smart-f5c7cb1f-d561-4ddd-81eb-6ad0b78cac30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988968811 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3988968811
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2343026887
Short name T132
Test name
Test status
Simulation time 76791507 ps
CPU time 1.04 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:45 PM PDT 24
Peak memory 221040 kb
Host smart-e38f99bc-e1e3-4083-8be6-076fb77ed163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343026887 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2343026887
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1982008203
Short name T48
Test name
Test status
Simulation time 40601430 ps
CPU time 1.41 seconds
Started Jun 28 06:01:36 PM PDT 24
Finished Jun 28 06:01:40 PM PDT 24
Peak memory 217732 kb
Host smart-76314658-5b3a-4555-ae4f-6f668280f9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982008203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1982008203
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1735555715
Short name T28
Test name
Test status
Simulation time 21276831 ps
CPU time 1.11 seconds
Started Jun 28 06:01:34 PM PDT 24
Finished Jun 28 06:01:37 PM PDT 24
Peak memory 216076 kb
Host smart-c9feb83b-2305-4d71-9dd9-28baad87475d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735555715 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1735555715
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.510018861
Short name T23
Test name
Test status
Simulation time 17175789 ps
CPU time 1.04 seconds
Started Jun 28 06:01:37 PM PDT 24
Finished Jun 28 06:01:41 PM PDT 24
Peak memory 207408 kb
Host smart-b74af712-0d08-45be-bf35-095909e3f7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510018861 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.510018861
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1485263164
Short name T64
Test name
Test status
Simulation time 507142204 ps
CPU time 8.3 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:54 PM PDT 24
Peak memory 236372 kb
Host smart-da9dcaab-4c5a-42fa-9cb2-c142b388c7fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485263164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1485263164
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.1993103935
Short name T803
Test name
Test status
Simulation time 18830513 ps
CPU time 1.03 seconds
Started Jun 28 06:01:38 PM PDT 24
Finished Jun 28 06:01:44 PM PDT 24
Peak memory 215612 kb
Host smart-de9d2e83-787f-42f4-aa45-be2f423c9b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993103935 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1993103935
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.732263857
Short name T240
Test name
Test status
Simulation time 258583981 ps
CPU time 4.94 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:50 PM PDT 24
Peak memory 215588 kb
Host smart-78912efa-3c67-4c85-b786-e7b3799ea140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732263857 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.732263857
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3645529966
Short name T222
Test name
Test status
Simulation time 5832168340 ps
CPU time 138.27 seconds
Started Jun 28 06:01:34 PM PDT 24
Finished Jun 28 06:03:54 PM PDT 24
Peak memory 218824 kb
Host smart-e644fa13-5013-436b-a564-3107f480fa69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645529966 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3645529966
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.392701951
Short name T80
Test name
Test status
Simulation time 71954435 ps
CPU time 1.14 seconds
Started Jun 28 06:02:04 PM PDT 24
Finished Jun 28 06:02:14 PM PDT 24
Peak memory 219444 kb
Host smart-36839a58-5d37-482b-856e-d8e82284d40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392701951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.392701951
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2928712381
Short name T887
Test name
Test status
Simulation time 15372564 ps
CPU time 0.96 seconds
Started Jun 28 06:02:14 PM PDT 24
Finished Jun 28 06:02:22 PM PDT 24
Peak memory 207084 kb
Host smart-040167d7-f867-4fbe-8027-9a7d944513dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928712381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2928712381
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.554771994
Short name T176
Test name
Test status
Simulation time 13667109 ps
CPU time 0.91 seconds
Started Jun 28 06:02:24 PM PDT 24
Finished Jun 28 06:02:30 PM PDT 24
Peak memory 216680 kb
Host smart-f24e5a37-2de8-4717-96de-7619592d10e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554771994 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.554771994
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_err.1796399498
Short name T146
Test name
Test status
Simulation time 47454480 ps
CPU time 1.04 seconds
Started Jun 28 06:02:03 PM PDT 24
Finished Jun 28 06:02:13 PM PDT 24
Peak memory 229876 kb
Host smart-f6eb852a-49d9-49a2-8548-72044f60881d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796399498 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1796399498
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1075851423
Short name T449
Test name
Test status
Simulation time 61480375 ps
CPU time 1.37 seconds
Started Jun 28 06:02:02 PM PDT 24
Finished Jun 28 06:02:12 PM PDT 24
Peak memory 217656 kb
Host smart-fe9a0d72-fc2f-4225-932e-e71edba3b450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075851423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1075851423
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3420967010
Short name T493
Test name
Test status
Simulation time 23152585 ps
CPU time 1.15 seconds
Started Jun 28 06:02:16 PM PDT 24
Finished Jun 28 06:02:24 PM PDT 24
Peak memory 215728 kb
Host smart-78fc68dc-c401-4672-82db-628abde5a42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420967010 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3420967010
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.53392119
Short name T582
Test name
Test status
Simulation time 66496131 ps
CPU time 0.99 seconds
Started Jun 28 06:02:25 PM PDT 24
Finished Jun 28 06:02:31 PM PDT 24
Peak memory 215600 kb
Host smart-c02efa34-8841-4fdd-9ff6-440f085f533e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53392119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.53392119
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.4064012074
Short name T890
Test name
Test status
Simulation time 1613903309 ps
CPU time 2.29 seconds
Started Jun 28 06:02:25 PM PDT 24
Finished Jun 28 06:02:32 PM PDT 24
Peak memory 217468 kb
Host smart-5589311e-23de-4e48-8c1b-e90a96de66f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064012074 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.4064012074
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.534736437
Short name T221
Test name
Test status
Simulation time 158384603113 ps
CPU time 1022.99 seconds
Started Jun 28 06:02:21 PM PDT 24
Finished Jun 28 06:19:30 PM PDT 24
Peak memory 224016 kb
Host smart-f3745d74-caec-4b91-a950-565d374421f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534736437 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.534736437
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3465628524
Short name T707
Test name
Test status
Simulation time 24159337 ps
CPU time 1.16 seconds
Started Jun 28 06:02:32 PM PDT 24
Finished Jun 28 06:02:38 PM PDT 24
Peak memory 219832 kb
Host smart-4a0d1930-33c3-474f-be24-94fca90e394c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465628524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3465628524
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2422715403
Short name T983
Test name
Test status
Simulation time 35281411 ps
CPU time 1.01 seconds
Started Jun 28 06:02:08 PM PDT 24
Finished Jun 28 06:02:18 PM PDT 24
Peak memory 215260 kb
Host smart-ff923025-680c-447d-ad10-cdf0e9e32885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422715403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2422715403
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.1658439824
Short name T177
Test name
Test status
Simulation time 10826152 ps
CPU time 0.85 seconds
Started Jun 28 06:02:02 PM PDT 24
Finished Jun 28 06:02:15 PM PDT 24
Peak memory 216644 kb
Host smart-f5407509-0f9b-4dab-918a-d8f1509c7c4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658439824 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1658439824
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1200352063
Short name T955
Test name
Test status
Simulation time 45659133 ps
CPU time 1.06 seconds
Started Jun 28 06:02:23 PM PDT 24
Finished Jun 28 06:02:29 PM PDT 24
Peak memory 218672 kb
Host smart-a34691ee-d7a8-401f-96a2-86eb0083e50e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200352063 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1200352063
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2715016778
Short name T205
Test name
Test status
Simulation time 22493171 ps
CPU time 1.09 seconds
Started Jun 28 06:02:16 PM PDT 24
Finished Jun 28 06:02:24 PM PDT 24
Peak memory 220160 kb
Host smart-2aecbdba-7831-4cc2-8b9e-9ea131d301c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715016778 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2715016778
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2787623928
Short name T349
Test name
Test status
Simulation time 52785510 ps
CPU time 1.42 seconds
Started Jun 28 06:02:17 PM PDT 24
Finished Jun 28 06:02:25 PM PDT 24
Peak memory 219128 kb
Host smart-c5958fbe-5281-4577-a953-2527e5469849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787623928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2787623928
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.491604384
Short name T801
Test name
Test status
Simulation time 23218251 ps
CPU time 0.96 seconds
Started Jun 28 06:02:14 PM PDT 24
Finished Jun 28 06:02:22 PM PDT 24
Peak memory 216124 kb
Host smart-5edcefc0-c30f-4f8e-81de-07d857d080bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491604384 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.491604384
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1086623769
Short name T732
Test name
Test status
Simulation time 18393850 ps
CPU time 1.01 seconds
Started Jun 28 06:02:17 PM PDT 24
Finished Jun 28 06:02:25 PM PDT 24
Peak memory 215572 kb
Host smart-122eb0b2-7b25-4ad0-a26d-e0c827b499e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086623769 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1086623769
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.2223679151
Short name T590
Test name
Test status
Simulation time 468244345 ps
CPU time 3.17 seconds
Started Jun 28 06:02:08 PM PDT 24
Finished Jun 28 06:02:20 PM PDT 24
Peak memory 220496 kb
Host smart-2c3935aa-8ced-475e-aa99-ca29d37d3786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223679151 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2223679151
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1699419307
Short name T412
Test name
Test status
Simulation time 215547395483 ps
CPU time 423.19 seconds
Started Jun 28 06:02:12 PM PDT 24
Finished Jun 28 06:09:22 PM PDT 24
Peak memory 219504 kb
Host smart-dc68f8d2-f738-477a-bbfe-35f95635648f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699419307 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1699419307
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.782303867
Short name T535
Test name
Test status
Simulation time 43745430 ps
CPU time 1.19 seconds
Started Jun 28 06:02:24 PM PDT 24
Finished Jun 28 06:02:30 PM PDT 24
Peak memory 219976 kb
Host smart-9700ce35-7c86-404e-a9ef-22bc355601ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782303867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.782303867
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3628442089
Short name T460
Test name
Test status
Simulation time 13616932 ps
CPU time 0.9 seconds
Started Jun 28 06:02:14 PM PDT 24
Finished Jun 28 06:02:22 PM PDT 24
Peak memory 215188 kb
Host smart-8d1231e1-8d99-4254-89f7-e9a0b16b5bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628442089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3628442089
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2490840874
Short name T867
Test name
Test status
Simulation time 21601197 ps
CPU time 1.03 seconds
Started Jun 28 06:02:17 PM PDT 24
Finished Jun 28 06:02:25 PM PDT 24
Peak memory 218644 kb
Host smart-084e4b6b-a039-42e5-b492-e41d8527ef84
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490840874 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2490840874
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.295974545
Short name T95
Test name
Test status
Simulation time 77939698 ps
CPU time 1.32 seconds
Started Jun 28 06:02:15 PM PDT 24
Finished Jun 28 06:02:24 PM PDT 24
Peak memory 225976 kb
Host smart-29cf0405-458d-426f-b9a4-ec38e0b9fd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295974545 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.295974545
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2536555624
Short name T870
Test name
Test status
Simulation time 56447135 ps
CPU time 1.53 seconds
Started Jun 28 06:02:01 PM PDT 24
Finished Jun 28 06:02:12 PM PDT 24
Peak memory 218612 kb
Host smart-c5824263-b46b-4c8e-9248-67bcd42c4607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536555624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2536555624
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2607900618
Short name T768
Test name
Test status
Simulation time 33865740 ps
CPU time 0.89 seconds
Started Jun 28 06:02:04 PM PDT 24
Finished Jun 28 06:02:14 PM PDT 24
Peak memory 215836 kb
Host smart-f65faf3a-781e-4a72-b852-b4a731d89de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607900618 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2607900618
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1236217737
Short name T856
Test name
Test status
Simulation time 23606714 ps
CPU time 0.93 seconds
Started Jun 28 06:02:01 PM PDT 24
Finished Jun 28 06:02:11 PM PDT 24
Peak memory 215596 kb
Host smart-2f1ccc47-248b-48de-a4fa-3e345f433f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236217737 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1236217737
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1205623468
Short name T938
Test name
Test status
Simulation time 136864328 ps
CPU time 1.17 seconds
Started Jun 28 06:02:17 PM PDT 24
Finished Jun 28 06:02:26 PM PDT 24
Peak memory 217760 kb
Host smart-268015be-ec59-4f79-8be3-79583742a45d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205623468 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1205623468
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2546227262
Short name T36
Test name
Test status
Simulation time 83501292216 ps
CPU time 1058.46 seconds
Started Jun 28 06:02:06 PM PDT 24
Finished Jun 28 06:19:53 PM PDT 24
Peak memory 222536 kb
Host smart-a3437d6f-3170-4aee-9e73-e262a53aad84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546227262 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2546227262
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3134532298
Short name T168
Test name
Test status
Simulation time 22805592 ps
CPU time 1.14 seconds
Started Jun 28 06:02:14 PM PDT 24
Finished Jun 28 06:02:22 PM PDT 24
Peak memory 219104 kb
Host smart-9247cd8d-ef79-46d1-8dd0-2f8bc641d2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134532298 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3134532298
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2002481810
Short name T408
Test name
Test status
Simulation time 132489146 ps
CPU time 1 seconds
Started Jun 28 06:02:02 PM PDT 24
Finished Jun 28 06:02:12 PM PDT 24
Peak memory 207068 kb
Host smart-53c6ccb4-fdf7-4e5f-9d78-3f8bf17e432c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002481810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2002481810
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1081377713
Short name T843
Test name
Test status
Simulation time 19608894 ps
CPU time 0.88 seconds
Started Jun 28 06:02:17 PM PDT 24
Finished Jun 28 06:02:25 PM PDT 24
Peak memory 216532 kb
Host smart-2e8061a6-1c07-48dc-b861-33f6242041c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081377713 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1081377713
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2356875887
Short name T553
Test name
Test status
Simulation time 87237309 ps
CPU time 1.05 seconds
Started Jun 28 06:02:11 PM PDT 24
Finished Jun 28 06:02:20 PM PDT 24
Peak memory 217284 kb
Host smart-4756aba9-febc-48ff-8a56-b2f957442794
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356875887 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2356875887
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_genbits.3983159945
Short name T972
Test name
Test status
Simulation time 58395769 ps
CPU time 1.39 seconds
Started Jun 28 06:02:15 PM PDT 24
Finished Jun 28 06:02:24 PM PDT 24
Peak memory 220532 kb
Host smart-44e55941-bc29-4c22-b645-df33080f4408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983159945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3983159945
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1987872869
Short name T31
Test name
Test status
Simulation time 20629821 ps
CPU time 1.06 seconds
Started Jun 28 06:02:22 PM PDT 24
Finished Jun 28 06:02:28 PM PDT 24
Peak memory 216004 kb
Host smart-772304cf-0643-4d69-b733-a1487b141fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987872869 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1987872869
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2407254006
Short name T993
Test name
Test status
Simulation time 28593981 ps
CPU time 0.91 seconds
Started Jun 28 06:02:27 PM PDT 24
Finished Jun 28 06:02:32 PM PDT 24
Peak memory 215552 kb
Host smart-45c4fd38-753d-4076-9523-3574c5f58ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407254006 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2407254006
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.961152508
Short name T543
Test name
Test status
Simulation time 935678316 ps
CPU time 3.58 seconds
Started Jun 28 06:02:04 PM PDT 24
Finished Jun 28 06:02:16 PM PDT 24
Peak memory 217492 kb
Host smart-f88a7a85-3851-40f1-b2da-5a33c9a5a3e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961152508 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.961152508
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2780469574
Short name T610
Test name
Test status
Simulation time 84347928459 ps
CPU time 229.63 seconds
Started Jun 28 06:02:05 PM PDT 24
Finished Jun 28 06:06:03 PM PDT 24
Peak memory 224028 kb
Host smart-111edbcb-dcd3-431f-8336-b7c3c796977c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780469574 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2780469574
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3380139310
Short name T674
Test name
Test status
Simulation time 68163020 ps
CPU time 1.06 seconds
Started Jun 28 06:02:09 PM PDT 24
Finished Jun 28 06:02:18 PM PDT 24
Peak memory 219880 kb
Host smart-915b13fa-6593-4035-ba66-f27f09e5f7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380139310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3380139310
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3369081744
Short name T395
Test name
Test status
Simulation time 23375845 ps
CPU time 1.06 seconds
Started Jun 28 06:02:24 PM PDT 24
Finished Jun 28 06:02:30 PM PDT 24
Peak memory 215192 kb
Host smart-fc41756b-3ff2-45e2-b87b-6ab4083903ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369081744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3369081744
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3256289879
Short name T767
Test name
Test status
Simulation time 12015678 ps
CPU time 0.87 seconds
Started Jun 28 06:02:31 PM PDT 24
Finished Jun 28 06:02:36 PM PDT 24
Peak memory 216748 kb
Host smart-7a77bf92-27cc-4809-bf03-a52b57ea0787
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256289879 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3256289879
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3855344631
Short name T506
Test name
Test status
Simulation time 23710347 ps
CPU time 1.09 seconds
Started Jun 28 06:02:22 PM PDT 24
Finished Jun 28 06:02:29 PM PDT 24
Peak memory 220008 kb
Host smart-652eb8b6-12a5-4614-ac73-11e240736e8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855344631 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3855344631
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.1952956626
Short name T455
Test name
Test status
Simulation time 32449871 ps
CPU time 1 seconds
Started Jun 28 06:02:21 PM PDT 24
Finished Jun 28 06:02:28 PM PDT 24
Peak memory 224076 kb
Host smart-1f35065a-8181-435f-b7de-771cb165b31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952956626 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1952956626
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3635716067
Short name T41
Test name
Test status
Simulation time 38684838 ps
CPU time 1.61 seconds
Started Jun 28 06:02:10 PM PDT 24
Finished Jun 28 06:02:19 PM PDT 24
Peak memory 218892 kb
Host smart-2d5c5f2d-df95-4a3e-84c6-3931f6c321dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635716067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3635716067
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.355218410
Short name T830
Test name
Test status
Simulation time 22083187 ps
CPU time 1.05 seconds
Started Jun 28 06:02:23 PM PDT 24
Finished Jun 28 06:02:29 PM PDT 24
Peak memory 215780 kb
Host smart-32a26a57-438c-4c7a-9d67-4c7e8a3c004a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355218410 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.355218410
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2464786583
Short name T831
Test name
Test status
Simulation time 16870430 ps
CPU time 1 seconds
Started Jun 28 06:02:24 PM PDT 24
Finished Jun 28 06:02:30 PM PDT 24
Peak memory 207348 kb
Host smart-14bfd218-55f6-4110-901e-cd1e194c9819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464786583 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2464786583
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3570879028
Short name T479
Test name
Test status
Simulation time 159385128 ps
CPU time 3.4 seconds
Started Jun 28 06:02:18 PM PDT 24
Finished Jun 28 06:02:29 PM PDT 24
Peak memory 217484 kb
Host smart-4098364c-e31d-4f10-b2d4-861fabe67846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570879028 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3570879028
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2884338095
Short name T807
Test name
Test status
Simulation time 70684589032 ps
CPU time 445 seconds
Started Jun 28 06:02:30 PM PDT 24
Finished Jun 28 06:10:00 PM PDT 24
Peak memory 219380 kb
Host smart-c644a7a5-c948-49bd-b14c-cf2ba68782ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884338095 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2884338095
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.462194844
Short name T164
Test name
Test status
Simulation time 255846999 ps
CPU time 1.36 seconds
Started Jun 28 06:02:32 PM PDT 24
Finished Jun 28 06:02:39 PM PDT 24
Peak memory 220136 kb
Host smart-c76e36db-6d45-447c-8781-33d77f61c318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462194844 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.462194844
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1326105695
Short name T571
Test name
Test status
Simulation time 12823819 ps
CPU time 0.86 seconds
Started Jun 28 06:02:02 PM PDT 24
Finished Jun 28 06:02:12 PM PDT 24
Peak memory 207240 kb
Host smart-3a742c13-0065-4ebb-8b3d-bc070dc6465b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326105695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1326105695
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.943735608
Short name T216
Test name
Test status
Simulation time 20609800 ps
CPU time 1.03 seconds
Started Jun 28 06:02:14 PM PDT 24
Finished Jun 28 06:02:22 PM PDT 24
Peak memory 216748 kb
Host smart-2a4fee72-5421-4dc7-bcc8-b779e69f5843
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943735608 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.943735608
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2610200004
Short name T68
Test name
Test status
Simulation time 44764857 ps
CPU time 1.23 seconds
Started Jun 28 06:02:20 PM PDT 24
Finished Jun 28 06:02:28 PM PDT 24
Peak memory 217296 kb
Host smart-542555f0-0919-4add-86fc-1324460576ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610200004 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2610200004
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.37728732
Short name T427
Test name
Test status
Simulation time 19037896 ps
CPU time 0.94 seconds
Started Jun 28 06:02:16 PM PDT 24
Finished Jun 28 06:02:24 PM PDT 24
Peak memory 218792 kb
Host smart-12fa625d-e0dc-4121-afae-ecdae6bc3a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37728732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.37728732
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.959532590
Short name T379
Test name
Test status
Simulation time 28677100 ps
CPU time 1.24 seconds
Started Jun 28 06:02:24 PM PDT 24
Finished Jun 28 06:02:31 PM PDT 24
Peak memory 218960 kb
Host smart-65abf27b-09ab-40bc-a3b0-51026203a7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959532590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.959532590
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.4220244820
Short name T617
Test name
Test status
Simulation time 21295191 ps
CPU time 1.11 seconds
Started Jun 28 06:02:12 PM PDT 24
Finished Jun 28 06:02:20 PM PDT 24
Peak memory 216196 kb
Host smart-5660c9d7-6be1-4703-aba4-ef6879302108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220244820 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.4220244820
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.299604580
Short name T501
Test name
Test status
Simulation time 50786259 ps
CPU time 0.91 seconds
Started Jun 28 06:02:18 PM PDT 24
Finished Jun 28 06:02:26 PM PDT 24
Peak memory 215692 kb
Host smart-26daf6c7-2c9e-45c2-af77-d7f4c7bddd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299604580 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.299604580
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.595966371
Short name T244
Test name
Test status
Simulation time 130085818 ps
CPU time 2.96 seconds
Started Jun 28 06:02:17 PM PDT 24
Finished Jun 28 06:02:27 PM PDT 24
Peak memory 215612 kb
Host smart-f7d24603-41fb-45f0-87ed-6e2b91e27758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595966371 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.595966371
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1667060375
Short name T494
Test name
Test status
Simulation time 5733524601 ps
CPU time 151.05 seconds
Started Jun 28 06:02:16 PM PDT 24
Finished Jun 28 06:04:54 PM PDT 24
Peak memory 217972 kb
Host smart-c10abf41-41ff-4ffb-aef0-864f19f6e002
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667060375 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1667060375
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert_test.4200345391
Short name T638
Test name
Test status
Simulation time 92555038 ps
CPU time 0.83 seconds
Started Jun 28 06:02:08 PM PDT 24
Finished Jun 28 06:02:18 PM PDT 24
Peak memory 206832 kb
Host smart-3f27d557-bc52-4fe6-a536-c8300e072828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200345391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.4200345391
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3133990634
Short name T167
Test name
Test status
Simulation time 15740530 ps
CPU time 0.89 seconds
Started Jun 28 06:02:20 PM PDT 24
Finished Jun 28 06:02:27 PM PDT 24
Peak memory 215712 kb
Host smart-96deec75-119b-44e4-ad67-a5a68cb57cb8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133990634 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3133990634
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.687976704
Short name T149
Test name
Test status
Simulation time 31250626 ps
CPU time 1.21 seconds
Started Jun 28 06:02:08 PM PDT 24
Finished Jun 28 06:02:18 PM PDT 24
Peak memory 217232 kb
Host smart-54e1dee7-ff94-42fc-b441-843783803c1e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687976704 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.687976704
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2564732340
Short name T203
Test name
Test status
Simulation time 26513971 ps
CPU time 0.91 seconds
Started Jun 28 06:02:02 PM PDT 24
Finished Jun 28 06:02:11 PM PDT 24
Peak memory 218816 kb
Host smart-cd3a77e0-e847-46c1-97e9-5c5bf585e108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564732340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2564732340
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3318304959
Short name T374
Test name
Test status
Simulation time 64796413 ps
CPU time 2.37 seconds
Started Jun 28 06:02:29 PM PDT 24
Finished Jun 28 06:02:36 PM PDT 24
Peak memory 215560 kb
Host smart-fdc08461-d94e-46a8-9e02-f6bd3cd8b60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318304959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3318304959
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.4180924302
Short name T27
Test name
Test status
Simulation time 33821527 ps
CPU time 0.92 seconds
Started Jun 28 06:02:09 PM PDT 24
Finished Jun 28 06:02:18 PM PDT 24
Peak memory 215912 kb
Host smart-1e40b763-dcd7-46ce-9283-365c21b0fc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180924302 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.4180924302
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1273579700
Short name T747
Test name
Test status
Simulation time 35312176 ps
CPU time 0.96 seconds
Started Jun 28 06:02:09 PM PDT 24
Finished Jun 28 06:02:18 PM PDT 24
Peak memory 215604 kb
Host smart-94ebcc32-53cc-4b2d-bdae-13bf18f95dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273579700 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1273579700
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1708793020
Short name T858
Test name
Test status
Simulation time 153216981 ps
CPU time 3.31 seconds
Started Jun 28 06:02:18 PM PDT 24
Finished Jun 28 06:02:28 PM PDT 24
Peak memory 217580 kb
Host smart-d1893639-3fe1-49e3-89a7-857ff0d0fd71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708793020 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1708793020
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_alert_test.996189273
Short name T497
Test name
Test status
Simulation time 13238707 ps
CPU time 0.89 seconds
Started Jun 28 06:02:20 PM PDT 24
Finished Jun 28 06:02:27 PM PDT 24
Peak memory 207268 kb
Host smart-b4ed0058-f49a-47d6-8067-9d8aa259c30d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996189273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.996189273
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_err.811229925
Short name T702
Test name
Test status
Simulation time 34776782 ps
CPU time 0.89 seconds
Started Jun 28 06:02:11 PM PDT 24
Finished Jun 28 06:02:19 PM PDT 24
Peak memory 219640 kb
Host smart-682eaa29-3ee6-4bc6-a423-0458ac273380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811229925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.811229925
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1844638941
Short name T397
Test name
Test status
Simulation time 98720123 ps
CPU time 1.2 seconds
Started Jun 28 06:02:04 PM PDT 24
Finished Jun 28 06:02:14 PM PDT 24
Peak memory 217880 kb
Host smart-bd50bcac-0769-44a6-b7e7-201a27eb6129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844638941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1844638941
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.579366870
Short name T761
Test name
Test status
Simulation time 24898800 ps
CPU time 0.95 seconds
Started Jun 28 06:02:17 PM PDT 24
Finished Jun 28 06:02:25 PM PDT 24
Peak memory 215840 kb
Host smart-dc84061b-54dc-462e-978b-4179de94f80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579366870 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.579366870
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.191942456
Short name T239
Test name
Test status
Simulation time 17481270 ps
CPU time 1.01 seconds
Started Jun 28 06:02:18 PM PDT 24
Finished Jun 28 06:02:26 PM PDT 24
Peak memory 215560 kb
Host smart-b57f97cf-a928-4040-abfc-56b2da8c2032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191942456 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.191942456
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3403817706
Short name T451
Test name
Test status
Simulation time 319770747 ps
CPU time 2.77 seconds
Started Jun 28 06:02:08 PM PDT 24
Finished Jun 28 06:02:19 PM PDT 24
Peak memory 220456 kb
Host smart-41d6567e-e01f-41c6-b95e-bce91503d94d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403817706 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3403817706
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.4178176986
Short name T995
Test name
Test status
Simulation time 87590290213 ps
CPU time 1007.99 seconds
Started Jun 28 06:02:11 PM PDT 24
Finished Jun 28 06:19:07 PM PDT 24
Peak memory 224000 kb
Host smart-382b75e9-7ea7-4790-88a4-8be41b64b51d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178176986 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.4178176986
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1513275252
Short name T664
Test name
Test status
Simulation time 24513183 ps
CPU time 1.14 seconds
Started Jun 28 06:02:04 PM PDT 24
Finished Jun 28 06:02:14 PM PDT 24
Peak memory 220260 kb
Host smart-f91d02cc-90f3-4e2a-9931-a74e2bfbd3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513275252 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1513275252
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_disable.4181278885
Short name T184
Test name
Test status
Simulation time 133226381 ps
CPU time 0.88 seconds
Started Jun 28 06:02:18 PM PDT 24
Finished Jun 28 06:02:26 PM PDT 24
Peak memory 216536 kb
Host smart-f36cd0d8-64c8-4deb-bbd1-45067106d8ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181278885 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.4181278885
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3166241288
Short name T536
Test name
Test status
Simulation time 102895267 ps
CPU time 1.11 seconds
Started Jun 28 06:02:21 PM PDT 24
Finished Jun 28 06:02:28 PM PDT 24
Peak memory 217192 kb
Host smart-a7469184-a769-4023-9bb7-91e6b752b4a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166241288 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3166241288
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1910219787
Short name T706
Test name
Test status
Simulation time 97773410 ps
CPU time 1.16 seconds
Started Jun 28 06:02:05 PM PDT 24
Finished Jun 28 06:02:15 PM PDT 24
Peak memory 225916 kb
Host smart-f929e45c-84b5-44e4-a410-1aeb56404598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910219787 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1910219787
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1339983929
Short name T773
Test name
Test status
Simulation time 30687890 ps
CPU time 1.25 seconds
Started Jun 28 06:02:22 PM PDT 24
Finished Jun 28 06:02:28 PM PDT 24
Peak memory 217388 kb
Host smart-19d2d29b-5aae-437c-8b82-4810d85f0234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339983929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1339983929
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.531791236
Short name T779
Test name
Test status
Simulation time 22639722 ps
CPU time 0.97 seconds
Started Jun 28 06:02:11 PM PDT 24
Finished Jun 28 06:02:20 PM PDT 24
Peak memory 216188 kb
Host smart-e519faaf-7bee-4fe5-b4be-57d048da7608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531791236 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.531791236
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1046293386
Short name T792
Test name
Test status
Simulation time 15899778 ps
CPU time 1.04 seconds
Started Jun 28 06:02:09 PM PDT 24
Finished Jun 28 06:02:18 PM PDT 24
Peak memory 215604 kb
Host smart-6b7d9cda-410a-4d90-9dd1-81af75255e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046293386 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1046293386
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3154107177
Short name T447
Test name
Test status
Simulation time 550870529 ps
CPU time 3.61 seconds
Started Jun 28 06:02:17 PM PDT 24
Finished Jun 28 06:02:28 PM PDT 24
Peak memory 215612 kb
Host smart-8e7fc7f8-c6e8-42dc-a3ec-5af5a2fde39e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154107177 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3154107177
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.320664208
Short name T445
Test name
Test status
Simulation time 62501271191 ps
CPU time 740.96 seconds
Started Jun 28 06:02:10 PM PDT 24
Finished Jun 28 06:14:39 PM PDT 24
Peak memory 224084 kb
Host smart-ea44a989-9af3-44e8-9d94-3b61e8939472
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320664208 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.320664208
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.851076184
Short name T842
Test name
Test status
Simulation time 65620472 ps
CPU time 1.16 seconds
Started Jun 28 06:02:23 PM PDT 24
Finished Jun 28 06:02:30 PM PDT 24
Peak memory 219536 kb
Host smart-ee3ffd86-6e77-4073-8561-762b323d0d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851076184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.851076184
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1304513968
Short name T518
Test name
Test status
Simulation time 47273307 ps
CPU time 0.86 seconds
Started Jun 28 06:02:14 PM PDT 24
Finished Jun 28 06:02:22 PM PDT 24
Peak memory 206828 kb
Host smart-6fefb2cb-b950-4e90-ab3f-3e5829f8439b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304513968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1304513968
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1407682739
Short name T681
Test name
Test status
Simulation time 12823629 ps
CPU time 0.9 seconds
Started Jun 28 06:02:36 PM PDT 24
Finished Jun 28 06:02:42 PM PDT 24
Peak memory 215896 kb
Host smart-105918b3-e946-4017-8402-25ab16491e82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407682739 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1407682739
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3112098985
Short name T687
Test name
Test status
Simulation time 105901691 ps
CPU time 1.16 seconds
Started Jun 28 06:02:32 PM PDT 24
Finished Jun 28 06:02:39 PM PDT 24
Peak memory 219804 kb
Host smart-5ee3a568-353b-4182-a58a-8858ed13074d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112098985 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3112098985
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3936798695
Short name T883
Test name
Test status
Simulation time 20597190 ps
CPU time 1.22 seconds
Started Jun 28 06:02:27 PM PDT 24
Finished Jun 28 06:02:33 PM PDT 24
Peak memory 219712 kb
Host smart-4a6bf1a7-e072-4f2c-a364-f71e02508fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936798695 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3936798695
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.143171253
Short name T924
Test name
Test status
Simulation time 55431272 ps
CPU time 1.61 seconds
Started Jun 28 06:02:16 PM PDT 24
Finished Jun 28 06:02:25 PM PDT 24
Peak memory 218832 kb
Host smart-96ffdb51-032e-4198-bf29-e0ff4b94cbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143171253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.143171253
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3751705001
Short name T579
Test name
Test status
Simulation time 29092116 ps
CPU time 1.02 seconds
Started Jun 28 06:02:30 PM PDT 24
Finished Jun 28 06:02:36 PM PDT 24
Peak memory 224240 kb
Host smart-f69c0523-b4f0-4937-a838-dcfbb8bc5706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751705001 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3751705001
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.3395843768
Short name T641
Test name
Test status
Simulation time 98973946 ps
CPU time 0.99 seconds
Started Jun 28 06:02:27 PM PDT 24
Finished Jun 28 06:02:33 PM PDT 24
Peak memory 215600 kb
Host smart-3fb3af82-e87f-476e-af30-2d6c5aac8d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395843768 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3395843768
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2035923238
Short name T675
Test name
Test status
Simulation time 1201628230 ps
CPU time 5.33 seconds
Started Jun 28 06:02:32 PM PDT 24
Finished Jun 28 06:02:42 PM PDT 24
Peak memory 215784 kb
Host smart-a4e35df2-14bb-48e7-b095-5c6f5944bc0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035923238 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2035923238
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.4206312982
Short name T345
Test name
Test status
Simulation time 349666263195 ps
CPU time 1034.52 seconds
Started Jun 28 06:02:33 PM PDT 24
Finished Jun 28 06:19:53 PM PDT 24
Peak memory 224300 kb
Host smart-47fa8b2d-a1c2-4265-8a38-14f55161fceb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206312982 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.4206312982
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2621204565
Short name T882
Test name
Test status
Simulation time 49485482 ps
CPU time 1.21 seconds
Started Jun 28 06:01:35 PM PDT 24
Finished Jun 28 06:01:39 PM PDT 24
Peak memory 219868 kb
Host smart-cd9118ce-cdc6-4384-8e4a-3fb23dd11f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621204565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2621204565
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.869210155
Short name T630
Test name
Test status
Simulation time 31848024 ps
CPU time 1.16 seconds
Started Jun 28 06:01:36 PM PDT 24
Finished Jun 28 06:01:40 PM PDT 24
Peak memory 215252 kb
Host smart-bb5994cd-e6f8-4fe3-a567-1f88a895f2a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869210155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.869210155
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2037560380
Short name T966
Test name
Test status
Simulation time 11313121 ps
CPU time 0.93 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:46 PM PDT 24
Peak memory 216632 kb
Host smart-d8558e43-5f37-4637-b48b-4d6f05a79e5b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037560380 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2037560380
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.514791267
Short name T611
Test name
Test status
Simulation time 133221643 ps
CPU time 1.28 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:47 PM PDT 24
Peak memory 218936 kb
Host smart-4f810ae9-068a-4177-8906-51a35f98efca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514791267 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.514791267
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2045769668
Short name T213
Test name
Test status
Simulation time 87225686 ps
CPU time 1.33 seconds
Started Jun 28 06:01:35 PM PDT 24
Finished Jun 28 06:01:39 PM PDT 24
Peak memory 225840 kb
Host smart-5836a74d-ad28-4f3d-bb45-a68a0969282a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045769668 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2045769668
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1102378525
Short name T393
Test name
Test status
Simulation time 59481935 ps
CPU time 1.13 seconds
Started Jun 28 06:01:34 PM PDT 24
Finished Jun 28 06:01:35 PM PDT 24
Peak memory 217512 kb
Host smart-f560c303-ffc4-460f-a490-292cfb4fef86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102378525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1102378525
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2544554735
Short name T614
Test name
Test status
Simulation time 95301602 ps
CPU time 0.89 seconds
Started Jun 28 06:01:35 PM PDT 24
Finished Jun 28 06:01:38 PM PDT 24
Peak memory 215580 kb
Host smart-219f92d7-da7b-4173-9f78-53942ac4528e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544554735 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2544554735
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.905209518
Short name T726
Test name
Test status
Simulation time 14537093 ps
CPU time 1.07 seconds
Started Jun 28 06:01:36 PM PDT 24
Finished Jun 28 06:01:40 PM PDT 24
Peak memory 207396 kb
Host smart-e29f4ce2-86ad-4299-a7f6-83f592299b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905209518 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.905209518
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1230677284
Short name T63
Test name
Test status
Simulation time 979536625 ps
CPU time 7.95 seconds
Started Jun 28 06:01:36 PM PDT 24
Finished Jun 28 06:01:46 PM PDT 24
Peak memory 236500 kb
Host smart-53770731-482b-4437-818d-373eb26476d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230677284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1230677284
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2884050503
Short name T682
Test name
Test status
Simulation time 24414130 ps
CPU time 0.94 seconds
Started Jun 28 06:01:38 PM PDT 24
Finished Jun 28 06:01:44 PM PDT 24
Peak memory 215632 kb
Host smart-abb76837-c393-4b7e-83f0-635c58d842cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884050503 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2884050503
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2295238332
Short name T979
Test name
Test status
Simulation time 153932419 ps
CPU time 3.15 seconds
Started Jun 28 06:01:36 PM PDT 24
Finished Jun 28 06:01:42 PM PDT 24
Peak memory 217760 kb
Host smart-a8a9e20c-0e18-4e81-a00d-b0556ce5ec43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295238332 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2295238332
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3625814605
Short name T720
Test name
Test status
Simulation time 147375346065 ps
CPU time 979.47 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:18:03 PM PDT 24
Peak memory 224136 kb
Host smart-661b9b8d-7a52-4971-82b6-9bac9b6244c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625814605 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3625814605
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1987853057
Short name T591
Test name
Test status
Simulation time 31573563 ps
CPU time 1.36 seconds
Started Jun 28 06:02:31 PM PDT 24
Finished Jun 28 06:02:38 PM PDT 24
Peak memory 220008 kb
Host smart-d0c98f29-3cd1-4314-bc8b-b33541479b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987853057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1987853057
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.236081071
Short name T475
Test name
Test status
Simulation time 16278463 ps
CPU time 1 seconds
Started Jun 28 06:02:45 PM PDT 24
Finished Jun 28 06:02:53 PM PDT 24
Peak memory 207048 kb
Host smart-091cde25-239e-4bde-bde2-4233324c3d93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236081071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.236081071
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.69893414
Short name T87
Test name
Test status
Simulation time 31179377 ps
CPU time 0.86 seconds
Started Jun 28 06:02:29 PM PDT 24
Finished Jun 28 06:02:34 PM PDT 24
Peak memory 216560 kb
Host smart-8cab85bb-b20e-44ed-9174-3462e13d60d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69893414 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.69893414
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.473621065
Short name T577
Test name
Test status
Simulation time 49061841 ps
CPU time 1.52 seconds
Started Jun 28 06:02:24 PM PDT 24
Finished Jun 28 06:02:30 PM PDT 24
Peak memory 217252 kb
Host smart-10c628ff-4995-4fab-bd51-e7129e212e5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473621065 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.473621065
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.4026173472
Short name T709
Test name
Test status
Simulation time 22159379 ps
CPU time 1.14 seconds
Started Jun 28 06:02:31 PM PDT 24
Finished Jun 28 06:02:36 PM PDT 24
Peak memory 220192 kb
Host smart-faf79e97-92c8-44f7-bd28-df85adadc974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026173472 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.4026173472
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1349238945
Short name T341
Test name
Test status
Simulation time 93584486 ps
CPU time 1.57 seconds
Started Jun 28 06:02:21 PM PDT 24
Finished Jun 28 06:02:28 PM PDT 24
Peak memory 218844 kb
Host smart-e72250de-72e3-43be-b862-2935b2efbbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349238945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1349238945
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3763427203
Short name T748
Test name
Test status
Simulation time 20369033 ps
CPU time 1.03 seconds
Started Jun 28 06:02:24 PM PDT 24
Finished Jun 28 06:02:30 PM PDT 24
Peak memory 216060 kb
Host smart-cdbf5701-7073-4c0f-a1a7-6d8f16c07a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763427203 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3763427203
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.355218935
Short name T652
Test name
Test status
Simulation time 24322526 ps
CPU time 0.91 seconds
Started Jun 28 06:02:36 PM PDT 24
Finished Jun 28 06:02:42 PM PDT 24
Peak memory 215604 kb
Host smart-07ebb592-a351-4766-9925-53c1cc5fda63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355218935 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.355218935
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2924642786
Short name T54
Test name
Test status
Simulation time 116082768 ps
CPU time 1.66 seconds
Started Jun 28 06:02:33 PM PDT 24
Finished Jun 28 06:02:40 PM PDT 24
Peak memory 215548 kb
Host smart-bb3dbce7-8345-47ff-ac6c-5cfbad8ae56b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924642786 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2924642786
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1342097518
Short name T225
Test name
Test status
Simulation time 37564463894 ps
CPU time 434.5 seconds
Started Jun 28 06:02:24 PM PDT 24
Finished Jun 28 06:09:43 PM PDT 24
Peak memory 224004 kb
Host smart-269ee9a7-9da7-4e4c-8fb4-11acca7205ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342097518 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1342097518
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.295426155
Short name T654
Test name
Test status
Simulation time 106209492 ps
CPU time 1.32 seconds
Started Jun 28 06:02:30 PM PDT 24
Finished Jun 28 06:02:36 PM PDT 24
Peak memory 216004 kb
Host smart-58249c77-e1d3-4423-b105-01cd3796a3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295426155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.295426155
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2742145258
Short name T468
Test name
Test status
Simulation time 19839219 ps
CPU time 1.02 seconds
Started Jun 28 06:02:32 PM PDT 24
Finished Jun 28 06:02:38 PM PDT 24
Peak memory 215184 kb
Host smart-0a1a3eed-b6bf-4659-a293-ea5cf4a4212a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742145258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2742145258
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3622700150
Short name T81
Test name
Test status
Simulation time 12530142 ps
CPU time 0.95 seconds
Started Jun 28 06:02:22 PM PDT 24
Finished Jun 28 06:02:28 PM PDT 24
Peak memory 216520 kb
Host smart-308f12e2-ec17-48c5-b4df-87b17adea090
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622700150 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3622700150
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_err.1535657876
Short name T488
Test name
Test status
Simulation time 62740460 ps
CPU time 1.02 seconds
Started Jun 28 06:02:23 PM PDT 24
Finished Jun 28 06:02:29 PM PDT 24
Peak memory 218836 kb
Host smart-2f01c566-dbcf-4de8-8761-904af3fee847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535657876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1535657876
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.4039167533
Short name T96
Test name
Test status
Simulation time 74330894 ps
CPU time 1.19 seconds
Started Jun 28 06:02:31 PM PDT 24
Finished Jun 28 06:02:36 PM PDT 24
Peak memory 218852 kb
Host smart-e217ef89-d141-4a2b-86c5-463312480593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039167533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.4039167533
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.301743690
Short name T559
Test name
Test status
Simulation time 25657207 ps
CPU time 0.97 seconds
Started Jun 28 06:02:28 PM PDT 24
Finished Jun 28 06:02:34 PM PDT 24
Peak memory 216164 kb
Host smart-610f5cd9-3144-4e1a-ae42-16f0e66de8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301743690 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.301743690
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3199212126
Short name T961
Test name
Test status
Simulation time 30164364 ps
CPU time 0.95 seconds
Started Jun 28 06:02:30 PM PDT 24
Finished Jun 28 06:02:36 PM PDT 24
Peak memory 215580 kb
Host smart-8bb84cb3-6094-4e79-9cb0-12c418ceee5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199212126 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3199212126
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2842212379
Short name T459
Test name
Test status
Simulation time 149581697 ps
CPU time 3.22 seconds
Started Jun 28 06:02:32 PM PDT 24
Finished Jun 28 06:02:40 PM PDT 24
Peak memory 217508 kb
Host smart-7a96c614-4da8-44a0-9cb4-79f55fea4513
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842212379 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2842212379
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3731616740
Short name T234
Test name
Test status
Simulation time 224974384984 ps
CPU time 1262.93 seconds
Started Jun 28 06:02:33 PM PDT 24
Finished Jun 28 06:23:42 PM PDT 24
Peak memory 224032 kb
Host smart-10c8f235-ac15-405f-a732-d60922d68fcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731616740 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3731616740
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3265663743
Short name T292
Test name
Test status
Simulation time 27320048 ps
CPU time 1.26 seconds
Started Jun 28 06:02:33 PM PDT 24
Finished Jun 28 06:02:40 PM PDT 24
Peak memory 219044 kb
Host smart-ee4214ee-e826-485f-9592-f765f3e6fbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265663743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3265663743
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2256760979
Short name T795
Test name
Test status
Simulation time 17477106 ps
CPU time 0.83 seconds
Started Jun 28 06:02:31 PM PDT 24
Finished Jun 28 06:02:37 PM PDT 24
Peak memory 207028 kb
Host smart-6611cb6c-81d6-4583-97cd-26aed3a2e795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256760979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2256760979
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2740929486
Short name T182
Test name
Test status
Simulation time 66895057 ps
CPU time 0.84 seconds
Started Jun 28 06:02:28 PM PDT 24
Finished Jun 28 06:02:33 PM PDT 24
Peak memory 216640 kb
Host smart-93ae9488-83fd-49cc-ba8f-ce41cc297cf3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740929486 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2740929486
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1181976427
Short name T567
Test name
Test status
Simulation time 45539278 ps
CPU time 1.03 seconds
Started Jun 28 06:02:30 PM PDT 24
Finished Jun 28 06:02:36 PM PDT 24
Peak memory 218908 kb
Host smart-a053e82d-ea3a-4006-ad3c-8061529c5998
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181976427 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1181976427
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.4030810014
Short name T165
Test name
Test status
Simulation time 24644953 ps
CPU time 0.93 seconds
Started Jun 28 06:02:32 PM PDT 24
Finished Jun 28 06:02:38 PM PDT 24
Peak memory 218852 kb
Host smart-70b2bdae-87e4-4bae-9fc8-71a7c02f1ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030810014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.4030810014
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2050982604
Short name T343
Test name
Test status
Simulation time 42793358 ps
CPU time 1.51 seconds
Started Jun 28 06:02:38 PM PDT 24
Finished Jun 28 06:02:44 PM PDT 24
Peak memory 220084 kb
Host smart-bc7d55eb-1ccf-475e-91a2-4ae31f31531c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050982604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2050982604
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.492729600
Short name T12
Test name
Test status
Simulation time 22593746 ps
CPU time 1.24 seconds
Started Jun 28 06:02:24 PM PDT 24
Finished Jun 28 06:02:30 PM PDT 24
Peak memory 224312 kb
Host smart-2562633b-44fa-4292-9394-286cf09551af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492729600 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.492729600
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.4181522400
Short name T597
Test name
Test status
Simulation time 41310409 ps
CPU time 0.9 seconds
Started Jun 28 06:02:30 PM PDT 24
Finished Jun 28 06:02:36 PM PDT 24
Peak memory 215604 kb
Host smart-c4804277-1d1e-4819-a7e5-bc6d0fe360cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181522400 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.4181522400
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2062591607
Short name T905
Test name
Test status
Simulation time 658500841 ps
CPU time 4.46 seconds
Started Jun 28 06:02:28 PM PDT 24
Finished Jun 28 06:02:37 PM PDT 24
Peak memory 217564 kb
Host smart-3f152a08-4b13-4d8e-b760-ef79b8d901a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062591607 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2062591607
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1935559645
Short name T416
Test name
Test status
Simulation time 30192747666 ps
CPU time 680.18 seconds
Started Jun 28 06:02:27 PM PDT 24
Finished Jun 28 06:13:52 PM PDT 24
Peak memory 224052 kb
Host smart-1ebf34b3-a002-4b62-8faf-1e5d59d272da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935559645 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1935559645
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.524473487
Short name T113
Test name
Test status
Simulation time 172535695 ps
CPU time 1.1 seconds
Started Jun 28 06:02:32 PM PDT 24
Finished Jun 28 06:02:38 PM PDT 24
Peak memory 218692 kb
Host smart-4bb92fbc-c323-4421-9e47-502131b1a336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524473487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.524473487
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1190254807
Short name T623
Test name
Test status
Simulation time 23430101 ps
CPU time 0.86 seconds
Started Jun 28 06:02:34 PM PDT 24
Finished Jun 28 06:02:40 PM PDT 24
Peak memory 206832 kb
Host smart-c99b7936-70a0-47a6-b727-8cf218c70ad3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190254807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1190254807
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1615623568
Short name T974
Test name
Test status
Simulation time 17222685 ps
CPU time 0.87 seconds
Started Jun 28 06:02:19 PM PDT 24
Finished Jun 28 06:02:27 PM PDT 24
Peak memory 215704 kb
Host smart-3ff8b2f4-30d6-4724-9aa6-219d41424fb0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615623568 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1615623568
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1269704578
Short name T136
Test name
Test status
Simulation time 100679663 ps
CPU time 1.14 seconds
Started Jun 28 06:02:29 PM PDT 24
Finished Jun 28 06:02:34 PM PDT 24
Peak memory 217320 kb
Host smart-725cc8bf-1b12-4599-8843-faf462c0c65b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269704578 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1269704578
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3178386448
Short name T166
Test name
Test status
Simulation time 46417264 ps
CPU time 1.25 seconds
Started Jun 28 06:02:31 PM PDT 24
Finished Jun 28 06:02:38 PM PDT 24
Peak memory 225100 kb
Host smart-30851479-fca5-4410-9951-d6f935c63f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178386448 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3178386448
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.730199434
Short name T745
Test name
Test status
Simulation time 47241909 ps
CPU time 1.38 seconds
Started Jun 28 06:02:30 PM PDT 24
Finished Jun 28 06:02:36 PM PDT 24
Peak memory 219132 kb
Host smart-2f2afc0e-00da-4784-864d-bc42ecf19a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730199434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.730199434
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1128056291
Short name T62
Test name
Test status
Simulation time 23151076 ps
CPU time 1.1 seconds
Started Jun 28 06:02:25 PM PDT 24
Finished Jun 28 06:02:31 PM PDT 24
Peak memory 215720 kb
Host smart-4e418ddd-0962-47b2-9955-21d96adecdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128056291 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1128056291
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.962547037
Short name T365
Test name
Test status
Simulation time 45360104 ps
CPU time 0.9 seconds
Started Jun 28 06:02:35 PM PDT 24
Finished Jun 28 06:02:41 PM PDT 24
Peak memory 215596 kb
Host smart-a86b9b6a-f8b4-42d8-a96e-fe31d4c00a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962547037 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.962547037
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3735074836
Short name T595
Test name
Test status
Simulation time 758307542 ps
CPU time 3.53 seconds
Started Jun 28 06:02:31 PM PDT 24
Finished Jun 28 06:02:40 PM PDT 24
Peak memory 217764 kb
Host smart-f47aa039-4848-4041-b7b2-f044f61f321a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735074836 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3735074836
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1931750735
Short name T956
Test name
Test status
Simulation time 82638324861 ps
CPU time 1017.23 seconds
Started Jun 28 06:02:30 PM PDT 24
Finished Jun 28 06:19:32 PM PDT 24
Peak memory 222360 kb
Host smart-cd7e5b9f-0769-41bd-bf66-037a370e3689
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931750735 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1931750735
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.637179444
Short name T307
Test name
Test status
Simulation time 62839057 ps
CPU time 1.19 seconds
Started Jun 28 06:02:31 PM PDT 24
Finished Jun 28 06:02:37 PM PDT 24
Peak memory 219860 kb
Host smart-78c49581-b17b-4851-9b7a-dbb2d7bc8372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637179444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.637179444
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1850230104
Short name T793
Test name
Test status
Simulation time 13994398 ps
CPU time 0.91 seconds
Started Jun 28 06:02:33 PM PDT 24
Finished Jun 28 06:02:39 PM PDT 24
Peak memory 206932 kb
Host smart-9d96cc3d-0df4-49a2-90e8-de5d6e69cd6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850230104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1850230104
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1275463842
Short name T175
Test name
Test status
Simulation time 31159546 ps
CPU time 0.87 seconds
Started Jun 28 06:02:27 PM PDT 24
Finished Jun 28 06:02:32 PM PDT 24
Peak memory 216656 kb
Host smart-c2e4fc49-8f9e-431f-8ba6-144f62d355a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275463842 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1275463842
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3188197628
Short name T975
Test name
Test status
Simulation time 92175463 ps
CPU time 1.07 seconds
Started Jun 28 06:02:41 PM PDT 24
Finished Jun 28 06:02:46 PM PDT 24
Peak memory 215912 kb
Host smart-e395ab5a-a0a9-478e-a61c-1cee67bf39a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188197628 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3188197628
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3781221767
Short name T919
Test name
Test status
Simulation time 18867405 ps
CPU time 1.13 seconds
Started Jun 28 06:02:32 PM PDT 24
Finished Jun 28 06:02:38 PM PDT 24
Peak memory 224268 kb
Host smart-deb66696-b96f-4969-8417-d4e311478f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781221767 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3781221767
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.657047101
Short name T347
Test name
Test status
Simulation time 126854795 ps
CPU time 1.45 seconds
Started Jun 28 06:02:34 PM PDT 24
Finished Jun 28 06:02:41 PM PDT 24
Peak memory 219036 kb
Host smart-e9668584-292b-4db0-a497-8085da8003b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657047101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.657047101
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3228259618
Short name T841
Test name
Test status
Simulation time 52969921 ps
CPU time 0.84 seconds
Started Jun 28 06:02:30 PM PDT 24
Finished Jun 28 06:02:35 PM PDT 24
Peak memory 215808 kb
Host smart-7a550ec8-413b-4ca0-afe7-5aa5e01cbab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228259618 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3228259618
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.63197250
Short name T967
Test name
Test status
Simulation time 15976938 ps
CPU time 0.97 seconds
Started Jun 28 06:02:30 PM PDT 24
Finished Jun 28 06:02:36 PM PDT 24
Peak memory 215596 kb
Host smart-1936eb10-50ac-4c20-9f41-928a4cd18262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63197250 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.63197250
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3821000756
Short name T533
Test name
Test status
Simulation time 194482637 ps
CPU time 4.13 seconds
Started Jun 28 06:02:27 PM PDT 24
Finished Jun 28 06:02:35 PM PDT 24
Peak memory 215612 kb
Host smart-b82a831a-3600-4cc9-a943-a2fc8323f631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821000756 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3821000756
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2518126796
Short name T35
Test name
Test status
Simulation time 18124795942 ps
CPU time 434.6 seconds
Started Jun 28 06:02:42 PM PDT 24
Finished Jun 28 06:10:02 PM PDT 24
Peak memory 218388 kb
Host smart-bf952552-0036-4f71-8984-f413c5756bae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518126796 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2518126796
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1530282285
Short name T219
Test name
Test status
Simulation time 48628822 ps
CPU time 1.17 seconds
Started Jun 28 06:02:33 PM PDT 24
Finished Jun 28 06:02:40 PM PDT 24
Peak memory 219176 kb
Host smart-db3e3e84-e585-4120-b111-632022889c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530282285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1530282285
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3200686115
Short name T874
Test name
Test status
Simulation time 26994830 ps
CPU time 0.93 seconds
Started Jun 28 06:02:28 PM PDT 24
Finished Jun 28 06:02:34 PM PDT 24
Peak memory 207072 kb
Host smart-5520c4f3-e3f4-496f-a779-543e24727609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200686115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3200686115
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.909873170
Short name T517
Test name
Test status
Simulation time 38497575 ps
CPU time 1.05 seconds
Started Jun 28 06:02:28 PM PDT 24
Finished Jun 28 06:02:34 PM PDT 24
Peak memory 220084 kb
Host smart-c5be78e1-93c3-494f-8ec9-814e422455b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909873170 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.909873170
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1637717163
Short name T197
Test name
Test status
Simulation time 20267086 ps
CPU time 1.18 seconds
Started Jun 28 06:02:28 PM PDT 24
Finished Jun 28 06:02:34 PM PDT 24
Peak memory 229832 kb
Host smart-57a5d600-cb67-46e1-90ec-b682eb6c3293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637717163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1637717163
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.397366946
Short name T812
Test name
Test status
Simulation time 114416021 ps
CPU time 1.3 seconds
Started Jun 28 06:02:31 PM PDT 24
Finished Jun 28 06:02:38 PM PDT 24
Peak memory 217808 kb
Host smart-3a907b3e-32da-4583-8f5b-a8b1c970b388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397366946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.397366946
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2768590590
Short name T916
Test name
Test status
Simulation time 22253645 ps
CPU time 1.15 seconds
Started Jun 28 06:02:26 PM PDT 24
Finished Jun 28 06:02:31 PM PDT 24
Peak memory 215720 kb
Host smart-6bc981ad-4f72-468b-b897-b6e1040ca34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768590590 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2768590590
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2248677199
Short name T935
Test name
Test status
Simulation time 18361963 ps
CPU time 1.03 seconds
Started Jun 28 06:02:42 PM PDT 24
Finished Jun 28 06:02:47 PM PDT 24
Peak memory 207420 kb
Host smart-1eb70846-a15f-4bc4-846b-f5cf0680ca19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248677199 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2248677199
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1316144682
Short name T581
Test name
Test status
Simulation time 276394032 ps
CPU time 3.7 seconds
Started Jun 28 06:02:28 PM PDT 24
Finished Jun 28 06:02:36 PM PDT 24
Peak memory 217756 kb
Host smart-38f2ce2d-10d4-46a8-81ad-318a7a3f4d18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316144682 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1316144682
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2660984103
Short name T231
Test name
Test status
Simulation time 115132184090 ps
CPU time 736.83 seconds
Started Jun 28 06:02:32 PM PDT 24
Finished Jun 28 06:14:54 PM PDT 24
Peak memory 224060 kb
Host smart-beb087cf-4857-4b73-b4e7-12651c93cbe9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660984103 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2660984103
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1941790265
Short name T242
Test name
Test status
Simulation time 52013503 ps
CPU time 1.24 seconds
Started Jun 28 06:02:34 PM PDT 24
Finished Jun 28 06:02:41 PM PDT 24
Peak memory 218840 kb
Host smart-1ca9ad1a-5ec9-474a-b71f-836d7505831f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941790265 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1941790265
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4181582502
Short name T909
Test name
Test status
Simulation time 13268977 ps
CPU time 0.9 seconds
Started Jun 28 06:02:27 PM PDT 24
Finished Jun 28 06:02:32 PM PDT 24
Peak memory 206936 kb
Host smart-8047a621-9d14-4fc1-8f98-4490a247c9b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181582502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4181582502
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1633643992
Short name T982
Test name
Test status
Simulation time 23900161 ps
CPU time 0.88 seconds
Started Jun 28 06:02:32 PM PDT 24
Finished Jun 28 06:02:38 PM PDT 24
Peak memory 216340 kb
Host smart-25a47f07-8d39-4bf9-a0c5-d066d74749ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633643992 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1633643992
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2547591256
Short name T877
Test name
Test status
Simulation time 44821948 ps
CPU time 1.49 seconds
Started Jun 28 06:02:28 PM PDT 24
Finished Jun 28 06:02:34 PM PDT 24
Peak memory 217168 kb
Host smart-613d8c2e-a1ce-4abc-8289-efee7fccfb79
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547591256 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2547591256
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2280119994
Short name T922
Test name
Test status
Simulation time 26473905 ps
CPU time 1.14 seconds
Started Jun 28 06:02:30 PM PDT 24
Finished Jun 28 06:02:35 PM PDT 24
Peak memory 220988 kb
Host smart-0e50aa60-7bfb-469b-b410-449e2e3f2f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280119994 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2280119994
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1361425955
Short name T9
Test name
Test status
Simulation time 54308271 ps
CPU time 1.34 seconds
Started Jun 28 06:02:33 PM PDT 24
Finished Jun 28 06:02:39 PM PDT 24
Peak memory 220200 kb
Host smart-c1e61fc5-6b14-4d6d-a806-c3e10dcf2895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361425955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1361425955
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1351474790
Short name T443
Test name
Test status
Simulation time 34652659 ps
CPU time 0.92 seconds
Started Jun 28 06:02:30 PM PDT 24
Finished Jun 28 06:02:36 PM PDT 24
Peak memory 215580 kb
Host smart-73dd4f44-c010-439d-b2e8-778d4253dc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351474790 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1351474790
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.751532294
Short name T802
Test name
Test status
Simulation time 41574061 ps
CPU time 0.98 seconds
Started Jun 28 06:02:42 PM PDT 24
Finished Jun 28 06:02:48 PM PDT 24
Peak memory 215600 kb
Host smart-cf87e298-a359-4b71-8472-8d655cd4b73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751532294 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.751532294
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2397438771
Short name T625
Test name
Test status
Simulation time 1070963435 ps
CPU time 4.21 seconds
Started Jun 28 06:02:23 PM PDT 24
Finished Jun 28 06:02:32 PM PDT 24
Peak memory 217504 kb
Host smart-0fe783a3-a867-4bf4-932c-bc47a957730f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397438771 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2397438771
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.559608882
Short name T994
Test name
Test status
Simulation time 69170985801 ps
CPU time 664.43 seconds
Started Jun 28 06:02:31 PM PDT 24
Finished Jun 28 06:13:40 PM PDT 24
Peak memory 220040 kb
Host smart-0642bbd6-0dee-46a5-ba7c-7322b660df5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559608882 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.559608882
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3519571236
Short name T311
Test name
Test status
Simulation time 25469890 ps
CPU time 1.22 seconds
Started Jun 28 06:02:44 PM PDT 24
Finished Jun 28 06:02:51 PM PDT 24
Peak memory 218900 kb
Host smart-f9466bda-6063-4a28-88ba-449783eef391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519571236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3519571236
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3485294467
Short name T728
Test name
Test status
Simulation time 49157292 ps
CPU time 0.88 seconds
Started Jun 28 06:02:35 PM PDT 24
Finished Jun 28 06:02:41 PM PDT 24
Peak memory 215020 kb
Host smart-b323263f-3c45-42d9-8e96-93e03c4c1f17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485294467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3485294467
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3111031648
Short name T46
Test name
Test status
Simulation time 20160297 ps
CPU time 0.89 seconds
Started Jun 28 06:02:34 PM PDT 24
Finished Jun 28 06:02:41 PM PDT 24
Peak memory 216612 kb
Host smart-f9192c9f-7da0-49cc-9298-cac04f9c9af2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111031648 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3111031648
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1635251956
Short name T257
Test name
Test status
Simulation time 32623530 ps
CPU time 1.18 seconds
Started Jun 28 06:02:38 PM PDT 24
Finished Jun 28 06:02:44 PM PDT 24
Peak memory 218848 kb
Host smart-b38be202-7fec-4cbf-8f94-89bca9c20857
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635251956 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1635251956
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3422988487
Short name T948
Test name
Test status
Simulation time 73979901 ps
CPU time 1.12 seconds
Started Jun 28 06:02:44 PM PDT 24
Finished Jun 28 06:02:50 PM PDT 24
Peak memory 225948 kb
Host smart-a1c78484-6a4d-4915-a466-a4b74000fc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422988487 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3422988487
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3025205966
Short name T646
Test name
Test status
Simulation time 104457314 ps
CPU time 1.15 seconds
Started Jun 28 06:02:32 PM PDT 24
Finished Jun 28 06:02:39 PM PDT 24
Peak memory 217472 kb
Host smart-11171691-6956-4202-acc1-9edcb2325cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025205966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3025205966
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.34686518
Short name T91
Test name
Test status
Simulation time 23333380 ps
CPU time 0.97 seconds
Started Jun 28 06:02:32 PM PDT 24
Finished Jun 28 06:02:38 PM PDT 24
Peak memory 216176 kb
Host smart-1709bf70-e4ad-4f5e-b58e-3c91e1697067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34686518 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.34686518
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2946537899
Short name T859
Test name
Test status
Simulation time 24821092 ps
CPU time 0.92 seconds
Started Jun 28 06:02:37 PM PDT 24
Finished Jun 28 06:02:43 PM PDT 24
Peak memory 215572 kb
Host smart-ced96d50-78ae-4549-85e3-737bf12e2b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946537899 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2946537899
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.196504091
Short name T839
Test name
Test status
Simulation time 332425060 ps
CPU time 1.68 seconds
Started Jun 28 06:02:42 PM PDT 24
Finished Jun 28 06:02:49 PM PDT 24
Peak memory 215536 kb
Host smart-982d60c8-0fb2-4fb5-a4ca-e5e1870c4bba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196504091 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.196504091
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3212467132
Short name T712
Test name
Test status
Simulation time 1312455914948 ps
CPU time 1730.34 seconds
Started Jun 28 06:02:40 PM PDT 24
Finished Jun 28 06:31:35 PM PDT 24
Peak memory 224008 kb
Host smart-c8f69341-6182-430b-bfdc-b5e58ef59139
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212467132 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3212467132
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2856545845
Short name T912
Test name
Test status
Simulation time 29838751 ps
CPU time 1.32 seconds
Started Jun 28 06:02:40 PM PDT 24
Finished Jun 28 06:02:45 PM PDT 24
Peak memory 219024 kb
Host smart-9c307239-283a-4f96-b92d-e9102308afa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856545845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2856545845
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1095025091
Short name T913
Test name
Test status
Simulation time 27959406 ps
CPU time 0.92 seconds
Started Jun 28 06:02:33 PM PDT 24
Finished Jun 28 06:02:39 PM PDT 24
Peak memory 207008 kb
Host smart-9303977b-7722-4678-b6d8-bb85b8024099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095025091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1095025091
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3132226541
Short name T18
Test name
Test status
Simulation time 27318222 ps
CPU time 0.93 seconds
Started Jun 28 06:02:39 PM PDT 24
Finished Jun 28 06:02:44 PM PDT 24
Peak memory 216180 kb
Host smart-768d203c-7637-4cb3-bc8e-2229747b1483
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132226541 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3132226541
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1907454114
Short name T740
Test name
Test status
Simulation time 40518243 ps
CPU time 1.28 seconds
Started Jun 28 06:02:35 PM PDT 24
Finished Jun 28 06:02:41 PM PDT 24
Peak memory 217236 kb
Host smart-224bb11b-e818-4295-81c4-634957ee517b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907454114 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1907454114
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1432198316
Short name T147
Test name
Test status
Simulation time 25341865 ps
CPU time 1.18 seconds
Started Jun 28 06:02:36 PM PDT 24
Finished Jun 28 06:02:42 PM PDT 24
Peak memory 229832 kb
Host smart-e9344270-b4da-450f-878c-23ceac5aeeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432198316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1432198316
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2820042933
Short name T737
Test name
Test status
Simulation time 84375147 ps
CPU time 1.13 seconds
Started Jun 28 06:02:42 PM PDT 24
Finished Jun 28 06:02:47 PM PDT 24
Peak memory 217648 kb
Host smart-62db3af0-74f6-4c5f-b76e-716df21fb0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820042933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2820042933
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_smoke.1405507794
Short name T531
Test name
Test status
Simulation time 18503113 ps
CPU time 1.02 seconds
Started Jun 28 06:02:46 PM PDT 24
Finished Jun 28 06:02:54 PM PDT 24
Peak memory 215616 kb
Host smart-a25e8f0b-2b98-43b6-b919-6c99b29d7d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405507794 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1405507794
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1750437336
Short name T340
Test name
Test status
Simulation time 135027544 ps
CPU time 3.06 seconds
Started Jun 28 06:02:35 PM PDT 24
Finished Jun 28 06:02:44 PM PDT 24
Peak memory 220108 kb
Host smart-b0dd0344-920d-41b9-9f0a-a33dfcf58de7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750437336 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1750437336
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.4202415518
Short name T604
Test name
Test status
Simulation time 145584360434 ps
CPU time 586.83 seconds
Started Jun 28 06:02:34 PM PDT 24
Finished Jun 28 06:12:27 PM PDT 24
Peak memory 220376 kb
Host smart-6543d0bd-345d-49fa-845c-64638d846cdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202415518 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.4202415518
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.503509980
Short name T218
Test name
Test status
Simulation time 44048026 ps
CPU time 1.23 seconds
Started Jun 28 06:02:42 PM PDT 24
Finished Jun 28 06:02:48 PM PDT 24
Peak memory 219456 kb
Host smart-73beaf5f-e033-4ff3-b296-9ee668afc186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503509980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.503509980
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2900050341
Short name T891
Test name
Test status
Simulation time 43625038 ps
CPU time 0.89 seconds
Started Jun 28 06:02:31 PM PDT 24
Finished Jun 28 06:02:36 PM PDT 24
Peak memory 215476 kb
Host smart-45c1fb85-fc6f-4744-b2ab-1b874937d9a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900050341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2900050341
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.905889694
Short name T562
Test name
Test status
Simulation time 36846601 ps
CPU time 0.85 seconds
Started Jun 28 06:02:34 PM PDT 24
Finished Jun 28 06:02:40 PM PDT 24
Peak memory 216652 kb
Host smart-ce49e536-f9c0-4f2c-b4be-a201be92a8f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905889694 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.905889694
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2332566020
Short name T368
Test name
Test status
Simulation time 72285730 ps
CPU time 1.11 seconds
Started Jun 28 06:02:36 PM PDT 24
Finished Jun 28 06:02:42 PM PDT 24
Peak memory 217252 kb
Host smart-00cea8f2-dc09-402b-aa03-a854cb5b5df6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332566020 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2332566020
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3002152190
Short name T696
Test name
Test status
Simulation time 35378393 ps
CPU time 0.89 seconds
Started Jun 28 06:02:34 PM PDT 24
Finished Jun 28 06:02:40 PM PDT 24
Peak memory 219608 kb
Host smart-6e5cce12-8b40-4d91-8501-0d09771e817f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002152190 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3002152190
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2346890686
Short name T849
Test name
Test status
Simulation time 143500546 ps
CPU time 2.82 seconds
Started Jun 28 06:02:43 PM PDT 24
Finished Jun 28 06:02:51 PM PDT 24
Peak memory 215616 kb
Host smart-9d7be343-632a-4864-8db5-3f8e29134a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346890686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2346890686
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_smoke.1952061453
Short name T360
Test name
Test status
Simulation time 23711066 ps
CPU time 0.91 seconds
Started Jun 28 06:02:46 PM PDT 24
Finished Jun 28 06:02:53 PM PDT 24
Peak memory 215712 kb
Host smart-91dd432e-9137-47d7-860c-515d86f601eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952061453 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1952061453
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1181076521
Short name T884
Test name
Test status
Simulation time 155925526 ps
CPU time 2.09 seconds
Started Jun 28 06:02:35 PM PDT 24
Finished Jun 28 06:02:42 PM PDT 24
Peak memory 217652 kb
Host smart-fc21cf51-8f4b-4802-bca7-333128b0f3c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181076521 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1181076521
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1972130845
Short name T439
Test name
Test status
Simulation time 100534474952 ps
CPU time 1337.37 seconds
Started Jun 28 06:02:45 PM PDT 24
Finished Jun 28 06:25:08 PM PDT 24
Peak memory 226396 kb
Host smart-b6437679-01ba-4d92-8940-f096de53ec8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972130845 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1972130845
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert_test.1636123139
Short name T953
Test name
Test status
Simulation time 28740249 ps
CPU time 0.94 seconds
Started Jun 28 06:01:36 PM PDT 24
Finished Jun 28 06:01:39 PM PDT 24
Peak memory 207036 kb
Host smart-601ff8f5-101d-46d6-a101-f9b63b5aebe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636123139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1636123139
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1761217161
Short name T465
Test name
Test status
Simulation time 13541079 ps
CPU time 0.97 seconds
Started Jun 28 06:01:36 PM PDT 24
Finished Jun 28 06:01:40 PM PDT 24
Peak memory 215884 kb
Host smart-b25664bb-c5c2-4d74-a7b7-96ec558bb5cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761217161 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1761217161
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2685212846
Short name T593
Test name
Test status
Simulation time 76445637 ps
CPU time 1.15 seconds
Started Jun 28 06:01:42 PM PDT 24
Finished Jun 28 06:01:49 PM PDT 24
Peak memory 217344 kb
Host smart-4a593940-73b0-435e-862d-a246ab2447c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685212846 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2685212846
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.419300187
Short name T94
Test name
Test status
Simulation time 25825485 ps
CPU time 0.96 seconds
Started Jun 28 06:01:34 PM PDT 24
Finished Jun 28 06:01:36 PM PDT 24
Peak memory 219008 kb
Host smart-211e4ac9-db19-4f4a-9086-8f1c72bc7a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419300187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.419300187
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1729558881
Short name T716
Test name
Test status
Simulation time 50514314 ps
CPU time 1.82 seconds
Started Jun 28 06:01:36 PM PDT 24
Finished Jun 28 06:01:41 PM PDT 24
Peak memory 218900 kb
Host smart-91f6f2b8-58b0-40eb-8a2c-f9fc713fd523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729558881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1729558881
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2132884904
Short name T32
Test name
Test status
Simulation time 26015630 ps
CPU time 0.95 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:45 PM PDT 24
Peak memory 216100 kb
Host smart-0bfd1b5f-45de-4076-9c91-e8aac2dffbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132884904 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2132884904
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1866252572
Short name T940
Test name
Test status
Simulation time 26125489 ps
CPU time 0.98 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:46 PM PDT 24
Peak memory 207040 kb
Host smart-8544ea6f-5646-4ae9-8e4c-916b1b092c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866252572 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1866252572
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1084049381
Short name T902
Test name
Test status
Simulation time 22590746 ps
CPU time 0.92 seconds
Started Jun 28 06:01:37 PM PDT 24
Finished Jun 28 06:01:42 PM PDT 24
Peak memory 215580 kb
Host smart-9a955e27-03ea-4b87-af93-25922d0923a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084049381 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1084049381
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1194908521
Short name T814
Test name
Test status
Simulation time 153609109 ps
CPU time 3.91 seconds
Started Jun 28 06:01:35 PM PDT 24
Finished Jun 28 06:01:40 PM PDT 24
Peak memory 217532 kb
Host smart-30803249-4190-4df9-9019-eb36968410e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194908521 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1194908521
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.92370226
Short name T923
Test name
Test status
Simulation time 86799479729 ps
CPU time 1974.46 seconds
Started Jun 28 06:01:34 PM PDT 24
Finished Jun 28 06:34:29 PM PDT 24
Peak memory 226452 kb
Host smart-faec6cb3-40b6-4273-9d06-edb2f62d46c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92370226 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.92370226
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.2405708527
Short name T809
Test name
Test status
Simulation time 27480000 ps
CPU time 1.26 seconds
Started Jun 28 06:02:45 PM PDT 24
Finished Jun 28 06:02:53 PM PDT 24
Peak memory 219084 kb
Host smart-8e45621d-01e1-4ca7-b466-92510ffff67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405708527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2405708527
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.760823056
Short name T256
Test name
Test status
Simulation time 65797843 ps
CPU time 0.82 seconds
Started Jun 28 06:02:37 PM PDT 24
Finished Jun 28 06:02:43 PM PDT 24
Peak memory 218600 kb
Host smart-80dbf441-901a-4057-885c-5a6ede8fa44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760823056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.760823056
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2236216902
Short name T378
Test name
Test status
Simulation time 87883052 ps
CPU time 1.22 seconds
Started Jun 28 06:02:33 PM PDT 24
Finished Jun 28 06:02:40 PM PDT 24
Peak memory 219268 kb
Host smart-a89f72cc-17ef-4075-a24d-dd8189cc657c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236216902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2236216902
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.3674508458
Short name T410
Test name
Test status
Simulation time 24014711 ps
CPU time 1.18 seconds
Started Jun 28 06:02:44 PM PDT 24
Finished Jun 28 06:02:51 PM PDT 24
Peak memory 220104 kb
Host smart-9ff5362f-e1d4-4895-b75e-c61a4a2f278b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674508458 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.3674508458
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.167064327
Short name T142
Test name
Test status
Simulation time 38758605 ps
CPU time 1.1 seconds
Started Jun 28 06:02:50 PM PDT 24
Finished Jun 28 06:02:57 PM PDT 24
Peak memory 220128 kb
Host smart-1c11f8a0-6b72-41cc-8c61-45e59e735d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167064327 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.167064327
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.128933462
Short name T786
Test name
Test status
Simulation time 29221831 ps
CPU time 1.25 seconds
Started Jun 28 06:02:35 PM PDT 24
Finished Jun 28 06:02:41 PM PDT 24
Peak memory 217584 kb
Host smart-b5166c57-684d-4e62-81e4-e26b2ac580ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128933462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.128933462
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.2420412898
Short name T810
Test name
Test status
Simulation time 50620258 ps
CPU time 1.24 seconds
Started Jun 28 06:02:40 PM PDT 24
Finished Jun 28 06:02:45 PM PDT 24
Peak memory 220124 kb
Host smart-4deb82d4-0bba-4c36-8d34-ed3502ca5882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420412898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.2420412898
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.3346296696
Short name T157
Test name
Test status
Simulation time 54668136 ps
CPU time 1.19 seconds
Started Jun 28 06:02:44 PM PDT 24
Finished Jun 28 06:02:51 PM PDT 24
Peak memory 230092 kb
Host smart-5d6435dc-7270-43b5-9d96-4139fd757bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346296696 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3346296696
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3770186841
Short name T76
Test name
Test status
Simulation time 38793392 ps
CPU time 1.55 seconds
Started Jun 28 06:02:43 PM PDT 24
Finished Jun 28 06:02:49 PM PDT 24
Peak memory 218888 kb
Host smart-d82d0379-4922-4d6c-a5e3-437c3dca4810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770186841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3770186841
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.327328788
Short name T755
Test name
Test status
Simulation time 115993147 ps
CPU time 1.29 seconds
Started Jun 28 06:02:42 PM PDT 24
Finished Jun 28 06:02:48 PM PDT 24
Peak memory 220132 kb
Host smart-3474d617-986a-40fa-9087-d87d9f43ba6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327328788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.327328788
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.1525492139
Short name T425
Test name
Test status
Simulation time 52663338 ps
CPU time 0.98 seconds
Started Jun 28 06:02:38 PM PDT 24
Finished Jun 28 06:02:43 PM PDT 24
Peak memory 224008 kb
Host smart-959c9898-ae09-494a-9ecc-aea415d4cde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525492139 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1525492139
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.4122664503
Short name T328
Test name
Test status
Simulation time 96221666 ps
CPU time 1.1 seconds
Started Jun 28 06:02:43 PM PDT 24
Finished Jun 28 06:02:50 PM PDT 24
Peak memory 217880 kb
Host smart-d6dc0e89-2ada-4c71-951b-71c61ba58ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122664503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.4122664503
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.2466932880
Short name T685
Test name
Test status
Simulation time 30828750 ps
CPU time 1.25 seconds
Started Jun 28 06:02:45 PM PDT 24
Finished Jun 28 06:02:53 PM PDT 24
Peak memory 220012 kb
Host smart-afa1e48d-9929-48e0-b30a-7b5ceab5db78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466932880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.2466932880
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.1347913533
Short name T131
Test name
Test status
Simulation time 20695491 ps
CPU time 1.28 seconds
Started Jun 28 06:02:41 PM PDT 24
Finished Jun 28 06:02:46 PM PDT 24
Peak memory 230068 kb
Host smart-4554ebc6-4931-4ea0-862d-40d74b3e65f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347913533 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1347913533
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.70906932
Short name T504
Test name
Test status
Simulation time 93972558 ps
CPU time 1.62 seconds
Started Jun 28 06:02:39 PM PDT 24
Finished Jun 28 06:02:45 PM PDT 24
Peak memory 219036 kb
Host smart-ee4daf1e-9cb7-4efb-864e-0c92e494c74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70906932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.70906932
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.951626428
Short name T650
Test name
Test status
Simulation time 56618457 ps
CPU time 1.15 seconds
Started Jun 28 06:02:42 PM PDT 24
Finished Jun 28 06:02:47 PM PDT 24
Peak memory 220944 kb
Host smart-93873025-c928-4fff-adcc-5e5eb6a1984a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951626428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.951626428
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2524010252
Short name T387
Test name
Test status
Simulation time 19587928 ps
CPU time 1.08 seconds
Started Jun 28 06:02:36 PM PDT 24
Finished Jun 28 06:02:42 PM PDT 24
Peak memory 218676 kb
Host smart-9ab46fa8-a4a6-4510-b83c-b5ad74c72503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524010252 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2524010252
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3561709134
Short name T845
Test name
Test status
Simulation time 50380731 ps
CPU time 1.66 seconds
Started Jun 28 06:02:42 PM PDT 24
Finished Jun 28 06:02:47 PM PDT 24
Peak memory 218832 kb
Host smart-8e3d2797-6310-4468-9924-4cf8c19e064f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561709134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3561709134
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.3911870144
Short name T594
Test name
Test status
Simulation time 91132010 ps
CPU time 1.23 seconds
Started Jun 28 06:02:31 PM PDT 24
Finished Jun 28 06:02:37 PM PDT 24
Peak memory 220080 kb
Host smart-49c28bb8-9d62-47c4-8b4c-7eab267a2bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911870144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.3911870144
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.3931813268
Short name T124
Test name
Test status
Simulation time 26636091 ps
CPU time 1.16 seconds
Started Jun 28 06:02:34 PM PDT 24
Finished Jun 28 06:02:41 PM PDT 24
Peak memory 229872 kb
Host smart-955379da-6368-44af-be1d-94b3f56acac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931813268 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3931813268
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.289251533
Short name T613
Test name
Test status
Simulation time 84803523 ps
CPU time 1.86 seconds
Started Jun 28 06:02:45 PM PDT 24
Finished Jun 28 06:02:53 PM PDT 24
Peak memory 218956 kb
Host smart-163ce2e0-8e4e-46c8-aa54-615b415e1b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289251533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.289251533
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.3711803468
Short name T259
Test name
Test status
Simulation time 39505268 ps
CPU time 1.07 seconds
Started Jun 28 06:02:34 PM PDT 24
Finished Jun 28 06:02:41 PM PDT 24
Peak memory 218680 kb
Host smart-ee510c47-d7fc-4d9f-8764-272b4befa2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711803468 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.3711803468
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.1612947901
Short name T204
Test name
Test status
Simulation time 18897045 ps
CPU time 1.12 seconds
Started Jun 28 06:02:40 PM PDT 24
Finished Jun 28 06:02:45 PM PDT 24
Peak memory 218848 kb
Host smart-df24348e-8481-4819-b83b-4b789f6dbe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612947901 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1612947901
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3206619358
Short name T228
Test name
Test status
Simulation time 71172868 ps
CPU time 1.1 seconds
Started Jun 28 06:02:40 PM PDT 24
Finished Jun 28 06:02:45 PM PDT 24
Peak memory 217540 kb
Host smart-e653db51-5beb-4a47-9b16-472f2955aa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206619358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3206619358
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.2197693174
Short name T418
Test name
Test status
Simulation time 28830140 ps
CPU time 1.32 seconds
Started Jun 28 06:02:46 PM PDT 24
Finished Jun 28 06:02:54 PM PDT 24
Peak memory 221088 kb
Host smart-71ac6bc6-5c9d-489d-90a5-b079a0319b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197693174 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.2197693174
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.2732444541
Short name T162
Test name
Test status
Simulation time 36439747 ps
CPU time 1.07 seconds
Started Jun 28 06:02:53 PM PDT 24
Finished Jun 28 06:03:00 PM PDT 24
Peak memory 229904 kb
Host smart-fe9e4bed-2281-4fb9-b07d-8aef63e5640e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732444541 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2732444541
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1449715598
Short name T499
Test name
Test status
Simulation time 32797595 ps
CPU time 1.52 seconds
Started Jun 28 06:02:34 PM PDT 24
Finished Jun 28 06:02:41 PM PDT 24
Peak memory 218864 kb
Host smart-f967eee8-7354-473c-817f-2f5190af26a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449715598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1449715598
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.3643910813
Short name T813
Test name
Test status
Simulation time 24017184 ps
CPU time 1.21 seconds
Started Jun 28 06:02:45 PM PDT 24
Finished Jun 28 06:02:52 PM PDT 24
Peak memory 221328 kb
Host smart-91812cb3-593d-4a86-83ee-0a609ef2f3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643910813 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.3643910813
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.1232764036
Short name T55
Test name
Test status
Simulation time 22904068 ps
CPU time 1.08 seconds
Started Jun 28 06:02:55 PM PDT 24
Finished Jun 28 06:03:02 PM PDT 24
Peak memory 224236 kb
Host smart-13b04e0b-f57b-4d00-b692-c6477615d93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232764036 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1232764036
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3981375925
Short name T346
Test name
Test status
Simulation time 50650214 ps
CPU time 1.07 seconds
Started Jun 28 06:02:50 PM PDT 24
Finished Jun 28 06:02:57 PM PDT 24
Peak memory 219336 kb
Host smart-47939dbd-849e-4dbc-9a89-695d173dc724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981375925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3981375925
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.731058128
Short name T145
Test name
Test status
Simulation time 98591019 ps
CPU time 1.24 seconds
Started Jun 28 06:01:37 PM PDT 24
Finished Jun 28 06:01:42 PM PDT 24
Peak memory 219624 kb
Host smart-b8c54fef-cfbb-4310-a346-7d36714439fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731058128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.731058128
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2184705388
Short name T534
Test name
Test status
Simulation time 27533744 ps
CPU time 1.19 seconds
Started Jun 28 06:01:36 PM PDT 24
Finished Jun 28 06:01:40 PM PDT 24
Peak memory 207080 kb
Host smart-8b43e905-251c-42ba-8e8b-95cdbc90eb91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184705388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2184705388
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2145161840
Short name T524
Test name
Test status
Simulation time 101470545 ps
CPU time 0.91 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:45 PM PDT 24
Peak memory 215888 kb
Host smart-8f8835a6-932e-4546-bdf4-d2af20050fbb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145161840 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2145161840
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.173756720
Short name T619
Test name
Test status
Simulation time 33556607 ps
CPU time 1 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:46 PM PDT 24
Peak memory 217172 kb
Host smart-8ab9a1f7-5ed8-41fe-adfb-fb888d88faf8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173756720 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.173756720
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1861304950
Short name T61
Test name
Test status
Simulation time 29673522 ps
CPU time 1.25 seconds
Started Jun 28 06:01:36 PM PDT 24
Finished Jun 28 06:01:40 PM PDT 24
Peak memory 219920 kb
Host smart-26b26961-cfa0-42fe-8e40-d7f133fdc9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861304950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1861304950
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.312092043
Short name T608
Test name
Test status
Simulation time 59737378 ps
CPU time 1.48 seconds
Started Jun 28 06:01:35 PM PDT 24
Finished Jun 28 06:01:38 PM PDT 24
Peak memory 218900 kb
Host smart-8fe96533-abe7-4956-b0b1-a928b44928e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312092043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.312092043
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2456352486
Short name T857
Test name
Test status
Simulation time 37320397 ps
CPU time 0.93 seconds
Started Jun 28 06:01:37 PM PDT 24
Finished Jun 28 06:01:41 PM PDT 24
Peak memory 215808 kb
Host smart-0f4d9cca-6af7-4f9b-85e9-5d4006b2a427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456352486 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2456352486
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.3922285421
Short name T24
Test name
Test status
Simulation time 16447742 ps
CPU time 1.05 seconds
Started Jun 28 06:01:36 PM PDT 24
Finished Jun 28 06:01:39 PM PDT 24
Peak memory 207420 kb
Host smart-638caf0f-0794-4e7c-876f-3e954c9f8040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922285421 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3922285421
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2113286979
Short name T952
Test name
Test status
Simulation time 45118089 ps
CPU time 0.93 seconds
Started Jun 28 06:01:37 PM PDT 24
Finished Jun 28 06:01:41 PM PDT 24
Peak memory 215596 kb
Host smart-e70ddc98-2888-4921-805b-304330abdd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113286979 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2113286979
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2391035412
Short name T847
Test name
Test status
Simulation time 423377932 ps
CPU time 2.01 seconds
Started Jun 28 06:01:38 PM PDT 24
Finished Jun 28 06:01:44 PM PDT 24
Peak memory 217728 kb
Host smart-eb9d4755-f74e-4a2e-a39d-ff63792b888a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391035412 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2391035412
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1760316776
Short name T250
Test name
Test status
Simulation time 248958869251 ps
CPU time 1427.13 seconds
Started Jun 28 06:01:36 PM PDT 24
Finished Jun 28 06:25:25 PM PDT 24
Peak memory 225788 kb
Host smart-27c65113-e4bd-4b9f-8eb3-841b01d84745
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760316776 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1760316776
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.2544357194
Short name T958
Test name
Test status
Simulation time 49732798 ps
CPU time 1.07 seconds
Started Jun 28 06:02:47 PM PDT 24
Finished Jun 28 06:02:54 PM PDT 24
Peak memory 219812 kb
Host smart-a16cbeb5-02f8-48e0-a4f8-9c2ea2f71e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544357194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.2544357194
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1897842521
Short name T173
Test name
Test status
Simulation time 21516192 ps
CPU time 0.97 seconds
Started Jun 28 06:02:45 PM PDT 24
Finished Jun 28 06:02:52 PM PDT 24
Peak memory 218736 kb
Host smart-003c023f-27a5-4cc5-b49b-4c1964bc13cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897842521 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1897842521
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3502289563
Short name T945
Test name
Test status
Simulation time 80960795 ps
CPU time 1.24 seconds
Started Jun 28 06:02:53 PM PDT 24
Finished Jun 28 06:02:59 PM PDT 24
Peak memory 220204 kb
Host smart-35da32d6-3abc-4064-bc70-57fe9beade17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502289563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3502289563
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.4285741232
Short name T976
Test name
Test status
Simulation time 397570904 ps
CPU time 1.16 seconds
Started Jun 28 06:02:47 PM PDT 24
Finished Jun 28 06:02:55 PM PDT 24
Peak memory 218688 kb
Host smart-582ec5b0-5e39-4a7a-a313-2be9ac5b5d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285741232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.4285741232
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.982936095
Short name T56
Test name
Test status
Simulation time 18697320 ps
CPU time 1.16 seconds
Started Jun 28 06:02:45 PM PDT 24
Finished Jun 28 06:02:52 PM PDT 24
Peak memory 224228 kb
Host smart-bfa36e0e-cba9-4304-90d9-ed6f419c8411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982936095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.982936095
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.4583650
Short name T450
Test name
Test status
Simulation time 113321254 ps
CPU time 1.22 seconds
Started Jun 28 06:02:43 PM PDT 24
Finished Jun 28 06:02:50 PM PDT 24
Peak memory 217664 kb
Host smart-27899df7-ab6f-4d03-a2b3-8892f4017492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4583650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.4583650
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.3684557067
Short name T930
Test name
Test status
Simulation time 22457098 ps
CPU time 0.94 seconds
Started Jun 28 06:02:47 PM PDT 24
Finished Jun 28 06:02:54 PM PDT 24
Peak memory 218600 kb
Host smart-a1b5fce6-f960-41d8-9ee9-e4ef3932b197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684557067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3684557067
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2940083821
Short name T583
Test name
Test status
Simulation time 49656670 ps
CPU time 1.47 seconds
Started Jun 28 06:02:51 PM PDT 24
Finished Jun 28 06:02:59 PM PDT 24
Peak memory 219044 kb
Host smart-500f6d1f-1003-4748-9b04-ea46f5b20b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940083821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2940083821
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.309563381
Short name T83
Test name
Test status
Simulation time 30846385 ps
CPU time 1.31 seconds
Started Jun 28 06:02:52 PM PDT 24
Finished Jun 28 06:02:59 PM PDT 24
Peak memory 219872 kb
Host smart-e58a2273-a356-4c7f-ac4a-a9114e2e34e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309563381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.309563381
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.1680421985
Short name T59
Test name
Test status
Simulation time 40600413 ps
CPU time 1.03 seconds
Started Jun 28 06:02:51 PM PDT 24
Finished Jun 28 06:02:58 PM PDT 24
Peak memory 224236 kb
Host smart-86618f60-1031-4e53-9faf-76008d9457c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680421985 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1680421985
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2542775237
Short name T853
Test name
Test status
Simulation time 157787243 ps
CPU time 2.91 seconds
Started Jun 28 06:02:43 PM PDT 24
Finished Jun 28 06:02:51 PM PDT 24
Peak memory 220520 kb
Host smart-ad2aba44-8b28-4450-ad35-879231113565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542775237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2542775237
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.1750477483
Short name T551
Test name
Test status
Simulation time 22811542 ps
CPU time 1.23 seconds
Started Jun 28 06:02:53 PM PDT 24
Finished Jun 28 06:03:00 PM PDT 24
Peak memory 220884 kb
Host smart-63d735b1-c8a0-4f7a-83ee-2d83480b60af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750477483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.1750477483
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.2144178257
Short name T121
Test name
Test status
Simulation time 25701181 ps
CPU time 1.03 seconds
Started Jun 28 06:02:44 PM PDT 24
Finished Jun 28 06:02:51 PM PDT 24
Peak memory 219860 kb
Host smart-f8fdca2c-8daf-47fc-a8aa-849365b63ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144178257 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2144178257
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2695128397
Short name T889
Test name
Test status
Simulation time 320379532 ps
CPU time 1.22 seconds
Started Jun 28 06:02:46 PM PDT 24
Finished Jun 28 06:02:54 PM PDT 24
Peak memory 217596 kb
Host smart-bce3c8f4-fff4-4e8d-924e-fca411813ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695128397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2695128397
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.3702354506
Short name T441
Test name
Test status
Simulation time 27508400 ps
CPU time 1.23 seconds
Started Jun 28 06:02:50 PM PDT 24
Finished Jun 28 06:02:57 PM PDT 24
Peak memory 219904 kb
Host smart-bba33263-0d23-4b32-a204-99bcaa663f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702354506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.3702354506
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.3448271720
Short name T105
Test name
Test status
Simulation time 24885020 ps
CPU time 0.95 seconds
Started Jun 28 06:02:44 PM PDT 24
Finished Jun 28 06:02:50 PM PDT 24
Peak memory 218836 kb
Host smart-fb402d0a-91cc-4756-b63f-fccde73732e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448271720 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3448271720
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2030344871
Short name T495
Test name
Test status
Simulation time 120793314 ps
CPU time 1.09 seconds
Started Jun 28 06:02:43 PM PDT 24
Finished Jun 28 06:02:50 PM PDT 24
Peak memory 215620 kb
Host smart-69a1fbbc-96fb-4934-b318-520afb84163b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030344871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2030344871
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.2199922492
Short name T618
Test name
Test status
Simulation time 44757523 ps
CPU time 1.17 seconds
Started Jun 28 06:02:49 PM PDT 24
Finished Jun 28 06:02:56 PM PDT 24
Peak memory 219632 kb
Host smart-e01646c7-5752-4ea5-8939-82be430b59d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199922492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.2199922492
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.139993395
Short name T851
Test name
Test status
Simulation time 41808628 ps
CPU time 0.91 seconds
Started Jun 28 06:02:48 PM PDT 24
Finished Jun 28 06:02:55 PM PDT 24
Peak memory 219844 kb
Host smart-3c2792da-9e60-40ed-9ff5-d5693e438f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139993395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.139993395
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1868182784
Short name T297
Test name
Test status
Simulation time 75486974 ps
CPU time 0.96 seconds
Started Jun 28 06:02:53 PM PDT 24
Finished Jun 28 06:02:59 PM PDT 24
Peak memory 217552 kb
Host smart-a58fcf73-51d6-4804-a9bc-993c5bdefbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868182784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1868182784
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.836272180
Short name T876
Test name
Test status
Simulation time 24708754 ps
CPU time 1.18 seconds
Started Jun 28 06:02:45 PM PDT 24
Finished Jun 28 06:02:53 PM PDT 24
Peak memory 219016 kb
Host smart-9aaf3a34-5bd7-447b-8c93-c66380b3406f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836272180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.836272180
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.2181076221
Short name T57
Test name
Test status
Simulation time 28266930 ps
CPU time 1 seconds
Started Jun 28 06:02:49 PM PDT 24
Finished Jun 28 06:02:56 PM PDT 24
Peak memory 224092 kb
Host smart-7bde0450-20e2-43a6-a17b-98b4a22d3537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181076221 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2181076221
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.86935959
Short name T959
Test name
Test status
Simulation time 72242216 ps
CPU time 1.47 seconds
Started Jun 28 06:02:45 PM PDT 24
Finished Jun 28 06:02:52 PM PDT 24
Peak memory 218340 kb
Host smart-da01469e-5f82-4972-9833-732e12c8f5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86935959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.86935959
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.3528971768
Short name T796
Test name
Test status
Simulation time 41399612 ps
CPU time 1.15 seconds
Started Jun 28 06:02:53 PM PDT 24
Finished Jun 28 06:03:00 PM PDT 24
Peak memory 219032 kb
Host smart-a91eb239-12e3-4b2e-b3f0-17439a8df3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528971768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.3528971768
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.301894330
Short name T730
Test name
Test status
Simulation time 60116848 ps
CPU time 1.24 seconds
Started Jun 28 06:02:43 PM PDT 24
Finished Jun 28 06:02:50 PM PDT 24
Peak memory 219876 kb
Host smart-0db99bcb-3bf7-4030-bea6-406c2cb0d82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301894330 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.301894330
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1516650253
Short name T973
Test name
Test status
Simulation time 54254039 ps
CPU time 1.27 seconds
Started Jun 28 06:02:52 PM PDT 24
Finished Jun 28 06:02:59 PM PDT 24
Peak memory 217764 kb
Host smart-135d356a-998a-40a0-b8c6-c398bccf0d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516650253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1516650253
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.3917688925
Short name T78
Test name
Test status
Simulation time 48661732 ps
CPU time 1.21 seconds
Started Jun 28 06:02:44 PM PDT 24
Finished Jun 28 06:02:51 PM PDT 24
Peak memory 219872 kb
Host smart-96794635-4350-428b-9f59-a42fa4144299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917688925 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.3917688925
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.307952651
Short name T808
Test name
Test status
Simulation time 18182515 ps
CPU time 1.06 seconds
Started Jun 28 06:02:46 PM PDT 24
Finished Jun 28 06:02:53 PM PDT 24
Peak memory 218984 kb
Host smart-1fd14fe6-84d7-4df1-9c46-1e958e1296f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307952651 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.307952651
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.4247779162
Short name T644
Test name
Test status
Simulation time 108919512 ps
CPU time 3.08 seconds
Started Jun 28 06:02:53 PM PDT 24
Finished Jun 28 06:03:02 PM PDT 24
Peak memory 220336 kb
Host smart-b56f6e30-f2cd-4862-b54f-df4c543ad460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247779162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.4247779162
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1670889711
Short name T434
Test name
Test status
Simulation time 28914591 ps
CPU time 1.28 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:45 PM PDT 24
Peak memory 218892 kb
Host smart-8c322538-dd87-469e-94da-8d5696442df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670889711 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1670889711
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1595054073
Short name T561
Test name
Test status
Simulation time 18387762 ps
CPU time 1 seconds
Started Jun 28 06:01:44 PM PDT 24
Finished Jun 28 06:01:50 PM PDT 24
Peak memory 215452 kb
Host smart-abb83491-0e65-4944-82c4-03c5e4f28289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595054073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1595054073
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1768972830
Short name T863
Test name
Test status
Simulation time 25660126 ps
CPU time 0.84 seconds
Started Jun 28 06:01:40 PM PDT 24
Finished Jun 28 06:01:47 PM PDT 24
Peak memory 215736 kb
Host smart-bb52bde0-7242-4798-850d-0fed523d0e41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768972830 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1768972830
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2583643841
Short name T750
Test name
Test status
Simulation time 88334417 ps
CPU time 1.1 seconds
Started Jun 28 06:01:38 PM PDT 24
Finished Jun 28 06:01:43 PM PDT 24
Peak memory 217216 kb
Host smart-3c5657a0-2eac-470b-9891-c9d45dc16347
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583643841 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2583643841
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3817390889
Short name T941
Test name
Test status
Simulation time 93696175 ps
CPU time 1.14 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:45 PM PDT 24
Peak memory 224240 kb
Host smart-bba84e9f-63d7-44f0-8fc7-cb3bac7d5346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817390889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3817390889
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2002026973
Short name T552
Test name
Test status
Simulation time 86417351 ps
CPU time 1.27 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:45 PM PDT 24
Peak memory 219676 kb
Host smart-5cc6f240-d8bc-481e-8e05-76da4b732b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002026973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2002026973
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1597749939
Short name T910
Test name
Test status
Simulation time 24224790 ps
CPU time 1.2 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:44 PM PDT 24
Peak memory 224296 kb
Host smart-b68cfc75-b69a-4931-b881-6a387bdbd9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597749939 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1597749939
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3041920307
Short name T722
Test name
Test status
Simulation time 55390479 ps
CPU time 0.92 seconds
Started Jun 28 06:01:38 PM PDT 24
Finished Jun 28 06:01:44 PM PDT 24
Peak memory 207416 kb
Host smart-162600f0-5ff6-44db-9df2-19374ee09361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041920307 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3041920307
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.4157911214
Short name T362
Test name
Test status
Simulation time 50696244 ps
CPU time 0.96 seconds
Started Jun 28 06:01:37 PM PDT 24
Finished Jun 28 06:01:41 PM PDT 24
Peak memory 215612 kb
Host smart-47d85b18-696c-4ce8-8df4-62ba970eb9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157911214 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.4157911214
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1687285258
Short name T201
Test name
Test status
Simulation time 320322892 ps
CPU time 6.3 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:50 PM PDT 24
Peak memory 217384 kb
Host smart-0a1780f0-214d-4a6a-9f72-41d3c4c5f835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687285258 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1687285258
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/70.edn_alert.711658825
Short name T287
Test name
Test status
Simulation time 92887826 ps
CPU time 1.22 seconds
Started Jun 28 06:02:54 PM PDT 24
Finished Jun 28 06:03:01 PM PDT 24
Peak memory 220584 kb
Host smart-93732ba2-3f4c-425b-8e69-d714a158d780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711658825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.711658825
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.986989825
Short name T359
Test name
Test status
Simulation time 25466405 ps
CPU time 1.16 seconds
Started Jun 28 06:02:45 PM PDT 24
Finished Jun 28 06:02:51 PM PDT 24
Peak memory 218456 kb
Host smart-81fb1fd8-039b-4d21-9823-3b5ddf3f677d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986989825 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.986989825
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3295622744
Short name T921
Test name
Test status
Simulation time 53786427 ps
CPU time 1.48 seconds
Started Jun 28 06:02:50 PM PDT 24
Finished Jun 28 06:02:57 PM PDT 24
Peak memory 218944 kb
Host smart-b4500b9e-6f72-4fd5-bb60-de84741fda2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295622744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3295622744
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.1049455798
Short name T540
Test name
Test status
Simulation time 53789383 ps
CPU time 1.23 seconds
Started Jun 28 06:02:51 PM PDT 24
Finished Jun 28 06:02:58 PM PDT 24
Peak memory 219188 kb
Host smart-512493e5-3dd1-4a1a-806c-9e3651b2ff61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049455798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.1049455798
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.379129811
Short name T962
Test name
Test status
Simulation time 41734543 ps
CPU time 1.2 seconds
Started Jun 28 06:02:43 PM PDT 24
Finished Jun 28 06:02:49 PM PDT 24
Peak memory 225228 kb
Host smart-76f059d1-2dfe-43a5-bcf4-26fa66f60cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379129811 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.379129811
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2992678092
Short name T873
Test name
Test status
Simulation time 247963163 ps
CPU time 3.36 seconds
Started Jun 28 06:02:41 PM PDT 24
Finished Jun 28 06:02:48 PM PDT 24
Peak memory 220668 kb
Host smart-a4d6f697-7ce2-4905-9e42-110b1b131be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992678092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2992678092
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.1536779681
Short name T546
Test name
Test status
Simulation time 71683308 ps
CPU time 1.14 seconds
Started Jun 28 06:02:49 PM PDT 24
Finished Jun 28 06:02:57 PM PDT 24
Peak memory 219824 kb
Host smart-e5170a1c-01ca-4bdb-a15f-5b3ef6097680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536779681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.1536779681
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3310055873
Short name T869
Test name
Test status
Simulation time 25914723 ps
CPU time 1.02 seconds
Started Jun 28 06:02:51 PM PDT 24
Finished Jun 28 06:02:58 PM PDT 24
Peak memory 219944 kb
Host smart-93f1b455-5a20-4651-851e-492826c64187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310055873 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3310055873
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2788783782
Short name T778
Test name
Test status
Simulation time 33270145 ps
CPU time 1.36 seconds
Started Jun 28 06:02:44 PM PDT 24
Finished Jun 28 06:02:50 PM PDT 24
Peak memory 217720 kb
Host smart-027dc669-7161-46bd-9eff-cf03f12ee8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788783782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2788783782
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.1590197969
Short name T464
Test name
Test status
Simulation time 59238559 ps
CPU time 1.13 seconds
Started Jun 28 06:02:54 PM PDT 24
Finished Jun 28 06:03:00 PM PDT 24
Peak memory 220172 kb
Host smart-7fa8bd79-d474-4ee6-9018-8e64a861ac26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590197969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.1590197969
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.3459167627
Short name T122
Test name
Test status
Simulation time 33810478 ps
CPU time 1.25 seconds
Started Jun 28 06:02:51 PM PDT 24
Finished Jun 28 06:02:58 PM PDT 24
Peak memory 229932 kb
Host smart-53a9e800-2621-471b-8dc3-908903cbfe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459167627 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3459167627
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3498383819
Short name T986
Test name
Test status
Simulation time 67135340 ps
CPU time 1.64 seconds
Started Jun 28 06:02:50 PM PDT 24
Finished Jun 28 06:02:57 PM PDT 24
Peak memory 219292 kb
Host smart-0dcf5c8b-7969-4570-ade2-b0a6feda66dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498383819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3498383819
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.4217845031
Short name T71
Test name
Test status
Simulation time 209800766 ps
CPU time 1.32 seconds
Started Jun 28 06:02:42 PM PDT 24
Finished Jun 28 06:02:48 PM PDT 24
Peak memory 219708 kb
Host smart-99e4c238-6485-4bbb-9df2-a09d714bdba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217845031 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.4217845031
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.3352681773
Short name T180
Test name
Test status
Simulation time 18025439 ps
CPU time 1.1 seconds
Started Jun 28 06:02:49 PM PDT 24
Finished Jun 28 06:02:57 PM PDT 24
Peak memory 218600 kb
Host smart-714e7f53-46df-422b-9c39-fd22310d9694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352681773 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3352681773
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1547663981
Short name T627
Test name
Test status
Simulation time 32256254 ps
CPU time 1.54 seconds
Started Jun 28 06:02:45 PM PDT 24
Finished Jun 28 06:02:52 PM PDT 24
Peak memory 217772 kb
Host smart-a108dfb0-6054-48c7-bb66-7601a256c46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547663981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1547663981
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.263582343
Short name T178
Test name
Test status
Simulation time 69412420 ps
CPU time 1.12 seconds
Started Jun 28 06:02:46 PM PDT 24
Finished Jun 28 06:02:53 PM PDT 24
Peak memory 218772 kb
Host smart-5f0459fc-283a-4143-80c0-f0ba0f56efce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263582343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.263582343
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.3027697348
Short name T155
Test name
Test status
Simulation time 20214358 ps
CPU time 1.15 seconds
Started Jun 28 06:02:43 PM PDT 24
Finished Jun 28 06:02:50 PM PDT 24
Peak memory 219940 kb
Host smart-2ac9b5f2-97b7-43d1-a433-92a212f826b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027697348 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3027697348
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/76.edn_alert.3115337727
Short name T585
Test name
Test status
Simulation time 44527782 ps
CPU time 1.23 seconds
Started Jun 28 06:02:51 PM PDT 24
Finished Jun 28 06:02:58 PM PDT 24
Peak memory 221008 kb
Host smart-8ce422a5-8696-48ad-8ff6-0b122a470fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115337727 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.3115337727
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.2229202305
Short name T156
Test name
Test status
Simulation time 22826854 ps
CPU time 1.03 seconds
Started Jun 28 06:02:49 PM PDT 24
Finished Jun 28 06:02:56 PM PDT 24
Peak memory 219884 kb
Host smart-75445e82-ce29-4f02-8d69-5c266be1ad70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229202305 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2229202305
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.336461153
Short name T386
Test name
Test status
Simulation time 84838296 ps
CPU time 1.38 seconds
Started Jun 28 06:02:45 PM PDT 24
Finished Jun 28 06:02:52 PM PDT 24
Peak memory 218964 kb
Host smart-a4d70c15-ce52-4d09-af02-0da752e2de26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336461153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.336461153
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.2542487111
Short name T658
Test name
Test status
Simulation time 28838972 ps
CPU time 1.28 seconds
Started Jun 28 06:02:49 PM PDT 24
Finished Jun 28 06:02:56 PM PDT 24
Peak memory 218856 kb
Host smart-10bf073c-5383-43aa-82e0-a78520ff0330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542487111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.2542487111
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.868241418
Short name T622
Test name
Test status
Simulation time 19189867 ps
CPU time 1.23 seconds
Started Jun 28 06:02:48 PM PDT 24
Finished Jun 28 06:02:56 PM PDT 24
Peak memory 224420 kb
Host smart-6070681e-446d-456d-b1ca-79c6857fecef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868241418 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.868241418
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.263666871
Short name T380
Test name
Test status
Simulation time 63100324 ps
CPU time 1.48 seconds
Started Jun 28 06:02:44 PM PDT 24
Finished Jun 28 06:02:51 PM PDT 24
Peak memory 218792 kb
Host smart-69e0f008-57ef-4426-9f30-625ca05bba10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263666871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.263666871
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.3582612375
Short name T243
Test name
Test status
Simulation time 76177053 ps
CPU time 1.1 seconds
Started Jun 28 06:02:53 PM PDT 24
Finished Jun 28 06:03:00 PM PDT 24
Peak memory 219824 kb
Host smart-4680fea2-ea88-4775-a2ea-8b238d627e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582612375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.3582612375
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.2260433464
Short name T865
Test name
Test status
Simulation time 51177813 ps
CPU time 1.06 seconds
Started Jun 28 06:02:43 PM PDT 24
Finished Jun 28 06:02:50 PM PDT 24
Peak memory 220772 kb
Host smart-a4292f4f-48eb-4a46-944b-67e4d20356b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260433464 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2260433464
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.4185180568
Short name T409
Test name
Test status
Simulation time 37437856 ps
CPU time 1.36 seconds
Started Jun 28 06:02:54 PM PDT 24
Finished Jun 28 06:03:01 PM PDT 24
Peak memory 218972 kb
Host smart-e86a9018-6607-4a21-a64c-f97e9d08dedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185180568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.4185180568
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.3559997072
Short name T987
Test name
Test status
Simulation time 48333604 ps
CPU time 1.25 seconds
Started Jun 28 06:02:51 PM PDT 24
Finished Jun 28 06:02:58 PM PDT 24
Peak memory 219024 kb
Host smart-d3d5f704-fc52-4909-9169-881777e953da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559997072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.3559997072
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.958685387
Short name T133
Test name
Test status
Simulation time 62063338 ps
CPU time 1.14 seconds
Started Jun 28 06:02:53 PM PDT 24
Finished Jun 28 06:03:00 PM PDT 24
Peak memory 220804 kb
Host smart-4b2bc7f0-5f71-482d-8649-268079a7d378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958685387 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.958685387
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.4105548214
Short name T739
Test name
Test status
Simulation time 35213572 ps
CPU time 1.46 seconds
Started Jun 28 06:02:44 PM PDT 24
Finished Jun 28 06:02:51 PM PDT 24
Peak memory 217636 kb
Host smart-675fac49-1efe-457b-84e3-409405a00da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105548214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.4105548214
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.602858014
Short name T850
Test name
Test status
Simulation time 53929943 ps
CPU time 1.24 seconds
Started Jun 28 06:01:34 PM PDT 24
Finished Jun 28 06:01:37 PM PDT 24
Peak memory 218852 kb
Host smart-ec8216c5-193f-4201-b236-e0bc9a3c0bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602858014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.602858014
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2465474422
Short name T977
Test name
Test status
Simulation time 13098754 ps
CPU time 0.92 seconds
Started Jun 28 06:01:42 PM PDT 24
Finished Jun 28 06:01:49 PM PDT 24
Peak memory 215440 kb
Host smart-1bfdca1b-cb36-4abf-a791-fcd6d62c9a23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465474422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2465474422
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2000072229
Short name T481
Test name
Test status
Simulation time 12091552 ps
CPU time 0.92 seconds
Started Jun 28 06:01:43 PM PDT 24
Finished Jun 28 06:01:49 PM PDT 24
Peak memory 216548 kb
Host smart-33dcbb24-945d-4053-a5db-c8283d4e1c44
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000072229 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2000072229
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1904134722
Short name T760
Test name
Test status
Simulation time 54845642 ps
CPU time 1.12 seconds
Started Jun 28 06:01:40 PM PDT 24
Finished Jun 28 06:01:47 PM PDT 24
Peak memory 218512 kb
Host smart-b1567c62-d1cf-461d-9188-0c6e367ff644
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904134722 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1904134722
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2201450898
Short name T871
Test name
Test status
Simulation time 22409624 ps
CPU time 1.04 seconds
Started Jun 28 06:01:38 PM PDT 24
Finished Jun 28 06:01:43 PM PDT 24
Peak memory 218820 kb
Host smart-6e7f08dc-86a8-4aa8-9e71-b6410aaa9e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201450898 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2201450898
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.350577499
Short name T521
Test name
Test status
Simulation time 211957094 ps
CPU time 1.3 seconds
Started Jun 28 06:01:37 PM PDT 24
Finished Jun 28 06:01:41 PM PDT 24
Peak memory 217668 kb
Host smart-0bd181b9-eb64-4d1d-9510-90bd994312bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350577499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.350577499
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1726312968
Short name T915
Test name
Test status
Simulation time 24891155 ps
CPU time 0.99 seconds
Started Jun 28 06:01:38 PM PDT 24
Finished Jun 28 06:01:44 PM PDT 24
Peak memory 216076 kb
Host smart-f588ace0-2041-40e9-96e0-5d4fd1569b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726312968 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1726312968
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1851457798
Short name T711
Test name
Test status
Simulation time 36209799 ps
CPU time 0.93 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:45 PM PDT 24
Peak memory 207408 kb
Host smart-366485b9-bba2-4479-98fa-89bd3c0d7a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851457798 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1851457798
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1176767524
Short name T516
Test name
Test status
Simulation time 29699952 ps
CPU time 1.01 seconds
Started Jun 28 06:01:42 PM PDT 24
Finished Jun 28 06:01:49 PM PDT 24
Peak memory 215612 kb
Host smart-eadb5f09-e595-4080-b1c6-282fed457018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176767524 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1176767524
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1427904165
Short name T777
Test name
Test status
Simulation time 309701678 ps
CPU time 6.21 seconds
Started Jun 28 06:01:43 PM PDT 24
Finished Jun 28 06:01:55 PM PDT 24
Peak memory 215824 kb
Host smart-b7bd9bff-3932-4646-8ff5-6ed728b188ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427904165 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1427904165
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/80.edn_alert.2804131645
Short name T179
Test name
Test status
Simulation time 44277519 ps
CPU time 1.21 seconds
Started Jun 28 06:02:51 PM PDT 24
Finished Jun 28 06:02:58 PM PDT 24
Peak memory 216092 kb
Host smart-4c611e15-cd7f-42bc-949c-ccc5461521f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804131645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2804131645
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.4227867372
Short name T723
Test name
Test status
Simulation time 45184806 ps
CPU time 1.24 seconds
Started Jun 28 06:02:47 PM PDT 24
Finished Jun 28 06:02:55 PM PDT 24
Peak memory 226068 kb
Host smart-af984de7-1c4d-460e-831e-bf6ef5acbf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227867372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.4227867372
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1526638096
Short name T415
Test name
Test status
Simulation time 39502097 ps
CPU time 1.22 seconds
Started Jun 28 06:02:51 PM PDT 24
Finished Jun 28 06:02:58 PM PDT 24
Peak memory 218980 kb
Host smart-0b2d5bdf-b14f-4ca3-b432-c5d213f7006a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526638096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1526638096
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1496653266
Short name T108
Test name
Test status
Simulation time 77947814 ps
CPU time 1.17 seconds
Started Jun 28 06:02:51 PM PDT 24
Finished Jun 28 06:02:58 PM PDT 24
Peak memory 218700 kb
Host smart-1a67df74-18df-4bf7-a1bd-8ae0168e5d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496653266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1496653266
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.3340288976
Short name T896
Test name
Test status
Simulation time 44847814 ps
CPU time 0.93 seconds
Started Jun 28 06:02:50 PM PDT 24
Finished Jun 28 06:02:57 PM PDT 24
Peak memory 219976 kb
Host smart-ed65391c-8270-4c17-abb0-c4715ca0d239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340288976 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3340288976
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3291557752
Short name T420
Test name
Test status
Simulation time 84899545 ps
CPU time 1.13 seconds
Started Jun 28 06:02:51 PM PDT 24
Finished Jun 28 06:02:58 PM PDT 24
Peak memory 217744 kb
Host smart-f0b40dc6-2841-448e-9922-8e7b198d9aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291557752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3291557752
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.3067422960
Short name T159
Test name
Test status
Simulation time 95834074 ps
CPU time 1.3 seconds
Started Jun 28 06:02:50 PM PDT 24
Finished Jun 28 06:02:57 PM PDT 24
Peak memory 220104 kb
Host smart-17f740d4-75e0-4ad4-996e-d3ac3e6f2769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067422960 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.3067422960
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.95147438
Short name T208
Test name
Test status
Simulation time 30619071 ps
CPU time 1.26 seconds
Started Jun 28 06:02:50 PM PDT 24
Finished Jun 28 06:02:57 PM PDT 24
Peak memory 220156 kb
Host smart-e67b09b9-3b8e-4420-a350-9f2fc65ec458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95147438 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.95147438
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3166064368
Short name T639
Test name
Test status
Simulation time 56653184 ps
CPU time 1.29 seconds
Started Jun 28 06:02:42 PM PDT 24
Finished Jun 28 06:02:48 PM PDT 24
Peak memory 220344 kb
Host smart-09ddc25b-5752-4539-bc5d-f371ba648f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166064368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3166064368
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.2272230863
Short name T697
Test name
Test status
Simulation time 152930403 ps
CPU time 1.29 seconds
Started Jun 28 06:02:46 PM PDT 24
Finished Jun 28 06:02:54 PM PDT 24
Peak memory 215972 kb
Host smart-8b07b76b-3dd2-41a1-b575-cf06c8264a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272230863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.2272230863
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.2015121440
Short name T174
Test name
Test status
Simulation time 25637961 ps
CPU time 1.08 seconds
Started Jun 28 06:02:44 PM PDT 24
Finished Jun 28 06:02:51 PM PDT 24
Peak memory 224332 kb
Host smart-20070098-59b2-41b2-a010-12b5b89d27b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015121440 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2015121440
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3651566339
Short name T653
Test name
Test status
Simulation time 360981994 ps
CPU time 3.12 seconds
Started Jun 28 06:02:51 PM PDT 24
Finished Jun 28 06:03:00 PM PDT 24
Peak memory 220620 kb
Host smart-22243bac-bd85-484f-b46b-14f8c69747e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651566339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3651566339
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.1754039405
Short name T864
Test name
Test status
Simulation time 26817741 ps
CPU time 1.24 seconds
Started Jun 28 06:03:01 PM PDT 24
Finished Jun 28 06:03:08 PM PDT 24
Peak memory 221220 kb
Host smart-aa0b359f-3efe-437b-a2a8-d0d00ec379c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754039405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.1754039405
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.2616224791
Short name T186
Test name
Test status
Simulation time 31420612 ps
CPU time 0.9 seconds
Started Jun 28 06:02:58 PM PDT 24
Finished Jun 28 06:03:04 PM PDT 24
Peak memory 218532 kb
Host smart-324250a8-6ab9-4053-8a92-2d7472193674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616224791 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2616224791
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2389422660
Short name T569
Test name
Test status
Simulation time 32305539 ps
CPU time 1.15 seconds
Started Jun 28 06:03:00 PM PDT 24
Finished Jun 28 06:03:08 PM PDT 24
Peak memory 217620 kb
Host smart-ebf16e3c-ffc6-4d22-882a-699f052b59c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389422660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2389422660
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.3358933639
Short name T631
Test name
Test status
Simulation time 23580649 ps
CPU time 1.12 seconds
Started Jun 28 06:02:56 PM PDT 24
Finished Jun 28 06:03:03 PM PDT 24
Peak memory 219916 kb
Host smart-a9177844-882b-4951-b1a9-c5efc6febf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358933639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.3358933639
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1524754356
Short name T454
Test name
Test status
Simulation time 29832218 ps
CPU time 0.88 seconds
Started Jun 28 06:02:57 PM PDT 24
Finished Jun 28 06:03:03 PM PDT 24
Peak memory 218712 kb
Host smart-74ec256c-d954-4db5-ba69-78c9ab537a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524754356 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1524754356
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3883810966
Short name T666
Test name
Test status
Simulation time 64176878 ps
CPU time 1.24 seconds
Started Jun 28 06:02:59 PM PDT 24
Finished Jun 28 06:03:05 PM PDT 24
Peak memory 219320 kb
Host smart-ffb9186a-98b2-42fc-83b1-26c44f242813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883810966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3883810966
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.267698859
Short name T929
Test name
Test status
Simulation time 88298354 ps
CPU time 1.25 seconds
Started Jun 28 06:02:59 PM PDT 24
Finished Jun 28 06:03:06 PM PDT 24
Peak memory 218748 kb
Host smart-292e48de-c07e-4c2c-bf70-49e55c8c06ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267698859 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.267698859
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.4216826385
Short name T970
Test name
Test status
Simulation time 25837441 ps
CPU time 0.96 seconds
Started Jun 28 06:02:57 PM PDT 24
Finished Jun 28 06:03:03 PM PDT 24
Peak memory 218816 kb
Host smart-9ecb4c4e-095a-42b0-a0b5-82305c21f5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216826385 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.4216826385
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.4074679329
Short name T507
Test name
Test status
Simulation time 56318877 ps
CPU time 1.3 seconds
Started Jun 28 06:03:00 PM PDT 24
Finished Jun 28 06:03:08 PM PDT 24
Peak memory 220136 kb
Host smart-24a04bf2-dbb0-4075-a124-d8dadf9f71fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074679329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.4074679329
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.4263184137
Short name T429
Test name
Test status
Simulation time 91823995 ps
CPU time 1.07 seconds
Started Jun 28 06:03:02 PM PDT 24
Finished Jun 28 06:03:11 PM PDT 24
Peak memory 220136 kb
Host smart-91005d9a-15fd-478a-a4f2-57db3577876b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263184137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.4263184137
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.2662713640
Short name T140
Test name
Test status
Simulation time 56349833 ps
CPU time 1.06 seconds
Started Jun 28 06:02:59 PM PDT 24
Finished Jun 28 06:03:05 PM PDT 24
Peak memory 220008 kb
Host smart-28dfe9db-e55b-4898-9595-541acb7cf69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662713640 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2662713640
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.1141984295
Short name T245
Test name
Test status
Simulation time 37398230 ps
CPU time 1.38 seconds
Started Jun 28 06:03:02 PM PDT 24
Finished Jun 28 06:03:10 PM PDT 24
Peak memory 219096 kb
Host smart-0baf1328-2980-46d1-a168-f4c3d5bae680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141984295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1141984295
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.3206261582
Short name T946
Test name
Test status
Simulation time 77991820 ps
CPU time 1.23 seconds
Started Jun 28 06:03:03 PM PDT 24
Finished Jun 28 06:03:12 PM PDT 24
Peak memory 219060 kb
Host smart-99198c47-44b9-4ba7-918e-36b6e767e008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206261582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.3206261582
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.311660890
Short name T456
Test name
Test status
Simulation time 19121745 ps
CPU time 1.17 seconds
Started Jun 28 06:02:58 PM PDT 24
Finished Jun 28 06:03:04 PM PDT 24
Peak memory 224256 kb
Host smart-463f4b78-de0d-4295-9b14-65017bf37e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311660890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.311660890
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1515786387
Short name T326
Test name
Test status
Simulation time 35497928 ps
CPU time 1.32 seconds
Started Jun 28 06:03:00 PM PDT 24
Finished Jun 28 06:03:08 PM PDT 24
Peak memory 220116 kb
Host smart-05a8366d-a71e-4455-9612-da6d689f0d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515786387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1515786387
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.385971244
Short name T82
Test name
Test status
Simulation time 99358119 ps
CPU time 1.4 seconds
Started Jun 28 06:02:59 PM PDT 24
Finished Jun 28 06:03:06 PM PDT 24
Peak memory 220256 kb
Host smart-cf8c6f4c-0033-4443-b12e-ba0347d905eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385971244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.385971244
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.2641407168
Short name T101
Test name
Test status
Simulation time 36206224 ps
CPU time 1.09 seconds
Started Jun 28 06:03:03 PM PDT 24
Finished Jun 28 06:03:12 PM PDT 24
Peak memory 220084 kb
Host smart-6aceb8b1-153e-437c-9961-1d1e5c67cc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641407168 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2641407168
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3340673015
Short name T400
Test name
Test status
Simulation time 50994509 ps
CPU time 1.54 seconds
Started Jun 28 06:03:01 PM PDT 24
Finished Jun 28 06:03:09 PM PDT 24
Peak memory 218872 kb
Host smart-45f04297-b1a2-481e-8331-8042c7167983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340673015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3340673015
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1535264907
Short name T680
Test name
Test status
Simulation time 37738417 ps
CPU time 1.21 seconds
Started Jun 28 06:01:41 PM PDT 24
Finished Jun 28 06:01:48 PM PDT 24
Peak memory 219276 kb
Host smart-cb3d32ea-58ad-4464-9f0e-668b300a6760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535264907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1535264907
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.264187525
Short name T550
Test name
Test status
Simulation time 93217856 ps
CPU time 0.91 seconds
Started Jun 28 06:01:41 PM PDT 24
Finished Jun 28 06:01:48 PM PDT 24
Peak memory 207008 kb
Host smart-9ff39247-04f2-4985-aaed-349803c4ad7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264187525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.264187525
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3649716087
Short name T206
Test name
Test status
Simulation time 33716420 ps
CPU time 0.92 seconds
Started Jun 28 06:01:47 PM PDT 24
Finished Jun 28 06:01:52 PM PDT 24
Peak memory 216636 kb
Host smart-7c31c059-fa44-4b39-a68f-b07338c017e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649716087 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3649716087
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.2575597773
Short name T134
Test name
Test status
Simulation time 135019592 ps
CPU time 1.06 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:01:46 PM PDT 24
Peak memory 217356 kb
Host smart-8a6309f2-623b-4c38-a0b0-f0888832bd7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575597773 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.2575597773
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.4188602912
Short name T161
Test name
Test status
Simulation time 25645762 ps
CPU time 1.33 seconds
Started Jun 28 06:01:51 PM PDT 24
Finished Jun 28 06:01:59 PM PDT 24
Peak memory 230000 kb
Host smart-33af52e2-7444-466e-a0d4-cd8514e080f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188602912 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.4188602912
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1000146586
Short name T574
Test name
Test status
Simulation time 48491892 ps
CPU time 1 seconds
Started Jun 28 06:01:38 PM PDT 24
Finished Jun 28 06:01:43 PM PDT 24
Peak memory 220300 kb
Host smart-651cf54a-0cb4-434e-81e3-be8f3ff3bf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000146586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1000146586
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.4256885892
Short name T115
Test name
Test status
Simulation time 42795416 ps
CPU time 0.89 seconds
Started Jun 28 06:01:44 PM PDT 24
Finished Jun 28 06:01:50 PM PDT 24
Peak memory 215836 kb
Host smart-da7c7a70-a413-4e71-82e4-82581536cedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256885892 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.4256885892
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1836104236
Short name T733
Test name
Test status
Simulation time 17052922 ps
CPU time 1.02 seconds
Started Jun 28 06:01:43 PM PDT 24
Finished Jun 28 06:01:49 PM PDT 24
Peak memory 207616 kb
Host smart-fd800e82-a809-4097-a170-8ae81ed50770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836104236 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1836104236
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2461036757
Short name T483
Test name
Test status
Simulation time 16042602 ps
CPU time 0.97 seconds
Started Jun 28 06:01:36 PM PDT 24
Finished Jun 28 06:01:39 PM PDT 24
Peak memory 215488 kb
Host smart-b424db5e-5f61-4b9d-8aba-ed27b3146e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461036757 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2461036757
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.573683050
Short name T247
Test name
Test status
Simulation time 244275453 ps
CPU time 4.46 seconds
Started Jun 28 06:01:41 PM PDT 24
Finished Jun 28 06:01:51 PM PDT 24
Peak memory 220684 kb
Host smart-2510611e-5052-4996-adbf-dc05ad2a7d84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573683050 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.573683050
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.44156784
Short name T686
Test name
Test status
Simulation time 50766054445 ps
CPU time 1214.75 seconds
Started Jun 28 06:01:39 PM PDT 24
Finished Jun 28 06:21:59 PM PDT 24
Peak memory 222192 kb
Host smart-21819bd8-6dd1-4b46-9c83-7c0524d9025f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44156784 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.44156784
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.2919896471
Short name T118
Test name
Test status
Simulation time 94014829 ps
CPU time 1.13 seconds
Started Jun 28 06:02:57 PM PDT 24
Finished Jun 28 06:03:03 PM PDT 24
Peak memory 220168 kb
Host smart-8336b1b5-30a2-499a-b37c-2672274cccc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919896471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.2919896471
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.2543957589
Short name T5
Test name
Test status
Simulation time 57492277 ps
CPU time 1.35 seconds
Started Jun 28 06:03:00 PM PDT 24
Finished Jun 28 06:03:08 PM PDT 24
Peak memory 225820 kb
Host smart-5fd4aa25-eaf7-4b90-8c45-7a495b1afec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543957589 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2543957589
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2888628983
Short name T763
Test name
Test status
Simulation time 25820510 ps
CPU time 1.28 seconds
Started Jun 28 06:03:00 PM PDT 24
Finished Jun 28 06:03:07 PM PDT 24
Peak memory 219068 kb
Host smart-c410048e-86c6-44a2-88e3-f1f54efcfb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888628983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2888628983
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.338997551
Short name T130
Test name
Test status
Simulation time 223936119 ps
CPU time 1.19 seconds
Started Jun 28 06:03:06 PM PDT 24
Finished Jun 28 06:03:15 PM PDT 24
Peak memory 218920 kb
Host smart-dced4279-cdd5-484a-9c16-b94f3cd1fa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338997551 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.338997551
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.3588584242
Short name T754
Test name
Test status
Simulation time 20270816 ps
CPU time 1.14 seconds
Started Jun 28 06:03:00 PM PDT 24
Finished Jun 28 06:03:06 PM PDT 24
Peak memory 219884 kb
Host smart-f59a2d05-ebe0-49cc-bbc3-7ad4d91821a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588584242 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3588584242
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1855483682
Short name T45
Test name
Test status
Simulation time 21335888 ps
CPU time 1.15 seconds
Started Jun 28 06:03:05 PM PDT 24
Finished Jun 28 06:03:14 PM PDT 24
Peak memory 217552 kb
Host smart-382402d4-9c53-433f-ae63-5d3cbd3ceb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855483682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1855483682
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.3514333823
Short name T110
Test name
Test status
Simulation time 26404167 ps
CPU time 1.34 seconds
Started Jun 28 06:02:58 PM PDT 24
Finished Jun 28 06:03:04 PM PDT 24
Peak memory 229936 kb
Host smart-5640a8f3-e9a2-4406-973a-514a653741cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514333823 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3514333823
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3354377584
Short name T564
Test name
Test status
Simulation time 34853765 ps
CPU time 1.44 seconds
Started Jun 28 06:03:04 PM PDT 24
Finished Jun 28 06:03:13 PM PDT 24
Peak memory 218880 kb
Host smart-ab7336a8-a117-4b1a-99f7-d93a6e08598c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354377584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3354377584
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.3571222190
Short name T875
Test name
Test status
Simulation time 44286096 ps
CPU time 1.26 seconds
Started Jun 28 06:03:10 PM PDT 24
Finished Jun 28 06:03:20 PM PDT 24
Peak memory 218784 kb
Host smart-012b5872-788c-47ac-85f8-72fab577e70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571222190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.3571222190
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.383789430
Short name T181
Test name
Test status
Simulation time 30339645 ps
CPU time 0.98 seconds
Started Jun 28 06:02:57 PM PDT 24
Finished Jun 28 06:03:04 PM PDT 24
Peak memory 224036 kb
Host smart-4e77b14c-ae0a-459e-b23a-28b9ebd6bc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383789430 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.383789430
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.790414896
Short name T558
Test name
Test status
Simulation time 72002237 ps
CPU time 1.23 seconds
Started Jun 28 06:03:07 PM PDT 24
Finished Jun 28 06:03:17 PM PDT 24
Peak memory 219176 kb
Host smart-3cf37a66-007f-458b-ad8c-0d41f6483819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790414896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.790414896
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1569423926
Short name T749
Test name
Test status
Simulation time 95299410 ps
CPU time 1.25 seconds
Started Jun 28 06:03:00 PM PDT 24
Finished Jun 28 06:03:08 PM PDT 24
Peak memory 218716 kb
Host smart-e192486f-6466-44b9-94e8-a95f15bc4a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569423926 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1569423926
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.3031684571
Short name T125
Test name
Test status
Simulation time 35704845 ps
CPU time 0.92 seconds
Started Jun 28 06:03:11 PM PDT 24
Finished Jun 28 06:03:20 PM PDT 24
Peak memory 219736 kb
Host smart-1af95f88-7aa1-4763-8e38-41b422b760c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031684571 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3031684571
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.591674751
Short name T589
Test name
Test status
Simulation time 179702522 ps
CPU time 1.16 seconds
Started Jun 28 06:03:00 PM PDT 24
Finished Jun 28 06:03:07 PM PDT 24
Peak memory 217700 kb
Host smart-1da226c0-e7bc-414d-af85-a99cfcd3e5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591674751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.591674751
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.3733916861
Short name T308
Test name
Test status
Simulation time 41863274 ps
CPU time 1.26 seconds
Started Jun 28 06:02:59 PM PDT 24
Finished Jun 28 06:03:05 PM PDT 24
Peak memory 220204 kb
Host smart-a0e875ad-e49f-424a-9af8-37da4b778610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733916861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.3733916861
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1372169504
Short name T120
Test name
Test status
Simulation time 25932082 ps
CPU time 1.03 seconds
Started Jun 28 06:02:57 PM PDT 24
Finished Jun 28 06:03:04 PM PDT 24
Peak memory 219840 kb
Host smart-45f732b8-deeb-400b-884a-d9fe370fbb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372169504 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1372169504
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.907528928
Short name T370
Test name
Test status
Simulation time 49428671 ps
CPU time 1.74 seconds
Started Jun 28 06:03:03 PM PDT 24
Finished Jun 28 06:03:12 PM PDT 24
Peak memory 218768 kb
Host smart-b3586699-3155-46d9-a71d-e18b089d623b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907528928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.907528928
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1597394894
Short name T566
Test name
Test status
Simulation time 31929043 ps
CPU time 1.33 seconds
Started Jun 28 06:03:02 PM PDT 24
Finished Jun 28 06:03:11 PM PDT 24
Peak memory 216076 kb
Host smart-7554fb18-5e80-4b01-bdd0-470dad667c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597394894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1597394894
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.4253842843
Short name T403
Test name
Test status
Simulation time 92788300 ps
CPU time 1.18 seconds
Started Jun 28 06:03:01 PM PDT 24
Finished Jun 28 06:03:09 PM PDT 24
Peak memory 220084 kb
Host smart-94be8fb0-2e03-4784-a36e-9a753fd3030f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253842843 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.4253842843
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.518939045
Short name T699
Test name
Test status
Simulation time 61004489 ps
CPU time 1.29 seconds
Started Jun 28 06:03:03 PM PDT 24
Finished Jun 28 06:03:12 PM PDT 24
Peak memory 218960 kb
Host smart-51dccf21-32c9-4229-bde2-778c03806d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518939045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.518939045
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.2574387919
Short name T963
Test name
Test status
Simulation time 23862781 ps
CPU time 1.2 seconds
Started Jun 28 06:02:57 PM PDT 24
Finished Jun 28 06:03:03 PM PDT 24
Peak memory 220148 kb
Host smart-ec1a5c18-6582-4088-b459-b7431cd3155f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574387919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.2574387919
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.2234645039
Short name T196
Test name
Test status
Simulation time 23688499 ps
CPU time 1 seconds
Started Jun 28 06:03:01 PM PDT 24
Finished Jun 28 06:03:09 PM PDT 24
Peak memory 219896 kb
Host smart-ae52589b-2ba3-4fb4-84f7-dc10e425795a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234645039 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2234645039
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2184331911
Short name T914
Test name
Test status
Simulation time 64796216 ps
CPU time 1.08 seconds
Started Jun 28 06:02:58 PM PDT 24
Finished Jun 28 06:03:05 PM PDT 24
Peak memory 219248 kb
Host smart-eb5ceb19-daf5-4db2-b6b8-13e34226afdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184331911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2184331911
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1110943504
Short name T714
Test name
Test status
Simulation time 17878161 ps
CPU time 1.15 seconds
Started Jun 28 06:03:03 PM PDT 24
Finished Jun 28 06:03:12 PM PDT 24
Peak memory 224236 kb
Host smart-f5292226-85ea-496a-8d55-29d0d9ef40a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110943504 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1110943504
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2955129517
Short name T762
Test name
Test status
Simulation time 35167225 ps
CPU time 1.36 seconds
Started Jun 28 06:03:04 PM PDT 24
Finished Jun 28 06:03:12 PM PDT 24
Peak memory 217908 kb
Host smart-c0ddff54-d9b5-4603-922a-649be1caa4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955129517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2955129517
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.833008817
Short name T129
Test name
Test status
Simulation time 33101372 ps
CPU time 1.37 seconds
Started Jun 28 06:03:06 PM PDT 24
Finished Jun 28 06:03:16 PM PDT 24
Peak memory 220028 kb
Host smart-88371941-5720-412d-a4a6-29d45c47cc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833008817 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.833008817
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.2015049911
Short name T514
Test name
Test status
Simulation time 38084286 ps
CPU time 0.95 seconds
Started Jun 28 06:03:03 PM PDT 24
Finished Jun 28 06:03:11 PM PDT 24
Peak memory 224080 kb
Host smart-b212aa1d-461a-4baa-ab4d-5135fc944366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015049911 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2015049911
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.52268200
Short name T717
Test name
Test status
Simulation time 52105089 ps
CPU time 1.2 seconds
Started Jun 28 06:03:06 PM PDT 24
Finished Jun 28 06:03:15 PM PDT 24
Peak memory 218840 kb
Host smart-2c631934-32d6-4c5e-a32b-d67199235729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52268200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.52268200
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%