Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.65 98.25 93.97 97.07 91.86 96.37 99.77 92.28


Total test records in report: 1130
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T1022 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2012006812 Jun 29 05:30:01 PM PDT 24 Jun 29 05:30:04 PM PDT 24 25069060 ps
T1023 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1085780725 Jun 29 05:30:10 PM PDT 24 Jun 29 05:30:12 PM PDT 24 55912728 ps
T283 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1504297289 Jun 29 05:30:01 PM PDT 24 Jun 29 05:30:04 PM PDT 24 35939470 ps
T1024 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.833423330 Jun 29 05:30:08 PM PDT 24 Jun 29 05:30:12 PM PDT 24 95705380 ps
T266 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3818579378 Jun 29 05:30:03 PM PDT 24 Jun 29 05:30:05 PM PDT 24 41480450 ps
T1025 /workspace/coverage/cover_reg_top/2.edn_intr_test.2176129158 Jun 29 05:30:01 PM PDT 24 Jun 29 05:30:04 PM PDT 24 50173022 ps
T267 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1703070771 Jun 29 05:30:10 PM PDT 24 Jun 29 05:30:13 PM PDT 24 18631885 ps
T295 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3138465894 Jun 29 05:30:27 PM PDT 24 Jun 29 05:30:30 PM PDT 24 63737402 ps
T1026 /workspace/coverage/cover_reg_top/34.edn_intr_test.2897462690 Jun 29 05:30:28 PM PDT 24 Jun 29 05:30:30 PM PDT 24 84646170 ps
T1027 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1829929916 Jun 29 05:30:24 PM PDT 24 Jun 29 05:30:26 PM PDT 24 21012889 ps
T1028 /workspace/coverage/cover_reg_top/18.edn_intr_test.562065967 Jun 29 05:30:25 PM PDT 24 Jun 29 05:30:27 PM PDT 24 14624020 ps
T1029 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3088102242 Jun 29 05:30:10 PM PDT 24 Jun 29 05:30:13 PM PDT 24 152281831 ps
T1030 /workspace/coverage/cover_reg_top/21.edn_intr_test.3902271072 Jun 29 05:30:24 PM PDT 24 Jun 29 05:30:25 PM PDT 24 10522495 ps
T1031 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2243120238 Jun 29 05:30:11 PM PDT 24 Jun 29 05:30:13 PM PDT 24 28495755 ps
T1032 /workspace/coverage/cover_reg_top/0.edn_intr_test.2451205529 Jun 29 05:29:56 PM PDT 24 Jun 29 05:29:58 PM PDT 24 21273704 ps
T1033 /workspace/coverage/cover_reg_top/9.edn_tl_errors.4076056324 Jun 29 05:30:09 PM PDT 24 Jun 29 05:30:11 PM PDT 24 96446870 ps
T1034 /workspace/coverage/cover_reg_top/45.edn_intr_test.2693559163 Jun 29 05:30:36 PM PDT 24 Jun 29 05:30:39 PM PDT 24 14422073 ps
T296 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3086639942 Jun 29 05:30:26 PM PDT 24 Jun 29 05:30:29 PM PDT 24 134797045 ps
T1035 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3374592706 Jun 29 05:30:00 PM PDT 24 Jun 29 05:30:02 PM PDT 24 42955318 ps
T302 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2684104831 Jun 29 05:30:18 PM PDT 24 Jun 29 05:30:20 PM PDT 24 59736277 ps
T1036 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3388518895 Jun 29 05:29:55 PM PDT 24 Jun 29 05:29:58 PM PDT 24 55545595 ps
T284 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.441135912 Jun 29 05:30:08 PM PDT 24 Jun 29 05:30:10 PM PDT 24 35389446 ps
T1037 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1675446275 Jun 29 05:30:26 PM PDT 24 Jun 29 05:30:28 PM PDT 24 24410014 ps
T1038 /workspace/coverage/cover_reg_top/15.edn_tl_errors.935401335 Jun 29 05:30:21 PM PDT 24 Jun 29 05:30:24 PM PDT 24 54664980 ps
T1039 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1167769931 Jun 29 05:29:56 PM PDT 24 Jun 29 05:29:58 PM PDT 24 50835723 ps
T1040 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2272179294 Jun 29 05:30:18 PM PDT 24 Jun 29 05:30:22 PM PDT 24 68707671 ps
T268 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3363470403 Jun 29 05:30:04 PM PDT 24 Jun 29 05:30:06 PM PDT 24 96782784 ps
T1041 /workspace/coverage/cover_reg_top/17.edn_csr_rw.384992165 Jun 29 05:30:27 PM PDT 24 Jun 29 05:30:28 PM PDT 24 61607861 ps
T303 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3924028779 Jun 29 05:30:11 PM PDT 24 Jun 29 05:30:16 PM PDT 24 313502469 ps
T1042 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.227233822 Jun 29 05:30:27 PM PDT 24 Jun 29 05:30:29 PM PDT 24 20986949 ps
T1043 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1177646194 Jun 29 05:30:00 PM PDT 24 Jun 29 05:30:04 PM PDT 24 220316767 ps
T305 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.978220979 Jun 29 05:30:10 PM PDT 24 Jun 29 05:30:14 PM PDT 24 550017882 ps
T1044 /workspace/coverage/cover_reg_top/10.edn_intr_test.1414104880 Jun 29 05:30:09 PM PDT 24 Jun 29 05:30:11 PM PDT 24 21449331 ps
T1045 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3804561615 Jun 29 05:30:30 PM PDT 24 Jun 29 05:30:31 PM PDT 24 15460446 ps
T1046 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1594206931 Jun 29 05:30:10 PM PDT 24 Jun 29 05:30:13 PM PDT 24 46949854 ps
T1047 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.600028368 Jun 29 05:30:11 PM PDT 24 Jun 29 05:30:14 PM PDT 24 64006025 ps
T1048 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3677137585 Jun 29 05:30:26 PM PDT 24 Jun 29 05:30:30 PM PDT 24 396978629 ps
T1049 /workspace/coverage/cover_reg_top/7.edn_csr_rw.127629469 Jun 29 05:30:10 PM PDT 24 Jun 29 05:30:12 PM PDT 24 48761049 ps
T1050 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2784773468 Jun 29 05:29:54 PM PDT 24 Jun 29 05:29:57 PM PDT 24 209103624 ps
T1051 /workspace/coverage/cover_reg_top/16.edn_intr_test.3513587694 Jun 29 05:30:20 PM PDT 24 Jun 29 05:30:21 PM PDT 24 116067468 ps
T1052 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.347818379 Jun 29 05:30:01 PM PDT 24 Jun 29 05:30:04 PM PDT 24 103444956 ps
T1053 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.524148741 Jun 29 05:30:00 PM PDT 24 Jun 29 05:30:03 PM PDT 24 47965044 ps
T1054 /workspace/coverage/cover_reg_top/47.edn_intr_test.2177735414 Jun 29 05:30:40 PM PDT 24 Jun 29 05:30:41 PM PDT 24 12914398 ps
T1055 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.205942238 Jun 29 05:30:10 PM PDT 24 Jun 29 05:30:12 PM PDT 24 67416175 ps
T1056 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1833055073 Jun 29 05:30:11 PM PDT 24 Jun 29 05:30:16 PM PDT 24 872190813 ps
T1057 /workspace/coverage/cover_reg_top/32.edn_intr_test.1866726658 Jun 29 05:30:26 PM PDT 24 Jun 29 05:30:27 PM PDT 24 23203802 ps
T1058 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3056393534 Jun 29 05:30:20 PM PDT 24 Jun 29 05:30:22 PM PDT 24 46973483 ps
T269 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1152211664 Jun 29 05:30:00 PM PDT 24 Jun 29 05:30:02 PM PDT 24 25881956 ps
T1059 /workspace/coverage/cover_reg_top/17.edn_intr_test.3487374048 Jun 29 05:30:27 PM PDT 24 Jun 29 05:30:29 PM PDT 24 33078689 ps
T1060 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3925584891 Jun 29 05:30:25 PM PDT 24 Jun 29 05:30:27 PM PDT 24 36904482 ps
T1061 /workspace/coverage/cover_reg_top/31.edn_intr_test.3851177692 Jun 29 05:30:28 PM PDT 24 Jun 29 05:30:30 PM PDT 24 13062846 ps
T1062 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2432906612 Jun 29 05:30:18 PM PDT 24 Jun 29 05:30:20 PM PDT 24 50192323 ps
T270 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3385275007 Jun 29 05:30:19 PM PDT 24 Jun 29 05:30:20 PM PDT 24 13684428 ps
T271 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2338754845 Jun 29 05:30:04 PM PDT 24 Jun 29 05:30:06 PM PDT 24 79702157 ps
T1063 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2835576265 Jun 29 05:30:25 PM PDT 24 Jun 29 05:30:27 PM PDT 24 57775620 ps
T272 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4100177243 Jun 29 05:30:00 PM PDT 24 Jun 29 05:30:03 PM PDT 24 38898171 ps
T1064 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3006687656 Jun 29 05:29:56 PM PDT 24 Jun 29 05:29:58 PM PDT 24 43862474 ps
T1065 /workspace/coverage/cover_reg_top/39.edn_intr_test.1589284405 Jun 29 05:30:33 PM PDT 24 Jun 29 05:30:36 PM PDT 24 16592464 ps
T1066 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2768665875 Jun 29 05:30:00 PM PDT 24 Jun 29 05:30:03 PM PDT 24 89172317 ps
T273 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1853220262 Jun 29 05:30:02 PM PDT 24 Jun 29 05:30:05 PM PDT 24 17915044 ps
T1067 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2097976102 Jun 29 05:30:08 PM PDT 24 Jun 29 05:30:10 PM PDT 24 19865859 ps
T1068 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2072184581 Jun 29 05:30:22 PM PDT 24 Jun 29 05:30:24 PM PDT 24 140857078 ps
T1069 /workspace/coverage/cover_reg_top/24.edn_intr_test.4121504499 Jun 29 05:30:25 PM PDT 24 Jun 29 05:30:27 PM PDT 24 87322876 ps
T1070 /workspace/coverage/cover_reg_top/38.edn_intr_test.697124396 Jun 29 05:30:36 PM PDT 24 Jun 29 05:30:39 PM PDT 24 17100430 ps
T1071 /workspace/coverage/cover_reg_top/11.edn_tl_errors.714475718 Jun 29 05:30:09 PM PDT 24 Jun 29 05:30:14 PM PDT 24 338900701 ps
T274 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1115561298 Jun 29 05:29:58 PM PDT 24 Jun 29 05:30:05 PM PDT 24 513207111 ps
T1072 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.48129222 Jun 29 05:30:09 PM PDT 24 Jun 29 05:30:11 PM PDT 24 17455533 ps
T1073 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.225874501 Jun 29 05:29:55 PM PDT 24 Jun 29 05:29:58 PM PDT 24 148269165 ps
T1074 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3453517319 Jun 29 05:30:38 PM PDT 24 Jun 29 05:30:41 PM PDT 24 32058159 ps
T275 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1752186360 Jun 29 05:30:18 PM PDT 24 Jun 29 05:30:19 PM PDT 24 13647349 ps
T1075 /workspace/coverage/cover_reg_top/12.edn_intr_test.1918191115 Jun 29 05:30:21 PM PDT 24 Jun 29 05:30:22 PM PDT 24 11431042 ps
T1076 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1270088232 Jun 29 05:30:17 PM PDT 24 Jun 29 05:30:19 PM PDT 24 23511854 ps
T1077 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1279131846 Jun 29 05:30:01 PM PDT 24 Jun 29 05:30:04 PM PDT 24 16831006 ps
T1078 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2893979668 Jun 29 05:30:19 PM PDT 24 Jun 29 05:30:23 PM PDT 24 444154810 ps
T1079 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3472815938 Jun 29 05:30:28 PM PDT 24 Jun 29 05:30:31 PM PDT 24 53797389 ps
T1080 /workspace/coverage/cover_reg_top/4.edn_intr_test.1946582609 Jun 29 05:30:04 PM PDT 24 Jun 29 05:30:06 PM PDT 24 13507435 ps
T1081 /workspace/coverage/cover_reg_top/0.edn_csr_rw.1026577334 Jun 29 05:29:54 PM PDT 24 Jun 29 05:29:55 PM PDT 24 67851986 ps
T1082 /workspace/coverage/cover_reg_top/33.edn_intr_test.3543073751 Jun 29 05:30:29 PM PDT 24 Jun 29 05:30:30 PM PDT 24 17092754 ps
T1083 /workspace/coverage/cover_reg_top/22.edn_intr_test.3969152089 Jun 29 05:30:38 PM PDT 24 Jun 29 05:30:40 PM PDT 24 19016215 ps
T1084 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4244786953 Jun 29 05:30:04 PM PDT 24 Jun 29 05:30:06 PM PDT 24 127152766 ps
T1085 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2294779132 Jun 29 05:30:38 PM PDT 24 Jun 29 05:30:41 PM PDT 24 16833464 ps
T1086 /workspace/coverage/cover_reg_top/30.edn_intr_test.2764378749 Jun 29 05:30:26 PM PDT 24 Jun 29 05:30:28 PM PDT 24 15912784 ps
T1087 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2770221701 Jun 29 05:30:11 PM PDT 24 Jun 29 05:30:15 PM PDT 24 1375122668 ps
T1088 /workspace/coverage/cover_reg_top/19.edn_tl_errors.512338016 Jun 29 05:30:25 PM PDT 24 Jun 29 05:30:28 PM PDT 24 44481971 ps
T1089 /workspace/coverage/cover_reg_top/11.edn_intr_test.1161615757 Jun 29 05:30:11 PM PDT 24 Jun 29 05:30:13 PM PDT 24 90694317 ps
T276 /workspace/coverage/cover_reg_top/15.edn_csr_rw.919296363 Jun 29 05:30:24 PM PDT 24 Jun 29 05:30:26 PM PDT 24 11616710 ps
T1090 /workspace/coverage/cover_reg_top/15.edn_intr_test.1754170142 Jun 29 05:30:18 PM PDT 24 Jun 29 05:30:20 PM PDT 24 15914315 ps
T1091 /workspace/coverage/cover_reg_top/4.edn_tl_errors.454924081 Jun 29 05:30:03 PM PDT 24 Jun 29 05:30:08 PM PDT 24 88204717 ps
T1092 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.4059029975 Jun 29 05:30:20 PM PDT 24 Jun 29 05:30:22 PM PDT 24 50496534 ps
T1093 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2948467663 Jun 29 05:30:08 PM PDT 24 Jun 29 05:30:10 PM PDT 24 226246859 ps
T1094 /workspace/coverage/cover_reg_top/3.edn_intr_test.3514451960 Jun 29 05:30:01 PM PDT 24 Jun 29 05:30:04 PM PDT 24 44473612 ps
T1095 /workspace/coverage/cover_reg_top/8.edn_tl_errors.306862541 Jun 29 05:30:09 PM PDT 24 Jun 29 05:30:14 PM PDT 24 723567710 ps
T1096 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2243929708 Jun 29 05:30:20 PM PDT 24 Jun 29 05:30:21 PM PDT 24 20809798 ps
T1097 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3564560527 Jun 29 05:30:26 PM PDT 24 Jun 29 05:30:28 PM PDT 24 30844992 ps
T1098 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.96181523 Jun 29 05:30:01 PM PDT 24 Jun 29 05:30:05 PM PDT 24 248936476 ps
T1099 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2006025726 Jun 29 05:30:02 PM PDT 24 Jun 29 05:30:06 PM PDT 24 36898407 ps
T1100 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2069014760 Jun 29 05:30:10 PM PDT 24 Jun 29 05:30:12 PM PDT 24 24579413 ps
T306 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2021917600 Jun 29 05:29:59 PM PDT 24 Jun 29 05:30:02 PM PDT 24 565994806 ps
T277 /workspace/coverage/cover_reg_top/4.edn_csr_rw.262633700 Jun 29 05:29:57 PM PDT 24 Jun 29 05:29:59 PM PDT 24 54209682 ps
T1101 /workspace/coverage/cover_reg_top/3.edn_csr_rw.4198611230 Jun 29 05:30:01 PM PDT 24 Jun 29 05:30:03 PM PDT 24 12009462 ps
T1102 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3232581007 Jun 29 05:30:20 PM PDT 24 Jun 29 05:30:22 PM PDT 24 16248994 ps
T1103 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1583563682 Jun 29 05:30:09 PM PDT 24 Jun 29 05:30:10 PM PDT 24 16298475 ps
T1104 /workspace/coverage/cover_reg_top/5.edn_intr_test.1493115189 Jun 29 05:30:08 PM PDT 24 Jun 29 05:30:10 PM PDT 24 15912755 ps
T1105 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1530177388 Jun 29 05:30:21 PM PDT 24 Jun 29 05:30:24 PM PDT 24 305269042 ps
T1106 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3221353348 Jun 29 05:29:55 PM PDT 24 Jun 29 05:29:58 PM PDT 24 31901446 ps
T1107 /workspace/coverage/cover_reg_top/49.edn_intr_test.1297860334 Jun 29 05:30:34 PM PDT 24 Jun 29 05:30:36 PM PDT 24 19686616 ps
T1108 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.711255333 Jun 29 05:30:11 PM PDT 24 Jun 29 05:30:13 PM PDT 24 45601668 ps
T1109 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3866007689 Jun 29 05:30:19 PM PDT 24 Jun 29 05:30:21 PM PDT 24 30138644 ps
T1110 /workspace/coverage/cover_reg_top/8.edn_intr_test.2508326664 Jun 29 05:30:10 PM PDT 24 Jun 29 05:30:12 PM PDT 24 35548004 ps
T304 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.235784129 Jun 29 05:30:03 PM PDT 24 Jun 29 05:30:07 PM PDT 24 71747705 ps
T1111 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2726416048 Jun 29 05:30:05 PM PDT 24 Jun 29 05:30:06 PM PDT 24 36577684 ps
T1112 /workspace/coverage/cover_reg_top/28.edn_intr_test.341258156 Jun 29 05:30:24 PM PDT 24 Jun 29 05:30:26 PM PDT 24 13681840 ps
T1113 /workspace/coverage/cover_reg_top/25.edn_intr_test.3707067967 Jun 29 05:30:38 PM PDT 24 Jun 29 05:30:40 PM PDT 24 32722818 ps
T1114 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.4091941820 Jun 29 05:29:57 PM PDT 24 Jun 29 05:29:59 PM PDT 24 30234727 ps
T1115 /workspace/coverage/cover_reg_top/40.edn_intr_test.2860132163 Jun 29 05:30:32 PM PDT 24 Jun 29 05:30:34 PM PDT 24 39154614 ps
T1116 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3087178395 Jun 29 05:30:11 PM PDT 24 Jun 29 05:30:14 PM PDT 24 155660880 ps
T1117 /workspace/coverage/cover_reg_top/35.edn_intr_test.1047623140 Jun 29 05:30:25 PM PDT 24 Jun 29 05:30:26 PM PDT 24 30327494 ps
T1118 /workspace/coverage/cover_reg_top/13.edn_intr_test.2932201190 Jun 29 05:30:18 PM PDT 24 Jun 29 05:30:19 PM PDT 24 36319429 ps
T1119 /workspace/coverage/cover_reg_top/26.edn_intr_test.2177931620 Jun 29 05:30:37 PM PDT 24 Jun 29 05:30:40 PM PDT 24 35686301 ps
T1120 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2443464469 Jun 29 05:30:10 PM PDT 24 Jun 29 05:30:13 PM PDT 24 41995106 ps
T1121 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3254250608 Jun 29 05:29:55 PM PDT 24 Jun 29 05:29:57 PM PDT 24 21535959 ps
T1122 /workspace/coverage/cover_reg_top/48.edn_intr_test.3458728360 Jun 29 05:30:33 PM PDT 24 Jun 29 05:30:35 PM PDT 24 12431435 ps
T1123 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1008717977 Jun 29 05:30:01 PM PDT 24 Jun 29 05:30:04 PM PDT 24 100730362 ps
T1124 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2431837835 Jun 29 05:30:11 PM PDT 24 Jun 29 05:30:14 PM PDT 24 102707338 ps
T1125 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1695305902 Jun 29 05:30:11 PM PDT 24 Jun 29 05:30:14 PM PDT 24 115224066 ps
T1126 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3268857459 Jun 29 05:29:56 PM PDT 24 Jun 29 05:29:58 PM PDT 24 13887409 ps
T1127 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1572152746 Jun 29 05:29:55 PM PDT 24 Jun 29 05:29:58 PM PDT 24 69319175 ps
T1128 /workspace/coverage/cover_reg_top/12.edn_tl_errors.2823236269 Jun 29 05:30:18 PM PDT 24 Jun 29 05:30:22 PM PDT 24 365078593 ps
T1129 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1329210626 Jun 29 05:30:00 PM PDT 24 Jun 29 05:30:03 PM PDT 24 43792080 ps
T1130 /workspace/coverage/cover_reg_top/42.edn_intr_test.665751234 Jun 29 05:30:31 PM PDT 24 Jun 29 05:30:33 PM PDT 24 23313380 ps

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2268671750
Short name T3
Test name
Test status
Simulation time 110332166 ps
CPU time 1.16 seconds
Started Jun 29 05:33:01 PM PDT 24
Finished Jun 29 05:33:02 PM PDT 24
Peak memory 217316 kb
Host smart-98e54859-c8dd-4ba8-864c-d74ba4c45f8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268671750 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2268671750
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/126.edn_genbits.1946860545
Short name T41
Test name
Test status
Simulation time 105435050 ps
CPU time 1.32 seconds
Started Jun 29 05:33:34 PM PDT 24
Finished Jun 29 05:33:36 PM PDT 24
Peak memory 219416 kb
Host smart-b080f83f-34de-4bc5-9fee-6c8b38ea8248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946860545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1946860545
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.997673323
Short name T36
Test name
Test status
Simulation time 37452616754 ps
CPU time 599.08 seconds
Started Jun 29 05:32:42 PM PDT 24
Finished Jun 29 05:42:43 PM PDT 24
Peak memory 224000 kb
Host smart-c2aef7b1-c3ec-40a6-8e51-deba2ba32af9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997673323 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.997673323
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.edn_alert.785862136
Short name T2
Test name
Test status
Simulation time 47577428 ps
CPU time 1.27 seconds
Started Jun 29 05:33:19 PM PDT 24
Finished Jun 29 05:33:21 PM PDT 24
Peak memory 220180 kb
Host smart-0f60004a-3bb8-4fc4-a747-83085be74b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785862136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.785862136
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1834304785
Short name T17
Test name
Test status
Simulation time 478545328 ps
CPU time 5.06 seconds
Started Jun 29 05:31:53 PM PDT 24
Finished Jun 29 05:31:59 PM PDT 24
Peak memory 236172 kb
Host smart-423bce9c-7c43-4d81-b709-62f34218ed9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834304785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1834304785
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_err.4090648419
Short name T4
Test name
Test status
Simulation time 46125108 ps
CPU time 1.28 seconds
Started Jun 29 05:31:45 PM PDT 24
Finished Jun 29 05:31:47 PM PDT 24
Peak memory 226004 kb
Host smart-782f384a-43ad-4063-ac51-1ee2a96446e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090648419 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.4090648419
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/26.edn_stress_all.3775360323
Short name T54
Test name
Test status
Simulation time 353484112 ps
CPU time 2.48 seconds
Started Jun 29 05:32:23 PM PDT 24
Finished Jun 29 05:32:26 PM PDT 24
Peak memory 220340 kb
Host smart-e7fb1126-d368-468d-b651-fa331b3030f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775360323 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3775360323
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/185.edn_alert.3914320023
Short name T42
Test name
Test status
Simulation time 63472481 ps
CPU time 1.11 seconds
Started Jun 29 05:33:45 PM PDT 24
Finished Jun 29 05:33:49 PM PDT 24
Peak memory 220088 kb
Host smart-acf177e2-801c-4adf-925c-0d6db6585ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914320023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.3914320023
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/210.edn_genbits.1469478652
Short name T11
Test name
Test status
Simulation time 102509078 ps
CPU time 1.49 seconds
Started Jun 29 05:33:57 PM PDT 24
Finished Jun 29 05:33:59 PM PDT 24
Peak memory 219184 kb
Host smart-3bd2748d-d19b-4d1f-a7e2-9831ec4ca60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469478652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1469478652
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.927158583
Short name T48
Test name
Test status
Simulation time 56280337 ps
CPU time 1.25 seconds
Started Jun 29 05:33:35 PM PDT 24
Finished Jun 29 05:33:37 PM PDT 24
Peak memory 220180 kb
Host smart-81bbcc04-4c00-478f-8a0c-5b6ec81a0474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927158583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.927158583
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/0.edn_regwen.2907514806
Short name T26
Test name
Test status
Simulation time 21230733 ps
CPU time 0.92 seconds
Started Jun 29 05:31:38 PM PDT 24
Finished Jun 29 05:31:39 PM PDT 24
Peak memory 207412 kb
Host smart-df7a86c6-5255-40d7-93f8-717bcb83cb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907514806 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2907514806
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1508935920
Short name T38
Test name
Test status
Simulation time 100571396387 ps
CPU time 2383.79 seconds
Started Jun 29 05:32:22 PM PDT 24
Finished Jun 29 06:12:07 PM PDT 24
Peak memory 227916 kb
Host smart-703f166f-5932-460e-bb50-a26a951d59bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508935920 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1508935920
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.edn_disable.1335342524
Short name T47
Test name
Test status
Simulation time 15685368 ps
CPU time 0.94 seconds
Started Jun 29 05:32:38 PM PDT 24
Finished Jun 29 05:32:41 PM PDT 24
Peak memory 216732 kb
Host smart-dd74664d-c783-4285-8b7a-5015f0878de2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335342524 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1335342524
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/64.edn_alert.2107569599
Short name T108
Test name
Test status
Simulation time 25966072 ps
CPU time 1.3 seconds
Started Jun 29 05:33:22 PM PDT 24
Finished Jun 29 05:33:24 PM PDT 24
Peak memory 218784 kb
Host smart-8091d8aa-d299-425b-813e-b89fa9d84eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107569599 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.2107569599
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3924028779
Short name T303
Test name
Test status
Simulation time 313502469 ps
CPU time 2.47 seconds
Started Jun 29 05:30:11 PM PDT 24
Finished Jun 29 05:30:16 PM PDT 24
Peak memory 215180 kb
Host smart-d7a247eb-f62d-47eb-8ef9-ca6d3065bd89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924028779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3924028779
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/32.edn_disable.4246228123
Short name T618
Test name
Test status
Simulation time 19919454 ps
CPU time 0.87 seconds
Started Jun 29 05:32:37 PM PDT 24
Finished Jun 29 05:32:40 PM PDT 24
Peak memory 216484 kb
Host smart-a3ac6dd5-5387-466f-b851-b3f29c446069
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246228123 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.4246228123
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2715731313
Short name T119
Test name
Test status
Simulation time 176017324 ps
CPU time 1.21 seconds
Started Jun 29 05:31:38 PM PDT 24
Finished Jun 29 05:31:39 PM PDT 24
Peak memory 218468 kb
Host smart-4586a923-b2d6-4c82-9f2d-1cbc18bffee4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715731313 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2715731313
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.4145383586
Short name T174
Test name
Test status
Simulation time 25263343 ps
CPU time 0.89 seconds
Started Jun 29 05:32:14 PM PDT 24
Finished Jun 29 05:32:16 PM PDT 24
Peak memory 218612 kb
Host smart-e9bcf60a-4f34-4ff9-b76e-282b57013ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145383586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.4145383586
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2556993591
Short name T149
Test name
Test status
Simulation time 24260655 ps
CPU time 1.04 seconds
Started Jun 29 05:32:46 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 217216 kb
Host smart-6a7b99a6-06ea-48e9-908b-b7bb9b9222ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556993591 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2556993591
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_alert.1371164602
Short name T103
Test name
Test status
Simulation time 27021417 ps
CPU time 1.29 seconds
Started Jun 29 05:31:46 PM PDT 24
Finished Jun 29 05:31:48 PM PDT 24
Peak memory 219436 kb
Host smart-6223b477-9164-4f6c-b0c4-186e1dcfdd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371164602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1371164602
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1115561298
Short name T274
Test name
Test status
Simulation time 513207111 ps
CPU time 6.58 seconds
Started Jun 29 05:29:58 PM PDT 24
Finished Jun 29 05:30:05 PM PDT 24
Peak memory 206836 kb
Host smart-696322d3-c303-47f8-9d1e-8d4c10055b10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115561298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1115561298
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/default/57.edn_alert.2251687462
Short name T258
Test name
Test status
Simulation time 107410092 ps
CPU time 1.17 seconds
Started Jun 29 05:32:55 PM PDT 24
Finished Jun 29 05:32:57 PM PDT 24
Peak memory 218856 kb
Host smart-d3817dd4-79aa-4604-9837-6863fe5fbad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251687462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.2251687462
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/140.edn_alert.306070234
Short name T142
Test name
Test status
Simulation time 24391072 ps
CPU time 1.21 seconds
Started Jun 29 05:33:38 PM PDT 24
Finished Jun 29 05:33:40 PM PDT 24
Peak memory 219012 kb
Host smart-bdc48f11-3f2b-4ce5-b621-225cf56707fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306070234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.306070234
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/142.edn_alert.1572645952
Short name T226
Test name
Test status
Simulation time 29445939 ps
CPU time 1.31 seconds
Started Jun 29 05:33:40 PM PDT 24
Finished Jun 29 05:33:42 PM PDT 24
Peak memory 219532 kb
Host smart-e8aed100-9bc1-435b-abaa-f077826389ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572645952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.1572645952
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert.687237466
Short name T71
Test name
Test status
Simulation time 43184721 ps
CPU time 1.15 seconds
Started Jun 29 05:32:45 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 220632 kb
Host smart-ae9e4632-7e7a-46d3-90f0-8add4a207d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687237466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.687237466
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.453364818
Short name T49
Test name
Test status
Simulation time 72745281 ps
CPU time 1.91 seconds
Started Jun 29 05:33:53 PM PDT 24
Finished Jun 29 05:33:55 PM PDT 24
Peak memory 220292 kb
Host smart-48723ceb-31be-475a-8895-df976bdd8a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453364818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.453364818
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.1106152150
Short name T738
Test name
Test status
Simulation time 23806338 ps
CPU time 1.18 seconds
Started Jun 29 05:33:32 PM PDT 24
Finished Jun 29 05:33:35 PM PDT 24
Peak memory 220320 kb
Host smart-6e987233-56ad-47c5-8c22-c2a8c39581fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106152150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.1106152150
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/107.edn_alert.3325836621
Short name T595
Test name
Test status
Simulation time 54359340 ps
CPU time 1.15 seconds
Started Jun 29 05:33:26 PM PDT 24
Finished Jun 29 05:33:28 PM PDT 24
Peak memory 219964 kb
Host smart-ea42ba51-510f-49f5-9840-0369e434f299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325836621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.3325836621
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/119.edn_alert.1220113426
Short name T104
Test name
Test status
Simulation time 256556371 ps
CPU time 1.28 seconds
Started Jun 29 05:33:30 PM PDT 24
Finished Jun 29 05:33:33 PM PDT 24
Peak memory 219796 kb
Host smart-5be3fc5a-242d-4446-a942-46fda7bb2a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220113426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1220113426
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/126.edn_alert.3481325585
Short name T106
Test name
Test status
Simulation time 165773692 ps
CPU time 1.03 seconds
Started Jun 29 05:33:27 PM PDT 24
Finished Jun 29 05:33:29 PM PDT 24
Peak memory 219768 kb
Host smart-12d68605-07f0-4e61-a766-a7f3993e6643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481325585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.3481325585
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/154.edn_alert.2373555877
Short name T140
Test name
Test status
Simulation time 91644210 ps
CPU time 1.21 seconds
Started Jun 29 05:33:51 PM PDT 24
Finished Jun 29 05:33:53 PM PDT 24
Peak memory 221164 kb
Host smart-ef770d7b-994f-4caf-b808-86f213131f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373555877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.2373555877
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/1.edn_intr.3071055697
Short name T31
Test name
Test status
Simulation time 26000956 ps
CPU time 0.99 seconds
Started Jun 29 05:31:48 PM PDT 24
Finished Jun 29 05:31:50 PM PDT 24
Peak memory 216088 kb
Host smart-3b46266b-db6a-49cb-b763-d364ed8cd1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071055697 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3071055697
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable.326254290
Short name T194
Test name
Test status
Simulation time 19759946 ps
CPU time 0.89 seconds
Started Jun 29 05:31:47 PM PDT 24
Finished Jun 29 05:31:48 PM PDT 24
Peak memory 216476 kb
Host smart-897987fc-f8a6-4e74-80e4-1afbfc03a70a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326254290 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.326254290
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/105.edn_alert.1256392023
Short name T152
Test name
Test status
Simulation time 27531967 ps
CPU time 1.24 seconds
Started Jun 29 05:33:36 PM PDT 24
Finished Jun 29 05:33:38 PM PDT 24
Peak memory 218728 kb
Host smart-9e841f75-8e93-46bd-87ab-ee65c0ef91d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256392023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.1256392023
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable.1589732430
Short name T185
Test name
Test status
Simulation time 13990273 ps
CPU time 0.87 seconds
Started Jun 29 05:32:01 PM PDT 24
Finished Jun 29 05:32:03 PM PDT 24
Peak memory 216548 kb
Host smart-956fc53d-dfc6-425e-b948-3646a384ccf9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589732430 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1589732430
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable.3683873714
Short name T222
Test name
Test status
Simulation time 22000065 ps
CPU time 0.83 seconds
Started Jun 29 05:32:25 PM PDT 24
Finished Jun 29 05:32:26 PM PDT 24
Peak memory 215712 kb
Host smart-abba472d-5005-46c2-81b0-927ac5fbc102
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683873714 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3683873714
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/12.edn_intr.1935110445
Short name T929
Test name
Test status
Simulation time 21649434 ps
CPU time 1.15 seconds
Started Jun 29 05:32:02 PM PDT 24
Finished Jun 29 05:32:04 PM PDT 24
Peak memory 216084 kb
Host smart-38a9487d-8f8b-4d7d-8e25-ca4390e48e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935110445 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1935110445
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2326586145
Short name T126
Test name
Test status
Simulation time 47786990 ps
CPU time 1.45 seconds
Started Jun 29 05:31:37 PM PDT 24
Finished Jun 29 05:31:39 PM PDT 24
Peak memory 217208 kb
Host smart-ec3f9f8a-66b3-4931-b620-3417a802a6f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326586145 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2326586145
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/113.edn_alert.3324472800
Short name T170
Test name
Test status
Simulation time 39763367 ps
CPU time 1.15 seconds
Started Jun 29 05:33:30 PM PDT 24
Finished Jun 29 05:33:32 PM PDT 24
Peak memory 220076 kb
Host smart-5996dd8d-6f37-4991-8453-d0cfb0ead868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324472800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.3324472800
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.2636865424
Short name T137
Test name
Test status
Simulation time 109970989 ps
CPU time 1.05 seconds
Started Jun 29 05:32:06 PM PDT 24
Finished Jun 29 05:32:07 PM PDT 24
Peak memory 218844 kb
Host smart-2d21fa27-cc2d-4b1f-8660-a10d829a586b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636865424 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.2636865424
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.959161556
Short name T191
Test name
Test status
Simulation time 23860290 ps
CPU time 0.97 seconds
Started Jun 29 05:32:10 PM PDT 24
Finished Jun 29 05:32:12 PM PDT 24
Peak memory 219784 kb
Host smart-073675d9-601a-4fb0-b713-635936706442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959161556 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.959161556
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3664866816
Short name T157
Test name
Test status
Simulation time 34244355 ps
CPU time 1.28 seconds
Started Jun 29 05:31:54 PM PDT 24
Finished Jun 29 05:31:56 PM PDT 24
Peak memory 217256 kb
Host smart-cb9fa998-f34a-4719-aa62-0076e5cf801c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664866816 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3664866816
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3080716356
Short name T210
Test name
Test status
Simulation time 28537095 ps
CPU time 1.1 seconds
Started Jun 29 05:32:27 PM PDT 24
Finished Jun 29 05:32:29 PM PDT 24
Peak memory 217260 kb
Host smart-ebfe1d0e-77c4-44b8-b515-c4e8fdb703d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080716356 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3080716356
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.576971733
Short name T56
Test name
Test status
Simulation time 23626165 ps
CPU time 1.01 seconds
Started Jun 29 05:32:36 PM PDT 24
Finished Jun 29 05:32:39 PM PDT 24
Peak memory 224080 kb
Host smart-2e10501f-4b23-4cdc-b281-ef9c15f1d731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576971733 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.576971733
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/34.edn_disable.3198308103
Short name T23
Test name
Test status
Simulation time 59492635 ps
CPU time 0.86 seconds
Started Jun 29 05:32:39 PM PDT 24
Finished Jun 29 05:32:43 PM PDT 24
Peak memory 216472 kb
Host smart-fc4fe561-84a3-478f-adb0-bf452af5838d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198308103 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3198308103
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1104258509
Short name T198
Test name
Test status
Simulation time 49015097 ps
CPU time 1.49 seconds
Started Jun 29 05:32:38 PM PDT 24
Finished Jun 29 05:32:41 PM PDT 24
Peak memory 217160 kb
Host smart-39251a1f-207b-496b-b3c4-96980efbe448
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104258509 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1104258509
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1622944698
Short name T213
Test name
Test status
Simulation time 124828377 ps
CPU time 1.27 seconds
Started Jun 29 05:32:43 PM PDT 24
Finished Jun 29 05:32:47 PM PDT 24
Peak memory 217204 kb
Host smart-3b766912-bc8d-4fb5-a13b-c9188105578d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622944698 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1622944698
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_disable.2812745359
Short name T177
Test name
Test status
Simulation time 33608124 ps
CPU time 0.82 seconds
Started Jun 29 05:32:43 PM PDT 24
Finished Jun 29 05:32:47 PM PDT 24
Peak memory 216640 kb
Host smart-924bc1b2-0337-4fbf-bd57-13c8bf1d7b7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812745359 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2812745359
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/63.edn_err.12769496
Short name T190
Test name
Test status
Simulation time 72790968 ps
CPU time 0.88 seconds
Started Jun 29 05:33:09 PM PDT 24
Finished Jun 29 05:33:11 PM PDT 24
Peak memory 218732 kb
Host smart-061c9c96-55bc-46f7-b8ed-2628fae05404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12769496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.12769496
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.1384830794
Short name T361
Test name
Test status
Simulation time 86032776 ps
CPU time 0.77 seconds
Started Jun 29 05:31:40 PM PDT 24
Finished Jun 29 05:31:42 PM PDT 24
Peak memory 206640 kb
Host smart-87080670-06c4-43e8-9698-9dd741647700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384830794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1384830794
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/193.edn_genbits.4047950749
Short name T326
Test name
Test status
Simulation time 83391564 ps
CPU time 3.04 seconds
Started Jun 29 05:33:46 PM PDT 24
Finished Jun 29 05:33:51 PM PDT 24
Peak memory 219152 kb
Host smart-190e9c1d-f142-4e93-8744-2300fa154825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047950749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.4047950749
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_genbits.788820269
Short name T83
Test name
Test status
Simulation time 22583073 ps
CPU time 1.19 seconds
Started Jun 29 05:33:15 PM PDT 24
Finished Jun 29 05:33:17 PM PDT 24
Peak memory 219928 kb
Host smart-b4d9e824-0033-490f-bb0d-b46042d24e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788820269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.788820269
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_genbits.56883254
Short name T84
Test name
Test status
Simulation time 55656501 ps
CPU time 1.32 seconds
Started Jun 29 05:33:24 PM PDT 24
Finished Jun 29 05:33:26 PM PDT 24
Peak memory 220260 kb
Host smart-62865415-a2b4-4819-8c24-cc6cb268400c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56883254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.56883254
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.1993594304
Short name T396
Test name
Test status
Simulation time 48757517 ps
CPU time 1.15 seconds
Started Jun 29 05:33:35 PM PDT 24
Finished Jun 29 05:33:37 PM PDT 24
Peak memory 219444 kb
Host smart-e7268fae-38ca-40dc-8266-e5fc39d63be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993594304 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.1993594304
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.4091580294
Short name T398
Test name
Test status
Simulation time 74589693 ps
CPU time 1.67 seconds
Started Jun 29 05:33:41 PM PDT 24
Finished Jun 29 05:33:44 PM PDT 24
Peak memory 218848 kb
Host smart-1ce8f200-db0f-4614-9940-309e4af18896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091580294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.4091580294
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.983460312
Short name T95
Test name
Test status
Simulation time 38260274 ps
CPU time 0.89 seconds
Started Jun 29 05:31:40 PM PDT 24
Finished Jun 29 05:31:41 PM PDT 24
Peak memory 215892 kb
Host smart-884dc91c-183e-4ce5-955e-63145ff5cf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983460312 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.983460312
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/182.edn_genbits.3261971931
Short name T341
Test name
Test status
Simulation time 125439559 ps
CPU time 1.45 seconds
Started Jun 29 05:33:41 PM PDT 24
Finished Jun 29 05:33:44 PM PDT 24
Peak memory 220524 kb
Host smart-fad918bc-f0a9-4c2f-b7f3-6cccfeaa6da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261971931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3261971931
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_genbits.815674769
Short name T13
Test name
Test status
Simulation time 75546588 ps
CPU time 1.47 seconds
Started Jun 29 05:33:25 PM PDT 24
Finished Jun 29 05:33:27 PM PDT 24
Peak memory 217872 kb
Host smart-78727bee-ab53-42dd-a305-695bbb2a28af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815674769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.815674769
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1432898768
Short name T264
Test name
Test status
Simulation time 43707083 ps
CPU time 0.9 seconds
Started Jun 29 05:29:54 PM PDT 24
Finished Jun 29 05:29:56 PM PDT 24
Peak memory 206920 kb
Host smart-709c2540-7c0f-4c98-a488-f48a28ca74eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432898768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1432898768
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3086639942
Short name T296
Test name
Test status
Simulation time 134797045 ps
CPU time 2.49 seconds
Started Jun 29 05:30:26 PM PDT 24
Finished Jun 29 05:30:29 PM PDT 24
Peak memory 206944 kb
Host smart-c1d2e0b9-e887-4c9b-b185-a69add59eada
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086639942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3086639942
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/default/104.edn_genbits.3750214053
Short name T62
Test name
Test status
Simulation time 45155716 ps
CPU time 1.2 seconds
Started Jun 29 05:33:32 PM PDT 24
Finished Jun 29 05:33:35 PM PDT 24
Peak memory 217676 kb
Host smart-1fb6f714-c245-4bd6-8784-bbd18e74ae3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750214053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3750214053
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.3035491865
Short name T736
Test name
Test status
Simulation time 68816952 ps
CPU time 1.63 seconds
Started Jun 29 05:33:29 PM PDT 24
Finished Jun 29 05:33:32 PM PDT 24
Peak memory 218036 kb
Host smart-eb720e90-1b11-435b-8b9c-d814bdefc45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035491865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3035491865
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_genbits.2754778106
Short name T329
Test name
Test status
Simulation time 38154718 ps
CPU time 1.71 seconds
Started Jun 29 05:32:03 PM PDT 24
Finished Jun 29 05:32:05 PM PDT 24
Peak memory 217720 kb
Host smart-e6ba065b-3973-4410-b4fa-d068612e11c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754778106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2754778106
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/110.edn_genbits.2041188211
Short name T73
Test name
Test status
Simulation time 33391603 ps
CPU time 1.54 seconds
Started Jun 29 05:33:31 PM PDT 24
Finished Jun 29 05:33:34 PM PDT 24
Peak memory 217784 kb
Host smart-7817b902-3e2c-4509-9b79-2ff516332f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041188211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2041188211
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.245447493
Short name T286
Test name
Test status
Simulation time 43911471 ps
CPU time 1.53 seconds
Started Jun 29 05:33:41 PM PDT 24
Finished Jun 29 05:33:43 PM PDT 24
Peak memory 217576 kb
Host smart-c37102b1-dca1-4c06-9857-9cf19f65a819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245447493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.245447493
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.3501883105
Short name T324
Test name
Test status
Simulation time 60604782 ps
CPU time 1.74 seconds
Started Jun 29 05:33:28 PM PDT 24
Finished Jun 29 05:33:30 PM PDT 24
Peak memory 217752 kb
Host smart-2c815d2c-cadd-480c-8397-6a112e16a7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501883105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3501883105
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.2836371930
Short name T701
Test name
Test status
Simulation time 49319401 ps
CPU time 1.95 seconds
Started Jun 29 05:33:31 PM PDT 24
Finished Jun 29 05:33:34 PM PDT 24
Peak memory 219088 kb
Host smart-9d1243c6-a11e-4297-a296-1cbb48a2f8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836371930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2836371930
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1893885645
Short name T232
Test name
Test status
Simulation time 19494892891 ps
CPU time 271.98 seconds
Started Jun 29 05:32:11 PM PDT 24
Finished Jun 29 05:36:45 PM PDT 24
Peak memory 217132 kb
Host smart-da40530b-1c49-4ce7-890a-d374c388883b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893885645 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1893885645
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2566525520
Short name T231
Test name
Test status
Simulation time 81586696240 ps
CPU time 1043.37 seconds
Started Jun 29 05:31:44 PM PDT 24
Finished Jun 29 05:49:08 PM PDT 24
Peak memory 223380 kb
Host smart-e211096d-b58c-4317-9e89-d7eb6cba64b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566525520 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2566525520
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.edn_genbits.4036066981
Short name T336
Test name
Test status
Simulation time 39466075 ps
CPU time 1.25 seconds
Started Jun 29 05:32:21 PM PDT 24
Finished Jun 29 05:32:24 PM PDT 24
Peak memory 218904 kb
Host smart-8221c2fb-f6b2-4853-b078-a8de58950694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036066981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.4036066981
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3079900849
Short name T288
Test name
Test status
Simulation time 33348672 ps
CPU time 1.32 seconds
Started Jun 29 05:32:40 PM PDT 24
Finished Jun 29 05:32:44 PM PDT 24
Peak memory 217324 kb
Host smart-c80e2f6b-8300-4b7e-993e-265aa3b7a1fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079900849 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3079900849
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_intr.307497653
Short name T96
Test name
Test status
Simulation time 21956020 ps
CPU time 1.02 seconds
Started Jun 29 05:32:33 PM PDT 24
Finished Jun 29 05:32:35 PM PDT 24
Peak memory 215968 kb
Host smart-bc9274f6-8bae-4324-9ad5-d2f29bf1eb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307497653 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.307497653
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/163.edn_alert.3819180376
Short name T114
Test name
Test status
Simulation time 55896017 ps
CPU time 1.22 seconds
Started Jun 29 05:33:43 PM PDT 24
Finished Jun 29 05:33:47 PM PDT 24
Peak memory 218900 kb
Host smart-361099b3-201e-40c7-8ca1-abceb2559941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819180376 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.3819180376
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.1952460345
Short name T94
Test name
Test status
Simulation time 60714924 ps
CPU time 2.05 seconds
Started Jun 29 05:33:43 PM PDT 24
Finished Jun 29 05:33:47 PM PDT 24
Peak memory 218952 kb
Host smart-fe8d4895-875d-45da-9cdb-bed022ca6b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952460345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1952460345
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_err.3959231479
Short name T141
Test name
Test status
Simulation time 23758110 ps
CPU time 1.16 seconds
Started Jun 29 05:32:25 PM PDT 24
Finished Jun 29 05:32:26 PM PDT 24
Peak memory 218932 kb
Host smart-552a9f6d-30fc-4cbc-953d-58b965e207aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959231479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3959231479
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/262.edn_genbits.437965032
Short name T931
Test name
Test status
Simulation time 33488770 ps
CPU time 1.44 seconds
Started Jun 29 05:34:04 PM PDT 24
Finished Jun 29 05:34:06 PM PDT 24
Peak memory 219228 kb
Host smart-a2b9a00f-6fa2-4788-b0ee-fa8cbb15f79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437965032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.437965032
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.4091941820
Short name T1114
Test name
Test status
Simulation time 30234727 ps
CPU time 1.24 seconds
Started Jun 29 05:29:57 PM PDT 24
Finished Jun 29 05:29:59 PM PDT 24
Peak memory 206844 kb
Host smart-94fe073c-ec97-4772-99a0-91f8ef32b114
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091941820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.4091941820
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3254250608
Short name T1121
Test name
Test status
Simulation time 21535959 ps
CPU time 1.07 seconds
Started Jun 29 05:29:55 PM PDT 24
Finished Jun 29 05:29:57 PM PDT 24
Peak memory 206920 kb
Host smart-ec4a9f8a-a5bc-4e17-a0f0-222e74f9eca0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254250608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3254250608
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3268857459
Short name T1126
Test name
Test status
Simulation time 13887409 ps
CPU time 1.15 seconds
Started Jun 29 05:29:56 PM PDT 24
Finished Jun 29 05:29:58 PM PDT 24
Peak memory 217064 kb
Host smart-ff5ecaa6-204a-4ed1-80be-53ddce911b56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268857459 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3268857459
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1026577334
Short name T1081
Test name
Test status
Simulation time 67851986 ps
CPU time 1.01 seconds
Started Jun 29 05:29:54 PM PDT 24
Finished Jun 29 05:29:55 PM PDT 24
Peak memory 206920 kb
Host smart-8f8fe441-eed6-41b3-a4d2-1e8e31e03b0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026577334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1026577334
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2451205529
Short name T1032
Test name
Test status
Simulation time 21273704 ps
CPU time 1.01 seconds
Started Jun 29 05:29:56 PM PDT 24
Finished Jun 29 05:29:58 PM PDT 24
Peak memory 206824 kb
Host smart-c8deeb50-6dc0-49ca-bbbb-6ef1d625e520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451205529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2451205529
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1167769931
Short name T1039
Test name
Test status
Simulation time 50835723 ps
CPU time 0.95 seconds
Started Jun 29 05:29:56 PM PDT 24
Finished Jun 29 05:29:58 PM PDT 24
Peak memory 206944 kb
Host smart-7d549e3b-be55-4eff-a779-8700bb5b980c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167769931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1167769931
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1663803978
Short name T1017
Test name
Test status
Simulation time 870223232 ps
CPU time 2.84 seconds
Started Jun 29 05:29:51 PM PDT 24
Finished Jun 29 05:29:55 PM PDT 24
Peak memory 215252 kb
Host smart-3c96fb9b-b38c-4825-bdf4-b53a47e5a483
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663803978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1663803978
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2784773468
Short name T1050
Test name
Test status
Simulation time 209103624 ps
CPU time 1.73 seconds
Started Jun 29 05:29:54 PM PDT 24
Finished Jun 29 05:29:57 PM PDT 24
Peak memory 215108 kb
Host smart-9d4e04c2-b090-4387-8046-b6886b32a811
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784773468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2784773468
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.225874501
Short name T1073
Test name
Test status
Simulation time 148269165 ps
CPU time 1.48 seconds
Started Jun 29 05:29:55 PM PDT 24
Finished Jun 29 05:29:58 PM PDT 24
Peak memory 206944 kb
Host smart-eb052f69-d061-4382-8b42-df14b17ae55a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225874501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.225874501
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1572152746
Short name T1127
Test name
Test status
Simulation time 69319175 ps
CPU time 2.03 seconds
Started Jun 29 05:29:55 PM PDT 24
Finished Jun 29 05:29:58 PM PDT 24
Peak memory 206864 kb
Host smart-6081eb31-3395-4def-b5f8-e19d781988d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572152746 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1572152746
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.4240193406
Short name T265
Test name
Test status
Simulation time 55332693 ps
CPU time 0.96 seconds
Started Jun 29 05:29:53 PM PDT 24
Finished Jun 29 05:29:54 PM PDT 24
Peak memory 206924 kb
Host smart-8cff9c05-4c16-4d5f-aba1-589140975da7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240193406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.4240193406
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1008717977
Short name T1123
Test name
Test status
Simulation time 100730362 ps
CPU time 1.31 seconds
Started Jun 29 05:30:01 PM PDT 24
Finished Jun 29 05:30:04 PM PDT 24
Peak memory 217308 kb
Host smart-44c98ca3-2c5e-4ee3-a4ec-29e166130da9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008717977 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1008717977
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1048322413
Short name T1018
Test name
Test status
Simulation time 13039169 ps
CPU time 0.93 seconds
Started Jun 29 05:29:56 PM PDT 24
Finished Jun 29 05:29:58 PM PDT 24
Peak memory 206852 kb
Host smart-cb23f24b-6e2b-465a-a7c8-0701efc9039a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048322413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1048322413
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3006687656
Short name T1064
Test name
Test status
Simulation time 43862474 ps
CPU time 1.14 seconds
Started Jun 29 05:29:56 PM PDT 24
Finished Jun 29 05:29:58 PM PDT 24
Peak memory 206912 kb
Host smart-47363893-65aa-4e7d-9f3a-5fe7c11eea64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006687656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3006687656
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3221353348
Short name T1106
Test name
Test status
Simulation time 31901446 ps
CPU time 2.21 seconds
Started Jun 29 05:29:55 PM PDT 24
Finished Jun 29 05:29:58 PM PDT 24
Peak memory 215196 kb
Host smart-075f6f69-9edf-4a8a-9c73-002ab68e1312
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221353348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3221353348
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3388518895
Short name T1036
Test name
Test status
Simulation time 55545595 ps
CPU time 1.77 seconds
Started Jun 29 05:29:55 PM PDT 24
Finished Jun 29 05:29:58 PM PDT 24
Peak memory 207052 kb
Host smart-40f105ba-067e-42c5-9931-182f796a389f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388518895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3388518895
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3739165076
Short name T998
Test name
Test status
Simulation time 78104068 ps
CPU time 1.44 seconds
Started Jun 29 05:30:12 PM PDT 24
Finished Jun 29 05:30:15 PM PDT 24
Peak memory 215240 kb
Host smart-422316bc-d44f-440a-8a63-b618bf76938e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739165076 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3739165076
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1517199333
Short name T279
Test name
Test status
Simulation time 12444863 ps
CPU time 0.95 seconds
Started Jun 29 05:30:10 PM PDT 24
Finished Jun 29 05:30:13 PM PDT 24
Peak memory 206860 kb
Host smart-5d48926c-44e9-476f-8b95-53b5c1aa681d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517199333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1517199333
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1414104880
Short name T1044
Test name
Test status
Simulation time 21449331 ps
CPU time 0.88 seconds
Started Jun 29 05:30:09 PM PDT 24
Finished Jun 29 05:30:11 PM PDT 24
Peak memory 206784 kb
Host smart-8270ce4f-6e9b-463d-be06-7a4ac8a0c78b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414104880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1414104880
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2069014760
Short name T1100
Test name
Test status
Simulation time 24579413 ps
CPU time 0.98 seconds
Started Jun 29 05:30:10 PM PDT 24
Finished Jun 29 05:30:12 PM PDT 24
Peak memory 206980 kb
Host smart-144c3f10-03aa-4189-bf23-08e5d5aff658
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069014760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2069014760
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2770221701
Short name T1087
Test name
Test status
Simulation time 1375122668 ps
CPU time 3.36 seconds
Started Jun 29 05:30:11 PM PDT 24
Finished Jun 29 05:30:15 PM PDT 24
Peak memory 215268 kb
Host smart-e440df81-5d5a-4d75-b09b-a93f495258ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770221701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2770221701
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3088102242
Short name T1029
Test name
Test status
Simulation time 152281831 ps
CPU time 1.06 seconds
Started Jun 29 05:30:10 PM PDT 24
Finished Jun 29 05:30:13 PM PDT 24
Peak memory 215148 kb
Host smart-f8ef2f73-409c-4476-af1e-ddad7fe82228
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088102242 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3088102242
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2443464469
Short name T1120
Test name
Test status
Simulation time 41995106 ps
CPU time 0.9 seconds
Started Jun 29 05:30:10 PM PDT 24
Finished Jun 29 05:30:13 PM PDT 24
Peak memory 206808 kb
Host smart-930f8d34-2d17-40db-aa2e-75b85148ade8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443464469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2443464469
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1161615757
Short name T1089
Test name
Test status
Simulation time 90694317 ps
CPU time 0.88 seconds
Started Jun 29 05:30:11 PM PDT 24
Finished Jun 29 05:30:13 PM PDT 24
Peak memory 206864 kb
Host smart-8ac809ac-baaf-4a7e-858e-29c4734888cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161615757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1161615757
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3937417643
Short name T282
Test name
Test status
Simulation time 117221921 ps
CPU time 1.36 seconds
Started Jun 29 05:30:10 PM PDT 24
Finished Jun 29 05:30:12 PM PDT 24
Peak memory 206840 kb
Host smart-f0c0c107-146e-43bf-9c87-65b5bb1cd8c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937417643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3937417643
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.714475718
Short name T1071
Test name
Test status
Simulation time 338900701 ps
CPU time 4.3 seconds
Started Jun 29 05:30:09 PM PDT 24
Finished Jun 29 05:30:14 PM PDT 24
Peak memory 219356 kb
Host smart-4ef2bcc6-c4be-4bdc-a7fd-53c6d39b53f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714475718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.714475718
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.600028368
Short name T1047
Test name
Test status
Simulation time 64006025 ps
CPU time 2 seconds
Started Jun 29 05:30:11 PM PDT 24
Finished Jun 29 05:30:14 PM PDT 24
Peak memory 206920 kb
Host smart-39775f2b-3f3b-45b9-9256-7d2d064179b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600028368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.600028368
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3866007689
Short name T1109
Test name
Test status
Simulation time 30138644 ps
CPU time 1.06 seconds
Started Jun 29 05:30:19 PM PDT 24
Finished Jun 29 05:30:21 PM PDT 24
Peak memory 206980 kb
Host smart-35f1cfaf-512d-4211-b35b-1d10a0df4fa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866007689 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3866007689
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2243929708
Short name T1096
Test name
Test status
Simulation time 20809798 ps
CPU time 0.83 seconds
Started Jun 29 05:30:20 PM PDT 24
Finished Jun 29 05:30:21 PM PDT 24
Peak memory 206740 kb
Host smart-c42dfec0-3ce8-45e3-b7dc-6a318733b7b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243929708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2243929708
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1918191115
Short name T1075
Test name
Test status
Simulation time 11431042 ps
CPU time 0.91 seconds
Started Jun 29 05:30:21 PM PDT 24
Finished Jun 29 05:30:22 PM PDT 24
Peak memory 206860 kb
Host smart-19a31014-9d86-4ffe-ac37-30f57fae2783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918191115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1918191115
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2825542124
Short name T278
Test name
Test status
Simulation time 55877213 ps
CPU time 1.11 seconds
Started Jun 29 05:30:25 PM PDT 24
Finished Jun 29 05:30:27 PM PDT 24
Peak memory 206904 kb
Host smart-38732061-b793-4a93-91cd-0abc5890322e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825542124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2825542124
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2823236269
Short name T1128
Test name
Test status
Simulation time 365078593 ps
CPU time 3.28 seconds
Started Jun 29 05:30:18 PM PDT 24
Finished Jun 29 05:30:22 PM PDT 24
Peak memory 215148 kb
Host smart-fc9820b9-0abb-49a1-88b8-0f49a2f51e6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823236269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2823236269
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2684104831
Short name T302
Test name
Test status
Simulation time 59736277 ps
CPU time 1.81 seconds
Started Jun 29 05:30:18 PM PDT 24
Finished Jun 29 05:30:20 PM PDT 24
Peak memory 215116 kb
Host smart-21f95794-e439-43fc-b0b2-c2c92e374ba8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684104831 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2684104831
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2072184581
Short name T1068
Test name
Test status
Simulation time 140857078 ps
CPU time 1.28 seconds
Started Jun 29 05:30:22 PM PDT 24
Finished Jun 29 05:30:24 PM PDT 24
Peak memory 215200 kb
Host smart-8d6c8ce3-0a26-48ef-8563-de5c3f06fdd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072184581 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2072184581
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3385275007
Short name T270
Test name
Test status
Simulation time 13684428 ps
CPU time 0.96 seconds
Started Jun 29 05:30:19 PM PDT 24
Finished Jun 29 05:30:20 PM PDT 24
Peak memory 206916 kb
Host smart-5c18c845-366f-496f-939b-de574370e625
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385275007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3385275007
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2932201190
Short name T1118
Test name
Test status
Simulation time 36319429 ps
CPU time 0.84 seconds
Started Jun 29 05:30:18 PM PDT 24
Finished Jun 29 05:30:19 PM PDT 24
Peak memory 206804 kb
Host smart-3cd098a3-0a6e-41bf-8cbc-459487ac6a4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932201190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2932201190
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2015860050
Short name T263
Test name
Test status
Simulation time 56563136 ps
CPU time 1.17 seconds
Started Jun 29 05:30:18 PM PDT 24
Finished Jun 29 05:30:20 PM PDT 24
Peak memory 206980 kb
Host smart-7cf6ebb9-2d25-4faa-b1fc-7b3b9c9d627f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015860050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2015860050
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2272179294
Short name T1040
Test name
Test status
Simulation time 68707671 ps
CPU time 2.77 seconds
Started Jun 29 05:30:18 PM PDT 24
Finished Jun 29 05:30:22 PM PDT 24
Peak memory 215268 kb
Host smart-5690ae63-937a-496e-a6af-c93db130c89d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272179294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2272179294
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.4059029975
Short name T1092
Test name
Test status
Simulation time 50496534 ps
CPU time 1.7 seconds
Started Jun 29 05:30:20 PM PDT 24
Finished Jun 29 05:30:22 PM PDT 24
Peak memory 206920 kb
Host smart-faa4d02b-ed13-4d81-a7d1-de1cc2d1be77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059029975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.4059029975
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1829929916
Short name T1027
Test name
Test status
Simulation time 21012889 ps
CPU time 1.11 seconds
Started Jun 29 05:30:24 PM PDT 24
Finished Jun 29 05:30:26 PM PDT 24
Peak memory 215164 kb
Host smart-a5e1b4bf-29c6-44f6-baa6-ec9788d2ca32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829929916 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1829929916
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1752186360
Short name T275
Test name
Test status
Simulation time 13647349 ps
CPU time 0.97 seconds
Started Jun 29 05:30:18 PM PDT 24
Finished Jun 29 05:30:19 PM PDT 24
Peak memory 206920 kb
Host smart-3ed11281-c274-49c3-abb1-849dc330c9c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752186360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1752186360
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2804917882
Short name T1008
Test name
Test status
Simulation time 13311613 ps
CPU time 0.92 seconds
Started Jun 29 05:30:19 PM PDT 24
Finished Jun 29 05:30:20 PM PDT 24
Peak memory 206864 kb
Host smart-0c06ae55-1303-4a1d-abb2-5778647a1ec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804917882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2804917882
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3232581007
Short name T1102
Test name
Test status
Simulation time 16248994 ps
CPU time 1.04 seconds
Started Jun 29 05:30:20 PM PDT 24
Finished Jun 29 05:30:22 PM PDT 24
Peak memory 206904 kb
Host smart-654b4418-7afc-422c-b8bb-71a4addb03f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232581007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3232581007
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2893979668
Short name T1078
Test name
Test status
Simulation time 444154810 ps
CPU time 3.54 seconds
Started Jun 29 05:30:19 PM PDT 24
Finished Jun 29 05:30:23 PM PDT 24
Peak memory 215408 kb
Host smart-1964a3f5-02d3-4065-9884-4d137c311723
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893979668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2893979668
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2432906612
Short name T1062
Test name
Test status
Simulation time 50192323 ps
CPU time 1.68 seconds
Started Jun 29 05:30:18 PM PDT 24
Finished Jun 29 05:30:20 PM PDT 24
Peak memory 206924 kb
Host smart-1dc7ffd4-ab55-43d7-beca-c9e43452af33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432906612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2432906612
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2783252789
Short name T1007
Test name
Test status
Simulation time 69724420 ps
CPU time 1.43 seconds
Started Jun 29 05:30:19 PM PDT 24
Finished Jun 29 05:30:21 PM PDT 24
Peak memory 215324 kb
Host smart-364d13f1-3648-4fe4-a308-b8c6d7b4a9e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783252789 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2783252789
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.919296363
Short name T276
Test name
Test status
Simulation time 11616710 ps
CPU time 0.86 seconds
Started Jun 29 05:30:24 PM PDT 24
Finished Jun 29 05:30:26 PM PDT 24
Peak memory 206908 kb
Host smart-d5527730-2709-4f5b-8bf3-200b3ba48a65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919296363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.919296363
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1754170142
Short name T1090
Test name
Test status
Simulation time 15914315 ps
CPU time 0.77 seconds
Started Jun 29 05:30:18 PM PDT 24
Finished Jun 29 05:30:20 PM PDT 24
Peak memory 206688 kb
Host smart-3d2ef8fd-87d3-4bab-be6c-422319b03c75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754170142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1754170142
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1270088232
Short name T1076
Test name
Test status
Simulation time 23511854 ps
CPU time 1.17 seconds
Started Jun 29 05:30:17 PM PDT 24
Finished Jun 29 05:30:19 PM PDT 24
Peak memory 206808 kb
Host smart-0f3c2e3c-3137-4f66-846b-2793ad29d222
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270088232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1270088232
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.935401335
Short name T1038
Test name
Test status
Simulation time 54664980 ps
CPU time 2.38 seconds
Started Jun 29 05:30:21 PM PDT 24
Finished Jun 29 05:30:24 PM PDT 24
Peak memory 215252 kb
Host smart-d9241c33-8de8-41be-9cea-aa5f58b204ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935401335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.935401335
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1530177388
Short name T1105
Test name
Test status
Simulation time 305269042 ps
CPU time 2.88 seconds
Started Jun 29 05:30:21 PM PDT 24
Finished Jun 29 05:30:24 PM PDT 24
Peak memory 206996 kb
Host smart-8eeabe07-f750-4a4a-b446-83253fdda5f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530177388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1530177388
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.227233822
Short name T1042
Test name
Test status
Simulation time 20986949 ps
CPU time 1.51 seconds
Started Jun 29 05:30:27 PM PDT 24
Finished Jun 29 05:30:29 PM PDT 24
Peak memory 219196 kb
Host smart-954e6829-0f1c-46b7-a520-763a0fa998cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227233822 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.227233822
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3925584891
Short name T1060
Test name
Test status
Simulation time 36904482 ps
CPU time 0.95 seconds
Started Jun 29 05:30:25 PM PDT 24
Finished Jun 29 05:30:27 PM PDT 24
Peak memory 206904 kb
Host smart-f80c5f70-6c36-41f8-b4c7-b98ea78ebf52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925584891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3925584891
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3513587694
Short name T1051
Test name
Test status
Simulation time 116067468 ps
CPU time 0.89 seconds
Started Jun 29 05:30:20 PM PDT 24
Finished Jun 29 05:30:21 PM PDT 24
Peak memory 206928 kb
Host smart-7db290f1-f3b4-4e9d-bb2d-0149cff343e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513587694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3513587694
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1675446275
Short name T1037
Test name
Test status
Simulation time 24410014 ps
CPU time 1.16 seconds
Started Jun 29 05:30:26 PM PDT 24
Finished Jun 29 05:30:28 PM PDT 24
Peak memory 206860 kb
Host smart-f1e6387f-80fc-402c-9fbc-76e845a502a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675446275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1675446275
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3056393534
Short name T1058
Test name
Test status
Simulation time 46973483 ps
CPU time 1.87 seconds
Started Jun 29 05:30:20 PM PDT 24
Finished Jun 29 05:30:22 PM PDT 24
Peak memory 215248 kb
Host smart-3f304f98-1540-4570-8ded-008e5376ef0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056393534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3056393534
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3453517319
Short name T1074
Test name
Test status
Simulation time 32058159 ps
CPU time 1.38 seconds
Started Jun 29 05:30:38 PM PDT 24
Finished Jun 29 05:30:41 PM PDT 24
Peak memory 215120 kb
Host smart-2c9d0937-4886-4e39-8720-9b2b1967cbd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453517319 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3453517319
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.384992165
Short name T1041
Test name
Test status
Simulation time 61607861 ps
CPU time 0.85 seconds
Started Jun 29 05:30:27 PM PDT 24
Finished Jun 29 05:30:28 PM PDT 24
Peak memory 206840 kb
Host smart-b050b696-b568-493a-95d9-c5c6512b0926
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384992165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.384992165
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3487374048
Short name T1059
Test name
Test status
Simulation time 33078689 ps
CPU time 0.86 seconds
Started Jun 29 05:30:27 PM PDT 24
Finished Jun 29 05:30:29 PM PDT 24
Peak memory 206684 kb
Host smart-13f2f988-b090-4c0f-8113-864d35d45cc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487374048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3487374048
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2383724266
Short name T280
Test name
Test status
Simulation time 43742595 ps
CPU time 1.59 seconds
Started Jun 29 05:30:25 PM PDT 24
Finished Jun 29 05:30:27 PM PDT 24
Peak memory 206920 kb
Host smart-2f5ebbbf-e277-4fbd-9b8b-9163aa898aca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383724266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2383724266
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2835576265
Short name T1063
Test name
Test status
Simulation time 57775620 ps
CPU time 1.71 seconds
Started Jun 29 05:30:25 PM PDT 24
Finished Jun 29 05:30:27 PM PDT 24
Peak memory 215248 kb
Host smart-e58f937b-be9d-4910-8878-a234b45ed958
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835576265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2835576265
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3138465894
Short name T295
Test name
Test status
Simulation time 63737402 ps
CPU time 1.93 seconds
Started Jun 29 05:30:27 PM PDT 24
Finished Jun 29 05:30:30 PM PDT 24
Peak memory 206944 kb
Host smart-ce55693b-3013-4e9a-8fc8-d83d3750e8cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138465894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3138465894
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3679234032
Short name T1000
Test name
Test status
Simulation time 57393786 ps
CPU time 2.21 seconds
Started Jun 29 05:30:25 PM PDT 24
Finished Jun 29 05:30:28 PM PDT 24
Peak memory 215176 kb
Host smart-8fcd5489-f809-4f36-965c-e33be6812e3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679234032 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3679234032
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1628002334
Short name T1009
Test name
Test status
Simulation time 69389351 ps
CPU time 0.9 seconds
Started Jun 29 05:30:38 PM PDT 24
Finished Jun 29 05:30:40 PM PDT 24
Peak memory 206892 kb
Host smart-89cdff23-304b-49d2-93a2-cb6110de5f05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628002334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1628002334
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.562065967
Short name T1028
Test name
Test status
Simulation time 14624020 ps
CPU time 0.96 seconds
Started Jun 29 05:30:25 PM PDT 24
Finished Jun 29 05:30:27 PM PDT 24
Peak memory 206796 kb
Host smart-8306accf-cccd-43ce-b37d-e791df8d4a27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562065967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.562065967
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3564560527
Short name T1097
Test name
Test status
Simulation time 30844992 ps
CPU time 1.14 seconds
Started Jun 29 05:30:26 PM PDT 24
Finished Jun 29 05:30:28 PM PDT 24
Peak memory 206984 kb
Host smart-4e71c850-fde5-40c8-8b29-9df85bcc8c1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564560527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3564560527
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3677137585
Short name T1048
Test name
Test status
Simulation time 396978629 ps
CPU time 3.65 seconds
Started Jun 29 05:30:26 PM PDT 24
Finished Jun 29 05:30:30 PM PDT 24
Peak memory 223364 kb
Host smart-12b6822c-303c-4da2-8be9-60422d0174c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677137585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3677137585
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.219984400
Short name T294
Test name
Test status
Simulation time 135734739 ps
CPU time 1.47 seconds
Started Jun 29 05:30:26 PM PDT 24
Finished Jun 29 05:30:29 PM PDT 24
Peak memory 206844 kb
Host smart-dd7a1939-3746-4b68-af14-7672d5a799a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219984400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.219984400
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.387885174
Short name T1003
Test name
Test status
Simulation time 54576153 ps
CPU time 1.16 seconds
Started Jun 29 05:30:26 PM PDT 24
Finished Jun 29 05:30:27 PM PDT 24
Peak memory 215096 kb
Host smart-04c6165f-c92d-4cfa-a7e5-ca3d1d7824ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387885174 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.387885174
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2294779132
Short name T1085
Test name
Test status
Simulation time 16833464 ps
CPU time 0.95 seconds
Started Jun 29 05:30:38 PM PDT 24
Finished Jun 29 05:30:41 PM PDT 24
Peak memory 206888 kb
Host smart-1810b87a-496a-4e60-9dcb-d707cb1cc1ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294779132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2294779132
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.4025768217
Short name T996
Test name
Test status
Simulation time 24411467 ps
CPU time 0.89 seconds
Started Jun 29 05:30:27 PM PDT 24
Finished Jun 29 05:30:29 PM PDT 24
Peak memory 206864 kb
Host smart-2d642273-f645-4977-98ab-cee7d3491d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025768217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.4025768217
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3804561615
Short name T1045
Test name
Test status
Simulation time 15460446 ps
CPU time 1.01 seconds
Started Jun 29 05:30:30 PM PDT 24
Finished Jun 29 05:30:31 PM PDT 24
Peak memory 206908 kb
Host smart-b0ab22ab-f557-4c21-8fa1-efe840cc290d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804561615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3804561615
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.512338016
Short name T1088
Test name
Test status
Simulation time 44481971 ps
CPU time 3.1 seconds
Started Jun 29 05:30:25 PM PDT 24
Finished Jun 29 05:30:28 PM PDT 24
Peak memory 215192 kb
Host smart-c82348a1-3800-4159-98c8-5ad07695de78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512338016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.512338016
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3472815938
Short name T1079
Test name
Test status
Simulation time 53797389 ps
CPU time 1.81 seconds
Started Jun 29 05:30:28 PM PDT 24
Finished Jun 29 05:30:31 PM PDT 24
Peak memory 206988 kb
Host smart-7dd961a3-9a4b-42f1-a5d0-f276733e4fc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472815938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3472815938
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4100177243
Short name T272
Test name
Test status
Simulation time 38898171 ps
CPU time 1.72 seconds
Started Jun 29 05:30:00 PM PDT 24
Finished Jun 29 05:30:03 PM PDT 24
Peak memory 206860 kb
Host smart-1f6a9814-5b45-42b0-9dde-8c67ce8099f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100177243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.4100177243
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1284160723
Short name T1002
Test name
Test status
Simulation time 62524471 ps
CPU time 2.06 seconds
Started Jun 29 05:30:01 PM PDT 24
Finished Jun 29 05:30:05 PM PDT 24
Peak memory 207028 kb
Host smart-a062ff76-4f5b-40cf-9607-2e1c33436861
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284160723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1284160723
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1152211664
Short name T269
Test name
Test status
Simulation time 25881956 ps
CPU time 0.9 seconds
Started Jun 29 05:30:00 PM PDT 24
Finished Jun 29 05:30:02 PM PDT 24
Peak memory 206864 kb
Host smart-8b16ca88-2a76-4aca-8a34-788b2ac458f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152211664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1152211664
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1329210626
Short name T1129
Test name
Test status
Simulation time 43792080 ps
CPU time 1.22 seconds
Started Jun 29 05:30:00 PM PDT 24
Finished Jun 29 05:30:03 PM PDT 24
Peak memory 215172 kb
Host smart-80af85e6-12e7-4326-8707-2ce012dbb7cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329210626 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1329210626
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3363470403
Short name T268
Test name
Test status
Simulation time 96782784 ps
CPU time 0.9 seconds
Started Jun 29 05:30:04 PM PDT 24
Finished Jun 29 05:30:06 PM PDT 24
Peak memory 206880 kb
Host smart-857bbdd6-1be7-41b7-aee9-a14ee60a18bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363470403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3363470403
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2176129158
Short name T1025
Test name
Test status
Simulation time 50173022 ps
CPU time 0.89 seconds
Started Jun 29 05:30:01 PM PDT 24
Finished Jun 29 05:30:04 PM PDT 24
Peak memory 206688 kb
Host smart-5c8a81e9-9d27-4c60-b4d1-666e348f9a1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176129158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2176129158
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2911271538
Short name T281
Test name
Test status
Simulation time 240482556 ps
CPU time 1.52 seconds
Started Jun 29 05:30:00 PM PDT 24
Finished Jun 29 05:30:03 PM PDT 24
Peak memory 206924 kb
Host smart-df2815e9-6a77-4b6b-9f53-7f28d64aaa0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911271538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2911271538
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1049808627
Short name T1012
Test name
Test status
Simulation time 109441928 ps
CPU time 2.72 seconds
Started Jun 29 05:29:59 PM PDT 24
Finished Jun 29 05:30:02 PM PDT 24
Peak memory 215120 kb
Host smart-12cd19e3-a0d9-45a4-bfe4-9a34c04d1095
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049808627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1049808627
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.524148741
Short name T1053
Test name
Test status
Simulation time 47965044 ps
CPU time 1.68 seconds
Started Jun 29 05:30:00 PM PDT 24
Finished Jun 29 05:30:03 PM PDT 24
Peak memory 207172 kb
Host smart-164bf294-4b60-41a2-ba93-eca520674af6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524148741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.524148741
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1694176394
Short name T1019
Test name
Test status
Simulation time 36362674 ps
CPU time 0.8 seconds
Started Jun 29 05:30:37 PM PDT 24
Finished Jun 29 05:30:40 PM PDT 24
Peak memory 206840 kb
Host smart-925a76e4-e1a6-478e-9c50-f82b15b67fc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694176394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1694176394
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3902271072
Short name T1030
Test name
Test status
Simulation time 10522495 ps
CPU time 0.87 seconds
Started Jun 29 05:30:24 PM PDT 24
Finished Jun 29 05:30:25 PM PDT 24
Peak memory 206652 kb
Host smart-8f64df3f-d3b4-47af-8c9b-9073e69f7bb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902271072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3902271072
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3969152089
Short name T1083
Test name
Test status
Simulation time 19016215 ps
CPU time 0.85 seconds
Started Jun 29 05:30:38 PM PDT 24
Finished Jun 29 05:30:40 PM PDT 24
Peak memory 206640 kb
Host smart-73a76d42-7234-4d40-b0bc-51e40ec296f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969152089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3969152089
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1867487994
Short name T1011
Test name
Test status
Simulation time 47150528 ps
CPU time 0.87 seconds
Started Jun 29 05:30:24 PM PDT 24
Finished Jun 29 05:30:26 PM PDT 24
Peak memory 206856 kb
Host smart-a91c3cec-9e36-4c09-83b6-333e877e7f7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867487994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1867487994
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.4121504499
Short name T1069
Test name
Test status
Simulation time 87322876 ps
CPU time 0.78 seconds
Started Jun 29 05:30:25 PM PDT 24
Finished Jun 29 05:30:27 PM PDT 24
Peak memory 206688 kb
Host smart-35adff9a-aa64-4d3f-89e4-70fdef17f5e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121504499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.4121504499
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3707067967
Short name T1113
Test name
Test status
Simulation time 32722818 ps
CPU time 0.84 seconds
Started Jun 29 05:30:38 PM PDT 24
Finished Jun 29 05:30:40 PM PDT 24
Peak memory 206656 kb
Host smart-6ee4aceb-6f69-4402-9d9e-fabecf5d663c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707067967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3707067967
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2177931620
Short name T1119
Test name
Test status
Simulation time 35686301 ps
CPU time 0.79 seconds
Started Jun 29 05:30:37 PM PDT 24
Finished Jun 29 05:30:40 PM PDT 24
Peak memory 206660 kb
Host smart-29440d5d-c116-4486-8dc9-b38a6e77e997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177931620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2177931620
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2380908545
Short name T1010
Test name
Test status
Simulation time 10947392 ps
CPU time 0.88 seconds
Started Jun 29 05:30:29 PM PDT 24
Finished Jun 29 05:30:30 PM PDT 24
Peak memory 206864 kb
Host smart-a5e1f3ea-ffe0-4518-bf05-3812748ee754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380908545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2380908545
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.341258156
Short name T1112
Test name
Test status
Simulation time 13681840 ps
CPU time 0.89 seconds
Started Jun 29 05:30:24 PM PDT 24
Finished Jun 29 05:30:26 PM PDT 24
Peak memory 206844 kb
Host smart-a396c0b1-a611-4141-87e6-f8ca791c2e98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341258156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.341258156
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.703817871
Short name T1015
Test name
Test status
Simulation time 46864446 ps
CPU time 0.86 seconds
Started Jun 29 05:30:27 PM PDT 24
Finished Jun 29 05:30:29 PM PDT 24
Peak memory 206864 kb
Host smart-dbd39054-89ce-4b34-862d-2a004f0ec056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703817871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.703817871
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2338754845
Short name T271
Test name
Test status
Simulation time 79702157 ps
CPU time 1.15 seconds
Started Jun 29 05:30:04 PM PDT 24
Finished Jun 29 05:30:06 PM PDT 24
Peak memory 206956 kb
Host smart-ab1b6089-026a-4d1c-92fc-17f39764313b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338754845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2338754845
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.833423330
Short name T1024
Test name
Test status
Simulation time 95705380 ps
CPU time 3.16 seconds
Started Jun 29 05:30:08 PM PDT 24
Finished Jun 29 05:30:12 PM PDT 24
Peak memory 206964 kb
Host smart-abb84b83-91ac-416a-9c32-b109fc2872d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833423330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.833423330
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2726416048
Short name T1111
Test name
Test status
Simulation time 36577684 ps
CPU time 0.85 seconds
Started Jun 29 05:30:05 PM PDT 24
Finished Jun 29 05:30:06 PM PDT 24
Peak memory 206744 kb
Host smart-0e948ba8-9722-4d78-b032-432334c613a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726416048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2726416048
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3919076023
Short name T1005
Test name
Test status
Simulation time 212910629 ps
CPU time 1.42 seconds
Started Jun 29 05:30:03 PM PDT 24
Finished Jun 29 05:30:06 PM PDT 24
Peak memory 215180 kb
Host smart-3fa278bc-d573-4ac5-ac6c-0f5fc4724745
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919076023 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3919076023
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.4198611230
Short name T1101
Test name
Test status
Simulation time 12009462 ps
CPU time 0.91 seconds
Started Jun 29 05:30:01 PM PDT 24
Finished Jun 29 05:30:03 PM PDT 24
Peak memory 206916 kb
Host smart-7974790b-cefb-4e58-b487-bff3f371a8ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198611230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.4198611230
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3514451960
Short name T1094
Test name
Test status
Simulation time 44473612 ps
CPU time 0.92 seconds
Started Jun 29 05:30:01 PM PDT 24
Finished Jun 29 05:30:04 PM PDT 24
Peak memory 206800 kb
Host smart-5ae4891b-112f-479c-9226-c7be6abea87d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514451960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3514451960
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1279131846
Short name T1077
Test name
Test status
Simulation time 16831006 ps
CPU time 1.19 seconds
Started Jun 29 05:30:01 PM PDT 24
Finished Jun 29 05:30:04 PM PDT 24
Peak memory 207064 kb
Host smart-868a53b8-cd5e-4a00-8e3f-e349737a11c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279131846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1279131846
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3374592706
Short name T1035
Test name
Test status
Simulation time 42955318 ps
CPU time 1.88 seconds
Started Jun 29 05:30:00 PM PDT 24
Finished Jun 29 05:30:02 PM PDT 24
Peak memory 218816 kb
Host smart-0c4a95f8-3b61-44f2-b5b6-dcba7fe16dcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374592706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3374592706
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.347818379
Short name T1052
Test name
Test status
Simulation time 103444956 ps
CPU time 1.74 seconds
Started Jun 29 05:30:01 PM PDT 24
Finished Jun 29 05:30:04 PM PDT 24
Peak memory 206984 kb
Host smart-6e823dc0-a4dd-4a91-ae46-8b043980a772
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347818379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.347818379
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2764378749
Short name T1086
Test name
Test status
Simulation time 15912784 ps
CPU time 0.92 seconds
Started Jun 29 05:30:26 PM PDT 24
Finished Jun 29 05:30:28 PM PDT 24
Peak memory 206864 kb
Host smart-f2a54e10-75a7-4b82-b096-6ccd178ae77d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764378749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2764378749
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3851177692
Short name T1061
Test name
Test status
Simulation time 13062846 ps
CPU time 0.89 seconds
Started Jun 29 05:30:28 PM PDT 24
Finished Jun 29 05:30:30 PM PDT 24
Peak memory 207004 kb
Host smart-0a415249-8017-4ee7-ae96-f0cdf610a1bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851177692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3851177692
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1866726658
Short name T1057
Test name
Test status
Simulation time 23203802 ps
CPU time 0.92 seconds
Started Jun 29 05:30:26 PM PDT 24
Finished Jun 29 05:30:27 PM PDT 24
Peak memory 206852 kb
Host smart-7f5cfd00-d4ff-4ee3-ad41-2285979fd489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866726658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1866726658
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3543073751
Short name T1082
Test name
Test status
Simulation time 17092754 ps
CPU time 0.98 seconds
Started Jun 29 05:30:29 PM PDT 24
Finished Jun 29 05:30:30 PM PDT 24
Peak memory 206864 kb
Host smart-6570cea8-9f3d-4a66-8f15-d9885c73d7a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543073751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3543073751
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2897462690
Short name T1026
Test name
Test status
Simulation time 84646170 ps
CPU time 0.96 seconds
Started Jun 29 05:30:28 PM PDT 24
Finished Jun 29 05:30:30 PM PDT 24
Peak memory 206864 kb
Host smart-c7ed2f66-4938-417a-90ce-7501bf2016d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897462690 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2897462690
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1047623140
Short name T1117
Test name
Test status
Simulation time 30327494 ps
CPU time 0.82 seconds
Started Jun 29 05:30:25 PM PDT 24
Finished Jun 29 05:30:26 PM PDT 24
Peak memory 206608 kb
Host smart-492b8323-c9fb-4a88-94a2-6f0bccb4e52c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047623140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1047623140
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3451179720
Short name T1001
Test name
Test status
Simulation time 13478370 ps
CPU time 0.89 seconds
Started Jun 29 05:30:27 PM PDT 24
Finished Jun 29 05:30:29 PM PDT 24
Peak memory 207088 kb
Host smart-0a7bdbc6-51e6-4aaa-a62d-beb2c98f1f03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451179720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3451179720
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1049660782
Short name T1014
Test name
Test status
Simulation time 14645339 ps
CPU time 0.87 seconds
Started Jun 29 05:30:37 PM PDT 24
Finished Jun 29 05:30:39 PM PDT 24
Peak memory 206836 kb
Host smart-01666ad8-4d8e-4502-964e-4e83b830315e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049660782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1049660782
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.697124396
Short name T1070
Test name
Test status
Simulation time 17100430 ps
CPU time 1 seconds
Started Jun 29 05:30:36 PM PDT 24
Finished Jun 29 05:30:39 PM PDT 24
Peak memory 206780 kb
Host smart-726c776d-f1a7-43a2-bf41-5a45040064ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697124396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.697124396
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1589284405
Short name T1065
Test name
Test status
Simulation time 16592464 ps
CPU time 0.93 seconds
Started Jun 29 05:30:33 PM PDT 24
Finished Jun 29 05:30:36 PM PDT 24
Peak memory 206864 kb
Host smart-e171d42d-d6c6-4195-ac1f-7bd305db0303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589284405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1589284405
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.956946313
Short name T1020
Test name
Test status
Simulation time 95735306 ps
CPU time 1.25 seconds
Started Jun 29 05:30:01 PM PDT 24
Finished Jun 29 05:30:04 PM PDT 24
Peak memory 206988 kb
Host smart-e3079032-4702-4b14-b1d6-4e6674d64956
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956946313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.956946313
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2006025726
Short name T1099
Test name
Test status
Simulation time 36898407 ps
CPU time 2.12 seconds
Started Jun 29 05:30:02 PM PDT 24
Finished Jun 29 05:30:06 PM PDT 24
Peak memory 207004 kb
Host smart-241444eb-4cdf-4078-b723-9bce225258e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006025726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2006025726
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1853220262
Short name T273
Test name
Test status
Simulation time 17915044 ps
CPU time 1.01 seconds
Started Jun 29 05:30:02 PM PDT 24
Finished Jun 29 05:30:05 PM PDT 24
Peak memory 206920 kb
Host smart-0991719d-daf2-4309-a082-75ed461ba6bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853220262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1853220262
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2097976102
Short name T1067
Test name
Test status
Simulation time 19865859 ps
CPU time 1.13 seconds
Started Jun 29 05:30:08 PM PDT 24
Finished Jun 29 05:30:10 PM PDT 24
Peak memory 215140 kb
Host smart-4240cda0-3932-432a-a154-5b421506e5ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097976102 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2097976102
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.262633700
Short name T277
Test name
Test status
Simulation time 54209682 ps
CPU time 0.89 seconds
Started Jun 29 05:29:57 PM PDT 24
Finished Jun 29 05:29:59 PM PDT 24
Peak memory 206912 kb
Host smart-0894397a-817f-4c9a-bcac-db2de1757839
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262633700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.262633700
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1946582609
Short name T1080
Test name
Test status
Simulation time 13507435 ps
CPU time 0.9 seconds
Started Jun 29 05:30:04 PM PDT 24
Finished Jun 29 05:30:06 PM PDT 24
Peak memory 206860 kb
Host smart-26eb60a1-228e-463c-beb8-644717c9d0cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946582609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1946582609
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4244786953
Short name T1084
Test name
Test status
Simulation time 127152766 ps
CPU time 1.51 seconds
Started Jun 29 05:30:04 PM PDT 24
Finished Jun 29 05:30:06 PM PDT 24
Peak memory 206920 kb
Host smart-c659a1ed-4c9b-48ae-9e02-3c96063ec7c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244786953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.4244786953
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.454924081
Short name T1091
Test name
Test status
Simulation time 88204717 ps
CPU time 3.26 seconds
Started Jun 29 05:30:03 PM PDT 24
Finished Jun 29 05:30:08 PM PDT 24
Peak memory 215180 kb
Host smart-772ae3e9-bb78-4fdb-9da2-c4d370b954ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454924081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.454924081
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.235784129
Short name T304
Test name
Test status
Simulation time 71747705 ps
CPU time 2.25 seconds
Started Jun 29 05:30:03 PM PDT 24
Finished Jun 29 05:30:07 PM PDT 24
Peak memory 207016 kb
Host smart-19af6cd3-e34e-4bfc-8526-6cd7853a04d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235784129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.235784129
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2860132163
Short name T1115
Test name
Test status
Simulation time 39154614 ps
CPU time 0.79 seconds
Started Jun 29 05:30:32 PM PDT 24
Finished Jun 29 05:30:34 PM PDT 24
Peak memory 206676 kb
Host smart-c11a4db1-198f-4f61-ab3f-e478e8449177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860132163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2860132163
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2007938230
Short name T1013
Test name
Test status
Simulation time 11757131 ps
CPU time 0.85 seconds
Started Jun 29 05:30:33 PM PDT 24
Finished Jun 29 05:30:34 PM PDT 24
Peak memory 206864 kb
Host smart-d34bc710-75d4-4430-966d-316b7be535ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007938230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2007938230
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.665751234
Short name T1130
Test name
Test status
Simulation time 23313380 ps
CPU time 0.92 seconds
Started Jun 29 05:30:31 PM PDT 24
Finished Jun 29 05:30:33 PM PDT 24
Peak memory 206860 kb
Host smart-2a6e16ac-45e5-480e-85b4-ab332e913e7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665751234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.665751234
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1222136442
Short name T1016
Test name
Test status
Simulation time 31753303 ps
CPU time 0.86 seconds
Started Jun 29 05:30:32 PM PDT 24
Finished Jun 29 05:30:33 PM PDT 24
Peak memory 206688 kb
Host smart-8305b8a0-3095-4c04-9a04-2982f5d8c12c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222136442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1222136442
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.846856385
Short name T1004
Test name
Test status
Simulation time 29557266 ps
CPU time 0.88 seconds
Started Jun 29 05:30:36 PM PDT 24
Finished Jun 29 05:30:39 PM PDT 24
Peak memory 206776 kb
Host smart-c412b037-e88c-43af-9b3b-2e91d46c1544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846856385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.846856385
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2693559163
Short name T1034
Test name
Test status
Simulation time 14422073 ps
CPU time 0.93 seconds
Started Jun 29 05:30:36 PM PDT 24
Finished Jun 29 05:30:39 PM PDT 24
Peak memory 206864 kb
Host smart-83b42ae6-3938-4285-aa29-dade4451237b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693559163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2693559163
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3568656160
Short name T999
Test name
Test status
Simulation time 13065828 ps
CPU time 0.87 seconds
Started Jun 29 05:30:34 PM PDT 24
Finished Jun 29 05:30:36 PM PDT 24
Peak memory 206864 kb
Host smart-726e0e1b-abfa-4dca-9e8f-3627b7f3e0b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568656160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3568656160
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2177735414
Short name T1054
Test name
Test status
Simulation time 12914398 ps
CPU time 0.86 seconds
Started Jun 29 05:30:40 PM PDT 24
Finished Jun 29 05:30:41 PM PDT 24
Peak memory 206784 kb
Host smart-8d6620a6-b1d2-46bd-8d80-d85a1ac0fb5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177735414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2177735414
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3458728360
Short name T1122
Test name
Test status
Simulation time 12431435 ps
CPU time 0.88 seconds
Started Jun 29 05:30:33 PM PDT 24
Finished Jun 29 05:30:35 PM PDT 24
Peak memory 206756 kb
Host smart-9d25f96a-a344-4e0e-9fd2-31505394ac66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458728360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3458728360
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1297860334
Short name T1107
Test name
Test status
Simulation time 19686616 ps
CPU time 0.8 seconds
Started Jun 29 05:30:34 PM PDT 24
Finished Jun 29 05:30:36 PM PDT 24
Peak memory 206632 kb
Host smart-94d1d52d-d2c6-4e80-ac01-062fb57c5c7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297860334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1297860334
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2012006812
Short name T1022
Test name
Test status
Simulation time 25069060 ps
CPU time 1.58 seconds
Started Jun 29 05:30:01 PM PDT 24
Finished Jun 29 05:30:04 PM PDT 24
Peak memory 220020 kb
Host smart-0396f6db-ffa1-4451-b099-93d2eb89af43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012006812 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2012006812
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2768665875
Short name T1066
Test name
Test status
Simulation time 89172317 ps
CPU time 0.93 seconds
Started Jun 29 05:30:00 PM PDT 24
Finished Jun 29 05:30:03 PM PDT 24
Peak memory 206916 kb
Host smart-25edce4c-0343-4567-b9e8-687ae6901c3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768665875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2768665875
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1493115189
Short name T1104
Test name
Test status
Simulation time 15912755 ps
CPU time 0.93 seconds
Started Jun 29 05:30:08 PM PDT 24
Finished Jun 29 05:30:10 PM PDT 24
Peak memory 206824 kb
Host smart-21d188d7-e04e-4ac2-b160-86e6eadc3001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493115189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1493115189
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1504297289
Short name T283
Test name
Test status
Simulation time 35939470 ps
CPU time 1.47 seconds
Started Jun 29 05:30:01 PM PDT 24
Finished Jun 29 05:30:04 PM PDT 24
Peak memory 206924 kb
Host smart-83af1eb2-7c6a-4d41-8799-02882be8896f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504297289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1504297289
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2948467663
Short name T1093
Test name
Test status
Simulation time 226246859 ps
CPU time 2.06 seconds
Started Jun 29 05:30:08 PM PDT 24
Finished Jun 29 05:30:10 PM PDT 24
Peak memory 215168 kb
Host smart-d2d29716-8f17-47fb-b6cc-bae764084d08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948467663 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2948467663
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.96181523
Short name T1098
Test name
Test status
Simulation time 248936476 ps
CPU time 2.27 seconds
Started Jun 29 05:30:01 PM PDT 24
Finished Jun 29 05:30:05 PM PDT 24
Peak memory 207008 kb
Host smart-c44523d3-713b-43f4-b3fa-ccd89d00347e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96181523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.96181523
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1695305902
Short name T1125
Test name
Test status
Simulation time 115224066 ps
CPU time 1.78 seconds
Started Jun 29 05:30:11 PM PDT 24
Finished Jun 29 05:30:14 PM PDT 24
Peak memory 215172 kb
Host smart-24695160-b76b-4496-ab56-b7c6b53ffefd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695305902 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1695305902
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3818579378
Short name T266
Test name
Test status
Simulation time 41480450 ps
CPU time 0.89 seconds
Started Jun 29 05:30:03 PM PDT 24
Finished Jun 29 05:30:05 PM PDT 24
Peak memory 206836 kb
Host smart-6762e4aa-6d2d-49be-8c96-6b68856fa1d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818579378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3818579378
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3699559618
Short name T1006
Test name
Test status
Simulation time 72920812 ps
CPU time 0.87 seconds
Started Jun 29 05:30:01 PM PDT 24
Finished Jun 29 05:30:03 PM PDT 24
Peak memory 207004 kb
Host smart-1384f330-1a23-41ce-b6f3-8c8a10297f4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699559618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3699559618
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.205942238
Short name T1055
Test name
Test status
Simulation time 67416175 ps
CPU time 1.11 seconds
Started Jun 29 05:30:10 PM PDT 24
Finished Jun 29 05:30:12 PM PDT 24
Peak memory 206904 kb
Host smart-7ae34585-a418-4830-98d6-421daea55d63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205942238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.205942238
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1177646194
Short name T1043
Test name
Test status
Simulation time 220316767 ps
CPU time 2.56 seconds
Started Jun 29 05:30:00 PM PDT 24
Finished Jun 29 05:30:04 PM PDT 24
Peak memory 215188 kb
Host smart-afe8a5b5-4cb2-45cd-82fd-eb763f710aa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177646194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1177646194
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2021917600
Short name T306
Test name
Test status
Simulation time 565994806 ps
CPU time 2.29 seconds
Started Jun 29 05:29:59 PM PDT 24
Finished Jun 29 05:30:02 PM PDT 24
Peak memory 206920 kb
Host smart-735a4189-49b0-42d8-bbe4-00f33e55dabe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021917600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2021917600
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3087178395
Short name T1116
Test name
Test status
Simulation time 155660880 ps
CPU time 1.58 seconds
Started Jun 29 05:30:11 PM PDT 24
Finished Jun 29 05:30:14 PM PDT 24
Peak memory 215176 kb
Host smart-f60fc2d0-97e9-4363-9119-7bfe8f6ffccf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087178395 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3087178395
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.127629469
Short name T1049
Test name
Test status
Simulation time 48761049 ps
CPU time 0.86 seconds
Started Jun 29 05:30:10 PM PDT 24
Finished Jun 29 05:30:12 PM PDT 24
Peak memory 206748 kb
Host smart-03c72a90-dc96-4e03-bb6d-23f09a59c3c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127629469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.127629469
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.419131677
Short name T1021
Test name
Test status
Simulation time 63734589 ps
CPU time 0.91 seconds
Started Jun 29 05:30:10 PM PDT 24
Finished Jun 29 05:30:12 PM PDT 24
Peak memory 206772 kb
Host smart-a2fb7811-884c-4388-b43a-c1c4ff6fb273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419131677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.419131677
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.48129222
Short name T1072
Test name
Test status
Simulation time 17455533 ps
CPU time 1.25 seconds
Started Jun 29 05:30:09 PM PDT 24
Finished Jun 29 05:30:11 PM PDT 24
Peak memory 206920 kb
Host smart-15a2c514-6fa4-437d-ae32-e097d98287bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48129222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outs
tanding.48129222
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1833055073
Short name T1056
Test name
Test status
Simulation time 872190813 ps
CPU time 3.44 seconds
Started Jun 29 05:30:11 PM PDT 24
Finished Jun 29 05:30:16 PM PDT 24
Peak memory 215188 kb
Host smart-cd40b690-a144-4e1c-a585-f4dc2ca86f3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833055073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1833055073
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2431837835
Short name T1124
Test name
Test status
Simulation time 102707338 ps
CPU time 1.6 seconds
Started Jun 29 05:30:11 PM PDT 24
Finished Jun 29 05:30:14 PM PDT 24
Peak memory 206996 kb
Host smart-a03ebed4-914b-412f-ad48-0b6743dac8fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431837835 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2431837835
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1085780725
Short name T1023
Test name
Test status
Simulation time 55912728 ps
CPU time 1.18 seconds
Started Jun 29 05:30:10 PM PDT 24
Finished Jun 29 05:30:12 PM PDT 24
Peak memory 217020 kb
Host smart-8132f68e-e59a-40d1-8a00-83ce26b22c66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085780725 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1085780725
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1583563682
Short name T1103
Test name
Test status
Simulation time 16298475 ps
CPU time 1.04 seconds
Started Jun 29 05:30:09 PM PDT 24
Finished Jun 29 05:30:10 PM PDT 24
Peak memory 206876 kb
Host smart-4e000748-234b-4328-8442-3c2dc4cf56b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583563682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1583563682
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2508326664
Short name T1110
Test name
Test status
Simulation time 35548004 ps
CPU time 0.79 seconds
Started Jun 29 05:30:10 PM PDT 24
Finished Jun 29 05:30:12 PM PDT 24
Peak memory 206676 kb
Host smart-055ed76f-dc3d-481a-8dc6-2b441fb22430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508326664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2508326664
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.711255333
Short name T1108
Test name
Test status
Simulation time 45601668 ps
CPU time 1.12 seconds
Started Jun 29 05:30:11 PM PDT 24
Finished Jun 29 05:30:13 PM PDT 24
Peak memory 206996 kb
Host smart-e66109b0-c802-409e-9f79-63a64bbfb965
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711255333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_out
standing.711255333
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.306862541
Short name T1095
Test name
Test status
Simulation time 723567710 ps
CPU time 3.44 seconds
Started Jun 29 05:30:09 PM PDT 24
Finished Jun 29 05:30:14 PM PDT 24
Peak memory 215180 kb
Host smart-d4197c21-4293-4cde-b127-1b4d058686f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306862541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.306862541
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1594206931
Short name T1046
Test name
Test status
Simulation time 46949854 ps
CPU time 1.62 seconds
Started Jun 29 05:30:10 PM PDT 24
Finished Jun 29 05:30:13 PM PDT 24
Peak memory 206920 kb
Host smart-088e56b6-a991-406a-affe-f6a9c00ab007
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594206931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1594206931
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2243120238
Short name T1031
Test name
Test status
Simulation time 28495755 ps
CPU time 1.08 seconds
Started Jun 29 05:30:11 PM PDT 24
Finished Jun 29 05:30:13 PM PDT 24
Peak memory 216644 kb
Host smart-433fe251-e435-417a-8c8a-0dae1d0ae1cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243120238 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2243120238
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1703070771
Short name T267
Test name
Test status
Simulation time 18631885 ps
CPU time 0.86 seconds
Started Jun 29 05:30:10 PM PDT 24
Finished Jun 29 05:30:13 PM PDT 24
Peak memory 206728 kb
Host smart-249968f3-632d-4f0d-8e05-8e3ba59cd132
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703070771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1703070771
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1733886234
Short name T997
Test name
Test status
Simulation time 43969234 ps
CPU time 0.91 seconds
Started Jun 29 05:30:11 PM PDT 24
Finished Jun 29 05:30:13 PM PDT 24
Peak memory 206864 kb
Host smart-05e11bee-4652-4a86-a7af-2847cb914d0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733886234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1733886234
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.441135912
Short name T284
Test name
Test status
Simulation time 35389446 ps
CPU time 1.23 seconds
Started Jun 29 05:30:08 PM PDT 24
Finished Jun 29 05:30:10 PM PDT 24
Peak memory 206880 kb
Host smart-be247231-63ee-4146-9edb-c30abe0e91cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441135912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.441135912
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.4076056324
Short name T1033
Test name
Test status
Simulation time 96446870 ps
CPU time 2.01 seconds
Started Jun 29 05:30:09 PM PDT 24
Finished Jun 29 05:30:11 PM PDT 24
Peak memory 215168 kb
Host smart-0b4ffcd4-4954-4d1a-b3cd-ee7b339d9bd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076056324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.4076056324
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.978220979
Short name T305
Test name
Test status
Simulation time 550017882 ps
CPU time 2.25 seconds
Started Jun 29 05:30:10 PM PDT 24
Finished Jun 29 05:30:14 PM PDT 24
Peak memory 215136 kb
Host smart-a97acd56-287d-47df-93af-053f0f8c14c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978220979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.978220979
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.672487225
Short name T307
Test name
Test status
Simulation time 38816960 ps
CPU time 1.13 seconds
Started Jun 29 05:31:42 PM PDT 24
Finished Jun 29 05:31:43 PM PDT 24
Peak memory 219008 kb
Host smart-cf77d92a-1448-4501-a142-37472cd2caa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672487225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.672487225
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable.2480940425
Short name T793
Test name
Test status
Simulation time 14097599 ps
CPU time 0.91 seconds
Started Jun 29 05:31:37 PM PDT 24
Finished Jun 29 05:31:38 PM PDT 24
Peak memory 216340 kb
Host smart-e680104b-e912-41e3-8c81-514738727489
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480940425 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2480940425
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.1056179758
Short name T208
Test name
Test status
Simulation time 44494422 ps
CPU time 1.12 seconds
Started Jun 29 05:31:38 PM PDT 24
Finished Jun 29 05:31:39 PM PDT 24
Peak memory 220060 kb
Host smart-b3922bae-6462-4199-9aab-a037828aed50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056179758 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1056179758
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2900445275
Short name T983
Test name
Test status
Simulation time 65346352 ps
CPU time 1.35 seconds
Started Jun 29 05:31:32 PM PDT 24
Finished Jun 29 05:31:34 PM PDT 24
Peak memory 215616 kb
Host smart-f2d0f57c-68ff-460f-8dfe-d4c28c37436a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900445275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2900445275
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2602328773
Short name T64
Test name
Test status
Simulation time 1753574981 ps
CPU time 7.28 seconds
Started Jun 29 05:31:45 PM PDT 24
Finished Jun 29 05:31:53 PM PDT 24
Peak memory 236664 kb
Host smart-ed4d8f5e-2776-4cd6-9c1c-21785e1f23de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602328773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2602328773
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.552389893
Short name T658
Test name
Test status
Simulation time 86155445 ps
CPU time 1.01 seconds
Started Jun 29 05:31:49 PM PDT 24
Finished Jun 29 05:31:51 PM PDT 24
Peak memory 215608 kb
Host smart-f70728c7-6265-4066-a554-167ae47f20af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552389893 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.552389893
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3862642341
Short name T440
Test name
Test status
Simulation time 2640484265 ps
CPU time 4.39 seconds
Started Jun 29 05:31:35 PM PDT 24
Finished Jun 29 05:31:40 PM PDT 24
Peak memory 217668 kb
Host smart-01b7735c-8b59-42c8-9c67-e6502b09b1ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862642341 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3862642341
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.321616057
Short name T37
Test name
Test status
Simulation time 162999353366 ps
CPU time 1219.88 seconds
Started Jun 29 05:31:44 PM PDT 24
Finished Jun 29 05:52:04 PM PDT 24
Peak memory 224816 kb
Host smart-96046993-67a3-460d-ba81-d674002f8261
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321616057 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.321616057
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.4110885760
Short name T946
Test name
Test status
Simulation time 45290816 ps
CPU time 1.29 seconds
Started Jun 29 05:31:39 PM PDT 24
Finished Jun 29 05:31:41 PM PDT 24
Peak memory 219716 kb
Host smart-0a0109c3-dac6-406e-a494-e100ef846f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110885760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.4110885760
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.3822789991
Short name T907
Test name
Test status
Simulation time 29328906 ps
CPU time 0.94 seconds
Started Jun 29 05:31:45 PM PDT 24
Finished Jun 29 05:31:47 PM PDT 24
Peak memory 215156 kb
Host smart-7965f647-07fc-45f8-8519-25a9e4263bc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822789991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3822789991
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_err.1420046317
Short name T145
Test name
Test status
Simulation time 20607330 ps
CPU time 1.28 seconds
Started Jun 29 05:31:39 PM PDT 24
Finished Jun 29 05:31:41 PM PDT 24
Peak memory 229976 kb
Host smart-d2fe2545-6580-4b20-9dca-a0c954145964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420046317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1420046317
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2808859502
Short name T538
Test name
Test status
Simulation time 46878301 ps
CPU time 1.62 seconds
Started Jun 29 05:31:40 PM PDT 24
Finished Jun 29 05:31:42 PM PDT 24
Peak memory 218852 kb
Host smart-f3397a8b-c489-42db-898c-94a0a9f3e471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808859502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2808859502
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.1261694531
Short name T25
Test name
Test status
Simulation time 67184410 ps
CPU time 0.94 seconds
Started Jun 29 05:31:42 PM PDT 24
Finished Jun 29 05:31:43 PM PDT 24
Peak memory 207408 kb
Host smart-dccc52b2-ad4d-4b5e-bab0-37921ce72387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261694531 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1261694531
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1861494518
Short name T18
Test name
Test status
Simulation time 960657920 ps
CPU time 5.27 seconds
Started Jun 29 05:31:43 PM PDT 24
Finished Jun 29 05:31:49 PM PDT 24
Peak memory 237648 kb
Host smart-fed8145a-68ef-4187-97af-e59181ef57e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861494518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1861494518
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2383067832
Short name T967
Test name
Test status
Simulation time 90833122 ps
CPU time 0.93 seconds
Started Jun 29 05:31:46 PM PDT 24
Finished Jun 29 05:31:48 PM PDT 24
Peak memory 215552 kb
Host smart-b8064c23-e085-4f7d-b217-349fde226710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383067832 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2383067832
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.277594700
Short name T704
Test name
Test status
Simulation time 377566389 ps
CPU time 7.56 seconds
Started Jun 29 05:31:37 PM PDT 24
Finished Jun 29 05:31:45 PM PDT 24
Peak memory 218792 kb
Host smart-6932baec-f654-4ea7-8512-28cd75bc044a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277594700 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.277594700
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1022837653
Short name T829
Test name
Test status
Simulation time 52674752045 ps
CPU time 538.05 seconds
Started Jun 29 05:31:42 PM PDT 24
Finished Jun 29 05:40:41 PM PDT 24
Peak memory 224032 kb
Host smart-07f34b0b-4e04-41d6-9c3f-a357782b1743
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022837653 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1022837653
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.289881607
Short name T109
Test name
Test status
Simulation time 35584371 ps
CPU time 1.27 seconds
Started Jun 29 05:31:57 PM PDT 24
Finished Jun 29 05:31:59 PM PDT 24
Peak memory 220744 kb
Host smart-a5a2be7c-8749-4781-8a16-3c4771b9a712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289881607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.289881607
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.4203965885
Short name T586
Test name
Test status
Simulation time 30777870 ps
CPU time 0.98 seconds
Started Jun 29 05:31:53 PM PDT 24
Finished Jun 29 05:31:55 PM PDT 24
Peak memory 206936 kb
Host smart-52ed2aec-cda7-424a-add6-80f7be5523cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203965885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.4203965885
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.2833370715
Short name T589
Test name
Test status
Simulation time 27748018 ps
CPU time 0.88 seconds
Started Jun 29 05:31:57 PM PDT 24
Finished Jun 29 05:31:59 PM PDT 24
Peak memory 215728 kb
Host smart-30af1be1-068f-4dca-b26d-dacc3b1e1475
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833370715 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2833370715
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.2845124487
Short name T837
Test name
Test status
Simulation time 102900806 ps
CPU time 1.16 seconds
Started Jun 29 05:31:53 PM PDT 24
Finished Jun 29 05:31:56 PM PDT 24
Peak memory 217268 kb
Host smart-583200e8-60c3-491c-9360-26bd3579a52c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845124487 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.2845124487
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.3727649279
Short name T912
Test name
Test status
Simulation time 31078101 ps
CPU time 1.43 seconds
Started Jun 29 05:32:02 PM PDT 24
Finished Jun 29 05:32:04 PM PDT 24
Peak memory 226056 kb
Host smart-5bfe61d6-d17e-463e-9b21-7fd0c6bb8b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727649279 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3727649279
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2338002146
Short name T371
Test name
Test status
Simulation time 183749774 ps
CPU time 1.56 seconds
Started Jun 29 05:31:55 PM PDT 24
Finished Jun 29 05:31:57 PM PDT 24
Peak memory 219204 kb
Host smart-fd1aff9a-ca13-4890-9d20-fc3e7f5b4a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338002146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2338002146
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.2946919165
Short name T726
Test name
Test status
Simulation time 23514652 ps
CPU time 1.17 seconds
Started Jun 29 05:31:57 PM PDT 24
Finished Jun 29 05:31:59 PM PDT 24
Peak memory 224296 kb
Host smart-db7ed590-6508-44a3-aa56-d0282ee0de95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946919165 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2946919165
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2832062645
Short name T880
Test name
Test status
Simulation time 15165520 ps
CPU time 1.17 seconds
Started Jun 29 05:31:56 PM PDT 24
Finished Jun 29 05:31:58 PM PDT 24
Peak memory 207408 kb
Host smart-b8ec3f14-a2bc-4632-a6bb-c8783538751c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832062645 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2832062645
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1914750515
Short name T662
Test name
Test status
Simulation time 253875438 ps
CPU time 3.15 seconds
Started Jun 29 05:31:57 PM PDT 24
Finished Jun 29 05:32:01 PM PDT 24
Peak memory 215588 kb
Host smart-a35afe32-217a-43d1-b4db-2e596e256a75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914750515 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1914750515
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1193436897
Short name T481
Test name
Test status
Simulation time 74280406940 ps
CPU time 2035.77 seconds
Started Jun 29 05:31:59 PM PDT 24
Finished Jun 29 06:05:56 PM PDT 24
Peak memory 228592 kb
Host smart-a1451c75-2e14-4e1c-a98d-1cf1ed9af14e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193436897 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1193436897
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.3075690144
Short name T681
Test name
Test status
Simulation time 107755829 ps
CPU time 1.12 seconds
Started Jun 29 05:33:32 PM PDT 24
Finished Jun 29 05:33:35 PM PDT 24
Peak memory 220088 kb
Host smart-5910f250-e2ee-4884-8b88-378fe8ac70a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075690144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.3075690144
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.2992030282
Short name T434
Test name
Test status
Simulation time 91329676 ps
CPU time 1.28 seconds
Started Jun 29 05:33:44 PM PDT 24
Finished Jun 29 05:33:48 PM PDT 24
Peak memory 218940 kb
Host smart-83f6afa2-3d8f-41cc-aaeb-6c52e56eda2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992030282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2992030282
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.1674704014
Short name T498
Test name
Test status
Simulation time 40297527 ps
CPU time 1.13 seconds
Started Jun 29 05:33:27 PM PDT 24
Finished Jun 29 05:33:29 PM PDT 24
Peak memory 218676 kb
Host smart-455709d9-a313-4916-a8c1-3614d185ba03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674704014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.1674704014
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.4091400364
Short name T580
Test name
Test status
Simulation time 57787392 ps
CPU time 1.53 seconds
Started Jun 29 05:33:32 PM PDT 24
Finished Jun 29 05:33:35 PM PDT 24
Peak memory 220268 kb
Host smart-96f45f83-fba1-4015-a08d-5669b329e854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091400364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.4091400364
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.1887370291
Short name T350
Test name
Test status
Simulation time 41306983 ps
CPU time 1.42 seconds
Started Jun 29 05:33:31 PM PDT 24
Finished Jun 29 05:33:33 PM PDT 24
Peak memory 218632 kb
Host smart-af4c24c6-accd-4975-a944-be652ed60f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887370291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1887370291
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3277029956
Short name T657
Test name
Test status
Simulation time 273000766 ps
CPU time 4.03 seconds
Started Jun 29 05:33:32 PM PDT 24
Finished Jun 29 05:33:38 PM PDT 24
Peak memory 219840 kb
Host smart-9ecb4a03-b20e-4c3b-b68a-8673a555200b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277029956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3277029956
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.1219705760
Short name T511
Test name
Test status
Simulation time 71251286 ps
CPU time 1.19 seconds
Started Jun 29 05:33:43 PM PDT 24
Finished Jun 29 05:33:46 PM PDT 24
Peak memory 218844 kb
Host smart-763a3c69-b02e-4762-bc18-c1d0b2a6c8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219705760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.1219705760
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/106.edn_alert.2622504419
Short name T894
Test name
Test status
Simulation time 97626568 ps
CPU time 1.17 seconds
Started Jun 29 05:33:33 PM PDT 24
Finished Jun 29 05:33:35 PM PDT 24
Peak memory 220192 kb
Host smart-45237c23-b664-43b0-8f12-550dcc103c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622504419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2622504419
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.1755356171
Short name T489
Test name
Test status
Simulation time 35852192 ps
CPU time 1.35 seconds
Started Jun 29 05:33:27 PM PDT 24
Finished Jun 29 05:33:29 PM PDT 24
Peak memory 217772 kb
Host smart-e9af7cd7-d5dc-4694-ba5e-823bd011f1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755356171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1755356171
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.2175698994
Short name T339
Test name
Test status
Simulation time 107518592 ps
CPU time 1.18 seconds
Started Jun 29 05:33:31 PM PDT 24
Finished Jun 29 05:33:34 PM PDT 24
Peak memory 220368 kb
Host smart-ce4a8323-d0f1-4b3f-b171-feee17ec1036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175698994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2175698994
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.1655429014
Short name T216
Test name
Test status
Simulation time 27993597 ps
CPU time 1.26 seconds
Started Jun 29 05:33:30 PM PDT 24
Finished Jun 29 05:33:32 PM PDT 24
Peak memory 220264 kb
Host smart-066fe6d8-4214-43f9-a1cb-b497d9330b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655429014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.1655429014
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.1755592794
Short name T715
Test name
Test status
Simulation time 131659984 ps
CPU time 2.69 seconds
Started Jun 29 05:33:29 PM PDT 24
Finished Jun 29 05:33:33 PM PDT 24
Peak memory 218908 kb
Host smart-e5f7b40b-caff-4674-ad41-5dd11c15c74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755592794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1755592794
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.3117220563
Short name T620
Test name
Test status
Simulation time 119836966 ps
CPU time 1.17 seconds
Started Jun 29 05:33:30 PM PDT 24
Finished Jun 29 05:33:33 PM PDT 24
Peak memory 219012 kb
Host smart-944a8170-2a3e-4d72-a53f-a8d5028f2405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117220563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3117220563
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.3273583702
Short name T560
Test name
Test status
Simulation time 39851431 ps
CPU time 1.78 seconds
Started Jun 29 05:33:34 PM PDT 24
Finished Jun 29 05:33:37 PM PDT 24
Peak memory 218884 kb
Host smart-7c896699-24e5-428e-a007-357bd756fbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273583702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3273583702
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2936341871
Short name T111
Test name
Test status
Simulation time 23322251 ps
CPU time 1.22 seconds
Started Jun 29 05:32:03 PM PDT 24
Finished Jun 29 05:32:05 PM PDT 24
Peak memory 220056 kb
Host smart-7c77bc8c-c7dd-4fe5-aeb1-ff22cf810852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936341871 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2936341871
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3960060680
Short name T397
Test name
Test status
Simulation time 25290646 ps
CPU time 1.17 seconds
Started Jun 29 05:32:03 PM PDT 24
Finished Jun 29 05:32:05 PM PDT 24
Peak memory 207156 kb
Host smart-75407ad1-41d4-4199-9fe7-2fea45bf102f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960060680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3960060680
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.730170892
Short name T778
Test name
Test status
Simulation time 25095828 ps
CPU time 0.88 seconds
Started Jun 29 05:32:06 PM PDT 24
Finished Jun 29 05:32:08 PM PDT 24
Peak memory 215728 kb
Host smart-eeb437ab-359d-4318-b323-860c79e3bb33
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730170892 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.730170892
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.504458034
Short name T938
Test name
Test status
Simulation time 76481224 ps
CPU time 1.16 seconds
Started Jun 29 05:32:07 PM PDT 24
Finished Jun 29 05:32:10 PM PDT 24
Peak memory 218836 kb
Host smart-0c635596-6806-41a7-98d5-fb170d43a86d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504458034 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.504458034
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.3698708551
Short name T768
Test name
Test status
Simulation time 19591455 ps
CPU time 1.22 seconds
Started Jun 29 05:32:05 PM PDT 24
Finished Jun 29 05:32:07 PM PDT 24
Peak memory 224260 kb
Host smart-56c3e653-485b-4459-9ceb-581b9db7db5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698708551 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3698708551
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.1618941647
Short name T558
Test name
Test status
Simulation time 119219491 ps
CPU time 0.82 seconds
Started Jun 29 05:32:07 PM PDT 24
Finished Jun 29 05:32:09 PM PDT 24
Peak memory 215504 kb
Host smart-789507da-d395-4785-afb1-ee19a8ac0e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618941647 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1618941647
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3712381053
Short name T731
Test name
Test status
Simulation time 27918852 ps
CPU time 0.98 seconds
Started Jun 29 05:31:55 PM PDT 24
Finished Jun 29 05:31:57 PM PDT 24
Peak memory 215616 kb
Host smart-16006a11-5642-4db8-83dd-b7a6be9b7d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712381053 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3712381053
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.3121201444
Short name T680
Test name
Test status
Simulation time 153235011 ps
CPU time 2.16 seconds
Started Jun 29 05:32:00 PM PDT 24
Finished Jun 29 05:32:03 PM PDT 24
Peak memory 217528 kb
Host smart-18d416ed-a80a-4318-96a1-f5d3d60d9f19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121201444 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3121201444
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1687266864
Short name T229
Test name
Test status
Simulation time 71401775969 ps
CPU time 873.04 seconds
Started Jun 29 05:32:05 PM PDT 24
Finished Jun 29 05:46:39 PM PDT 24
Peak memory 220792 kb
Host smart-1068ef3c-062e-4aa9-8667-7ae03f40c8be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687266864 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1687266864
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.2509129319
Short name T783
Test name
Test status
Simulation time 25927619 ps
CPU time 1.23 seconds
Started Jun 29 05:33:31 PM PDT 24
Finished Jun 29 05:33:33 PM PDT 24
Peak memory 218804 kb
Host smart-0e91ff41-4518-406b-b951-12a07457fecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509129319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.2509129319
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/111.edn_alert.1891425575
Short name T708
Test name
Test status
Simulation time 38854147 ps
CPU time 1.15 seconds
Started Jun 29 05:33:30 PM PDT 24
Finished Jun 29 05:33:32 PM PDT 24
Peak memory 220156 kb
Host smart-fef1e9b6-3171-40cb-96fd-33baba06284c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891425575 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.1891425575
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.463145994
Short name T246
Test name
Test status
Simulation time 33504631 ps
CPU time 1.57 seconds
Started Jun 29 05:33:32 PM PDT 24
Finished Jun 29 05:33:36 PM PDT 24
Peak memory 218012 kb
Host smart-cf63a322-eb4b-4bac-9c93-33f7e8398af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463145994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.463145994
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.2637538825
Short name T86
Test name
Test status
Simulation time 37676773 ps
CPU time 1.23 seconds
Started Jun 29 05:33:30 PM PDT 24
Finished Jun 29 05:33:32 PM PDT 24
Peak memory 219876 kb
Host smart-26c6bf8f-e835-4dd6-888d-47719bb3cc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637538825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.2637538825
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.3065202394
Short name T864
Test name
Test status
Simulation time 42420083 ps
CPU time 1.21 seconds
Started Jun 29 05:33:33 PM PDT 24
Finished Jun 29 05:33:35 PM PDT 24
Peak memory 220452 kb
Host smart-e7961f31-ff03-45af-becd-3ad7a4b450b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065202394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3065202394
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.2021053775
Short name T21
Test name
Test status
Simulation time 217385827 ps
CPU time 2.45 seconds
Started Jun 29 05:33:32 PM PDT 24
Finished Jun 29 05:33:36 PM PDT 24
Peak memory 219636 kb
Host smart-57700e7b-67e3-49e6-986b-74fcd7f3c0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021053775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2021053775
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.3812076047
Short name T913
Test name
Test status
Simulation time 32088794 ps
CPU time 1.3 seconds
Started Jun 29 05:33:22 PM PDT 24
Finished Jun 29 05:33:24 PM PDT 24
Peak memory 216000 kb
Host smart-e329f8c9-67ef-478e-844f-92314d092947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812076047 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3812076047
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.3900388496
Short name T867
Test name
Test status
Simulation time 52782391 ps
CPU time 1.45 seconds
Started Jun 29 05:33:30 PM PDT 24
Finished Jun 29 05:33:33 PM PDT 24
Peak memory 219016 kb
Host smart-cd7694d1-5179-4efa-9716-c8c832cf3d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900388496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3900388496
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.1598711202
Short name T854
Test name
Test status
Simulation time 43396282 ps
CPU time 1.16 seconds
Started Jun 29 05:33:32 PM PDT 24
Finished Jun 29 05:33:35 PM PDT 24
Peak memory 220132 kb
Host smart-f272317c-27ff-4229-af36-26968f8bb026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598711202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.1598711202
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/117.edn_alert.3019545343
Short name T308
Test name
Test status
Simulation time 81166609 ps
CPU time 1.14 seconds
Started Jun 29 05:33:30 PM PDT 24
Finished Jun 29 05:33:32 PM PDT 24
Peak memory 219636 kb
Host smart-960251af-3827-4e76-b404-fdbf44ca3659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019545343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.3019545343
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.199352952
Short name T619
Test name
Test status
Simulation time 178484498 ps
CPU time 2.85 seconds
Started Jun 29 05:33:44 PM PDT 24
Finished Jun 29 05:33:48 PM PDT 24
Peak memory 217692 kb
Host smart-b9fdbdb8-e0b6-4b4e-a24a-b91513c1d804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199352952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.199352952
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.1858525422
Short name T402
Test name
Test status
Simulation time 24727900 ps
CPU time 1.22 seconds
Started Jun 29 05:33:32 PM PDT 24
Finished Jun 29 05:33:35 PM PDT 24
Peak memory 219912 kb
Host smart-5c1ed3c5-a37b-4e0a-acc5-e237bd7b54c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858525422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1858525422
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.3234151685
Short name T600
Test name
Test status
Simulation time 89941268 ps
CPU time 1.25 seconds
Started Jun 29 05:33:29 PM PDT 24
Finished Jun 29 05:33:31 PM PDT 24
Peak memory 215600 kb
Host smart-1a162f43-62e9-439f-acb3-031d97f89902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234151685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3234151685
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.133408262
Short name T377
Test name
Test status
Simulation time 36962231 ps
CPU time 1.23 seconds
Started Jun 29 05:33:28 PM PDT 24
Finished Jun 29 05:33:30 PM PDT 24
Peak memory 218700 kb
Host smart-68613e32-a537-4623-965d-a3dda62dc665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133408262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.133408262
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2539015955
Short name T663
Test name
Test status
Simulation time 433325014 ps
CPU time 1.47 seconds
Started Jun 29 05:32:02 PM PDT 24
Finished Jun 29 05:32:04 PM PDT 24
Peak memory 218696 kb
Host smart-e5d59162-a712-4db7-a0ff-6ce592b2018a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539015955 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2539015955
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2415053859
Short name T390
Test name
Test status
Simulation time 42641598 ps
CPU time 0.86 seconds
Started Jun 29 05:32:06 PM PDT 24
Finished Jun 29 05:32:08 PM PDT 24
Peak memory 206976 kb
Host smart-63cf68c8-f693-471c-be12-16791b7171dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415053859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2415053859
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_err.3191705309
Short name T163
Test name
Test status
Simulation time 19768070 ps
CPU time 1.1 seconds
Started Jun 29 05:32:03 PM PDT 24
Finished Jun 29 05:32:04 PM PDT 24
Peak memory 218832 kb
Host smart-b07dd742-840c-4ed3-8771-c69e06538390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191705309 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3191705309
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3411501596
Short name T720
Test name
Test status
Simulation time 45155187 ps
CPU time 1.88 seconds
Started Jun 29 05:32:05 PM PDT 24
Finished Jun 29 05:32:07 PM PDT 24
Peak memory 217704 kb
Host smart-279a4fed-24c1-4e3a-825d-58c414267c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411501596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3411501596
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.1308177845
Short name T764
Test name
Test status
Simulation time 32145303 ps
CPU time 1 seconds
Started Jun 29 05:32:00 PM PDT 24
Finished Jun 29 05:32:01 PM PDT 24
Peak memory 215504 kb
Host smart-ec6458e6-a85d-44f3-9eb7-51e07d7bad16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308177845 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1308177845
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1883781770
Short name T474
Test name
Test status
Simulation time 756830904 ps
CPU time 2.44 seconds
Started Jun 29 05:32:03 PM PDT 24
Finished Jun 29 05:32:07 PM PDT 24
Peak memory 215688 kb
Host smart-623b56fc-e450-473f-86fe-362ef44825ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883781770 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1883781770
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3027734069
Short name T804
Test name
Test status
Simulation time 1834117939784 ps
CPU time 3514.06 seconds
Started Jun 29 05:32:01 PM PDT 24
Finished Jun 29 06:30:37 PM PDT 24
Peak memory 230088 kb
Host smart-adad16cd-abc1-4b4e-8b35-38c502ddd5f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027734069 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3027734069
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.2109790431
Short name T865
Test name
Test status
Simulation time 35007515 ps
CPU time 1.09 seconds
Started Jun 29 05:33:33 PM PDT 24
Finished Jun 29 05:33:35 PM PDT 24
Peak memory 218852 kb
Host smart-fc9e9c94-3092-48df-9cc3-b06c321b6677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109790431 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.2109790431
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.1229902549
Short name T436
Test name
Test status
Simulation time 34455981 ps
CPU time 1.39 seconds
Started Jun 29 05:33:39 PM PDT 24
Finished Jun 29 05:33:41 PM PDT 24
Peak memory 219164 kb
Host smart-37fb9921-c1a0-4a03-8639-03e9fb57ba38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229902549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1229902549
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.3649797479
Short name T625
Test name
Test status
Simulation time 37619244 ps
CPU time 1.11 seconds
Started Jun 29 05:33:42 PM PDT 24
Finished Jun 29 05:33:45 PM PDT 24
Peak memory 218824 kb
Host smart-8002bfc1-21d1-4c4c-b49e-36ce72ac5b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649797479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3649797479
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.1311152669
Short name T331
Test name
Test status
Simulation time 28604091 ps
CPU time 1.36 seconds
Started Jun 29 05:33:31 PM PDT 24
Finished Jun 29 05:33:35 PM PDT 24
Peak memory 218804 kb
Host smart-36070ba9-2336-4461-b734-6189ff2e40d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311152669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1311152669
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.1532841091
Short name T117
Test name
Test status
Simulation time 30944872 ps
CPU time 1.34 seconds
Started Jun 29 05:33:34 PM PDT 24
Finished Jun 29 05:33:36 PM PDT 24
Peak memory 220028 kb
Host smart-7c66d92d-a70b-4d0a-a0c3-9f752b812ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532841091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.1532841091
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.85471258
Short name T607
Test name
Test status
Simulation time 33000976 ps
CPU time 1.44 seconds
Started Jun 29 05:33:29 PM PDT 24
Finished Jun 29 05:33:31 PM PDT 24
Peak memory 217820 kb
Host smart-d2f5e314-f73a-4cfd-9df9-ce489f1bcae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85471258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.85471258
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.2126855575
Short name T220
Test name
Test status
Simulation time 85122196 ps
CPU time 1.26 seconds
Started Jun 29 05:33:26 PM PDT 24
Finished Jun 29 05:33:28 PM PDT 24
Peak memory 219548 kb
Host smart-d79c714d-92df-418e-946b-59119f5c6c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126855575 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2126855575
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/124.edn_alert.242270497
Short name T796
Test name
Test status
Simulation time 58640391 ps
CPU time 1.12 seconds
Started Jun 29 05:33:33 PM PDT 24
Finished Jun 29 05:33:36 PM PDT 24
Peak memory 219876 kb
Host smart-4bea1195-c2e2-4b35-b144-2acc2bfb83bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242270497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.242270497
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/125.edn_alert.3603500183
Short name T827
Test name
Test status
Simulation time 45093795 ps
CPU time 1.2 seconds
Started Jun 29 05:33:30 PM PDT 24
Finished Jun 29 05:33:32 PM PDT 24
Peak memory 220172 kb
Host smart-131a3da7-2e4b-4781-bab3-6171d4c1868a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603500183 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.3603500183
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.1648867670
Short name T542
Test name
Test status
Simulation time 32118540 ps
CPU time 1.02 seconds
Started Jun 29 05:33:41 PM PDT 24
Finished Jun 29 05:33:43 PM PDT 24
Peak memory 217544 kb
Host smart-eb26ff4c-864f-46e1-82b3-ccb21d2fcd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648867670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1648867670
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.1294293087
Short name T678
Test name
Test status
Simulation time 29649175 ps
CPU time 1.3 seconds
Started Jun 29 05:33:38 PM PDT 24
Finished Jun 29 05:33:39 PM PDT 24
Peak memory 215988 kb
Host smart-d9638102-ead4-41ba-a070-43418742b563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294293087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.1294293087
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.2015339452
Short name T777
Test name
Test status
Simulation time 88556875 ps
CPU time 1.13 seconds
Started Jun 29 05:33:38 PM PDT 24
Finished Jun 29 05:33:39 PM PDT 24
Peak memory 220332 kb
Host smart-d9c7611d-589e-4e60-b9e2-4e9bee8ec6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015339452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2015339452
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.3803866797
Short name T604
Test name
Test status
Simulation time 98421455 ps
CPU time 1.13 seconds
Started Jun 29 05:33:33 PM PDT 24
Finished Jun 29 05:33:35 PM PDT 24
Peak memory 218876 kb
Host smart-21fa75a1-aabc-4830-bdc8-c2b4dd574375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803866797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.3803866797
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.807833211
Short name T467
Test name
Test status
Simulation time 37008711 ps
CPU time 1.7 seconds
Started Jun 29 05:33:30 PM PDT 24
Finished Jun 29 05:33:33 PM PDT 24
Peak memory 217808 kb
Host smart-6e1066b4-31c7-4976-9574-dc9af12065e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807833211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.807833211
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.451819387
Short name T431
Test name
Test status
Simulation time 30762083 ps
CPU time 1.11 seconds
Started Jun 29 05:33:37 PM PDT 24
Finished Jun 29 05:33:38 PM PDT 24
Peak memory 218852 kb
Host smart-b6c9500c-9061-4361-82fc-b35418099f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451819387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.451819387
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.338341938
Short name T633
Test name
Test status
Simulation time 280489698 ps
CPU time 3.97 seconds
Started Jun 29 05:33:29 PM PDT 24
Finished Jun 29 05:33:33 PM PDT 24
Peak memory 220512 kb
Host smart-2ebf3080-b5b7-4de7-97cc-f207dddc3880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338341938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.338341938
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1943224183
Short name T144
Test name
Test status
Simulation time 47613456 ps
CPU time 1.04 seconds
Started Jun 29 05:32:06 PM PDT 24
Finished Jun 29 05:32:08 PM PDT 24
Peak memory 221100 kb
Host smart-2d861319-4436-4fbe-bf6d-2451c56d9973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943224183 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1943224183
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.1361263276
Short name T75
Test name
Test status
Simulation time 14685300 ps
CPU time 0.95 seconds
Started Jun 29 05:32:07 PM PDT 24
Finished Jun 29 05:32:09 PM PDT 24
Peak memory 207032 kb
Host smart-721c83f6-7ac7-4cca-bb74-c43279703bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361263276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1361263276
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.846072334
Short name T585
Test name
Test status
Simulation time 30964303 ps
CPU time 0.91 seconds
Started Jun 29 05:32:01 PM PDT 24
Finished Jun 29 05:32:02 PM PDT 24
Peak memory 216232 kb
Host smart-195cdfd9-b947-4a54-9592-ad36a65e7f40
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846072334 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.846072334
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3563636841
Short name T136
Test name
Test status
Simulation time 96759066 ps
CPU time 1.27 seconds
Started Jun 29 05:32:04 PM PDT 24
Finished Jun 29 05:32:06 PM PDT 24
Peak memory 217052 kb
Host smart-69390e1e-e3ba-486c-bc52-d160a84ab805
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563636841 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3563636841
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.192538212
Short name T203
Test name
Test status
Simulation time 165535145 ps
CPU time 1.15 seconds
Started Jun 29 05:32:04 PM PDT 24
Finished Jun 29 05:32:06 PM PDT 24
Peak memory 220284 kb
Host smart-8a316046-edd1-42a4-9b22-c1baf7e28225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192538212 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.192538212
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1953668181
Short name T355
Test name
Test status
Simulation time 58326182 ps
CPU time 1.05 seconds
Started Jun 29 05:32:08 PM PDT 24
Finished Jun 29 05:32:10 PM PDT 24
Peak memory 217708 kb
Host smart-66259c56-a75f-43ab-9065-f91c71d8e783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953668181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1953668181
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.4105024130
Short name T112
Test name
Test status
Simulation time 30883083 ps
CPU time 0.95 seconds
Started Jun 29 05:32:02 PM PDT 24
Finished Jun 29 05:32:04 PM PDT 24
Peak memory 216148 kb
Host smart-a5a59001-0220-4a1f-8037-f3f96d8949ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105024130 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.4105024130
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2887897837
Short name T717
Test name
Test status
Simulation time 74409444 ps
CPU time 0.92 seconds
Started Jun 29 05:32:01 PM PDT 24
Finished Jun 29 05:32:02 PM PDT 24
Peak memory 215516 kb
Host smart-21ac56e2-ae3e-4e96-8b91-48b21ec2525b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887897837 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2887897837
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3789511820
Short name T460
Test name
Test status
Simulation time 367953624 ps
CPU time 4.03 seconds
Started Jun 29 05:32:07 PM PDT 24
Finished Jun 29 05:32:12 PM PDT 24
Peak memory 220452 kb
Host smart-000403c8-cc2a-464b-98a3-fb4221128838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789511820 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3789511820
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.306926396
Short name T718
Test name
Test status
Simulation time 37808067519 ps
CPU time 961.91 seconds
Started Jun 29 05:32:07 PM PDT 24
Finished Jun 29 05:48:10 PM PDT 24
Peak memory 219952 kb
Host smart-01a06158-6f64-45e0-b217-df63f385e996
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306926396 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.306926396
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.2093626664
Short name T973
Test name
Test status
Simulation time 30635129 ps
CPU time 1.18 seconds
Started Jun 29 05:33:36 PM PDT 24
Finished Jun 29 05:33:38 PM PDT 24
Peak memory 219972 kb
Host smart-9253f7aa-1556-40db-af02-7625afedf5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093626664 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2093626664
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.935495383
Short name T668
Test name
Test status
Simulation time 44941892 ps
CPU time 1.14 seconds
Started Jun 29 05:33:43 PM PDT 24
Finished Jun 29 05:33:46 PM PDT 24
Peak memory 218980 kb
Host smart-ba54fd51-6082-4110-b9f6-393eaca10858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935495383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.935495383
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.1779555081
Short name T743
Test name
Test status
Simulation time 215522976 ps
CPU time 1.24 seconds
Started Jun 29 05:33:44 PM PDT 24
Finished Jun 29 05:33:47 PM PDT 24
Peak memory 218952 kb
Host smart-2031ed54-a03b-430e-ae55-5ce1c342c5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779555081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.1779555081
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.4218041314
Short name T469
Test name
Test status
Simulation time 71447919 ps
CPU time 1.38 seconds
Started Jun 29 05:33:34 PM PDT 24
Finished Jun 29 05:33:37 PM PDT 24
Peak memory 217844 kb
Host smart-a476d73b-f2e9-4dc2-893e-2bac3f23e7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218041314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.4218041314
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.2587503957
Short name T513
Test name
Test status
Simulation time 55062486 ps
CPU time 1.29 seconds
Started Jun 29 05:33:47 PM PDT 24
Finished Jun 29 05:33:50 PM PDT 24
Peak memory 218956 kb
Host smart-0b8a6c73-9b8e-460d-bf58-879eddd1a411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587503957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.2587503957
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.2716202677
Short name T410
Test name
Test status
Simulation time 39579975 ps
CPU time 1.49 seconds
Started Jun 29 05:33:29 PM PDT 24
Finished Jun 29 05:33:31 PM PDT 24
Peak memory 218596 kb
Host smart-632d82dd-cf4e-4bf1-a47f-0068c39ee0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716202677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2716202677
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.4073897492
Short name T661
Test name
Test status
Simulation time 24491017 ps
CPU time 1.22 seconds
Started Jun 29 05:33:35 PM PDT 24
Finished Jun 29 05:33:37 PM PDT 24
Peak memory 220872 kb
Host smart-a3989675-6a47-43f8-a367-ebd3b6b605ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073897492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.4073897492
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.3713356619
Short name T754
Test name
Test status
Simulation time 41511384 ps
CPU time 1.66 seconds
Started Jun 29 05:33:33 PM PDT 24
Finished Jun 29 05:33:36 PM PDT 24
Peak memory 217764 kb
Host smart-f0c5b2d7-51da-4586-a856-00dd3b9f56c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713356619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3713356619
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.1613867700
Short name T159
Test name
Test status
Simulation time 81741590 ps
CPU time 1.35 seconds
Started Jun 29 05:33:41 PM PDT 24
Finished Jun 29 05:33:44 PM PDT 24
Peak memory 218676 kb
Host smart-64e2a76f-9654-4210-b2fd-2fccfa73892b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613867700 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1613867700
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.32017790
Short name T713
Test name
Test status
Simulation time 19771454 ps
CPU time 1.18 seconds
Started Jun 29 05:33:42 PM PDT 24
Finished Jun 29 05:33:46 PM PDT 24
Peak memory 217572 kb
Host smart-52102daf-b142-490a-b5c8-8a568f731966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32017790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.32017790
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.301481881
Short name T89
Test name
Test status
Simulation time 31669754 ps
CPU time 1.18 seconds
Started Jun 29 05:33:30 PM PDT 24
Finished Jun 29 05:33:33 PM PDT 24
Peak memory 218864 kb
Host smart-235e806c-f8c9-4da8-98e9-baa8d2655897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301481881 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.301481881
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.3817515874
Short name T769
Test name
Test status
Simulation time 38965836 ps
CPU time 1.65 seconds
Started Jun 29 05:33:31 PM PDT 24
Finished Jun 29 05:33:35 PM PDT 24
Peak memory 218652 kb
Host smart-0ce30ebb-8241-4f35-abee-dcf49c018d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817515874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3817515874
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.3866844181
Short name T298
Test name
Test status
Simulation time 141911479 ps
CPU time 1.18 seconds
Started Jun 29 05:33:47 PM PDT 24
Finished Jun 29 05:33:50 PM PDT 24
Peak memory 218844 kb
Host smart-2c58301d-b4fe-42db-9a15-2940783d4cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866844181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.3866844181
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.2485897441
Short name T508
Test name
Test status
Simulation time 236607496 ps
CPU time 3.31 seconds
Started Jun 29 05:33:30 PM PDT 24
Finished Jun 29 05:33:35 PM PDT 24
Peak memory 220340 kb
Host smart-2ecf60a3-4f3f-4a21-b2b3-138037866dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485897441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2485897441
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.991581343
Short name T454
Test name
Test status
Simulation time 77785329 ps
CPU time 1.08 seconds
Started Jun 29 05:33:41 PM PDT 24
Finished Jun 29 05:33:44 PM PDT 24
Peak memory 220140 kb
Host smart-10ce0ecc-96b0-43e8-8514-513d31eebbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991581343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.991581343
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.720592574
Short name T480
Test name
Test status
Simulation time 218853426 ps
CPU time 1.79 seconds
Started Jun 29 05:33:39 PM PDT 24
Finished Jun 29 05:33:41 PM PDT 24
Peak memory 220404 kb
Host smart-454449b4-ee72-45d3-be1b-8c134e57f57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720592574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.720592574
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.904488362
Short name T289
Test name
Test status
Simulation time 27361352 ps
CPU time 1.29 seconds
Started Jun 29 05:33:41 PM PDT 24
Finished Jun 29 05:33:43 PM PDT 24
Peak memory 218876 kb
Host smart-3ce3e22f-3367-4e36-aa7d-165c6a4b968c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904488362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.904488362
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.2938676064
Short name T839
Test name
Test status
Simulation time 36620037 ps
CPU time 1.62 seconds
Started Jun 29 05:33:40 PM PDT 24
Finished Jun 29 05:33:42 PM PDT 24
Peak memory 218784 kb
Host smart-55413798-51d6-42f9-a225-a5a92b5e3f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938676064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2938676064
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.2927195275
Short name T462
Test name
Test status
Simulation time 41453191 ps
CPU time 1.2 seconds
Started Jun 29 05:33:33 PM PDT 24
Finished Jun 29 05:33:35 PM PDT 24
Peak memory 219724 kb
Host smart-74b64257-1089-4319-a32a-7131580db0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927195275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.2927195275
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.601065716
Short name T631
Test name
Test status
Simulation time 28972455 ps
CPU time 1.3 seconds
Started Jun 29 05:33:44 PM PDT 24
Finished Jun 29 05:33:47 PM PDT 24
Peak memory 220244 kb
Host smart-5b7a9379-52cc-4bfd-9718-7b819a5f65f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601065716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.601065716
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3178368610
Short name T150
Test name
Test status
Simulation time 39185257 ps
CPU time 1.18 seconds
Started Jun 29 05:32:12 PM PDT 24
Finished Jun 29 05:32:14 PM PDT 24
Peak memory 219568 kb
Host smart-a795609d-7d5a-4cc0-93ac-902a10d1a0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178368610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3178368610
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1789811317
Short name T77
Test name
Test status
Simulation time 25806656 ps
CPU time 0.91 seconds
Started Jun 29 05:32:11 PM PDT 24
Finished Jun 29 05:32:13 PM PDT 24
Peak memory 215468 kb
Host smart-2aff23de-aa9b-4ed3-86de-1aced176f868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789811317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1789811317
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.2915427192
Short name T873
Test name
Test status
Simulation time 118581968 ps
CPU time 0.91 seconds
Started Jun 29 05:32:10 PM PDT 24
Finished Jun 29 05:32:11 PM PDT 24
Peak memory 216540 kb
Host smart-81ffc4ab-4395-4bb0-9d22-b2d5af6f08a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915427192 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2915427192
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3051273724
Short name T425
Test name
Test status
Simulation time 34999455 ps
CPU time 1.26 seconds
Started Jun 29 05:32:11 PM PDT 24
Finished Jun 29 05:32:14 PM PDT 24
Peak memory 217272 kb
Host smart-14720a34-c6e7-4850-91cc-b8c89527b4bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051273724 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3051273724
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3006139064
Short name T193
Test name
Test status
Simulation time 18539647 ps
CPU time 1.03 seconds
Started Jun 29 05:32:12 PM PDT 24
Finished Jun 29 05:32:14 PM PDT 24
Peak memory 218532 kb
Host smart-75c6fe40-f0c5-4624-ab7c-0e8117b4bc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006139064 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3006139064
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.4235727605
Short name T812
Test name
Test status
Simulation time 60676621 ps
CPU time 1.94 seconds
Started Jun 29 05:32:07 PM PDT 24
Finished Jun 29 05:32:10 PM PDT 24
Peak memory 220004 kb
Host smart-348d542f-82f0-402c-9fc4-f0d335293ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235727605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.4235727605
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2754362995
Short name T670
Test name
Test status
Simulation time 32270676 ps
CPU time 0.94 seconds
Started Jun 29 05:32:12 PM PDT 24
Finished Jun 29 05:32:14 PM PDT 24
Peak memory 215708 kb
Host smart-09187bb6-109b-41aa-a004-05e695508d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754362995 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2754362995
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.1535192910
Short name T882
Test name
Test status
Simulation time 26727368 ps
CPU time 0.89 seconds
Started Jun 29 05:32:01 PM PDT 24
Finished Jun 29 05:32:03 PM PDT 24
Peak memory 215620 kb
Host smart-82c3e8f7-b6c1-4bdd-80c3-183da1d2e372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535192910 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1535192910
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.835714006
Short name T572
Test name
Test status
Simulation time 930925684 ps
CPU time 5.26 seconds
Started Jun 29 05:32:02 PM PDT 24
Finished Jun 29 05:32:08 PM PDT 24
Peak memory 217716 kb
Host smart-644cb3e2-a04b-4e11-b390-7774b661ab50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835714006 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.835714006
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3754016096
Short name T944
Test name
Test status
Simulation time 46287924412 ps
CPU time 467.46 seconds
Started Jun 29 05:32:02 PM PDT 24
Finished Jun 29 05:39:50 PM PDT 24
Peak memory 218232 kb
Host smart-5b055e79-051f-44e0-a6dc-27215a1ae33e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754016096 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3754016096
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.2080907073
Short name T338
Test name
Test status
Simulation time 34536556 ps
CPU time 1.41 seconds
Started Jun 29 05:33:37 PM PDT 24
Finished Jun 29 05:33:39 PM PDT 24
Peak memory 220044 kb
Host smart-5a180381-b2ba-42a1-b87a-7ef5d306d949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080907073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2080907073
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.3701310895
Short name T919
Test name
Test status
Simulation time 28470531 ps
CPU time 1.24 seconds
Started Jun 29 05:33:45 PM PDT 24
Finished Jun 29 05:33:49 PM PDT 24
Peak memory 215976 kb
Host smart-51ef1df8-78e6-4b29-8a83-00e672a9a128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701310895 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.3701310895
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.1646362267
Short name T881
Test name
Test status
Simulation time 31531302 ps
CPU time 1.57 seconds
Started Jun 29 05:33:52 PM PDT 24
Finished Jun 29 05:33:54 PM PDT 24
Peak memory 218660 kb
Host smart-7d012b8c-df05-4679-8cdd-2d950c63a060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646362267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1646362267
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.3087297219
Short name T501
Test name
Test status
Simulation time 46635172 ps
CPU time 1.8 seconds
Started Jun 29 05:33:43 PM PDT 24
Finished Jun 29 05:33:47 PM PDT 24
Peak memory 220372 kb
Host smart-df5a754e-5db9-415f-b510-8e4047c50b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087297219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3087297219
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.281872985
Short name T943
Test name
Test status
Simulation time 123642458 ps
CPU time 1.16 seconds
Started Jun 29 05:33:30 PM PDT 24
Finished Jun 29 05:33:32 PM PDT 24
Peak memory 220764 kb
Host smart-0e69ed1b-9e5c-4783-aa2a-395a106dcbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281872985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.281872985
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.4148750747
Short name T995
Test name
Test status
Simulation time 32785039 ps
CPU time 1.38 seconds
Started Jun 29 05:33:47 PM PDT 24
Finished Jun 29 05:33:50 PM PDT 24
Peak memory 218948 kb
Host smart-f26efa02-f12f-4f95-b088-0328d6a6ad8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148750747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.4148750747
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.2199631954
Short name T599
Test name
Test status
Simulation time 35070583 ps
CPU time 1.06 seconds
Started Jun 29 05:33:39 PM PDT 24
Finished Jun 29 05:33:41 PM PDT 24
Peak memory 220152 kb
Host smart-0b142bca-2d77-46c8-b3f0-84f8d358f70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199631954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.2199631954
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.4049582160
Short name T941
Test name
Test status
Simulation time 28665889 ps
CPU time 1.25 seconds
Started Jun 29 05:33:41 PM PDT 24
Finished Jun 29 05:33:44 PM PDT 24
Peak memory 219872 kb
Host smart-54d6604f-0f2b-4587-8e95-c873b7b2da83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049582160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.4049582160
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.3716806617
Short name T671
Test name
Test status
Simulation time 131024131 ps
CPU time 1.28 seconds
Started Jun 29 05:33:38 PM PDT 24
Finished Jun 29 05:33:40 PM PDT 24
Peak memory 221152 kb
Host smart-07428726-1617-4aa2-954e-4edc9e2fe8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716806617 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.3716806617
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.1054870058
Short name T334
Test name
Test status
Simulation time 38958997 ps
CPU time 1.4 seconds
Started Jun 29 05:33:39 PM PDT 24
Finished Jun 29 05:33:40 PM PDT 24
Peak memory 218692 kb
Host smart-34fd78a3-c6b3-4120-a1f2-5e72017b0235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054870058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1054870058
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.2943388152
Short name T636
Test name
Test status
Simulation time 91423438 ps
CPU time 1.28 seconds
Started Jun 29 05:33:41 PM PDT 24
Finished Jun 29 05:33:43 PM PDT 24
Peak memory 215896 kb
Host smart-a49b6857-53a5-4e70-ab77-fa5edee49a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943388152 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.2943388152
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2983987003
Short name T85
Test name
Test status
Simulation time 39054458 ps
CPU time 1.16 seconds
Started Jun 29 05:33:40 PM PDT 24
Finished Jun 29 05:33:42 PM PDT 24
Peak memory 219076 kb
Host smart-234dca73-eda4-45ab-8efd-4892540315c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983987003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2983987003
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.1169322927
Short name T449
Test name
Test status
Simulation time 69154254 ps
CPU time 1.14 seconds
Started Jun 29 05:33:34 PM PDT 24
Finished Jun 29 05:33:36 PM PDT 24
Peak memory 220108 kb
Host smart-8e3b9675-a843-4f2e-9329-82360022f065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169322927 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.1169322927
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.4086885717
Short name T74
Test name
Test status
Simulation time 40502332 ps
CPU time 1.57 seconds
Started Jun 29 05:33:46 PM PDT 24
Finished Jun 29 05:33:50 PM PDT 24
Peak memory 218640 kb
Host smart-1c386dad-9291-48e7-927b-53edfcea2600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086885717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.4086885717
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.3979772134
Short name T855
Test name
Test status
Simulation time 47699426 ps
CPU time 1.2 seconds
Started Jun 29 05:33:31 PM PDT 24
Finished Jun 29 05:33:34 PM PDT 24
Peak memory 220964 kb
Host smart-0c4a8aad-5e06-4cad-80c3-82f35b457456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979772134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.3979772134
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.3383212458
Short name T475
Test name
Test status
Simulation time 239047424 ps
CPU time 1.91 seconds
Started Jun 29 05:33:39 PM PDT 24
Finished Jun 29 05:33:42 PM PDT 24
Peak memory 218976 kb
Host smart-677fe07c-48a3-4182-b9cb-24036b974739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383212458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3383212458
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.2039720584
Short name T579
Test name
Test status
Simulation time 39978747 ps
CPU time 1.09 seconds
Started Jun 29 05:33:40 PM PDT 24
Finished Jun 29 05:33:43 PM PDT 24
Peak memory 218844 kb
Host smart-579bdb6f-24d0-48da-84a2-a1ced4d8403e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039720584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.2039720584
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.2959716093
Short name T916
Test name
Test status
Simulation time 100082303 ps
CPU time 1.39 seconds
Started Jun 29 05:33:35 PM PDT 24
Finished Jun 29 05:33:37 PM PDT 24
Peak memory 220212 kb
Host smart-7849b10a-6fde-4a7a-b875-79ea995cc07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959716093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2959716093
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.997804256
Short name T799
Test name
Test status
Simulation time 23167811 ps
CPU time 1.22 seconds
Started Jun 29 05:32:09 PM PDT 24
Finished Jun 29 05:32:10 PM PDT 24
Peak memory 219904 kb
Host smart-71ecf93b-77b0-4cf1-af65-fc6367d2f2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997804256 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.997804256
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3852247211
Short name T828
Test name
Test status
Simulation time 23600373 ps
CPU time 0.84 seconds
Started Jun 29 05:32:09 PM PDT 24
Finished Jun 29 05:32:11 PM PDT 24
Peak memory 206756 kb
Host smart-8e7d81a9-c86a-4c73-ba84-5e9292331dcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852247211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3852247211
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.4076391469
Short name T588
Test name
Test status
Simulation time 44988619 ps
CPU time 0.94 seconds
Started Jun 29 05:32:13 PM PDT 24
Finished Jun 29 05:32:15 PM PDT 24
Peak memory 216360 kb
Host smart-b54ddb77-0f48-4f64-9c5c-93669041149e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076391469 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.4076391469
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3436413663
Short name T253
Test name
Test status
Simulation time 87805164 ps
CPU time 1.32 seconds
Started Jun 29 05:32:10 PM PDT 24
Finished Jun 29 05:32:12 PM PDT 24
Peak memory 217036 kb
Host smart-bacf9bc6-d3d7-4325-8fa2-692585d92b7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436413663 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3436413663
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_genbits.1229547516
Short name T775
Test name
Test status
Simulation time 79445396 ps
CPU time 1.21 seconds
Started Jun 29 05:32:10 PM PDT 24
Finished Jun 29 05:32:12 PM PDT 24
Peak memory 219392 kb
Host smart-36d3ce18-57f5-4eb5-8aac-fd24b28fe732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229547516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1229547516
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.521825782
Short name T30
Test name
Test status
Simulation time 33928331 ps
CPU time 0.92 seconds
Started Jun 29 05:32:08 PM PDT 24
Finished Jun 29 05:32:10 PM PDT 24
Peak memory 216064 kb
Host smart-13113004-b0b7-43fd-8c31-c23e1cf44b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521825782 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.521825782
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3315601687
Short name T613
Test name
Test status
Simulation time 18411041 ps
CPU time 1.1 seconds
Started Jun 29 05:32:08 PM PDT 24
Finished Jun 29 05:32:10 PM PDT 24
Peak memory 215620 kb
Host smart-1c3de965-eb2c-41c0-9ca7-15ee763cd18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315601687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3315601687
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2009093886
Short name T956
Test name
Test status
Simulation time 325836425 ps
CPU time 2.67 seconds
Started Jun 29 05:32:11 PM PDT 24
Finished Jun 29 05:32:16 PM PDT 24
Peak memory 217460 kb
Host smart-07820e96-24c6-4d07-854d-9bd0ed85d66e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009093886 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2009093886
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.132289907
Short name T570
Test name
Test status
Simulation time 128190899772 ps
CPU time 1707.44 seconds
Started Jun 29 05:32:11 PM PDT 24
Finished Jun 29 06:00:40 PM PDT 24
Peak memory 227036 kb
Host smart-24e4826a-0583-4e58-a8cc-873b22245b87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132289907 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.132289907
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.1894908955
Short name T557
Test name
Test status
Simulation time 88758097 ps
CPU time 1.25 seconds
Started Jun 29 05:33:40 PM PDT 24
Finished Jun 29 05:33:43 PM PDT 24
Peak memory 216000 kb
Host smart-84d248ed-9e94-45d4-87e4-598966fe6bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894908955 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.1894908955
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.1505863614
Short name T430
Test name
Test status
Simulation time 26686458 ps
CPU time 1.17 seconds
Started Jun 29 05:33:44 PM PDT 24
Finished Jun 29 05:33:48 PM PDT 24
Peak memory 218776 kb
Host smart-e96968dd-d330-4ea7-a685-fdf340e8dc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505863614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1505863614
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.753943188
Short name T121
Test name
Test status
Simulation time 47708811 ps
CPU time 1.2 seconds
Started Jun 29 05:33:31 PM PDT 24
Finished Jun 29 05:33:34 PM PDT 24
Peak memory 219524 kb
Host smart-99c73da2-a21a-470a-a28c-78df0903b943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753943188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.753943188
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.3695446976
Short name T641
Test name
Test status
Simulation time 95800014 ps
CPU time 1.28 seconds
Started Jun 29 05:33:34 PM PDT 24
Finished Jun 29 05:33:37 PM PDT 24
Peak memory 220400 kb
Host smart-d4a8cafc-6af0-4570-bbd5-5c034066d819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695446976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3695446976
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.3608934068
Short name T293
Test name
Test status
Simulation time 40191162 ps
CPU time 1.24 seconds
Started Jun 29 05:33:36 PM PDT 24
Finished Jun 29 05:33:38 PM PDT 24
Peak memory 219024 kb
Host smart-470531e4-7e16-4e55-83ac-590c59ec2b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608934068 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3608934068
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.3008453882
Short name T72
Test name
Test status
Simulation time 163051671 ps
CPU time 1.23 seconds
Started Jun 29 05:33:41 PM PDT 24
Finished Jun 29 05:33:44 PM PDT 24
Peak memory 220016 kb
Host smart-bd7f5fde-ce36-499c-a604-276f0ed95a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008453882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3008453882
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.1545471832
Short name T313
Test name
Test status
Simulation time 25635713 ps
CPU time 1.26 seconds
Started Jun 29 05:33:50 PM PDT 24
Finished Jun 29 05:33:52 PM PDT 24
Peak memory 220012 kb
Host smart-ac111052-f08a-4ad8-9c36-8c98bc2bd54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545471832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1545471832
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.1028880261
Short name T622
Test name
Test status
Simulation time 43377231 ps
CPU time 1.11 seconds
Started Jun 29 05:33:46 PM PDT 24
Finished Jun 29 05:33:50 PM PDT 24
Peak memory 217600 kb
Host smart-3895d6da-bcea-4c95-b508-3ec9e2fd10b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028880261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1028880261
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.3777922980
Short name T698
Test name
Test status
Simulation time 52232982 ps
CPU time 1.67 seconds
Started Jun 29 05:33:40 PM PDT 24
Finished Jun 29 05:33:42 PM PDT 24
Peak memory 218776 kb
Host smart-cd89341d-b262-4604-81ce-d379c2365fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777922980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3777922980
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.3670144992
Short name T158
Test name
Test status
Simulation time 93379953 ps
CPU time 1.28 seconds
Started Jun 29 05:33:31 PM PDT 24
Finished Jun 29 05:33:34 PM PDT 24
Peak memory 220124 kb
Host smart-f1f6adcc-8be1-4747-9c75-85a0b6b4e788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670144992 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.3670144992
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1116932894
Short name T965
Test name
Test status
Simulation time 37459683 ps
CPU time 1.41 seconds
Started Jun 29 05:33:32 PM PDT 24
Finished Jun 29 05:33:35 PM PDT 24
Peak memory 218704 kb
Host smart-b76f6c8a-12a8-48a3-95f7-23f554672b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116932894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1116932894
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.3102033829
Short name T105
Test name
Test status
Simulation time 39832748 ps
CPU time 1.18 seconds
Started Jun 29 05:33:32 PM PDT 24
Finished Jun 29 05:33:35 PM PDT 24
Peak memory 220132 kb
Host smart-1f62d961-895e-4f4e-ba93-fe20c6e892e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102033829 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.3102033829
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.2065211852
Short name T935
Test name
Test status
Simulation time 36282663 ps
CPU time 1.5 seconds
Started Jun 29 05:33:38 PM PDT 24
Finished Jun 29 05:33:40 PM PDT 24
Peak memory 220136 kb
Host smart-379f75f4-89fa-4f62-a3a3-56ab9c8635de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065211852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2065211852
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.1841302801
Short name T792
Test name
Test status
Simulation time 24012606 ps
CPU time 1.13 seconds
Started Jun 29 05:33:38 PM PDT 24
Finished Jun 29 05:33:40 PM PDT 24
Peak memory 218724 kb
Host smart-2ac0461f-24b8-4c97-bf35-47b6a6b778e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841302801 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.1841302801
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/158.edn_alert.2709943507
Short name T630
Test name
Test status
Simulation time 26300830 ps
CPU time 1.27 seconds
Started Jun 29 05:33:44 PM PDT 24
Finished Jun 29 05:33:47 PM PDT 24
Peak memory 219820 kb
Host smart-aea219e4-ec8f-4462-b828-26f5371f724c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709943507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.2709943507
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.359124066
Short name T1
Test name
Test status
Simulation time 84199782 ps
CPU time 1.85 seconds
Started Jun 29 05:33:40 PM PDT 24
Finished Jun 29 05:33:42 PM PDT 24
Peak memory 219184 kb
Host smart-c5140d97-d2fd-4780-a46e-7f28802af44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359124066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.359124066
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.2364663707
Short name T714
Test name
Test status
Simulation time 103742525 ps
CPU time 1.28 seconds
Started Jun 29 05:33:42 PM PDT 24
Finished Jun 29 05:33:44 PM PDT 24
Peak memory 220284 kb
Host smart-948aa476-3683-4c3d-916d-c732c81607d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364663707 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.2364663707
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.3987888090
Short name T517
Test name
Test status
Simulation time 28159398 ps
CPU time 1.19 seconds
Started Jun 29 05:33:46 PM PDT 24
Finished Jun 29 05:33:50 PM PDT 24
Peak memory 218848 kb
Host smart-95760558-371e-49f5-b7ad-02df637324e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987888090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3987888090
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2240775977
Short name T810
Test name
Test status
Simulation time 27246504 ps
CPU time 1.29 seconds
Started Jun 29 05:32:09 PM PDT 24
Finished Jun 29 05:32:11 PM PDT 24
Peak memory 220140 kb
Host smart-fb6f8df6-178d-4b23-815f-6366ec66ee0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240775977 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2240775977
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.617254801
Short name T724
Test name
Test status
Simulation time 55985106 ps
CPU time 0.99 seconds
Started Jun 29 05:32:13 PM PDT 24
Finished Jun 29 05:32:15 PM PDT 24
Peak memory 215288 kb
Host smart-7e1e2b86-c351-411c-bdab-95195d1e0536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617254801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.617254801
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.3721834557
Short name T970
Test name
Test status
Simulation time 60737025 ps
CPU time 0.81 seconds
Started Jun 29 05:32:09 PM PDT 24
Finished Jun 29 05:32:10 PM PDT 24
Peak memory 216284 kb
Host smart-bd305c98-591d-4489-aeaf-f403f894a3fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721834557 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3721834557
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1380505902
Short name T147
Test name
Test status
Simulation time 53679618 ps
CPU time 1.17 seconds
Started Jun 29 05:32:11 PM PDT 24
Finished Jun 29 05:32:14 PM PDT 24
Peak memory 217216 kb
Host smart-c2187656-95ff-40b4-b68d-9dc660eb0e25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380505902 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1380505902
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1188769047
Short name T443
Test name
Test status
Simulation time 46628268 ps
CPU time 0.85 seconds
Started Jun 29 05:32:12 PM PDT 24
Finished Jun 29 05:32:14 PM PDT 24
Peak memory 218664 kb
Host smart-b0c5e4cc-6d35-4bb4-927f-5a29a1ebdb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188769047 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1188769047
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3443094691
Short name T700
Test name
Test status
Simulation time 284184816 ps
CPU time 1.18 seconds
Started Jun 29 05:32:10 PM PDT 24
Finished Jun 29 05:32:13 PM PDT 24
Peak memory 217604 kb
Host smart-cf87a5b5-3cff-425d-b091-6a60a5748e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443094691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3443094691
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2915396888
Short name T33
Test name
Test status
Simulation time 38209895 ps
CPU time 0.92 seconds
Started Jun 29 05:32:32 PM PDT 24
Finished Jun 29 05:32:34 PM PDT 24
Peak memory 216156 kb
Host smart-7910c965-c647-4fea-a24c-e25b37d89938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915396888 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2915396888
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3933391752
Short name T857
Test name
Test status
Simulation time 22833961 ps
CPU time 0.92 seconds
Started Jun 29 05:32:12 PM PDT 24
Finished Jun 29 05:32:14 PM PDT 24
Peak memory 215676 kb
Host smart-dfe28828-5a22-4da3-90b2-54b6c652f9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933391752 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3933391752
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3620811745
Short name T555
Test name
Test status
Simulation time 220700495 ps
CPU time 2.77 seconds
Started Jun 29 05:32:15 PM PDT 24
Finished Jun 29 05:32:18 PM PDT 24
Peak memory 215540 kb
Host smart-fd0f7d22-4f06-47b3-a224-9ff7892e3ced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620811745 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3620811745
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3467592311
Short name T918
Test name
Test status
Simulation time 55122820687 ps
CPU time 1376.42 seconds
Started Jun 29 05:32:08 PM PDT 24
Finished Jun 29 05:55:06 PM PDT 24
Peak memory 224512 kb
Host smart-8846c56b-41bd-4a95-b071-e45a3bcf22e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467592311 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3467592311
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.3629685073
Short name T752
Test name
Test status
Simulation time 76926798 ps
CPU time 1.19 seconds
Started Jun 29 05:33:33 PM PDT 24
Finished Jun 29 05:33:35 PM PDT 24
Peak memory 219212 kb
Host smart-08b4e0d3-89f4-40e6-b555-ae0d65554a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629685073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3629685073
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1282870565
Short name T50
Test name
Test status
Simulation time 80406986 ps
CPU time 1.58 seconds
Started Jun 29 05:33:41 PM PDT 24
Finished Jun 29 05:33:44 PM PDT 24
Peak memory 219008 kb
Host smart-475aa68e-4322-4a61-b3e1-c6e736533543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282870565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1282870565
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.1322479297
Short name T315
Test name
Test status
Simulation time 27024906 ps
CPU time 1.3 seconds
Started Jun 29 05:33:44 PM PDT 24
Finished Jun 29 05:33:47 PM PDT 24
Peak memory 220828 kb
Host smart-42162274-e74a-45ab-84d3-6f4c9f4cb31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322479297 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.1322479297
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.3804219652
Short name T974
Test name
Test status
Simulation time 82303066 ps
CPU time 1.09 seconds
Started Jun 29 05:33:46 PM PDT 24
Finished Jun 29 05:33:50 PM PDT 24
Peak memory 217720 kb
Host smart-85844292-b75d-4a6f-a386-03db835d2914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804219652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3804219652
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.618679488
Short name T862
Test name
Test status
Simulation time 33673583 ps
CPU time 1.28 seconds
Started Jun 29 05:33:45 PM PDT 24
Finished Jun 29 05:33:48 PM PDT 24
Peak memory 220240 kb
Host smart-351a3ca4-4236-48a4-afde-34f8faed122f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618679488 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.618679488
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.1687241041
Short name T722
Test name
Test status
Simulation time 34549352 ps
CPU time 1.3 seconds
Started Jun 29 05:33:43 PM PDT 24
Finished Jun 29 05:33:46 PM PDT 24
Peak memory 217496 kb
Host smart-a5422d42-5f74-4c7d-a7d0-4952269ed892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687241041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1687241041
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2880480259
Short name T915
Test name
Test status
Simulation time 27247779 ps
CPU time 1.21 seconds
Started Jun 29 05:33:42 PM PDT 24
Finished Jun 29 05:33:45 PM PDT 24
Peak memory 220260 kb
Host smart-692d2c56-924d-4f35-be2b-012a5b927c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880480259 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2880480259
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.1631927298
Short name T923
Test name
Test status
Simulation time 52443193 ps
CPU time 1.54 seconds
Started Jun 29 05:33:34 PM PDT 24
Finished Jun 29 05:33:37 PM PDT 24
Peak memory 218668 kb
Host smart-d82261eb-89dd-411f-8b5d-c30454cb2211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631927298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1631927298
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.1923199318
Short name T561
Test name
Test status
Simulation time 102824569 ps
CPU time 1.17 seconds
Started Jun 29 05:33:41 PM PDT 24
Finished Jun 29 05:33:44 PM PDT 24
Peak memory 220120 kb
Host smart-fae1f71b-5451-4872-9f26-01f14ab58427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923199318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.1923199318
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1573898425
Short name T615
Test name
Test status
Simulation time 64848243 ps
CPU time 1.39 seconds
Started Jun 29 05:33:37 PM PDT 24
Finished Jun 29 05:33:39 PM PDT 24
Peak memory 218684 kb
Host smart-7619c3df-b45f-4d8f-b2ef-abbaa533f54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573898425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1573898425
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.3689763757
Short name T291
Test name
Test status
Simulation time 263881833 ps
CPU time 1.2 seconds
Started Jun 29 05:33:33 PM PDT 24
Finished Jun 29 05:33:35 PM PDT 24
Peak memory 218696 kb
Host smart-afdda250-217c-4cc6-9817-aa4555a74e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689763757 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.3689763757
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.1875528985
Short name T447
Test name
Test status
Simulation time 68141870 ps
CPU time 1.16 seconds
Started Jun 29 05:33:41 PM PDT 24
Finished Jun 29 05:33:44 PM PDT 24
Peak memory 217616 kb
Host smart-567b12e6-d44b-47a7-a14a-d51b74bb8e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875528985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1875528985
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.2604129214
Short name T904
Test name
Test status
Simulation time 71397423 ps
CPU time 1.13 seconds
Started Jun 29 05:33:41 PM PDT 24
Finished Jun 29 05:33:44 PM PDT 24
Peak memory 220004 kb
Host smart-c3594432-e423-48b0-88a7-24fb44053fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604129214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.2604129214
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.2650643734
Short name T840
Test name
Test status
Simulation time 67510630 ps
CPU time 1.38 seconds
Started Jun 29 05:33:34 PM PDT 24
Finished Jun 29 05:33:36 PM PDT 24
Peak memory 219196 kb
Host smart-5fa6c134-6655-425e-8a58-83ef13a9a7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650643734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2650643734
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.703066245
Short name T259
Test name
Test status
Simulation time 49561819 ps
CPU time 1.35 seconds
Started Jun 29 05:33:36 PM PDT 24
Finished Jun 29 05:33:38 PM PDT 24
Peak memory 216236 kb
Host smart-e1c74caa-e8ee-47c0-ade2-8268fb0b7e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703066245 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.703066245
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.3560615859
Short name T394
Test name
Test status
Simulation time 85800646 ps
CPU time 2.69 seconds
Started Jun 29 05:33:36 PM PDT 24
Finished Jun 29 05:33:39 PM PDT 24
Peak memory 220500 kb
Host smart-cf934e16-5d65-4f42-9237-81b34b4c7116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560615859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3560615859
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.3586507971
Short name T945
Test name
Test status
Simulation time 29287861 ps
CPU time 1.33 seconds
Started Jun 29 05:33:39 PM PDT 24
Finished Jun 29 05:33:41 PM PDT 24
Peak memory 221136 kb
Host smart-40163ed8-eef2-42f8-aa5a-de4d5289ef7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586507971 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.3586507971
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.1828771791
Short name T843
Test name
Test status
Simulation time 42588281 ps
CPU time 1.71 seconds
Started Jun 29 05:33:45 PM PDT 24
Finished Jun 29 05:33:49 PM PDT 24
Peak memory 217692 kb
Host smart-ae39b213-b95f-48f4-a592-9b113088bcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828771791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1828771791
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2683629530
Short name T223
Test name
Test status
Simulation time 46146571 ps
CPU time 1.2 seconds
Started Jun 29 05:32:33 PM PDT 24
Finished Jun 29 05:32:35 PM PDT 24
Peak memory 219016 kb
Host smart-11241653-6290-4be8-b49f-235819f8bde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683629530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2683629530
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.1011620576
Short name T922
Test name
Test status
Simulation time 17881437 ps
CPU time 1.02 seconds
Started Jun 29 05:32:29 PM PDT 24
Finished Jun 29 05:32:31 PM PDT 24
Peak memory 207008 kb
Host smart-03bb3c8a-1e27-4009-8a50-556db715aad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011620576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1011620576
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3397108332
Short name T824
Test name
Test status
Simulation time 55705747 ps
CPU time 0.88 seconds
Started Jun 29 05:32:09 PM PDT 24
Finished Jun 29 05:32:10 PM PDT 24
Peak memory 216468 kb
Host smart-e2be8260-f3ac-4837-8c8d-73bbf0ec5c91
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397108332 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3397108332
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2396725122
Short name T755
Test name
Test status
Simulation time 63618679 ps
CPU time 1.18 seconds
Started Jun 29 05:32:12 PM PDT 24
Finished Jun 29 05:32:15 PM PDT 24
Peak memory 217228 kb
Host smart-86f3e282-3930-4439-b409-948ffff81157
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396725122 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2396725122
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.2678354526
Short name T539
Test name
Test status
Simulation time 28323740 ps
CPU time 0.97 seconds
Started Jun 29 05:32:12 PM PDT 24
Finished Jun 29 05:32:14 PM PDT 24
Peak memory 219796 kb
Host smart-4e514346-6a63-4757-b89c-cba03674dbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678354526 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2678354526
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2346278735
Short name T40
Test name
Test status
Simulation time 99587819 ps
CPU time 1.3 seconds
Started Jun 29 05:32:15 PM PDT 24
Finished Jun 29 05:32:17 PM PDT 24
Peak memory 215616 kb
Host smart-2fd7db5e-f8b1-4f1c-8fb2-ca90806e2dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346278735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2346278735
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.4100289071
Short name T780
Test name
Test status
Simulation time 54337748 ps
CPU time 1 seconds
Started Jun 29 05:32:09 PM PDT 24
Finished Jun 29 05:32:11 PM PDT 24
Peak memory 224104 kb
Host smart-1a097c85-9d53-4e81-a73c-0f4f81979ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100289071 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.4100289071
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1368860218
Short name T419
Test name
Test status
Simulation time 24147692 ps
CPU time 0.97 seconds
Started Jun 29 05:32:11 PM PDT 24
Finished Jun 29 05:32:14 PM PDT 24
Peak memory 215620 kb
Host smart-01ef42c9-c25c-47f1-8081-3cce91fb23b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368860218 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1368860218
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1189262825
Short name T360
Test name
Test status
Simulation time 633171086 ps
CPU time 6.11 seconds
Started Jun 29 05:32:11 PM PDT 24
Finished Jun 29 05:32:19 PM PDT 24
Peak memory 217620 kb
Host smart-35e9ff41-3449-421d-a9eb-083e3e5f5de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189262825 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1189262825
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3384923969
Short name T468
Test name
Test status
Simulation time 187715414105 ps
CPU time 1189.37 seconds
Started Jun 29 05:32:12 PM PDT 24
Finished Jun 29 05:52:03 PM PDT 24
Peak memory 225416 kb
Host smart-42723dee-722f-4dd8-a6fb-7e103ad9a5c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384923969 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3384923969
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.4071514255
Short name T139
Test name
Test status
Simulation time 27114086 ps
CPU time 1.25 seconds
Started Jun 29 05:33:41 PM PDT 24
Finished Jun 29 05:33:43 PM PDT 24
Peak memory 220012 kb
Host smart-2e1312ee-c3b7-4c84-adcc-d5693f468a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071514255 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.4071514255
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.1149565001
Short name T523
Test name
Test status
Simulation time 73426982 ps
CPU time 1.17 seconds
Started Jun 29 05:33:45 PM PDT 24
Finished Jun 29 05:33:48 PM PDT 24
Peak memory 217708 kb
Host smart-7cdee735-33bb-48e3-85d6-237d19bbe6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149565001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1149565001
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.4031845271
Short name T522
Test name
Test status
Simulation time 82687196 ps
CPU time 1.11 seconds
Started Jun 29 05:33:42 PM PDT 24
Finished Jun 29 05:33:45 PM PDT 24
Peak memory 219812 kb
Host smart-488293b7-8f47-4acd-abaf-ebdd4370cf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031845271 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.4031845271
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.1735680388
Short name T346
Test name
Test status
Simulation time 224160593 ps
CPU time 2.83 seconds
Started Jun 29 05:33:32 PM PDT 24
Finished Jun 29 05:33:37 PM PDT 24
Peak memory 220536 kb
Host smart-e6f6da27-77b1-43d3-b19a-1856ff969cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735680388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1735680388
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1660633958
Short name T487
Test name
Test status
Simulation time 72249023 ps
CPU time 1.15 seconds
Started Jun 29 05:33:47 PM PDT 24
Finished Jun 29 05:33:50 PM PDT 24
Peak memory 220104 kb
Host smart-ec873a6c-fe98-4d2a-a307-5589307e9cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660633958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1660633958
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.1711605169
Short name T422
Test name
Test status
Simulation time 47488020 ps
CPU time 1.54 seconds
Started Jun 29 05:33:42 PM PDT 24
Finished Jun 29 05:33:45 PM PDT 24
Peak memory 218648 kb
Host smart-f0cab0a8-2c50-46a7-b7c0-0cf4c8190aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711605169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1711605169
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.3520536269
Short name T316
Test name
Test status
Simulation time 75554475 ps
CPU time 1.12 seconds
Started Jun 29 05:33:44 PM PDT 24
Finished Jun 29 05:33:48 PM PDT 24
Peak memory 219904 kb
Host smart-ceed9006-989b-48c3-ac17-4b12752691ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520536269 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3520536269
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.2481734694
Short name T383
Test name
Test status
Simulation time 44534722 ps
CPU time 1.14 seconds
Started Jun 29 05:33:54 PM PDT 24
Finished Jun 29 05:33:55 PM PDT 24
Peak memory 217692 kb
Host smart-448c4738-257d-4e2e-84db-2294ed6ea957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481734694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2481734694
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.2791669914
Short name T292
Test name
Test status
Simulation time 26498258 ps
CPU time 1.22 seconds
Started Jun 29 05:33:59 PM PDT 24
Finished Jun 29 05:34:01 PM PDT 24
Peak memory 219840 kb
Host smart-b4c94cc7-1a33-4400-8cd9-3c67d2481fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791669914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.2791669914
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.2099206456
Short name T369
Test name
Test status
Simulation time 54167374 ps
CPU time 1.03 seconds
Started Jun 29 05:33:45 PM PDT 24
Finished Jun 29 05:33:49 PM PDT 24
Peak memory 217852 kb
Host smart-a8007a77-e0ed-4769-ae43-c027477b9a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099206456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2099206456
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.2344735995
Short name T949
Test name
Test status
Simulation time 23917273 ps
CPU time 1.29 seconds
Started Jun 29 05:33:52 PM PDT 24
Finished Jun 29 05:33:54 PM PDT 24
Peak memory 220164 kb
Host smart-2aa691d8-74a9-4d14-ab8f-b8383db0fe48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344735995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.2344735995
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.4062238507
Short name T417
Test name
Test status
Simulation time 81619408 ps
CPU time 1.56 seconds
Started Jun 29 05:33:42 PM PDT 24
Finished Jun 29 05:33:45 PM PDT 24
Peak memory 219196 kb
Host smart-f5ff9c53-cf6d-4c94-a27f-3afa6b5c5d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062238507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.4062238507
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.98658446
Short name T534
Test name
Test status
Simulation time 126454892 ps
CPU time 1.22 seconds
Started Jun 29 05:33:45 PM PDT 24
Finished Jun 29 05:33:49 PM PDT 24
Peak memory 220572 kb
Host smart-71254e93-068e-44be-bd6c-f09ff8f927ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98658446 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.98658446
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.604954327
Short name T473
Test name
Test status
Simulation time 72704526 ps
CPU time 1.1 seconds
Started Jun 29 05:33:47 PM PDT 24
Finished Jun 29 05:33:50 PM PDT 24
Peak memory 217664 kb
Host smart-e0c51ec5-a25a-4e10-a7d2-1f076085aed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604954327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.604954327
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.3064757500
Short name T224
Test name
Test status
Simulation time 119298249 ps
CPU time 1.31 seconds
Started Jun 29 05:33:40 PM PDT 24
Finished Jun 29 05:33:43 PM PDT 24
Peak memory 220636 kb
Host smart-9e46ae00-10c0-4e85-9837-ed5cfdb0aec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064757500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.3064757500
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.2425348481
Short name T766
Test name
Test status
Simulation time 81995701 ps
CPU time 1.23 seconds
Started Jun 29 05:33:40 PM PDT 24
Finished Jun 29 05:33:41 PM PDT 24
Peak memory 217592 kb
Host smart-49103db2-9c99-4f24-8094-a68bc344e6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425348481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2425348481
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.2923871211
Short name T218
Test name
Test status
Simulation time 81609256 ps
CPU time 1.15 seconds
Started Jun 29 05:33:49 PM PDT 24
Finished Jun 29 05:33:51 PM PDT 24
Peak memory 218992 kb
Host smart-dfeef070-a18f-41a1-840d-34fbf3cfdea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923871211 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.2923871211
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.1044905003
Short name T597
Test name
Test status
Simulation time 79342054 ps
CPU time 2.76 seconds
Started Jun 29 05:34:00 PM PDT 24
Finished Jun 29 05:34:08 PM PDT 24
Peak memory 219184 kb
Host smart-46dbd95c-ca5e-4a30-9fa2-059e28b44298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044905003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1044905003
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.3241635815
Short name T695
Test name
Test status
Simulation time 29763508 ps
CPU time 1.3 seconds
Started Jun 29 05:33:45 PM PDT 24
Finished Jun 29 05:33:49 PM PDT 24
Peak memory 220180 kb
Host smart-5cc3c14c-5597-439a-a258-f805f030b9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241635815 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.3241635815
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.352291003
Short name T14
Test name
Test status
Simulation time 107277415 ps
CPU time 1.18 seconds
Started Jun 29 05:33:44 PM PDT 24
Finished Jun 29 05:33:47 PM PDT 24
Peak memory 219776 kb
Host smart-6b5a35f2-48f7-4e33-99db-23332db9db3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352291003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.352291003
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1472505344
Short name T90
Test name
Test status
Simulation time 45070384 ps
CPU time 1.31 seconds
Started Jun 29 05:32:11 PM PDT 24
Finished Jun 29 05:32:14 PM PDT 24
Peak memory 219724 kb
Host smart-e86c60e6-0887-48e0-9935-d845c86ceec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472505344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1472505344
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.52295643
Short name T886
Test name
Test status
Simulation time 69187339 ps
CPU time 0.96 seconds
Started Jun 29 05:32:11 PM PDT 24
Finished Jun 29 05:32:14 PM PDT 24
Peak memory 207052 kb
Host smart-943e5970-7285-4dd2-b53b-722363b081a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52295643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.52295643
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2616001248
Short name T869
Test name
Test status
Simulation time 14027184 ps
CPU time 0.96 seconds
Started Jun 29 05:32:12 PM PDT 24
Finished Jun 29 05:32:14 PM PDT 24
Peak memory 216424 kb
Host smart-3214cf2a-19d9-4e27-9c3c-db4dcaae5da3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616001248 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2616001248
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2190055139
Short name T833
Test name
Test status
Simulation time 47659088 ps
CPU time 1.05 seconds
Started Jun 29 05:32:19 PM PDT 24
Finished Jun 29 05:32:20 PM PDT 24
Peak memory 218584 kb
Host smart-c9036967-d064-4200-9dac-7db896ba32c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190055139 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2190055139
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1916354562
Short name T646
Test name
Test status
Simulation time 35092503 ps
CPU time 0.97 seconds
Started Jun 29 05:32:11 PM PDT 24
Finished Jun 29 05:32:14 PM PDT 24
Peak memory 219680 kb
Host smart-bbc1f79d-f93c-413b-a4ba-ae159d474c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916354562 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1916354562
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.147592538
Short name T382
Test name
Test status
Simulation time 97631807 ps
CPU time 1.56 seconds
Started Jun 29 05:32:13 PM PDT 24
Finished Jun 29 05:32:15 PM PDT 24
Peak memory 219064 kb
Host smart-221abbfc-3fec-4003-b985-4ac8f39000e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147592538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.147592538
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.3993363384
Short name T533
Test name
Test status
Simulation time 25370122 ps
CPU time 0.95 seconds
Started Jun 29 05:32:11 PM PDT 24
Finished Jun 29 05:32:13 PM PDT 24
Peak memory 215840 kb
Host smart-295d8149-09b3-4d0c-a450-675fd2622624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993363384 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3993363384
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2251643180
Short name T413
Test name
Test status
Simulation time 14860794 ps
CPU time 0.97 seconds
Started Jun 29 05:32:11 PM PDT 24
Finished Jun 29 05:32:14 PM PDT 24
Peak memory 215564 kb
Host smart-414e8bbf-94bb-4a80-962b-3423d5bdabd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251643180 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2251643180
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1882983352
Short name T411
Test name
Test status
Simulation time 554750191 ps
CPU time 2.49 seconds
Started Jun 29 05:32:08 PM PDT 24
Finished Jun 29 05:32:11 PM PDT 24
Peak memory 217728 kb
Host smart-0a99d1ce-07c3-4560-b4c5-38446086481c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882983352 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1882983352
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3129823332
Short name T948
Test name
Test status
Simulation time 18162905642 ps
CPU time 225.21 seconds
Started Jun 29 05:32:11 PM PDT 24
Finished Jun 29 05:35:58 PM PDT 24
Peak memory 219628 kb
Host smart-7cf5bb7e-04ac-406f-aacd-cb99c5430c58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129823332 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3129823332
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.2418268070
Short name T167
Test name
Test status
Simulation time 29242006 ps
CPU time 1.23 seconds
Started Jun 29 05:33:46 PM PDT 24
Finished Jun 29 05:33:50 PM PDT 24
Peak memory 219880 kb
Host smart-5358b43c-0598-4954-9a2a-e47b20c81972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418268070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.2418268070
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.3343907521
Short name T676
Test name
Test status
Simulation time 80668711 ps
CPU time 1.18 seconds
Started Jun 29 05:33:46 PM PDT 24
Finished Jun 29 05:33:49 PM PDT 24
Peak memory 217500 kb
Host smart-ca13e9f5-aa79-4b49-9a9a-223da8349188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343907521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3343907521
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.1475965866
Short name T107
Test name
Test status
Simulation time 98928585 ps
CPU time 1.33 seconds
Started Jun 29 05:33:45 PM PDT 24
Finished Jun 29 05:33:49 PM PDT 24
Peak memory 215996 kb
Host smart-54a6c97f-c70d-4479-ad09-3d8bca7115ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475965866 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.1475965866
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.4141523165
Short name T933
Test name
Test status
Simulation time 31937014 ps
CPU time 1.13 seconds
Started Jun 29 05:33:50 PM PDT 24
Finished Jun 29 05:33:52 PM PDT 24
Peak memory 220224 kb
Host smart-55bcfdc0-c01e-4210-aec5-6dc15463dca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141523165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.4141523165
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.4124938233
Short name T960
Test name
Test status
Simulation time 28139462 ps
CPU time 1.23 seconds
Started Jun 29 05:34:01 PM PDT 24
Finished Jun 29 05:34:03 PM PDT 24
Peak memory 218696 kb
Host smart-fd89bf9d-a2ca-4673-9f6f-29aaac4b8c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124938233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.4124938233
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/183.edn_alert.2654317859
Short name T587
Test name
Test status
Simulation time 307349677 ps
CPU time 1.27 seconds
Started Jun 29 05:33:44 PM PDT 24
Finished Jun 29 05:33:48 PM PDT 24
Peak memory 221032 kb
Host smart-0b4a4e75-546b-43fe-b234-1a42d4d527f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654317859 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.2654317859
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.2534361747
Short name T348
Test name
Test status
Simulation time 131698950 ps
CPU time 1.14 seconds
Started Jun 29 05:33:43 PM PDT 24
Finished Jun 29 05:33:46 PM PDT 24
Peak memory 217488 kb
Host smart-6f663345-0d26-4c8b-ba6c-223c9ceec885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534361747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2534361747
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.2102976387
Short name T503
Test name
Test status
Simulation time 50603389 ps
CPU time 1.27 seconds
Started Jun 29 05:33:44 PM PDT 24
Finished Jun 29 05:33:47 PM PDT 24
Peak memory 215944 kb
Host smart-5d3b3c4c-3749-4fa1-aed0-b4d74b863baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102976387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.2102976387
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.3577785428
Short name T438
Test name
Test status
Simulation time 63949580 ps
CPU time 1.05 seconds
Started Jun 29 05:34:00 PM PDT 24
Finished Jun 29 05:34:02 PM PDT 24
Peak memory 217552 kb
Host smart-c1a1291f-d1bf-4446-8080-c765da0c991c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577785428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3577785428
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.1395215210
Short name T403
Test name
Test status
Simulation time 84999729 ps
CPU time 1.46 seconds
Started Jun 29 05:33:44 PM PDT 24
Finished Jun 29 05:33:48 PM PDT 24
Peak memory 219096 kb
Host smart-34f23ce9-274b-4fb3-9f4b-fbe7bced2a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395215210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1395215210
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.1672894420
Short name T554
Test name
Test status
Simulation time 26988561 ps
CPU time 1.29 seconds
Started Jun 29 05:33:56 PM PDT 24
Finished Jun 29 05:33:57 PM PDT 24
Peak memory 219496 kb
Host smart-c56c2c46-bdf6-4dcd-9739-2a8c01e1c94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672894420 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.1672894420
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.4263772231
Short name T465
Test name
Test status
Simulation time 56811921 ps
CPU time 1.72 seconds
Started Jun 29 05:33:44 PM PDT 24
Finished Jun 29 05:33:48 PM PDT 24
Peak memory 215536 kb
Host smart-14fd4667-41d2-407b-ada3-3588071d37c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263772231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.4263772231
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.776391900
Short name T496
Test name
Test status
Simulation time 62443942 ps
CPU time 1.03 seconds
Started Jun 29 05:33:48 PM PDT 24
Finished Jun 29 05:33:51 PM PDT 24
Peak memory 219000 kb
Host smart-b2345e1b-ce5d-4aa3-a3f3-c31e4175b51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776391900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.776391900
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.2864075438
Short name T734
Test name
Test status
Simulation time 76339010 ps
CPU time 1.11 seconds
Started Jun 29 05:33:45 PM PDT 24
Finished Jun 29 05:33:48 PM PDT 24
Peak memory 218872 kb
Host smart-7329bc3e-c274-4956-b032-af6a95a06a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864075438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2864075438
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.2956346705
Short name T179
Test name
Test status
Simulation time 60765700 ps
CPU time 1.1 seconds
Started Jun 29 05:33:46 PM PDT 24
Finished Jun 29 05:33:50 PM PDT 24
Peak memory 218888 kb
Host smart-dc30e33f-4f53-4489-b485-68cd4f972d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956346705 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2956346705
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.3064621908
Short name T914
Test name
Test status
Simulation time 36434646 ps
CPU time 1.49 seconds
Started Jun 29 05:33:48 PM PDT 24
Finished Jun 29 05:33:51 PM PDT 24
Peak memory 218732 kb
Host smart-9886719c-6624-4769-9b4f-64afcac1d3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064621908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3064621908
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.2282296133
Short name T311
Test name
Test status
Simulation time 40920230 ps
CPU time 1.2 seconds
Started Jun 29 05:33:46 PM PDT 24
Finished Jun 29 05:33:49 PM PDT 24
Peak memory 221388 kb
Host smart-8149c82d-9d9c-4b05-8418-ec43dfc03318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282296133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2282296133
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.43934116
Short name T644
Test name
Test status
Simulation time 113500770 ps
CPU time 1 seconds
Started Jun 29 05:33:45 PM PDT 24
Finished Jun 29 05:33:49 PM PDT 24
Peak memory 217612 kb
Host smart-a6c24159-35a7-4cb4-a33e-00eac1a34679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43934116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.43934116
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1394517250
Short name T543
Test name
Test status
Simulation time 24004817 ps
CPU time 1.13 seconds
Started Jun 29 05:32:33 PM PDT 24
Finished Jun 29 05:32:35 PM PDT 24
Peak memory 218644 kb
Host smart-a78a640f-ed06-41ee-8f85-119da72134a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394517250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1394517250
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3707260919
Short name T674
Test name
Test status
Simulation time 27490697 ps
CPU time 0.84 seconds
Started Jun 29 05:32:13 PM PDT 24
Finished Jun 29 05:32:15 PM PDT 24
Peak memory 206304 kb
Host smart-5717f9a2-33ee-49bc-87e0-e5d9cc486cb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707260919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3707260919
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1759227310
Short name T808
Test name
Test status
Simulation time 26883588 ps
CPU time 0.82 seconds
Started Jun 29 05:32:09 PM PDT 24
Finished Jun 29 05:32:11 PM PDT 24
Peak memory 216652 kb
Host smart-534e8dd0-1a1b-4b51-922d-fca2b5b5f929
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759227310 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1759227310
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.4119236412
Short name T961
Test name
Test status
Simulation time 81259529 ps
CPU time 1.1 seconds
Started Jun 29 05:32:11 PM PDT 24
Finished Jun 29 05:32:14 PM PDT 24
Peak memory 217028 kb
Host smart-c2139153-1d40-4097-894b-7de9671a3c63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119236412 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.4119236412
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.811948634
Short name T958
Test name
Test status
Simulation time 29673866 ps
CPU time 1.43 seconds
Started Jun 29 05:32:13 PM PDT 24
Finished Jun 29 05:32:16 PM PDT 24
Peak memory 225964 kb
Host smart-ddddda5c-c4ef-4992-aa0c-a9add5458ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811948634 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.811948634
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.233219115
Short name T87
Test name
Test status
Simulation time 104392641 ps
CPU time 1.46 seconds
Started Jun 29 05:32:10 PM PDT 24
Finished Jun 29 05:32:13 PM PDT 24
Peak memory 219216 kb
Host smart-766c8fb6-b121-4990-ae99-1c22a78df73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233219115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.233219115
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2685819157
Short name T972
Test name
Test status
Simulation time 59617853 ps
CPU time 0.86 seconds
Started Jun 29 05:32:10 PM PDT 24
Finished Jun 29 05:32:13 PM PDT 24
Peak memory 215524 kb
Host smart-0335477f-6132-450c-8605-382e8c4cf053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685819157 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2685819157
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3349156427
Short name T685
Test name
Test status
Simulation time 16450740 ps
CPU time 1 seconds
Started Jun 29 05:32:13 PM PDT 24
Finished Jun 29 05:32:15 PM PDT 24
Peak memory 215564 kb
Host smart-0fa0dce1-b9cd-4f00-8a09-58740327b102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349156427 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3349156427
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3401357561
Short name T453
Test name
Test status
Simulation time 195074409 ps
CPU time 4.15 seconds
Started Jun 29 05:32:10 PM PDT 24
Finished Jun 29 05:32:15 PM PDT 24
Peak memory 217556 kb
Host smart-e862666b-62f8-4fef-bd44-87153d9cdf14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401357561 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3401357561
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/190.edn_alert.1815228405
Short name T942
Test name
Test status
Simulation time 93365935 ps
CPU time 1.26 seconds
Started Jun 29 05:33:50 PM PDT 24
Finished Jun 29 05:33:52 PM PDT 24
Peak memory 220016 kb
Host smart-fdbc72c4-6eac-462e-93a6-0e162650cf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815228405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.1815228405
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3884407355
Short name T252
Test name
Test status
Simulation time 45549230 ps
CPU time 1.73 seconds
Started Jun 29 05:33:45 PM PDT 24
Finished Jun 29 05:33:49 PM PDT 24
Peak memory 218888 kb
Host smart-e57e2539-6dfd-4692-aa81-5a5a0632e225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884407355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3884407355
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.3039578067
Short name T667
Test name
Test status
Simulation time 69829942 ps
CPU time 1.14 seconds
Started Jun 29 05:33:51 PM PDT 24
Finished Jun 29 05:33:53 PM PDT 24
Peak memory 219228 kb
Host smart-3ea1c6b5-b93b-4fc3-a4da-2a5161081f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039578067 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.3039578067
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.891451729
Short name T705
Test name
Test status
Simulation time 24792923 ps
CPU time 1.19 seconds
Started Jun 29 05:33:46 PM PDT 24
Finished Jun 29 05:33:49 PM PDT 24
Peak memory 217772 kb
Host smart-b12e15fe-feec-4567-bfd8-47fd1b5adc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891451729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.891451729
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.2270593630
Short name T617
Test name
Test status
Simulation time 29168931 ps
CPU time 1.24 seconds
Started Jun 29 05:33:48 PM PDT 24
Finished Jun 29 05:33:51 PM PDT 24
Peak memory 218912 kb
Host smart-ad6e4a92-c088-4f0c-bbc3-eabda7c0fd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270593630 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2270593630
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.2622631580
Short name T823
Test name
Test status
Simulation time 29041211 ps
CPU time 1.32 seconds
Started Jun 29 05:34:02 PM PDT 24
Finished Jun 29 05:34:04 PM PDT 24
Peak memory 217692 kb
Host smart-bfbdd502-d148-4049-ac72-5942a56ec731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622631580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2622631580
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.757588098
Short name T786
Test name
Test status
Simulation time 34346437 ps
CPU time 1.09 seconds
Started Jun 29 05:33:45 PM PDT 24
Finished Jun 29 05:33:49 PM PDT 24
Peak memory 218840 kb
Host smart-d91c4098-af5b-424c-ad85-3657c54e0bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757588098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.757588098
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/194.edn_alert.248603383
Short name T262
Test name
Test status
Simulation time 74581314 ps
CPU time 1.04 seconds
Started Jun 29 05:33:51 PM PDT 24
Finished Jun 29 05:33:53 PM PDT 24
Peak memory 218860 kb
Host smart-a587bd27-18e9-4245-a4fb-c240e9d89f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248603383 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.248603383
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.3128018838
Short name T782
Test name
Test status
Simulation time 63477722 ps
CPU time 1.4 seconds
Started Jun 29 05:33:51 PM PDT 24
Finished Jun 29 05:33:53 PM PDT 24
Peak memory 218724 kb
Host smart-3dcd9488-f369-4c74-a73f-33028121f4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128018838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3128018838
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.2665277122
Short name T955
Test name
Test status
Simulation time 236373258 ps
CPU time 1.38 seconds
Started Jun 29 05:33:58 PM PDT 24
Finished Jun 29 05:34:00 PM PDT 24
Peak memory 222020 kb
Host smart-c2228633-92f9-407f-b68b-70bc00c7b8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665277122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2665277122
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.3465586214
Short name T568
Test name
Test status
Simulation time 80568026 ps
CPU time 1.53 seconds
Started Jun 29 05:33:46 PM PDT 24
Finished Jun 29 05:33:50 PM PDT 24
Peak memory 217732 kb
Host smart-c66f124c-519e-498c-bc65-a7da0885ddee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465586214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3465586214
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.3760019903
Short name T556
Test name
Test status
Simulation time 306752265 ps
CPU time 1.36 seconds
Started Jun 29 05:33:58 PM PDT 24
Finished Jun 29 05:34:00 PM PDT 24
Peak memory 220040 kb
Host smart-85c06b1d-da19-4520-b0fc-527be2a04504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760019903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.3760019903
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.2319951746
Short name T441
Test name
Test status
Simulation time 148721864 ps
CPU time 3.19 seconds
Started Jun 29 05:33:45 PM PDT 24
Finished Jun 29 05:33:50 PM PDT 24
Peak memory 220256 kb
Host smart-d7d4ac2c-5456-47d1-a9c9-a2916e6925eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319951746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2319951746
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.3892359873
Short name T151
Test name
Test status
Simulation time 65969933 ps
CPU time 1.22 seconds
Started Jun 29 05:33:52 PM PDT 24
Finished Jun 29 05:33:54 PM PDT 24
Peak memory 218992 kb
Host smart-a1af4932-5aa2-4b74-aea6-19043c6e2b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892359873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3892359873
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.3743900517
Short name T301
Test name
Test status
Simulation time 66821378 ps
CPU time 1.38 seconds
Started Jun 29 05:33:45 PM PDT 24
Finished Jun 29 05:33:48 PM PDT 24
Peak memory 218776 kb
Host smart-bcc7e5b1-1871-4f46-b995-1bb5663e1bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743900517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3743900517
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.2633287804
Short name T314
Test name
Test status
Simulation time 42708522 ps
CPU time 1.16 seconds
Started Jun 29 05:33:52 PM PDT 24
Finished Jun 29 05:33:54 PM PDT 24
Peak memory 219956 kb
Host smart-46e1cb3e-9aff-485e-834b-a48296a1ec1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633287804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.2633287804
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.843974032
Short name T847
Test name
Test status
Simulation time 27689588 ps
CPU time 1.21 seconds
Started Jun 29 05:33:48 PM PDT 24
Finished Jun 29 05:33:51 PM PDT 24
Peak memory 217664 kb
Host smart-a58d8374-1801-40ae-8825-ae1d6b7a67e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843974032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.843974032
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.2815622963
Short name T821
Test name
Test status
Simulation time 32478296 ps
CPU time 1.4 seconds
Started Jun 29 05:33:52 PM PDT 24
Finished Jun 29 05:33:54 PM PDT 24
Peak memory 215984 kb
Host smart-e47ae987-b875-4e73-8511-42ea118d595f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815622963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.2815622963
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.2484110683
Short name T665
Test name
Test status
Simulation time 24492021 ps
CPU time 1.19 seconds
Started Jun 29 05:33:59 PM PDT 24
Finished Jun 29 05:34:01 PM PDT 24
Peak memory 217660 kb
Host smart-6d0ac5a6-3c97-428c-8501-7e56f059f015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484110683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2484110683
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3982032247
Short name T372
Test name
Test status
Simulation time 25156063 ps
CPU time 1.21 seconds
Started Jun 29 05:31:51 PM PDT 24
Finished Jun 29 05:31:52 PM PDT 24
Peak memory 218984 kb
Host smart-e81770f0-939c-4fc8-aa4e-23241989c547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982032247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3982032247
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.4141801904
Short name T689
Test name
Test status
Simulation time 22213578 ps
CPU time 1.12 seconds
Started Jun 29 05:31:39 PM PDT 24
Finished Jun 29 05:31:41 PM PDT 24
Peak memory 215328 kb
Host smart-bc3faee6-9dd9-462c-9af1-77be5ea22e7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141801904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.4141801904
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2803614795
Short name T362
Test name
Test status
Simulation time 20592967 ps
CPU time 0.9 seconds
Started Jun 29 05:31:48 PM PDT 24
Finished Jun 29 05:31:50 PM PDT 24
Peak memory 216240 kb
Host smart-cade4688-fdc9-444d-80df-1851cd25c16f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803614795 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2803614795
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.1902715334
Short name T805
Test name
Test status
Simulation time 27679747 ps
CPU time 0.97 seconds
Started Jun 29 05:31:46 PM PDT 24
Finished Jun 29 05:31:48 PM PDT 24
Peak memory 218488 kb
Host smart-a9eb6cf5-f75c-4ac1-848e-71dae27cb9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902715334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1902715334
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.988584693
Short name T858
Test name
Test status
Simulation time 121857670 ps
CPU time 1.72 seconds
Started Jun 29 05:31:40 PM PDT 24
Finished Jun 29 05:31:42 PM PDT 24
Peak memory 219240 kb
Host smart-9d12cca0-8ad1-4b17-870f-8382dada5458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988584693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.988584693
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2903073081
Short name T414
Test name
Test status
Simulation time 40133172 ps
CPU time 0.94 seconds
Started Jun 29 05:31:40 PM PDT 24
Finished Jun 29 05:31:42 PM PDT 24
Peak memory 215824 kb
Host smart-9b2003c8-97d9-41b7-a58f-ca7d51c6e189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903073081 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2903073081
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.693217409
Short name T711
Test name
Test status
Simulation time 48659411 ps
CPU time 0.92 seconds
Started Jun 29 05:31:54 PM PDT 24
Finished Jun 29 05:31:56 PM PDT 24
Peak memory 207352 kb
Host smart-a4b672c1-0d32-4138-a8d9-c8e894367df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693217409 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.693217409
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1898916989
Short name T65
Test name
Test status
Simulation time 2158831904 ps
CPU time 4.27 seconds
Started Jun 29 05:31:39 PM PDT 24
Finished Jun 29 05:31:44 PM PDT 24
Peak memory 235784 kb
Host smart-21557147-8480-4369-8bbd-6f3a3a4e6a13
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898916989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1898916989
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.583497
Short name T514
Test name
Test status
Simulation time 24252525 ps
CPU time 0.93 seconds
Started Jun 29 05:31:45 PM PDT 24
Finished Jun 29 05:31:47 PM PDT 24
Peak memory 215552 kb
Host smart-63a3530e-ebc5-450e-aab3-ac6bee4bd98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583497 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.583497
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1393306428
Short name T497
Test name
Test status
Simulation time 373406104 ps
CPU time 2.4 seconds
Started Jun 29 05:31:50 PM PDT 24
Finished Jun 29 05:31:53 PM PDT 24
Peak memory 217764 kb
Host smart-b89989cb-53ea-4f55-9d1b-cc4dab46fbe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393306428 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1393306428
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_alert.2642747536
Short name T723
Test name
Test status
Simulation time 32615228 ps
CPU time 1.32 seconds
Started Jun 29 05:32:29 PM PDT 24
Finished Jun 29 05:32:31 PM PDT 24
Peak memory 220868 kb
Host smart-7c5154b8-3a21-495f-95e6-014329a7d9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642747536 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2642747536
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1181682576
Short name T841
Test name
Test status
Simulation time 19282145 ps
CPU time 1.01 seconds
Started Jun 29 05:32:27 PM PDT 24
Finished Jun 29 05:32:29 PM PDT 24
Peak memory 215180 kb
Host smart-bba93736-6cb4-44b9-818e-cdb6c8c16470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181682576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1181682576
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1273352594
Short name T391
Test name
Test status
Simulation time 33318489 ps
CPU time 0.88 seconds
Started Jun 29 05:32:39 PM PDT 24
Finished Jun 29 05:32:42 PM PDT 24
Peak memory 216240 kb
Host smart-0f3966ac-52ea-4c62-9694-459d79c34de0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273352594 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1273352594
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.4274260535
Short name T836
Test name
Test status
Simulation time 55008669 ps
CPU time 1.17 seconds
Started Jun 29 05:32:25 PM PDT 24
Finished Jun 29 05:32:27 PM PDT 24
Peak memory 217164 kb
Host smart-5f3a2dc1-fb92-450c-b06a-af2f27e1fe97
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274260535 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.4274260535
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_genbits.3096250797
Short name T767
Test name
Test status
Simulation time 42703398 ps
CPU time 1.44 seconds
Started Jun 29 05:32:33 PM PDT 24
Finished Jun 29 05:32:36 PM PDT 24
Peak memory 218688 kb
Host smart-eff3d522-ae6e-4052-8ad8-373765480ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096250797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3096250797
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.4228224293
Short name T445
Test name
Test status
Simulation time 29866831 ps
CPU time 0.91 seconds
Started Jun 29 05:32:11 PM PDT 24
Finished Jun 29 05:32:13 PM PDT 24
Peak memory 216084 kb
Host smart-f744e3b2-df2b-46cf-8f91-46e367231607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228224293 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.4228224293
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2497899432
Short name T891
Test name
Test status
Simulation time 17761090 ps
CPU time 1.06 seconds
Started Jun 29 05:32:10 PM PDT 24
Finished Jun 29 05:32:13 PM PDT 24
Peak memory 207656 kb
Host smart-50852fec-412f-4f7e-8913-d231cf38917b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497899432 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2497899432
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.189402658
Short name T5
Test name
Test status
Simulation time 119331902 ps
CPU time 1.32 seconds
Started Jun 29 05:32:13 PM PDT 24
Finished Jun 29 05:32:16 PM PDT 24
Peak memory 215584 kb
Host smart-b2844cd5-a904-47c3-9a04-5db85238960c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189402658 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.189402658
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1707976464
Short name T240
Test name
Test status
Simulation time 28369170585 ps
CPU time 630.61 seconds
Started Jun 29 05:32:10 PM PDT 24
Finished Jun 29 05:42:42 PM PDT 24
Peak memory 220484 kb
Host smart-602b0412-a634-4ed1-b594-91c0a2ada577
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707976464 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1707976464
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2712569013
Short name T405
Test name
Test status
Simulation time 57153762 ps
CPU time 1.09 seconds
Started Jun 29 05:33:59 PM PDT 24
Finished Jun 29 05:34:01 PM PDT 24
Peak memory 217608 kb
Host smart-b92fecbd-73e1-4af1-bc35-ef4a4a41337f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712569013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2712569013
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.661341919
Short name T349
Test name
Test status
Simulation time 34752976 ps
CPU time 1.32 seconds
Started Jun 29 05:33:53 PM PDT 24
Finished Jun 29 05:33:55 PM PDT 24
Peak memory 217544 kb
Host smart-ca4971e5-262e-4752-8680-8006e3481016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661341919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.661341919
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2550084327
Short name T420
Test name
Test status
Simulation time 43680633 ps
CPU time 1.64 seconds
Started Jun 29 05:33:56 PM PDT 24
Finished Jun 29 05:33:58 PM PDT 24
Peak memory 220236 kb
Host smart-3dfbedf9-3610-4443-86ff-6593a6ba7019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550084327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2550084327
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2233603428
Short name T897
Test name
Test status
Simulation time 47441460 ps
CPU time 1.56 seconds
Started Jun 29 05:33:51 PM PDT 24
Finished Jun 29 05:33:53 PM PDT 24
Peak memory 218804 kb
Host smart-d4298e8f-8583-4807-9222-d021d218359f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233603428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2233603428
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.4012823120
Short name T885
Test name
Test status
Simulation time 81366175 ps
CPU time 1.19 seconds
Started Jun 29 05:33:52 PM PDT 24
Finished Jun 29 05:33:53 PM PDT 24
Peak memory 217520 kb
Host smart-87c53da5-3dc4-49fe-b8dd-34540795a108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012823120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.4012823120
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.571187454
Short name T647
Test name
Test status
Simulation time 221762207 ps
CPU time 1.81 seconds
Started Jun 29 05:33:59 PM PDT 24
Finished Jun 29 05:34:02 PM PDT 24
Peak memory 219432 kb
Host smart-9653bbb0-2eb6-4de0-86d4-9b519a78a1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571187454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.571187454
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1395659125
Short name T379
Test name
Test status
Simulation time 71686710 ps
CPU time 1.25 seconds
Started Jun 29 05:33:48 PM PDT 24
Finished Jun 29 05:33:51 PM PDT 24
Peak memory 219104 kb
Host smart-e5506347-300f-4037-8779-08290d2a469f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395659125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1395659125
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3693994747
Short name T803
Test name
Test status
Simulation time 41653895 ps
CPU time 1.74 seconds
Started Jun 29 05:33:52 PM PDT 24
Finished Jun 29 05:33:55 PM PDT 24
Peak memory 218800 kb
Host smart-6363b173-d947-4f48-8fcd-da14121491b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693994747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3693994747
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1681688945
Short name T629
Test name
Test status
Simulation time 53120499 ps
CPU time 1.25 seconds
Started Jun 29 05:33:47 PM PDT 24
Finished Jun 29 05:33:50 PM PDT 24
Peak memory 217660 kb
Host smart-5e453416-eaf5-4e1d-b266-78f183904c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681688945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1681688945
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2432437286
Short name T747
Test name
Test status
Simulation time 74058641 ps
CPU time 1.1 seconds
Started Jun 29 05:33:52 PM PDT 24
Finished Jun 29 05:33:54 PM PDT 24
Peak memory 217660 kb
Host smart-e94a803e-3fe5-4cda-b334-0c39a427845c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432437286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2432437286
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1509437828
Short name T285
Test name
Test status
Simulation time 26755212 ps
CPU time 1.28 seconds
Started Jun 29 05:32:21 PM PDT 24
Finished Jun 29 05:32:23 PM PDT 24
Peak memory 219784 kb
Host smart-8ecca562-fd7d-4f88-acd6-162c756fe066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509437828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1509437828
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.19409920
Short name T639
Test name
Test status
Simulation time 77197878 ps
CPU time 0.99 seconds
Started Jun 29 05:32:22 PM PDT 24
Finished Jun 29 05:32:24 PM PDT 24
Peak memory 207068 kb
Host smart-747a665d-7bc7-469a-91be-5437ec1652c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19409920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.19409920
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.447721298
Short name T472
Test name
Test status
Simulation time 72015438 ps
CPU time 0.85 seconds
Started Jun 29 05:32:21 PM PDT 24
Finished Jun 29 05:32:22 PM PDT 24
Peak memory 215644 kb
Host smart-3485dd96-644d-4c72-85d7-72c64938926c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447721298 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.447721298
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2064479009
Short name T127
Test name
Test status
Simulation time 26815761 ps
CPU time 1.15 seconds
Started Jun 29 05:32:28 PM PDT 24
Finished Jun 29 05:32:29 PM PDT 24
Peak memory 217152 kb
Host smart-e8b4fb78-2440-417e-ad2b-c996fa656f37
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064479009 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2064479009
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_intr.1574372223
Short name T356
Test name
Test status
Simulation time 26678028 ps
CPU time 1 seconds
Started Jun 29 05:32:21 PM PDT 24
Finished Jun 29 05:32:24 PM PDT 24
Peak memory 215840 kb
Host smart-f1c57be0-ae99-4d75-888e-7876b3bf3b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574372223 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1574372223
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1840803542
Short name T464
Test name
Test status
Simulation time 14765910 ps
CPU time 0.96 seconds
Started Jun 29 05:32:27 PM PDT 24
Finished Jun 29 05:32:29 PM PDT 24
Peak memory 207420 kb
Host smart-d45c748f-05b2-4439-a6d1-2427bc6f1f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840803542 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1840803542
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1029902732
Short name T250
Test name
Test status
Simulation time 717070707 ps
CPU time 2.37 seconds
Started Jun 29 05:32:21 PM PDT 24
Finished Jun 29 05:32:25 PM PDT 24
Peak memory 215600 kb
Host smart-d777a484-47fa-4313-a887-4512c88142e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029902732 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1029902732
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.4248560868
Short name T582
Test name
Test status
Simulation time 46114604836 ps
CPU time 1194.92 seconds
Started Jun 29 05:32:21 PM PDT 24
Finished Jun 29 05:52:17 PM PDT 24
Peak memory 223980 kb
Host smart-f9ecd80b-151b-4c11-aadf-4317f318f552
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248560868 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.4248560868
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/211.edn_genbits.1530848799
Short name T583
Test name
Test status
Simulation time 248425624 ps
CPU time 1.45 seconds
Started Jun 29 05:33:52 PM PDT 24
Finished Jun 29 05:33:54 PM PDT 24
Peak memory 219140 kb
Host smart-de2d2421-49a5-4e9c-b071-c0d6e26bfa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530848799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1530848799
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.901759888
Short name T860
Test name
Test status
Simulation time 72268168 ps
CPU time 1.08 seconds
Started Jun 29 05:33:58 PM PDT 24
Finished Jun 29 05:34:00 PM PDT 24
Peak memory 217508 kb
Host smart-d0d7c79c-7416-4dcf-a53e-9451538ee0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901759888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.901759888
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.785820741
Short name T814
Test name
Test status
Simulation time 50922186 ps
CPU time 1.82 seconds
Started Jun 29 05:33:47 PM PDT 24
Finished Jun 29 05:33:51 PM PDT 24
Peak memory 218664 kb
Host smart-6710f1a6-23db-48c0-87b2-9b02a666df2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785820741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.785820741
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.715495685
Short name T934
Test name
Test status
Simulation time 86206114 ps
CPU time 1.28 seconds
Started Jun 29 05:33:51 PM PDT 24
Finished Jun 29 05:33:53 PM PDT 24
Peak memory 218964 kb
Host smart-4b7d3120-8004-4def-abd3-0d19bde7f9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715495685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.715495685
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.436372421
Short name T502
Test name
Test status
Simulation time 43912444 ps
CPU time 1.58 seconds
Started Jun 29 05:33:59 PM PDT 24
Finished Jun 29 05:34:01 PM PDT 24
Peak memory 217700 kb
Host smart-d61dd15e-be12-4f2b-9dc8-b0bf6cb9fcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436372421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.436372421
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2776739166
Short name T44
Test name
Test status
Simulation time 76414818 ps
CPU time 1.13 seconds
Started Jun 29 05:33:55 PM PDT 24
Finished Jun 29 05:33:56 PM PDT 24
Peak memory 218956 kb
Host smart-21c3d5e3-9ba5-4ac6-8f55-7a91e467babb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776739166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2776739166
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2816980367
Short name T909
Test name
Test status
Simulation time 67842168 ps
CPU time 0.91 seconds
Started Jun 29 05:33:50 PM PDT 24
Finished Jun 29 05:33:52 PM PDT 24
Peak memory 217636 kb
Host smart-433ac2b3-2a84-4b22-8376-e59b415de099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816980367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2816980367
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2243992137
Short name T24
Test name
Test status
Simulation time 33572520 ps
CPU time 1.3 seconds
Started Jun 29 05:33:58 PM PDT 24
Finished Jun 29 05:34:00 PM PDT 24
Peak memory 217652 kb
Host smart-2385e2ab-5f71-4584-a91c-a01029cc3da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243992137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2243992137
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2572806104
Short name T327
Test name
Test status
Simulation time 321284454 ps
CPU time 4.24 seconds
Started Jun 29 05:33:56 PM PDT 24
Finished Jun 29 05:34:01 PM PDT 24
Peak memory 220456 kb
Host smart-a5fd661f-bcf8-43c9-aa6f-14c29ab17ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572806104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2572806104
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2134768119
Short name T733
Test name
Test status
Simulation time 83265327 ps
CPU time 1.18 seconds
Started Jun 29 05:32:21 PM PDT 24
Finished Jun 29 05:32:24 PM PDT 24
Peak memory 219836 kb
Host smart-d59534fa-52cf-4300-b631-3f79cca8ddfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134768119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2134768119
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.959507302
Short name T53
Test name
Test status
Simulation time 23939454 ps
CPU time 0.9 seconds
Started Jun 29 05:32:27 PM PDT 24
Finished Jun 29 05:32:29 PM PDT 24
Peak memory 215120 kb
Host smart-a999e602-3c45-4bf2-9fcd-03ae2c7cc4b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959507302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.959507302
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.738659091
Short name T515
Test name
Test status
Simulation time 100076032 ps
CPU time 0.94 seconds
Started Jun 29 05:32:27 PM PDT 24
Finished Jun 29 05:32:29 PM PDT 24
Peak memory 215716 kb
Host smart-97050edf-6ad3-4e6b-9193-1bfd2777c6f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738659091 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.738659091
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3071963860
Short name T476
Test name
Test status
Simulation time 57805911 ps
CPU time 1.14 seconds
Started Jun 29 05:32:22 PM PDT 24
Finished Jun 29 05:32:24 PM PDT 24
Peak memory 218676 kb
Host smart-ca87bf52-6dd4-4ee3-b752-cea1dce56265
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071963860 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3071963860
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1379789832
Short name T130
Test name
Test status
Simulation time 20971191 ps
CPU time 1.24 seconds
Started Jun 29 05:32:27 PM PDT 24
Finished Jun 29 05:32:28 PM PDT 24
Peak memory 229820 kb
Host smart-63bb3428-cc6b-4793-a9f4-328f53bf8433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379789832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1379789832
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3775763363
Short name T63
Test name
Test status
Simulation time 73904115 ps
CPU time 1.27 seconds
Started Jun 29 05:32:29 PM PDT 24
Finished Jun 29 05:32:30 PM PDT 24
Peak memory 219224 kb
Host smart-84cb1f41-cc4f-4562-9e00-f4eab2569c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775763363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3775763363
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1378935881
Short name T34
Test name
Test status
Simulation time 32301948 ps
CPU time 0.89 seconds
Started Jun 29 05:32:26 PM PDT 24
Finished Jun 29 05:32:28 PM PDT 24
Peak memory 215888 kb
Host smart-e3a73550-7e7b-434a-a58d-74025b12ca2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378935881 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1378935881
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1905807787
Short name T491
Test name
Test status
Simulation time 16106742 ps
CPU time 0.99 seconds
Started Jun 29 05:32:23 PM PDT 24
Finished Jun 29 05:32:25 PM PDT 24
Peak memory 215580 kb
Host smart-ceb4a5eb-96a3-43bf-9c21-3953bd6c5a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905807787 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1905807787
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2531583983
Short name T774
Test name
Test status
Simulation time 161755332 ps
CPU time 1.95 seconds
Started Jun 29 05:32:21 PM PDT 24
Finished Jun 29 05:32:24 PM PDT 24
Peak memory 207480 kb
Host smart-11c57e44-8495-4d97-81c5-839cf53ef466
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531583983 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2531583983
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1447233102
Short name T239
Test name
Test status
Simulation time 432545674730 ps
CPU time 1300.73 seconds
Started Jun 29 05:32:21 PM PDT 24
Finished Jun 29 05:54:02 PM PDT 24
Peak memory 224180 kb
Host smart-68cb7692-37b9-40de-808c-2737dd2d310b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447233102 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1447233102
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3173111459
Short name T709
Test name
Test status
Simulation time 102929625 ps
CPU time 1.52 seconds
Started Jun 29 05:33:57 PM PDT 24
Finished Jun 29 05:34:00 PM PDT 24
Peak memory 219208 kb
Host smart-f7670d45-f69a-4b92-ae93-605e09ef6758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173111459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3173111459
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1957661885
Short name T547
Test name
Test status
Simulation time 45988293 ps
CPU time 1.73 seconds
Started Jun 29 05:34:00 PM PDT 24
Finished Jun 29 05:34:03 PM PDT 24
Peak memory 217908 kb
Host smart-07e876c4-60e0-4402-87a1-49c0af0d69e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957661885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1957661885
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3743529185
Short name T429
Test name
Test status
Simulation time 67087879 ps
CPU time 1.16 seconds
Started Jun 29 05:33:58 PM PDT 24
Finished Jun 29 05:34:00 PM PDT 24
Peak memory 217580 kb
Host smart-6adf26f8-480b-4f1a-abc7-b0fa4b412036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743529185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3743529185
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.858426223
Short name T330
Test name
Test status
Simulation time 31919412 ps
CPU time 1.36 seconds
Started Jun 29 05:34:03 PM PDT 24
Finished Jun 29 05:34:05 PM PDT 24
Peak memory 218956 kb
Host smart-8a406dbe-7931-4d4d-b547-73d21dd2dc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858426223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.858426223
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.4133939949
Short name T381
Test name
Test status
Simulation time 68087731 ps
CPU time 1.32 seconds
Started Jun 29 05:34:03 PM PDT 24
Finished Jun 29 05:34:05 PM PDT 24
Peak memory 218848 kb
Host smart-9314dc58-32e2-4902-8ae4-ea8d5ca8d4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133939949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.4133939949
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2751509652
Short name T883
Test name
Test status
Simulation time 44779301 ps
CPU time 1.26 seconds
Started Jun 29 05:33:55 PM PDT 24
Finished Jun 29 05:33:57 PM PDT 24
Peak memory 217756 kb
Host smart-baba4bca-1b7a-49ab-af86-ad67ddfbc744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751509652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2751509652
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1344880208
Short name T712
Test name
Test status
Simulation time 40571104 ps
CPU time 1.52 seconds
Started Jun 29 05:34:01 PM PDT 24
Finished Jun 29 05:34:03 PM PDT 24
Peak memory 217692 kb
Host smart-37575458-5f47-4e3c-9b37-d647d8d19b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344880208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1344880208
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3787744661
Short name T609
Test name
Test status
Simulation time 260243821 ps
CPU time 1 seconds
Started Jun 29 05:34:12 PM PDT 24
Finished Jun 29 05:34:13 PM PDT 24
Peak memory 219620 kb
Host smart-66d984bc-2ff1-4141-b701-c9783bea318b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787744661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3787744661
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1979575751
Short name T763
Test name
Test status
Simulation time 26965529 ps
CPU time 1.27 seconds
Started Jun 29 05:33:55 PM PDT 24
Finished Jun 29 05:33:56 PM PDT 24
Peak memory 220264 kb
Host smart-6d7e9791-07d6-4536-8598-a72ea3391757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979575751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1979575751
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.4289053069
Short name T376
Test name
Test status
Simulation time 58364154 ps
CPU time 1.91 seconds
Started Jun 29 05:33:57 PM PDT 24
Finished Jun 29 05:33:59 PM PDT 24
Peak memory 218884 kb
Host smart-ca390e19-d5d1-4939-898b-7746ee076f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289053069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.4289053069
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1799620844
Short name T887
Test name
Test status
Simulation time 23088475 ps
CPU time 1.24 seconds
Started Jun 29 05:32:33 PM PDT 24
Finished Jun 29 05:32:36 PM PDT 24
Peak memory 220712 kb
Host smart-3f590322-6bcd-4dec-a699-0992663f2d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799620844 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1799620844
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3412389635
Short name T863
Test name
Test status
Simulation time 26587937 ps
CPU time 0.95 seconds
Started Jun 29 05:32:22 PM PDT 24
Finished Jun 29 05:32:24 PM PDT 24
Peak memory 207072 kb
Host smart-86ddf593-a2d5-4ba9-8b2a-97642e6825e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412389635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3412389635
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.63468144
Short name T91
Test name
Test status
Simulation time 10641101 ps
CPU time 0.87 seconds
Started Jun 29 05:32:32 PM PDT 24
Finished Jun 29 05:32:34 PM PDT 24
Peak memory 216652 kb
Host smart-09afb1a5-bad0-4fdf-b094-1774459b3d4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63468144 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.63468144
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.567780456
Short name T602
Test name
Test status
Simulation time 71007262 ps
CPU time 1.02 seconds
Started Jun 29 05:32:25 PM PDT 24
Finished Jun 29 05:32:27 PM PDT 24
Peak memory 218432 kb
Host smart-85a054a8-1d0b-42d8-964f-8f2402183e8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567780456 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.567780456
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.935878538
Short name T209
Test name
Test status
Simulation time 55221042 ps
CPU time 1.03 seconds
Started Jun 29 05:32:21 PM PDT 24
Finished Jun 29 05:32:24 PM PDT 24
Peak memory 220028 kb
Host smart-993a0b1b-17d9-42b2-ae6a-e86551b7683d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935878538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.935878538
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1892850739
Short name T851
Test name
Test status
Simulation time 136933272 ps
CPU time 2.32 seconds
Started Jun 29 05:32:22 PM PDT 24
Finished Jun 29 05:32:25 PM PDT 24
Peak memory 217720 kb
Host smart-d418a873-3773-4112-be27-4f4ca5b2222b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892850739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1892850739
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3688096180
Short name T100
Test name
Test status
Simulation time 29458875 ps
CPU time 0.94 seconds
Started Jun 29 05:32:32 PM PDT 24
Finished Jun 29 05:32:33 PM PDT 24
Peak memory 215840 kb
Host smart-5b5e6efc-a61d-4c7e-b1bc-ebc0c28ef0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688096180 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3688096180
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.756810635
Short name T893
Test name
Test status
Simulation time 25073603 ps
CPU time 0.99 seconds
Started Jun 29 05:32:24 PM PDT 24
Finished Jun 29 05:32:25 PM PDT 24
Peak memory 215648 kb
Host smart-2925abc4-3410-4d1a-a1c6-3bd7deddc1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756810635 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.756810635
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1903776200
Short name T991
Test name
Test status
Simulation time 290617166 ps
CPU time 2.17 seconds
Started Jun 29 05:32:21 PM PDT 24
Finished Jun 29 05:32:23 PM PDT 24
Peak memory 215636 kb
Host smart-34254986-43b9-47c0-bb48-0fd5ba569c3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903776200 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1903776200
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1382092506
Short name T241
Test name
Test status
Simulation time 157692088409 ps
CPU time 1890.7 seconds
Started Jun 29 05:32:23 PM PDT 24
Finished Jun 29 06:03:55 PM PDT 24
Peak memory 226236 kb
Host smart-e4fe97b5-2545-4d64-8d07-bc94763005a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382092506 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1382092506
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1503739209
Short name T770
Test name
Test status
Simulation time 43450606 ps
CPU time 1.48 seconds
Started Jun 29 05:34:12 PM PDT 24
Finished Jun 29 05:34:14 PM PDT 24
Peak memory 218760 kb
Host smart-b2e86e3c-1ff0-46e4-9624-a079e9218669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503739209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1503739209
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.286096480
Short name T521
Test name
Test status
Simulation time 118692931 ps
CPU time 1.18 seconds
Started Jun 29 05:34:14 PM PDT 24
Finished Jun 29 05:34:15 PM PDT 24
Peak memory 217608 kb
Host smart-56890688-ea51-44ca-bb4d-d0258853767a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286096480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.286096480
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2971343144
Short name T832
Test name
Test status
Simulation time 330551622 ps
CPU time 1.98 seconds
Started Jun 29 05:33:56 PM PDT 24
Finished Jun 29 05:33:58 PM PDT 24
Peak memory 219156 kb
Host smart-4073b850-3405-4ca9-bba4-16973797ee94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971343144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2971343144
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.396833175
Short name T905
Test name
Test status
Simulation time 38903126 ps
CPU time 1.4 seconds
Started Jun 29 05:33:57 PM PDT 24
Finished Jun 29 05:33:59 PM PDT 24
Peak memory 219680 kb
Host smart-f4536c18-4825-450f-a19f-86eb00d5a90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396833175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.396833175
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.355856353
Short name T868
Test name
Test status
Simulation time 49300888 ps
CPU time 1.59 seconds
Started Jun 29 05:34:03 PM PDT 24
Finished Jun 29 05:34:05 PM PDT 24
Peak memory 218768 kb
Host smart-fc67a584-7055-4b24-9858-f51aaad13702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355856353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.355856353
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3139591193
Short name T505
Test name
Test status
Simulation time 48465920 ps
CPU time 1.38 seconds
Started Jun 29 05:34:01 PM PDT 24
Finished Jun 29 05:34:03 PM PDT 24
Peak memory 218796 kb
Host smart-8d9b9115-39a4-4bcd-aa94-9f63d55a42ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139591193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3139591193
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.4247406067
Short name T900
Test name
Test status
Simulation time 32691392 ps
CPU time 1.35 seconds
Started Jun 29 05:34:04 PM PDT 24
Finished Jun 29 05:34:06 PM PDT 24
Peak memory 218676 kb
Host smart-bdb6d2aa-e528-4c24-8e66-e1629be25b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247406067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.4247406067
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1122912181
Short name T947
Test name
Test status
Simulation time 95165495 ps
CPU time 1.38 seconds
Started Jun 29 05:33:56 PM PDT 24
Finished Jun 29 05:33:57 PM PDT 24
Peak memory 220048 kb
Host smart-50301c44-50e7-4171-8af4-325af21bd7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122912181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1122912181
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1638774471
Short name T532
Test name
Test status
Simulation time 263100728 ps
CPU time 3.94 seconds
Started Jun 29 05:34:03 PM PDT 24
Finished Jun 29 05:34:08 PM PDT 24
Peak memory 217692 kb
Host smart-e85a7e02-3fff-4449-a448-c685039f3ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638774471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1638774471
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2911514255
Short name T656
Test name
Test status
Simulation time 52612733 ps
CPU time 1.51 seconds
Started Jun 29 05:33:56 PM PDT 24
Finished Jun 29 05:33:58 PM PDT 24
Peak memory 218772 kb
Host smart-67fdeccf-ee2e-480e-b75f-88eb5d479ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911514255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2911514255
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1992570297
Short name T133
Test name
Test status
Simulation time 87721955 ps
CPU time 1.22 seconds
Started Jun 29 05:32:22 PM PDT 24
Finished Jun 29 05:32:24 PM PDT 24
Peak memory 219512 kb
Host smart-880ee154-9421-4a12-b029-ffb8f9122dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992570297 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1992570297
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2502435635
Short name T895
Test name
Test status
Simulation time 12098282 ps
CPU time 0.9 seconds
Started Jun 29 05:32:22 PM PDT 24
Finished Jun 29 05:32:24 PM PDT 24
Peak memory 206996 kb
Host smart-2d738bed-e4bf-4111-993d-c72feb55fcb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502435635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2502435635
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.42144583
Short name T672
Test name
Test status
Simulation time 13300455 ps
CPU time 0.93 seconds
Started Jun 29 05:32:20 PM PDT 24
Finished Jun 29 05:32:22 PM PDT 24
Peak memory 215816 kb
Host smart-83603f48-9d30-4af1-8425-07be39bdfe70
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42144583 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.42144583
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.1135963177
Short name T375
Test name
Test status
Simulation time 36071253 ps
CPU time 0.97 seconds
Started Jun 29 05:32:22 PM PDT 24
Finished Jun 29 05:32:24 PM PDT 24
Peak memory 220184 kb
Host smart-a8657c03-11ff-4c0b-b5f5-1a493a45d649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135963177 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1135963177
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2248544580
Short name T352
Test name
Test status
Simulation time 100227407 ps
CPU time 2.53 seconds
Started Jun 29 05:32:20 PM PDT 24
Finished Jun 29 05:32:22 PM PDT 24
Peak memory 220584 kb
Host smart-48256643-a66a-420f-8094-4ee93190f1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248544580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2248544580
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.4276616350
Short name T920
Test name
Test status
Simulation time 52133382 ps
CPU time 0.84 seconds
Started Jun 29 05:32:32 PM PDT 24
Finished Jun 29 05:32:35 PM PDT 24
Peak memory 215820 kb
Host smart-b0f257db-d946-4903-8f41-8018ca322b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276616350 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.4276616350
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3274832061
Short name T428
Test name
Test status
Simulation time 88059493 ps
CPU time 0.9 seconds
Started Jun 29 05:32:37 PM PDT 24
Finished Jun 29 05:32:40 PM PDT 24
Peak memory 215600 kb
Host smart-a915255c-5d36-4493-8c77-d8346c77a429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274832061 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3274832061
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.4174530231
Short name T773
Test name
Test status
Simulation time 1033224285 ps
CPU time 5.96 seconds
Started Jun 29 05:32:23 PM PDT 24
Finished Jun 29 05:32:30 PM PDT 24
Peak memory 217364 kb
Host smart-d46ebe7f-32c7-40ce-8558-af482ff77ae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174530231 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.4174530231
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2102482314
Short name T903
Test name
Test status
Simulation time 108610987125 ps
CPU time 760.11 seconds
Started Jun 29 05:32:22 PM PDT 24
Finished Jun 29 05:45:03 PM PDT 24
Peak memory 224000 kb
Host smart-94291b73-7179-474c-86f7-d0a0c3f8dafb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102482314 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2102482314
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1761646417
Short name T576
Test name
Test status
Simulation time 114444666 ps
CPU time 1.41 seconds
Started Jun 29 05:33:56 PM PDT 24
Finished Jun 29 05:33:58 PM PDT 24
Peak memory 218868 kb
Host smart-a5adae28-5880-43b7-9437-57a76e9fd52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761646417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1761646417
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1671211414
Short name T321
Test name
Test status
Simulation time 110169369 ps
CPU time 2.73 seconds
Started Jun 29 05:33:57 PM PDT 24
Finished Jun 29 05:34:00 PM PDT 24
Peak memory 220340 kb
Host smart-f3a9770c-da16-45ac-8ecf-046073772677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671211414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1671211414
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1598079208
Short name T423
Test name
Test status
Simulation time 35707946 ps
CPU time 1.26 seconds
Started Jun 29 05:33:55 PM PDT 24
Finished Jun 29 05:33:57 PM PDT 24
Peak memory 218704 kb
Host smart-35ce0e35-ba36-49aa-98e0-f9644705b494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598079208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1598079208
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2250038585
Short name T325
Test name
Test status
Simulation time 53158642 ps
CPU time 1.27 seconds
Started Jun 29 05:34:00 PM PDT 24
Finished Jun 29 05:34:02 PM PDT 24
Peak memory 219004 kb
Host smart-10ef53e6-a54d-4667-b367-457635319fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250038585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2250038585
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3047437946
Short name T577
Test name
Test status
Simulation time 39606193 ps
CPU time 0.98 seconds
Started Jun 29 05:33:57 PM PDT 24
Finished Jun 29 05:33:59 PM PDT 24
Peak memory 217712 kb
Host smart-d031b03a-f388-4bc7-ac5b-5c22e6c51d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047437946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3047437946
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3045510631
Short name T448
Test name
Test status
Simulation time 75327057 ps
CPU time 1.24 seconds
Started Jun 29 05:33:59 PM PDT 24
Finished Jun 29 05:34:01 PM PDT 24
Peak memory 218748 kb
Host smart-f782d72e-d405-46d2-a715-d714b4e89cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045510631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3045510631
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3202171399
Short name T742
Test name
Test status
Simulation time 52309250 ps
CPU time 1.32 seconds
Started Jun 29 05:34:00 PM PDT 24
Finished Jun 29 05:34:02 PM PDT 24
Peak memory 218800 kb
Host smart-0d491a98-457a-4cb9-be35-b6a64da82026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202171399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3202171399
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3331775096
Short name T888
Test name
Test status
Simulation time 307831244 ps
CPU time 3.69 seconds
Started Jun 29 05:34:03 PM PDT 24
Finished Jun 29 05:34:07 PM PDT 24
Peak memory 220220 kb
Host smart-01c65c72-4082-4c8f-bdd8-9ed6f99c5b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331775096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3331775096
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3048226735
Short name T490
Test name
Test status
Simulation time 63150518 ps
CPU time 1.34 seconds
Started Jun 29 05:33:59 PM PDT 24
Finished Jun 29 05:34:02 PM PDT 24
Peak memory 218604 kb
Host smart-3fd4036b-cdde-4e52-9780-fb38cc7388be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048226735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3048226735
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2105872043
Short name T651
Test name
Test status
Simulation time 67838786 ps
CPU time 1.25 seconds
Started Jun 29 05:34:01 PM PDT 24
Finished Jun 29 05:34:03 PM PDT 24
Peak memory 220136 kb
Host smart-78ef9bca-9d2c-4816-8593-c812a55ea52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105872043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2105872043
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1843638393
Short name T129
Test name
Test status
Simulation time 103349909 ps
CPU time 1.26 seconds
Started Jun 29 05:32:20 PM PDT 24
Finished Jun 29 05:32:22 PM PDT 24
Peak memory 218668 kb
Host smart-d2ef4dbb-30c9-4e3e-b4fc-4d399f0f22b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843638393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1843638393
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3771484867
Short name T510
Test name
Test status
Simulation time 35081768 ps
CPU time 0.84 seconds
Started Jun 29 05:32:21 PM PDT 24
Finished Jun 29 05:32:23 PM PDT 24
Peak memory 207068 kb
Host smart-7531f025-b9ce-484d-a93a-2317aef4d286
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771484867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3771484867
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.1248467528
Short name T186
Test name
Test status
Simulation time 84525038 ps
CPU time 0.86 seconds
Started Jun 29 05:32:33 PM PDT 24
Finished Jun 29 05:32:35 PM PDT 24
Peak memory 216536 kb
Host smart-00e22acc-1b92-48e8-a304-62ff07a6ab0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248467528 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1248467528
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.742689957
Short name T484
Test name
Test status
Simulation time 37645451 ps
CPU time 1.35 seconds
Started Jun 29 05:32:24 PM PDT 24
Finished Jun 29 05:32:26 PM PDT 24
Peak memory 217200 kb
Host smart-222a302d-346f-4f05-ab61-6e920cf31794
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742689957 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.742689957
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.3457689422
Short name T594
Test name
Test status
Simulation time 19058449 ps
CPU time 1.03 seconds
Started Jun 29 05:32:32 PM PDT 24
Finished Jun 29 05:32:34 PM PDT 24
Peak memory 218728 kb
Host smart-f4d31f76-8146-4c33-88c8-63cc84e7baf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457689422 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3457689422
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.899877650
Short name T404
Test name
Test status
Simulation time 43969878 ps
CPU time 1.56 seconds
Started Jun 29 05:32:21 PM PDT 24
Finished Jun 29 05:32:24 PM PDT 24
Peak memory 215616 kb
Host smart-141b77d9-8426-4b2d-8752-1a050c704b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899877650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.899877650
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.840072532
Short name T113
Test name
Test status
Simulation time 26665136 ps
CPU time 0.97 seconds
Started Jun 29 05:32:21 PM PDT 24
Finished Jun 29 05:32:23 PM PDT 24
Peak memory 216140 kb
Host smart-27dae681-3ab5-486b-a26d-09afa4bcac39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840072532 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.840072532
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3671243820
Short name T516
Test name
Test status
Simulation time 16884489 ps
CPU time 1.01 seconds
Started Jun 29 05:32:32 PM PDT 24
Finished Jun 29 05:32:33 PM PDT 24
Peak memory 215520 kb
Host smart-0c7d718b-1608-4500-8e5a-44ac93513cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671243820 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3671243820
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.406323746
Short name T749
Test name
Test status
Simulation time 214467129 ps
CPU time 3.67 seconds
Started Jun 29 05:32:21 PM PDT 24
Finished Jun 29 05:32:26 PM PDT 24
Peak memory 217600 kb
Host smart-ac6a2fff-31a7-4095-9f5e-4467ec2deee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406323746 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.406323746
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/250.edn_genbits.208841366
Short name T825
Test name
Test status
Simulation time 92568278 ps
CPU time 1.33 seconds
Started Jun 29 05:33:58 PM PDT 24
Finished Jun 29 05:34:00 PM PDT 24
Peak memory 217524 kb
Host smart-a6935b64-5f8c-4664-8af2-4370bdf60567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208841366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.208841366
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.3479842006
Short name T494
Test name
Test status
Simulation time 119817648 ps
CPU time 1.72 seconds
Started Jun 29 05:34:03 PM PDT 24
Finished Jun 29 05:34:06 PM PDT 24
Peak memory 219316 kb
Host smart-8e822ba8-9c4a-4b8f-ab6a-10237f48550b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479842006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3479842006
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2703150292
Short name T567
Test name
Test status
Simulation time 132678779 ps
CPU time 1.26 seconds
Started Jun 29 05:34:03 PM PDT 24
Finished Jun 29 05:34:05 PM PDT 24
Peak memory 217744 kb
Host smart-131f387a-ad47-4dfd-aec4-ce7131218e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703150292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2703150292
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2390600483
Short name T953
Test name
Test status
Simulation time 34677133 ps
CPU time 1.33 seconds
Started Jun 29 05:34:07 PM PDT 24
Finished Jun 29 05:34:09 PM PDT 24
Peak memory 218896 kb
Host smart-4c6fe3d6-163e-4f76-8cc6-e31c7d3ed4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390600483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2390600483
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.162283143
Short name T849
Test name
Test status
Simulation time 30184882 ps
CPU time 1.36 seconds
Started Jun 29 05:34:07 PM PDT 24
Finished Jun 29 05:34:09 PM PDT 24
Peak memory 218888 kb
Host smart-de1a4add-e4c9-4713-8f22-f519e137b5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162283143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.162283143
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2505335876
Short name T765
Test name
Test status
Simulation time 263562787 ps
CPU time 3.9 seconds
Started Jun 29 05:34:02 PM PDT 24
Finished Jun 29 05:34:06 PM PDT 24
Peak memory 220928 kb
Host smart-7b84a52a-18c7-4c4c-93e1-c55fb5b2cf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505335876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2505335876
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1976694390
Short name T664
Test name
Test status
Simulation time 50621979 ps
CPU time 1.34 seconds
Started Jun 29 05:34:04 PM PDT 24
Finished Jun 29 05:34:06 PM PDT 24
Peak memory 218872 kb
Host smart-83500849-2b13-4e47-acad-d6084a538fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976694390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1976694390
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1509359287
Short name T415
Test name
Test status
Simulation time 112162483 ps
CPU time 1.54 seconds
Started Jun 29 05:34:01 PM PDT 24
Finished Jun 29 05:34:04 PM PDT 24
Peak memory 218936 kb
Host smart-2999774d-7f2d-4de9-8061-81d39f63ab2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509359287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1509359287
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1367206710
Short name T977
Test name
Test status
Simulation time 44591364 ps
CPU time 1.83 seconds
Started Jun 29 05:34:03 PM PDT 24
Finished Jun 29 05:34:06 PM PDT 24
Peak memory 220332 kb
Host smart-960d7f3f-1337-4fb8-9def-635afcdad9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367206710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1367206710
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3565430540
Short name T963
Test name
Test status
Simulation time 52491462 ps
CPU time 1.21 seconds
Started Jun 29 05:34:01 PM PDT 24
Finished Jun 29 05:34:03 PM PDT 24
Peak memory 217716 kb
Host smart-90489263-9a66-401f-acbf-c7c90253b4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565430540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3565430540
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1370086870
Short name T459
Test name
Test status
Simulation time 157823293 ps
CPU time 1.26 seconds
Started Jun 29 05:32:24 PM PDT 24
Finished Jun 29 05:32:26 PM PDT 24
Peak memory 218712 kb
Host smart-265d0880-be3c-45d0-aba3-6bc480eab311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370086870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1370086870
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2607943501
Short name T727
Test name
Test status
Simulation time 67276619 ps
CPU time 1.23 seconds
Started Jun 29 05:32:27 PM PDT 24
Finished Jun 29 05:32:29 PM PDT 24
Peak memory 215208 kb
Host smart-6a166de1-e74f-4641-b918-ce8538be4be1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607943501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2607943501
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1137802631
Short name T740
Test name
Test status
Simulation time 48231849 ps
CPU time 1.47 seconds
Started Jun 29 05:32:35 PM PDT 24
Finished Jun 29 05:32:38 PM PDT 24
Peak memory 217220 kb
Host smart-81c6ffb5-0a7a-4bfd-bea4-61bde659e44c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137802631 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1137802631
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.4266156072
Short name T207
Test name
Test status
Simulation time 29491090 ps
CPU time 1.33 seconds
Started Jun 29 05:32:27 PM PDT 24
Finished Jun 29 05:32:29 PM PDT 24
Peak memory 220000 kb
Host smart-c39f8d72-bc2c-4762-b1bc-bbb2cc9bdaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266156072 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.4266156072
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2278666876
Short name T930
Test name
Test status
Simulation time 40337882 ps
CPU time 1.72 seconds
Started Jun 29 05:32:33 PM PDT 24
Finished Jun 29 05:32:36 PM PDT 24
Peak memory 218876 kb
Host smart-9420a84c-9065-402e-9a0b-2ce1b1b64da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278666876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2278666876
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2254776229
Short name T35
Test name
Test status
Simulation time 26806404 ps
CPU time 0.97 seconds
Started Jun 29 05:32:21 PM PDT 24
Finished Jun 29 05:32:24 PM PDT 24
Peak memory 216148 kb
Host smart-d49a3f52-dec5-485a-9e65-691893accae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254776229 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2254776229
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2648058972
Short name T690
Test name
Test status
Simulation time 26678236 ps
CPU time 0.95 seconds
Started Jun 29 05:32:21 PM PDT 24
Finished Jun 29 05:32:23 PM PDT 24
Peak memory 215600 kb
Host smart-44c2bdf2-d918-4a37-b802-ba69e1422f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648058972 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2648058972
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3323526856
Short name T233
Test name
Test status
Simulation time 87910321057 ps
CPU time 516.04 seconds
Started Jun 29 05:32:29 PM PDT 24
Finished Jun 29 05:41:06 PM PDT 24
Peak memory 224024 kb
Host smart-68d2da74-9011-4e68-b8d1-feb5801a313c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323526856 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3323526856
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3225509584
Short name T337
Test name
Test status
Simulation time 75091090 ps
CPU time 1.26 seconds
Started Jun 29 05:33:57 PM PDT 24
Finished Jun 29 05:33:59 PM PDT 24
Peak memory 219224 kb
Host smart-28893acc-5980-4953-a79e-d089df7c39d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225509584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3225509584
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.808315499
Short name T794
Test name
Test status
Simulation time 92542761 ps
CPU time 1.59 seconds
Started Jun 29 05:33:56 PM PDT 24
Finished Jun 29 05:33:58 PM PDT 24
Peak memory 219304 kb
Host smart-793b26a9-1f5d-4beb-a459-196b221dd787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808315499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.808315499
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3800993099
Short name T244
Test name
Test status
Simulation time 48979806 ps
CPU time 1.71 seconds
Started Jun 29 05:34:02 PM PDT 24
Finished Jun 29 05:34:05 PM PDT 24
Peak memory 218980 kb
Host smart-2ab40fa2-09af-4671-ae2a-600782bb7c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800993099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3800993099
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1175701680
Short name T924
Test name
Test status
Simulation time 52211591 ps
CPU time 1.54 seconds
Started Jun 29 05:33:59 PM PDT 24
Finished Jun 29 05:34:02 PM PDT 24
Peak memory 217716 kb
Host smart-ce4edfc4-ac41-4645-a6e4-3c033dc456a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175701680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1175701680
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2594362957
Short name T856
Test name
Test status
Simulation time 246806298 ps
CPU time 1.15 seconds
Started Jun 29 05:34:01 PM PDT 24
Finished Jun 29 05:34:03 PM PDT 24
Peak memory 217648 kb
Host smart-185dec24-ca2c-445a-bc89-b6c673fb8cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594362957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2594362957
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3433580141
Short name T245
Test name
Test status
Simulation time 93881290 ps
CPU time 1.11 seconds
Started Jun 29 05:33:53 PM PDT 24
Finished Jun 29 05:33:55 PM PDT 24
Peak memory 215620 kb
Host smart-477df35c-e446-4043-9def-45fe29204cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433580141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3433580141
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.445404013
Short name T387
Test name
Test status
Simulation time 105347545 ps
CPU time 1.24 seconds
Started Jun 29 05:34:04 PM PDT 24
Finished Jun 29 05:34:06 PM PDT 24
Peak memory 217720 kb
Host smart-3e3431f6-8f18-43a2-8394-5291b2b5c343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445404013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.445404013
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.4148334087
Short name T809
Test name
Test status
Simulation time 61330252 ps
CPU time 2.37 seconds
Started Jun 29 05:34:00 PM PDT 24
Finished Jun 29 05:34:04 PM PDT 24
Peak memory 220620 kb
Host smart-4f9cf7be-f523-4392-9225-77a1588ac368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148334087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.4148334087
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3288521328
Short name T753
Test name
Test status
Simulation time 18792439 ps
CPU time 1.19 seconds
Started Jun 29 05:33:58 PM PDT 24
Finished Jun 29 05:33:59 PM PDT 24
Peak memory 217656 kb
Host smart-c9d65aa5-f1c3-4e6f-a977-093fc28a0de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288521328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3288521328
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.4048452783
Short name T666
Test name
Test status
Simulation time 47366959 ps
CPU time 1.27 seconds
Started Jun 29 05:32:45 PM PDT 24
Finished Jun 29 05:32:49 PM PDT 24
Peak memory 218796 kb
Host smart-e2faa337-daf4-4741-81d2-f3313fb8eca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048452783 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.4048452783
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2626911892
Short name T450
Test name
Test status
Simulation time 16896022 ps
CPU time 1.02 seconds
Started Jun 29 05:32:31 PM PDT 24
Finished Jun 29 05:32:33 PM PDT 24
Peak memory 215140 kb
Host smart-e1f8b2fe-a43f-4ae8-ae0c-f779d56a6f41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626911892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2626911892
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.576635009
Short name T169
Test name
Test status
Simulation time 45424581 ps
CPU time 0.89 seconds
Started Jun 29 05:32:33 PM PDT 24
Finished Jun 29 05:32:36 PM PDT 24
Peak memory 216560 kb
Host smart-744d32db-49dc-4bc8-9eda-9ac288e745bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576635009 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.576635009
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.810522455
Short name T120
Test name
Test status
Simulation time 33789272 ps
CPU time 1.29 seconds
Started Jun 29 05:32:47 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 218568 kb
Host smart-b6f88de7-1436-4501-8950-b3c360bbae5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810522455 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.810522455
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3388488150
Short name T989
Test name
Test status
Simulation time 18170844 ps
CPU time 1.16 seconds
Started Jun 29 05:32:22 PM PDT 24
Finished Jun 29 05:32:24 PM PDT 24
Peak memory 224116 kb
Host smart-68a625dc-1b97-46b9-903e-1a49da4c3f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388488150 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3388488150
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3663961194
Short name T779
Test name
Test status
Simulation time 47428434 ps
CPU time 1.48 seconds
Started Jun 29 05:32:32 PM PDT 24
Finished Jun 29 05:32:34 PM PDT 24
Peak memory 215588 kb
Host smart-1055b20a-53f7-4a20-b522-60924cd6f0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663961194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3663961194
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1154993189
Short name T838
Test name
Test status
Simulation time 27185644 ps
CPU time 1.03 seconds
Started Jun 29 05:32:31 PM PDT 24
Finished Jun 29 05:32:33 PM PDT 24
Peak memory 215840 kb
Host smart-4f31cf34-ee46-45ff-ad89-fb6dfa3e7ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154993189 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1154993189
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3503541944
Short name T486
Test name
Test status
Simulation time 42773324 ps
CPU time 0.95 seconds
Started Jun 29 05:32:25 PM PDT 24
Finished Jun 29 05:32:27 PM PDT 24
Peak memory 215600 kb
Host smart-bd35f24f-70a8-4069-a19e-20eb6cd63cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503541944 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3503541944
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.628088298
Short name T624
Test name
Test status
Simulation time 149902857 ps
CPU time 3.21 seconds
Started Jun 29 05:32:35 PM PDT 24
Finished Jun 29 05:32:40 PM PDT 24
Peak memory 215676 kb
Host smart-d87fe5c6-7d39-4ebc-9d2d-18160060c199
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628088298 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.628088298
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.521012998
Short name T677
Test name
Test status
Simulation time 104429710052 ps
CPU time 257.01 seconds
Started Jun 29 05:32:29 PM PDT 24
Finished Jun 29 05:36:46 PM PDT 24
Peak memory 219392 kb
Host smart-062a22bc-d541-43ad-9fea-dc9eab167d41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521012998 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.521012998
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3434985111
Short name T536
Test name
Test status
Simulation time 65181213 ps
CPU time 1.68 seconds
Started Jun 29 05:34:00 PM PDT 24
Finished Jun 29 05:34:03 PM PDT 24
Peak memory 217804 kb
Host smart-bdcb8dad-fbd3-479f-8e52-31a4eac1c221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434985111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3434985111
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.137972051
Short name T254
Test name
Test status
Simulation time 53178448 ps
CPU time 1.33 seconds
Started Jun 29 05:33:57 PM PDT 24
Finished Jun 29 05:33:59 PM PDT 24
Peak memory 218824 kb
Host smart-a5b43bf2-eb16-4bcb-b60b-7e06e2ecef56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137972051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.137972051
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.711742871
Short name T255
Test name
Test status
Simulation time 62414628 ps
CPU time 1.24 seconds
Started Jun 29 05:33:57 PM PDT 24
Finished Jun 29 05:33:59 PM PDT 24
Peak memory 217572 kb
Host smart-29775ff9-6d83-470d-8597-c26478c4c1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711742871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.711742871
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3353426465
Short name T699
Test name
Test status
Simulation time 240699328 ps
CPU time 3.58 seconds
Started Jun 29 05:34:01 PM PDT 24
Finished Jun 29 05:34:05 PM PDT 24
Peak memory 217740 kb
Host smart-c5d22e1e-0af8-4a86-87fd-81b8054aed35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353426465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3353426465
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.2328481169
Short name T871
Test name
Test status
Simulation time 154563107 ps
CPU time 1.22 seconds
Started Jun 29 05:33:59 PM PDT 24
Finished Jun 29 05:34:01 PM PDT 24
Peak memory 220064 kb
Host smart-74d91417-ff13-454e-9192-170308c607c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328481169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.2328481169
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2812846072
Short name T866
Test name
Test status
Simulation time 46283332 ps
CPU time 1.2 seconds
Started Jun 29 05:33:57 PM PDT 24
Finished Jun 29 05:33:58 PM PDT 24
Peak memory 220256 kb
Host smart-054a950e-63a7-4e84-a880-10ff9b3b65d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812846072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2812846072
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2171921340
Short name T716
Test name
Test status
Simulation time 95720286 ps
CPU time 1.18 seconds
Started Jun 29 05:34:01 PM PDT 24
Finished Jun 29 05:34:03 PM PDT 24
Peak memory 218648 kb
Host smart-ce470cf3-942d-4f37-85f9-383a01e3b1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171921340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2171921340
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3487421871
Short name T509
Test name
Test status
Simulation time 53476048 ps
CPU time 1.66 seconds
Started Jun 29 05:34:02 PM PDT 24
Finished Jun 29 05:34:05 PM PDT 24
Peak memory 218620 kb
Host smart-27acd42b-4f41-461c-9736-329d142cdcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487421871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3487421871
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.528537673
Short name T966
Test name
Test status
Simulation time 36316053 ps
CPU time 1.47 seconds
Started Jun 29 05:34:02 PM PDT 24
Finished Jun 29 05:34:04 PM PDT 24
Peak memory 220252 kb
Host smart-d3c2f71d-4e78-40ac-90d6-55791f639c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528537673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.528537673
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.961312021
Short name T351
Test name
Test status
Simulation time 26098091 ps
CPU time 1.18 seconds
Started Jun 29 05:33:59 PM PDT 24
Finished Jun 29 05:34:01 PM PDT 24
Peak memory 217532 kb
Host smart-3ef1dc92-7696-4f98-bb3c-37ba9ecba5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961312021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.961312021
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1400109477
Short name T581
Test name
Test status
Simulation time 37655913 ps
CPU time 1.2 seconds
Started Jun 29 05:32:27 PM PDT 24
Finished Jun 29 05:32:30 PM PDT 24
Peak memory 220088 kb
Host smart-6fe4f9ee-7310-41fc-9431-5c93c2e1b0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400109477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1400109477
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3721601677
Short name T566
Test name
Test status
Simulation time 20485409 ps
CPU time 1.02 seconds
Started Jun 29 05:32:38 PM PDT 24
Finished Jun 29 05:32:42 PM PDT 24
Peak memory 207052 kb
Host smart-e28f165a-340d-4bf8-acf8-039df9ae8e01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721601677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3721601677
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1379332148
Short name T702
Test name
Test status
Simulation time 31253528 ps
CPU time 1.16 seconds
Started Jun 29 05:32:33 PM PDT 24
Finished Jun 29 05:32:35 PM PDT 24
Peak memory 218820 kb
Host smart-185b4104-094b-44dc-b600-78554fbd0999
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379332148 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1379332148
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_genbits.201342670
Short name T691
Test name
Test status
Simulation time 31019439 ps
CPU time 1.34 seconds
Started Jun 29 05:32:37 PM PDT 24
Finished Jun 29 05:32:40 PM PDT 24
Peak memory 218988 kb
Host smart-86e3e4af-6393-4307-a59a-103376b81d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201342670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.201342670
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.502731311
Short name T603
Test name
Test status
Simulation time 87689895 ps
CPU time 0.92 seconds
Started Jun 29 05:32:39 PM PDT 24
Finished Jun 29 05:32:42 PM PDT 24
Peak memory 215580 kb
Host smart-26934ecc-a556-4405-b725-00d31450190c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502731311 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.502731311
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2520403406
Short name T354
Test name
Test status
Simulation time 55012516 ps
CPU time 0.93 seconds
Started Jun 29 05:32:39 PM PDT 24
Finished Jun 29 05:32:42 PM PDT 24
Peak memory 215620 kb
Host smart-76d938fb-3fae-4bb8-adab-5e53d969318e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520403406 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2520403406
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2250689886
Short name T569
Test name
Test status
Simulation time 279599030 ps
CPU time 5.6 seconds
Started Jun 29 05:32:42 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 217516 kb
Host smart-ef83daf5-58f4-4162-aaf0-32a6cbe86532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250689886 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2250689886
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2413816122
Short name T243
Test name
Test status
Simulation time 75277232903 ps
CPU time 1262.01 seconds
Started Jun 29 05:32:33 PM PDT 24
Finished Jun 29 05:53:36 PM PDT 24
Peak memory 222640 kb
Host smart-57609bda-84d8-4454-880a-94f6e6d3b67f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413816122 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2413816122
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3676071285
Short name T902
Test name
Test status
Simulation time 46310955 ps
CPU time 1.26 seconds
Started Jun 29 05:34:03 PM PDT 24
Finished Jun 29 05:34:05 PM PDT 24
Peak memory 217648 kb
Host smart-bc507164-48a6-4197-889d-9be74c070dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676071285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3676071285
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.853392443
Short name T632
Test name
Test status
Simulation time 108898493 ps
CPU time 1.49 seconds
Started Jun 29 05:33:57 PM PDT 24
Finished Jun 29 05:34:00 PM PDT 24
Peak memory 218872 kb
Host smart-25c16323-fc40-4527-afdb-853e1c33ccd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853392443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.853392443
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.698802173
Short name T937
Test name
Test status
Simulation time 51000310 ps
CPU time 1.36 seconds
Started Jun 29 05:34:02 PM PDT 24
Finished Jun 29 05:34:04 PM PDT 24
Peak memory 219220 kb
Host smart-9a48ad51-b8b3-49eb-9ab2-64dd65e067ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698802173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.698802173
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.767931308
Short name T788
Test name
Test status
Simulation time 308927001 ps
CPU time 1.46 seconds
Started Jun 29 05:33:58 PM PDT 24
Finished Jun 29 05:34:00 PM PDT 24
Peak memory 217856 kb
Host smart-8af5d3d4-0d2f-4517-a4d5-9b2df6332988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767931308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.767931308
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1118587177
Short name T388
Test name
Test status
Simulation time 60269375 ps
CPU time 1.17 seconds
Started Jun 29 05:34:04 PM PDT 24
Finished Jun 29 05:34:05 PM PDT 24
Peak memory 219340 kb
Host smart-270f7821-f683-4940-ac1f-abd4ed752151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118587177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1118587177
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1265886600
Short name T358
Test name
Test status
Simulation time 124919498 ps
CPU time 1.11 seconds
Started Jun 29 05:34:02 PM PDT 24
Finished Jun 29 05:34:03 PM PDT 24
Peak memory 217536 kb
Host smart-59fcdd37-bf36-487d-a9cb-a9a32697311c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265886600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1265886600
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3094880226
Short name T421
Test name
Test status
Simulation time 56365015 ps
CPU time 2.02 seconds
Started Jun 29 05:34:06 PM PDT 24
Finished Jun 29 05:34:09 PM PDT 24
Peak memory 218716 kb
Host smart-f1ea7d2c-2132-429a-8952-40523d638256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094880226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3094880226
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3326896741
Short name T987
Test name
Test status
Simulation time 42218174 ps
CPU time 1.13 seconds
Started Jun 29 05:34:15 PM PDT 24
Finished Jun 29 05:34:17 PM PDT 24
Peak memory 217496 kb
Host smart-61550184-e97f-42cc-b0b2-7b0ee819b209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326896741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3326896741
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2119947375
Short name T506
Test name
Test status
Simulation time 38003592 ps
CPU time 1.08 seconds
Started Jun 29 05:34:08 PM PDT 24
Finished Jun 29 05:34:09 PM PDT 24
Peak memory 217556 kb
Host smart-4e7ce7d8-3cc2-48e0-8bb1-72bc635adad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119947375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2119947375
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2557572514
Short name T785
Test name
Test status
Simulation time 51895283 ps
CPU time 1.87 seconds
Started Jun 29 05:34:19 PM PDT 24
Finished Jun 29 05:34:21 PM PDT 24
Peak memory 217976 kb
Host smart-77dc2812-50a3-40b1-954d-e4d9d6973699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557572514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2557572514
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.3174428090
Short name T432
Test name
Test status
Simulation time 99337015 ps
CPU time 1.29 seconds
Started Jun 29 05:32:35 PM PDT 24
Finished Jun 29 05:32:38 PM PDT 24
Peak memory 215944 kb
Host smart-b07a1ce6-a37b-4a52-a782-40afd235c416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174428090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3174428090
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1048455477
Short name T877
Test name
Test status
Simulation time 12737977 ps
CPU time 0.9 seconds
Started Jun 29 05:32:35 PM PDT 24
Finished Jun 29 05:32:37 PM PDT 24
Peak memory 206976 kb
Host smart-032eaa9e-c03d-4513-8696-a9a30edb3445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048455477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1048455477
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.594775183
Short name T225
Test name
Test status
Simulation time 26370544 ps
CPU time 0.84 seconds
Started Jun 29 05:32:36 PM PDT 24
Finished Jun 29 05:32:39 PM PDT 24
Peak memory 215716 kb
Host smart-e5170b74-6683-4aaa-b3c3-672f6039b8c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594775183 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.594775183
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1759833252
Short name T504
Test name
Test status
Simulation time 60586393 ps
CPU time 0.95 seconds
Started Jun 29 05:32:34 PM PDT 24
Finished Jun 29 05:32:36 PM PDT 24
Peak memory 218564 kb
Host smart-d63b7f3e-275a-42b7-81f3-b153820cdbbc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759833252 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1759833252
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3058950616
Short name T212
Test name
Test status
Simulation time 22000493 ps
CPU time 1.08 seconds
Started Jun 29 05:32:31 PM PDT 24
Finished Jun 29 05:32:32 PM PDT 24
Peak memory 220036 kb
Host smart-e7cb826a-a9ab-47dc-a673-9dc64f3e6175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058950616 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3058950616
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3090496958
Short name T456
Test name
Test status
Simulation time 33928777 ps
CPU time 1.36 seconds
Started Jun 29 05:32:31 PM PDT 24
Finished Jun 29 05:32:33 PM PDT 24
Peak memory 218796 kb
Host smart-363fb9f0-1aaf-46c1-adfa-4dea71afb83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090496958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3090496958
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.4167109153
Short name T101
Test name
Test status
Simulation time 19649682 ps
CPU time 1.08 seconds
Started Jun 29 05:32:36 PM PDT 24
Finished Jun 29 05:32:39 PM PDT 24
Peak memory 216080 kb
Host smart-10f8e3f2-3b9c-4724-9b1e-b562a732ad4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167109153 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.4167109153
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1081196996
Short name T492
Test name
Test status
Simulation time 41108739 ps
CPU time 0.91 seconds
Started Jun 29 05:32:34 PM PDT 24
Finished Jun 29 05:32:36 PM PDT 24
Peak memory 215612 kb
Host smart-f12b179e-c8d0-4234-a8d8-9f3c78e5cb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081196996 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1081196996
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3106207758
Short name T384
Test name
Test status
Simulation time 72737778 ps
CPU time 1.03 seconds
Started Jun 29 05:32:46 PM PDT 24
Finished Jun 29 05:32:49 PM PDT 24
Peak memory 207052 kb
Host smart-640af590-283e-48e3-83f6-4338a73ee159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106207758 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3106207758
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3037154337
Short name T227
Test name
Test status
Simulation time 172646879256 ps
CPU time 1223.83 seconds
Started Jun 29 05:32:36 PM PDT 24
Finished Jun 29 05:53:01 PM PDT 24
Peak memory 225044 kb
Host smart-3ddfc708-c56f-4403-b04d-2e4d172d7493
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037154337 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3037154337
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.797627785
Short name T412
Test name
Test status
Simulation time 77214818 ps
CPU time 1.59 seconds
Started Jun 29 05:34:09 PM PDT 24
Finished Jun 29 05:34:11 PM PDT 24
Peak memory 218960 kb
Host smart-23d9b32f-cd2f-428f-b6e5-94fbc770a975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797627785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.797627785
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2085265881
Short name T12
Test name
Test status
Simulation time 150088309 ps
CPU time 1.22 seconds
Started Jun 29 05:34:09 PM PDT 24
Finished Jun 29 05:34:11 PM PDT 24
Peak memory 220608 kb
Host smart-691ed953-ca4d-4bee-92a4-80d39c06cddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085265881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2085265881
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2437582915
Short name T801
Test name
Test status
Simulation time 72424353 ps
CPU time 1.1 seconds
Started Jun 29 05:34:14 PM PDT 24
Finished Jun 29 05:34:16 PM PDT 24
Peak memory 217572 kb
Host smart-985f3c1d-5e5e-45c9-ad26-8a1842f06375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437582915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2437582915
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1719357972
Short name T739
Test name
Test status
Simulation time 71801175 ps
CPU time 1.19 seconds
Started Jun 29 05:34:19 PM PDT 24
Finished Jun 29 05:34:20 PM PDT 24
Peak memory 217604 kb
Host smart-166e25e1-9d71-48d5-9755-4f1c3039b15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719357972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1719357972
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1552423935
Short name T789
Test name
Test status
Simulation time 111273759 ps
CPU time 2.66 seconds
Started Jun 29 05:34:10 PM PDT 24
Finished Jun 29 05:34:13 PM PDT 24
Peak memory 220520 kb
Host smart-3a212d04-0201-4c70-b238-2ac882d0dd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552423935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1552423935
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.373900228
Short name T927
Test name
Test status
Simulation time 40623869 ps
CPU time 1.1 seconds
Started Jun 29 05:34:11 PM PDT 24
Finished Jun 29 05:34:12 PM PDT 24
Peak memory 217444 kb
Host smart-ea3f9e6e-cfdb-4373-9401-9e26129004ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373900228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.373900228
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.261370527
Short name T957
Test name
Test status
Simulation time 32959813 ps
CPU time 1.49 seconds
Started Jun 29 05:34:09 PM PDT 24
Finished Jun 29 05:34:11 PM PDT 24
Peak memory 217692 kb
Host smart-2d8f31f1-a753-4c44-9bf8-e15f58eb1cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261370527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.261370527
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.4128559013
Short name T392
Test name
Test status
Simulation time 32437774 ps
CPU time 1.32 seconds
Started Jun 29 05:34:12 PM PDT 24
Finished Jun 29 05:34:14 PM PDT 24
Peak memory 217588 kb
Host smart-0ef4a27a-6a39-40e9-aa35-ede5e6e7565a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128559013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.4128559013
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1119864046
Short name T512
Test name
Test status
Simulation time 65493627 ps
CPU time 1.18 seconds
Started Jun 29 05:34:14 PM PDT 24
Finished Jun 29 05:34:15 PM PDT 24
Peak memory 217596 kb
Host smart-24d506e3-3dd4-4929-a103-52b29a9d090d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119864046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1119864046
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1135202153
Short name T968
Test name
Test status
Simulation time 48639043 ps
CPU time 1.19 seconds
Started Jun 29 05:34:15 PM PDT 24
Finished Jun 29 05:34:17 PM PDT 24
Peak memory 218920 kb
Host smart-dc095870-7e17-4bce-a32f-fe02f7184d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135202153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1135202153
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2680165792
Short name T952
Test name
Test status
Simulation time 337485355 ps
CPU time 1.3 seconds
Started Jun 29 05:31:56 PM PDT 24
Finished Jun 29 05:31:58 PM PDT 24
Peak memory 218816 kb
Host smart-bf1b0fd8-ed5e-441a-a226-1f19aaa07ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680165792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2680165792
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1168198397
Short name T426
Test name
Test status
Simulation time 24884273 ps
CPU time 0.91 seconds
Started Jun 29 05:31:39 PM PDT 24
Finished Jun 29 05:31:40 PM PDT 24
Peak memory 215168 kb
Host smart-19d82282-41c4-44e8-b3eb-617daad5ac54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168198397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1168198397
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2211513725
Short name T652
Test name
Test status
Simulation time 10463971 ps
CPU time 0.88 seconds
Started Jun 29 05:31:43 PM PDT 24
Finished Jun 29 05:31:45 PM PDT 24
Peak memory 216344 kb
Host smart-87cb6d62-9832-4545-944d-262f0d16f61e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211513725 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2211513725
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1916681395
Short name T247
Test name
Test status
Simulation time 29712211 ps
CPU time 1.13 seconds
Started Jun 29 05:31:44 PM PDT 24
Finished Jun 29 05:31:46 PM PDT 24
Peak memory 218768 kb
Host smart-6efe7ded-2bc1-4cf3-b747-2da127b92c5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916681395 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1916681395
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3308299619
Short name T116
Test name
Test status
Simulation time 34124768 ps
CPU time 1.03 seconds
Started Jun 29 05:31:38 PM PDT 24
Finished Jun 29 05:31:39 PM PDT 24
Peak memory 229940 kb
Host smart-03579e94-2e3a-4b69-b08b-e0e56ca81ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308299619 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3308299619
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.4152341910
Short name T614
Test name
Test status
Simulation time 44994070 ps
CPU time 1.5 seconds
Started Jun 29 05:31:44 PM PDT 24
Finished Jun 29 05:31:46 PM PDT 24
Peak memory 217764 kb
Host smart-272d125f-cf31-47e7-bdfb-52741c86b3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152341910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.4152341910
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2205498167
Short name T795
Test name
Test status
Simulation time 28325506 ps
CPU time 0.99 seconds
Started Jun 29 05:31:43 PM PDT 24
Finished Jun 29 05:31:44 PM PDT 24
Peak memory 215816 kb
Host smart-a4ae11c9-9f2d-4ec6-9249-104b372e5858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205498167 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2205498167
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.3012970767
Short name T22
Test name
Test status
Simulation time 27214379 ps
CPU time 0.99 seconds
Started Jun 29 05:31:39 PM PDT 24
Finished Jun 29 05:31:40 PM PDT 24
Peak memory 207416 kb
Host smart-87b607c8-0022-41fc-aa90-98a36b717b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012970767 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3012970767
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.945270804
Short name T19
Test name
Test status
Simulation time 1750198866 ps
CPU time 7.44 seconds
Started Jun 29 05:31:49 PM PDT 24
Finished Jun 29 05:31:58 PM PDT 24
Peak memory 237900 kb
Host smart-1e0433a2-4190-4097-924a-37b21cdc8d24
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945270804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.945270804
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3065133950
Short name T634
Test name
Test status
Simulation time 14795340 ps
CPU time 0.95 seconds
Started Jun 29 05:31:45 PM PDT 24
Finished Jun 29 05:31:47 PM PDT 24
Peak memory 215572 kb
Host smart-4c561116-a3f3-4c62-843d-127614a05be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065133950 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3065133950
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.4222477023
Short name T815
Test name
Test status
Simulation time 155499502 ps
CPU time 3.4 seconds
Started Jun 29 05:31:45 PM PDT 24
Finished Jun 29 05:31:50 PM PDT 24
Peak memory 218772 kb
Host smart-651e01cc-4899-479e-ad01-ddb9ca18aa07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222477023 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.4222477023
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3653415404
Short name T333
Test name
Test status
Simulation time 235309649314 ps
CPU time 999.73 seconds
Started Jun 29 05:31:41 PM PDT 24
Finished Jun 29 05:48:22 PM PDT 24
Peak memory 232200 kb
Host smart-59f59599-1cb4-4f04-a7da-29a14952b071
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653415404 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3653415404
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3160477061
Short name T551
Test name
Test status
Simulation time 26648171 ps
CPU time 1.19 seconds
Started Jun 29 05:32:40 PM PDT 24
Finished Jun 29 05:32:43 PM PDT 24
Peak memory 219868 kb
Host smart-68289056-ffff-4258-907b-07736592a4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160477061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3160477061
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1618798847
Short name T578
Test name
Test status
Simulation time 13593225 ps
CPU time 0.9 seconds
Started Jun 29 05:32:36 PM PDT 24
Finished Jun 29 05:32:39 PM PDT 24
Peak memory 206996 kb
Host smart-42575117-d4be-4290-8df9-0dc768b6612f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618798847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1618798847
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1491877372
Short name T635
Test name
Test status
Simulation time 36329630 ps
CPU time 0.86 seconds
Started Jun 29 05:32:30 PM PDT 24
Finished Jun 29 05:32:31 PM PDT 24
Peak memory 215672 kb
Host smart-8f5fa41b-72b9-46d9-9fd5-111f79b4fd22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491877372 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1491877372
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.285387483
Short name T309
Test name
Test status
Simulation time 52291269 ps
CPU time 1.15 seconds
Started Jun 29 05:32:46 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 217252 kb
Host smart-be0d7e99-162d-4034-82bc-d464f51c32df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285387483 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.285387483
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.4251147851
Short name T204
Test name
Test status
Simulation time 25100998 ps
CPU time 1.04 seconds
Started Jun 29 05:32:32 PM PDT 24
Finished Jun 29 05:32:35 PM PDT 24
Peak memory 224252 kb
Host smart-8f50eb30-0010-40d7-a710-443381c0de03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251147851 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.4251147851
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3671948866
Short name T332
Test name
Test status
Simulation time 189290789 ps
CPU time 2.51 seconds
Started Jun 29 05:32:30 PM PDT 24
Finished Jun 29 05:32:33 PM PDT 24
Peak memory 220428 kb
Host smart-66c59709-acc3-4a79-8911-547ae7a86734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671948866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3671948866
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2113753825
Short name T969
Test name
Test status
Simulation time 27104772 ps
CPU time 1.05 seconds
Started Jun 29 05:32:32 PM PDT 24
Finished Jun 29 05:32:34 PM PDT 24
Peak memory 224352 kb
Host smart-eda7cb2a-986a-4c2f-a824-6e0f3a305846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113753825 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2113753825
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3293525571
Short name T444
Test name
Test status
Simulation time 24670522 ps
CPU time 0.95 seconds
Started Jun 29 05:32:45 PM PDT 24
Finished Jun 29 05:32:49 PM PDT 24
Peak memory 207412 kb
Host smart-5128c1a8-6697-48f0-ac0e-613c189068b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293525571 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3293525571
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2112014378
Short name T70
Test name
Test status
Simulation time 2798357094 ps
CPU time 4.51 seconds
Started Jun 29 05:32:35 PM PDT 24
Finished Jun 29 05:32:40 PM PDT 24
Peak memory 217896 kb
Host smart-5c80d0fb-ac43-4809-a9d5-f9e740cefadf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112014378 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2112014378
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3541561890
Short name T235
Test name
Test status
Simulation time 165164191305 ps
CPU time 2053.93 seconds
Started Jun 29 05:32:29 PM PDT 24
Finished Jun 29 06:06:43 PM PDT 24
Peak memory 225932 kb
Host smart-b161a044-ebb6-4ee9-a6fd-90020df37e28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541561890 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3541561890
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2859056899
Short name T844
Test name
Test status
Simulation time 29572739 ps
CPU time 1.33 seconds
Started Jun 29 05:32:30 PM PDT 24
Finished Jun 29 05:32:31 PM PDT 24
Peak memory 215916 kb
Host smart-6b219e9a-0b2b-46a5-a776-cb272222eb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859056899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2859056899
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.4269826113
Short name T378
Test name
Test status
Simulation time 63468810 ps
CPU time 0.97 seconds
Started Jun 29 05:32:30 PM PDT 24
Finished Jun 29 05:32:31 PM PDT 24
Peak memory 215396 kb
Host smart-feff1a9d-cd9d-47f7-8d65-5522b8a50662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269826113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.4269826113
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.1768479169
Short name T757
Test name
Test status
Simulation time 12611163 ps
CPU time 0.89 seconds
Started Jun 29 05:32:35 PM PDT 24
Finished Jun 29 05:32:37 PM PDT 24
Peak memory 216340 kb
Host smart-5fba05b0-737f-4c1d-a8fb-7733d14b3c0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768479169 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1768479169
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1109762851
Short name T623
Test name
Test status
Simulation time 69093628 ps
CPU time 1.22 seconds
Started Jun 29 05:32:32 PM PDT 24
Finished Jun 29 05:32:35 PM PDT 24
Peak memory 217112 kb
Host smart-323c7815-724c-496b-b853-108b23befa6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109762851 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1109762851
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3366492081
Short name T201
Test name
Test status
Simulation time 48322537 ps
CPU time 1.16 seconds
Started Jun 29 05:32:49 PM PDT 24
Finished Jun 29 05:32:52 PM PDT 24
Peak memory 219824 kb
Host smart-bd192fea-56ff-4a9e-956e-e1ea70e8449f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366492081 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3366492081
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.4140409421
Short name T525
Test name
Test status
Simulation time 47812752 ps
CPU time 1.82 seconds
Started Jun 29 05:32:42 PM PDT 24
Finished Jun 29 05:32:46 PM PDT 24
Peak memory 219132 kb
Host smart-a573048b-4d28-4868-9ddc-a49f0aa6dab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140409421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.4140409421
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_smoke.32577068
Short name T386
Test name
Test status
Simulation time 38052667 ps
CPU time 0.91 seconds
Started Jun 29 05:32:33 PM PDT 24
Finished Jun 29 05:32:35 PM PDT 24
Peak memory 215608 kb
Host smart-02c5bd4d-eff9-4b83-ab55-df1a96cec2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32577068 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.32577068
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3272768281
Short name T756
Test name
Test status
Simulation time 767961697 ps
CPU time 4.9 seconds
Started Jun 29 05:32:44 PM PDT 24
Finished Jun 29 05:32:51 PM PDT 24
Peak memory 217816 kb
Host smart-9872fe68-fbc1-4f57-8201-ea080348e4fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272768281 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3272768281
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3889000445
Short name T236
Test name
Test status
Simulation time 113434604762 ps
CPU time 1427.14 seconds
Started Jun 29 05:32:34 PM PDT 24
Finished Jun 29 05:56:23 PM PDT 24
Peak memory 224240 kb
Host smart-b0cc236f-b6d5-4e98-a6e2-b1bc43600012
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889000445 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3889000445
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3510486349
Short name T621
Test name
Test status
Simulation time 81563048 ps
CPU time 1.23 seconds
Started Jun 29 05:32:38 PM PDT 24
Finished Jun 29 05:32:42 PM PDT 24
Peak memory 218828 kb
Host smart-047621da-dd41-4f48-9e92-2a037c9287d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510486349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3510486349
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.598924588
Short name T400
Test name
Test status
Simulation time 26709968 ps
CPU time 0.9 seconds
Started Jun 29 05:32:45 PM PDT 24
Finished Jun 29 05:32:49 PM PDT 24
Peak memory 215208 kb
Host smart-acfac99d-a24b-44ac-85e7-00bd1928d761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598924588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.598924588
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3686549809
Short name T93
Test name
Test status
Simulation time 36295703 ps
CPU time 1.31 seconds
Started Jun 29 05:32:43 PM PDT 24
Finished Jun 29 05:32:47 PM PDT 24
Peak memory 217336 kb
Host smart-a39ac059-eaf6-4ca5-b963-53e7c65d8aec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686549809 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3686549809
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2115780552
Short name T181
Test name
Test status
Simulation time 29613066 ps
CPU time 0.88 seconds
Started Jun 29 05:32:33 PM PDT 24
Finished Jun 29 05:32:36 PM PDT 24
Peak memory 218732 kb
Host smart-a2b78cd0-ea25-4fdf-b360-7151099a2738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115780552 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2115780552
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.4163537427
Short name T344
Test name
Test status
Simulation time 52019926 ps
CPU time 1.46 seconds
Started Jun 29 05:32:32 PM PDT 24
Finished Jun 29 05:32:34 PM PDT 24
Peak memory 219008 kb
Host smart-d67745ea-f466-40e8-ae38-8b6b2002d944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163537427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.4163537427
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.4148064514
Short name T737
Test name
Test status
Simulation time 24822219 ps
CPU time 0.99 seconds
Started Jun 29 05:32:34 PM PDT 24
Finished Jun 29 05:32:36 PM PDT 24
Peak memory 215800 kb
Host smart-f32ff968-d496-43e6-8d9e-0e95b12afded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148064514 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.4148064514
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.823044216
Short name T399
Test name
Test status
Simulation time 22653525 ps
CPU time 0.93 seconds
Started Jun 29 05:32:37 PM PDT 24
Finished Jun 29 05:32:40 PM PDT 24
Peak memory 215592 kb
Host smart-b80bf848-075a-42f4-adda-dfb60b071df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823044216 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.823044216
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1141745016
Short name T659
Test name
Test status
Simulation time 254078466 ps
CPU time 1.98 seconds
Started Jun 29 05:32:36 PM PDT 24
Finished Jun 29 05:32:39 PM PDT 24
Peak memory 215544 kb
Host smart-6db0c50f-daa0-4e7f-88af-d0f95f21a1c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141745016 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1141745016
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.811619438
Short name T951
Test name
Test status
Simulation time 233929048770 ps
CPU time 1608.83 seconds
Started Jun 29 05:32:35 PM PDT 24
Finished Jun 29 05:59:25 PM PDT 24
Peak memory 226708 kb
Host smart-19cbbe9f-1191-4513-b07f-1f8d4dde2356
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811619438 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.811619438
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.82204015
Short name T642
Test name
Test status
Simulation time 30268428 ps
CPU time 1.25 seconds
Started Jun 29 05:32:32 PM PDT 24
Finished Jun 29 05:32:35 PM PDT 24
Peak memory 216004 kb
Host smart-175d28c1-3bea-4194-afa5-e46767d8641a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82204015 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.82204015
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2258114684
Short name T470
Test name
Test status
Simulation time 60222464 ps
CPU time 0.89 seconds
Started Jun 29 05:32:36 PM PDT 24
Finished Jun 29 05:32:38 PM PDT 24
Peak memory 206984 kb
Host smart-de0ed851-a6c8-4d68-ae16-8069563be69c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258114684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2258114684
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.110121293
Short name T457
Test name
Test status
Simulation time 29867856 ps
CPU time 0.87 seconds
Started Jun 29 05:32:35 PM PDT 24
Finished Jun 29 05:32:38 PM PDT 24
Peak memory 215708 kb
Host smart-92319b8d-3026-4930-ae92-1dd71b47995b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110121293 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.110121293
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_err.3644857506
Short name T9
Test name
Test status
Simulation time 32801073 ps
CPU time 1.07 seconds
Started Jun 29 05:32:35 PM PDT 24
Finished Jun 29 05:32:38 PM PDT 24
Peak memory 220788 kb
Host smart-57e784bd-4358-4e45-a8a1-ee87df08ec09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644857506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3644857506
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3441942614
Short name T694
Test name
Test status
Simulation time 47425258 ps
CPU time 1.59 seconds
Started Jun 29 05:32:30 PM PDT 24
Finished Jun 29 05:32:32 PM PDT 24
Peak memory 217764 kb
Host smart-ae48d139-8a60-4f76-a8a9-c4ad50e490ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441942614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3441942614
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1882741191
Short name T992
Test name
Test status
Simulation time 31889006 ps
CPU time 0.98 seconds
Started Jun 29 05:32:46 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 224096 kb
Host smart-febf9469-5df8-4500-a98e-20a5b6ac1caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882741191 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1882741191
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1848892644
Short name T988
Test name
Test status
Simulation time 19404882 ps
CPU time 0.94 seconds
Started Jun 29 05:32:33 PM PDT 24
Finished Jun 29 05:32:35 PM PDT 24
Peak memory 215600 kb
Host smart-8596c0cd-2f2a-4e81-8dd9-3b8ae6b78d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848892644 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1848892644
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3389432081
Short name T590
Test name
Test status
Simulation time 99938575 ps
CPU time 1.71 seconds
Started Jun 29 05:32:30 PM PDT 24
Finished Jun 29 05:32:33 PM PDT 24
Peak memory 215588 kb
Host smart-482cec2b-10b3-4276-b5e5-7ebcf7714375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389432081 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3389432081
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_alert.3297954433
Short name T251
Test name
Test status
Simulation time 136490208 ps
CPU time 1.25 seconds
Started Jun 29 05:32:38 PM PDT 24
Finished Jun 29 05:32:41 PM PDT 24
Peak memory 220044 kb
Host smart-018c697b-c01f-4607-8e03-790dfa0d1f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297954433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3297954433
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.645294656
Short name T730
Test name
Test status
Simulation time 20403743 ps
CPU time 0.98 seconds
Started Jun 29 05:32:46 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 207028 kb
Host smart-11c4f5d0-8806-4d55-b7e1-8d1d968ae394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645294656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.645294656
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_err.4264879572
Short name T57
Test name
Test status
Simulation time 59828061 ps
CPU time 1.15 seconds
Started Jun 29 05:32:48 PM PDT 24
Finished Jun 29 05:32:52 PM PDT 24
Peak memory 232440 kb
Host smart-31f56bec-99d9-4108-9025-c6cfb174a74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264879572 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.4264879572
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1738499925
Short name T46
Test name
Test status
Simulation time 269247219 ps
CPU time 1.71 seconds
Started Jun 29 05:32:42 PM PDT 24
Finished Jun 29 05:32:45 PM PDT 24
Peak memory 219224 kb
Host smart-870eb902-0585-41de-a304-765139de8f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738499925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1738499925
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1224348983
Short name T98
Test name
Test status
Simulation time 32188622 ps
CPU time 0.87 seconds
Started Jun 29 05:32:47 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 216048 kb
Host smart-46bc3958-64e2-49dd-89e0-d62e1ae745a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224348983 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1224348983
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3856207325
Short name T234
Test name
Test status
Simulation time 40034236 ps
CPU time 0.92 seconds
Started Jun 29 05:32:47 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 215600 kb
Host smart-2841f9a1-f350-4260-9e55-28d7808080ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856207325 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3856207325
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.251605807
Short name T364
Test name
Test status
Simulation time 51119078 ps
CPU time 1.6 seconds
Started Jun 29 05:32:38 PM PDT 24
Finished Jun 29 05:32:42 PM PDT 24
Peak memory 218804 kb
Host smart-c2d06389-00cc-4898-befb-59532933fae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251605807 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.251605807
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2212282660
Short name T811
Test name
Test status
Simulation time 29215519002 ps
CPU time 660.68 seconds
Started Jun 29 05:32:42 PM PDT 24
Finished Jun 29 05:43:45 PM PDT 24
Peak memory 218844 kb
Host smart-42a02500-9579-40ef-b4dd-bca91b697b48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212282660 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2212282660
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3363323172
Short name T219
Test name
Test status
Simulation time 66676197 ps
CPU time 1.19 seconds
Started Jun 29 05:32:38 PM PDT 24
Finished Jun 29 05:32:42 PM PDT 24
Peak memory 218712 kb
Host smart-19920daf-325c-4773-bdb5-e12720a79c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363323172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3363323172
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1704695784
Short name T819
Test name
Test status
Simulation time 37224031 ps
CPU time 0.92 seconds
Started Jun 29 05:32:46 PM PDT 24
Finished Jun 29 05:32:49 PM PDT 24
Peak memory 206988 kb
Host smart-2bda2c41-d879-4611-a360-f043828c3fb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704695784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1704695784
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3805381961
Short name T211
Test name
Test status
Simulation time 11914198 ps
CPU time 0.95 seconds
Started Jun 29 05:32:32 PM PDT 24
Finished Jun 29 05:32:34 PM PDT 24
Peak memory 216732 kb
Host smart-b1bdabb7-1c32-4ab0-a29a-4e5b172f9787
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805381961 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3805381961
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.4123694448
Short name T818
Test name
Test status
Simulation time 60822484 ps
CPU time 1.2 seconds
Started Jun 29 05:32:45 PM PDT 24
Finished Jun 29 05:32:48 PM PDT 24
Peak memory 219976 kb
Host smart-3a7f1b99-200e-493d-a132-2f094979a31a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123694448 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.4123694448
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2016077042
Short name T153
Test name
Test status
Simulation time 31165300 ps
CPU time 1.19 seconds
Started Jun 29 05:32:39 PM PDT 24
Finished Jun 29 05:32:42 PM PDT 24
Peak memory 229764 kb
Host smart-199c87d2-338e-4aca-897f-c03bd64a17ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016077042 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2016077042
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.640789904
Short name T684
Test name
Test status
Simulation time 87525931 ps
CPU time 1.19 seconds
Started Jun 29 05:32:33 PM PDT 24
Finished Jun 29 05:32:36 PM PDT 24
Peak memory 217520 kb
Host smart-5b55500f-08b5-4491-8835-7a1885eab3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640789904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.640789904
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3104836651
Short name T706
Test name
Test status
Simulation time 31768166 ps
CPU time 1.04 seconds
Started Jun 29 05:32:40 PM PDT 24
Finished Jun 29 05:32:43 PM PDT 24
Peak memory 224132 kb
Host smart-cfd7da78-7f82-4c1f-bf56-3f8dadf26b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104836651 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3104836651
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3654227118
Short name T395
Test name
Test status
Simulation time 32630871 ps
CPU time 0.94 seconds
Started Jun 29 05:32:35 PM PDT 24
Finished Jun 29 05:32:37 PM PDT 24
Peak memory 215600 kb
Host smart-6f48f578-58e6-40a2-bd6b-eda9eeddb0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654227118 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3654227118
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.88263755
Short name T368
Test name
Test status
Simulation time 504672717 ps
CPU time 2.09 seconds
Started Jun 29 05:32:37 PM PDT 24
Finished Jun 29 05:32:41 PM PDT 24
Peak memory 207464 kb
Host smart-998e8c26-fbcd-4458-9e1d-bffc341b055c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88263755 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.88263755
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1921409498
Short name T802
Test name
Test status
Simulation time 121408358230 ps
CPU time 1599.43 seconds
Started Jun 29 05:32:41 PM PDT 24
Finished Jun 29 05:59:22 PM PDT 24
Peak memory 227872 kb
Host smart-5bf0afd8-f4d5-4387-8c96-e41f74f7b930
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921409498 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1921409498
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.911146980
Short name T143
Test name
Test status
Simulation time 28716269 ps
CPU time 1.31 seconds
Started Jun 29 05:32:43 PM PDT 24
Finished Jun 29 05:32:46 PM PDT 24
Peak memory 221164 kb
Host smart-78dda86c-4d56-4be0-bd0a-28065e614fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911146980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.911146980
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2281374402
Short name T76
Test name
Test status
Simulation time 55938495 ps
CPU time 0.84 seconds
Started Jun 29 05:32:37 PM PDT 24
Finished Jun 29 05:32:39 PM PDT 24
Peak memory 206816 kb
Host smart-83b75b47-d2d0-47ad-a3bb-d6e1ceef7acc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281374402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2281374402
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1440528671
Short name T433
Test name
Test status
Simulation time 44043598 ps
CPU time 0.87 seconds
Started Jun 29 05:32:47 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 216540 kb
Host smart-97d2729c-b42a-49f1-88e0-b79f4efa24db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440528671 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1440528671
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_err.2280247172
Short name T541
Test name
Test status
Simulation time 31498668 ps
CPU time 1.05 seconds
Started Jun 29 05:32:44 PM PDT 24
Finished Jun 29 05:32:47 PM PDT 24
Peak memory 220020 kb
Host smart-3777c796-6db3-4958-8e2c-1ab266e7c927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280247172 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2280247172
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1412437872
Short name T43
Test name
Test status
Simulation time 89049873 ps
CPU time 1.21 seconds
Started Jun 29 05:32:39 PM PDT 24
Finished Jun 29 05:32:43 PM PDT 24
Peak memory 219260 kb
Host smart-87707ab9-68e7-400b-974b-a4a6e9a02620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412437872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1412437872
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3957921962
Short name T97
Test name
Test status
Simulation time 27655215 ps
CPU time 0.89 seconds
Started Jun 29 05:32:36 PM PDT 24
Finished Jun 29 05:32:38 PM PDT 24
Peak memory 215964 kb
Host smart-631a252f-5aec-4688-8224-f20a97d23406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957921962 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3957921962
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1456684903
Short name T911
Test name
Test status
Simulation time 59295773 ps
CPU time 0.95 seconds
Started Jun 29 05:32:38 PM PDT 24
Finished Jun 29 05:32:40 PM PDT 24
Peak memory 215608 kb
Host smart-ead4b74c-9774-4830-87b7-412f36647e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456684903 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1456684903
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.829578104
Short name T640
Test name
Test status
Simulation time 57776440 ps
CPU time 0.95 seconds
Started Jun 29 05:32:37 PM PDT 24
Finished Jun 29 05:32:40 PM PDT 24
Peak memory 206688 kb
Host smart-4e16da33-a246-4405-b3a3-c6e7c3f63483
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829578104 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.829578104
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.416173684
Short name T797
Test name
Test status
Simulation time 241782642127 ps
CPU time 1601.48 seconds
Started Jun 29 05:32:39 PM PDT 24
Finished Jun 29 05:59:23 PM PDT 24
Peak memory 227356 kb
Host smart-69d98dbe-ebe4-480d-b57d-d635d68da82b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416173684 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.416173684
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.936921503
Short name T772
Test name
Test status
Simulation time 190626314 ps
CPU time 1.2 seconds
Started Jun 29 05:32:32 PM PDT 24
Finished Jun 29 05:32:34 PM PDT 24
Peak memory 219532 kb
Host smart-41a1b689-2492-4d08-8dbf-fffeb750bec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936921503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.936921503
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2320677018
Short name T546
Test name
Test status
Simulation time 30555059 ps
CPU time 0.81 seconds
Started Jun 29 05:32:36 PM PDT 24
Finished Jun 29 05:32:38 PM PDT 24
Peak memory 206660 kb
Host smart-01a18dfc-a74d-4a6d-9a36-ccbc6dc1b966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320677018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2320677018
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.266079619
Short name T861
Test name
Test status
Simulation time 12493007 ps
CPU time 0.9 seconds
Started Jun 29 05:32:33 PM PDT 24
Finished Jun 29 05:32:35 PM PDT 24
Peak memory 216740 kb
Host smart-425f821e-6ed4-4beb-84ec-bd67805c6e30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266079619 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.266079619
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1200918326
Short name T435
Test name
Test status
Simulation time 27756076 ps
CPU time 1.45 seconds
Started Jun 29 05:32:43 PM PDT 24
Finished Jun 29 05:32:48 PM PDT 24
Peak memory 217112 kb
Host smart-9b86456e-ae1d-45fa-a21f-aa84030a3aec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200918326 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1200918326
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3068120697
Short name T791
Test name
Test status
Simulation time 30411600 ps
CPU time 1.3 seconds
Started Jun 29 05:32:47 PM PDT 24
Finished Jun 29 05:32:51 PM PDT 24
Peak memory 225780 kb
Host smart-edc646dd-7f9a-4dab-9226-efa0353fc4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068120697 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3068120697
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1932279791
Short name T683
Test name
Test status
Simulation time 40635852 ps
CPU time 1.54 seconds
Started Jun 29 05:32:39 PM PDT 24
Finished Jun 29 05:32:43 PM PDT 24
Peak memory 219644 kb
Host smart-e0f19c8c-e332-44f8-9a2e-24312b8d5679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932279791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1932279791
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.334725250
Short name T650
Test name
Test status
Simulation time 33650526 ps
CPU time 0.85 seconds
Started Jun 29 05:32:36 PM PDT 24
Finished Jun 29 05:32:39 PM PDT 24
Peak memory 215916 kb
Host smart-828b370e-f71a-49ea-bc01-2cf946790050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334725250 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.334725250
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1486873899
Short name T980
Test name
Test status
Simulation time 31116565 ps
CPU time 0.95 seconds
Started Jun 29 05:32:35 PM PDT 24
Finished Jun 29 05:32:37 PM PDT 24
Peak memory 215520 kb
Host smart-09335c44-c5c1-43e3-90e4-aee21a1d454e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486873899 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1486873899
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2256996492
Short name T102
Test name
Test status
Simulation time 502607907 ps
CPU time 5.17 seconds
Started Jun 29 05:32:39 PM PDT 24
Finished Jun 29 05:32:46 PM PDT 24
Peak memory 217504 kb
Host smart-f0b80e86-69ea-4a94-8a10-18b314d494f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256996492 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2256996492
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.870493309
Short name T638
Test name
Test status
Simulation time 27574271462 ps
CPU time 356.66 seconds
Started Jun 29 05:32:49 PM PDT 24
Finished Jun 29 05:38:48 PM PDT 24
Peak memory 224064 kb
Host smart-bf71c185-f8cd-4131-aa83-0a878e2c25e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870493309 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.870493309
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3753248382
Short name T257
Test name
Test status
Simulation time 31930112 ps
CPU time 1.37 seconds
Started Jun 29 05:32:39 PM PDT 24
Finished Jun 29 05:32:43 PM PDT 24
Peak memory 220200 kb
Host smart-b9d68ecc-6884-4344-ba37-86c9f25ba754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753248382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3753248382
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.754660837
Short name T359
Test name
Test status
Simulation time 19286774 ps
CPU time 1.01 seconds
Started Jun 29 05:32:42 PM PDT 24
Finished Jun 29 05:32:46 PM PDT 24
Peak memory 215152 kb
Host smart-2e0bfb66-b5c8-4e40-9176-9f3aa263911c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754660837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.754660837
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.4065188907
Short name T565
Test name
Test status
Simulation time 43460541 ps
CPU time 0.86 seconds
Started Jun 29 05:32:38 PM PDT 24
Finished Jun 29 05:32:41 PM PDT 24
Peak memory 216340 kb
Host smart-d22be4b5-8366-4e2d-92d3-2022c1f7c921
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065188907 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.4065188907
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1653858200
Short name T206
Test name
Test status
Simulation time 135216277 ps
CPU time 1.29 seconds
Started Jun 29 05:32:49 PM PDT 24
Finished Jun 29 05:32:52 PM PDT 24
Peak memory 218640 kb
Host smart-c8d0c6b3-b0a1-4c06-8df1-97ab0e443f5c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653858200 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1653858200
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.554676316
Short name T374
Test name
Test status
Simulation time 18831297 ps
CPU time 1.02 seconds
Started Jun 29 05:32:38 PM PDT 24
Finished Jun 29 05:32:41 PM PDT 24
Peak memory 218384 kb
Host smart-58e2137a-c5f3-4aa8-baf7-cee15d8ecab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554676316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.554676316
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2187681575
Short name T483
Test name
Test status
Simulation time 47500365 ps
CPU time 1.71 seconds
Started Jun 29 05:32:46 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 219324 kb
Host smart-414b51b0-b550-4745-9847-3781b2f9469c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187681575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2187681575
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.4056098959
Short name T964
Test name
Test status
Simulation time 31644355 ps
CPU time 0.95 seconds
Started Jun 29 05:32:43 PM PDT 24
Finished Jun 29 05:32:47 PM PDT 24
Peak memory 215772 kb
Host smart-780defea-01da-4081-8592-2f32668ea0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056098959 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.4056098959
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1717042860
Short name T427
Test name
Test status
Simulation time 30329911 ps
CPU time 0.97 seconds
Started Jun 29 05:32:38 PM PDT 24
Finished Jun 29 05:32:41 PM PDT 24
Peak memory 215560 kb
Host smart-5770745c-c828-49c8-97d1-766498e0d0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717042860 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1717042860
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2020817707
Short name T408
Test name
Test status
Simulation time 26833323 ps
CPU time 0.97 seconds
Started Jun 29 05:32:55 PM PDT 24
Finished Jun 29 05:32:57 PM PDT 24
Peak memory 206816 kb
Host smart-df0580d4-9e83-4bb0-a4b5-e85c1582c1aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020817707 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2020817707
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3617453172
Short name T535
Test name
Test status
Simulation time 91646270623 ps
CPU time 586.91 seconds
Started Jun 29 05:32:42 PM PDT 24
Finished Jun 29 05:42:31 PM PDT 24
Peak memory 220604 kb
Host smart-b36f8e17-cbe8-42b8-a6ba-2fdee60c3113
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617453172 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3617453172
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3124427596
Short name T986
Test name
Test status
Simulation time 66563414 ps
CPU time 1.14 seconds
Started Jun 29 05:32:38 PM PDT 24
Finished Jun 29 05:32:41 PM PDT 24
Peak memory 219716 kb
Host smart-0231c9fa-3dec-447b-8a79-63b69f1c932b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124427596 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3124427596
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1584562656
Short name T380
Test name
Test status
Simulation time 26349444 ps
CPU time 0.86 seconds
Started Jun 29 05:32:46 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 207072 kb
Host smart-bb2b2a46-87d0-4fc2-aa73-266451a72b95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584562656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1584562656
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_err.608173768
Short name T122
Test name
Test status
Simulation time 63385468 ps
CPU time 1.2 seconds
Started Jun 29 05:32:50 PM PDT 24
Finished Jun 29 05:32:53 PM PDT 24
Peak memory 229968 kb
Host smart-62ad0ffb-6f7d-403e-a7b4-b25b760229ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608173768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.608173768
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3301771779
Short name T758
Test name
Test status
Simulation time 65744838 ps
CPU time 2.28 seconds
Started Jun 29 05:32:48 PM PDT 24
Finished Jun 29 05:32:52 PM PDT 24
Peak memory 220248 kb
Host smart-ecc36302-3e0b-49e7-9a94-3e9af322ecd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301771779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3301771779
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1983838534
Short name T745
Test name
Test status
Simulation time 25451273 ps
CPU time 0.97 seconds
Started Jun 29 05:32:44 PM PDT 24
Finished Jun 29 05:32:48 PM PDT 24
Peak memory 216036 kb
Host smart-be01c4cc-713a-457d-b4dc-fbaf859b9c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983838534 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1983838534
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1477408976
Short name T751
Test name
Test status
Simulation time 14608837 ps
CPU time 0.94 seconds
Started Jun 29 05:32:46 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 215620 kb
Host smart-b2245a3b-5e5b-4ccb-9562-d6d9884f3528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477408976 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1477408976
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.952113233
Short name T776
Test name
Test status
Simulation time 106635911 ps
CPU time 1.17 seconds
Started Jun 29 05:32:51 PM PDT 24
Finished Jun 29 05:32:54 PM PDT 24
Peak memory 217628 kb
Host smart-e12e88b9-f36d-49cf-b3e5-de49abaa9879
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952113233 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.952113233
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2861232349
Short name T242
Test name
Test status
Simulation time 122406292689 ps
CPU time 823.9 seconds
Started Jun 29 05:32:39 PM PDT 24
Finished Jun 29 05:46:26 PM PDT 24
Peak memory 224004 kb
Host smart-c6cc2c87-7b0a-40cd-b515-66b224c520a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861232349 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2861232349
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1260030759
Short name T553
Test name
Test status
Simulation time 30405294 ps
CPU time 1.33 seconds
Started Jun 29 05:31:42 PM PDT 24
Finished Jun 29 05:31:44 PM PDT 24
Peak memory 221000 kb
Host smart-0aaf11df-e9f4-4dab-b8af-03d4dc31f9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260030759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1260030759
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1113932741
Short name T416
Test name
Test status
Simulation time 33507092 ps
CPU time 1.21 seconds
Started Jun 29 05:31:52 PM PDT 24
Finished Jun 29 05:31:54 PM PDT 24
Peak memory 215244 kb
Host smart-f479a8cf-bd6d-4c36-a1d0-c8a7c789016b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113932741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1113932741
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3037024926
Short name T199
Test name
Test status
Simulation time 31235812 ps
CPU time 0.82 seconds
Started Jun 29 05:31:45 PM PDT 24
Finished Jun 29 05:31:46 PM PDT 24
Peak memory 216520 kb
Host smart-8f4071b3-f0ab-4a8d-9f0f-ce5d622e1e4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037024926 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3037024926
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3048821173
Short name T197
Test name
Test status
Simulation time 96863036 ps
CPU time 1.06 seconds
Started Jun 29 05:31:46 PM PDT 24
Finished Jun 29 05:31:48 PM PDT 24
Peak memory 217140 kb
Host smart-7a8522ca-acff-4d3d-ac44-2b15e397721d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048821173 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3048821173
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_genbits.1736130843
Short name T69
Test name
Test status
Simulation time 92207810 ps
CPU time 1.3 seconds
Started Jun 29 05:31:46 PM PDT 24
Finished Jun 29 05:31:48 PM PDT 24
Peak memory 217608 kb
Host smart-e4fa0722-d587-4df7-b394-9d09f8fa93d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736130843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1736130843
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3463498025
Short name T870
Test name
Test status
Simulation time 22799245 ps
CPU time 1.12 seconds
Started Jun 29 05:31:49 PM PDT 24
Finished Jun 29 05:31:51 PM PDT 24
Peak memory 215796 kb
Host smart-9068630e-3bbc-46a0-a2ab-865cffa3843c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463498025 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3463498025
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1700752420
Short name T817
Test name
Test status
Simulation time 17692140 ps
CPU time 0.97 seconds
Started Jun 29 05:31:35 PM PDT 24
Finished Jun 29 05:31:37 PM PDT 24
Peak memory 207392 kb
Host smart-7d68b8c8-77e1-450b-95d1-33d4cab1cbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700752420 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1700752420
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.2911764861
Short name T688
Test name
Test status
Simulation time 56977624 ps
CPU time 0.94 seconds
Started Jun 29 05:31:38 PM PDT 24
Finished Jun 29 05:31:39 PM PDT 24
Peak memory 215548 kb
Host smart-b850034f-7982-47d4-a787-553827d3f10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911764861 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2911764861
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1492721047
Short name T55
Test name
Test status
Simulation time 709616735 ps
CPU time 4.51 seconds
Started Jun 29 05:31:43 PM PDT 24
Finished Jun 29 05:31:49 PM PDT 24
Peak memory 215608 kb
Host smart-84991fa4-2ce0-4395-8abe-6c8b7d7000c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492721047 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1492721047
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.4043360766
Short name T990
Test name
Test status
Simulation time 33859198609 ps
CPU time 402.28 seconds
Started Jun 29 05:31:43 PM PDT 24
Finished Jun 29 05:38:26 PM PDT 24
Peak memory 224004 kb
Host smart-63521dc2-4681-41ab-aed4-ea7d4db56896
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043360766 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.4043360766
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert_test.1455938229
Short name T401
Test name
Test status
Simulation time 14260425 ps
CPU time 0.95 seconds
Started Jun 29 05:32:49 PM PDT 24
Finished Jun 29 05:32:52 PM PDT 24
Peak memory 207008 kb
Host smart-e296f970-ef7f-4a9e-a3c3-8f6990ff244e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455938229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1455938229
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1216699426
Short name T168
Test name
Test status
Simulation time 20073524 ps
CPU time 0.88 seconds
Started Jun 29 05:32:36 PM PDT 24
Finished Jun 29 05:32:38 PM PDT 24
Peak memory 216504 kb
Host smart-da021e02-0206-43d8-8ded-8f76f5e5118a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216699426 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1216699426
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3458209384
Short name T125
Test name
Test status
Simulation time 47133416 ps
CPU time 0.98 seconds
Started Jun 29 05:32:50 PM PDT 24
Finished Jun 29 05:32:52 PM PDT 24
Peak memory 217148 kb
Host smart-1c68bf98-ab83-47bc-a17c-3dada463ffa6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458209384 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3458209384
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.707957271
Short name T750
Test name
Test status
Simulation time 23469811 ps
CPU time 0.92 seconds
Started Jun 29 05:32:42 PM PDT 24
Finished Jun 29 05:32:46 PM PDT 24
Peak memory 218724 kb
Host smart-5e716eb8-73d3-4c81-a9a9-e8bc3f26c619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707957271 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.707957271
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2068495254
Short name T806
Test name
Test status
Simulation time 28473731 ps
CPU time 1.21 seconds
Started Jun 29 05:32:39 PM PDT 24
Finished Jun 29 05:32:42 PM PDT 24
Peak memory 220280 kb
Host smart-f81fa4e0-3f31-47b3-ac81-f1d9bddf9433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068495254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2068495254
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2038399646
Short name T926
Test name
Test status
Simulation time 25105145 ps
CPU time 0.95 seconds
Started Jun 29 05:32:43 PM PDT 24
Finished Jun 29 05:32:46 PM PDT 24
Peak memory 215680 kb
Host smart-73dd4874-aa06-450a-b6c0-f0f12b7a9dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038399646 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2038399646
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.245493291
Short name T660
Test name
Test status
Simulation time 17561296 ps
CPU time 1.01 seconds
Started Jun 29 05:32:43 PM PDT 24
Finished Jun 29 05:32:46 PM PDT 24
Peak memory 215572 kb
Host smart-139298ad-531b-4648-9bc8-991cfab61a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245493291 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.245493291
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1430106065
Short name T248
Test name
Test status
Simulation time 659246679 ps
CPU time 3.89 seconds
Started Jun 29 05:32:41 PM PDT 24
Finished Jun 29 05:32:47 PM PDT 24
Peak memory 217504 kb
Host smart-bd0cfbcf-daed-4f9a-a7cb-1644397e08e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430106065 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1430106065
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.828334717
Short name T761
Test name
Test status
Simulation time 64410563184 ps
CPU time 762.27 seconds
Started Jun 29 05:32:39 PM PDT 24
Finished Jun 29 05:45:24 PM PDT 24
Peak memory 219360 kb
Host smart-fee7956b-a8b3-48f3-b767-bd2a544b562d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828334717 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.828334717
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2891898744
Short name T183
Test name
Test status
Simulation time 157756870 ps
CPU time 1.22 seconds
Started Jun 29 05:32:39 PM PDT 24
Finished Jun 29 05:32:42 PM PDT 24
Peak memory 221692 kb
Host smart-39909c79-00e9-4cdd-a9e1-8fa5dfb22457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891898744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2891898744
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.433585023
Short name T879
Test name
Test status
Simulation time 16950230 ps
CPU time 0.95 seconds
Started Jun 29 05:32:43 PM PDT 24
Finished Jun 29 05:32:46 PM PDT 24
Peak memory 207052 kb
Host smart-9b641c3f-e160-4289-917f-1797d71d2baa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433585023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.433585023
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1385434259
Short name T353
Test name
Test status
Simulation time 21592004 ps
CPU time 0.93 seconds
Started Jun 29 05:32:45 PM PDT 24
Finished Jun 29 05:32:49 PM PDT 24
Peak memory 216240 kb
Host smart-e28e4d56-f204-4e66-9218-7bfd00077dc7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385434259 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1385434259
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2567204919
Short name T442
Test name
Test status
Simulation time 111120078 ps
CPU time 1.1 seconds
Started Jun 29 05:32:42 PM PDT 24
Finished Jun 29 05:32:45 PM PDT 24
Peak memory 217172 kb
Host smart-b36a1ad0-1cb9-4183-9cdc-d0ae138c1511
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567204919 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2567204919
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3149397456
Short name T184
Test name
Test status
Simulation time 32528633 ps
CPU time 0.93 seconds
Started Jun 29 05:32:47 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 218640 kb
Host smart-ab5f353f-479a-42ee-8505-eaa33b450611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149397456 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3149397456
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3153317605
Short name T878
Test name
Test status
Simulation time 159875597 ps
CPU time 1.5 seconds
Started Jun 29 05:32:42 PM PDT 24
Finished Jun 29 05:32:46 PM PDT 24
Peak memory 220216 kb
Host smart-cf0a0671-7b2a-4d52-89fa-0dd2a897fa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153317605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3153317605
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.4065139054
Short name T15
Test name
Test status
Simulation time 32703100 ps
CPU time 0.97 seconds
Started Jun 29 05:32:48 PM PDT 24
Finished Jun 29 05:32:52 PM PDT 24
Peak memory 224232 kb
Host smart-51208517-9606-4eeb-95cd-386ac3fb9b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065139054 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.4065139054
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2002826124
Short name T455
Test name
Test status
Simulation time 54871431 ps
CPU time 0.97 seconds
Started Jun 29 05:32:47 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 215592 kb
Host smart-c8913cc4-6272-437d-9781-0b0aab16e69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002826124 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2002826124
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3759794103
Short name T954
Test name
Test status
Simulation time 46458440 ps
CPU time 1.55 seconds
Started Jun 29 05:32:42 PM PDT 24
Finished Jun 29 05:32:46 PM PDT 24
Peak memory 217312 kb
Host smart-c4e9a225-1132-47b0-8586-e8287bf95b46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759794103 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3759794103
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2737876553
Short name T822
Test name
Test status
Simulation time 240719392223 ps
CPU time 780.3 seconds
Started Jun 29 05:32:37 PM PDT 24
Finished Jun 29 05:45:39 PM PDT 24
Peak memory 220308 kb
Host smart-15d1d575-93fd-4c95-91cb-73cbc60f53a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737876553 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2737876553
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1195538690
Short name T979
Test name
Test status
Simulation time 24196136 ps
CPU time 1.17 seconds
Started Jun 29 05:32:46 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 221004 kb
Host smart-9ed95b6f-64f6-4b8b-90c1-966e2163f252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195538690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1195538690
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2082458844
Short name T482
Test name
Test status
Simulation time 131853986 ps
CPU time 0.89 seconds
Started Jun 29 05:32:42 PM PDT 24
Finished Jun 29 05:32:45 PM PDT 24
Peak memory 206716 kb
Host smart-34254ca2-b023-4594-9cef-6cbfd38d2872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082458844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2082458844
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1056307693
Short name T39
Test name
Test status
Simulation time 11872051 ps
CPU time 0.87 seconds
Started Jun 29 05:32:42 PM PDT 24
Finished Jun 29 05:32:45 PM PDT 24
Peak memory 215712 kb
Host smart-458fcf28-b76f-492a-8bf8-5dabf79553da
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056307693 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1056307693
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.830823280
Short name T463
Test name
Test status
Simulation time 33886641 ps
CPU time 1.12 seconds
Started Jun 29 05:32:49 PM PDT 24
Finished Jun 29 05:32:52 PM PDT 24
Peak memory 218548 kb
Host smart-588efdfc-741a-4ad8-b601-59c7ecdcb602
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830823280 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.830823280
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.570560753
Short name T682
Test name
Test status
Simulation time 36163969 ps
CPU time 1.17 seconds
Started Jun 29 05:32:44 PM PDT 24
Finished Jun 29 05:32:48 PM PDT 24
Peak memory 220868 kb
Host smart-6b7649f9-d756-418b-9cc0-fe48d4235373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570560753 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.570560753
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.762057472
Short name T499
Test name
Test status
Simulation time 53913693 ps
CPU time 1.51 seconds
Started Jun 29 05:32:43 PM PDT 24
Finished Jun 29 05:32:46 PM PDT 24
Peak memory 218848 kb
Host smart-baf545bd-a684-4136-b79e-0d4f8b69a10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762057472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.762057472
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3619228456
Short name T850
Test name
Test status
Simulation time 41267003 ps
CPU time 1.04 seconds
Started Jun 29 05:32:46 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 224288 kb
Host smart-c7d2e5ed-7880-472a-a838-30ee7ff8bab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619228456 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3619228456
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.4216023388
Short name T519
Test name
Test status
Simulation time 64479070 ps
CPU time 0.91 seconds
Started Jun 29 05:32:50 PM PDT 24
Finished Jun 29 05:32:53 PM PDT 24
Peak memory 215532 kb
Host smart-f1237518-2315-48d7-926c-446f4e4aebca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216023388 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.4216023388
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2327206327
Short name T896
Test name
Test status
Simulation time 191561902 ps
CPU time 2.1 seconds
Started Jun 29 05:32:42 PM PDT 24
Finished Jun 29 05:32:47 PM PDT 24
Peak memory 215612 kb
Host smart-4f5fa8da-0aea-44b1-9d24-5dde14dcd444
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327206327 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2327206327
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.195642728
Short name T925
Test name
Test status
Simulation time 106464889391 ps
CPU time 1352.1 seconds
Started Jun 29 05:32:43 PM PDT 24
Finished Jun 29 05:55:18 PM PDT 24
Peak memory 226180 kb
Host smart-057dbc98-4b0c-4ed7-a477-ad91626c783b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195642728 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.195642728
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.600970291
Short name T729
Test name
Test status
Simulation time 39018184 ps
CPU time 1.15 seconds
Started Jun 29 05:32:47 PM PDT 24
Finished Jun 29 05:32:51 PM PDT 24
Peak memory 220472 kb
Host smart-378670cb-29ad-48c1-83f4-64e240ff246f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600970291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.600970291
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.4071602401
Short name T901
Test name
Test status
Simulation time 21355478 ps
CPU time 1.01 seconds
Started Jun 29 05:32:50 PM PDT 24
Finished Jun 29 05:32:52 PM PDT 24
Peak memory 215192 kb
Host smart-d6cf170f-1f01-4a9c-95c5-8a46385b627f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071602401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.4071602401
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3522404337
Short name T200
Test name
Test status
Simulation time 18784887 ps
CPU time 0.88 seconds
Started Jun 29 05:32:44 PM PDT 24
Finished Jun 29 05:32:48 PM PDT 24
Peak memory 216540 kb
Host smart-650391ed-0d92-416a-9bce-d26556664972
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522404337 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3522404337
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2007338137
Short name T526
Test name
Test status
Simulation time 41678404 ps
CPU time 1.11 seconds
Started Jun 29 05:32:41 PM PDT 24
Finished Jun 29 05:32:44 PM PDT 24
Peak memory 218804 kb
Host smart-cef62dab-65a4-4c4e-bd65-ad8248a9a82b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007338137 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2007338137
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3610298369
Short name T564
Test name
Test status
Simulation time 19324240 ps
CPU time 1.1 seconds
Started Jun 29 05:32:51 PM PDT 24
Finished Jun 29 05:32:53 PM PDT 24
Peak memory 219048 kb
Host smart-101db413-9dd3-4255-bd4d-a0aea0468a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610298369 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3610298369
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2221378053
Short name T345
Test name
Test status
Simulation time 213270204 ps
CPU time 2.85 seconds
Started Jun 29 05:32:49 PM PDT 24
Finished Jun 29 05:32:54 PM PDT 24
Peak memory 220404 kb
Host smart-50837727-76ca-40cc-84f0-9d569966a910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221378053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2221378053
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.239256123
Short name T787
Test name
Test status
Simulation time 87367363 ps
CPU time 0.99 seconds
Started Jun 29 05:32:52 PM PDT 24
Finished Jun 29 05:32:54 PM PDT 24
Peak memory 224144 kb
Host smart-e46d81b8-e996-4bbd-a8fd-352d5ad72580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239256123 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.239256123
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2613780386
Short name T478
Test name
Test status
Simulation time 18444074 ps
CPU time 1.1 seconds
Started Jun 29 05:32:45 PM PDT 24
Finished Jun 29 05:32:49 PM PDT 24
Peak memory 215632 kb
Host smart-97ddc67f-d73a-4430-a90d-e2bd74d11ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613780386 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2613780386
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1852658610
Short name T826
Test name
Test status
Simulation time 317998305 ps
CPU time 6.34 seconds
Started Jun 29 05:32:50 PM PDT 24
Finished Jun 29 05:32:58 PM PDT 24
Peak memory 215668 kb
Host smart-3e04c912-cb2a-4f72-a167-645164f57f4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852658610 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1852658610
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3443752535
Short name T892
Test name
Test status
Simulation time 40467848569 ps
CPU time 486.58 seconds
Started Jun 29 05:32:43 PM PDT 24
Finished Jun 29 05:40:53 PM PDT 24
Peak memory 224004 kb
Host smart-8250cd34-d0f6-4a4e-9463-4d161cc1812c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443752535 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3443752535
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.4263117498
Short name T261
Test name
Test status
Simulation time 29406170 ps
CPU time 1.34 seconds
Started Jun 29 05:32:48 PM PDT 24
Finished Jun 29 05:32:52 PM PDT 24
Peak memory 219072 kb
Host smart-be000f7e-5ee0-4f79-add7-9d13fce91dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263117498 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.4263117498
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3356440305
Short name T80
Test name
Test status
Simulation time 17717720 ps
CPU time 1 seconds
Started Jun 29 05:32:48 PM PDT 24
Finished Jun 29 05:32:52 PM PDT 24
Peak memory 215196 kb
Host smart-487f17ce-4a44-4bb8-8f01-33a481204599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356440305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3356440305
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.464459862
Short name T176
Test name
Test status
Simulation time 29645694 ps
CPU time 0.86 seconds
Started Jun 29 05:32:42 PM PDT 24
Finished Jun 29 05:32:44 PM PDT 24
Peak memory 216540 kb
Host smart-9ef176e4-fdd5-4992-af82-c5e8d98e0b5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464459862 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.464459862
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2862540575
Short name T214
Test name
Test status
Simulation time 23748923 ps
CPU time 1.1 seconds
Started Jun 29 05:32:55 PM PDT 24
Finished Jun 29 05:32:56 PM PDT 24
Peak memory 217164 kb
Host smart-14d29817-7e30-42ca-abcc-4c1908302997
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862540575 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2862540575
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.239414591
Short name T835
Test name
Test status
Simulation time 18582536 ps
CPU time 1.02 seconds
Started Jun 29 05:32:51 PM PDT 24
Finished Jun 29 05:32:53 PM PDT 24
Peak memory 218340 kb
Host smart-b7cf5ac2-c0f3-4ed8-b1d2-bdf960aa1174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239414591 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.239414591
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3055693232
Short name T959
Test name
Test status
Simulation time 53662807 ps
CPU time 1.45 seconds
Started Jun 29 05:32:56 PM PDT 24
Finished Jun 29 05:32:57 PM PDT 24
Peak memory 219088 kb
Host smart-894d8c09-8e25-4601-b6f3-250f600c2bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055693232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3055693232
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3879429985
Short name T439
Test name
Test status
Simulation time 36317927 ps
CPU time 0.89 seconds
Started Jun 29 05:32:43 PM PDT 24
Finished Jun 29 05:32:46 PM PDT 24
Peak memory 215888 kb
Host smart-a65d7906-55b5-476c-b663-b367bddaa3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879429985 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3879429985
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2969346892
Short name T984
Test name
Test status
Simulation time 23308307 ps
CPU time 0.95 seconds
Started Jun 29 05:32:48 PM PDT 24
Finished Jun 29 05:32:52 PM PDT 24
Peak memory 215520 kb
Host smart-5fb23fb3-4ce5-45b2-a3fe-05f893a01f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969346892 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2969346892
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3824420233
Short name T520
Test name
Test status
Simulation time 222020920 ps
CPU time 2.82 seconds
Started Jun 29 05:32:53 PM PDT 24
Finished Jun 29 05:32:56 PM PDT 24
Peak memory 219880 kb
Host smart-5f9fa498-f2b2-4c40-b08b-b51c4d49316e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824420233 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3824420233
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2698826303
Short name T628
Test name
Test status
Simulation time 25798494813 ps
CPU time 470.57 seconds
Started Jun 29 05:32:48 PM PDT 24
Finished Jun 29 05:40:41 PM PDT 24
Peak memory 218540 kb
Host smart-deb32de6-ac74-4ec8-b272-8626188a1f1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698826303 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2698826303
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1004469217
Short name T188
Test name
Test status
Simulation time 83411093 ps
CPU time 1.19 seconds
Started Jun 29 05:32:50 PM PDT 24
Finished Jun 29 05:32:52 PM PDT 24
Peak memory 220128 kb
Host smart-81a33093-c75e-4f97-86a2-5a5bd5c043aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004469217 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1004469217
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1691782174
Short name T370
Test name
Test status
Simulation time 15313709 ps
CPU time 0.89 seconds
Started Jun 29 05:32:46 PM PDT 24
Finished Jun 29 05:32:49 PM PDT 24
Peak memory 207024 kb
Host smart-7e1c79d7-1375-49e4-bdf4-fa46f4a2658c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691782174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1691782174
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3691224007
Short name T92
Test name
Test status
Simulation time 19089168 ps
CPU time 0.86 seconds
Started Jun 29 05:32:54 PM PDT 24
Finished Jun 29 05:32:55 PM PDT 24
Peak memory 216252 kb
Host smart-81d8aff4-64e2-4a15-b7b5-e849ebf8389f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691224007 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3691224007
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1662548755
Short name T549
Test name
Test status
Simulation time 67622847 ps
CPU time 1.32 seconds
Started Jun 29 05:32:46 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 217088 kb
Host smart-08441b97-4eed-4154-b6ab-b84dbd188777
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662548755 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1662548755
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2840840350
Short name T528
Test name
Test status
Simulation time 18961488 ps
CPU time 1.07 seconds
Started Jun 29 05:32:44 PM PDT 24
Finished Jun 29 05:32:48 PM PDT 24
Peak memory 218748 kb
Host smart-de420c1b-1b40-4b4a-8c1a-e5e293d5f11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840840350 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2840840350
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2536111979
Short name T20
Test name
Test status
Simulation time 136368738 ps
CPU time 2.85 seconds
Started Jun 29 05:32:59 PM PDT 24
Finished Jun 29 05:33:03 PM PDT 24
Peak memory 220376 kb
Host smart-49f7d88e-510b-4f70-9fd0-923084723550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536111979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2536111979
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.988436948
Short name T950
Test name
Test status
Simulation time 49536110 ps
CPU time 0.89 seconds
Started Jun 29 05:32:44 PM PDT 24
Finished Jun 29 05:32:48 PM PDT 24
Peak memory 215648 kb
Host smart-ff996eb0-9340-46f8-86c9-6344b9187dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988436948 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.988436948
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3927075614
Short name T365
Test name
Test status
Simulation time 43136039 ps
CPU time 0.93 seconds
Started Jun 29 05:32:46 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 215508 kb
Host smart-06e491ed-82a5-45ac-bd7c-a0189ba07e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927075614 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3927075614
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1299970043
Short name T452
Test name
Test status
Simulation time 116682568 ps
CPU time 1.75 seconds
Started Jun 29 05:32:45 PM PDT 24
Finished Jun 29 05:32:49 PM PDT 24
Peak memory 215588 kb
Host smart-84d0f304-3a9d-4246-a622-651fd2270cc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299970043 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1299970043
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.805648472
Short name T648
Test name
Test status
Simulation time 51327925387 ps
CPU time 1328.78 seconds
Started Jun 29 05:32:49 PM PDT 24
Finished Jun 29 05:55:00 PM PDT 24
Peak memory 223668 kb
Host smart-cbc1f2f2-8ebe-44ea-8c58-27972cfead2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805648472 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.805648472
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.938344964
Short name T800
Test name
Test status
Simulation time 25166839 ps
CPU time 1.18 seconds
Started Jun 29 05:32:51 PM PDT 24
Finished Jun 29 05:32:53 PM PDT 24
Peak memory 218864 kb
Host smart-49fe7e5f-86dd-4aaf-a11f-f95f9dd5cb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938344964 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.938344964
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1222299943
Short name T409
Test name
Test status
Simulation time 18963260 ps
CPU time 1 seconds
Started Jun 29 05:32:48 PM PDT 24
Finished Jun 29 05:32:52 PM PDT 24
Peak memory 206928 kb
Host smart-5fe41628-ece0-4bff-8686-590bd36ce74e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222299943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1222299943
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2677196927
Short name T645
Test name
Test status
Simulation time 19663644 ps
CPU time 0.91 seconds
Started Jun 29 05:32:57 PM PDT 24
Finished Jun 29 05:32:58 PM PDT 24
Peak memory 216248 kb
Host smart-53ef5e90-9299-46a2-8a88-6b8a092d5d5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677196927 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2677196927
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2476846025
Short name T719
Test name
Test status
Simulation time 35537644 ps
CPU time 1.27 seconds
Started Jun 29 05:32:42 PM PDT 24
Finished Jun 29 05:32:46 PM PDT 24
Peak memory 217240 kb
Host smart-d77b1c84-4677-48ce-bdd1-eebd96ff356a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476846025 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2476846025
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.4195485847
Short name T173
Test name
Test status
Simulation time 30075904 ps
CPU time 0.91 seconds
Started Jun 29 05:32:43 PM PDT 24
Finished Jun 29 05:32:46 PM PDT 24
Peak memory 218368 kb
Host smart-a2d680a7-0d3d-46fd-b4a6-46c2188ec952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195485847 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.4195485847
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1343170559
Short name T256
Test name
Test status
Simulation time 58961163 ps
CPU time 1.99 seconds
Started Jun 29 05:32:51 PM PDT 24
Finished Jun 29 05:32:54 PM PDT 24
Peak memory 220496 kb
Host smart-a3b62919-b393-41b6-b05e-dad02a99a017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343170559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1343170559
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.212865665
Short name T32
Test name
Test status
Simulation time 33232871 ps
CPU time 0.93 seconds
Started Jun 29 05:32:45 PM PDT 24
Finished Jun 29 05:32:49 PM PDT 24
Peak memory 215972 kb
Host smart-0338ca1d-663c-497b-8696-b9fc4bbcb6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212865665 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.212865665
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1664699751
Short name T598
Test name
Test status
Simulation time 51952792 ps
CPU time 0.9 seconds
Started Jun 29 05:32:51 PM PDT 24
Finished Jun 29 05:32:53 PM PDT 24
Peak memory 215600 kb
Host smart-82d400d0-c10d-4039-8776-0b27df1857a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664699751 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1664699751
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3884653700
Short name T573
Test name
Test status
Simulation time 467026260 ps
CPU time 2.79 seconds
Started Jun 29 05:32:46 PM PDT 24
Finished Jun 29 05:32:52 PM PDT 24
Peak memory 219928 kb
Host smart-26a3cdb4-1aed-4f40-8e87-e212910ca9e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884653700 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3884653700
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2157193457
Short name T906
Test name
Test status
Simulation time 197268754028 ps
CPU time 1203.93 seconds
Started Jun 29 05:32:48 PM PDT 24
Finished Jun 29 05:52:55 PM PDT 24
Peak memory 224032 kb
Host smart-df66f7cf-d299-4da1-b55f-281ef120dfa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157193457 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2157193457
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1242349507
Short name T290
Test name
Test status
Simulation time 33630583 ps
CPU time 1.3 seconds
Started Jun 29 05:33:01 PM PDT 24
Finished Jun 29 05:33:03 PM PDT 24
Peak memory 219784 kb
Host smart-7e4a671d-bed1-40c0-a158-e04ea9829ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242349507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1242349507
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1374395046
Short name T853
Test name
Test status
Simulation time 17569502 ps
CPU time 1.03 seconds
Started Jun 29 05:32:53 PM PDT 24
Finished Jun 29 05:32:55 PM PDT 24
Peak memory 215428 kb
Host smart-225e2c93-86ee-4b77-92a1-841c11eab1bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374395046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1374395046
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1141577446
Short name T160
Test name
Test status
Simulation time 21767061 ps
CPU time 0.87 seconds
Started Jun 29 05:32:55 PM PDT 24
Finished Jun 29 05:32:57 PM PDT 24
Peak memory 215724 kb
Host smart-03dafc8f-7de5-4068-b99e-a43075dd1d4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141577446 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1141577446
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2742705688
Short name T816
Test name
Test status
Simulation time 103328707 ps
CPU time 1.14 seconds
Started Jun 29 05:32:59 PM PDT 24
Finished Jun 29 05:33:01 PM PDT 24
Peak memory 220184 kb
Host smart-d97c6297-bfe3-4a18-95ff-3610b50cb0f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742705688 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2742705688
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1323620096
Short name T493
Test name
Test status
Simulation time 19121634 ps
CPU time 1.08 seconds
Started Jun 29 05:33:12 PM PDT 24
Finished Jun 29 05:33:14 PM PDT 24
Peak memory 224204 kb
Host smart-84f3ca69-b6e6-4de4-8aea-9bfe52ae4822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323620096 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1323620096
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2949484392
Short name T347
Test name
Test status
Simulation time 77863069 ps
CPU time 1.02 seconds
Started Jun 29 05:32:54 PM PDT 24
Finished Jun 29 05:32:56 PM PDT 24
Peak memory 217616 kb
Host smart-a603e6c1-74f8-408d-a49b-eca413932858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949484392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2949484392
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2047346642
Short name T985
Test name
Test status
Simulation time 27222849 ps
CPU time 1.13 seconds
Started Jun 29 05:32:53 PM PDT 24
Finished Jun 29 05:32:55 PM PDT 24
Peak memory 224256 kb
Host smart-4209fdc1-de4e-4c19-af79-2f64518851b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047346642 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2047346642
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1829177680
Short name T418
Test name
Test status
Simulation time 28627029 ps
CPU time 0.95 seconds
Started Jun 29 05:32:44 PM PDT 24
Finished Jun 29 05:32:48 PM PDT 24
Peak memory 215540 kb
Host smart-8c28aaeb-cb18-4f75-8dd2-67f3c99f79c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829177680 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1829177680
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2553390238
Short name T393
Test name
Test status
Simulation time 178235885 ps
CPU time 2.48 seconds
Started Jun 29 05:32:56 PM PDT 24
Finished Jun 29 05:32:59 PM PDT 24
Peak memory 215684 kb
Host smart-5ba06636-950e-4a7c-a376-a531c27f4cea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553390238 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2553390238
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1752428581
Short name T575
Test name
Test status
Simulation time 122805026572 ps
CPU time 1538.87 seconds
Started Jun 29 05:32:52 PM PDT 24
Finished Jun 29 05:58:32 PM PDT 24
Peak memory 224844 kb
Host smart-abb83844-187d-4653-93a3-131cecea514c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752428581 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1752428581
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1161183183
Short name T978
Test name
Test status
Simulation time 54454414 ps
CPU time 1.21 seconds
Started Jun 29 05:32:57 PM PDT 24
Finished Jun 29 05:32:59 PM PDT 24
Peak memory 218904 kb
Host smart-e10d3352-9963-486d-8278-bb32c9f71281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161183183 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1161183183
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1945914926
Short name T592
Test name
Test status
Simulation time 78464653 ps
CPU time 1.07 seconds
Started Jun 29 05:32:53 PM PDT 24
Finished Jun 29 05:32:55 PM PDT 24
Peak memory 215448 kb
Host smart-9c6cfd06-186f-485a-a170-0de2b1120795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945914926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1945914926
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3856498224
Short name T195
Test name
Test status
Simulation time 49700648 ps
CPU time 0.85 seconds
Started Jun 29 05:33:01 PM PDT 24
Finished Jun 29 05:33:03 PM PDT 24
Peak memory 216540 kb
Host smart-b973c1a7-28b9-4d74-a4d3-fc70a47823be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856498224 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3856498224
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_err.894915204
Short name T485
Test name
Test status
Simulation time 45469943 ps
CPU time 1.01 seconds
Started Jun 29 05:33:07 PM PDT 24
Finished Jun 29 05:33:08 PM PDT 24
Peak memory 218924 kb
Host smart-7efe8304-53c8-4e0f-9649-3981a7d5ca1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894915204 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.894915204
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.876896836
Short name T962
Test name
Test status
Simulation time 53744589 ps
CPU time 1.28 seconds
Started Jun 29 05:32:54 PM PDT 24
Finished Jun 29 05:32:56 PM PDT 24
Peak memory 217436 kb
Host smart-6488bc14-017c-413e-a0e2-2a52e40278a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876896836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.876896836
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3543245210
Short name T798
Test name
Test status
Simulation time 22348677 ps
CPU time 1.19 seconds
Started Jun 29 05:32:53 PM PDT 24
Finished Jun 29 05:32:56 PM PDT 24
Peak memory 215876 kb
Host smart-dbd2c12d-07e7-4a9a-bb70-9df2120466ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543245210 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3543245210
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3479324251
Short name T627
Test name
Test status
Simulation time 16465446 ps
CPU time 1.01 seconds
Started Jun 29 05:32:54 PM PDT 24
Finished Jun 29 05:32:55 PM PDT 24
Peak memory 215836 kb
Host smart-3a55bb6d-93b0-4b61-a40e-30ea3ac378f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479324251 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3479324251
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1059607552
Short name T363
Test name
Test status
Simulation time 249932027 ps
CPU time 4.81 seconds
Started Jun 29 05:32:52 PM PDT 24
Finished Jun 29 05:32:58 PM PDT 24
Peak memory 218712 kb
Host smart-4d56995c-01eb-4cf5-83bc-6da790b3a54e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059607552 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1059607552
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.429981270
Short name T643
Test name
Test status
Simulation time 176872113578 ps
CPU time 1675.54 seconds
Started Jun 29 05:32:57 PM PDT 24
Finished Jun 29 06:00:53 PM PDT 24
Peak memory 227668 kb
Host smart-910b6dbc-8a6d-42cb-9b23-ab36be72a267
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429981270 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.429981270
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2165612579
Short name T318
Test name
Test status
Simulation time 22999411 ps
CPU time 1.21 seconds
Started Jun 29 05:32:51 PM PDT 24
Finished Jun 29 05:32:53 PM PDT 24
Peak memory 218936 kb
Host smart-9ba7c82a-ab85-43f8-9312-4de0d2696efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165612579 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2165612579
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2582351669
Short name T479
Test name
Test status
Simulation time 15355922 ps
CPU time 0.93 seconds
Started Jun 29 05:33:12 PM PDT 24
Finished Jun 29 05:33:14 PM PDT 24
Peak memory 206976 kb
Host smart-ba84948b-c159-4b12-ae54-1ba619103887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582351669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2582351669
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1493176788
Short name T205
Test name
Test status
Simulation time 10646326 ps
CPU time 0.89 seconds
Started Jun 29 05:32:56 PM PDT 24
Finished Jun 29 05:32:58 PM PDT 24
Peak memory 216564 kb
Host smart-062804a2-66c2-4abe-bf28-0c6f22fcde2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493176788 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1493176788
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.650024332
Short name T196
Test name
Test status
Simulation time 202437728 ps
CPU time 1.16 seconds
Started Jun 29 05:32:52 PM PDT 24
Finished Jun 29 05:32:54 PM PDT 24
Peak memory 217236 kb
Host smart-df03bf32-43aa-42a2-8d46-c7fb8f2105a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650024332 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.650024332
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.76651964
Short name T164
Test name
Test status
Simulation time 55410792 ps
CPU time 0.91 seconds
Started Jun 29 05:32:54 PM PDT 24
Finished Jun 29 05:32:55 PM PDT 24
Peak memory 218652 kb
Host smart-7cea46a4-8500-4ee4-9244-f35739458ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76651964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.76651964
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.762234115
Short name T611
Test name
Test status
Simulation time 53325670 ps
CPU time 1.44 seconds
Started Jun 29 05:32:57 PM PDT 24
Finished Jun 29 05:32:59 PM PDT 24
Peak memory 217900 kb
Host smart-212d0d1a-b027-4f8d-8c3a-eecd226f8633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762234115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.762234115
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1092216639
Short name T940
Test name
Test status
Simulation time 23384137 ps
CPU time 1.2 seconds
Started Jun 29 05:33:13 PM PDT 24
Finished Jun 29 05:33:15 PM PDT 24
Peak memory 224284 kb
Host smart-a80e07b0-160c-4ec5-ad2a-c159564954d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092216639 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1092216639
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.623234277
Short name T735
Test name
Test status
Simulation time 24398841 ps
CPU time 0.96 seconds
Started Jun 29 05:32:57 PM PDT 24
Finished Jun 29 05:32:59 PM PDT 24
Peak memory 215636 kb
Host smart-d2f31886-a163-4a08-885d-477a20e2f0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623234277 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.623234277
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2721136931
Short name T593
Test name
Test status
Simulation time 369960765 ps
CPU time 2.62 seconds
Started Jun 29 05:32:57 PM PDT 24
Finished Jun 29 05:33:01 PM PDT 24
Peak memory 215604 kb
Host smart-1a08fdbb-0e8d-4689-a855-d356f01f6174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721136931 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2721136931
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2098580926
Short name T606
Test name
Test status
Simulation time 25177476727 ps
CPU time 512.43 seconds
Started Jun 29 05:32:55 PM PDT 24
Finished Jun 29 05:41:28 PM PDT 24
Peak memory 218592 kb
Host smart-bb275719-d332-417b-885d-a540b4fbc0ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098580926 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2098580926
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3101064744
Short name T518
Test name
Test status
Simulation time 30948319 ps
CPU time 1.26 seconds
Started Jun 29 05:31:50 PM PDT 24
Finished Jun 29 05:31:52 PM PDT 24
Peak memory 218844 kb
Host smart-44dfa9ea-4b9f-41d7-9103-77d405bbdc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101064744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3101064744
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2486354523
Short name T507
Test name
Test status
Simulation time 16967183 ps
CPU time 0.95 seconds
Started Jun 29 05:31:55 PM PDT 24
Finished Jun 29 05:31:56 PM PDT 24
Peak memory 206916 kb
Host smart-76fe6373-af1b-467a-a7b1-05fd19c2aae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486354523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2486354523
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.81288537
Short name T994
Test name
Test status
Simulation time 12282554 ps
CPU time 0.92 seconds
Started Jun 29 05:31:48 PM PDT 24
Finished Jun 29 05:31:49 PM PDT 24
Peak memory 216560 kb
Host smart-0148f1a6-f3af-4f27-b4a2-4767bf033a3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81288537 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.81288537
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2056589558
Short name T148
Test name
Test status
Simulation time 443047113 ps
CPU time 1.2 seconds
Started Jun 29 05:31:50 PM PDT 24
Finished Jun 29 05:31:52 PM PDT 24
Peak memory 217244 kb
Host smart-860dccc4-c502-472b-9e79-fcff29cf4a59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056589558 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2056589558
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1690858748
Short name T872
Test name
Test status
Simulation time 54056682 ps
CPU time 1.05 seconds
Started Jun 29 05:31:45 PM PDT 24
Finished Jun 29 05:31:46 PM PDT 24
Peak memory 219912 kb
Host smart-2fcb1506-e555-4703-b2da-66dd4d7425f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690858748 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1690858748
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1790602859
Short name T529
Test name
Test status
Simulation time 93684081 ps
CPU time 1.15 seconds
Started Jun 29 05:31:45 PM PDT 24
Finished Jun 29 05:31:47 PM PDT 24
Peak memory 217520 kb
Host smart-ab57b40e-0008-4210-b934-25d81ad84eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790602859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1790602859
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1909649807
Short name T29
Test name
Test status
Simulation time 31120243 ps
CPU time 0.87 seconds
Started Jun 29 05:31:59 PM PDT 24
Finished Jun 29 05:32:00 PM PDT 24
Peak memory 215892 kb
Host smart-8cbae9ff-9699-4903-a108-71105e4611cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909649807 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1909649807
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.539179289
Short name T921
Test name
Test status
Simulation time 45482933 ps
CPU time 0.95 seconds
Started Jun 29 05:31:48 PM PDT 24
Finished Jun 29 05:31:50 PM PDT 24
Peak memory 207400 kb
Host smart-c4223ff9-2ff2-4856-b2e8-8e967695e5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539179289 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.539179289
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3797739493
Short name T669
Test name
Test status
Simulation time 26295610 ps
CPU time 0.99 seconds
Started Jun 29 05:31:51 PM PDT 24
Finished Jun 29 05:31:53 PM PDT 24
Peak memory 215464 kb
Host smart-0d327f70-d9b2-48d5-a184-d3a0db7457af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797739493 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3797739493
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2606970216
Short name T249
Test name
Test status
Simulation time 131530685 ps
CPU time 3.11 seconds
Started Jun 29 05:31:53 PM PDT 24
Finished Jun 29 05:31:57 PM PDT 24
Peak memory 217500 kb
Host smart-3785a690-7119-4d7c-b834-b1faace77c3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606970216 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2606970216
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3217015179
Short name T237
Test name
Test status
Simulation time 36364054331 ps
CPU time 763.96 seconds
Started Jun 29 05:32:01 PM PDT 24
Finished Jun 29 05:44:46 PM PDT 24
Peak memory 216980 kb
Host smart-25cdf843-70a7-4905-8791-ff3a28d2077c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217015179 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3217015179
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.97814601
Short name T182
Test name
Test status
Simulation time 32846705 ps
CPU time 1.13 seconds
Started Jun 29 05:33:12 PM PDT 24
Finished Jun 29 05:33:14 PM PDT 24
Peak memory 219124 kb
Host smart-5c1fdc40-88c1-409a-a7e9-3d8749329739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97814601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.97814601
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.2789881393
Short name T202
Test name
Test status
Simulation time 23826602 ps
CPU time 1.04 seconds
Started Jun 29 05:32:59 PM PDT 24
Finished Jun 29 05:33:00 PM PDT 24
Peak memory 218884 kb
Host smart-34c8a1cd-9cbd-4319-9a3d-e5ea56c9722e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789881393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2789881393
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3399241547
Short name T68
Test name
Test status
Simulation time 29874966 ps
CPU time 1.35 seconds
Started Jun 29 05:32:58 PM PDT 24
Finished Jun 29 05:33:00 PM PDT 24
Peak memory 218644 kb
Host smart-6e614c94-c533-4ade-bf35-9c24182ed9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399241547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3399241547
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.1888432265
Short name T890
Test name
Test status
Simulation time 92885818 ps
CPU time 1.19 seconds
Started Jun 29 05:32:54 PM PDT 24
Finished Jun 29 05:32:56 PM PDT 24
Peak memory 219256 kb
Host smart-384d5df8-1190-4788-b8cf-06265bf9137e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888432265 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.1888432265
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.266156286
Short name T608
Test name
Test status
Simulation time 50691942 ps
CPU time 1.04 seconds
Started Jun 29 05:32:55 PM PDT 24
Finished Jun 29 05:32:57 PM PDT 24
Peak memory 220120 kb
Host smart-899bb022-cdef-465c-9d05-0ddfdcc7b19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266156286 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.266156286
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.156535438
Short name T982
Test name
Test status
Simulation time 38486772 ps
CPU time 1.12 seconds
Started Jun 29 05:33:02 PM PDT 24
Finished Jun 29 05:33:04 PM PDT 24
Peak memory 218984 kb
Host smart-d81635bf-dbb7-4bc8-ae58-150d383237ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156535438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.156535438
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.2104031044
Short name T187
Test name
Test status
Simulation time 23137784 ps
CPU time 1.18 seconds
Started Jun 29 05:32:59 PM PDT 24
Finished Jun 29 05:33:01 PM PDT 24
Peak memory 219044 kb
Host smart-b4c6791f-961f-43f0-9785-01e3d1e47d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104031044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.2104031044
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.2885153424
Short name T488
Test name
Test status
Simulation time 19264205 ps
CPU time 1.18 seconds
Started Jun 29 05:33:01 PM PDT 24
Finished Jun 29 05:33:03 PM PDT 24
Peak memory 224272 kb
Host smart-65db6a8e-6dd3-4b34-84a6-5c17f625c8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885153424 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2885153424
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3973378242
Short name T548
Test name
Test status
Simulation time 59401641 ps
CPU time 1.38 seconds
Started Jun 29 05:32:56 PM PDT 24
Finished Jun 29 05:32:58 PM PDT 24
Peak memory 218760 kb
Host smart-95999511-aeff-4545-a62c-ad227794f778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973378242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3973378242
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.1789621911
Short name T178
Test name
Test status
Simulation time 70260171 ps
CPU time 1.2 seconds
Started Jun 29 05:32:51 PM PDT 24
Finished Jun 29 05:32:54 PM PDT 24
Peak memory 219880 kb
Host smart-b2f4859c-0774-4423-877c-aa0309001d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789621911 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.1789621911
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.10992993
Short name T58
Test name
Test status
Simulation time 25290418 ps
CPU time 1.35 seconds
Started Jun 29 05:32:55 PM PDT 24
Finished Jun 29 05:32:57 PM PDT 24
Peak memory 224280 kb
Host smart-06f4bdf8-676b-426f-8a3e-72a16b52e406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10992993 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.10992993
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2752128601
Short name T500
Test name
Test status
Simulation time 41206750 ps
CPU time 1.58 seconds
Started Jun 29 05:33:00 PM PDT 24
Finished Jun 29 05:33:02 PM PDT 24
Peak memory 220064 kb
Host smart-200ce80b-d1b4-4ba3-88b5-9d47682bd471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752128601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2752128601
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.2694627559
Short name T574
Test name
Test status
Simulation time 243861504 ps
CPU time 1.27 seconds
Started Jun 29 05:33:12 PM PDT 24
Finished Jun 29 05:33:15 PM PDT 24
Peak memory 215972 kb
Host smart-bb932e86-d38b-4d5b-b951-b15cd8d3965c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694627559 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.2694627559
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.3998347328
Short name T848
Test name
Test status
Simulation time 26853472 ps
CPU time 1.09 seconds
Started Jun 29 05:33:14 PM PDT 24
Finished Jun 29 05:33:16 PM PDT 24
Peak memory 224204 kb
Host smart-5890d588-6665-4409-9b88-e77943a61cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998347328 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3998347328
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3635690656
Short name T323
Test name
Test status
Simulation time 46546000 ps
CPU time 1.78 seconds
Started Jun 29 05:33:10 PM PDT 24
Finished Jun 29 05:33:12 PM PDT 24
Peak memory 217536 kb
Host smart-78e45d97-fa96-42fc-a372-49d98ae1e4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635690656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3635690656
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.1688853004
Short name T655
Test name
Test status
Simulation time 99493986 ps
CPU time 1.31 seconds
Started Jun 29 05:32:52 PM PDT 24
Finished Jun 29 05:32:54 PM PDT 24
Peak memory 219720 kb
Host smart-e0775210-4632-4226-bc42-36cc699fd57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688853004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.1688853004
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2779545558
Short name T175
Test name
Test status
Simulation time 18237590 ps
CPU time 1.07 seconds
Started Jun 29 05:33:04 PM PDT 24
Finished Jun 29 05:33:06 PM PDT 24
Peak memory 218668 kb
Host smart-9bc426d2-239d-4e68-98e5-ca14459e959d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779545558 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2779545558
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.4248402735
Short name T976
Test name
Test status
Simulation time 67769162 ps
CPU time 0.92 seconds
Started Jun 29 05:32:53 PM PDT 24
Finished Jun 29 05:32:55 PM PDT 24
Peak memory 217596 kb
Host smart-055875dc-1968-46b9-b579-73c38a6f8ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248402735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.4248402735
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.1088865519
Short name T317
Test name
Test status
Simulation time 91131163 ps
CPU time 1.14 seconds
Started Jun 29 05:32:53 PM PDT 24
Finished Jun 29 05:32:55 PM PDT 24
Peak memory 221960 kb
Host smart-da8ff95f-f179-451f-9095-794e0602a970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088865519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.1088865519
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.1956017889
Short name T118
Test name
Test status
Simulation time 31587206 ps
CPU time 1.07 seconds
Started Jun 29 05:32:58 PM PDT 24
Finished Jun 29 05:33:00 PM PDT 24
Peak memory 219764 kb
Host smart-b680ee6c-bc02-450c-8fce-a2ba60b9c5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956017889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1956017889
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1129175177
Short name T917
Test name
Test status
Simulation time 58480681 ps
CPU time 1.45 seconds
Started Jun 29 05:32:52 PM PDT 24
Finished Jun 29 05:32:54 PM PDT 24
Peak memory 218828 kb
Host smart-cf27d1a4-1438-402b-96cd-6bc7492169f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129175177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1129175177
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2191374960
Short name T373
Test name
Test status
Simulation time 20640896 ps
CPU time 1.06 seconds
Started Jun 29 05:32:59 PM PDT 24
Finished Jun 29 05:33:01 PM PDT 24
Peak memory 218940 kb
Host smart-49f47f20-eaf9-448f-af2c-8fbf37092e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191374960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2191374960
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.239812236
Short name T693
Test name
Test status
Simulation time 134214519 ps
CPU time 1.64 seconds
Started Jun 29 05:32:53 PM PDT 24
Finished Jun 29 05:32:55 PM PDT 24
Peak memory 219176 kb
Host smart-98d0f0de-22eb-482a-9084-38f4ef52f0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239812236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.239812236
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.2380450228
Short name T889
Test name
Test status
Simulation time 38462804 ps
CPU time 1.08 seconds
Started Jun 29 05:33:01 PM PDT 24
Finished Jun 29 05:33:02 PM PDT 24
Peak memory 219052 kb
Host smart-d24fb97c-39e7-4be2-b051-a90331a4adc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380450228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.2380450228
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.2790073881
Short name T192
Test name
Test status
Simulation time 60696030 ps
CPU time 0.83 seconds
Started Jun 29 05:33:00 PM PDT 24
Finished Jun 29 05:33:01 PM PDT 24
Peak memory 219448 kb
Host smart-6a60daf0-183b-4572-bea7-7c3bd0e70314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790073881 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2790073881
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.845736045
Short name T45
Test name
Test status
Simulation time 70848495 ps
CPU time 1.22 seconds
Started Jun 29 05:32:58 PM PDT 24
Finished Jun 29 05:33:00 PM PDT 24
Peak memory 217720 kb
Host smart-3379d8a8-c598-438e-9d91-12074bafc401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845736045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.845736045
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.3688875208
Short name T132
Test name
Test status
Simulation time 45077846 ps
CPU time 1.19 seconds
Started Jun 29 05:33:00 PM PDT 24
Finished Jun 29 05:33:02 PM PDT 24
Peak memory 218908 kb
Host smart-e5cac5ab-0045-4b27-aff7-d3d8caddc4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688875208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.3688875208
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.2661242010
Short name T626
Test name
Test status
Simulation time 22624629 ps
CPU time 1.12 seconds
Started Jun 29 05:32:58 PM PDT 24
Finished Jun 29 05:32:59 PM PDT 24
Peak memory 218852 kb
Host smart-28ec04a4-99eb-42f5-8190-c8612503137e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661242010 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2661242010
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.1744706883
Short name T406
Test name
Test status
Simulation time 88268768 ps
CPU time 2.26 seconds
Started Jun 29 05:33:02 PM PDT 24
Finished Jun 29 05:33:05 PM PDT 24
Peak memory 220636 kb
Host smart-c5eae0cf-b9f6-4c59-9979-575b7272978f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744706883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1744706883
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.138396261
Short name T687
Test name
Test status
Simulation time 26856741 ps
CPU time 1.27 seconds
Started Jun 29 05:31:50 PM PDT 24
Finished Jun 29 05:31:52 PM PDT 24
Peak memory 219688 kb
Host smart-a0054d61-ab0c-4284-b351-e96d95c80f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138396261 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.138396261
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2086350605
Short name T79
Test name
Test status
Simulation time 14731019 ps
CPU time 0.94 seconds
Started Jun 29 05:31:57 PM PDT 24
Finished Jun 29 05:31:59 PM PDT 24
Peak memory 207004 kb
Host smart-26be69d9-aba1-4457-848a-e8cdf44ee4d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086350605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2086350605
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2362865022
Short name T612
Test name
Test status
Simulation time 31451592 ps
CPU time 0.86 seconds
Started Jun 29 05:31:53 PM PDT 24
Finished Jun 29 05:31:55 PM PDT 24
Peak memory 216548 kb
Host smart-6710dd98-5390-4bcc-8c4d-b0c30c43b384
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362865022 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2362865022
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.32349358
Short name T552
Test name
Test status
Simulation time 63176777 ps
CPU time 1.21 seconds
Started Jun 29 05:31:46 PM PDT 24
Finished Jun 29 05:31:48 PM PDT 24
Peak memory 217136 kb
Host smart-b0879c7a-2e7d-44cb-8610-0c187d65b2ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32349358 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disa
ble_auto_req_mode.32349358
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.4241141650
Short name T654
Test name
Test status
Simulation time 43768426 ps
CPU time 0.98 seconds
Started Jun 29 05:31:45 PM PDT 24
Finished Jun 29 05:31:47 PM PDT 24
Peak memory 220084 kb
Host smart-165db493-da63-43e3-b869-5a95dedddded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241141650 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.4241141650
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3926227351
Short name T328
Test name
Test status
Simulation time 56679381 ps
CPU time 1.27 seconds
Started Jun 29 05:31:50 PM PDT 24
Finished Jun 29 05:31:52 PM PDT 24
Peak memory 218820 kb
Host smart-0bc4eb81-23d1-4e58-8744-101afa469cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926227351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3926227351
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.4228243869
Short name T51
Test name
Test status
Simulation time 21908695 ps
CPU time 1.12 seconds
Started Jun 29 05:31:53 PM PDT 24
Finished Jun 29 05:31:55 PM PDT 24
Peak memory 215720 kb
Host smart-9fcedbff-8c3c-442c-a0cf-8e964ddfc3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228243869 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.4228243869
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.839053165
Short name T932
Test name
Test status
Simulation time 18532051 ps
CPU time 1.04 seconds
Started Jun 29 05:31:50 PM PDT 24
Finished Jun 29 05:31:52 PM PDT 24
Peak memory 207404 kb
Host smart-352b5742-9da9-4d87-8821-3b3865afe40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839053165 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.839053165
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.897880794
Short name T981
Test name
Test status
Simulation time 39193830 ps
CPU time 0.9 seconds
Started Jun 29 05:31:51 PM PDT 24
Finished Jun 29 05:31:52 PM PDT 24
Peak memory 215720 kb
Host smart-474ae740-1889-4671-8857-f75db182c06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897880794 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.897880794
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3515441766
Short name T928
Test name
Test status
Simulation time 265472132 ps
CPU time 2.13 seconds
Started Jun 29 05:31:55 PM PDT 24
Finished Jun 29 05:31:58 PM PDT 24
Peak memory 215648 kb
Host smart-e3556b2c-164d-4cf7-8ee3-9b7c197b5c68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515441766 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3515441766
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3335103069
Short name T230
Test name
Test status
Simulation time 164714791598 ps
CPU time 1123.17 seconds
Started Jun 29 05:31:48 PM PDT 24
Finished Jun 29 05:50:32 PM PDT 24
Peak memory 224780 kb
Host smart-492a6e1b-61fa-4a93-a39e-993c288e66f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335103069 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3335103069
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.4162900654
Short name T171
Test name
Test status
Simulation time 100399883 ps
CPU time 1.25 seconds
Started Jun 29 05:33:02 PM PDT 24
Finished Jun 29 05:33:03 PM PDT 24
Peak memory 220076 kb
Host smart-518af335-7460-4a9e-b2cb-9ea32e55b946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162900654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.4162900654
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.3537650262
Short name T759
Test name
Test status
Simulation time 24538641 ps
CPU time 0.98 seconds
Started Jun 29 05:33:01 PM PDT 24
Finished Jun 29 05:33:03 PM PDT 24
Peak memory 218692 kb
Host smart-662a1a3b-746b-4be8-8256-d909cfe29579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537650262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3537650262
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1965928622
Short name T559
Test name
Test status
Simulation time 25869276 ps
CPU time 1.29 seconds
Started Jun 29 05:33:03 PM PDT 24
Finished Jun 29 05:33:05 PM PDT 24
Peak memory 218680 kb
Host smart-7279db2b-2b4d-42ce-afba-e431aa6ebceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965928622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1965928622
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1524690981
Short name T649
Test name
Test status
Simulation time 26276129 ps
CPU time 1.21 seconds
Started Jun 29 05:33:09 PM PDT 24
Finished Jun 29 05:33:10 PM PDT 24
Peak memory 220960 kb
Host smart-6f5bbca5-3af6-484a-9392-155a64dbd600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524690981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1524690981
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.3375925185
Short name T115
Test name
Test status
Simulation time 47431892 ps
CPU time 0.9 seconds
Started Jun 29 05:33:00 PM PDT 24
Finished Jun 29 05:33:01 PM PDT 24
Peak memory 219848 kb
Host smart-25350be1-236f-4b2e-819d-49e30ce49a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375925185 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3375925185
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3882751879
Short name T762
Test name
Test status
Simulation time 70361475 ps
CPU time 1.1 seconds
Started Jun 29 05:33:04 PM PDT 24
Finished Jun 29 05:33:06 PM PDT 24
Peak memory 217512 kb
Host smart-955e015e-6bda-43be-86a9-a832383e9ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882751879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3882751879
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.2374165685
Short name T830
Test name
Test status
Simulation time 46962882 ps
CPU time 1.22 seconds
Started Jun 29 05:33:00 PM PDT 24
Finished Jun 29 05:33:02 PM PDT 24
Peak memory 221000 kb
Host smart-8c1691fc-8ca8-4e4d-b8fc-06866dc7940b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374165685 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.2374165685
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.1089021389
Short name T134
Test name
Test status
Simulation time 34515457 ps
CPU time 0.95 seconds
Started Jun 29 05:33:10 PM PDT 24
Finished Jun 29 05:33:11 PM PDT 24
Peak memory 219784 kb
Host smart-96b2f644-b2be-4235-ae62-6109b6020381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089021389 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1089021389
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1492942145
Short name T335
Test name
Test status
Simulation time 112691577 ps
CPU time 1.54 seconds
Started Jun 29 05:32:59 PM PDT 24
Finished Jun 29 05:33:01 PM PDT 24
Peak memory 219444 kb
Host smart-3bf8c226-90a5-4333-8998-2a8d35991d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492942145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1492942145
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.1969226906
Short name T128
Test name
Test status
Simulation time 84114922 ps
CPU time 1.34 seconds
Started Jun 29 05:33:10 PM PDT 24
Finished Jun 29 05:33:12 PM PDT 24
Peak memory 219144 kb
Host smart-8083dadb-047e-4e93-8f45-21db8b254e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969226906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.1969226906
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_genbits.2434271072
Short name T562
Test name
Test status
Simulation time 36894372 ps
CPU time 1.41 seconds
Started Jun 29 05:33:01 PM PDT 24
Finished Jun 29 05:33:03 PM PDT 24
Peak memory 217620 kb
Host smart-a3799e19-7366-4cac-8bfa-61c01ca46b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434271072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2434271072
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.1346422408
Short name T67
Test name
Test status
Simulation time 31446280 ps
CPU time 1.3 seconds
Started Jun 29 05:33:12 PM PDT 24
Finished Jun 29 05:33:15 PM PDT 24
Peak memory 219912 kb
Host smart-8e107a4c-db21-4bbd-9f95-5d3f2090abdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346422408 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1346422408
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3360521678
Short name T385
Test name
Test status
Simulation time 32275157 ps
CPU time 1.32 seconds
Started Jun 29 05:33:06 PM PDT 24
Finished Jun 29 05:33:08 PM PDT 24
Peak memory 218668 kb
Host smart-c2098d70-5b41-475f-bc4b-90b906cb9d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360521678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3360521678
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.289094712
Short name T297
Test name
Test status
Simulation time 106792378 ps
CPU time 1.26 seconds
Started Jun 29 05:33:11 PM PDT 24
Finished Jun 29 05:33:13 PM PDT 24
Peak memory 216000 kb
Host smart-5527a91d-3ebf-4eec-98ff-5ab3c6da04e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289094712 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.289094712
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.53372727
Short name T875
Test name
Test status
Simulation time 24730564 ps
CPU time 1 seconds
Started Jun 29 05:33:13 PM PDT 24
Finished Jun 29 05:33:15 PM PDT 24
Peak memory 218860 kb
Host smart-bc0143c8-4789-44b6-9a66-b51653f65fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53372727 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.53372727
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.685730389
Short name T446
Test name
Test status
Simulation time 33990137 ps
CPU time 1.51 seconds
Started Jun 29 05:33:07 PM PDT 24
Finished Jun 29 05:33:09 PM PDT 24
Peak memory 218792 kb
Host smart-22959330-f6e2-4738-9882-7a8904b7850e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685730389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.685730389
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.1932155538
Short name T540
Test name
Test status
Simulation time 68476182 ps
CPU time 1.22 seconds
Started Jun 29 05:33:17 PM PDT 24
Finished Jun 29 05:33:19 PM PDT 24
Peak memory 220084 kb
Host smart-2b929afd-a558-48cc-89b6-e6b7edb7163a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932155538 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.1932155538
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.1743171580
Short name T7
Test name
Test status
Simulation time 58906776 ps
CPU time 0.98 seconds
Started Jun 29 05:33:12 PM PDT 24
Finished Jun 29 05:33:13 PM PDT 24
Peak memory 219964 kb
Host smart-d76a74e2-ba53-4609-b1c0-669764084e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743171580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1743171580
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2865440168
Short name T859
Test name
Test status
Simulation time 54035660 ps
CPU time 1.18 seconds
Started Jun 29 05:33:13 PM PDT 24
Finished Jun 29 05:33:15 PM PDT 24
Peak memory 217716 kb
Host smart-4c14db65-5ee5-430b-9ef6-31376f8444ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865440168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2865440168
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.4218589617
Short name T138
Test name
Test status
Simulation time 100719674 ps
CPU time 1.25 seconds
Started Jun 29 05:33:14 PM PDT 24
Finished Jun 29 05:33:16 PM PDT 24
Peak memory 219940 kb
Host smart-45d40532-b9bc-4341-8124-c0117abd3152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218589617 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.4218589617
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.2818184992
Short name T110
Test name
Test status
Simulation time 104375883 ps
CPU time 1.06 seconds
Started Jun 29 05:33:08 PM PDT 24
Finished Jun 29 05:33:10 PM PDT 24
Peak memory 221020 kb
Host smart-23a1e66e-7065-4817-9a6e-fe515b1a64fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818184992 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2818184992
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.962986802
Short name T692
Test name
Test status
Simulation time 37333253 ps
CPU time 1.4 seconds
Started Jun 29 05:33:11 PM PDT 24
Finished Jun 29 05:33:13 PM PDT 24
Peak memory 217592 kb
Host smart-6630f6e5-babb-4400-9fd5-26273923d181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962986802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.962986802
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.1410487383
Short name T28
Test name
Test status
Simulation time 128294726 ps
CPU time 1.23 seconds
Started Jun 29 05:33:10 PM PDT 24
Finished Jun 29 05:33:12 PM PDT 24
Peak memory 219396 kb
Host smart-db7ffa2c-fdd9-46fd-b39e-d5eb30262d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410487383 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.1410487383
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.443965494
Short name T637
Test name
Test status
Simulation time 33322746 ps
CPU time 0.83 seconds
Started Jun 29 05:33:13 PM PDT 24
Finished Jun 29 05:33:15 PM PDT 24
Peak memory 218476 kb
Host smart-29f29273-fa4a-449b-a4e9-ab16b0ce720a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443965494 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.443965494
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3054857402
Short name T784
Test name
Test status
Simulation time 84229697 ps
CPU time 2.84 seconds
Started Jun 29 05:33:18 PM PDT 24
Finished Jun 29 05:33:22 PM PDT 24
Peak memory 220428 kb
Host smart-d5f9e8f8-0457-4762-81e8-edfbaf12a24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054857402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3054857402
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.792064973
Short name T166
Test name
Test status
Simulation time 32292465 ps
CPU time 1.35 seconds
Started Jun 29 05:33:22 PM PDT 24
Finished Jun 29 05:33:24 PM PDT 24
Peak memory 215996 kb
Host smart-84faca73-81c3-459f-8cea-e7b5821f72cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792064973 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.792064973
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.1912159186
Short name T8
Test name
Test status
Simulation time 23092582 ps
CPU time 1.13 seconds
Started Jun 29 05:33:27 PM PDT 24
Finished Jun 29 05:33:28 PM PDT 24
Peak memory 220184 kb
Host smart-e6f79403-7639-425c-955a-3c823f80aa3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912159186 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1912159186
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.723143439
Short name T971
Test name
Test status
Simulation time 50987107 ps
CPU time 1.49 seconds
Started Jun 29 05:33:17 PM PDT 24
Finished Jun 29 05:33:19 PM PDT 24
Peak memory 219100 kb
Host smart-e019ea8b-b724-4fa7-880a-b191f690aac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723143439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.723143439
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert_test.2100129926
Short name T477
Test name
Test status
Simulation time 46971365 ps
CPU time 0.84 seconds
Started Jun 29 05:31:44 PM PDT 24
Finished Jun 29 05:31:46 PM PDT 24
Peak memory 206992 kb
Host smart-1c58cf30-dcc6-4403-a3b6-ab0d77735a6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100129926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2100129926
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.733270686
Short name T66
Test name
Test status
Simulation time 13661856 ps
CPU time 0.93 seconds
Started Jun 29 05:31:51 PM PDT 24
Finished Jun 29 05:31:53 PM PDT 24
Peak memory 216712 kb
Host smart-9b5a8432-3262-4dc7-a15b-d53c387a563e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733270686 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.733270686
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.712860883
Short name T88
Test name
Test status
Simulation time 92167718 ps
CPU time 1.17 seconds
Started Jun 29 05:31:48 PM PDT 24
Finished Jun 29 05:31:50 PM PDT 24
Peak memory 219864 kb
Host smart-61e6e2ac-4157-4b59-aa91-5546a96d5b75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712860883 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.712860883
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.653702121
Short name T154
Test name
Test status
Simulation time 22036595 ps
CPU time 1.25 seconds
Started Jun 29 05:31:46 PM PDT 24
Finished Jun 29 05:31:48 PM PDT 24
Peak memory 229908 kb
Host smart-b7c6e206-b652-40d1-a043-f5b251c2057d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653702121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.653702121
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1934572938
Short name T741
Test name
Test status
Simulation time 50490820 ps
CPU time 1.28 seconds
Started Jun 29 05:31:52 PM PDT 24
Finished Jun 29 05:31:54 PM PDT 24
Peak memory 219212 kb
Host smart-14faade6-9a19-4c25-8ac3-604ebd7ff056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934572938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1934572938
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3653713161
Short name T461
Test name
Test status
Simulation time 26623244 ps
CPU time 1.05 seconds
Started Jun 29 05:31:58 PM PDT 24
Finished Jun 29 05:32:00 PM PDT 24
Peak memory 215816 kb
Host smart-06d1e9f5-500d-4516-a632-1131644bf3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653713161 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3653713161
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2751353336
Short name T910
Test name
Test status
Simulation time 24544509 ps
CPU time 0.95 seconds
Started Jun 29 05:31:48 PM PDT 24
Finished Jun 29 05:31:50 PM PDT 24
Peak memory 207416 kb
Host smart-6793fd2c-3c7a-4943-bc24-1077cea1c479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751353336 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2751353336
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1883863249
Short name T81
Test name
Test status
Simulation time 21155680 ps
CPU time 1.03 seconds
Started Jun 29 05:31:46 PM PDT 24
Finished Jun 29 05:31:48 PM PDT 24
Peak memory 207392 kb
Host smart-150cd0b4-c1c9-4646-be10-8294bb5822f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883863249 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1883863249
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1103236460
Short name T524
Test name
Test status
Simulation time 102456816 ps
CPU time 2.62 seconds
Started Jun 29 05:31:49 PM PDT 24
Finished Jun 29 05:31:52 PM PDT 24
Peak memory 217536 kb
Host smart-c8d66020-62aa-4772-9e21-3f1aefae660b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103236460 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1103236460
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2126630223
Short name T898
Test name
Test status
Simulation time 43223080792 ps
CPU time 285.82 seconds
Started Jun 29 05:31:48 PM PDT 24
Finished Jun 29 05:36:34 PM PDT 24
Peak memory 224004 kb
Host smart-7067f743-834b-456d-be91-ef202e985aa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126630223 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2126630223
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.1180413417
Short name T299
Test name
Test status
Simulation time 78667313 ps
CPU time 1.29 seconds
Started Jun 29 05:33:17 PM PDT 24
Finished Jun 29 05:33:18 PM PDT 24
Peak memory 220020 kb
Host smart-1124e33e-6ef4-4487-8378-72366c4ac041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180413417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.1180413417
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.1473505712
Short name T123
Test name
Test status
Simulation time 42045152 ps
CPU time 1.14 seconds
Started Jun 29 05:33:11 PM PDT 24
Finished Jun 29 05:33:13 PM PDT 24
Peak memory 217488 kb
Host smart-a169c2bb-3b5f-4951-acdb-ba91d3f027b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473505712 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1473505712
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3775012384
Short name T936
Test name
Test status
Simulation time 57169708 ps
CPU time 1.97 seconds
Started Jun 29 05:33:13 PM PDT 24
Finished Jun 29 05:33:16 PM PDT 24
Peak memory 217680 kb
Host smart-3a49eacd-c97d-4118-8755-55a956fd50f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775012384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3775012384
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.143118870
Short name T407
Test name
Test status
Simulation time 26111296 ps
CPU time 1.18 seconds
Started Jun 29 05:33:10 PM PDT 24
Finished Jun 29 05:33:18 PM PDT 24
Peak memory 218728 kb
Host smart-fe3bbb5b-e890-4691-b768-68013d91aa8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143118870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.143118870
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.2726984292
Short name T845
Test name
Test status
Simulation time 40525208 ps
CPU time 1.18 seconds
Started Jun 29 05:33:13 PM PDT 24
Finished Jun 29 05:33:15 PM PDT 24
Peak memory 217828 kb
Host smart-919c98c2-968e-4edf-ab0d-f4c21b318021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726984292 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2726984292
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.832536359
Short name T842
Test name
Test status
Simulation time 79694841 ps
CPU time 1.43 seconds
Started Jun 29 05:33:22 PM PDT 24
Finished Jun 29 05:33:23 PM PDT 24
Peak memory 219068 kb
Host smart-943b8b85-4965-4f69-a405-9c294e3a9295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832536359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.832536359
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.3958985859
Short name T300
Test name
Test status
Simulation time 22470060 ps
CPU time 1.22 seconds
Started Jun 29 05:33:13 PM PDT 24
Finished Jun 29 05:33:16 PM PDT 24
Peak memory 218992 kb
Host smart-27e2a713-1721-4946-86cf-7356f48a3727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958985859 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.3958985859
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.2151074314
Short name T899
Test name
Test status
Simulation time 19231763 ps
CPU time 1.09 seconds
Started Jun 29 05:33:11 PM PDT 24
Finished Jun 29 05:33:12 PM PDT 24
Peak memory 215800 kb
Host smart-8bb91d8d-c318-4d1a-b674-296f5a02582b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151074314 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2151074314
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3551538767
Short name T357
Test name
Test status
Simulation time 39445076 ps
CPU time 1.48 seconds
Started Jun 29 05:33:14 PM PDT 24
Finished Jun 29 05:33:17 PM PDT 24
Peak memory 218816 kb
Host smart-c8429ea3-31b7-48df-8df3-e20daa192228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551538767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3551538767
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.4132133084
Short name T781
Test name
Test status
Simulation time 21925360 ps
CPU time 1.2 seconds
Started Jun 29 05:33:10 PM PDT 24
Finished Jun 29 05:33:11 PM PDT 24
Peak memory 220088 kb
Host smart-d7dcdf01-9b16-4340-9ff9-9337ec8e910c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132133084 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.4132133084
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.1377967028
Short name T939
Test name
Test status
Simulation time 23650870 ps
CPU time 1.23 seconds
Started Jun 29 05:33:13 PM PDT 24
Finished Jun 29 05:33:15 PM PDT 24
Peak memory 220176 kb
Host smart-d4dd7de0-27d1-41e0-b69a-ea4b94363926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377967028 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1377967028
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1339791901
Short name T527
Test name
Test status
Simulation time 55391571 ps
CPU time 2.03 seconds
Started Jun 29 05:33:11 PM PDT 24
Finished Jun 29 05:33:13 PM PDT 24
Peak memory 220216 kb
Host smart-df40b5bf-2fef-4593-9212-2385dc0ef45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339791901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1339791901
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.3715403676
Short name T537
Test name
Test status
Simulation time 55001439 ps
CPU time 1.29 seconds
Started Jun 29 05:33:13 PM PDT 24
Finished Jun 29 05:33:16 PM PDT 24
Peak memory 220452 kb
Host smart-e58d945a-2c3f-4f84-b9a9-d7b60f9f3804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715403676 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.3715403676
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2989752384
Short name T571
Test name
Test status
Simulation time 24347283 ps
CPU time 0.92 seconds
Started Jun 29 05:33:13 PM PDT 24
Finished Jun 29 05:33:15 PM PDT 24
Peak memory 218532 kb
Host smart-3f6478af-7f4f-4737-a1af-819f6f603edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989752384 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2989752384
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3603420919
Short name T721
Test name
Test status
Simulation time 289481151 ps
CPU time 1.16 seconds
Started Jun 29 05:33:12 PM PDT 24
Finished Jun 29 05:33:14 PM PDT 24
Peak memory 217572 kb
Host smart-49481542-93ab-4460-a5e8-729cca3358e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603420919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3603420919
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.2284611651
Short name T531
Test name
Test status
Simulation time 43322674 ps
CPU time 1.13 seconds
Started Jun 29 05:33:13 PM PDT 24
Finished Jun 29 05:33:16 PM PDT 24
Peak memory 220140 kb
Host smart-900498a9-266e-4830-85ad-7530ce6b34c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284611651 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.2284611651
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.3057462813
Short name T874
Test name
Test status
Simulation time 19623520 ps
CPU time 1.08 seconds
Started Jun 29 05:33:10 PM PDT 24
Finished Jun 29 05:33:12 PM PDT 24
Peak memory 220004 kb
Host smart-4c693a1a-e1d3-49a6-8552-bba4801becc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057462813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3057462813
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3941931007
Short name T790
Test name
Test status
Simulation time 60889242 ps
CPU time 1.44 seconds
Started Jun 29 05:33:06 PM PDT 24
Finished Jun 29 05:33:08 PM PDT 24
Peak memory 219444 kb
Host smart-0f1c31ba-1575-4dcc-a969-050e111d3ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941931007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3941931007
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.19284564
Short name T180
Test name
Test status
Simulation time 43946450 ps
CPU time 1.2 seconds
Started Jun 29 05:33:23 PM PDT 24
Finished Jun 29 05:33:24 PM PDT 24
Peak memory 221052 kb
Host smart-4fe5b9eb-db8d-4a99-ae3b-79d4c2372b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19284564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.19284564
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.3211177561
Short name T591
Test name
Test status
Simulation time 21398644 ps
CPU time 1.18 seconds
Started Jun 29 05:33:12 PM PDT 24
Finished Jun 29 05:33:14 PM PDT 24
Peak memory 218884 kb
Host smart-ab19b827-e8a7-4a76-92fd-036d7bbc506d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211177561 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3211177561
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1349604547
Short name T10
Test name
Test status
Simulation time 81227636 ps
CPU time 1.73 seconds
Started Jun 29 05:33:10 PM PDT 24
Finished Jun 29 05:33:13 PM PDT 24
Peak memory 220320 kb
Host smart-c0a47146-ab40-4535-8a36-b7ceac24ae50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349604547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1349604547
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.700178537
Short name T686
Test name
Test status
Simulation time 96339717 ps
CPU time 1.09 seconds
Started Jun 29 05:33:11 PM PDT 24
Finished Jun 29 05:33:12 PM PDT 24
Peak memory 220124 kb
Host smart-da01b459-b854-428a-9fc7-a41d74346eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700178537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.700178537
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.2585648622
Short name T834
Test name
Test status
Simulation time 35304951 ps
CPU time 1.13 seconds
Started Jun 29 05:33:12 PM PDT 24
Finished Jun 29 05:33:14 PM PDT 24
Peak memory 229864 kb
Host smart-939e6f24-3bdb-452b-9cc6-42297d81a01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585648622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2585648622
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3510391010
Short name T530
Test name
Test status
Simulation time 90245500 ps
CPU time 3.34 seconds
Started Jun 29 05:33:09 PM PDT 24
Finished Jun 29 05:33:13 PM PDT 24
Peak memory 220544 kb
Host smart-a27fe4bb-adb8-4b90-8c25-5e304ab7777d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510391010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3510391010
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.782659768
Short name T52
Test name
Test status
Simulation time 30410537 ps
CPU time 1.29 seconds
Started Jun 29 05:33:16 PM PDT 24
Finished Jun 29 05:33:18 PM PDT 24
Peak memory 218876 kb
Host smart-fc3f7b0d-295d-4fad-8ec2-913124441926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782659768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.782659768
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.189557881
Short name T215
Test name
Test status
Simulation time 35746222 ps
CPU time 0.86 seconds
Started Jun 29 05:33:11 PM PDT 24
Finished Jun 29 05:33:12 PM PDT 24
Peak memory 219756 kb
Host smart-4e3dd0dc-3a0a-4f26-8158-1fc3b44e03e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189557881 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.189557881
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.379475214
Short name T732
Test name
Test status
Simulation time 35133882 ps
CPU time 1.31 seconds
Started Jun 29 05:33:15 PM PDT 24
Finished Jun 29 05:33:18 PM PDT 24
Peak memory 217584 kb
Host smart-625482e3-d06c-44d0-8bf3-993cf54c7829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379475214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.379475214
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.2443681303
Short name T172
Test name
Test status
Simulation time 78053808 ps
CPU time 1.09 seconds
Started Jun 29 05:33:07 PM PDT 24
Finished Jun 29 05:33:08 PM PDT 24
Peak memory 220024 kb
Host smart-88af6f1e-6c4a-4a8d-a3d9-e36d96141f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443681303 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.2443681303
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.674865108
Short name T16
Test name
Test status
Simulation time 94003207 ps
CPU time 1.33 seconds
Started Jun 29 05:33:12 PM PDT 24
Finished Jun 29 05:33:14 PM PDT 24
Peak memory 225936 kb
Host smart-266c95d7-3a7a-4ca5-988e-f95241e727b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674865108 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.674865108
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.535144229
Short name T550
Test name
Test status
Simulation time 33177402 ps
CPU time 1.3 seconds
Started Jun 29 05:33:09 PM PDT 24
Finished Jun 29 05:33:11 PM PDT 24
Peak memory 218800 kb
Host smart-9d8985a7-11bf-455d-b189-fd9188abcdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535144229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.535144229
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3670314383
Short name T846
Test name
Test status
Simulation time 91112823 ps
CPU time 1.18 seconds
Started Jun 29 05:31:54 PM PDT 24
Finished Jun 29 05:31:56 PM PDT 24
Peak memory 219796 kb
Host smart-96b1d653-7c59-43c0-820e-0ae41e72d709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670314383 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3670314383
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2566203333
Short name T367
Test name
Test status
Simulation time 28593505 ps
CPU time 0.92 seconds
Started Jun 29 05:31:47 PM PDT 24
Finished Jun 29 05:31:48 PM PDT 24
Peak memory 207040 kb
Host smart-38e05180-40a3-496e-bce6-ccd789bb915c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566203333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2566203333
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.92790405
Short name T728
Test name
Test status
Simulation time 11241453 ps
CPU time 0.88 seconds
Started Jun 29 05:31:54 PM PDT 24
Finished Jun 29 05:31:55 PM PDT 24
Peak memory 215712 kb
Host smart-ffda19e9-11d3-4d4d-bc13-e3d93c6cc505
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92790405 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.92790405
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.4273323376
Short name T156
Test name
Test status
Simulation time 77522871 ps
CPU time 1.22 seconds
Started Jun 29 05:31:51 PM PDT 24
Finished Jun 29 05:31:53 PM PDT 24
Peak memory 217072 kb
Host smart-d4476ca9-ad78-4718-88b1-001428bd0e95
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273323376 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.4273323376
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1376670717
Short name T760
Test name
Test status
Simulation time 19651166 ps
CPU time 1.14 seconds
Started Jun 29 05:31:50 PM PDT 24
Finished Jun 29 05:31:52 PM PDT 24
Peak memory 219932 kb
Host smart-22ab9723-a5cb-433e-af4c-485f0e76fbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376670717 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1376670717
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3225899914
Short name T993
Test name
Test status
Simulation time 107548231 ps
CPU time 1.07 seconds
Started Jun 29 05:31:48 PM PDT 24
Finished Jun 29 05:31:50 PM PDT 24
Peak memory 217480 kb
Host smart-e273a602-d5bc-48a4-9fba-a864bea56705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225899914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3225899914
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3626548880
Short name T852
Test name
Test status
Simulation time 20488760 ps
CPU time 1.1 seconds
Started Jun 29 05:31:50 PM PDT 24
Finished Jun 29 05:31:52 PM PDT 24
Peak memory 215796 kb
Host smart-8e15ae14-84ff-4dbd-b6ed-092dc8cb6f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626548880 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3626548880
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1128524926
Short name T495
Test name
Test status
Simulation time 16053453 ps
CPU time 1.05 seconds
Started Jun 29 05:31:55 PM PDT 24
Finished Jun 29 05:31:57 PM PDT 24
Peak memory 207404 kb
Host smart-9f1c587a-a0ba-45ec-b028-e3764e87f5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128524926 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1128524926
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2557511543
Short name T807
Test name
Test status
Simulation time 115709682 ps
CPU time 0.92 seconds
Started Jun 29 05:31:48 PM PDT 24
Finished Jun 29 05:31:49 PM PDT 24
Peak memory 215620 kb
Host smart-d498712f-da92-44e1-8baa-0e7ec4dd27cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557511543 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2557511543
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3407482239
Short name T616
Test name
Test status
Simulation time 244867804 ps
CPU time 4.92 seconds
Started Jun 29 05:31:54 PM PDT 24
Finished Jun 29 05:32:00 PM PDT 24
Peak memory 218792 kb
Host smart-3ecd11dc-0764-4584-b008-31ef6ade349c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407482239 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3407482239
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1535693039
Short name T228
Test name
Test status
Simulation time 106066747355 ps
CPU time 621.13 seconds
Started Jun 29 05:31:46 PM PDT 24
Finished Jun 29 05:42:08 PM PDT 24
Peak memory 220492 kb
Host smart-9bae820e-c3bd-436c-8755-5938d4aecaed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535693039 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1535693039
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.4215145734
Short name T813
Test name
Test status
Simulation time 33336175 ps
CPU time 1.39 seconds
Started Jun 29 05:33:13 PM PDT 24
Finished Jun 29 05:33:16 PM PDT 24
Peak memory 220156 kb
Host smart-a0303579-c4a0-4c17-beb5-f2584c8e13b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215145734 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.4215145734
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.1955450720
Short name T6
Test name
Test status
Simulation time 49165844 ps
CPU time 0.86 seconds
Started Jun 29 05:33:27 PM PDT 24
Finished Jun 29 05:33:28 PM PDT 24
Peak memory 218476 kb
Host smart-ba2f93a6-4623-493b-b7a3-66cb33d0e0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955450720 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1955450720
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3419833204
Short name T287
Test name
Test status
Simulation time 98632681 ps
CPU time 1.16 seconds
Started Jun 29 05:33:15 PM PDT 24
Finished Jun 29 05:33:17 PM PDT 24
Peak memory 217612 kb
Host smart-d678ce25-40e9-4134-837c-5b8df94557bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419833204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3419833204
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1605157139
Short name T366
Test name
Test status
Simulation time 58318542 ps
CPU time 1.18 seconds
Started Jun 29 05:33:25 PM PDT 24
Finished Jun 29 05:33:26 PM PDT 24
Peak memory 220756 kb
Host smart-0ad7df1e-07da-49c2-9c03-7935b2396c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605157139 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1605157139
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.2489995369
Short name T605
Test name
Test status
Simulation time 43079889 ps
CPU time 1.23 seconds
Started Jun 29 05:33:23 PM PDT 24
Finished Jun 29 05:33:24 PM PDT 24
Peak memory 225900 kb
Host smart-dba28b14-33a2-43b7-bec7-cd5efb71b725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489995369 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2489995369
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/82.edn_alert.2550421938
Short name T653
Test name
Test status
Simulation time 24574590 ps
CPU time 1.26 seconds
Started Jun 29 05:33:27 PM PDT 24
Finished Jun 29 05:33:29 PM PDT 24
Peak memory 219976 kb
Host smart-6761f86e-4e1d-4016-b088-2deff566fa2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550421938 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.2550421938
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.3247819576
Short name T189
Test name
Test status
Simulation time 18688162 ps
CPU time 1.05 seconds
Started Jun 29 05:33:21 PM PDT 24
Finished Jun 29 05:33:23 PM PDT 24
Peak memory 218780 kb
Host smart-fba2d4ac-6233-4582-a270-97a1421d9877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247819576 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3247819576
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3342518299
Short name T319
Test name
Test status
Simulation time 92624528 ps
CPU time 1.23 seconds
Started Jun 29 05:33:22 PM PDT 24
Finished Jun 29 05:33:23 PM PDT 24
Peak memory 218920 kb
Host smart-50f59f1e-b054-4d2a-89ac-74c817d22cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342518299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3342518299
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.2816001808
Short name T217
Test name
Test status
Simulation time 86388380 ps
CPU time 1.25 seconds
Started Jun 29 05:33:24 PM PDT 24
Finished Jun 29 05:33:26 PM PDT 24
Peak memory 220692 kb
Host smart-d2db1c72-e9c9-4783-9d63-12b1ce1daba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816001808 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.2816001808
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.3980910160
Short name T748
Test name
Test status
Simulation time 20818251 ps
CPU time 1.07 seconds
Started Jun 29 05:33:27 PM PDT 24
Finished Jun 29 05:33:28 PM PDT 24
Peak memory 218780 kb
Host smart-6d93131a-0942-4a8b-a5a4-124fa4077377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980910160 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3980910160
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.795198145
Short name T343
Test name
Test status
Simulation time 146698823 ps
CPU time 1.2 seconds
Started Jun 29 05:33:29 PM PDT 24
Finished Jun 29 05:33:31 PM PDT 24
Peak memory 219420 kb
Host smart-1eac8070-b2e4-40f1-8698-85601f49b29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795198145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.795198145
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.214661119
Short name T471
Test name
Test status
Simulation time 271025447 ps
CPU time 1.48 seconds
Started Jun 29 05:33:15 PM PDT 24
Finished Jun 29 05:33:18 PM PDT 24
Peak memory 219432 kb
Host smart-efa4fbf8-bf78-4d3f-b7ce-03820c129321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214661119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.214661119
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.3770232001
Short name T60
Test name
Test status
Simulation time 36475713 ps
CPU time 1.03 seconds
Started Jun 29 05:33:26 PM PDT 24
Finished Jun 29 05:33:27 PM PDT 24
Peak memory 224064 kb
Host smart-556f80a6-a30d-4657-90d9-f3842704e60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770232001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3770232001
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1646912988
Short name T596
Test name
Test status
Simulation time 354113336 ps
CPU time 4.04 seconds
Started Jun 29 05:33:20 PM PDT 24
Finished Jun 29 05:33:25 PM PDT 24
Peak memory 217608 kb
Host smart-fd333675-adf8-4682-bc6e-6609136ba341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646912988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1646912988
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.4252195880
Short name T876
Test name
Test status
Simulation time 30439517 ps
CPU time 1.25 seconds
Started Jun 29 05:33:29 PM PDT 24
Finished Jun 29 05:33:30 PM PDT 24
Peak memory 215940 kb
Host smart-e07544fe-b032-412c-97f8-5a81bee6fbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252195880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.4252195880
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.3146289690
Short name T673
Test name
Test status
Simulation time 19063537 ps
CPU time 1.08 seconds
Started Jun 29 05:33:25 PM PDT 24
Finished Jun 29 05:33:27 PM PDT 24
Peak memory 218676 kb
Host smart-ef9adb46-01f2-4131-b123-c60f826e23b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146289690 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3146289690
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/86.edn_alert.3683291689
Short name T310
Test name
Test status
Simulation time 76321674 ps
CPU time 1.14 seconds
Started Jun 29 05:33:17 PM PDT 24
Finished Jun 29 05:33:20 PM PDT 24
Peak memory 219036 kb
Host smart-b25a7fc1-5128-40f5-be94-7fad7b9bb8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683291689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.3683291689
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2514535887
Short name T601
Test name
Test status
Simulation time 21282288 ps
CPU time 0.93 seconds
Started Jun 29 05:33:14 PM PDT 24
Finished Jun 29 05:33:16 PM PDT 24
Peak memory 218560 kb
Host smart-b806da95-a6ee-44ad-804b-452da93ca362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514535887 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2514535887
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3790163305
Short name T884
Test name
Test status
Simulation time 208490384 ps
CPU time 1.26 seconds
Started Jun 29 05:33:29 PM PDT 24
Finished Jun 29 05:33:30 PM PDT 24
Peak memory 220324 kb
Host smart-fbc1f3ef-549c-4b25-81db-d8d975eabf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790163305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3790163305
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.15761194
Short name T82
Test name
Test status
Simulation time 148215790 ps
CPU time 1.22 seconds
Started Jun 29 05:33:18 PM PDT 24
Finished Jun 29 05:33:20 PM PDT 24
Peak memory 219176 kb
Host smart-60b3ec3a-fa23-403d-84ae-6f5d7018d44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15761194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.15761194
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.1444180440
Short name T131
Test name
Test status
Simulation time 31531977 ps
CPU time 1.08 seconds
Started Jun 29 05:33:30 PM PDT 24
Finished Jun 29 05:33:33 PM PDT 24
Peak memory 220100 kb
Host smart-8f28006a-ceb0-47db-950c-632d13beb48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444180440 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1444180440
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2656166527
Short name T675
Test name
Test status
Simulation time 54510346 ps
CPU time 1.17 seconds
Started Jun 29 05:33:24 PM PDT 24
Finished Jun 29 05:33:26 PM PDT 24
Peak memory 217464 kb
Host smart-6550a48b-d232-43a1-b22c-0e84177e9d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656166527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2656166527
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.4147183336
Short name T545
Test name
Test status
Simulation time 82807068 ps
CPU time 1.38 seconds
Started Jun 29 05:33:15 PM PDT 24
Finished Jun 29 05:33:18 PM PDT 24
Peak memory 219772 kb
Host smart-163708ce-521c-4c2a-95be-e6a867b88bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147183336 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.4147183336
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.1706406497
Short name T146
Test name
Test status
Simulation time 25175643 ps
CPU time 1 seconds
Started Jun 29 05:33:21 PM PDT 24
Finished Jun 29 05:33:23 PM PDT 24
Peak memory 219800 kb
Host smart-e5d6077a-b024-4377-ab40-191e5ae6a3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706406497 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1706406497
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/89.edn_alert.1769912358
Short name T610
Test name
Test status
Simulation time 105723674 ps
CPU time 1.2 seconds
Started Jun 29 05:33:18 PM PDT 24
Finished Jun 29 05:33:20 PM PDT 24
Peak memory 218992 kb
Host smart-efa92a44-3f3d-43b4-b3a1-441c41ff40ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769912358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.1769912358
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.4036921541
Short name T61
Test name
Test status
Simulation time 36317473 ps
CPU time 1.36 seconds
Started Jun 29 05:33:15 PM PDT 24
Finished Jun 29 05:33:18 PM PDT 24
Peak memory 230808 kb
Host smart-da5157ca-32eb-47a1-80cc-5b48d826588e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036921541 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.4036921541
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2015512388
Short name T437
Test name
Test status
Simulation time 25772066 ps
CPU time 1.05 seconds
Started Jun 29 05:33:28 PM PDT 24
Finished Jun 29 05:33:30 PM PDT 24
Peak memory 219288 kb
Host smart-b43fe71a-efc6-4fb8-85b2-ab05b3afcdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015512388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2015512388
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3835560826
Short name T260
Test name
Test status
Simulation time 29266540 ps
CPU time 1.32 seconds
Started Jun 29 05:31:58 PM PDT 24
Finished Jun 29 05:32:00 PM PDT 24
Peak memory 219012 kb
Host smart-3a3bf423-b143-48d0-a5dd-9657e4609c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835560826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3835560826
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.558230984
Short name T458
Test name
Test status
Simulation time 39402969 ps
CPU time 1.25 seconds
Started Jun 29 05:31:54 PM PDT 24
Finished Jun 29 05:31:56 PM PDT 24
Peak memory 215268 kb
Host smart-7ab84180-f9b7-4837-991a-98a7334f123c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558230984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.558230984
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1231374745
Short name T697
Test name
Test status
Simulation time 120419159 ps
CPU time 0.81 seconds
Started Jun 29 05:31:56 PM PDT 24
Finished Jun 29 05:31:58 PM PDT 24
Peak memory 216564 kb
Host smart-99deb056-faaf-4ddd-9b9d-19ee5fdd8770
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231374745 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1231374745
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1585196434
Short name T679
Test name
Test status
Simulation time 41265332 ps
CPU time 1.3 seconds
Started Jun 29 05:31:57 PM PDT 24
Finished Jun 29 05:31:59 PM PDT 24
Peak memory 217276 kb
Host smart-b3373761-b9ac-49a2-a2ba-be535db73a06
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585196434 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1585196434
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.202730345
Short name T155
Test name
Test status
Simulation time 37798760 ps
CPU time 1.29 seconds
Started Jun 29 05:32:03 PM PDT 24
Finished Jun 29 05:32:05 PM PDT 24
Peak memory 229936 kb
Host smart-3c88143e-bdc1-41e3-a5ca-bf86dbb3b1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202730345 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.202730345
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.4101247552
Short name T322
Test name
Test status
Simulation time 64869378 ps
CPU time 1.67 seconds
Started Jun 29 05:31:54 PM PDT 24
Finished Jun 29 05:31:56 PM PDT 24
Peak memory 215872 kb
Host smart-f0426175-e167-42be-907f-ba4111fb2229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101247552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.4101247552
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3091732366
Short name T544
Test name
Test status
Simulation time 28843257 ps
CPU time 1.14 seconds
Started Jun 29 05:31:58 PM PDT 24
Finished Jun 29 05:32:00 PM PDT 24
Peak memory 224196 kb
Host smart-250d0c6b-8011-4fbe-8652-ebe4ecddb231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091732366 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3091732366
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.288524076
Short name T312
Test name
Test status
Simulation time 47279855 ps
CPU time 0.88 seconds
Started Jun 29 05:31:54 PM PDT 24
Finished Jun 29 05:31:56 PM PDT 24
Peak memory 207412 kb
Host smart-ec4d99d4-866c-4a4b-80c1-57e09c945758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288524076 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.288524076
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1858710151
Short name T563
Test name
Test status
Simulation time 26734652 ps
CPU time 0.99 seconds
Started Jun 29 05:31:50 PM PDT 24
Finished Jun 29 05:31:52 PM PDT 24
Peak memory 215620 kb
Host smart-b2b8fa86-751f-4adf-9dcd-f9ca737eb29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858710151 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1858710151
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1313609368
Short name T78
Test name
Test status
Simulation time 63767134 ps
CPU time 1.85 seconds
Started Jun 29 05:32:02 PM PDT 24
Finished Jun 29 05:32:05 PM PDT 24
Peak memory 217592 kb
Host smart-5d3c9e16-c70e-43fc-acc8-c8ff6b1fced1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313609368 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1313609368
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.4131114486
Short name T238
Test name
Test status
Simulation time 116742297715 ps
CPU time 690.87 seconds
Started Jun 29 05:31:50 PM PDT 24
Finished Jun 29 05:43:22 PM PDT 24
Peak memory 224012 kb
Host smart-faefd319-d4d2-4e1c-b9fe-543d93dce26b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131114486 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.4131114486
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.3124611058
Short name T27
Test name
Test status
Simulation time 65600147 ps
CPU time 1.17 seconds
Started Jun 29 05:33:16 PM PDT 24
Finished Jun 29 05:33:18 PM PDT 24
Peak memory 219068 kb
Host smart-bc12b9ff-5a9a-4b6d-be5b-c163872f2091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124611058 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.3124611058
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.1609160795
Short name T820
Test name
Test status
Simulation time 52732177 ps
CPU time 0.9 seconds
Started Jun 29 05:33:15 PM PDT 24
Finished Jun 29 05:33:17 PM PDT 24
Peak memory 219668 kb
Host smart-45f9d871-75c7-4f0d-a857-2c85a19bed6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609160795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1609160795
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1645749835
Short name T320
Test name
Test status
Simulation time 31029244 ps
CPU time 1.4 seconds
Started Jun 29 05:33:21 PM PDT 24
Finished Jun 29 05:33:23 PM PDT 24
Peak memory 217420 kb
Host smart-ddbe56c8-1364-4fdd-b8be-5a0a3ae95afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645749835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1645749835
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.3131089896
Short name T221
Test name
Test status
Simulation time 65363145 ps
CPU time 1.29 seconds
Started Jun 29 05:33:30 PM PDT 24
Finished Jun 29 05:33:32 PM PDT 24
Peak memory 221436 kb
Host smart-d4106541-7e38-4925-9d94-652bd288a078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131089896 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.3131089896
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.210543527
Short name T124
Test name
Test status
Simulation time 36845916 ps
CPU time 1.11 seconds
Started Jun 29 05:33:16 PM PDT 24
Finished Jun 29 05:33:18 PM PDT 24
Peak memory 220896 kb
Host smart-3c985dfc-915b-40ac-a321-c438cda76120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210543527 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.210543527
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.895368160
Short name T451
Test name
Test status
Simulation time 36601724 ps
CPU time 1.5 seconds
Started Jun 29 05:33:17 PM PDT 24
Finished Jun 29 05:33:19 PM PDT 24
Peak memory 220336 kb
Host smart-800016c2-7172-496c-8620-13651ea48d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895368160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.895368160
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.2754935604
Short name T162
Test name
Test status
Simulation time 41149701 ps
CPU time 1.2 seconds
Started Jun 29 05:33:23 PM PDT 24
Finished Jun 29 05:33:25 PM PDT 24
Peak memory 218984 kb
Host smart-bafaeff6-22b8-4ba3-9b77-a89f596ff4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754935604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.2754935604
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.215542437
Short name T165
Test name
Test status
Simulation time 44403220 ps
CPU time 1.24 seconds
Started Jun 29 05:33:35 PM PDT 24
Finished Jun 29 05:33:37 PM PDT 24
Peak memory 219804 kb
Host smart-801d4cbb-3a24-4c05-a7c5-43e8afbd6be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215542437 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.215542437
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3936849802
Short name T340
Test name
Test status
Simulation time 119416671 ps
CPU time 2.85 seconds
Started Jun 29 05:33:24 PM PDT 24
Finished Jun 29 05:33:28 PM PDT 24
Peak memory 220416 kb
Host smart-fcf498b8-047a-478a-b643-83689bc1db11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936849802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3936849802
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.4025326110
Short name T831
Test name
Test status
Simulation time 24898082 ps
CPU time 1.24 seconds
Started Jun 29 05:33:21 PM PDT 24
Finished Jun 29 05:33:23 PM PDT 24
Peak memory 218792 kb
Host smart-20c4758e-ccde-49b8-982d-9b81b704a283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025326110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.4025326110
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.887529276
Short name T975
Test name
Test status
Simulation time 23648819 ps
CPU time 1.3 seconds
Started Jun 29 05:33:23 PM PDT 24
Finished Jun 29 05:33:25 PM PDT 24
Peak memory 224204 kb
Host smart-725aee75-c817-4158-9082-0f775ec93ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887529276 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.887529276
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2422408761
Short name T771
Test name
Test status
Simulation time 87247855 ps
CPU time 1.18 seconds
Started Jun 29 05:33:15 PM PDT 24
Finished Jun 29 05:33:18 PM PDT 24
Peak memory 219820 kb
Host smart-7a67381a-1235-4847-8f73-ca580bf3739f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422408761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2422408761
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.3522126352
Short name T59
Test name
Test status
Simulation time 30529720 ps
CPU time 0.99 seconds
Started Jun 29 05:33:15 PM PDT 24
Finished Jun 29 05:33:17 PM PDT 24
Peak memory 224000 kb
Host smart-e5f46e0d-7a52-4cfb-8fbf-46c5645afe6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522126352 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3522126352
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3280941128
Short name T424
Test name
Test status
Simulation time 62309696 ps
CPU time 1.02 seconds
Started Jun 29 05:33:26 PM PDT 24
Finished Jun 29 05:33:27 PM PDT 24
Peak memory 217540 kb
Host smart-1974ac4d-59cf-42c1-a38c-a6553a06fa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280941128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3280941128
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.353371478
Short name T725
Test name
Test status
Simulation time 71703717 ps
CPU time 1.13 seconds
Started Jun 29 05:33:25 PM PDT 24
Finished Jun 29 05:33:26 PM PDT 24
Peak memory 218856 kb
Host smart-8409bf0d-f993-42e5-b2dc-e19b48f8d25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353371478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.353371478
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.2645560932
Short name T703
Test name
Test status
Simulation time 27776814 ps
CPU time 0.99 seconds
Started Jun 29 05:33:18 PM PDT 24
Finished Jun 29 05:33:20 PM PDT 24
Peak memory 219096 kb
Host smart-c1692e97-c581-43ec-8267-07ac0f54053d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645560932 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2645560932
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2742208978
Short name T710
Test name
Test status
Simulation time 21845180 ps
CPU time 1.13 seconds
Started Jun 29 05:33:14 PM PDT 24
Finished Jun 29 05:33:16 PM PDT 24
Peak memory 215588 kb
Host smart-a575d6a0-9d88-4513-8a2d-9dd8a45e6823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742208978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2742208978
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.2957364594
Short name T161
Test name
Test status
Simulation time 68901823 ps
CPU time 1.16 seconds
Started Jun 29 05:33:23 PM PDT 24
Finished Jun 29 05:33:24 PM PDT 24
Peak memory 220860 kb
Host smart-828dfb24-d103-40ef-a3d0-75efe6f40cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957364594 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.2957364594
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.1808213730
Short name T99
Test name
Test status
Simulation time 18687598 ps
CPU time 1.09 seconds
Started Jun 29 05:33:18 PM PDT 24
Finished Jun 29 05:33:20 PM PDT 24
Peak memory 218756 kb
Host smart-58dbf3be-0a2b-43ba-a7a7-404ac219e1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808213730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1808213730
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.366257589
Short name T389
Test name
Test status
Simulation time 74530292 ps
CPU time 1.62 seconds
Started Jun 29 05:33:23 PM PDT 24
Finished Jun 29 05:33:25 PM PDT 24
Peak memory 218956 kb
Host smart-e22968cd-dd56-4dc6-9467-ca0eb45e8ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366257589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.366257589
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.3702498759
Short name T707
Test name
Test status
Simulation time 36545593 ps
CPU time 1.19 seconds
Started Jun 29 05:33:16 PM PDT 24
Finished Jun 29 05:33:18 PM PDT 24
Peak memory 221008 kb
Host smart-ed302989-bc7d-46c8-948e-96522b830730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702498759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.3702498759
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.118047069
Short name T466
Test name
Test status
Simulation time 43674915 ps
CPU time 1.02 seconds
Started Jun 29 05:33:16 PM PDT 24
Finished Jun 29 05:33:18 PM PDT 24
Peak memory 218968 kb
Host smart-27dbe8ce-8d70-4fdd-b4f0-5544364fb9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118047069 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.118047069
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.950658445
Short name T342
Test name
Test status
Simulation time 769106563 ps
CPU time 5.84 seconds
Started Jun 29 05:33:16 PM PDT 24
Finished Jun 29 05:33:23 PM PDT 24
Peak memory 219180 kb
Host smart-8206b39e-eeb6-4542-a3dc-3cb622330318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950658445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.950658445
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.494639915
Short name T744
Test name
Test status
Simulation time 82850815 ps
CPU time 1.18 seconds
Started Jun 29 05:33:27 PM PDT 24
Finished Jun 29 05:33:29 PM PDT 24
Peak memory 219872 kb
Host smart-320465a0-1338-442c-b0c1-065abb121ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494639915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.494639915
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.1805612070
Short name T135
Test name
Test status
Simulation time 25216835 ps
CPU time 0.98 seconds
Started Jun 29 05:33:29 PM PDT 24
Finished Jun 29 05:33:31 PM PDT 24
Peak memory 220116 kb
Host smart-3733193c-c5ba-4d34-b5a1-a73c7e774f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805612070 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1805612070
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2547041599
Short name T908
Test name
Test status
Simulation time 80641318 ps
CPU time 1.15 seconds
Started Jun 29 05:33:14 PM PDT 24
Finished Jun 29 05:33:16 PM PDT 24
Peak memory 217668 kb
Host smart-e4ecbc1d-8fd2-4a54-9cbc-1da6fa075786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547041599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2547041599
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.182109926
Short name T696
Test name
Test status
Simulation time 76305298 ps
CPU time 1.06 seconds
Started Jun 29 05:33:15 PM PDT 24
Finished Jun 29 05:33:18 PM PDT 24
Peak memory 220100 kb
Host smart-c7792fbe-1eb8-4220-ad69-aec975c899be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182109926 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.182109926
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.290243852
Short name T746
Test name
Test status
Simulation time 33170202 ps
CPU time 1.07 seconds
Started Jun 29 05:33:30 PM PDT 24
Finished Jun 29 05:33:31 PM PDT 24
Peak memory 218812 kb
Host smart-bf207a51-6721-4dd4-8163-4be4654dedc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290243852 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.290243852
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1453267311
Short name T584
Test name
Test status
Simulation time 256767802 ps
CPU time 3.46 seconds
Started Jun 29 05:33:21 PM PDT 24
Finished Jun 29 05:33:25 PM PDT 24
Peak memory 220096 kb
Host smart-a5bbcd26-7e95-4a9e-9a91-18b605621c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453267311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1453267311
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%