Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.45 98.25 93.91 97.07 90.70 96.37 99.77 92.08


Total test records in report: 1130
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T1020 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1985862587 Jun 30 06:18:24 PM PDT 24 Jun 30 06:18:27 PM PDT 24 107062706 ps
T1021 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.285063622 Jun 30 06:18:29 PM PDT 24 Jun 30 06:18:31 PM PDT 24 22813264 ps
T1022 /workspace/coverage/cover_reg_top/34.edn_intr_test.3837710165 Jun 30 06:18:53 PM PDT 24 Jun 30 06:18:55 PM PDT 24 15816971 ps
T1023 /workspace/coverage/cover_reg_top/36.edn_intr_test.1396687910 Jun 30 06:18:57 PM PDT 24 Jun 30 06:18:59 PM PDT 24 24450285 ps
T1024 /workspace/coverage/cover_reg_top/45.edn_intr_test.432111716 Jun 30 06:18:51 PM PDT 24 Jun 30 06:18:53 PM PDT 24 51102319 ps
T1025 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2232542752 Jun 30 06:18:29 PM PDT 24 Jun 30 06:18:31 PM PDT 24 121080473 ps
T1026 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1775910594 Jun 30 06:18:39 PM PDT 24 Jun 30 06:18:40 PM PDT 24 63567506 ps
T1027 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2381092952 Jun 30 06:18:30 PM PDT 24 Jun 30 06:18:31 PM PDT 24 16579593 ps
T265 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.386230768 Jun 30 06:18:29 PM PDT 24 Jun 30 06:18:32 PM PDT 24 169602961 ps
T1028 /workspace/coverage/cover_reg_top/0.edn_intr_test.2531348074 Jun 30 06:18:14 PM PDT 24 Jun 30 06:18:15 PM PDT 24 69477220 ps
T1029 /workspace/coverage/cover_reg_top/37.edn_intr_test.352793994 Jun 30 06:18:53 PM PDT 24 Jun 30 06:18:56 PM PDT 24 30188790 ps
T1030 /workspace/coverage/cover_reg_top/25.edn_intr_test.74446113 Jun 30 06:18:53 PM PDT 24 Jun 30 06:18:56 PM PDT 24 58400010 ps
T1031 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1421158 Jun 30 06:18:35 PM PDT 24 Jun 30 06:18:38 PM PDT 24 50165982 ps
T1032 /workspace/coverage/cover_reg_top/40.edn_intr_test.1897281009 Jun 30 06:18:56 PM PDT 24 Jun 30 06:18:58 PM PDT 24 19455114 ps
T239 /workspace/coverage/cover_reg_top/11.edn_csr_rw.206580129 Jun 30 06:18:32 PM PDT 24 Jun 30 06:18:33 PM PDT 24 55625165 ps
T1033 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1616433921 Jun 30 06:18:32 PM PDT 24 Jun 30 06:18:34 PM PDT 24 80155531 ps
T1034 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.754304556 Jun 30 06:18:46 PM PDT 24 Jun 30 06:18:48 PM PDT 24 22092347 ps
T255 /workspace/coverage/cover_reg_top/13.edn_csr_rw.4029600084 Jun 30 06:18:39 PM PDT 24 Jun 30 06:18:40 PM PDT 24 18528139 ps
T1035 /workspace/coverage/cover_reg_top/49.edn_intr_test.477168341 Jun 30 06:18:56 PM PDT 24 Jun 30 06:18:58 PM PDT 24 14960583 ps
T256 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1719865113 Jun 30 06:18:21 PM PDT 24 Jun 30 06:18:22 PM PDT 24 246568475 ps
T1036 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.922290815 Jun 30 06:18:31 PM PDT 24 Jun 30 06:18:33 PM PDT 24 225050579 ps
T240 /workspace/coverage/cover_reg_top/7.edn_csr_rw.43442785 Jun 30 06:18:35 PM PDT 24 Jun 30 06:18:37 PM PDT 24 15299915 ps
T266 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3260174880 Jun 30 06:18:29 PM PDT 24 Jun 30 06:18:32 PM PDT 24 72497921 ps
T1037 /workspace/coverage/cover_reg_top/44.edn_intr_test.2662714360 Jun 30 06:18:53 PM PDT 24 Jun 30 06:18:55 PM PDT 24 38551599 ps
T257 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3642646026 Jun 30 06:18:35 PM PDT 24 Jun 30 06:18:37 PM PDT 24 28249115 ps
T1038 /workspace/coverage/cover_reg_top/2.edn_intr_test.3185655871 Jun 30 06:18:21 PM PDT 24 Jun 30 06:18:23 PM PDT 24 32763149 ps
T1039 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1021540549 Jun 30 06:18:46 PM PDT 24 Jun 30 06:18:49 PM PDT 24 114152368 ps
T1040 /workspace/coverage/cover_reg_top/6.edn_tl_errors.37772593 Jun 30 06:18:29 PM PDT 24 Jun 30 06:18:35 PM PDT 24 589068236 ps
T1041 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1281912979 Jun 30 06:18:41 PM PDT 24 Jun 30 06:18:44 PM PDT 24 94993218 ps
T1042 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.313141480 Jun 30 06:18:40 PM PDT 24 Jun 30 06:18:42 PM PDT 24 39974393 ps
T1043 /workspace/coverage/cover_reg_top/8.edn_intr_test.1291799573 Jun 30 06:18:34 PM PDT 24 Jun 30 06:18:36 PM PDT 24 12144687 ps
T1044 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1269845482 Jun 30 06:18:29 PM PDT 24 Jun 30 06:18:30 PM PDT 24 144056157 ps
T1045 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1226743151 Jun 30 06:18:42 PM PDT 24 Jun 30 06:18:44 PM PDT 24 36302252 ps
T1046 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2608634218 Jun 30 06:18:21 PM PDT 24 Jun 30 06:18:23 PM PDT 24 150010142 ps
T1047 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3077933062 Jun 30 06:18:49 PM PDT 24 Jun 30 06:18:54 PM PDT 24 207437136 ps
T273 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.964357194 Jun 30 06:18:40 PM PDT 24 Jun 30 06:18:44 PM PDT 24 122006784 ps
T1048 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2597038113 Jun 30 06:18:20 PM PDT 24 Jun 30 06:18:22 PM PDT 24 24460120 ps
T241 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.417755402 Jun 30 06:18:20 PM PDT 24 Jun 30 06:18:21 PM PDT 24 57335778 ps
T242 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3281276434 Jun 30 06:18:47 PM PDT 24 Jun 30 06:18:49 PM PDT 24 17767937 ps
T1049 /workspace/coverage/cover_reg_top/1.edn_intr_test.1209740642 Jun 30 06:18:17 PM PDT 24 Jun 30 06:18:18 PM PDT 24 39098360 ps
T1050 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3064953634 Jun 30 06:18:30 PM PDT 24 Jun 30 06:18:32 PM PDT 24 22080204 ps
T1051 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2056093912 Jun 30 06:18:32 PM PDT 24 Jun 30 06:18:35 PM PDT 24 193029743 ps
T1052 /workspace/coverage/cover_reg_top/27.edn_intr_test.935778082 Jun 30 06:18:54 PM PDT 24 Jun 30 06:18:56 PM PDT 24 15417980 ps
T1053 /workspace/coverage/cover_reg_top/24.edn_intr_test.1278982611 Jun 30 06:18:53 PM PDT 24 Jun 30 06:18:55 PM PDT 24 47658508 ps
T1054 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.297053679 Jun 30 06:18:50 PM PDT 24 Jun 30 06:18:53 PM PDT 24 203865553 ps
T1055 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3494376995 Jun 30 06:18:50 PM PDT 24 Jun 30 06:18:54 PM PDT 24 241175844 ps
T1056 /workspace/coverage/cover_reg_top/15.edn_intr_test.3808643873 Jun 30 06:18:38 PM PDT 24 Jun 30 06:18:39 PM PDT 24 20687433 ps
T1057 /workspace/coverage/cover_reg_top/3.edn_intr_test.3951843310 Jun 30 06:18:28 PM PDT 24 Jun 30 06:18:30 PM PDT 24 24799931 ps
T1058 /workspace/coverage/cover_reg_top/19.edn_intr_test.1600698807 Jun 30 06:18:45 PM PDT 24 Jun 30 06:18:47 PM PDT 24 22343503 ps
T1059 /workspace/coverage/cover_reg_top/47.edn_intr_test.4115619936 Jun 30 06:18:54 PM PDT 24 Jun 30 06:18:56 PM PDT 24 20328690 ps
T1060 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1144839445 Jun 30 06:18:28 PM PDT 24 Jun 30 06:18:31 PM PDT 24 109533521 ps
T1061 /workspace/coverage/cover_reg_top/46.edn_intr_test.3869556594 Jun 30 06:18:56 PM PDT 24 Jun 30 06:18:58 PM PDT 24 12925995 ps
T243 /workspace/coverage/cover_reg_top/18.edn_csr_rw.2171524727 Jun 30 06:18:46 PM PDT 24 Jun 30 06:18:49 PM PDT 24 19145306 ps
T1062 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1630554452 Jun 30 06:18:17 PM PDT 24 Jun 30 06:18:20 PM PDT 24 136477480 ps
T1063 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3509079859 Jun 30 06:18:43 PM PDT 24 Jun 30 06:18:45 PM PDT 24 165028077 ps
T1064 /workspace/coverage/cover_reg_top/6.edn_intr_test.4016716658 Jun 30 06:18:29 PM PDT 24 Jun 30 06:18:31 PM PDT 24 42756204 ps
T1065 /workspace/coverage/cover_reg_top/7.edn_intr_test.791009694 Jun 30 06:18:33 PM PDT 24 Jun 30 06:18:35 PM PDT 24 43177156 ps
T1066 /workspace/coverage/cover_reg_top/16.edn_intr_test.3713936958 Jun 30 06:18:46 PM PDT 24 Jun 30 06:18:49 PM PDT 24 26732493 ps
T1067 /workspace/coverage/cover_reg_top/22.edn_intr_test.1009594739 Jun 30 06:18:54 PM PDT 24 Jun 30 06:18:56 PM PDT 24 38005522 ps
T274 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1081231210 Jun 30 06:18:32 PM PDT 24 Jun 30 06:18:35 PM PDT 24 99523360 ps
T1068 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3414915272 Jun 30 06:18:14 PM PDT 24 Jun 30 06:18:16 PM PDT 24 128598639 ps
T1069 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1386578581 Jun 30 06:18:51 PM PDT 24 Jun 30 06:18:52 PM PDT 24 23384039 ps
T1070 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2849770245 Jun 30 06:18:32 PM PDT 24 Jun 30 06:18:35 PM PDT 24 317443280 ps
T244 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2192930838 Jun 30 06:18:35 PM PDT 24 Jun 30 06:18:36 PM PDT 24 33495080 ps
T1071 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1096986095 Jun 30 06:18:27 PM PDT 24 Jun 30 06:18:29 PM PDT 24 58053468 ps
T1072 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3476482762 Jun 30 06:18:29 PM PDT 24 Jun 30 06:18:30 PM PDT 24 43005789 ps
T1073 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3043713865 Jun 30 06:18:50 PM PDT 24 Jun 30 06:18:53 PM PDT 24 150795585 ps
T1074 /workspace/coverage/cover_reg_top/35.edn_intr_test.3734662867 Jun 30 06:18:53 PM PDT 24 Jun 30 06:18:56 PM PDT 24 18502537 ps
T245 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1248964841 Jun 30 06:18:29 PM PDT 24 Jun 30 06:18:31 PM PDT 24 61016902 ps
T1075 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2167580325 Jun 30 06:18:15 PM PDT 24 Jun 30 06:18:18 PM PDT 24 168904941 ps
T1076 /workspace/coverage/cover_reg_top/18.edn_intr_test.2452263030 Jun 30 06:18:48 PM PDT 24 Jun 30 06:18:50 PM PDT 24 14921948 ps
T246 /workspace/coverage/cover_reg_top/0.edn_csr_rw.4215071196 Jun 30 06:18:16 PM PDT 24 Jun 30 06:18:17 PM PDT 24 51190817 ps
T1077 /workspace/coverage/cover_reg_top/13.edn_intr_test.1935654136 Jun 30 06:18:39 PM PDT 24 Jun 30 06:18:40 PM PDT 24 34191788 ps
T1078 /workspace/coverage/cover_reg_top/14.edn_intr_test.3061814866 Jun 30 06:18:39 PM PDT 24 Jun 30 06:18:40 PM PDT 24 13623846 ps
T1079 /workspace/coverage/cover_reg_top/39.edn_intr_test.294343080 Jun 30 06:18:55 PM PDT 24 Jun 30 06:18:57 PM PDT 24 15650123 ps
T1080 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3740490712 Jun 30 06:18:20 PM PDT 24 Jun 30 06:18:21 PM PDT 24 21985906 ps
T1081 /workspace/coverage/cover_reg_top/12.edn_tl_errors.2524422581 Jun 30 06:18:39 PM PDT 24 Jun 30 06:18:41 PM PDT 24 142311912 ps
T1082 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3755521336 Jun 30 06:18:24 PM PDT 24 Jun 30 06:18:26 PM PDT 24 42451321 ps
T1083 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3040159210 Jun 30 06:18:28 PM PDT 24 Jun 30 06:18:32 PM PDT 24 97591714 ps
T1084 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1942088929 Jun 30 06:18:46 PM PDT 24 Jun 30 06:18:49 PM PDT 24 18913877 ps
T1085 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1620356276 Jun 30 06:18:46 PM PDT 24 Jun 30 06:18:49 PM PDT 24 41689514 ps
T1086 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.63839209 Jun 30 06:18:39 PM PDT 24 Jun 30 06:18:41 PM PDT 24 117980719 ps
T1087 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2471164605 Jun 30 06:18:20 PM PDT 24 Jun 30 06:18:21 PM PDT 24 24895026 ps
T1088 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1235297374 Jun 30 06:18:28 PM PDT 24 Jun 30 06:18:29 PM PDT 24 23952590 ps
T1089 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3543079173 Jun 30 06:18:49 PM PDT 24 Jun 30 06:18:51 PM PDT 24 17905196 ps
T1090 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1734054993 Jun 30 06:18:17 PM PDT 24 Jun 30 06:18:19 PM PDT 24 494309880 ps
T1091 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2741401741 Jun 30 06:18:48 PM PDT 24 Jun 30 06:18:51 PM PDT 24 19700466 ps
T1092 /workspace/coverage/cover_reg_top/33.edn_intr_test.1537040054 Jun 30 06:18:53 PM PDT 24 Jun 30 06:18:55 PM PDT 24 21650280 ps
T1093 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.363834632 Jun 30 06:18:33 PM PDT 24 Jun 30 06:18:34 PM PDT 24 14798420 ps
T1094 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.14368657 Jun 30 06:18:46 PM PDT 24 Jun 30 06:18:49 PM PDT 24 120242034 ps
T1095 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2493241928 Jun 30 06:18:34 PM PDT 24 Jun 30 06:18:36 PM PDT 24 48094776 ps
T276 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3041418716 Jun 30 06:18:39 PM PDT 24 Jun 30 06:18:41 PM PDT 24 112484931 ps
T1096 /workspace/coverage/cover_reg_top/17.edn_intr_test.2180534525 Jun 30 06:18:47 PM PDT 24 Jun 30 06:18:49 PM PDT 24 45988976 ps
T1097 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1345941923 Jun 30 06:18:27 PM PDT 24 Jun 30 06:18:31 PM PDT 24 51336711 ps
T248 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2761610795 Jun 30 06:18:21 PM PDT 24 Jun 30 06:18:29 PM PDT 24 1375003218 ps
T1098 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3872355763 Jun 30 06:18:46 PM PDT 24 Jun 30 06:18:51 PM PDT 24 81858998 ps
T1099 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.158253126 Jun 30 06:18:45 PM PDT 24 Jun 30 06:18:47 PM PDT 24 72719794 ps
T1100 /workspace/coverage/cover_reg_top/29.edn_intr_test.3897478009 Jun 30 06:18:56 PM PDT 24 Jun 30 06:18:58 PM PDT 24 76107451 ps
T1101 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3346256053 Jun 30 06:18:32 PM PDT 24 Jun 30 06:18:37 PM PDT 24 210822947 ps
T1102 /workspace/coverage/cover_reg_top/41.edn_intr_test.3146343620 Jun 30 06:18:57 PM PDT 24 Jun 30 06:18:59 PM PDT 24 17426324 ps
T1103 /workspace/coverage/cover_reg_top/11.edn_intr_test.1363290323 Jun 30 06:18:33 PM PDT 24 Jun 30 06:18:34 PM PDT 24 103325915 ps
T1104 /workspace/coverage/cover_reg_top/5.edn_intr_test.2267683061 Jun 30 06:18:27 PM PDT 24 Jun 30 06:18:28 PM PDT 24 240054862 ps
T1105 /workspace/coverage/cover_reg_top/43.edn_intr_test.2057806768 Jun 30 06:18:52 PM PDT 24 Jun 30 06:18:54 PM PDT 24 26867258 ps
T1106 /workspace/coverage/cover_reg_top/20.edn_intr_test.506090972 Jun 30 06:18:47 PM PDT 24 Jun 30 06:18:49 PM PDT 24 14204885 ps
T1107 /workspace/coverage/cover_reg_top/30.edn_intr_test.2282809354 Jun 30 06:18:58 PM PDT 24 Jun 30 06:18:59 PM PDT 24 44598899 ps
T1108 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2554839216 Jun 30 06:18:27 PM PDT 24 Jun 30 06:18:29 PM PDT 24 37930329 ps
T1109 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3174990627 Jun 30 06:18:45 PM PDT 24 Jun 30 06:18:48 PM PDT 24 176780425 ps
T275 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2072874134 Jun 30 06:18:28 PM PDT 24 Jun 30 06:18:31 PM PDT 24 95700421 ps
T1110 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2036274550 Jun 30 06:18:29 PM PDT 24 Jun 30 06:18:31 PM PDT 24 20110419 ps
T1111 /workspace/coverage/cover_reg_top/32.edn_intr_test.2639710394 Jun 30 06:18:54 PM PDT 24 Jun 30 06:18:56 PM PDT 24 13645443 ps
T1112 /workspace/coverage/cover_reg_top/14.edn_tl_errors.4186276972 Jun 30 06:18:40 PM PDT 24 Jun 30 06:18:42 PM PDT 24 47726720 ps
T1113 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3515077161 Jun 30 06:18:15 PM PDT 24 Jun 30 06:18:19 PM PDT 24 81959157 ps
T1114 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2435544676 Jun 30 06:18:16 PM PDT 24 Jun 30 06:18:18 PM PDT 24 25451037 ps
T1115 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2541939556 Jun 30 06:18:40 PM PDT 24 Jun 30 06:18:42 PM PDT 24 249125149 ps
T1116 /workspace/coverage/cover_reg_top/28.edn_intr_test.2518607333 Jun 30 06:18:56 PM PDT 24 Jun 30 06:18:58 PM PDT 24 11076318 ps
T1117 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1674303782 Jun 30 06:18:47 PM PDT 24 Jun 30 06:18:49 PM PDT 24 30213145 ps
T1118 /workspace/coverage/cover_reg_top/12.edn_intr_test.1639177807 Jun 30 06:18:43 PM PDT 24 Jun 30 06:18:44 PM PDT 24 42615238 ps
T1119 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3918449568 Jun 30 06:18:48 PM PDT 24 Jun 30 06:18:50 PM PDT 24 19180352 ps
T1120 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.890192032 Jun 30 06:18:16 PM PDT 24 Jun 30 06:18:18 PM PDT 24 19365417 ps
T1121 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1248174324 Jun 30 06:18:34 PM PDT 24 Jun 30 06:18:35 PM PDT 24 62919812 ps
T1122 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.857400121 Jun 30 06:18:14 PM PDT 24 Jun 30 06:18:16 PM PDT 24 115727743 ps
T1123 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1118796460 Jun 30 06:18:33 PM PDT 24 Jun 30 06:18:34 PM PDT 24 71615064 ps
T1124 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1031760406 Jun 30 06:18:38 PM PDT 24 Jun 30 06:18:40 PM PDT 24 366164015 ps
T1125 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2422416056 Jun 30 06:18:34 PM PDT 24 Jun 30 06:18:36 PM PDT 24 78268085 ps
T1126 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1468472208 Jun 30 06:18:34 PM PDT 24 Jun 30 06:18:36 PM PDT 24 49506246 ps
T249 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3028376774 Jun 30 06:18:15 PM PDT 24 Jun 30 06:18:17 PM PDT 24 15787718 ps
T1127 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1246304206 Jun 30 06:18:29 PM PDT 24 Jun 30 06:18:31 PM PDT 24 47702618 ps
T1128 /workspace/coverage/cover_reg_top/4.edn_intr_test.4138232557 Jun 30 06:18:28 PM PDT 24 Jun 30 06:18:30 PM PDT 24 17288091 ps
T1129 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3400104802 Jun 30 06:18:26 PM PDT 24 Jun 30 06:18:27 PM PDT 24 93476183 ps
T1130 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1373747869 Jun 30 06:18:40 PM PDT 24 Jun 30 06:18:41 PM PDT 24 41759009 ps

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2028871754
Short name T5
Test name
Test status
Simulation time 19060073987 ps
CPU time 443.16 seconds
Started Jun 30 05:22:31 PM PDT 24
Finished Jun 30 05:29:55 PM PDT 24
Peak memory 223964 kb
Host smart-5c6320bf-145b-4988-ab8a-d7f0688ead99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028871754 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2028871754
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.edn_genbits.1394280787
Short name T70
Test name
Test status
Simulation time 67491912 ps
CPU time 1.32 seconds
Started Jun 30 05:22:35 PM PDT 24
Finished Jun 30 05:22:36 PM PDT 24
Peak memory 219248 kb
Host smart-fb3af94a-8ff3-42fc-82b1-21aab99d1960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394280787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1394280787
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.661572057
Short name T6
Test name
Test status
Simulation time 25218646 ps
CPU time 1.24 seconds
Started Jun 30 05:24:33 PM PDT 24
Finished Jun 30 05:24:35 PM PDT 24
Peak memory 220944 kb
Host smart-5c99edaf-58b7-4407-a3a6-7644cf3bbe97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661572057 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.661572057
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1526583333
Short name T17
Test name
Test status
Simulation time 2205154712 ps
CPU time 8.3 seconds
Started Jun 30 05:21:38 PM PDT 24
Finished Jun 30 05:21:47 PM PDT 24
Peak memory 236204 kb
Host smart-96ae9428-245e-400c-b647-81b5516c6d9f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526583333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1526583333
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/145.edn_alert.657329694
Short name T28
Test name
Test status
Simulation time 93684517 ps
CPU time 1.16 seconds
Started Jun 30 05:25:23 PM PDT 24
Finished Jun 30 05:25:25 PM PDT 24
Peak memory 220988 kb
Host smart-3e80d1c3-8729-4e91-9c70-4cf349ef6495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657329694 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.657329694
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2183014376
Short name T41
Test name
Test status
Simulation time 47419632 ps
CPU time 1.04 seconds
Started Jun 30 05:21:47 PM PDT 24
Finished Jun 30 05:21:49 PM PDT 24
Peak memory 218848 kb
Host smart-da4688c6-51eb-4730-9ec6-597bf45ef098
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183014376 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2183014376
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.961669390
Short name T212
Test name
Test status
Simulation time 334228576088 ps
CPU time 2228.58 seconds
Started Jun 30 05:22:29 PM PDT 24
Finished Jun 30 05:59:38 PM PDT 24
Peak memory 227024 kb
Host smart-6320f51f-c32b-4bd4-95f7-32409be67bf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961669390 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.961669390
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.edn_genbits.1652799346
Short name T10
Test name
Test status
Simulation time 44158248 ps
CPU time 1.58 seconds
Started Jun 30 05:24:32 PM PDT 24
Finished Jun 30 05:24:34 PM PDT 24
Peak memory 220108 kb
Host smart-6c4d87b7-5c25-4517-ac48-44004b4d8d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652799346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1652799346
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_alert.3215560368
Short name T47
Test name
Test status
Simulation time 85248587 ps
CPU time 1.16 seconds
Started Jun 30 05:23:48 PM PDT 24
Finished Jun 30 05:23:50 PM PDT 24
Peak memory 220036 kb
Host smart-f381ffdc-e6d3-44c7-ba81-47f37cd0caae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215560368 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3215560368
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert.3649455981
Short name T55
Test name
Test status
Simulation time 50015546 ps
CPU time 1.25 seconds
Started Jun 30 05:23:50 PM PDT 24
Finished Jun 30 05:23:52 PM PDT 24
Peak memory 218832 kb
Host smart-40acd712-3a56-411d-ab43-b4a8dc06e387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649455981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3649455981
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert.635487922
Short name T45
Test name
Test status
Simulation time 50503711 ps
CPU time 1.18 seconds
Started Jun 30 05:23:11 PM PDT 24
Finished Jun 30 05:23:14 PM PDT 24
Peak memory 221120 kb
Host smart-b818ee33-3e7e-45fc-9cc6-d64ad66e26e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635487922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.635487922
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/5.edn_regwen.2759583671
Short name T527
Test name
Test status
Simulation time 75529990 ps
CPU time 0.89 seconds
Started Jun 30 05:22:07 PM PDT 24
Finished Jun 30 05:22:08 PM PDT 24
Peak memory 207348 kb
Host smart-29d61197-2de7-4e52-acd5-aafb4a3253aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759583671 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2759583671
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/177.edn_alert.2604526797
Short name T267
Test name
Test status
Simulation time 131112990 ps
CPU time 1.24 seconds
Started Jun 30 05:25:39 PM PDT 24
Finished Jun 30 05:25:41 PM PDT 24
Peak memory 218884 kb
Host smart-3a6f7d82-ed53-4ae2-ae97-74be34048de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604526797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.2604526797
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/35.edn_disable.4029617315
Short name T73
Test name
Test status
Simulation time 24508766 ps
CPU time 0.92 seconds
Started Jun 30 05:23:52 PM PDT 24
Finished Jun 30 05:23:53 PM PDT 24
Peak memory 216688 kb
Host smart-5ebd60d2-e773-462d-bc55-8f21dfe98fb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029617315 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.4029617315
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1081231210
Short name T274
Test name
Test status
Simulation time 99523360 ps
CPU time 2.67 seconds
Started Jun 30 06:18:32 PM PDT 24
Finished Jun 30 06:18:35 PM PDT 24
Peak memory 215128 kb
Host smart-e5dfe1f6-9cd9-4629-bcc0-9f051f088801
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081231210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1081231210
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.4271926747
Short name T20
Test name
Test status
Simulation time 34643670 ps
CPU time 1.28 seconds
Started Jun 30 05:23:12 PM PDT 24
Finished Jun 30 05:23:15 PM PDT 24
Peak memory 217404 kb
Host smart-6ea50969-30d4-4d8c-9938-7a21768e334c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271926747 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.4271926747
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_disable.3556888766
Short name T202
Test name
Test status
Simulation time 14011475 ps
CPU time 0.89 seconds
Started Jun 30 05:22:30 PM PDT 24
Finished Jun 30 05:22:32 PM PDT 24
Peak memory 216540 kb
Host smart-96578748-26c3-42e6-8fb7-67bf3a9c3121
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556888766 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3556888766
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable.883728462
Short name T78
Test name
Test status
Simulation time 40911107 ps
CPU time 0.85 seconds
Started Jun 30 05:21:46 PM PDT 24
Finished Jun 30 05:21:48 PM PDT 24
Peak memory 216620 kb
Host smart-f921e3d0-ffef-483e-bfdb-5c70b501cd30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883728462 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.883728462
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable.1827237060
Short name T188
Test name
Test status
Simulation time 35591267 ps
CPU time 0.84 seconds
Started Jun 30 05:23:11 PM PDT 24
Finished Jun 30 05:23:13 PM PDT 24
Peak memory 216536 kb
Host smart-7e4e4b73-b3b3-4154-ad0d-1537bcb9be91
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827237060 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1827237060
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1372415065
Short name T136
Test name
Test status
Simulation time 49151986 ps
CPU time 1.07 seconds
Started Jun 30 05:23:21 PM PDT 24
Finished Jun 30 05:23:23 PM PDT 24
Peak memory 217084 kb
Host smart-9779bfde-a33c-49d5-acbf-d4fb08de5d02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372415065 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1372415065
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3281276434
Short name T242
Test name
Test status
Simulation time 17767937 ps
CPU time 0.99 seconds
Started Jun 30 06:18:47 PM PDT 24
Finished Jun 30 06:18:49 PM PDT 24
Peak memory 206940 kb
Host smart-a3c98094-d320-474b-8e92-f322b0de5ebf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281276434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3281276434
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/default/78.edn_alert.1244099762
Short name T49
Test name
Test status
Simulation time 76564388 ps
CPU time 1.16 seconds
Started Jun 30 05:24:39 PM PDT 24
Finished Jun 30 05:24:42 PM PDT 24
Peak memory 220716 kb
Host smart-44559abc-477b-424b-92e8-8269a60c6e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244099762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.1244099762
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/109.edn_alert.495573118
Short name T139
Test name
Test status
Simulation time 268287696 ps
CPU time 1.42 seconds
Started Jun 30 05:25:06 PM PDT 24
Finished Jun 30 05:25:07 PM PDT 24
Peak memory 220032 kb
Host smart-02f48fdf-b226-430b-88d0-cdae511f1d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495573118 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.495573118
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3603613955
Short name T86
Test name
Test status
Simulation time 163253459411 ps
CPU time 977.76 seconds
Started Jun 30 05:21:59 PM PDT 24
Finished Jun 30 05:38:17 PM PDT 24
Peak memory 222432 kb
Host smart-fc29a369-c381-48c1-bf29-90703d311881
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603613955 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3603613955
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.1855707530
Short name T281
Test name
Test status
Simulation time 92834745 ps
CPU time 1.23 seconds
Started Jun 30 05:25:24 PM PDT 24
Finished Jun 30 05:25:26 PM PDT 24
Peak memory 220172 kb
Host smart-562f6e01-715a-4398-b7a3-47e3bb123af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855707530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.1855707530
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/112.edn_alert.2771599680
Short name T97
Test name
Test status
Simulation time 85165598 ps
CPU time 1.14 seconds
Started Jun 30 05:25:07 PM PDT 24
Finished Jun 30 05:25:08 PM PDT 24
Peak memory 219952 kb
Host smart-9689c80f-cf89-4aca-8d21-b95c0d89495c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771599680 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.2771599680
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/108.edn_alert.1548622053
Short name T800
Test name
Test status
Simulation time 406988792 ps
CPU time 1.36 seconds
Started Jun 30 05:25:08 PM PDT 24
Finished Jun 30 05:25:10 PM PDT 24
Peak memory 220360 kb
Host smart-deadf7cb-4416-4a89-8bef-e5cad72cb288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548622053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.1548622053
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert.2253071255
Short name T117
Test name
Test status
Simulation time 43998068 ps
CPU time 1.28 seconds
Started Jun 30 05:23:06 PM PDT 24
Finished Jun 30 05:23:09 PM PDT 24
Peak memory 219844 kb
Host smart-c61803b6-6158-4eb9-9ec9-05e773c8df9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253071255 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2253071255
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert.447564451
Short name T127
Test name
Test status
Simulation time 82244574 ps
CPU time 1.11 seconds
Started Jun 30 05:23:11 PM PDT 24
Finished Jun 30 05:23:13 PM PDT 24
Peak memory 220768 kb
Host smart-ba3bba1d-722f-4a2a-9975-5db6ac3f4436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447564451 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.447564451
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.3261548813
Short name T58
Test name
Test status
Simulation time 36526662 ps
CPU time 0.98 seconds
Started Jun 30 05:24:46 PM PDT 24
Finished Jun 30 05:24:47 PM PDT 24
Peak memory 224112 kb
Host smart-56f14b28-d3f8-414d-a694-8f4b864f4ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261548813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3261548813
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/25.edn_intr.2468598524
Short name T29
Test name
Test status
Simulation time 21157704 ps
CPU time 1.05 seconds
Started Jun 30 05:23:11 PM PDT 24
Finished Jun 30 05:23:13 PM PDT 24
Peak memory 216204 kb
Host smart-a8bbc566-3bb3-4969-9861-20015a6db503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468598524 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2468598524
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/149.edn_genbits.2514671068
Short name T80
Test name
Test status
Simulation time 47029136 ps
CPU time 1.87 seconds
Started Jun 30 05:25:25 PM PDT 24
Finished Jun 30 05:25:28 PM PDT 24
Peak memory 220184 kb
Host smart-831854f9-7669-48c3-b0dc-d95de6cd6175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514671068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2514671068
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_disable.1742434350
Short name T193
Test name
Test status
Simulation time 19796818 ps
CPU time 0.88 seconds
Started Jun 30 05:22:50 PM PDT 24
Finished Jun 30 05:22:51 PM PDT 24
Peak memory 216644 kb
Host smart-1e077a8b-c55c-4f42-960a-493f134cc652
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742434350 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1742434350
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable.2166466501
Short name T196
Test name
Test status
Simulation time 24929441 ps
CPU time 0.85 seconds
Started Jun 30 05:23:07 PM PDT 24
Finished Jun 30 05:23:09 PM PDT 24
Peak memory 216564 kb
Host smart-c5d48dee-41cc-444f-8c87-33fdc65f1ffc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166466501 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2166466501
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/18.edn_intr.1170287309
Short name T34
Test name
Test status
Simulation time 26122867 ps
CPU time 0.86 seconds
Started Jun 30 05:22:49 PM PDT 24
Finished Jun 30 05:22:50 PM PDT 24
Peak memory 215844 kb
Host smart-d4fea054-0357-453c-adb6-a8f6a0e8e18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170287309 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1170287309
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3096200843
Short name T115
Test name
Test status
Simulation time 45717434 ps
CPU time 1.81 seconds
Started Jun 30 05:21:39 PM PDT 24
Finished Jun 30 05:21:41 PM PDT 24
Peak memory 217220 kb
Host smart-a296a9ff-75a0-4ab9-8f1d-be4092be6b8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096200843 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3096200843
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_disable.3972422517
Short name T557
Test name
Test status
Simulation time 10705415 ps
CPU time 0.86 seconds
Started Jun 30 05:21:46 PM PDT 24
Finished Jun 30 05:21:48 PM PDT 24
Peak memory 216572 kb
Host smart-a6179d22-806c-4ba0-8caf-9c29bb3dc37c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972422517 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3972422517
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/100.edn_alert.3906650632
Short name T896
Test name
Test status
Simulation time 233604185 ps
CPU time 1.04 seconds
Started Jun 30 05:25:00 PM PDT 24
Finished Jun 30 05:25:02 PM PDT 24
Peak memory 220076 kb
Host smart-a1bff7a7-44dd-49c2-aaa4-4b41f5497c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906650632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.3906650632
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/113.edn_alert.1443927549
Short name T403
Test name
Test status
Simulation time 95031288 ps
CPU time 1.24 seconds
Started Jun 30 05:25:09 PM PDT 24
Finished Jun 30 05:25:11 PM PDT 24
Peak memory 219768 kb
Host smart-ded374df-cbc0-4e62-892b-e9519c6f220d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443927549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.1443927549
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/123.edn_alert.2359716061
Short name T122
Test name
Test status
Simulation time 54399282 ps
CPU time 1.36 seconds
Started Jun 30 05:25:08 PM PDT 24
Finished Jun 30 05:25:10 PM PDT 24
Peak memory 220420 kb
Host smart-862583f6-74ae-49df-8ccb-f6e1d441418d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359716061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.2359716061
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/158.edn_alert.745986014
Short name T170
Test name
Test status
Simulation time 29618775 ps
CPU time 1.21 seconds
Started Jun 30 05:25:32 PM PDT 24
Finished Jun 30 05:25:35 PM PDT 24
Peak memory 219980 kb
Host smart-1228f546-5ddc-4e32-95bf-4e02f6cf00ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745986014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.745986014
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.785851023
Short name T718
Test name
Test status
Simulation time 66383823 ps
CPU time 1.3 seconds
Started Jun 30 05:22:50 PM PDT 24
Finished Jun 30 05:22:52 PM PDT 24
Peak memory 217220 kb
Host smart-febf2d9c-6203-4e77-a629-8a5606f748d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785851023 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.785851023
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3738424746
Short name T68
Test name
Test status
Simulation time 19138783 ps
CPU time 1.06 seconds
Started Jun 30 05:23:07 PM PDT 24
Finished Jun 30 05:23:10 PM PDT 24
Peak memory 218668 kb
Host smart-546f14bb-bcef-4ad2-9c3a-5eff43905fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738424746 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3738424746
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1364098681
Short name T125
Test name
Test status
Simulation time 22839797 ps
CPU time 1.08 seconds
Started Jun 30 05:23:06 PM PDT 24
Finished Jun 30 05:23:08 PM PDT 24
Peak memory 217104 kb
Host smart-4e4af59e-e7b2-4246-a3f7-eaf214d77cf3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364098681 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1364098681
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1250822599
Short name T709
Test name
Test status
Simulation time 31815939 ps
CPU time 1.02 seconds
Started Jun 30 05:24:20 PM PDT 24
Finished Jun 30 05:24:21 PM PDT 24
Peak memory 229648 kb
Host smart-b6c2557f-b0e8-41cd-817c-c8f17acc5bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250822599 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1250822599
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/72.edn_err.3831413546
Short name T180
Test name
Test status
Simulation time 81158647 ps
CPU time 0.98 seconds
Started Jun 30 05:24:38 PM PDT 24
Finished Jun 30 05:24:39 PM PDT 24
Peak memory 224088 kb
Host smart-49978467-2b46-4bab-9940-5ace2a4efd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831413546 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3831413546
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/132.edn_genbits.3314266044
Short name T71
Test name
Test status
Simulation time 49491516 ps
CPU time 1.17 seconds
Started Jun 30 05:25:12 PM PDT 24
Finished Jun 30 05:25:14 PM PDT 24
Peak memory 217532 kb
Host smart-a540c84d-ff1b-4216-abf0-178eb8128200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314266044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3314266044
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2926514131
Short name T258
Test name
Test status
Simulation time 120889349 ps
CPU time 2.96 seconds
Started Jun 30 05:25:59 PM PDT 24
Finished Jun 30 05:26:05 PM PDT 24
Peak memory 220460 kb
Host smart-a8c79de5-45f9-4399-87b0-80b74db2838f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926514131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2926514131
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.102699947
Short name T87
Test name
Test status
Simulation time 11936613503 ps
CPU time 281.34 seconds
Started Jun 30 05:23:35 PM PDT 24
Finished Jun 30 05:28:17 PM PDT 24
Peak memory 218060 kb
Host smart-4690e701-ce0e-4ac2-b645-ecd5b5f9e0d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102699947 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.102699947
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_alert_test.830623347
Short name T65
Test name
Test status
Simulation time 14647715 ps
CPU time 0.87 seconds
Started Jun 30 05:22:31 PM PDT 24
Finished Jun 30 05:22:33 PM PDT 24
Peak memory 215176 kb
Host smart-aa462b30-6d94-4301-9288-031a1234d4ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830623347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.830623347
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/230.edn_genbits.797078499
Short name T755
Test name
Test status
Simulation time 69668176 ps
CPU time 1.69 seconds
Started Jun 30 05:25:53 PM PDT 24
Finished Jun 30 05:25:56 PM PDT 24
Peak memory 220556 kb
Host smart-cd3d9749-5a21-44f1-a9d0-fe4b7a909f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797078499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.797078499
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.845837719
Short name T288
Test name
Test status
Simulation time 72493018 ps
CPU time 1.24 seconds
Started Jun 30 05:25:12 PM PDT 24
Finished Jun 30 05:25:13 PM PDT 24
Peak memory 220456 kb
Host smart-44b4b088-b187-418f-9330-04ab7eb02a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845837719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.845837719
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.3980543896
Short name T296
Test name
Test status
Simulation time 82626392 ps
CPU time 1.45 seconds
Started Jun 30 05:25:23 PM PDT 24
Finished Jun 30 05:25:26 PM PDT 24
Peak memory 219248 kb
Host smart-aa85ecad-60ce-46a8-bf3a-2ce0d3527135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980543896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3980543896
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3863403800
Short name T84
Test name
Test status
Simulation time 35014474 ps
CPU time 0.87 seconds
Started Jun 30 05:22:56 PM PDT 24
Finished Jun 30 05:22:57 PM PDT 24
Peak memory 216000 kb
Host smart-2a43a75e-27d3-4bb7-81c2-1295c8ac144c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863403800 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3863403800
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2481404825
Short name T247
Test name
Test status
Simulation time 18867196 ps
CPU time 0.94 seconds
Started Jun 30 06:18:19 PM PDT 24
Finished Jun 30 06:18:21 PM PDT 24
Peak memory 206880 kb
Host smart-686a0b54-f727-455e-bd53-1bc4b8a6491f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481404825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2481404825
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.964357194
Short name T273
Test name
Test status
Simulation time 122006784 ps
CPU time 2.84 seconds
Started Jun 30 06:18:40 PM PDT 24
Finished Jun 30 06:18:44 PM PDT 24
Peak memory 207144 kb
Host smart-9bae5520-cf3d-4e2e-857a-7081bce850e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964357194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.964357194
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/default/101.edn_genbits.4018961721
Short name T836
Test name
Test status
Simulation time 74533076 ps
CPU time 1.41 seconds
Started Jun 30 05:25:01 PM PDT 24
Finished Jun 30 05:25:03 PM PDT 24
Peak memory 219972 kb
Host smart-5ecca304-0192-4e3d-b9c4-3246cf27bddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018961721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.4018961721
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.2310881581
Short name T300
Test name
Test status
Simulation time 29819846 ps
CPU time 1.37 seconds
Started Jun 30 05:25:07 PM PDT 24
Finished Jun 30 05:25:09 PM PDT 24
Peak memory 220220 kb
Host smart-066c1997-16f0-406f-9a7d-56038e153bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310881581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2310881581
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.698501076
Short name T549
Test name
Test status
Simulation time 26764930 ps
CPU time 1.24 seconds
Started Jun 30 05:25:14 PM PDT 24
Finished Jun 30 05:25:16 PM PDT 24
Peak memory 221084 kb
Host smart-6f01cedd-c0de-4293-a5ab-773c988ada41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698501076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.698501076
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.3663965899
Short name T723
Test name
Test status
Simulation time 68531130 ps
CPU time 2.52 seconds
Started Jun 30 05:25:14 PM PDT 24
Finished Jun 30 05:25:17 PM PDT 24
Peak memory 220596 kb
Host smart-5b418dd0-8977-48fb-a32c-2509b4764ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663965899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3663965899
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_stress_all.3954110914
Short name T867
Test name
Test status
Simulation time 514680975 ps
CPU time 5.26 seconds
Started Jun 30 05:22:35 PM PDT 24
Finished Jun 30 05:22:41 PM PDT 24
Peak memory 220668 kb
Host smart-bd375f16-a9a0-47b2-8b81-fa01fa96743c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954110914 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3954110914
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/140.edn_genbits.2859504661
Short name T293
Test name
Test status
Simulation time 57660817 ps
CPU time 1.46 seconds
Started Jun 30 05:25:22 PM PDT 24
Finished Jun 30 05:25:24 PM PDT 24
Peak memory 218924 kb
Host smart-180cbb11-95c6-41b7-a59b-b70fca3ea799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859504661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2859504661
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.3356037344
Short name T290
Test name
Test status
Simulation time 118914995 ps
CPU time 1.44 seconds
Started Jun 30 05:25:32 PM PDT 24
Finished Jun 30 05:25:34 PM PDT 24
Peak memory 217784 kb
Host smart-cde189ce-adea-46e3-b3bc-d90bdb4658a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356037344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3356037344
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.1669876906
Short name T311
Test name
Test status
Simulation time 40683191 ps
CPU time 1.48 seconds
Started Jun 30 05:25:33 PM PDT 24
Finished Jun 30 05:25:35 PM PDT 24
Peak memory 217656 kb
Host smart-ec90b5d5-7ca1-4479-b3b5-8ef5ce98513c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669876906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1669876906
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.3117432181
Short name T302
Test name
Test status
Simulation time 61383257 ps
CPU time 1.36 seconds
Started Jun 30 05:25:39 PM PDT 24
Finished Jun 30 05:25:40 PM PDT 24
Peak memory 218820 kb
Host smart-6127665d-5a47-4363-b5cc-f17eec9ab683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117432181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3117432181
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_genbits.37118081
Short name T306
Test name
Test status
Simulation time 54539974 ps
CPU time 1.32 seconds
Started Jun 30 05:23:32 PM PDT 24
Finished Jun 30 05:23:34 PM PDT 24
Peak memory 218936 kb
Host smart-a3e956d9-6b43-4ea3-8022-d2786ab7d870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37118081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.37118081
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.3204623611
Short name T30
Test name
Test status
Simulation time 20284575 ps
CPU time 1.05 seconds
Started Jun 30 05:23:19 PM PDT 24
Finished Jun 30 05:23:20 PM PDT 24
Peak memory 216340 kb
Host smart-f1bc676a-d7a1-4e01-8c33-6354b33425af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204623611 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3204623611
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/11.edn_alert.9753425
Short name T208
Test name
Test status
Simulation time 21826909 ps
CPU time 1.17 seconds
Started Jun 30 05:22:29 PM PDT 24
Finished Jun 30 05:22:30 PM PDT 24
Peak memory 219184 kb
Host smart-fbc7aeba-c646-4ce6-a198-5b640bd2b532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9753425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.9753425
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/138.edn_alert.4294622138
Short name T102
Test name
Test status
Simulation time 84135161 ps
CPU time 1.14 seconds
Started Jun 30 05:25:25 PM PDT 24
Finished Jun 30 05:25:27 PM PDT 24
Peak memory 220640 kb
Host smart-a1f99d17-5f43-40ff-b5a3-30ee14e66cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294622138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.4294622138
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/153.edn_alert.1698880617
Short name T96
Test name
Test status
Simulation time 28352797 ps
CPU time 1.3 seconds
Started Jun 30 05:25:23 PM PDT 24
Finished Jun 30 05:25:25 PM PDT 24
Peak memory 220612 kb
Host smart-64bc4c81-e3af-4aa5-9f54-0610a141bccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698880617 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1698880617
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.2071282964
Short name T553
Test name
Test status
Simulation time 71101073 ps
CPU time 1.75 seconds
Started Jun 30 05:24:59 PM PDT 24
Finished Jun 30 05:25:01 PM PDT 24
Peak memory 220516 kb
Host smart-7ca6ff4a-6054-4fef-9f5f-34fd791cdfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071282964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2071282964
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.2240327098
Short name T329
Test name
Test status
Simulation time 65157506 ps
CPU time 1.2 seconds
Started Jun 30 05:24:59 PM PDT 24
Finished Jun 30 05:25:01 PM PDT 24
Peak memory 217624 kb
Host smart-3f886aae-6b21-496b-b917-8871262bfdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240327098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2240327098
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.3059786007
Short name T543
Test name
Test status
Simulation time 33331206 ps
CPU time 1.42 seconds
Started Jun 30 05:25:32 PM PDT 24
Finished Jun 30 05:25:34 PM PDT 24
Peak memory 219984 kb
Host smart-ab04d824-c662-4bea-8b5d-6d9e9236bb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059786007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3059786007
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.857400121
Short name T1122
Test name
Test status
Simulation time 115727743 ps
CPU time 1.41 seconds
Started Jun 30 06:18:14 PM PDT 24
Finished Jun 30 06:18:16 PM PDT 24
Peak memory 206976 kb
Host smart-a04f8f59-e8f9-44d7-bec3-85378ae51a20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857400121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.857400121
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.830204320
Short name T1006
Test name
Test status
Simulation time 91633599 ps
CPU time 2.96 seconds
Started Jun 30 06:18:17 PM PDT 24
Finished Jun 30 06:18:20 PM PDT 24
Peak memory 206864 kb
Host smart-9b1aba0c-7674-4c90-8941-387f1c453c52
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830204320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.830204320
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3028376774
Short name T249
Test name
Test status
Simulation time 15787718 ps
CPU time 0.91 seconds
Started Jun 30 06:18:15 PM PDT 24
Finished Jun 30 06:18:17 PM PDT 24
Peak memory 206920 kb
Host smart-e828eb55-8406-4621-8527-b849c010ae07
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028376774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3028376774
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2435544676
Short name T1114
Test name
Test status
Simulation time 25451037 ps
CPU time 1.29 seconds
Started Jun 30 06:18:16 PM PDT 24
Finished Jun 30 06:18:18 PM PDT 24
Peak memory 217804 kb
Host smart-57493d8c-dd36-41ad-974e-ab7727d31f9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435544676 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2435544676
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.4215071196
Short name T246
Test name
Test status
Simulation time 51190817 ps
CPU time 0.83 seconds
Started Jun 30 06:18:16 PM PDT 24
Finished Jun 30 06:18:17 PM PDT 24
Peak memory 206924 kb
Host smart-4da73712-dd2c-4eb5-a931-cf97128641f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215071196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.4215071196
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2531348074
Short name T1028
Test name
Test status
Simulation time 69477220 ps
CPU time 0.83 seconds
Started Jun 30 06:18:14 PM PDT 24
Finished Jun 30 06:18:15 PM PDT 24
Peak memory 206720 kb
Host smart-0fce27fb-2d33-4e34-8742-ff25d04ea126
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531348074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2531348074
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.890192032
Short name T1120
Test name
Test status
Simulation time 19365417 ps
CPU time 1.13 seconds
Started Jun 30 06:18:16 PM PDT 24
Finished Jun 30 06:18:18 PM PDT 24
Peak memory 206932 kb
Host smart-d0cd730a-ffd2-452d-9dc6-59304783cc9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890192032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.890192032
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1630554452
Short name T1062
Test name
Test status
Simulation time 136477480 ps
CPU time 1.97 seconds
Started Jun 30 06:18:17 PM PDT 24
Finished Jun 30 06:18:20 PM PDT 24
Peak memory 215180 kb
Host smart-3ea0a54e-272a-4f40-9cb3-3e1b15e352e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630554452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1630554452
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2167580325
Short name T1075
Test name
Test status
Simulation time 168904941 ps
CPU time 1.64 seconds
Started Jun 30 06:18:15 PM PDT 24
Finished Jun 30 06:18:18 PM PDT 24
Peak memory 207032 kb
Host smart-d599bfe4-b85a-456c-9453-3c54cd850b4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167580325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2167580325
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3740490712
Short name T1080
Test name
Test status
Simulation time 21985906 ps
CPU time 0.99 seconds
Started Jun 30 06:18:20 PM PDT 24
Finished Jun 30 06:18:21 PM PDT 24
Peak memory 207008 kb
Host smart-0151a07f-f002-419e-a5b4-2f1c3566bae5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740490712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3740490712
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.484666775
Short name T1018
Test name
Test status
Simulation time 179312454 ps
CPU time 5.32 seconds
Started Jun 30 06:18:29 PM PDT 24
Finished Jun 30 06:18:35 PM PDT 24
Peak memory 207000 kb
Host smart-ef3eaccc-b1dc-4b59-b621-7fdbeaa9ae9c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484666775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.484666775
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3414915272
Short name T1068
Test name
Test status
Simulation time 128598639 ps
CPU time 0.95 seconds
Started Jun 30 06:18:14 PM PDT 24
Finished Jun 30 06:18:16 PM PDT 24
Peak memory 206940 kb
Host smart-1275e170-168a-4238-868b-2357447fd18b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414915272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3414915272
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2608634218
Short name T1046
Test name
Test status
Simulation time 150010142 ps
CPU time 1.58 seconds
Started Jun 30 06:18:21 PM PDT 24
Finished Jun 30 06:18:23 PM PDT 24
Peak memory 215244 kb
Host smart-55fa0e0b-3d60-4f76-980b-350f2eb816b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608634218 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2608634218
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1209740642
Short name T1049
Test name
Test status
Simulation time 39098360 ps
CPU time 0.81 seconds
Started Jun 30 06:18:17 PM PDT 24
Finished Jun 30 06:18:18 PM PDT 24
Peak memory 206676 kb
Host smart-a2be3dce-ce4c-4afb-8a08-1ccd310251bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209740642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1209740642
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1719865113
Short name T256
Test name
Test status
Simulation time 246568475 ps
CPU time 1.08 seconds
Started Jun 30 06:18:21 PM PDT 24
Finished Jun 30 06:18:22 PM PDT 24
Peak memory 207100 kb
Host smart-93925b9c-7b19-4eb9-a9c2-63bc16628f37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719865113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1719865113
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3515077161
Short name T1113
Test name
Test status
Simulation time 81959157 ps
CPU time 2.78 seconds
Started Jun 30 06:18:15 PM PDT 24
Finished Jun 30 06:18:19 PM PDT 24
Peak memory 215224 kb
Host smart-d323c5ab-d718-42d7-ae4e-8800c186fa74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515077161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3515077161
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1734054993
Short name T1090
Test name
Test status
Simulation time 494309880 ps
CPU time 2.03 seconds
Started Jun 30 06:18:17 PM PDT 24
Finished Jun 30 06:18:19 PM PDT 24
Peak memory 206988 kb
Host smart-a171b615-c26a-49f8-8354-668643b010d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734054993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1734054993
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1616433921
Short name T1033
Test name
Test status
Simulation time 80155531 ps
CPU time 1.58 seconds
Started Jun 30 06:18:32 PM PDT 24
Finished Jun 30 06:18:34 PM PDT 24
Peak memory 215184 kb
Host smart-5034207a-20db-4ba1-a9d2-9a396f3decd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616433921 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1616433921
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2192930838
Short name T244
Test name
Test status
Simulation time 33495080 ps
CPU time 0.92 seconds
Started Jun 30 06:18:35 PM PDT 24
Finished Jun 30 06:18:36 PM PDT 24
Peak memory 206920 kb
Host smart-a550fc2c-d369-49a1-ab68-48a74cc1e7e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192930838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2192930838
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2142116693
Short name T1010
Test name
Test status
Simulation time 12128493 ps
CPU time 0.91 seconds
Started Jun 30 06:18:33 PM PDT 24
Finished Jun 30 06:18:35 PM PDT 24
Peak memory 206852 kb
Host smart-5fa15b18-73eb-4a32-8278-944e97fd5054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142116693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2142116693
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.4035450296
Short name T254
Test name
Test status
Simulation time 22050133 ps
CPU time 1.12 seconds
Started Jun 30 06:18:32 PM PDT 24
Finished Jun 30 06:18:34 PM PDT 24
Peak memory 207012 kb
Host smart-42cb25b7-b685-427f-a377-71e4d8ce3574
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035450296 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.4035450296
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1421158
Short name T1031
Test name
Test status
Simulation time 50165982 ps
CPU time 1.93 seconds
Started Jun 30 06:18:35 PM PDT 24
Finished Jun 30 06:18:38 PM PDT 24
Peak memory 214508 kb
Host smart-0212e438-9cba-4bcc-9acd-707905c22e63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1421158
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1022701044
Short name T264
Test name
Test status
Simulation time 87330709 ps
CPU time 1.61 seconds
Started Jun 30 06:18:34 PM PDT 24
Finished Jun 30 06:18:36 PM PDT 24
Peak memory 215084 kb
Host smart-37d94eae-e391-4e2f-8e9a-c621ffbc5550
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022701044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1022701044
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1775910594
Short name T1026
Test name
Test status
Simulation time 63567506 ps
CPU time 1.14 seconds
Started Jun 30 06:18:39 PM PDT 24
Finished Jun 30 06:18:40 PM PDT 24
Peak memory 215208 kb
Host smart-6506c751-52cc-4a8a-95ce-83f0cd7e99c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775910594 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1775910594
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.206580129
Short name T239
Test name
Test status
Simulation time 55625165 ps
CPU time 0.87 seconds
Started Jun 30 06:18:32 PM PDT 24
Finished Jun 30 06:18:33 PM PDT 24
Peak memory 206880 kb
Host smart-5c5290d4-9707-4e4e-b2b9-eb5c25ebe724
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206580129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.206580129
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1363290323
Short name T1103
Test name
Test status
Simulation time 103325915 ps
CPU time 0.82 seconds
Started Jun 30 06:18:33 PM PDT 24
Finished Jun 30 06:18:34 PM PDT 24
Peak memory 206740 kb
Host smart-29d32049-a20d-4e8a-a026-ec6627393249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363290323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1363290323
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2149393955
Short name T250
Test name
Test status
Simulation time 59959767 ps
CPU time 1.16 seconds
Started Jun 30 06:18:40 PM PDT 24
Finished Jun 30 06:18:42 PM PDT 24
Peak memory 206976 kb
Host smart-a67c8e0e-667c-4d94-babb-35b7eec07cab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149393955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2149393955
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1288326896
Short name T1003
Test name
Test status
Simulation time 130096033 ps
CPU time 2.47 seconds
Started Jun 30 06:18:32 PM PDT 24
Finished Jun 30 06:18:35 PM PDT 24
Peak memory 215104 kb
Host smart-89d488d0-39d9-4ad0-8ffe-86aab65da08f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288326896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1288326896
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2056093912
Short name T1051
Test name
Test status
Simulation time 193029743 ps
CPU time 2.53 seconds
Started Jun 30 06:18:32 PM PDT 24
Finished Jun 30 06:18:35 PM PDT 24
Peak memory 206996 kb
Host smart-5bebb356-6c78-42f6-aa6c-3da4a7a75356
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056093912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2056093912
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.63839209
Short name T1086
Test name
Test status
Simulation time 117980719 ps
CPU time 1.39 seconds
Started Jun 30 06:18:39 PM PDT 24
Finished Jun 30 06:18:41 PM PDT 24
Peak memory 217800 kb
Host smart-bbe00879-e89e-44ae-ac28-7456991478d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63839209 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.63839209
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1373747869
Short name T1130
Test name
Test status
Simulation time 41759009 ps
CPU time 0.85 seconds
Started Jun 30 06:18:40 PM PDT 24
Finished Jun 30 06:18:41 PM PDT 24
Peak memory 206708 kb
Host smart-b2b17e27-aad0-48dd-a98f-d18513414dec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373747869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1373747869
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1639177807
Short name T1118
Test name
Test status
Simulation time 42615238 ps
CPU time 0.88 seconds
Started Jun 30 06:18:43 PM PDT 24
Finished Jun 30 06:18:44 PM PDT 24
Peak memory 206892 kb
Host smart-e4a04bcf-dd32-494b-afb4-5f519e9bd4f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639177807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1639177807
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3839424567
Short name T251
Test name
Test status
Simulation time 70643611 ps
CPU time 1.26 seconds
Started Jun 30 06:18:41 PM PDT 24
Finished Jun 30 06:18:43 PM PDT 24
Peak memory 207032 kb
Host smart-5836c4e3-5713-4cac-981c-f56cfda37ef1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839424567 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3839424567
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2524422581
Short name T1081
Test name
Test status
Simulation time 142311912 ps
CPU time 2.06 seconds
Started Jun 30 06:18:39 PM PDT 24
Finished Jun 30 06:18:41 PM PDT 24
Peak memory 215100 kb
Host smart-92acca36-4ba9-430e-8ce2-ed67ecb3c470
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524422581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2524422581
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1281912979
Short name T1041
Test name
Test status
Simulation time 94993218 ps
CPU time 1.72 seconds
Started Jun 30 06:18:41 PM PDT 24
Finished Jun 30 06:18:44 PM PDT 24
Peak memory 206928 kb
Host smart-3c835eac-75fe-467e-a851-29843237dbbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281912979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1281912979
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1226743151
Short name T1045
Test name
Test status
Simulation time 36302252 ps
CPU time 1.31 seconds
Started Jun 30 06:18:42 PM PDT 24
Finished Jun 30 06:18:44 PM PDT 24
Peak memory 215284 kb
Host smart-3f649d7b-5411-4dbb-8d4f-f0b43caa179f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226743151 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1226743151
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.4029600084
Short name T255
Test name
Test status
Simulation time 18528139 ps
CPU time 0.86 seconds
Started Jun 30 06:18:39 PM PDT 24
Finished Jun 30 06:18:40 PM PDT 24
Peak memory 206864 kb
Host smart-542fcbd2-810a-4b40-b0af-7a9e6fb83b41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029600084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.4029600084
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1935654136
Short name T1077
Test name
Test status
Simulation time 34191788 ps
CPU time 0.82 seconds
Started Jun 30 06:18:39 PM PDT 24
Finished Jun 30 06:18:40 PM PDT 24
Peak memory 206900 kb
Host smart-a8621e7f-5952-48f9-a022-9fee7697eab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935654136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1935654136
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.313141480
Short name T1042
Test name
Test status
Simulation time 39974393 ps
CPU time 0.96 seconds
Started Jun 30 06:18:40 PM PDT 24
Finished Jun 30 06:18:42 PM PDT 24
Peak memory 206996 kb
Host smart-fedbf521-8e17-464c-a69b-9107288a2a50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313141480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.313141480
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1559546812
Short name T1014
Test name
Test status
Simulation time 136183582 ps
CPU time 1.9 seconds
Started Jun 30 06:18:39 PM PDT 24
Finished Jun 30 06:18:42 PM PDT 24
Peak memory 219000 kb
Host smart-a9ffe342-0f20-49c2-aa7e-1a41b53eb59d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559546812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1559546812
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2524705955
Short name T998
Test name
Test status
Simulation time 61448899 ps
CPU time 1.08 seconds
Started Jun 30 06:18:43 PM PDT 24
Finished Jun 30 06:18:44 PM PDT 24
Peak memory 215352 kb
Host smart-0846e0cd-5e4a-461b-b1d7-030b35b0c392
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524705955 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2524705955
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3509079859
Short name T1063
Test name
Test status
Simulation time 165028077 ps
CPU time 0.85 seconds
Started Jun 30 06:18:43 PM PDT 24
Finished Jun 30 06:18:45 PM PDT 24
Peak memory 206780 kb
Host smart-8ead38a5-b821-4430-a24b-3ef9e910f815
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509079859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3509079859
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3061814866
Short name T1078
Test name
Test status
Simulation time 13623846 ps
CPU time 0.88 seconds
Started Jun 30 06:18:39 PM PDT 24
Finished Jun 30 06:18:40 PM PDT 24
Peak memory 206856 kb
Host smart-6ae11701-bb49-4217-83aa-50bda5950da4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061814866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3061814866
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3865702454
Short name T236
Test name
Test status
Simulation time 18906070 ps
CPU time 1.24 seconds
Started Jun 30 06:18:41 PM PDT 24
Finished Jun 30 06:18:43 PM PDT 24
Peak memory 207028 kb
Host smart-b6a9cbe6-447b-48ae-ad7f-bb078d3ad57e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865702454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3865702454
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.4186276972
Short name T1112
Test name
Test status
Simulation time 47726720 ps
CPU time 1.8 seconds
Started Jun 30 06:18:40 PM PDT 24
Finished Jun 30 06:18:42 PM PDT 24
Peak memory 215156 kb
Host smart-df2f3681-088f-4a82-a4df-a8352fbef1ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186276972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.4186276972
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2541939556
Short name T1115
Test name
Test status
Simulation time 249125149 ps
CPU time 1.47 seconds
Started Jun 30 06:18:40 PM PDT 24
Finished Jun 30 06:18:42 PM PDT 24
Peak memory 207020 kb
Host smart-c4bb617f-e712-4c64-8756-376c8f421cf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541939556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2541939556
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1942088929
Short name T1084
Test name
Test status
Simulation time 18913877 ps
CPU time 1.1 seconds
Started Jun 30 06:18:46 PM PDT 24
Finished Jun 30 06:18:49 PM PDT 24
Peak memory 215164 kb
Host smart-54253546-c9c7-4490-87f7-3b723105e0b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942088929 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1942088929
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1285224523
Short name T1002
Test name
Test status
Simulation time 13385450 ps
CPU time 0.94 seconds
Started Jun 30 06:18:48 PM PDT 24
Finished Jun 30 06:18:50 PM PDT 24
Peak memory 206600 kb
Host smart-f9535fef-09e5-4a67-926d-5cf4e63f2ac9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285224523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1285224523
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3808643873
Short name T1056
Test name
Test status
Simulation time 20687433 ps
CPU time 0.86 seconds
Started Jun 30 06:18:38 PM PDT 24
Finished Jun 30 06:18:39 PM PDT 24
Peak memory 206836 kb
Host smart-0573d7f2-c426-4327-ab0a-1cd17ef3c93e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808643873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3808643873
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.158253126
Short name T1099
Test name
Test status
Simulation time 72719794 ps
CPU time 1.09 seconds
Started Jun 30 06:18:45 PM PDT 24
Finished Jun 30 06:18:47 PM PDT 24
Peak memory 206944 kb
Host smart-82cc2c38-e24d-4167-8f7d-c82595959b4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158253126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.158253126
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1031760406
Short name T1124
Test name
Test status
Simulation time 366164015 ps
CPU time 1.84 seconds
Started Jun 30 06:18:38 PM PDT 24
Finished Jun 30 06:18:40 PM PDT 24
Peak memory 215440 kb
Host smart-6f517ca0-1a43-4ca7-806a-5117d47492a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031760406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1031760406
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3041418716
Short name T276
Test name
Test status
Simulation time 112484931 ps
CPU time 1.61 seconds
Started Jun 30 06:18:39 PM PDT 24
Finished Jun 30 06:18:41 PM PDT 24
Peak memory 206896 kb
Host smart-8a118f6a-b6e0-4ad1-8548-9f5623189526
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041418716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3041418716
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.754304556
Short name T1034
Test name
Test status
Simulation time 22092347 ps
CPU time 1.18 seconds
Started Jun 30 06:18:46 PM PDT 24
Finished Jun 30 06:18:48 PM PDT 24
Peak memory 216988 kb
Host smart-3d710f3d-7b30-42cb-97dd-983a23032d6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754304556 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.754304556
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3167123018
Short name T1005
Test name
Test status
Simulation time 38528427 ps
CPU time 0.8 seconds
Started Jun 30 06:18:46 PM PDT 24
Finished Jun 30 06:18:49 PM PDT 24
Peak memory 206752 kb
Host smart-def33ac3-1f85-4565-b7a2-74aa0d55f341
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167123018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3167123018
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3713936958
Short name T1066
Test name
Test status
Simulation time 26732493 ps
CPU time 0.92 seconds
Started Jun 30 06:18:46 PM PDT 24
Finished Jun 30 06:18:49 PM PDT 24
Peak memory 206840 kb
Host smart-7c974b8f-7af7-46b9-bb0c-e0ff0768e7f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713936958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3713936958
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1620356276
Short name T1085
Test name
Test status
Simulation time 41689514 ps
CPU time 1.64 seconds
Started Jun 30 06:18:46 PM PDT 24
Finished Jun 30 06:18:49 PM PDT 24
Peak memory 206916 kb
Host smart-12190536-a8d3-4331-a7c3-b5bbce1c90c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620356276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1620356276
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3077933062
Short name T1047
Test name
Test status
Simulation time 207437136 ps
CPU time 3.96 seconds
Started Jun 30 06:18:49 PM PDT 24
Finished Jun 30 06:18:54 PM PDT 24
Peak memory 215276 kb
Host smart-5d04a162-f8e2-4a02-bee4-7a46a957af58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077933062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3077933062
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3174990627
Short name T1109
Test name
Test status
Simulation time 176780425 ps
CPU time 1.64 seconds
Started Jun 30 06:18:45 PM PDT 24
Finished Jun 30 06:18:48 PM PDT 24
Peak memory 206952 kb
Host smart-a9843837-d920-47de-8105-2fc49808a05f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174990627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3174990627
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1674303782
Short name T1117
Test name
Test status
Simulation time 30213145 ps
CPU time 1.24 seconds
Started Jun 30 06:18:47 PM PDT 24
Finished Jun 30 06:18:49 PM PDT 24
Peak memory 215312 kb
Host smart-eea9bf3b-40ec-4bd3-bab2-bb1238fe7ca2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674303782 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1674303782
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2180534525
Short name T1096
Test name
Test status
Simulation time 45988976 ps
CPU time 0.92 seconds
Started Jun 30 06:18:47 PM PDT 24
Finished Jun 30 06:18:49 PM PDT 24
Peak memory 206880 kb
Host smart-a54975f9-5b83-45a1-81d7-bb90d4dd4806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180534525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2180534525
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3543079173
Short name T1089
Test name
Test status
Simulation time 17905196 ps
CPU time 1.21 seconds
Started Jun 30 06:18:49 PM PDT 24
Finished Jun 30 06:18:51 PM PDT 24
Peak memory 207004 kb
Host smart-abee5ca3-4529-42dd-8bae-2c48cd8a696b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543079173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3543079173
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2741401741
Short name T1091
Test name
Test status
Simulation time 19700466 ps
CPU time 1.45 seconds
Started Jun 30 06:18:48 PM PDT 24
Finished Jun 30 06:18:51 PM PDT 24
Peak memory 218320 kb
Host smart-612ceb96-cb4f-489d-bef3-1bbff514c6de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741401741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2741401741
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.297053679
Short name T1054
Test name
Test status
Simulation time 203865553 ps
CPU time 2.12 seconds
Started Jun 30 06:18:50 PM PDT 24
Finished Jun 30 06:18:53 PM PDT 24
Peak memory 207024 kb
Host smart-c214673d-7592-4f39-8707-e92b078ff8b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297053679 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.297053679
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.769063783
Short name T997
Test name
Test status
Simulation time 13948363 ps
CPU time 1 seconds
Started Jun 30 06:18:48 PM PDT 24
Finished Jun 30 06:18:50 PM PDT 24
Peak memory 206988 kb
Host smart-c445929f-4dfb-4bfe-930b-1709583bfef2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769063783 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.769063783
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2171524727
Short name T243
Test name
Test status
Simulation time 19145306 ps
CPU time 0.87 seconds
Started Jun 30 06:18:46 PM PDT 24
Finished Jun 30 06:18:49 PM PDT 24
Peak memory 206728 kb
Host smart-c0b36201-0ee4-48b3-adf9-7c7e6cdaf40e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171524727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2171524727
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2452263030
Short name T1076
Test name
Test status
Simulation time 14921948 ps
CPU time 0.92 seconds
Started Jun 30 06:18:48 PM PDT 24
Finished Jun 30 06:18:50 PM PDT 24
Peak memory 206396 kb
Host smart-826b6945-7433-41c9-8353-fe4c28d5ebb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452263030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2452263030
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1386578581
Short name T1069
Test name
Test status
Simulation time 23384039 ps
CPU time 0.98 seconds
Started Jun 30 06:18:51 PM PDT 24
Finished Jun 30 06:18:52 PM PDT 24
Peak memory 206988 kb
Host smart-833a5537-7146-4f3e-aaa0-3c0746eeba45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386578581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1386578581
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3872355763
Short name T1098
Test name
Test status
Simulation time 81858998 ps
CPU time 3.07 seconds
Started Jun 30 06:18:46 PM PDT 24
Finished Jun 30 06:18:51 PM PDT 24
Peak memory 215284 kb
Host smart-80d34bbd-c147-4292-8ddd-61c42dbd3276
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872355763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3872355763
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3494376995
Short name T1055
Test name
Test status
Simulation time 241175844 ps
CPU time 2.95 seconds
Started Jun 30 06:18:50 PM PDT 24
Finished Jun 30 06:18:54 PM PDT 24
Peak memory 207096 kb
Host smart-95408d37-53b0-48b3-8987-da3ed13ccc4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494376995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3494376995
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1021540549
Short name T1039
Test name
Test status
Simulation time 114152368 ps
CPU time 2.19 seconds
Started Jun 30 06:18:46 PM PDT 24
Finished Jun 30 06:18:49 PM PDT 24
Peak memory 215244 kb
Host smart-5c83f2f1-296d-43ae-a404-f7894b5ff6b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021540549 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1021540549
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2596752512
Short name T237
Test name
Test status
Simulation time 28767958 ps
CPU time 0.86 seconds
Started Jun 30 06:18:47 PM PDT 24
Finished Jun 30 06:18:49 PM PDT 24
Peak memory 206732 kb
Host smart-a6bf6fa1-7601-4e3e-896a-836bc2958d88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596752512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2596752512
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1600698807
Short name T1058
Test name
Test status
Simulation time 22343503 ps
CPU time 0.82 seconds
Started Jun 30 06:18:45 PM PDT 24
Finished Jun 30 06:18:47 PM PDT 24
Peak memory 206852 kb
Host smart-fc8dce42-6d72-4653-beea-74e1b60849cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600698807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1600698807
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3918449568
Short name T1119
Test name
Test status
Simulation time 19180352 ps
CPU time 1.15 seconds
Started Jun 30 06:18:48 PM PDT 24
Finished Jun 30 06:18:50 PM PDT 24
Peak memory 206912 kb
Host smart-1304cf32-1214-4f76-9674-301c1abe615e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918449568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3918449568
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3043713865
Short name T1073
Test name
Test status
Simulation time 150795585 ps
CPU time 2.39 seconds
Started Jun 30 06:18:50 PM PDT 24
Finished Jun 30 06:18:53 PM PDT 24
Peak memory 215248 kb
Host smart-7d71fa1a-a191-4a91-b05a-d9657c57dfe6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043713865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3043713865
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.14368657
Short name T1094
Test name
Test status
Simulation time 120242034 ps
CPU time 2.88 seconds
Started Jun 30 06:18:46 PM PDT 24
Finished Jun 30 06:18:49 PM PDT 24
Peak memory 206920 kb
Host smart-891775c3-a9fa-4fe0-8258-6ab112135f7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14368657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.14368657
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.778457071
Short name T238
Test name
Test status
Simulation time 34847502 ps
CPU time 1.28 seconds
Started Jun 30 06:18:20 PM PDT 24
Finished Jun 30 06:18:21 PM PDT 24
Peak memory 206916 kb
Host smart-d98c0633-d0b9-40a9-9e57-11797d5b38f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778457071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.778457071
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3040159210
Short name T1083
Test name
Test status
Simulation time 97591714 ps
CPU time 3.15 seconds
Started Jun 30 06:18:28 PM PDT 24
Finished Jun 30 06:18:32 PM PDT 24
Peak memory 206972 kb
Host smart-24f08de9-4e16-4a72-977b-873e07a61a3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040159210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3040159210
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.417755402
Short name T241
Test name
Test status
Simulation time 57335778 ps
CPU time 0.99 seconds
Started Jun 30 06:18:20 PM PDT 24
Finished Jun 30 06:18:21 PM PDT 24
Peak memory 206936 kb
Host smart-1d084b87-1874-4075-9049-02b78ee82e65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417755402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.417755402
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.285063622
Short name T1021
Test name
Test status
Simulation time 22813264 ps
CPU time 1.16 seconds
Started Jun 30 06:18:29 PM PDT 24
Finished Jun 30 06:18:31 PM PDT 24
Peak memory 215220 kb
Host smart-4f9582ea-06d6-426a-90e4-783f2b04ea00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285063622 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.285063622
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3476482762
Short name T1072
Test name
Test status
Simulation time 43005789 ps
CPU time 0.87 seconds
Started Jun 30 06:18:29 PM PDT 24
Finished Jun 30 06:18:30 PM PDT 24
Peak memory 206784 kb
Host smart-f2cc6f23-b04c-4f10-93a8-37363163cfab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476482762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3476482762
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3185655871
Short name T1038
Test name
Test status
Simulation time 32763149 ps
CPU time 0.85 seconds
Started Jun 30 06:18:21 PM PDT 24
Finished Jun 30 06:18:23 PM PDT 24
Peak memory 206672 kb
Host smart-99757e61-e027-4fa9-a30c-fe70508dc5a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185655871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3185655871
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2597038113
Short name T1048
Test name
Test status
Simulation time 24460120 ps
CPU time 1.12 seconds
Started Jun 30 06:18:20 PM PDT 24
Finished Jun 30 06:18:22 PM PDT 24
Peak memory 206916 kb
Host smart-bfe36c49-7af4-4c5a-97c5-0b78798fe5a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597038113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2597038113
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1985862587
Short name T1020
Test name
Test status
Simulation time 107062706 ps
CPU time 2.86 seconds
Started Jun 30 06:18:24 PM PDT 24
Finished Jun 30 06:18:27 PM PDT 24
Peak memory 215192 kb
Host smart-60098b99-95b1-4db9-92f2-95d204f60679
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985862587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1985862587
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3755521336
Short name T1082
Test name
Test status
Simulation time 42451321 ps
CPU time 1.62 seconds
Started Jun 30 06:18:24 PM PDT 24
Finished Jun 30 06:18:26 PM PDT 24
Peak memory 207008 kb
Host smart-d7f2a362-dcec-4535-a8a8-e677bbc87231
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755521336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3755521336
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.506090972
Short name T1106
Test name
Test status
Simulation time 14204885 ps
CPU time 0.9 seconds
Started Jun 30 06:18:47 PM PDT 24
Finished Jun 30 06:18:49 PM PDT 24
Peak memory 206864 kb
Host smart-aba38e94-d34f-4793-8765-6602f144ddd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506090972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.506090972
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1066504370
Short name T999
Test name
Test status
Simulation time 12584644 ps
CPU time 0.89 seconds
Started Jun 30 06:18:56 PM PDT 24
Finished Jun 30 06:18:58 PM PDT 24
Peak memory 206868 kb
Host smart-44de26bd-fa22-4737-b801-8143b43b7657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066504370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1066504370
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1009594739
Short name T1067
Test name
Test status
Simulation time 38005522 ps
CPU time 0.82 seconds
Started Jun 30 06:18:54 PM PDT 24
Finished Jun 30 06:18:56 PM PDT 24
Peak memory 206632 kb
Host smart-40097706-8a6f-46fe-8df0-1e3eec6d1c01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009594739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1009594739
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3035249913
Short name T1015
Test name
Test status
Simulation time 11799780 ps
CPU time 0.85 seconds
Started Jun 30 06:18:54 PM PDT 24
Finished Jun 30 06:18:56 PM PDT 24
Peak memory 207080 kb
Host smart-7325a1d5-f4e4-40ca-a90a-e7faf91dbe9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035249913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3035249913
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1278982611
Short name T1053
Test name
Test status
Simulation time 47658508 ps
CPU time 0.87 seconds
Started Jun 30 06:18:53 PM PDT 24
Finished Jun 30 06:18:55 PM PDT 24
Peak memory 206848 kb
Host smart-abd239eb-596f-4cdc-b1b0-d110eff4bdab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278982611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1278982611
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.74446113
Short name T1030
Test name
Test status
Simulation time 58400010 ps
CPU time 0.93 seconds
Started Jun 30 06:18:53 PM PDT 24
Finished Jun 30 06:18:56 PM PDT 24
Peak memory 206904 kb
Host smart-9533c3b1-e2aa-4de5-9ddb-cfdcccdc18d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74446113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.74446113
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1414085391
Short name T1008
Test name
Test status
Simulation time 41411390 ps
CPU time 0.86 seconds
Started Jun 30 06:18:54 PM PDT 24
Finished Jun 30 06:18:57 PM PDT 24
Peak memory 206868 kb
Host smart-906c71c8-b85f-422a-a4ce-ba9c4b3d6127
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414085391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1414085391
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.935778082
Short name T1052
Test name
Test status
Simulation time 15417980 ps
CPU time 0.9 seconds
Started Jun 30 06:18:54 PM PDT 24
Finished Jun 30 06:18:56 PM PDT 24
Peak memory 206844 kb
Host smart-0584b2b5-4761-4c35-8e77-8d6730c538aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935778082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.935778082
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2518607333
Short name T1116
Test name
Test status
Simulation time 11076318 ps
CPU time 0.86 seconds
Started Jun 30 06:18:56 PM PDT 24
Finished Jun 30 06:18:58 PM PDT 24
Peak memory 206900 kb
Host smart-109aac7d-e16e-4577-91d3-79b0bf6f7876
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518607333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2518607333
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3897478009
Short name T1100
Test name
Test status
Simulation time 76107451 ps
CPU time 0.77 seconds
Started Jun 30 06:18:56 PM PDT 24
Finished Jun 30 06:18:58 PM PDT 24
Peak memory 206552 kb
Host smart-89afaa6d-dc0b-4331-8d1e-4ee12ee211b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897478009 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3897478009
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1468472208
Short name T1126
Test name
Test status
Simulation time 49506246 ps
CPU time 1.16 seconds
Started Jun 30 06:18:34 PM PDT 24
Finished Jun 30 06:18:36 PM PDT 24
Peak memory 206936 kb
Host smart-c2ea79cc-af8a-4718-819e-dbe022cb2781
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468472208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1468472208
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2761610795
Short name T248
Test name
Test status
Simulation time 1375003218 ps
CPU time 6.84 seconds
Started Jun 30 06:18:21 PM PDT 24
Finished Jun 30 06:18:29 PM PDT 24
Peak memory 206956 kb
Host smart-90556645-886f-4323-ba6e-c204e64e04a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761610795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2761610795
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2381092952
Short name T1027
Test name
Test status
Simulation time 16579593 ps
CPU time 0.97 seconds
Started Jun 30 06:18:30 PM PDT 24
Finished Jun 30 06:18:31 PM PDT 24
Peak memory 206912 kb
Host smart-bad3b4b5-efc8-437f-9a80-acb1a955623d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381092952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2381092952
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3400104802
Short name T1129
Test name
Test status
Simulation time 93476183 ps
CPU time 1.11 seconds
Started Jun 30 06:18:26 PM PDT 24
Finished Jun 30 06:18:27 PM PDT 24
Peak memory 215188 kb
Host smart-2938115b-f8b1-4f45-b329-d9337dded0c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400104802 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3400104802
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2471164605
Short name T1087
Test name
Test status
Simulation time 24895026 ps
CPU time 0.86 seconds
Started Jun 30 06:18:20 PM PDT 24
Finished Jun 30 06:18:21 PM PDT 24
Peak memory 206920 kb
Host smart-143f67f7-b5cd-42d3-b4ab-a215991fcddb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471164605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2471164605
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3951843310
Short name T1057
Test name
Test status
Simulation time 24799931 ps
CPU time 0.82 seconds
Started Jun 30 06:18:28 PM PDT 24
Finished Jun 30 06:18:30 PM PDT 24
Peak memory 206900 kb
Host smart-ed1cd50d-32cf-46c7-adb5-99ab1d31e6f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951843310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3951843310
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2036274550
Short name T1110
Test name
Test status
Simulation time 20110419 ps
CPU time 1.18 seconds
Started Jun 30 06:18:29 PM PDT 24
Finished Jun 30 06:18:31 PM PDT 24
Peak memory 206972 kb
Host smart-47522023-672f-49f6-92f4-7b3279ecc706
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036274550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2036274550
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1472504938
Short name T1016
Test name
Test status
Simulation time 699374603 ps
CPU time 4.47 seconds
Started Jun 30 06:18:28 PM PDT 24
Finished Jun 30 06:18:32 PM PDT 24
Peak memory 215284 kb
Host smart-81c65bcb-4ebc-4aca-a57f-bcf099a08f62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472504938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1472504938
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.386230768
Short name T265
Test name
Test status
Simulation time 169602961 ps
CPU time 1.65 seconds
Started Jun 30 06:18:29 PM PDT 24
Finished Jun 30 06:18:32 PM PDT 24
Peak memory 206936 kb
Host smart-dcb92d19-8f80-4d8b-a790-ec364a923cbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386230768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.386230768
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2282809354
Short name T1107
Test name
Test status
Simulation time 44598899 ps
CPU time 0.83 seconds
Started Jun 30 06:18:58 PM PDT 24
Finished Jun 30 06:18:59 PM PDT 24
Peak memory 206688 kb
Host smart-10b7ee64-342f-428c-808a-5c31af611a4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282809354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2282809354
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3851810244
Short name T1013
Test name
Test status
Simulation time 20390638 ps
CPU time 0.82 seconds
Started Jun 30 06:18:53 PM PDT 24
Finished Jun 30 06:18:55 PM PDT 24
Peak memory 206884 kb
Host smart-67b9b817-43de-44fa-bd28-e77fd9730bab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851810244 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3851810244
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2639710394
Short name T1111
Test name
Test status
Simulation time 13645443 ps
CPU time 0.87 seconds
Started Jun 30 06:18:54 PM PDT 24
Finished Jun 30 06:18:56 PM PDT 24
Peak memory 206804 kb
Host smart-34388fbc-9841-44ef-984e-38b97b7e0399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639710394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2639710394
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1537040054
Short name T1092
Test name
Test status
Simulation time 21650280 ps
CPU time 0.83 seconds
Started Jun 30 06:18:53 PM PDT 24
Finished Jun 30 06:18:55 PM PDT 24
Peak memory 206896 kb
Host smart-ce47fed7-ced2-4d18-9351-5f7623f77a1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537040054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1537040054
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3837710165
Short name T1022
Test name
Test status
Simulation time 15816971 ps
CPU time 0.79 seconds
Started Jun 30 06:18:53 PM PDT 24
Finished Jun 30 06:18:55 PM PDT 24
Peak memory 206600 kb
Host smart-f9c23392-f72d-4658-89cc-a8589f965b93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837710165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3837710165
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3734662867
Short name T1074
Test name
Test status
Simulation time 18502537 ps
CPU time 0.82 seconds
Started Jun 30 06:18:53 PM PDT 24
Finished Jun 30 06:18:56 PM PDT 24
Peak memory 206692 kb
Host smart-6bff2ffc-70f8-4aed-9ccf-87734388ce06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734662867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3734662867
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1396687910
Short name T1023
Test name
Test status
Simulation time 24450285 ps
CPU time 0.86 seconds
Started Jun 30 06:18:57 PM PDT 24
Finished Jun 30 06:18:59 PM PDT 24
Peak memory 206888 kb
Host smart-b776c1d3-1bb9-4833-8861-e46b76ec91cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396687910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1396687910
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.352793994
Short name T1029
Test name
Test status
Simulation time 30188790 ps
CPU time 0.79 seconds
Started Jun 30 06:18:53 PM PDT 24
Finished Jun 30 06:18:56 PM PDT 24
Peak memory 206720 kb
Host smart-37ac43f3-198f-40fc-9e92-65c722c3299b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352793994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.352793994
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.4099963858
Short name T1011
Test name
Test status
Simulation time 40913720 ps
CPU time 0.84 seconds
Started Jun 30 06:18:56 PM PDT 24
Finished Jun 30 06:18:58 PM PDT 24
Peak memory 207044 kb
Host smart-fcb3d973-2ff4-4067-bcf5-03c0d527ba5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099963858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.4099963858
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.294343080
Short name T1079
Test name
Test status
Simulation time 15650123 ps
CPU time 0.93 seconds
Started Jun 30 06:18:55 PM PDT 24
Finished Jun 30 06:18:57 PM PDT 24
Peak memory 206844 kb
Host smart-f419208b-e622-4b73-b9fe-8b2d0be49efd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294343080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.294343080
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1248964841
Short name T245
Test name
Test status
Simulation time 61016902 ps
CPU time 1.43 seconds
Started Jun 30 06:18:29 PM PDT 24
Finished Jun 30 06:18:31 PM PDT 24
Peak memory 206920 kb
Host smart-ea0728eb-1364-412d-be22-145576ea4c14
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248964841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1248964841
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3848997846
Short name T1019
Test name
Test status
Simulation time 877854218 ps
CPU time 3.84 seconds
Started Jun 30 06:18:27 PM PDT 24
Finished Jun 30 06:18:31 PM PDT 24
Peak memory 206968 kb
Host smart-5057a691-0b61-43bc-8d9c-a50af25012e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848997846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3848997846
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1246304206
Short name T1127
Test name
Test status
Simulation time 47702618 ps
CPU time 0.97 seconds
Started Jun 30 06:18:29 PM PDT 24
Finished Jun 30 06:18:31 PM PDT 24
Peak memory 206932 kb
Host smart-765e714d-d89c-439c-a570-91027098d29a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246304206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1246304206
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2654452809
Short name T1009
Test name
Test status
Simulation time 55609518 ps
CPU time 1.91 seconds
Started Jun 30 06:18:34 PM PDT 24
Finished Jun 30 06:18:37 PM PDT 24
Peak memory 215232 kb
Host smart-44ef7245-de0a-4543-a888-4ec0a1eb7226
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654452809 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2654452809
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1042465845
Short name T1004
Test name
Test status
Simulation time 13715852 ps
CPU time 0.94 seconds
Started Jun 30 06:18:29 PM PDT 24
Finished Jun 30 06:18:31 PM PDT 24
Peak memory 206900 kb
Host smart-75e07a57-866f-452c-a575-ccd710929f12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042465845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1042465845
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.4138232557
Short name T1128
Test name
Test status
Simulation time 17288091 ps
CPU time 0.95 seconds
Started Jun 30 06:18:28 PM PDT 24
Finished Jun 30 06:18:30 PM PDT 24
Peak memory 206880 kb
Host smart-1bb8e576-6948-4917-a8e5-e17d34c7471e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138232557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.4138232557
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1096986095
Short name T1071
Test name
Test status
Simulation time 58053468 ps
CPU time 1.31 seconds
Started Jun 30 06:18:27 PM PDT 24
Finished Jun 30 06:18:29 PM PDT 24
Peak memory 206920 kb
Host smart-09f284c1-32f6-4c17-a305-97cb5ef85c55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096986095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1096986095
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1345941923
Short name T1097
Test name
Test status
Simulation time 51336711 ps
CPU time 2.85 seconds
Started Jun 30 06:18:27 PM PDT 24
Finished Jun 30 06:18:31 PM PDT 24
Peak memory 215260 kb
Host smart-21d4b061-ca59-4d23-a46b-6c4924cbca15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345941923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1345941923
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2072874134
Short name T275
Test name
Test status
Simulation time 95700421 ps
CPU time 2.55 seconds
Started Jun 30 06:18:28 PM PDT 24
Finished Jun 30 06:18:31 PM PDT 24
Peak memory 207000 kb
Host smart-e788babd-90f1-4b95-97ee-e2e6742c5474
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072874134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2072874134
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1897281009
Short name T1032
Test name
Test status
Simulation time 19455114 ps
CPU time 0.8 seconds
Started Jun 30 06:18:56 PM PDT 24
Finished Jun 30 06:18:58 PM PDT 24
Peak memory 206700 kb
Host smart-70f2432b-7317-4684-b122-5eb01e4b7f0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897281009 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1897281009
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3146343620
Short name T1102
Test name
Test status
Simulation time 17426324 ps
CPU time 0.81 seconds
Started Jun 30 06:18:57 PM PDT 24
Finished Jun 30 06:18:59 PM PDT 24
Peak memory 206804 kb
Host smart-20d30b0a-2320-448e-a68d-dc8fd6e2aea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146343620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3146343620
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2479177528
Short name T1007
Test name
Test status
Simulation time 13352627 ps
CPU time 0.87 seconds
Started Jun 30 06:18:55 PM PDT 24
Finished Jun 30 06:18:57 PM PDT 24
Peak memory 206912 kb
Host smart-216b8488-a4b8-4f59-aa9a-1c9bc069f109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479177528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2479177528
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2057806768
Short name T1105
Test name
Test status
Simulation time 26867258 ps
CPU time 0.89 seconds
Started Jun 30 06:18:52 PM PDT 24
Finished Jun 30 06:18:54 PM PDT 24
Peak memory 206872 kb
Host smart-4a3557da-3ad7-4db5-82cf-e86b8f0157b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057806768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2057806768
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2662714360
Short name T1037
Test name
Test status
Simulation time 38551599 ps
CPU time 0.84 seconds
Started Jun 30 06:18:53 PM PDT 24
Finished Jun 30 06:18:55 PM PDT 24
Peak memory 206688 kb
Host smart-0848bcab-57da-4d27-ae84-f489117888d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662714360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2662714360
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.432111716
Short name T1024
Test name
Test status
Simulation time 51102319 ps
CPU time 0.83 seconds
Started Jun 30 06:18:51 PM PDT 24
Finished Jun 30 06:18:53 PM PDT 24
Peak memory 206916 kb
Host smart-c61906b3-d76c-4c0c-9a1f-ee4ec60bdee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432111716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.432111716
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3869556594
Short name T1061
Test name
Test status
Simulation time 12925995 ps
CPU time 0.85 seconds
Started Jun 30 06:18:56 PM PDT 24
Finished Jun 30 06:18:58 PM PDT 24
Peak memory 206780 kb
Host smart-2415b978-64dc-4ea6-8f90-f6b68d666fdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869556594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3869556594
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.4115619936
Short name T1059
Test name
Test status
Simulation time 20328690 ps
CPU time 0.84 seconds
Started Jun 30 06:18:54 PM PDT 24
Finished Jun 30 06:18:56 PM PDT 24
Peak memory 206660 kb
Host smart-7a184b85-375f-43cd-acce-6f7b0773153e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115619936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.4115619936
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.653443811
Short name T1017
Test name
Test status
Simulation time 46688516 ps
CPU time 0.89 seconds
Started Jun 30 06:18:53 PM PDT 24
Finished Jun 30 06:18:56 PM PDT 24
Peak memory 206896 kb
Host smart-fcba6d45-3e2f-49fa-8a4d-52591c2665e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653443811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.653443811
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.477168341
Short name T1035
Test name
Test status
Simulation time 14960583 ps
CPU time 0.95 seconds
Started Jun 30 06:18:56 PM PDT 24
Finished Jun 30 06:18:58 PM PDT 24
Peak memory 206888 kb
Host smart-850daa43-ad1a-496f-a428-678861819566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477168341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.477168341
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3267219712
Short name T995
Test name
Test status
Simulation time 19421853 ps
CPU time 1.05 seconds
Started Jun 30 06:18:26 PM PDT 24
Finished Jun 30 06:18:27 PM PDT 24
Peak memory 216476 kb
Host smart-2a776a43-bdb0-493d-978a-8e24b3620be2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267219712 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3267219712
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1235297374
Short name T1088
Test name
Test status
Simulation time 23952590 ps
CPU time 0.88 seconds
Started Jun 30 06:18:28 PM PDT 24
Finished Jun 30 06:18:29 PM PDT 24
Peak memory 206960 kb
Host smart-96fabd59-fb28-4dc4-a90e-b4a56190451a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235297374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1235297374
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2267683061
Short name T1104
Test name
Test status
Simulation time 240054862 ps
CPU time 0.97 seconds
Started Jun 30 06:18:27 PM PDT 24
Finished Jun 30 06:18:28 PM PDT 24
Peak memory 206856 kb
Host smart-323b0699-89a7-49d7-b7dc-04471a670c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267683061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2267683061
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2554839216
Short name T1108
Test name
Test status
Simulation time 37930329 ps
CPU time 1.12 seconds
Started Jun 30 06:18:27 PM PDT 24
Finished Jun 30 06:18:29 PM PDT 24
Peak memory 206952 kb
Host smart-755f0721-84de-440f-a5ea-ac66c4753613
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554839216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2554839216
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3064953634
Short name T1050
Test name
Test status
Simulation time 22080204 ps
CPU time 1.58 seconds
Started Jun 30 06:18:30 PM PDT 24
Finished Jun 30 06:18:32 PM PDT 24
Peak memory 215272 kb
Host smart-889982b6-1a32-4164-8bd7-04b273152e9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064953634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3064953634
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3260174880
Short name T266
Test name
Test status
Simulation time 72497921 ps
CPU time 2.4 seconds
Started Jun 30 06:18:29 PM PDT 24
Finished Jun 30 06:18:32 PM PDT 24
Peak memory 215144 kb
Host smart-75e81567-0df2-4d0b-aa79-ead5c5aa9263
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260174880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3260174880
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.922290815
Short name T1036
Test name
Test status
Simulation time 225050579 ps
CPU time 1.87 seconds
Started Jun 30 06:18:31 PM PDT 24
Finished Jun 30 06:18:33 PM PDT 24
Peak memory 215324 kb
Host smart-14c5ed9b-3c5f-449e-9a99-1ae0080608ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922290815 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.922290815
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1269845482
Short name T1044
Test name
Test status
Simulation time 144056157 ps
CPU time 0.85 seconds
Started Jun 30 06:18:29 PM PDT 24
Finished Jun 30 06:18:30 PM PDT 24
Peak memory 206704 kb
Host smart-16e6960e-6cd1-45ad-b28c-e80ab656f00a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269845482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1269845482
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.4016716658
Short name T1064
Test name
Test status
Simulation time 42756204 ps
CPU time 0.82 seconds
Started Jun 30 06:18:29 PM PDT 24
Finished Jun 30 06:18:31 PM PDT 24
Peak memory 206876 kb
Host smart-b4a41c2c-0c3b-4b62-a5b6-19cc73b7efd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016716658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.4016716658
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2700397739
Short name T252
Test name
Test status
Simulation time 32800858 ps
CPU time 1.11 seconds
Started Jun 30 06:18:26 PM PDT 24
Finished Jun 30 06:18:28 PM PDT 24
Peak memory 206884 kb
Host smart-68ab830b-cc08-4c3e-be56-412406097f70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700397739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2700397739
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.37772593
Short name T1040
Test name
Test status
Simulation time 589068236 ps
CPU time 5.39 seconds
Started Jun 30 06:18:29 PM PDT 24
Finished Jun 30 06:18:35 PM PDT 24
Peak memory 223368 kb
Host smart-caee9257-acbb-4f78-aee9-821fcf3b44a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37772593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.37772593
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1144839445
Short name T1060
Test name
Test status
Simulation time 109533521 ps
CPU time 2.86 seconds
Started Jun 30 06:18:28 PM PDT 24
Finished Jun 30 06:18:31 PM PDT 24
Peak memory 207144 kb
Host smart-83d24117-5323-43f2-b1a0-f0b02d70b9ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144839445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1144839445
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1080197207
Short name T1000
Test name
Test status
Simulation time 23095687 ps
CPU time 1.5 seconds
Started Jun 30 06:18:33 PM PDT 24
Finished Jun 30 06:18:35 PM PDT 24
Peak memory 215180 kb
Host smart-ddda00f6-21ea-4137-ae9d-1d320c750aee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080197207 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1080197207
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.43442785
Short name T240
Test name
Test status
Simulation time 15299915 ps
CPU time 0.94 seconds
Started Jun 30 06:18:35 PM PDT 24
Finished Jun 30 06:18:37 PM PDT 24
Peak memory 206912 kb
Host smart-858536fc-bd8a-4955-9710-a3919544cf07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43442785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.43442785
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.791009694
Short name T1065
Test name
Test status
Simulation time 43177156 ps
CPU time 0.89 seconds
Started Jun 30 06:18:33 PM PDT 24
Finished Jun 30 06:18:35 PM PDT 24
Peak memory 206860 kb
Host smart-0b68d8a2-9570-4da1-a6c4-053172e15cd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791009694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.791009694
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2493241928
Short name T1095
Test name
Test status
Simulation time 48094776 ps
CPU time 1.12 seconds
Started Jun 30 06:18:34 PM PDT 24
Finished Jun 30 06:18:36 PM PDT 24
Peak memory 206924 kb
Host smart-6489d4cb-972d-4d3d-a29f-aec3975cf0c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493241928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2493241928
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2232542752
Short name T1025
Test name
Test status
Simulation time 121080473 ps
CPU time 2.27 seconds
Started Jun 30 06:18:29 PM PDT 24
Finished Jun 30 06:18:31 PM PDT 24
Peak memory 215184 kb
Host smart-6b983c01-d242-4e16-be32-d59cba86784e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232542752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2232542752
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2799138189
Short name T1012
Test name
Test status
Simulation time 30105776 ps
CPU time 1.03 seconds
Started Jun 30 06:18:33 PM PDT 24
Finished Jun 30 06:18:35 PM PDT 24
Peak memory 215184 kb
Host smart-13c38162-4f89-4c62-9de2-5dc0d0f9e4df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799138189 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2799138189
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3642646026
Short name T257
Test name
Test status
Simulation time 28249115 ps
CPU time 0.96 seconds
Started Jun 30 06:18:35 PM PDT 24
Finished Jun 30 06:18:37 PM PDT 24
Peak memory 206388 kb
Host smart-d64a761c-eaf9-4d55-b3fe-27786534bf79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642646026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3642646026
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1291799573
Short name T1043
Test name
Test status
Simulation time 12144687 ps
CPU time 0.88 seconds
Started Jun 30 06:18:34 PM PDT 24
Finished Jun 30 06:18:36 PM PDT 24
Peak memory 206880 kb
Host smart-0b3b2b43-1f2f-49a7-af7f-63e0995e52a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291799573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1291799573
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1248174324
Short name T1121
Test name
Test status
Simulation time 62919812 ps
CPU time 1.18 seconds
Started Jun 30 06:18:34 PM PDT 24
Finished Jun 30 06:18:35 PM PDT 24
Peak memory 207000 kb
Host smart-3ae9eaec-be02-4f10-b4f1-939feda3fe40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248174324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1248174324
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3845776635
Short name T996
Test name
Test status
Simulation time 461537473 ps
CPU time 4.5 seconds
Started Jun 30 06:18:32 PM PDT 24
Finished Jun 30 06:18:37 PM PDT 24
Peak memory 215232 kb
Host smart-42306cc3-5a39-417a-b919-dc4afec668a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845776635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3845776635
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2422416056
Short name T1125
Test name
Test status
Simulation time 78268085 ps
CPU time 1.51 seconds
Started Jun 30 06:18:34 PM PDT 24
Finished Jun 30 06:18:36 PM PDT 24
Peak memory 206932 kb
Host smart-e706b2a3-232b-433e-a167-74dd483a4542
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422416056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2422416056
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1118796460
Short name T1123
Test name
Test status
Simulation time 71615064 ps
CPU time 1.1 seconds
Started Jun 30 06:18:33 PM PDT 24
Finished Jun 30 06:18:34 PM PDT 24
Peak memory 216580 kb
Host smart-1bac8ed8-8ff8-4e9a-a139-cf8ef34a7218
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118796460 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1118796460
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.985723148
Short name T253
Test name
Test status
Simulation time 13230743 ps
CPU time 0.94 seconds
Started Jun 30 06:18:34 PM PDT 24
Finished Jun 30 06:18:36 PM PDT 24
Peak memory 206920 kb
Host smart-ff078172-d9b5-4572-a9b1-7709c2ffbdd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985723148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.985723148
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1875332842
Short name T1001
Test name
Test status
Simulation time 14555802 ps
CPU time 0.83 seconds
Started Jun 30 06:18:32 PM PDT 24
Finished Jun 30 06:18:33 PM PDT 24
Peak memory 206892 kb
Host smart-672c14ef-13d6-4118-9116-d99c8cbb3044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875332842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1875332842
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.363834632
Short name T1093
Test name
Test status
Simulation time 14798420 ps
CPU time 1.04 seconds
Started Jun 30 06:18:33 PM PDT 24
Finished Jun 30 06:18:34 PM PDT 24
Peak memory 206924 kb
Host smart-b44b1f71-c6f1-4911-9e84-515cc79b22a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363834632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.363834632
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3346256053
Short name T1101
Test name
Test status
Simulation time 210822947 ps
CPU time 4.23 seconds
Started Jun 30 06:18:32 PM PDT 24
Finished Jun 30 06:18:37 PM PDT 24
Peak memory 215156 kb
Host smart-820a55e7-9ac6-4810-97bc-7f3292e5feeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346256053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3346256053
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2849770245
Short name T1070
Test name
Test status
Simulation time 317443280 ps
CPU time 2.38 seconds
Started Jun 30 06:18:32 PM PDT 24
Finished Jun 30 06:18:35 PM PDT 24
Peak memory 207004 kb
Host smart-c459b6e4-e988-4ac1-9342-163a507d852a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849770245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2849770245
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.2754643738
Short name T385
Test name
Test status
Simulation time 85198557 ps
CPU time 1.16 seconds
Started Jun 30 05:21:44 PM PDT 24
Finished Jun 30 05:21:45 PM PDT 24
Peak memory 219764 kb
Host smart-688f4e09-55cc-423e-9734-72677a476f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754643738 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2754643738
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.1126791274
Short name T805
Test name
Test status
Simulation time 85572564 ps
CPU time 0.84 seconds
Started Jun 30 05:21:40 PM PDT 24
Finished Jun 30 05:21:42 PM PDT 24
Peak memory 215004 kb
Host smart-bb29d635-fd28-4bd7-89b0-73646601d2a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126791274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1126791274
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.2860526176
Short name T825
Test name
Test status
Simulation time 118189015 ps
CPU time 0.84 seconds
Started Jun 30 05:21:39 PM PDT 24
Finished Jun 30 05:21:40 PM PDT 24
Peak memory 216208 kb
Host smart-e6893fc3-26cd-4998-8955-1628c422e143
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860526176 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2860526176
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.2304353379
Short name T14
Test name
Test status
Simulation time 19525714 ps
CPU time 1.21 seconds
Started Jun 30 05:21:39 PM PDT 24
Finished Jun 30 05:21:40 PM PDT 24
Peak memory 224148 kb
Host smart-dfe0c0ca-4dd5-4a37-98b7-6c26890ddb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304353379 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2304353379
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1014921114
Short name T881
Test name
Test status
Simulation time 62060313 ps
CPU time 1.68 seconds
Started Jun 30 05:21:39 PM PDT 24
Finished Jun 30 05:21:41 PM PDT 24
Peak memory 219032 kb
Host smart-8cfb6247-b04e-44a1-ab23-64d9d1176550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014921114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1014921114
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.3026042143
Short name T673
Test name
Test status
Simulation time 22496579 ps
CPU time 1.06 seconds
Started Jun 30 05:21:40 PM PDT 24
Finished Jun 30 05:21:42 PM PDT 24
Peak memory 215668 kb
Host smart-696f6b99-978c-4f84-b638-79989b88adda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026042143 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3026042143
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.3779402515
Short name T517
Test name
Test status
Simulation time 19373341 ps
CPU time 1 seconds
Started Jun 30 05:21:32 PM PDT 24
Finished Jun 30 05:21:33 PM PDT 24
Peak memory 207364 kb
Host smart-52297673-9209-4a31-bbea-113a65b08a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779402515 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3779402515
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.3889799482
Short name T529
Test name
Test status
Simulation time 84076038 ps
CPU time 0.93 seconds
Started Jun 30 05:21:32 PM PDT 24
Finished Jun 30 05:21:33 PM PDT 24
Peak memory 215584 kb
Host smart-c2ab0d49-82f6-4861-84d4-e8e63f94df4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889799482 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3889799482
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.813032815
Short name T681
Test name
Test status
Simulation time 366689045 ps
CPU time 2.56 seconds
Started Jun 30 05:21:40 PM PDT 24
Finished Jun 30 05:21:43 PM PDT 24
Peak memory 217712 kb
Host smart-f01aa67f-904f-4acf-a49b-7619515d4b99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813032815 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.813032815
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3484676360
Short name T609
Test name
Test status
Simulation time 56844573029 ps
CPU time 758.12 seconds
Started Jun 30 05:21:40 PM PDT 24
Finished Jun 30 05:34:19 PM PDT 24
Peak memory 219300 kb
Host smart-cf9a4034-41d5-48e0-92e2-ce77bcdc20bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484676360 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3484676360
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.386941375
Short name T955
Test name
Test status
Simulation time 70456418 ps
CPU time 1.08 seconds
Started Jun 30 05:21:45 PM PDT 24
Finished Jun 30 05:21:47 PM PDT 24
Peak memory 219064 kb
Host smart-e6003f05-6d36-4f2b-a273-51f1f3c674f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386941375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.386941375
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.3342365410
Short name T366
Test name
Test status
Simulation time 52139150 ps
CPU time 0.94 seconds
Started Jun 30 05:21:46 PM PDT 24
Finished Jun 30 05:21:48 PM PDT 24
Peak memory 207224 kb
Host smart-133686fd-3b11-430f-a3bd-c4ac4538f0f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342365410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3342365410
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_err.1459879964
Short name T797
Test name
Test status
Simulation time 31192346 ps
CPU time 0.84 seconds
Started Jun 30 05:21:46 PM PDT 24
Finished Jun 30 05:21:47 PM PDT 24
Peak memory 218640 kb
Host smart-4f40deed-89e9-4fff-beec-db4120b37539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459879964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1459879964
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3738559336
Short name T791
Test name
Test status
Simulation time 111153779 ps
CPU time 1.38 seconds
Started Jun 30 05:21:39 PM PDT 24
Finished Jun 30 05:21:41 PM PDT 24
Peak memory 215520 kb
Host smart-7ff08d60-d87a-4842-83fc-d8fcbdcd774f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738559336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3738559336
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1203388635
Short name T451
Test name
Test status
Simulation time 38643418 ps
CPU time 0.91 seconds
Started Jun 30 05:21:41 PM PDT 24
Finished Jun 30 05:21:42 PM PDT 24
Peak memory 216024 kb
Host smart-73335a7c-1931-448c-bc72-4e3168a3192a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203388635 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1203388635
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.2560262154
Short name T850
Test name
Test status
Simulation time 54278935 ps
CPU time 0.92 seconds
Started Jun 30 05:21:39 PM PDT 24
Finished Jun 30 05:21:41 PM PDT 24
Peak memory 207436 kb
Host smart-bd12edaa-a66a-4257-906b-a1f77743d51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560262154 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2560262154
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3741500010
Short name T62
Test name
Test status
Simulation time 845279106 ps
CPU time 7.17 seconds
Started Jun 30 05:21:46 PM PDT 24
Finished Jun 30 05:21:54 PM PDT 24
Peak memory 237852 kb
Host smart-9fc0ff1e-f816-4e84-9394-6002552782b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741500010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3741500010
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.4183418191
Short name T618
Test name
Test status
Simulation time 63897424 ps
CPU time 0.96 seconds
Started Jun 30 05:21:40 PM PDT 24
Finished Jun 30 05:21:42 PM PDT 24
Peak memory 215804 kb
Host smart-60ad7423-887e-484a-a4bc-6fa85f53d6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183418191 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.4183418191
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2935852279
Short name T793
Test name
Test status
Simulation time 218518022 ps
CPU time 4.89 seconds
Started Jun 30 05:21:38 PM PDT 24
Finished Jun 30 05:21:43 PM PDT 24
Peak memory 220076 kb
Host smart-ec93cad8-9bb6-4748-9533-002f59c94da7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935852279 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2935852279
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1936863919
Short name T389
Test name
Test status
Simulation time 33355497854 ps
CPU time 820.78 seconds
Started Jun 30 05:21:39 PM PDT 24
Finished Jun 30 05:35:20 PM PDT 24
Peak memory 219804 kb
Host smart-e9b9fdd3-ee63-4c51-9820-c7dd1d6fb733
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936863919 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1936863919
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.2625481750
Short name T572
Test name
Test status
Simulation time 23260588 ps
CPU time 1.09 seconds
Started Jun 30 05:22:29 PM PDT 24
Finished Jun 30 05:22:30 PM PDT 24
Peak memory 218812 kb
Host smart-1a549723-544d-43df-b1b1-852880b02563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625481750 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2625481750
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.933743632
Short name T636
Test name
Test status
Simulation time 24694004 ps
CPU time 0.9 seconds
Started Jun 30 05:22:29 PM PDT 24
Finished Jun 30 05:22:30 PM PDT 24
Peak memory 207024 kb
Host smart-607b3335-0572-4ec4-a10b-05402ac0f0d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933743632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.933743632
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3618891329
Short name T570
Test name
Test status
Simulation time 104196012 ps
CPU time 1.19 seconds
Started Jun 30 05:22:31 PM PDT 24
Finished Jun 30 05:22:33 PM PDT 24
Peak memory 217108 kb
Host smart-0701b347-be27-43c0-9ecf-c08f2a148e31
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618891329 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3618891329
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.2453429415
Short name T172
Test name
Test status
Simulation time 52342310 ps
CPU time 1.11 seconds
Started Jun 30 05:22:31 PM PDT 24
Finished Jun 30 05:22:33 PM PDT 24
Peak memory 218716 kb
Host smart-0d12307f-ff7b-4ece-b3aa-26f8627c6a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453429415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2453429415
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.4129683950
Short name T930
Test name
Test status
Simulation time 55283497 ps
CPU time 1.55 seconds
Started Jun 30 05:22:25 PM PDT 24
Finished Jun 30 05:22:27 PM PDT 24
Peak memory 220168 kb
Host smart-915806dd-382a-4a2f-b531-21dec59a733c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129683950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.4129683950
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1951313531
Short name T771
Test name
Test status
Simulation time 23071737 ps
CPU time 1.22 seconds
Started Jun 30 05:22:21 PM PDT 24
Finished Jun 30 05:22:23 PM PDT 24
Peak memory 224324 kb
Host smart-093d3da7-50cc-4014-8734-c096dacc928f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951313531 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1951313531
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.437976386
Short name T371
Test name
Test status
Simulation time 22419733 ps
CPU time 0.98 seconds
Started Jun 30 05:22:21 PM PDT 24
Finished Jun 30 05:22:23 PM PDT 24
Peak memory 215524 kb
Host smart-8b0c1523-9059-4f8c-9048-4f821153e5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437976386 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.437976386
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1154696044
Short name T706
Test name
Test status
Simulation time 164771388 ps
CPU time 1.49 seconds
Started Jun 30 05:22:19 PM PDT 24
Finished Jun 30 05:22:21 PM PDT 24
Peak memory 217788 kb
Host smart-5b51da33-49ad-4da9-8e5a-b2e75a6bbd91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154696044 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1154696044
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3299410852
Short name T687
Test name
Test status
Simulation time 224875616708 ps
CPU time 1354.69 seconds
Started Jun 30 05:22:22 PM PDT 24
Finished Jun 30 05:44:57 PM PDT 24
Peak memory 224336 kb
Host smart-2eb81c61-6264-4070-a50a-9cfea4a1fe7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299410852 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3299410852
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.1439360245
Short name T516
Test name
Test status
Simulation time 37092498 ps
CPU time 1.37 seconds
Started Jun 30 05:25:00 PM PDT 24
Finished Jun 30 05:25:02 PM PDT 24
Peak memory 215628 kb
Host smart-de092d84-a7c2-4700-8301-e515fb5230a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439360245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1439360245
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.3494650632
Short name T234
Test name
Test status
Simulation time 40572241 ps
CPU time 1.29 seconds
Started Jun 30 05:25:00 PM PDT 24
Finished Jun 30 05:25:03 PM PDT 24
Peak memory 219036 kb
Host smart-e54c718b-ebf4-46f9-9ed6-e614245f75e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494650632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.3494650632
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/102.edn_alert.669194610
Short name T877
Test name
Test status
Simulation time 207476956 ps
CPU time 1.21 seconds
Started Jun 30 05:24:59 PM PDT 24
Finished Jun 30 05:25:01 PM PDT 24
Peak memory 220148 kb
Host smart-32d7a303-e03f-4329-b733-a55e0c4b5415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669194610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.669194610
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.2556277027
Short name T837
Test name
Test status
Simulation time 26281342 ps
CPU time 1.28 seconds
Started Jun 30 05:24:59 PM PDT 24
Finished Jun 30 05:25:00 PM PDT 24
Peak memory 218672 kb
Host smart-302fb584-fef0-4c58-86f9-f8893f52abe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556277027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2556277027
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.1208307920
Short name T149
Test name
Test status
Simulation time 25302446 ps
CPU time 1.19 seconds
Started Jun 30 05:24:59 PM PDT 24
Finished Jun 30 05:25:01 PM PDT 24
Peak memory 220364 kb
Host smart-3d1772dc-68f8-4f0d-b1c1-549f8647c370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208307920 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1208307920
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.4080943581
Short name T376
Test name
Test status
Simulation time 85171127 ps
CPU time 1.06 seconds
Started Jun 30 05:24:59 PM PDT 24
Finished Jun 30 05:25:01 PM PDT 24
Peak memory 217708 kb
Host smart-c5a2b46b-2d86-45c8-9e12-f1f8f4aa98db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080943581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.4080943581
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.2741425986
Short name T92
Test name
Test status
Simulation time 41736447 ps
CPU time 1.11 seconds
Started Jun 30 05:24:58 PM PDT 24
Finished Jun 30 05:25:00 PM PDT 24
Peak memory 219964 kb
Host smart-86a29f11-2e9a-4173-aa53-a7e3d2e54da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741425986 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.2741425986
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.3972833239
Short name T524
Test name
Test status
Simulation time 59193162 ps
CPU time 1.5 seconds
Started Jun 30 05:24:59 PM PDT 24
Finished Jun 30 05:25:01 PM PDT 24
Peak memory 218872 kb
Host smart-0a652b08-112b-4010-a244-7cbccdc5e345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972833239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3972833239
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.5929839
Short name T586
Test name
Test status
Simulation time 28470481 ps
CPU time 1.2 seconds
Started Jun 30 05:25:00 PM PDT 24
Finished Jun 30 05:25:02 PM PDT 24
Peak memory 220228 kb
Host smart-5173a7ff-0f8e-405f-8238-f9266e243696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5929839 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.5929839
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.3189442592
Short name T363
Test name
Test status
Simulation time 48263575 ps
CPU time 1.32 seconds
Started Jun 30 05:24:59 PM PDT 24
Finished Jun 30 05:25:01 PM PDT 24
Peak memory 217920 kb
Host smart-0cf83d79-8a55-4d73-a8fe-acf98754d819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189442592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3189442592
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.2705555470
Short name T283
Test name
Test status
Simulation time 28201968 ps
CPU time 1.28 seconds
Started Jun 30 05:25:01 PM PDT 24
Finished Jun 30 05:25:03 PM PDT 24
Peak memory 221060 kb
Host smart-b8cabe1f-04fc-4d5b-9d66-c50b99e6c95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705555470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2705555470
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/107.edn_alert.1558978378
Short name T2
Test name
Test status
Simulation time 48762328 ps
CPU time 1.12 seconds
Started Jun 30 05:25:08 PM PDT 24
Finished Jun 30 05:25:09 PM PDT 24
Peak memory 219972 kb
Host smart-3edc89d6-2c75-443f-9de4-29b91c064452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558978378 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.1558978378
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.1125200896
Short name T348
Test name
Test status
Simulation time 43664972 ps
CPU time 1.19 seconds
Started Jun 30 05:24:59 PM PDT 24
Finished Jun 30 05:25:01 PM PDT 24
Peak memory 217708 kb
Host smart-40caba38-789b-4b51-b774-1810c5f2a991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125200896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1125200896
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.1073549244
Short name T492
Test name
Test status
Simulation time 33994537 ps
CPU time 1.32 seconds
Started Jun 30 05:24:59 PM PDT 24
Finished Jun 30 05:25:00 PM PDT 24
Peak memory 217596 kb
Host smart-3fa178b1-bbc0-4358-b12f-a99d0442fa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073549244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1073549244
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.3060093548
Short name T523
Test name
Test status
Simulation time 16913573 ps
CPU time 0.93 seconds
Started Jun 30 05:22:30 PM PDT 24
Finished Jun 30 05:22:32 PM PDT 24
Peak memory 215684 kb
Host smart-15b3a3e7-e54f-41a7-9a4b-d0ac7e2166e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060093548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3060093548
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.2861298149
Short name T205
Test name
Test status
Simulation time 21477205 ps
CPU time 0.89 seconds
Started Jun 30 05:22:29 PM PDT 24
Finished Jun 30 05:22:31 PM PDT 24
Peak memory 215732 kb
Host smart-8c4d9651-ea51-4677-9479-230994e39955
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861298149 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2861298149
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1885045581
Short name T405
Test name
Test status
Simulation time 63738785 ps
CPU time 1.22 seconds
Started Jun 30 05:22:33 PM PDT 24
Finished Jun 30 05:22:35 PM PDT 24
Peak memory 217104 kb
Host smart-7a0d6514-fe72-42d2-93a3-04d603c26c59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885045581 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1885045581
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1039975779
Short name T145
Test name
Test status
Simulation time 45754949 ps
CPU time 1.26 seconds
Started Jun 30 05:22:29 PM PDT 24
Finished Jun 30 05:22:32 PM PDT 24
Peak memory 226248 kb
Host smart-fea135d6-7c10-4d64-8f27-060b62eb4aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039975779 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1039975779
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1560551701
Short name T981
Test name
Test status
Simulation time 40390175 ps
CPU time 1.57 seconds
Started Jun 30 05:22:31 PM PDT 24
Finished Jun 30 05:22:34 PM PDT 24
Peak memory 218832 kb
Host smart-41fe705d-0f35-46db-a7d4-94553bdacd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560551701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1560551701
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.3392759549
Short name T489
Test name
Test status
Simulation time 19965347 ps
CPU time 1.09 seconds
Started Jun 30 05:22:28 PM PDT 24
Finished Jun 30 05:22:30 PM PDT 24
Peak memory 216160 kb
Host smart-d8fd5aad-9755-47a3-a731-71d3e29a4cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392759549 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3392759549
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1886529687
Short name T551
Test name
Test status
Simulation time 16671296 ps
CPU time 1.01 seconds
Started Jun 30 05:22:29 PM PDT 24
Finished Jun 30 05:22:31 PM PDT 24
Peak memory 215576 kb
Host smart-a07a8b35-93fa-4bcb-8962-9a1696a0d036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886529687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1886529687
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.755205218
Short name T60
Test name
Test status
Simulation time 258975155 ps
CPU time 5.53 seconds
Started Jun 30 05:22:29 PM PDT 24
Finished Jun 30 05:22:35 PM PDT 24
Peak memory 215584 kb
Host smart-e98336ee-a930-4fca-bfc2-3a2cb3b94b5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755205218 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.755205218
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/110.edn_alert.1168617176
Short name T182
Test name
Test status
Simulation time 27726559 ps
CPU time 1.26 seconds
Started Jun 30 05:25:08 PM PDT 24
Finished Jun 30 05:25:10 PM PDT 24
Peak memory 216016 kb
Host smart-d5ec8ecb-49d6-4d31-b7e3-bc2633a954de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168617176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.1168617176
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.3932054606
Short name T444
Test name
Test status
Simulation time 52557916 ps
CPU time 1.62 seconds
Started Jun 30 05:25:06 PM PDT 24
Finished Jun 30 05:25:08 PM PDT 24
Peak memory 218756 kb
Host smart-c03e5d71-3953-4024-b0cb-934b92305a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932054606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3932054606
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.1716639219
Short name T862
Test name
Test status
Simulation time 32226246 ps
CPU time 1.38 seconds
Started Jun 30 05:25:10 PM PDT 24
Finished Jun 30 05:25:12 PM PDT 24
Peak memory 216016 kb
Host smart-ebbcea94-0993-4fdf-a37c-e5ec8e6e6cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716639219 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.1716639219
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.739556100
Short name T721
Test name
Test status
Simulation time 41004065 ps
CPU time 1.43 seconds
Started Jun 30 05:25:06 PM PDT 24
Finished Jun 30 05:25:08 PM PDT 24
Peak memory 218812 kb
Host smart-9ca71afa-8663-4def-9347-ce3f7c3dfffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739556100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.739556100
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.2956576239
Short name T657
Test name
Test status
Simulation time 42331977 ps
CPU time 1.09 seconds
Started Jun 30 05:25:10 PM PDT 24
Finished Jun 30 05:25:12 PM PDT 24
Peak memory 217556 kb
Host smart-aed4c2f0-9443-4a33-ac82-6cde755a9b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956576239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2956576239
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.2349505222
Short name T801
Test name
Test status
Simulation time 132563479 ps
CPU time 1.37 seconds
Started Jun 30 05:25:10 PM PDT 24
Finished Jun 30 05:25:12 PM PDT 24
Peak memory 219968 kb
Host smart-0a28a895-20c6-4b53-af2c-0c5f1151915e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349505222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.2349505222
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.3111792277
Short name T746
Test name
Test status
Simulation time 90651068 ps
CPU time 2.18 seconds
Started Jun 30 05:25:10 PM PDT 24
Finished Jun 30 05:25:13 PM PDT 24
Peak memory 220384 kb
Host smart-a14c17b4-9407-4bbd-b58c-6d384bac44fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111792277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3111792277
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.672871194
Short name T421
Test name
Test status
Simulation time 24459344 ps
CPU time 1.21 seconds
Started Jun 30 05:25:08 PM PDT 24
Finished Jun 30 05:25:10 PM PDT 24
Peak memory 221196 kb
Host smart-dddb4fd4-d14e-4a9c-9515-f3f27aa6c937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672871194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.672871194
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.3222991286
Short name T968
Test name
Test status
Simulation time 81889696 ps
CPU time 1.8 seconds
Started Jun 30 05:25:07 PM PDT 24
Finished Jun 30 05:25:10 PM PDT 24
Peak memory 220508 kb
Host smart-2a8aac2b-bfde-444b-a767-936fe31a5da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222991286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3222991286
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.991702699
Short name T481
Test name
Test status
Simulation time 38704647 ps
CPU time 1.1 seconds
Started Jun 30 05:25:11 PM PDT 24
Finished Jun 30 05:25:12 PM PDT 24
Peak memory 216036 kb
Host smart-ba7b7ad7-b7f4-4a24-8687-0bba067e20da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991702699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.991702699
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.1674408034
Short name T359
Test name
Test status
Simulation time 49550915 ps
CPU time 1.76 seconds
Started Jun 30 05:25:09 PM PDT 24
Finished Jun 30 05:25:11 PM PDT 24
Peak memory 218620 kb
Host smart-29193196-08f1-4196-80f8-593d9ae8e38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674408034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1674408034
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.3277609540
Short name T753
Test name
Test status
Simulation time 44589126 ps
CPU time 1.17 seconds
Started Jun 30 05:25:11 PM PDT 24
Finished Jun 30 05:25:13 PM PDT 24
Peak memory 218908 kb
Host smart-1ff5e590-f878-4642-89a9-1abfa8f53cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277609540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.3277609540
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.1135907205
Short name T66
Test name
Test status
Simulation time 69965251 ps
CPU time 1.06 seconds
Started Jun 30 05:25:07 PM PDT 24
Finished Jun 30 05:25:08 PM PDT 24
Peak memory 217456 kb
Host smart-bd3449b6-121d-40b5-ba32-eab2786ebd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135907205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1135907205
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.1514186885
Short name T772
Test name
Test status
Simulation time 68271800 ps
CPU time 1.1 seconds
Started Jun 30 05:25:06 PM PDT 24
Finished Jun 30 05:25:08 PM PDT 24
Peak memory 219820 kb
Host smart-892a4222-52dd-408a-bf04-f7204b65af76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514186885 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.1514186885
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.4120219254
Short name T617
Test name
Test status
Simulation time 27904931 ps
CPU time 1.22 seconds
Started Jun 30 05:25:08 PM PDT 24
Finished Jun 30 05:25:10 PM PDT 24
Peak memory 220256 kb
Host smart-4ea95fd1-d257-4478-8960-0ec787833bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120219254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.4120219254
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.3974935782
Short name T525
Test name
Test status
Simulation time 367489572 ps
CPU time 1.25 seconds
Started Jun 30 05:25:07 PM PDT 24
Finished Jun 30 05:25:09 PM PDT 24
Peak memory 218968 kb
Host smart-40a095dd-15c5-4cd1-af8a-b086872cb11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974935782 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.3974935782
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.4185262263
Short name T333
Test name
Test status
Simulation time 41151836 ps
CPU time 1.48 seconds
Started Jun 30 05:25:06 PM PDT 24
Finished Jun 30 05:25:07 PM PDT 24
Peak memory 217528 kb
Host smart-5dbe1b1c-05af-44fd-ab00-d9dba5fdc378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185262263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.4185262263
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2295791637
Short name T526
Test name
Test status
Simulation time 30116768 ps
CPU time 1.32 seconds
Started Jun 30 05:22:27 PM PDT 24
Finished Jun 30 05:22:29 PM PDT 24
Peak memory 218936 kb
Host smart-169377f6-f331-496d-8030-1ba9c3df7f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295791637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2295791637
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable.1609708366
Short name T818
Test name
Test status
Simulation time 38187474 ps
CPU time 0.85 seconds
Started Jun 30 05:22:31 PM PDT 24
Finished Jun 30 05:22:33 PM PDT 24
Peak memory 216528 kb
Host smart-5e4089e2-7bbd-4968-b615-66bdf5b3b2c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609708366 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1609708366
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.394679076
Short name T560
Test name
Test status
Simulation time 120892836 ps
CPU time 1.28 seconds
Started Jun 30 05:22:33 PM PDT 24
Finished Jun 30 05:22:35 PM PDT 24
Peak memory 217052 kb
Host smart-7c8bf514-3a76-4612-9098-6562295c93d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394679076 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.394679076
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.222452265
Short name T691
Test name
Test status
Simulation time 61870951 ps
CPU time 1 seconds
Started Jun 30 05:22:30 PM PDT 24
Finished Jun 30 05:22:32 PM PDT 24
Peak memory 221044 kb
Host smart-d565b6d4-5bcf-49e8-9c93-c9e96daccf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222452265 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.222452265
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2306200171
Short name T890
Test name
Test status
Simulation time 61917291 ps
CPU time 1.43 seconds
Started Jun 30 05:22:29 PM PDT 24
Finished Jun 30 05:22:31 PM PDT 24
Peak memory 218740 kb
Host smart-40a4e4ba-75bd-4433-8f09-4eed54f00add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306200171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2306200171
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.965203286
Short name T447
Test name
Test status
Simulation time 30688924 ps
CPU time 1.02 seconds
Started Jun 30 05:22:30 PM PDT 24
Finished Jun 30 05:22:32 PM PDT 24
Peak memory 215864 kb
Host smart-e9199699-9439-4bed-8863-1c0192607fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965203286 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.965203286
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1014678969
Short name T470
Test name
Test status
Simulation time 48663763 ps
CPU time 0.9 seconds
Started Jun 30 05:22:31 PM PDT 24
Finished Jun 30 05:22:33 PM PDT 24
Peak memory 215592 kb
Host smart-87d4910f-f254-4a2b-98b4-916a4e375c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014678969 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1014678969
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.4100636811
Short name T232
Test name
Test status
Simulation time 92529036 ps
CPU time 2.19 seconds
Started Jun 30 05:22:30 PM PDT 24
Finished Jun 30 05:22:34 PM PDT 24
Peak memory 217456 kb
Host smart-d30bf67a-32c1-4b5b-a1db-c96743ee214b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100636811 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.4100636811
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/120.edn_alert.3076299283
Short name T235
Test name
Test status
Simulation time 44867235 ps
CPU time 1.22 seconds
Started Jun 30 05:25:05 PM PDT 24
Finished Jun 30 05:25:07 PM PDT 24
Peak memory 219612 kb
Host smart-a1823af9-3e84-43f2-8a24-dd934e443aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076299283 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.3076299283
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.3896134740
Short name T898
Test name
Test status
Simulation time 45198086 ps
CPU time 1.48 seconds
Started Jun 30 05:25:09 PM PDT 24
Finished Jun 30 05:25:11 PM PDT 24
Peak memory 218528 kb
Host smart-2504e103-22ef-42d6-8e6b-2ff9c50046d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896134740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3896134740
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.991205093
Short name T773
Test name
Test status
Simulation time 68354618 ps
CPU time 1.21 seconds
Started Jun 30 05:25:07 PM PDT 24
Finished Jun 30 05:25:09 PM PDT 24
Peak memory 219316 kb
Host smart-2bfdb045-688b-4c1e-92aa-035fda0c539d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991205093 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.991205093
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.1103079467
Short name T351
Test name
Test status
Simulation time 100626203 ps
CPU time 2.88 seconds
Started Jun 30 05:25:06 PM PDT 24
Finished Jun 30 05:25:10 PM PDT 24
Peak memory 220492 kb
Host smart-217ab944-862b-4852-95a7-b49e17b19b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103079467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1103079467
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.244794890
Short name T694
Test name
Test status
Simulation time 74112951 ps
CPU time 1.31 seconds
Started Jun 30 05:25:07 PM PDT 24
Finished Jun 30 05:25:10 PM PDT 24
Peak memory 220172 kb
Host smart-ec8d3105-a175-41bd-a7ab-4ebe9db925cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244794890 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.244794890
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.2510247116
Short name T77
Test name
Test status
Simulation time 203913332 ps
CPU time 1.23 seconds
Started Jun 30 05:25:09 PM PDT 24
Finished Jun 30 05:25:10 PM PDT 24
Peak memory 215516 kb
Host smart-345021dc-9d7b-4567-956b-aef77baefba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510247116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2510247116
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2858543385
Short name T418
Test name
Test status
Simulation time 231036477 ps
CPU time 1.5 seconds
Started Jun 30 05:25:06 PM PDT 24
Finished Jun 30 05:25:08 PM PDT 24
Peak memory 219356 kb
Host smart-07bd28bb-17e4-41c2-bcc6-197a48d2486a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858543385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2858543385
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.2829101578
Short name T631
Test name
Test status
Simulation time 24682024 ps
CPU time 1.22 seconds
Started Jun 30 05:25:15 PM PDT 24
Finished Jun 30 05:25:17 PM PDT 24
Peak memory 218772 kb
Host smart-58dceb13-e8bb-4181-bbd3-500fa68bee77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829101578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.2829101578
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.3745059168
Short name T610
Test name
Test status
Simulation time 31506720 ps
CPU time 1.19 seconds
Started Jun 30 05:25:13 PM PDT 24
Finished Jun 30 05:25:15 PM PDT 24
Peak memory 217520 kb
Host smart-80cbdf1a-521b-4fc1-aec9-6e266959481a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745059168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3745059168
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.3462432574
Short name T128
Test name
Test status
Simulation time 78935852 ps
CPU time 1.14 seconds
Started Jun 30 05:25:13 PM PDT 24
Finished Jun 30 05:25:15 PM PDT 24
Peak memory 218996 kb
Host smart-b58ced24-eb02-4f8a-8865-4f9f3e9f6c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462432574 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.3462432574
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.3889726817
Short name T511
Test name
Test status
Simulation time 37730033 ps
CPU time 1.09 seconds
Started Jun 30 05:25:15 PM PDT 24
Finished Jun 30 05:25:17 PM PDT 24
Peak memory 218752 kb
Host smart-fd4e0d8c-9955-4080-86a1-f3b6d5b23c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889726817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3889726817
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.821002457
Short name T956
Test name
Test status
Simulation time 83819214 ps
CPU time 1.2 seconds
Started Jun 30 05:25:12 PM PDT 24
Finished Jun 30 05:25:14 PM PDT 24
Peak memory 219836 kb
Host smart-e714af6a-96b7-4cc8-b8f1-d877483f01d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821002457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.821002457
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.3354128074
Short name T992
Test name
Test status
Simulation time 50278678 ps
CPU time 1.1 seconds
Started Jun 30 05:25:15 PM PDT 24
Finished Jun 30 05:25:17 PM PDT 24
Peak memory 217620 kb
Host smart-7f2239a0-18db-4a08-9e06-4e73457a72cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354128074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3354128074
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.2390614469
Short name T362
Test name
Test status
Simulation time 39390117 ps
CPU time 1.25 seconds
Started Jun 30 05:25:14 PM PDT 24
Finished Jun 30 05:25:15 PM PDT 24
Peak memory 220616 kb
Host smart-219edeff-9741-4f5c-b34f-ee843620adb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390614469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.2390614469
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.3918439751
Short name T616
Test name
Test status
Simulation time 142058568 ps
CPU time 1.77 seconds
Started Jun 30 05:25:12 PM PDT 24
Finished Jun 30 05:25:14 PM PDT 24
Peak memory 219840 kb
Host smart-da9c1767-1f2c-4c0c-ae00-442b9a98471b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918439751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3918439751
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.1030184568
Short name T477
Test name
Test status
Simulation time 91093164 ps
CPU time 1.25 seconds
Started Jun 30 05:25:12 PM PDT 24
Finished Jun 30 05:25:14 PM PDT 24
Peak memory 219000 kb
Host smart-04c19fca-5246-4b4c-aaa0-a9e8f6847327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030184568 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.1030184568
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.1947918845
Short name T827
Test name
Test status
Simulation time 50848575 ps
CPU time 1.33 seconds
Started Jun 30 05:25:13 PM PDT 24
Finished Jun 30 05:25:15 PM PDT 24
Peak memory 217628 kb
Host smart-f34f1abb-7326-4de6-8b59-74790b4ca52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947918845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1947918845
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.107536117
Short name T789
Test name
Test status
Simulation time 27590734 ps
CPU time 1.29 seconds
Started Jun 30 05:22:31 PM PDT 24
Finished Jun 30 05:22:33 PM PDT 24
Peak memory 219696 kb
Host smart-49d5ff8c-2a95-4832-a854-3cb4cc002828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107536117 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.107536117
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.1385072512
Short name T372
Test name
Test status
Simulation time 30695280 ps
CPU time 0.87 seconds
Started Jun 30 05:22:39 PM PDT 24
Finished Jun 30 05:22:41 PM PDT 24
Peak memory 206660 kb
Host smart-ec9abdd1-a23f-4c27-91da-963ab9dacff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385072512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1385072512
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3281278107
Short name T744
Test name
Test status
Simulation time 20742683 ps
CPU time 0.83 seconds
Started Jun 30 05:22:35 PM PDT 24
Finished Jun 30 05:22:36 PM PDT 24
Peak memory 215648 kb
Host smart-e8f1c882-365d-40ba-aa26-4c1ee7eb0c13
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281278107 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3281278107
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2452894325
Short name T194
Test name
Test status
Simulation time 78650473 ps
CPU time 1.07 seconds
Started Jun 30 05:22:39 PM PDT 24
Finished Jun 30 05:22:41 PM PDT 24
Peak memory 217180 kb
Host smart-b384c09d-996d-4833-844f-517d283a72d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452894325 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2452894325
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2357675081
Short name T912
Test name
Test status
Simulation time 24369841 ps
CPU time 1.18 seconds
Started Jun 30 05:22:39 PM PDT 24
Finished Jun 30 05:22:41 PM PDT 24
Peak memory 219852 kb
Host smart-654b3c3c-5c31-4bba-a2be-c408bf22f11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357675081 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2357675081
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3969413913
Short name T975
Test name
Test status
Simulation time 55248169 ps
CPU time 1.4 seconds
Started Jun 30 05:22:28 PM PDT 24
Finished Jun 30 05:22:30 PM PDT 24
Peak memory 218708 kb
Host smart-0223f0e6-c9c0-4cca-80e3-75e04645ed64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969413913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3969413913
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1556936633
Short name T4
Test name
Test status
Simulation time 37108352 ps
CPU time 0.9 seconds
Started Jun 30 05:22:31 PM PDT 24
Finished Jun 30 05:22:33 PM PDT 24
Peak memory 215708 kb
Host smart-e7e7ef87-6535-4fda-b0ee-b1e0e464fa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556936633 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1556936633
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.4135075259
Short name T593
Test name
Test status
Simulation time 21677982 ps
CPU time 0.96 seconds
Started Jun 30 05:22:33 PM PDT 24
Finished Jun 30 05:22:35 PM PDT 24
Peak memory 215564 kb
Host smart-75493a07-ad17-4ad2-9ab3-ff63f319deb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135075259 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.4135075259
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1514976571
Short name T892
Test name
Test status
Simulation time 174726691 ps
CPU time 3.78 seconds
Started Jun 30 05:22:28 PM PDT 24
Finished Jun 30 05:22:32 PM PDT 24
Peak memory 219900 kb
Host smart-d33ddaaf-89db-4fcc-a103-e891b4d8857b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514976571 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1514976571
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1077315548
Short name T761
Test name
Test status
Simulation time 324397315332 ps
CPU time 1956.56 seconds
Started Jun 30 05:22:31 PM PDT 24
Finished Jun 30 05:55:09 PM PDT 24
Peak memory 226760 kb
Host smart-cd0afac9-5d65-45f3-a15d-78257c7108f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077315548 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1077315548
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.450972495
Short name T130
Test name
Test status
Simulation time 97566752 ps
CPU time 1.2 seconds
Started Jun 30 05:25:13 PM PDT 24
Finished Jun 30 05:25:15 PM PDT 24
Peak memory 218896 kb
Host smart-dfb370c7-017f-4d95-b66e-aa09dbeea6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450972495 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.450972495
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.2063738178
Short name T841
Test name
Test status
Simulation time 56534847 ps
CPU time 1.33 seconds
Started Jun 30 05:25:12 PM PDT 24
Finished Jun 30 05:25:14 PM PDT 24
Peak memory 217740 kb
Host smart-2b737b9a-feec-444b-b032-808a7960d1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063738178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2063738178
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.2749131721
Short name T677
Test name
Test status
Simulation time 71053658 ps
CPU time 1.14 seconds
Started Jun 30 05:25:15 PM PDT 24
Finished Jun 30 05:25:17 PM PDT 24
Peak memory 218968 kb
Host smart-0d56a7d1-4326-496b-934f-c4f2bdaaba3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749131721 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.2749131721
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.2213145146
Short name T784
Test name
Test status
Simulation time 35891328 ps
CPU time 1.37 seconds
Started Jun 30 05:25:15 PM PDT 24
Finished Jun 30 05:25:17 PM PDT 24
Peak memory 218904 kb
Host smart-c8c84b8b-c555-4c45-8fae-f18a48970c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213145146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2213145146
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.1369437452
Short name T613
Test name
Test status
Simulation time 29497971 ps
CPU time 1.33 seconds
Started Jun 30 05:25:11 PM PDT 24
Finished Jun 30 05:25:13 PM PDT 24
Peak memory 221108 kb
Host smart-e388b13d-6c0e-4b2f-b3be-2f774b19c847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369437452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.1369437452
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/133.edn_alert.1748675186
Short name T901
Test name
Test status
Simulation time 26755674 ps
CPU time 1.22 seconds
Started Jun 30 05:25:15 PM PDT 24
Finished Jun 30 05:25:17 PM PDT 24
Peak memory 218912 kb
Host smart-8365d463-36d8-4094-96c0-6ad0f38af0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748675186 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.1748675186
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.2470203949
Short name T614
Test name
Test status
Simulation time 45000495 ps
CPU time 1.13 seconds
Started Jun 30 05:25:15 PM PDT 24
Finished Jun 30 05:25:17 PM PDT 24
Peak memory 215496 kb
Host smart-5d9de011-4a5a-4d44-9657-c54ee757a7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470203949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2470203949
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.2985518194
Short name T701
Test name
Test status
Simulation time 30433339 ps
CPU time 1.34 seconds
Started Jun 30 05:25:15 PM PDT 24
Finished Jun 30 05:25:17 PM PDT 24
Peak memory 216016 kb
Host smart-8e36d855-0417-4e19-b098-a941455578eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985518194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.2985518194
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.3158612007
Short name T871
Test name
Test status
Simulation time 152181455 ps
CPU time 1.19 seconds
Started Jun 30 05:25:12 PM PDT 24
Finished Jun 30 05:25:14 PM PDT 24
Peak memory 219140 kb
Host smart-e63d173a-ba34-4a15-a3cd-877786a70c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158612007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3158612007
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.4134016703
Short name T263
Test name
Test status
Simulation time 27459854 ps
CPU time 1.26 seconds
Started Jun 30 05:25:15 PM PDT 24
Finished Jun 30 05:25:17 PM PDT 24
Peak memory 220232 kb
Host smart-276070c0-21de-47b2-996b-a1bf74974484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134016703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.4134016703
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.1604010265
Short name T734
Test name
Test status
Simulation time 159771877 ps
CPU time 1.83 seconds
Started Jun 30 05:25:12 PM PDT 24
Finished Jun 30 05:25:15 PM PDT 24
Peak memory 219324 kb
Host smart-2e32d28f-45a3-42a7-bda3-f6d9ae364f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604010265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1604010265
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.1724325709
Short name T268
Test name
Test status
Simulation time 32731943 ps
CPU time 1.3 seconds
Started Jun 30 05:25:13 PM PDT 24
Finished Jun 30 05:25:15 PM PDT 24
Peak memory 218884 kb
Host smart-75555a7f-132d-496b-80a0-4daa9368237f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724325709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1724325709
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/137.edn_alert.3159820046
Short name T941
Test name
Test status
Simulation time 88173474 ps
CPU time 1.36 seconds
Started Jun 30 05:25:13 PM PDT 24
Finished Jun 30 05:25:15 PM PDT 24
Peak memory 221160 kb
Host smart-6b6d9188-8a26-4865-98e8-bd9935c2d8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159820046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.3159820046
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.3082526074
Short name T468
Test name
Test status
Simulation time 83334443 ps
CPU time 1.59 seconds
Started Jun 30 05:25:12 PM PDT 24
Finished Jun 30 05:25:14 PM PDT 24
Peak memory 220620 kb
Host smart-e62fad85-f067-4e86-9c0f-bbc6b41fcd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082526074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3082526074
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2114281937
Short name T505
Test name
Test status
Simulation time 42244213 ps
CPU time 1.47 seconds
Started Jun 30 05:25:22 PM PDT 24
Finished Jun 30 05:25:25 PM PDT 24
Peak memory 218656 kb
Host smart-119937f4-ab41-41c4-8058-db2394a682fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114281937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2114281937
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.583654215
Short name T587
Test name
Test status
Simulation time 22213223 ps
CPU time 1.14 seconds
Started Jun 30 05:25:24 PM PDT 24
Finished Jun 30 05:25:26 PM PDT 24
Peak memory 219064 kb
Host smart-93105791-da7a-4cad-9e92-f5afe597ad64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583654215 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.583654215
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.1177285542
Short name T561
Test name
Test status
Simulation time 105500044 ps
CPU time 1.16 seconds
Started Jun 30 05:25:25 PM PDT 24
Finished Jun 30 05:25:27 PM PDT 24
Peak memory 220080 kb
Host smart-1b75b5dc-20b6-4915-8dbd-2788001e87aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177285542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1177285542
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2490126795
Short name T602
Test name
Test status
Simulation time 80558211 ps
CPU time 1.22 seconds
Started Jun 30 05:22:35 PM PDT 24
Finished Jun 30 05:22:37 PM PDT 24
Peak memory 221068 kb
Host smart-71d5a560-f0f5-44ca-8051-43a876a10f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490126795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2490126795
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.628346000
Short name T325
Test name
Test status
Simulation time 63298283 ps
CPU time 0.79 seconds
Started Jun 30 05:22:37 PM PDT 24
Finished Jun 30 05:22:38 PM PDT 24
Peak memory 206664 kb
Host smart-83e1b982-4e78-49b2-b01a-4d593ded9607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628346000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.628346000
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.10308823
Short name T969
Test name
Test status
Simulation time 17274997 ps
CPU time 0.84 seconds
Started Jun 30 05:22:37 PM PDT 24
Finished Jun 30 05:22:38 PM PDT 24
Peak memory 216648 kb
Host smart-68b8eb51-38b6-4c6d-a463-e56d2678f719
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10308823 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.10308823
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1487137382
Short name T794
Test name
Test status
Simulation time 89789438 ps
CPU time 1.02 seconds
Started Jun 30 05:22:38 PM PDT 24
Finished Jun 30 05:22:40 PM PDT 24
Peak memory 218360 kb
Host smart-cb9bfaf8-c50b-4c3d-a670-6453f75817d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487137382 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1487137382
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.525918009
Short name T133
Test name
Test status
Simulation time 56479268 ps
CPU time 1.02 seconds
Started Jun 30 05:22:38 PM PDT 24
Finished Jun 30 05:22:40 PM PDT 24
Peak memory 220880 kb
Host smart-232576ed-2f65-4229-9565-201a5360eb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525918009 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.525918009
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_intr.98781055
Short name T786
Test name
Test status
Simulation time 22134922 ps
CPU time 1.09 seconds
Started Jun 30 05:22:38 PM PDT 24
Finished Jun 30 05:22:40 PM PDT 24
Peak memory 215676 kb
Host smart-250f66c6-0790-4186-b849-ec2e1cf460b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98781055 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.98781055
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.1593987366
Short name T984
Test name
Test status
Simulation time 26587350 ps
CPU time 0.95 seconds
Started Jun 30 05:22:38 PM PDT 24
Finished Jun 30 05:22:39 PM PDT 24
Peak memory 215500 kb
Host smart-9223618a-3ee5-4d4f-bb5a-ad0dfa45378f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593987366 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1593987366
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.501835911
Short name T223
Test name
Test status
Simulation time 35782603624 ps
CPU time 410 seconds
Started Jun 30 05:22:38 PM PDT 24
Finished Jun 30 05:29:29 PM PDT 24
Peak memory 223980 kb
Host smart-4a0df7de-467f-4baa-9df9-0d292730bbd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501835911 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.501835911
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.3366516154
Short name T260
Test name
Test status
Simulation time 39161193 ps
CPU time 1.22 seconds
Started Jun 30 05:25:25 PM PDT 24
Finished Jun 30 05:25:27 PM PDT 24
Peak memory 218872 kb
Host smart-f1164824-d001-49f3-b70a-0e3b24b16664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366516154 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.3366516154
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/141.edn_alert.41185795
Short name T69
Test name
Test status
Simulation time 51413642 ps
CPU time 1.33 seconds
Started Jun 30 05:25:23 PM PDT 24
Finished Jun 30 05:25:26 PM PDT 24
Peak memory 215980 kb
Host smart-6a8513b0-b462-413e-bfb2-b32d99c56304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41185795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.41185795
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.3337410454
Short name T347
Test name
Test status
Simulation time 45032266 ps
CPU time 1.49 seconds
Started Jun 30 05:25:24 PM PDT 24
Finished Jun 30 05:25:27 PM PDT 24
Peak memory 217888 kb
Host smart-3c6d2cec-ebca-4fb1-961a-4a37c31470f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337410454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3337410454
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.2780132197
Short name T792
Test name
Test status
Simulation time 70724740 ps
CPU time 1.04 seconds
Started Jun 30 05:25:23 PM PDT 24
Finished Jun 30 05:25:25 PM PDT 24
Peak memory 219032 kb
Host smart-fe27484e-4646-4a84-a556-940cb892a4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780132197 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.2780132197
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.3648871553
Short name T509
Test name
Test status
Simulation time 208736002 ps
CPU time 2.47 seconds
Started Jun 30 05:25:25 PM PDT 24
Finished Jun 30 05:25:29 PM PDT 24
Peak memory 219788 kb
Host smart-b4cdea51-043d-4a4e-8897-99d07a713806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648871553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3648871553
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.2215531540
Short name T965
Test name
Test status
Simulation time 49520203 ps
CPU time 1.17 seconds
Started Jun 30 05:25:23 PM PDT 24
Finished Jun 30 05:25:25 PM PDT 24
Peak memory 219988 kb
Host smart-a00b0fb5-2184-4a3e-8324-0204d789b689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215531540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.2215531540
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.658403115
Short name T401
Test name
Test status
Simulation time 85232967 ps
CPU time 1.29 seconds
Started Jun 30 05:25:23 PM PDT 24
Finished Jun 30 05:25:26 PM PDT 24
Peak memory 218888 kb
Host smart-3dcff58b-81c5-40fc-bdb4-61373437414f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658403115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.658403115
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.1423069493
Short name T148
Test name
Test status
Simulation time 128563896 ps
CPU time 1.3 seconds
Started Jun 30 05:25:23 PM PDT 24
Finished Jun 30 05:25:25 PM PDT 24
Peak memory 220868 kb
Host smart-13d681e6-60d7-4fca-98ab-04219a2926dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423069493 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.1423069493
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.2391366590
Short name T785
Test name
Test status
Simulation time 85441983 ps
CPU time 1.5 seconds
Started Jun 30 05:25:25 PM PDT 24
Finished Jun 30 05:25:28 PM PDT 24
Peak memory 218896 kb
Host smart-80c104b9-58c1-4240-b8a0-b5b615aba214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391366590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2391366590
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.1303612743
Short name T812
Test name
Test status
Simulation time 35971470 ps
CPU time 1.12 seconds
Started Jun 30 05:25:22 PM PDT 24
Finished Jun 30 05:25:25 PM PDT 24
Peak memory 219176 kb
Host smart-27b2324b-efea-44d2-9a4f-7c4659b61a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303612743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.1303612743
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2072849633
Short name T435
Test name
Test status
Simulation time 159348189 ps
CPU time 2.15 seconds
Started Jun 30 05:25:23 PM PDT 24
Finished Jun 30 05:25:27 PM PDT 24
Peak memory 220420 kb
Host smart-7039de79-e58c-432b-8891-fd25cc4d3b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072849633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2072849633
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.827079388
Short name T767
Test name
Test status
Simulation time 51687816 ps
CPU time 1.25 seconds
Started Jun 30 05:25:24 PM PDT 24
Finished Jun 30 05:25:26 PM PDT 24
Peak memory 219540 kb
Host smart-05be2656-ea6b-4ab3-808c-5aead2a43cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827079388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.827079388
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3405605481
Short name T453
Test name
Test status
Simulation time 21084276 ps
CPU time 1.18 seconds
Started Jun 30 05:25:22 PM PDT 24
Finished Jun 30 05:25:24 PM PDT 24
Peak memory 220336 kb
Host smart-d9cc7dc6-a867-4e42-8a08-65d820e54ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405605481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3405605481
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.1054061474
Short name T872
Test name
Test status
Simulation time 44831735 ps
CPU time 1.28 seconds
Started Jun 30 05:25:25 PM PDT 24
Finished Jun 30 05:25:27 PM PDT 24
Peak memory 219184 kb
Host smart-4e21c521-4073-43ae-b9ed-aaec0a251539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054061474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.1054061474
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.3377308442
Short name T886
Test name
Test status
Simulation time 83522636 ps
CPU time 1.07 seconds
Started Jun 30 05:25:23 PM PDT 24
Finished Jun 30 05:25:25 PM PDT 24
Peak memory 218736 kb
Host smart-6d9f1987-b2c0-462d-93ce-27d8df763f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377308442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3377308442
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.1223745076
Short name T209
Test name
Test status
Simulation time 75075889 ps
CPU time 1.22 seconds
Started Jun 30 05:25:22 PM PDT 24
Finished Jun 30 05:25:25 PM PDT 24
Peak memory 220040 kb
Host smart-fcf6f129-cca4-4498-92f4-2a8cb53644f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223745076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.1223745076
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert.2355735289
Short name T567
Test name
Test status
Simulation time 41221789 ps
CPU time 1.14 seconds
Started Jun 30 05:22:38 PM PDT 24
Finished Jun 30 05:22:40 PM PDT 24
Peak memory 218656 kb
Host smart-c318f59f-8ea6-4f59-9107-07d7d511b4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355735289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2355735289
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2123035575
Short name T399
Test name
Test status
Simulation time 19243181 ps
CPU time 0.91 seconds
Started Jun 30 05:22:43 PM PDT 24
Finished Jun 30 05:22:45 PM PDT 24
Peak memory 207340 kb
Host smart-b7ed50a4-4a34-45f1-b642-e9a1ed7b5082
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123035575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2123035575
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.352881395
Short name T175
Test name
Test status
Simulation time 10733238 ps
CPU time 0.84 seconds
Started Jun 30 05:22:35 PM PDT 24
Finished Jun 30 05:22:36 PM PDT 24
Peak memory 216480 kb
Host smart-e73b1569-8fbb-494b-aa6f-a77adeafc933
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352881395 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.352881395
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2687679085
Short name T806
Test name
Test status
Simulation time 99239598 ps
CPU time 1.1 seconds
Started Jun 30 05:22:45 PM PDT 24
Finished Jun 30 05:22:47 PM PDT 24
Peak memory 217076 kb
Host smart-fdcc2014-e8f1-42dd-bf77-a9d843a72c40
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687679085 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2687679085
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.161890920
Short name T521
Test name
Test status
Simulation time 37605253 ps
CPU time 0.88 seconds
Started Jun 30 05:22:37 PM PDT 24
Finished Jun 30 05:22:38 PM PDT 24
Peak memory 218364 kb
Host smart-8a196ad9-416c-44e3-b6e8-46a6eb57dd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161890920 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.161890920
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.4247691093
Short name T298
Test name
Test status
Simulation time 53291754 ps
CPU time 1.54 seconds
Started Jun 30 05:22:35 PM PDT 24
Finished Jun 30 05:22:37 PM PDT 24
Peak memory 219056 kb
Host smart-179af71f-a8a7-43a1-a81d-449867153def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247691093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.4247691093
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2074960307
Short name T914
Test name
Test status
Simulation time 38602926 ps
CPU time 0.91 seconds
Started Jun 30 05:22:39 PM PDT 24
Finished Jun 30 05:22:42 PM PDT 24
Peak memory 216152 kb
Host smart-455e8958-d7c0-418f-a325-a52da2bdfc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074960307 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2074960307
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2285555351
Short name T320
Test name
Test status
Simulation time 47043123 ps
CPU time 0.96 seconds
Started Jun 30 05:22:37 PM PDT 24
Finished Jun 30 05:22:38 PM PDT 24
Peak memory 215628 kb
Host smart-4b535444-a6b2-4e06-a9f8-e5ea58d8fbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285555351 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2285555351
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.4134359956
Short name T622
Test name
Test status
Simulation time 193387240 ps
CPU time 4.19 seconds
Started Jun 30 05:22:36 PM PDT 24
Finished Jun 30 05:22:40 PM PDT 24
Peak memory 215632 kb
Host smart-ffc2c108-280f-49ab-afb5-ed066ffcd5a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134359956 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.4134359956
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2379715793
Short name T310
Test name
Test status
Simulation time 72497077791 ps
CPU time 1628.58 seconds
Started Jun 30 05:22:37 PM PDT 24
Finished Jun 30 05:49:46 PM PDT 24
Peak memory 224664 kb
Host smart-655eb6cc-e694-4841-89a5-e7b3164d6d1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379715793 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2379715793
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.3578357642
Short name T655
Test name
Test status
Simulation time 57517582 ps
CPU time 1.39 seconds
Started Jun 30 05:25:25 PM PDT 24
Finished Jun 30 05:25:28 PM PDT 24
Peak memory 219024 kb
Host smart-32e6d77b-c28e-4bd6-afa2-40d7b428c0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578357642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3578357642
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.2936391922
Short name T27
Test name
Test status
Simulation time 394120349 ps
CPU time 1.22 seconds
Started Jun 30 05:25:22 PM PDT 24
Finished Jun 30 05:25:24 PM PDT 24
Peak memory 220760 kb
Host smart-ef47728d-143b-4ca2-b41a-3c29d7bd08fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936391922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.2936391922
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.121817339
Short name T427
Test name
Test status
Simulation time 51873105 ps
CPU time 1.56 seconds
Started Jun 30 05:25:26 PM PDT 24
Finished Jun 30 05:25:28 PM PDT 24
Peak memory 218744 kb
Host smart-71329ffa-bb53-466a-8368-ca7b5febd222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121817339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.121817339
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.205450730
Short name T574
Test name
Test status
Simulation time 33580288 ps
CPU time 1.21 seconds
Started Jun 30 05:25:24 PM PDT 24
Finished Jun 30 05:25:26 PM PDT 24
Peak memory 219336 kb
Host smart-23c90242-5321-4a6b-b273-13af77157221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205450730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.205450730
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.1286864263
Short name T312
Test name
Test status
Simulation time 67155966 ps
CPU time 2.41 seconds
Started Jun 30 05:25:24 PM PDT 24
Finished Jun 30 05:25:28 PM PDT 24
Peak memory 219100 kb
Host smart-33939ca5-fef2-46ce-8444-81d4a104e5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286864263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1286864263
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.2497494978
Short name T779
Test name
Test status
Simulation time 49862882 ps
CPU time 1.32 seconds
Started Jun 30 05:25:23 PM PDT 24
Finished Jun 30 05:25:25 PM PDT 24
Peak memory 218976 kb
Host smart-4b6886f2-2bac-4f36-9f64-1b51b23f4bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497494978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2497494978
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.1726363039
Short name T951
Test name
Test status
Simulation time 26422553 ps
CPU time 1.26 seconds
Started Jun 30 05:25:22 PM PDT 24
Finished Jun 30 05:25:24 PM PDT 24
Peak memory 219772 kb
Host smart-e9d8c987-c9ab-4540-b2d8-e36cbb765290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726363039 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.1726363039
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.326936838
Short name T54
Test name
Test status
Simulation time 45671087 ps
CPU time 1.61 seconds
Started Jun 30 05:25:23 PM PDT 24
Finished Jun 30 05:25:25 PM PDT 24
Peak memory 218748 kb
Host smart-4faaf3b1-1807-4ef2-aa26-b3d0d7d27277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326936838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.326936838
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.295744435
Short name T67
Test name
Test status
Simulation time 30137773 ps
CPU time 1.29 seconds
Started Jun 30 05:25:24 PM PDT 24
Finished Jun 30 05:25:26 PM PDT 24
Peak memory 220996 kb
Host smart-f70dc3c8-3819-46e2-82de-8740fd351ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295744435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.295744435
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1160798506
Short name T626
Test name
Test status
Simulation time 88874714 ps
CPU time 2.9 seconds
Started Jun 30 05:25:23 PM PDT 24
Finished Jun 30 05:25:27 PM PDT 24
Peak memory 220720 kb
Host smart-f5e83a32-ae6f-4600-a603-c951f412538a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160798506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1160798506
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.3406834649
Short name T415
Test name
Test status
Simulation time 51321837 ps
CPU time 1.16 seconds
Started Jun 30 05:25:33 PM PDT 24
Finished Jun 30 05:25:35 PM PDT 24
Peak memory 215968 kb
Host smart-d980dd37-0257-4920-8538-de613edba43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406834649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.3406834649
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/157.edn_alert.1706571316
Short name T903
Test name
Test status
Simulation time 24378041 ps
CPU time 1.25 seconds
Started Jun 30 05:25:29 PM PDT 24
Finished Jun 30 05:25:31 PM PDT 24
Peak memory 220056 kb
Host smart-2dbeb885-d47a-4fb3-8b1e-4ba3088f8a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706571316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.1706571316
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.870520842
Short name T412
Test name
Test status
Simulation time 50480238 ps
CPU time 1.9 seconds
Started Jun 30 05:25:32 PM PDT 24
Finished Jun 30 05:25:35 PM PDT 24
Peak memory 218636 kb
Host smart-17ec9078-9de7-448b-9607-a52ecf2d93d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870520842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.870520842
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.4190215940
Short name T332
Test name
Test status
Simulation time 56336494 ps
CPU time 1.41 seconds
Started Jun 30 05:25:34 PM PDT 24
Finished Jun 30 05:25:36 PM PDT 24
Peak memory 217724 kb
Host smart-8e079a13-bdbc-4ce8-a52e-392c03b16b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190215940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.4190215940
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.228416949
Short name T659
Test name
Test status
Simulation time 241845521 ps
CPU time 1.32 seconds
Started Jun 30 05:25:33 PM PDT 24
Finished Jun 30 05:25:35 PM PDT 24
Peak memory 219892 kb
Host smart-3429022e-b36e-4c7d-97f3-e75ec7df5553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228416949 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.228416949
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.391081129
Short name T588
Test name
Test status
Simulation time 28538685 ps
CPU time 1.29 seconds
Started Jun 30 05:25:30 PM PDT 24
Finished Jun 30 05:25:31 PM PDT 24
Peak memory 219952 kb
Host smart-6f7d6f44-badc-4bcf-89b4-4b5f05650037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391081129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.391081129
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2845284168
Short name T876
Test name
Test status
Simulation time 57721183 ps
CPU time 1.22 seconds
Started Jun 30 05:22:43 PM PDT 24
Finished Jun 30 05:22:44 PM PDT 24
Peak memory 218876 kb
Host smart-090de5d3-4f09-4ee5-8ed5-2724d96eaa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845284168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2845284168
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.783040773
Short name T911
Test name
Test status
Simulation time 45501256 ps
CPU time 0.91 seconds
Started Jun 30 05:22:41 PM PDT 24
Finished Jun 30 05:22:43 PM PDT 24
Peak memory 215208 kb
Host smart-9cb44e20-cf8a-41f0-8be0-47465b38f39d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783040773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.783040773
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.699309499
Short name T715
Test name
Test status
Simulation time 37385110 ps
CPU time 0.82 seconds
Started Jun 30 05:22:45 PM PDT 24
Finished Jun 30 05:22:46 PM PDT 24
Peak memory 216204 kb
Host smart-0af7616a-7d1b-4d5c-b457-222b79368719
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699309499 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.699309499
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3324262359
Short name T135
Test name
Test status
Simulation time 115955874 ps
CPU time 1.22 seconds
Started Jun 30 05:22:42 PM PDT 24
Finished Jun 30 05:22:44 PM PDT 24
Peak memory 217272 kb
Host smart-b9bf9f56-e081-437c-8670-7780e6eb5e53
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324262359 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3324262359
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1742207622
Short name T110
Test name
Test status
Simulation time 24637017 ps
CPU time 0.98 seconds
Started Jun 30 05:22:44 PM PDT 24
Finished Jun 30 05:22:46 PM PDT 24
Peak memory 220060 kb
Host smart-70cef807-1513-49dc-820e-d03e744c9008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742207622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1742207622
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3498932119
Short name T814
Test name
Test status
Simulation time 71942779 ps
CPU time 1.27 seconds
Started Jun 30 05:22:43 PM PDT 24
Finished Jun 30 05:22:45 PM PDT 24
Peak memory 217564 kb
Host smart-771a87eb-4a70-4749-9710-b863f46c8a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498932119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3498932119
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1391955638
Short name T760
Test name
Test status
Simulation time 41083291 ps
CPU time 1.02 seconds
Started Jun 30 05:22:42 PM PDT 24
Finished Jun 30 05:22:43 PM PDT 24
Peak memory 215824 kb
Host smart-4920cc13-94d5-431e-9901-642bfa36d08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391955638 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1391955638
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2774468428
Short name T861
Test name
Test status
Simulation time 54763797 ps
CPU time 0.93 seconds
Started Jun 30 05:22:45 PM PDT 24
Finished Jun 30 05:22:47 PM PDT 24
Peak memory 215540 kb
Host smart-d09201ff-cc24-4772-bfea-1cfad8f9830d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774468428 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2774468428
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2649466063
Short name T63
Test name
Test status
Simulation time 662332128 ps
CPU time 4.22 seconds
Started Jun 30 05:22:40 PM PDT 24
Finished Jun 30 05:22:45 PM PDT 24
Peak memory 217680 kb
Host smart-8aa60f34-6aa9-4257-add6-1e6b3c65147f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649466063 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2649466063
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3425389321
Short name T943
Test name
Test status
Simulation time 509132848652 ps
CPU time 2034.5 seconds
Started Jun 30 05:22:43 PM PDT 24
Finished Jun 30 05:56:38 PM PDT 24
Peak memory 229868 kb
Host smart-44d69903-6626-4108-9194-a683c03e7b0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425389321 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3425389321
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.4095548654
Short name T164
Test name
Test status
Simulation time 28757345 ps
CPU time 1.12 seconds
Started Jun 30 05:25:32 PM PDT 24
Finished Jun 30 05:25:33 PM PDT 24
Peak memory 220260 kb
Host smart-f53ef97e-11e7-4891-8832-26f42ff93b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095548654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.4095548654
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1474500223
Short name T417
Test name
Test status
Simulation time 33135181 ps
CPU time 1.25 seconds
Started Jun 30 05:25:30 PM PDT 24
Finished Jun 30 05:25:31 PM PDT 24
Peak memory 217492 kb
Host smart-45cedbe8-6c57-4fa1-bbc6-abea0ebdee4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474500223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1474500223
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.2409965515
Short name T233
Test name
Test status
Simulation time 25647360 ps
CPU time 1.25 seconds
Started Jun 30 05:25:32 PM PDT 24
Finished Jun 30 05:25:35 PM PDT 24
Peak memory 218844 kb
Host smart-55ee80c6-585c-4d31-8381-a9b2b0073dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409965515 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.2409965515
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/162.edn_alert.2459496495
Short name T475
Test name
Test status
Simulation time 29896104 ps
CPU time 1.05 seconds
Started Jun 30 05:25:33 PM PDT 24
Finished Jun 30 05:25:35 PM PDT 24
Peak memory 219096 kb
Host smart-827cc0e1-ee75-459a-95b5-40db0b710be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459496495 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.2459496495
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.1470047301
Short name T286
Test name
Test status
Simulation time 62863967 ps
CPU time 1.06 seconds
Started Jun 30 05:25:31 PM PDT 24
Finished Jun 30 05:25:32 PM PDT 24
Peak memory 217600 kb
Host smart-ca8d8010-1a17-4382-b9d6-e16d06fe365c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470047301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1470047301
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.567975537
Short name T830
Test name
Test status
Simulation time 66383898 ps
CPU time 1.12 seconds
Started Jun 30 05:25:34 PM PDT 24
Finished Jun 30 05:25:36 PM PDT 24
Peak memory 218968 kb
Host smart-384faf43-ad27-4aeb-b0fe-33b99995663e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567975537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.567975537
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/164.edn_alert.340769305
Short name T206
Test name
Test status
Simulation time 26751935 ps
CPU time 1.23 seconds
Started Jun 30 05:25:32 PM PDT 24
Finished Jun 30 05:25:34 PM PDT 24
Peak memory 220068 kb
Host smart-915f350c-8ab3-4b85-8052-b08ca01677c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340769305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.340769305
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.3845153567
Short name T307
Test name
Test status
Simulation time 69692331 ps
CPU time 2.47 seconds
Started Jun 30 05:25:30 PM PDT 24
Finished Jun 30 05:25:33 PM PDT 24
Peak memory 220480 kb
Host smart-d3614895-2aa8-4389-9d27-29b90f201981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845153567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3845153567
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.4089922032
Short name T638
Test name
Test status
Simulation time 39731463 ps
CPU time 1.1 seconds
Started Jun 30 05:25:32 PM PDT 24
Finished Jun 30 05:25:34 PM PDT 24
Peak memory 218888 kb
Host smart-bb2788f6-a6e5-4c5d-9698-9148294f7018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089922032 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.4089922032
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1522415952
Short name T802
Test name
Test status
Simulation time 35326740 ps
CPU time 1.31 seconds
Started Jun 30 05:25:31 PM PDT 24
Finished Jun 30 05:25:33 PM PDT 24
Peak memory 217596 kb
Host smart-f7e4b5f0-7c98-4e21-9a17-885693d64b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522415952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1522415952
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.4241205001
Short name T152
Test name
Test status
Simulation time 46957058 ps
CPU time 1.27 seconds
Started Jun 30 05:25:32 PM PDT 24
Finished Jun 30 05:25:34 PM PDT 24
Peak memory 218860 kb
Host smart-dcd203a6-48c4-478f-b65f-c9bf5f91bc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241205001 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.4241205001
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.2251825774
Short name T271
Test name
Test status
Simulation time 60649330 ps
CPU time 1.33 seconds
Started Jun 30 05:25:31 PM PDT 24
Finished Jun 30 05:25:33 PM PDT 24
Peak memory 219064 kb
Host smart-69d9a94f-d83f-4826-a130-6f96b8e86dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251825774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2251825774
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.1949972813
Short name T153
Test name
Test status
Simulation time 28846180 ps
CPU time 1.29 seconds
Started Jun 30 05:25:33 PM PDT 24
Finished Jun 30 05:25:35 PM PDT 24
Peak memory 216012 kb
Host smart-cf3237db-4a67-4ca7-a87a-9192c533b2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949972813 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1949972813
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.1744574247
Short name T354
Test name
Test status
Simulation time 27946066 ps
CPU time 1.42 seconds
Started Jun 30 05:25:34 PM PDT 24
Finished Jun 30 05:25:36 PM PDT 24
Peak memory 219152 kb
Host smart-86c751dc-d959-49de-8276-5b51801f06b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744574247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1744574247
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.4085084740
Short name T630
Test name
Test status
Simulation time 228774320 ps
CPU time 1.2 seconds
Started Jun 30 05:25:30 PM PDT 24
Finished Jun 30 05:25:32 PM PDT 24
Peak memory 215924 kb
Host smart-185d817d-6fe5-4d9c-94a3-53d059a7e4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085084740 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.4085084740
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.3353854639
Short name T299
Test name
Test status
Simulation time 8767083561 ps
CPU time 92.81 seconds
Started Jun 30 05:25:33 PM PDT 24
Finished Jun 30 05:27:07 PM PDT 24
Peak memory 220956 kb
Host smart-dc03d956-6ef8-4d8c-8645-8d282c37f712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353854639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3353854639
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.1757898532
Short name T269
Test name
Test status
Simulation time 24615113 ps
CPU time 1.23 seconds
Started Jun 30 05:25:31 PM PDT 24
Finished Jun 30 05:25:33 PM PDT 24
Peak memory 218888 kb
Host smart-e99d2e8e-e9d8-4ab5-bc4d-8aa13276ceef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757898532 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.1757898532
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.1239548690
Short name T907
Test name
Test status
Simulation time 97852668 ps
CPU time 1.36 seconds
Started Jun 30 05:25:31 PM PDT 24
Finished Jun 30 05:25:33 PM PDT 24
Peak memory 217628 kb
Host smart-b45bc63b-0d5c-4f7a-8c2b-8cf4527431b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239548690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1239548690
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.381972028
Short name T177
Test name
Test status
Simulation time 25157269 ps
CPU time 1.17 seconds
Started Jun 30 05:22:50 PM PDT 24
Finished Jun 30 05:22:51 PM PDT 24
Peak memory 220156 kb
Host smart-8b57dcf0-dd64-490f-8719-448cbb53261a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381972028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.381972028
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2817619105
Short name T910
Test name
Test status
Simulation time 22460768 ps
CPU time 0.86 seconds
Started Jun 30 05:22:54 PM PDT 24
Finished Jun 30 05:22:55 PM PDT 24
Peak memory 215312 kb
Host smart-b716e416-1d8a-41a8-84d3-4d45d70a4f93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817619105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2817619105
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_err.2530550815
Short name T878
Test name
Test status
Simulation time 32010807 ps
CPU time 1.14 seconds
Started Jun 30 05:22:54 PM PDT 24
Finished Jun 30 05:22:55 PM PDT 24
Peak memory 217664 kb
Host smart-8a918669-b2b2-43e0-bb68-ca90d1daa5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530550815 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2530550815
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3420189933
Short name T849
Test name
Test status
Simulation time 48445763 ps
CPU time 1.11 seconds
Started Jun 30 05:22:47 PM PDT 24
Finished Jun 30 05:22:49 PM PDT 24
Peak memory 217548 kb
Host smart-e8073e54-2382-4a1b-a1c3-1bd4fe01db04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420189933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3420189933
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.339892786
Short name T483
Test name
Test status
Simulation time 25358716 ps
CPU time 1.06 seconds
Started Jun 30 05:22:49 PM PDT 24
Finished Jun 30 05:22:50 PM PDT 24
Peak memory 224200 kb
Host smart-64c0037d-7cfe-4e46-8ae4-90106385ebc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339892786 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.339892786
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.900583807
Short name T870
Test name
Test status
Simulation time 16267846 ps
CPU time 1.02 seconds
Started Jun 30 05:22:43 PM PDT 24
Finished Jun 30 05:22:45 PM PDT 24
Peak memory 215592 kb
Host smart-e3f31f5c-b472-4721-9f3a-0c718f3526e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900583807 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.900583807
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1024945250
Short name T848
Test name
Test status
Simulation time 159565408 ps
CPU time 1.47 seconds
Started Jun 30 05:22:48 PM PDT 24
Finished Jun 30 05:22:51 PM PDT 24
Peak memory 207492 kb
Host smart-7f388d26-80c9-4791-8fe7-27d62608761e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024945250 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1024945250
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3422093445
Short name T684
Test name
Test status
Simulation time 343410108831 ps
CPU time 1887.88 seconds
Started Jun 30 05:22:51 PM PDT 24
Finished Jun 30 05:54:19 PM PDT 24
Peak memory 225948 kb
Host smart-ceddcb2e-bbea-498f-9300-0a9f5c3709fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422093445 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3422093445
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.527393677
Short name T391
Test name
Test status
Simulation time 73629099 ps
CPU time 1.09 seconds
Started Jun 30 05:25:34 PM PDT 24
Finished Jun 30 05:25:36 PM PDT 24
Peak memory 218708 kb
Host smart-093aa26f-99f6-4e33-a16b-e739308a91d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527393677 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.527393677
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.2360865868
Short name T11
Test name
Test status
Simulation time 38719115 ps
CPU time 1.45 seconds
Started Jun 30 05:25:32 PM PDT 24
Finished Jun 30 05:25:33 PM PDT 24
Peak memory 220260 kb
Host smart-a2659f0e-ad29-4124-8d2c-401518ab9e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360865868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2360865868
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.2588000059
Short name T95
Test name
Test status
Simulation time 27405298 ps
CPU time 1.28 seconds
Started Jun 30 05:25:32 PM PDT 24
Finished Jun 30 05:25:34 PM PDT 24
Peak memory 219412 kb
Host smart-6e06d2bd-932a-4658-b217-f4fe1d8554c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588000059 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.2588000059
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.2698506731
Short name T499
Test name
Test status
Simulation time 56698052 ps
CPU time 1.24 seconds
Started Jun 30 05:25:32 PM PDT 24
Finished Jun 30 05:25:35 PM PDT 24
Peak memory 218672 kb
Host smart-2d9b2751-516f-48d5-8cc8-4a5d3ee85240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698506731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2698506731
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.587328516
Short name T105
Test name
Test status
Simulation time 81155275 ps
CPU time 1.2 seconds
Started Jun 30 05:25:35 PM PDT 24
Finished Jun 30 05:25:36 PM PDT 24
Peak memory 219900 kb
Host smart-98f6dfc0-3bff-46be-b4b7-53c986719f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587328516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.587328516
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.3847528657
Short name T770
Test name
Test status
Simulation time 40866066 ps
CPU time 1.44 seconds
Started Jun 30 05:25:33 PM PDT 24
Finished Jun 30 05:25:35 PM PDT 24
Peak memory 218620 kb
Host smart-ba43a026-3386-488a-9309-c711f6c5d2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847528657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3847528657
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.1030967518
Short name T724
Test name
Test status
Simulation time 29828600 ps
CPU time 1.3 seconds
Started Jun 30 05:25:33 PM PDT 24
Finished Jun 30 05:25:35 PM PDT 24
Peak memory 221072 kb
Host smart-c9357c1e-6ae3-416d-8435-fdf750059554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030967518 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.1030967518
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.3260552990
Short name T541
Test name
Test status
Simulation time 117685675 ps
CPU time 1.08 seconds
Started Jun 30 05:25:34 PM PDT 24
Finished Jun 30 05:25:36 PM PDT 24
Peak memory 217592 kb
Host smart-61a0452d-5ae7-4637-866c-3b9cbbfcb8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260552990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3260552990
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.390434639
Short name T959
Test name
Test status
Simulation time 81631055 ps
CPU time 1.17 seconds
Started Jun 30 05:25:31 PM PDT 24
Finished Jun 30 05:25:33 PM PDT 24
Peak memory 219944 kb
Host smart-09bb7f96-1f49-42cf-ba18-9f524802b1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390434639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.390434639
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.4248735743
Short name T775
Test name
Test status
Simulation time 65961900 ps
CPU time 1.03 seconds
Started Jun 30 05:25:33 PM PDT 24
Finished Jun 30 05:25:35 PM PDT 24
Peak memory 217612 kb
Host smart-558ac330-9d7c-4006-a9d9-592ac3695c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248735743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.4248735743
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3757476499
Short name T262
Test name
Test status
Simulation time 104923752 ps
CPU time 0.98 seconds
Started Jun 30 05:25:33 PM PDT 24
Finished Jun 30 05:25:35 PM PDT 24
Peak memory 218848 kb
Host smart-6c60a053-dd76-4fb6-9e4c-b23aa573ef05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757476499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3757476499
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.57651059
Short name T927
Test name
Test status
Simulation time 186264748 ps
CPU time 2.63 seconds
Started Jun 30 05:25:32 PM PDT 24
Finished Jun 30 05:25:35 PM PDT 24
Peak memory 219248 kb
Host smart-d827ac65-0f1b-4d5d-a683-a5393d535b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57651059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.57651059
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.395530011
Short name T261
Test name
Test status
Simulation time 70530267 ps
CPU time 1.03 seconds
Started Jun 30 05:25:34 PM PDT 24
Finished Jun 30 05:25:36 PM PDT 24
Peak memory 221052 kb
Host smart-2d50bf9b-dddd-449a-894f-929f74bdf9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395530011 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.395530011
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.3927826645
Short name T563
Test name
Test status
Simulation time 91234033 ps
CPU time 1.25 seconds
Started Jun 30 05:25:37 PM PDT 24
Finished Jun 30 05:25:39 PM PDT 24
Peak memory 219032 kb
Host smart-08fd19bf-dbf0-43c7-bb61-4101ff95a18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927826645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3927826645
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.4009512848
Short name T656
Test name
Test status
Simulation time 79506526 ps
CPU time 1.78 seconds
Started Jun 30 05:25:45 PM PDT 24
Finished Jun 30 05:25:48 PM PDT 24
Peak memory 219128 kb
Host smart-c867d60a-bb4e-43b5-a503-872c1ed8094c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009512848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.4009512848
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.1201078224
Short name T611
Test name
Test status
Simulation time 193011222 ps
CPU time 1.3 seconds
Started Jun 30 05:25:37 PM PDT 24
Finished Jun 30 05:25:39 PM PDT 24
Peak memory 218784 kb
Host smart-e8efc8b4-d144-4b19-8c9e-c54c8b8fab88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201078224 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.1201078224
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.2676514322
Short name T540
Test name
Test status
Simulation time 108019292 ps
CPU time 2.3 seconds
Started Jun 30 05:25:40 PM PDT 24
Finished Jun 30 05:25:42 PM PDT 24
Peak memory 220688 kb
Host smart-3ffbd408-3359-4960-9447-2ea91fceb68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676514322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2676514322
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.4202694630
Short name T340
Test name
Test status
Simulation time 53715273 ps
CPU time 1.28 seconds
Started Jun 30 05:25:37 PM PDT 24
Finished Jun 30 05:25:39 PM PDT 24
Peak memory 220284 kb
Host smart-7b3063f6-a22f-4615-bfa6-3b68f4e9a40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202694630 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.4202694630
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.994677394
Short name T562
Test name
Test status
Simulation time 52168409 ps
CPU time 1.18 seconds
Started Jun 30 05:25:38 PM PDT 24
Finished Jun 30 05:25:40 PM PDT 24
Peak memory 217468 kb
Host smart-01cb86ee-bd6e-44be-901c-fffae9b2beb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994677394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.994677394
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.463760123
Short name T865
Test name
Test status
Simulation time 79259116 ps
CPU time 1.21 seconds
Started Jun 30 05:22:48 PM PDT 24
Finished Jun 30 05:22:50 PM PDT 24
Peak memory 219584 kb
Host smart-273a4f70-69ca-4b13-b355-8f97f72665f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463760123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.463760123
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.734200240
Short name T93
Test name
Test status
Simulation time 40537719 ps
CPU time 0.82 seconds
Started Jun 30 05:23:03 PM PDT 24
Finished Jun 30 05:23:05 PM PDT 24
Peak memory 206576 kb
Host smart-36274d25-433a-4240-b9b7-e79dea9db80a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734200240 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.734200240
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2318393202
Short name T727
Test name
Test status
Simulation time 65850666 ps
CPU time 0.9 seconds
Started Jun 30 05:22:50 PM PDT 24
Finished Jun 30 05:22:52 PM PDT 24
Peak memory 216668 kb
Host smart-038d76fb-16ca-4639-9bbb-3ea33013e74d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318393202 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2318393202
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3992676607
Short name T605
Test name
Test status
Simulation time 40961691 ps
CPU time 1.02 seconds
Started Jun 30 05:22:48 PM PDT 24
Finished Jun 30 05:22:49 PM PDT 24
Peak memory 217136 kb
Host smart-0641a68e-5d58-4a64-921b-71b763fa4a17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992676607 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3992676607
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.3749112798
Short name T766
Test name
Test status
Simulation time 18866416 ps
CPU time 1.17 seconds
Started Jun 30 05:22:52 PM PDT 24
Finished Jun 30 05:22:53 PM PDT 24
Peak memory 218976 kb
Host smart-1e7a6c62-db7d-466b-89d7-4df50972fac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749112798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3749112798
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2149975534
Short name T554
Test name
Test status
Simulation time 77179355 ps
CPU time 1.81 seconds
Started Jun 30 05:22:54 PM PDT 24
Finished Jun 30 05:22:56 PM PDT 24
Peak memory 218832 kb
Host smart-2d5eebde-235e-49dc-9ba4-1e161abe1018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149975534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2149975534
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.3753266447
Short name T732
Test name
Test status
Simulation time 18142594 ps
CPU time 1.03 seconds
Started Jun 30 05:22:52 PM PDT 24
Finished Jun 30 05:22:53 PM PDT 24
Peak memory 215664 kb
Host smart-4cea698c-916d-49ae-8a0a-12b974aecb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753266447 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3753266447
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3193435690
Short name T782
Test name
Test status
Simulation time 394686395 ps
CPU time 2.76 seconds
Started Jun 30 05:22:50 PM PDT 24
Finished Jun 30 05:22:53 PM PDT 24
Peak memory 217492 kb
Host smart-ce40fdca-3822-4a26-a157-015cc619c450
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193435690 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3193435690
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1759218311
Short name T335
Test name
Test status
Simulation time 67490152904 ps
CPU time 848.85 seconds
Started Jun 30 05:22:48 PM PDT 24
Finished Jun 30 05:36:58 PM PDT 24
Peak memory 220832 kb
Host smart-eba6a3ac-517d-40a9-b527-0540d6c5ba2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759218311 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1759218311
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.1185994025
Short name T982
Test name
Test status
Simulation time 24525745 ps
CPU time 1.22 seconds
Started Jun 30 05:25:40 PM PDT 24
Finished Jun 30 05:25:42 PM PDT 24
Peak memory 220360 kb
Host smart-cd1818a3-14f2-4d03-9300-949ed3257e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185994025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.1185994025
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.1083299610
Short name T485
Test name
Test status
Simulation time 62319715 ps
CPU time 1.26 seconds
Started Jun 30 05:25:45 PM PDT 24
Finished Jun 30 05:25:47 PM PDT 24
Peak memory 215656 kb
Host smart-6de10df4-7df6-4e40-9b93-e3203eaf112d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083299610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1083299610
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.553303471
Short name T542
Test name
Test status
Simulation time 23976914 ps
CPU time 1.19 seconds
Started Jun 30 05:25:38 PM PDT 24
Finished Jun 30 05:25:39 PM PDT 24
Peak memory 221192 kb
Host smart-a5ea4cfa-50f4-4b47-94a9-87c37763ddda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553303471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.553303471
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.2029918147
Short name T230
Test name
Test status
Simulation time 49997622 ps
CPU time 1.78 seconds
Started Jun 30 05:25:37 PM PDT 24
Finished Jun 30 05:25:40 PM PDT 24
Peak memory 217832 kb
Host smart-9fe50d68-0804-4b42-9ab3-b72ce2ea73a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029918147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2029918147
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.2938560020
Short name T576
Test name
Test status
Simulation time 79020468 ps
CPU time 1.12 seconds
Started Jun 30 05:25:40 PM PDT 24
Finished Jun 30 05:25:41 PM PDT 24
Peak memory 215964 kb
Host smart-5bd89f87-615b-4fd4-8333-431160709d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938560020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2938560020
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.700663461
Short name T357
Test name
Test status
Simulation time 28956200 ps
CPU time 1.11 seconds
Started Jun 30 05:25:44 PM PDT 24
Finished Jun 30 05:25:46 PM PDT 24
Peak memory 217712 kb
Host smart-ccdfcb18-1714-464a-b370-da2949886eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700663461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.700663461
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.320609199
Short name T777
Test name
Test status
Simulation time 95040375 ps
CPU time 1.15 seconds
Started Jun 30 05:25:38 PM PDT 24
Finished Jun 30 05:25:40 PM PDT 24
Peak memory 218748 kb
Host smart-defad58b-3f43-458e-96d1-5198d1361885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320609199 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.320609199
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.1651505626
Short name T693
Test name
Test status
Simulation time 27168890 ps
CPU time 1.21 seconds
Started Jun 30 05:25:44 PM PDT 24
Finished Jun 30 05:25:45 PM PDT 24
Peak memory 218632 kb
Host smart-e3bb6773-cdfd-48de-b5b5-ff9bff544bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651505626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1651505626
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.967104891
Short name T756
Test name
Test status
Simulation time 40769433 ps
CPU time 1.15 seconds
Started Jun 30 05:25:41 PM PDT 24
Finished Jun 30 05:25:42 PM PDT 24
Peak memory 219628 kb
Host smart-f144af15-5644-4eec-bd1b-3afb4273955a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967104891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.967104891
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.178592096
Short name T804
Test name
Test status
Simulation time 35442819 ps
CPU time 1.35 seconds
Started Jun 30 05:25:40 PM PDT 24
Finished Jun 30 05:25:42 PM PDT 24
Peak memory 218668 kb
Host smart-ae62ffae-b7ee-4e72-83f3-0810e7f7188c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178592096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.178592096
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.536546226
Short name T809
Test name
Test status
Simulation time 43136688 ps
CPU time 1.22 seconds
Started Jun 30 05:25:40 PM PDT 24
Finished Jun 30 05:25:42 PM PDT 24
Peak memory 219000 kb
Host smart-cc26d6df-c803-414f-8eca-07bc75967fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536546226 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.536546226
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/186.edn_alert.2668042325
Short name T396
Test name
Test status
Simulation time 44470106 ps
CPU time 1.24 seconds
Started Jun 30 05:25:44 PM PDT 24
Finished Jun 30 05:25:47 PM PDT 24
Peak memory 219872 kb
Host smart-f77a084f-f144-429b-8ad4-3b6256a7f7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668042325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.2668042325
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.1493450447
Short name T519
Test name
Test status
Simulation time 68646048 ps
CPU time 1.46 seconds
Started Jun 30 05:25:36 PM PDT 24
Finished Jun 30 05:25:37 PM PDT 24
Peak memory 220232 kb
Host smart-9498934b-a2e0-49a4-9e3d-076f90fad4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493450447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1493450447
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.1804328935
Short name T643
Test name
Test status
Simulation time 43242630 ps
CPU time 1.22 seconds
Started Jun 30 05:25:38 PM PDT 24
Finished Jun 30 05:25:40 PM PDT 24
Peak memory 220224 kb
Host smart-a64433f3-6248-4554-b583-54a875e2f3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804328935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1804328935
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.677926594
Short name T496
Test name
Test status
Simulation time 33662594 ps
CPU time 1.32 seconds
Started Jun 30 05:25:44 PM PDT 24
Finished Jun 30 05:25:46 PM PDT 24
Peak memory 218804 kb
Host smart-84869e62-1faa-464b-9fa1-ca9577c7fe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677926594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.677926594
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.261253593
Short name T515
Test name
Test status
Simulation time 41426695 ps
CPU time 1.15 seconds
Started Jun 30 05:25:46 PM PDT 24
Finished Jun 30 05:25:48 PM PDT 24
Peak memory 221052 kb
Host smart-2603ea64-7811-4da2-8c04-2f28b515ded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261253593 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.261253593
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.2354918298
Short name T480
Test name
Test status
Simulation time 48917144 ps
CPU time 1.66 seconds
Started Jun 30 05:25:40 PM PDT 24
Finished Jun 30 05:25:43 PM PDT 24
Peak memory 220524 kb
Host smart-dbb077d1-acb0-49dd-893a-920c1f619e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354918298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2354918298
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.2484988209
Short name T116
Test name
Test status
Simulation time 29769828 ps
CPU time 1.32 seconds
Started Jun 30 05:25:45 PM PDT 24
Finished Jun 30 05:25:47 PM PDT 24
Peak memory 219564 kb
Host smart-20fd36aa-eea2-49e2-8e40-2e9e5c0a50e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484988209 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2484988209
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.619587591
Short name T420
Test name
Test status
Simulation time 40590996 ps
CPU time 1.31 seconds
Started Jun 30 05:25:38 PM PDT 24
Finished Jun 30 05:25:40 PM PDT 24
Peak memory 218820 kb
Host smart-cae2a41f-b244-49a4-b77d-c0707bef6c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619587591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.619587591
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1326553383
Short name T937
Test name
Test status
Simulation time 68283007 ps
CPU time 1.05 seconds
Started Jun 30 05:23:03 PM PDT 24
Finished Jun 30 05:23:05 PM PDT 24
Peak memory 219052 kb
Host smart-deae0442-e596-4fa1-9a89-23b1c76444b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326553383 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1326553383
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.666139510
Short name T469
Test name
Test status
Simulation time 14389554 ps
CPU time 0.92 seconds
Started Jun 30 05:22:59 PM PDT 24
Finished Jun 30 05:23:00 PM PDT 24
Peak memory 215172 kb
Host smart-a2fc782f-b1d6-4f7f-a939-585ec1fc249c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666139510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.666139510
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.3756755602
Short name T654
Test name
Test status
Simulation time 46865084 ps
CPU time 0.83 seconds
Started Jun 30 05:22:55 PM PDT 24
Finished Jun 30 05:22:56 PM PDT 24
Peak memory 216240 kb
Host smart-29dd6063-1af3-4115-9ef1-58522696a05e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756755602 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3756755602
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1201700125
Short name T72
Test name
Test status
Simulation time 135970509 ps
CPU time 1.11 seconds
Started Jun 30 05:23:01 PM PDT 24
Finished Jun 30 05:23:02 PM PDT 24
Peak memory 217144 kb
Host smart-cc6eaf74-3719-4739-b254-d11240683255
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201700125 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1201700125
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2944561357
Short name T106
Test name
Test status
Simulation time 36577862 ps
CPU time 1.23 seconds
Started Jun 30 05:22:54 PM PDT 24
Finished Jun 30 05:22:56 PM PDT 24
Peak memory 229932 kb
Host smart-7dbba5c9-0b00-4e23-9def-2f88a3f792cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944561357 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2944561357
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.964062174
Short name T12
Test name
Test status
Simulation time 107148857 ps
CPU time 1.39 seconds
Started Jun 30 05:22:55 PM PDT 24
Finished Jun 30 05:22:57 PM PDT 24
Peak memory 217764 kb
Host smart-342784dc-3ef0-4dc5-ae26-defcd0fcd55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964062174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.964062174
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_smoke.1776649613
Short name T994
Test name
Test status
Simulation time 23914773 ps
CPU time 1 seconds
Started Jun 30 05:22:56 PM PDT 24
Finished Jun 30 05:22:58 PM PDT 24
Peak memory 215588 kb
Host smart-a20a3520-cebf-4459-a4df-d02cb29bb863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776649613 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1776649613
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.119866027
Short name T414
Test name
Test status
Simulation time 776035017 ps
CPU time 4.71 seconds
Started Jun 30 05:22:56 PM PDT 24
Finished Jun 30 05:23:01 PM PDT 24
Peak memory 217692 kb
Host smart-5a7ae037-4f1c-42fa-9f0b-2022ef1376fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119866027 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.119866027
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2485053443
Short name T556
Test name
Test status
Simulation time 94328713623 ps
CPU time 1202.08 seconds
Started Jun 30 05:22:55 PM PDT 24
Finished Jun 30 05:42:58 PM PDT 24
Peak memory 225516 kb
Host smart-9799a480-f2bb-4006-8c04-38d6f1b40e95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485053443 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2485053443
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.2603467597
Short name T712
Test name
Test status
Simulation time 39431017 ps
CPU time 1.15 seconds
Started Jun 30 05:25:37 PM PDT 24
Finished Jun 30 05:25:38 PM PDT 24
Peak memory 219848 kb
Host smart-e7601123-d2de-480b-a4f2-bfdc0c5d9ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603467597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.2603467597
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.932692040
Short name T297
Test name
Test status
Simulation time 42168084 ps
CPU time 1.47 seconds
Started Jun 30 05:25:44 PM PDT 24
Finished Jun 30 05:25:46 PM PDT 24
Peak memory 218720 kb
Host smart-add8d1f2-ba18-4c0f-b736-443c4e5e4d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932692040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.932692040
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.1749315856
Short name T948
Test name
Test status
Simulation time 25771927 ps
CPU time 1.19 seconds
Started Jun 30 05:25:39 PM PDT 24
Finished Jun 30 05:25:41 PM PDT 24
Peak memory 218972 kb
Host smart-188b3ed5-8c45-4a70-84ca-dfc43464502f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749315856 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.1749315856
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.3581361120
Short name T533
Test name
Test status
Simulation time 75393223 ps
CPU time 1.11 seconds
Started Jun 30 05:25:37 PM PDT 24
Finished Jun 30 05:25:39 PM PDT 24
Peak memory 217544 kb
Host smart-3c08a4f7-70c7-4495-83bb-e6afbaacd699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581361120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3581361120
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.1978574749
Short name T138
Test name
Test status
Simulation time 34839802 ps
CPU time 1.19 seconds
Started Jun 30 05:25:46 PM PDT 24
Finished Jun 30 05:25:49 PM PDT 24
Peak memory 219660 kb
Host smart-b36c14f1-a270-4ea4-9ba6-fbeb73e31838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978574749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.1978574749
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.4081065115
Short name T807
Test name
Test status
Simulation time 51831713 ps
CPU time 1.26 seconds
Started Jun 30 05:25:41 PM PDT 24
Finished Jun 30 05:25:42 PM PDT 24
Peak memory 219232 kb
Host smart-3749bfd3-ad64-4ecb-9bee-c387964a9347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081065115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.4081065115
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.3372177641
Short name T750
Test name
Test status
Simulation time 29917520 ps
CPU time 1.34 seconds
Started Jun 30 05:25:45 PM PDT 24
Finished Jun 30 05:25:47 PM PDT 24
Peak memory 215996 kb
Host smart-9b5977fc-ba5d-46d6-b275-0b4b613243e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372177641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.3372177641
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.3074576900
Short name T944
Test name
Test status
Simulation time 94758340 ps
CPU time 1.08 seconds
Started Jun 30 05:25:44 PM PDT 24
Finished Jun 30 05:25:46 PM PDT 24
Peak memory 217468 kb
Host smart-5fedde40-881e-42c8-88c8-d582bff765da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074576900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3074576900
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.943732517
Short name T259
Test name
Test status
Simulation time 68601928 ps
CPU time 1.22 seconds
Started Jun 30 05:25:46 PM PDT 24
Finished Jun 30 05:25:49 PM PDT 24
Peak memory 219548 kb
Host smart-68b54496-02ea-4fe6-b5e1-ad677ffdcc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943732517 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.943732517
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.2652936873
Short name T315
Test name
Test status
Simulation time 27630481 ps
CPU time 1.23 seconds
Started Jun 30 05:25:45 PM PDT 24
Finished Jun 30 05:25:47 PM PDT 24
Peak memory 220268 kb
Host smart-dc1caa38-cb52-4224-83b2-50ed8518e6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652936873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2652936873
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.886369791
Short name T39
Test name
Test status
Simulation time 258054334 ps
CPU time 1.11 seconds
Started Jun 30 05:25:44 PM PDT 24
Finished Jun 30 05:25:46 PM PDT 24
Peak memory 219036 kb
Host smart-3c002910-de7a-418d-affa-31e6d2132c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886369791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.886369791
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.3737145702
Short name T880
Test name
Test status
Simulation time 52538991 ps
CPU time 1.28 seconds
Started Jun 30 05:25:48 PM PDT 24
Finished Jun 30 05:25:50 PM PDT 24
Peak memory 218944 kb
Host smart-8fee9b28-57e2-40ce-b022-a4afad1f5460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737145702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3737145702
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.259159936
Short name T88
Test name
Test status
Simulation time 98400375 ps
CPU time 1.11 seconds
Started Jun 30 05:25:48 PM PDT 24
Finished Jun 30 05:25:50 PM PDT 24
Peak memory 218820 kb
Host smart-34212468-7f22-4c34-82f1-e369b40cf818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259159936 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.259159936
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.1317427627
Short name T558
Test name
Test status
Simulation time 71871400 ps
CPU time 1.1 seconds
Started Jun 30 05:25:45 PM PDT 24
Finished Jun 30 05:25:46 PM PDT 24
Peak memory 217748 kb
Host smart-f8edc58a-cd76-464a-99e5-d02011770858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317427627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1317427627
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.1301700214
Short name T918
Test name
Test status
Simulation time 41031343 ps
CPU time 1.15 seconds
Started Jun 30 05:25:52 PM PDT 24
Finished Jun 30 05:25:53 PM PDT 24
Peak memory 220124 kb
Host smart-6f0027cc-ec9a-4cbe-8968-61d5301c6d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301700214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.1301700214
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.966991712
Short name T538
Test name
Test status
Simulation time 33024973 ps
CPU time 1.42 seconds
Started Jun 30 05:25:46 PM PDT 24
Finished Jun 30 05:25:49 PM PDT 24
Peak memory 218844 kb
Host smart-a9d8a20b-b5ac-43c7-bdb9-b75f9a922a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966991712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.966991712
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.936731145
Short name T758
Test name
Test status
Simulation time 24820161 ps
CPU time 1.18 seconds
Started Jun 30 05:25:52 PM PDT 24
Finished Jun 30 05:25:53 PM PDT 24
Peak memory 219064 kb
Host smart-d1c3c104-bad0-4397-84c8-72f666167c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936731145 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.936731145
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.1665340072
Short name T272
Test name
Test status
Simulation time 91164962 ps
CPU time 3.03 seconds
Started Jun 30 05:25:48 PM PDT 24
Finished Jun 30 05:25:52 PM PDT 24
Peak memory 218804 kb
Host smart-c7e80162-2ffa-4fbc-a485-334edd3693cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665340072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1665340072
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.1866502485
Short name T171
Test name
Test status
Simulation time 74453471 ps
CPU time 1.17 seconds
Started Jun 30 05:25:48 PM PDT 24
Finished Jun 30 05:25:49 PM PDT 24
Peak memory 219916 kb
Host smart-fff8668c-6629-47da-b7b8-45ad59a75155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866502485 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.1866502485
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.2152046163
Short name T768
Test name
Test status
Simulation time 30408068 ps
CPU time 1.48 seconds
Started Jun 30 05:25:52 PM PDT 24
Finished Jun 30 05:25:54 PM PDT 24
Peak memory 220372 kb
Host smart-41105769-2dfc-47c8-add5-6814844a93c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152046163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2152046163
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.108774786
Short name T285
Test name
Test status
Simulation time 200407127 ps
CPU time 1.16 seconds
Started Jun 30 05:21:47 PM PDT 24
Finished Jun 30 05:21:48 PM PDT 24
Peak memory 219284 kb
Host smart-1bba711a-a2fd-440f-bfcf-4fa9774f4d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108774786 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.108774786
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.221824447
Short name T506
Test name
Test status
Simulation time 18467407 ps
CPU time 0.85 seconds
Started Jun 30 05:21:46 PM PDT 24
Finished Jun 30 05:21:47 PM PDT 24
Peak memory 207040 kb
Host smart-d2fec282-67c3-4e1d-893b-77ac698c9d93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221824447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.221824447
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2302601717
Short name T597
Test name
Test status
Simulation time 78667104 ps
CPU time 1.09 seconds
Started Jun 30 05:21:45 PM PDT 24
Finished Jun 30 05:21:47 PM PDT 24
Peak memory 217280 kb
Host smart-7636ec52-bfb5-4da7-97b9-fb395b03b4da
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302601717 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2302601717
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3659773513
Short name T156
Test name
Test status
Simulation time 20074951 ps
CPU time 1.2 seconds
Started Jun 30 05:21:46 PM PDT 24
Finished Jun 30 05:21:48 PM PDT 24
Peak memory 224248 kb
Host smart-a4b5eacc-2242-49ea-8a98-86ee9a5de1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659773513 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3659773513
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1439275156
Short name T603
Test name
Test status
Simulation time 41513794 ps
CPU time 1.16 seconds
Started Jun 30 05:21:47 PM PDT 24
Finished Jun 30 05:21:49 PM PDT 24
Peak memory 218972 kb
Host smart-8b5c25d7-4d5a-42f9-83ed-a93ab217e37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439275156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1439275156
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3492706080
Short name T678
Test name
Test status
Simulation time 48387360 ps
CPU time 0.85 seconds
Started Jun 30 05:21:46 PM PDT 24
Finished Jun 30 05:21:47 PM PDT 24
Peak memory 215768 kb
Host smart-987da5d3-b9c8-4847-8639-cbbe50bb18c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492706080 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3492706080
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2872492826
Short name T26
Test name
Test status
Simulation time 37958851 ps
CPU time 0.95 seconds
Started Jun 30 05:21:48 PM PDT 24
Finished Jun 30 05:21:49 PM PDT 24
Peak memory 207336 kb
Host smart-9a2fa45e-3015-4dea-96ac-8b7831834b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872492826 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2872492826
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1584259903
Short name T61
Test name
Test status
Simulation time 454733668 ps
CPU time 7.64 seconds
Started Jun 30 05:21:47 PM PDT 24
Finished Jun 30 05:21:55 PM PDT 24
Peak memory 236484 kb
Host smart-d9d31b1f-29b8-4c30-8c18-3798a1e61a9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584259903 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1584259903
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1262904068
Short name T365
Test name
Test status
Simulation time 27804147 ps
CPU time 0.95 seconds
Started Jun 30 05:21:48 PM PDT 24
Finished Jun 30 05:21:50 PM PDT 24
Peak memory 215476 kb
Host smart-8492365e-5b85-40d9-992c-eed61cb16e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262904068 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1262904068
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.702084589
Short name T231
Test name
Test status
Simulation time 184168041 ps
CPU time 3.89 seconds
Started Jun 30 05:21:48 PM PDT 24
Finished Jun 30 05:21:52 PM PDT 24
Peak memory 217540 kb
Host smart-9ca7a3a5-66f3-47ba-943a-26f87753d7f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702084589 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.702084589
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3476326378
Short name T798
Test name
Test status
Simulation time 52428786025 ps
CPU time 462.57 seconds
Started Jun 30 05:21:46 PM PDT 24
Finished Jun 30 05:29:30 PM PDT 24
Peak memory 218420 kb
Host smart-0ceec895-45d7-4682-98ee-670a21590eb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476326378 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3476326378
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3535336729
Short name T109
Test name
Test status
Simulation time 30766716 ps
CPU time 1.31 seconds
Started Jun 30 05:23:02 PM PDT 24
Finished Jun 30 05:23:03 PM PDT 24
Peak memory 215992 kb
Host smart-d8250df2-783e-4efd-97dd-6b791f64b09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535336729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3535336729
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3207228385
Short name T364
Test name
Test status
Simulation time 139922248 ps
CPU time 1.01 seconds
Started Jun 30 05:22:56 PM PDT 24
Finished Jun 30 05:22:58 PM PDT 24
Peak memory 207144 kb
Host smart-46c42f53-aa4c-413f-a2f1-7373258e7d7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207228385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3207228385
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.593821320
Short name T162
Test name
Test status
Simulation time 11632653 ps
CPU time 0.86 seconds
Started Jun 30 05:22:56 PM PDT 24
Finished Jun 30 05:22:57 PM PDT 24
Peak memory 216644 kb
Host smart-57167492-1d47-4fed-90a6-cc4661392d70
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593821320 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.593821320
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.779840073
Short name T569
Test name
Test status
Simulation time 32756914 ps
CPU time 1.23 seconds
Started Jun 30 05:22:55 PM PDT 24
Finished Jun 30 05:22:57 PM PDT 24
Peak memory 217084 kb
Host smart-ed0e9bdd-bb26-4b7a-83db-18eed1e36f29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779840073 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.779840073
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2656470755
Short name T190
Test name
Test status
Simulation time 24603483 ps
CPU time 1 seconds
Started Jun 30 05:22:55 PM PDT 24
Finished Jun 30 05:22:56 PM PDT 24
Peak memory 219080 kb
Host smart-15984e6e-4a91-455a-8340-d836214c5538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656470755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2656470755
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3127285665
Short name T432
Test name
Test status
Simulation time 39397811 ps
CPU time 1.53 seconds
Started Jun 30 05:22:55 PM PDT 24
Finished Jun 30 05:22:57 PM PDT 24
Peak memory 217504 kb
Host smart-e7f4e188-54cb-49a8-8465-01826101ff41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127285665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3127285665
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3134916357
Short name T101
Test name
Test status
Simulation time 20855116 ps
CPU time 1.01 seconds
Started Jun 30 05:22:55 PM PDT 24
Finished Jun 30 05:22:56 PM PDT 24
Peak memory 216120 kb
Host smart-01688d81-06d7-42e6-9f02-9cf682beb5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134916357 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3134916357
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1149834591
Short name T762
Test name
Test status
Simulation time 17557895 ps
CPU time 0.99 seconds
Started Jun 30 05:22:55 PM PDT 24
Finished Jun 30 05:22:56 PM PDT 24
Peak memory 215564 kb
Host smart-b3cc807f-c28a-4bd2-b10d-603051e3a19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149834591 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1149834591
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1732362391
Short name T922
Test name
Test status
Simulation time 413101734 ps
CPU time 4.32 seconds
Started Jun 30 05:23:01 PM PDT 24
Finished Jun 30 05:23:06 PM PDT 24
Peak memory 217656 kb
Host smart-ddda7299-6f94-4822-9bcd-136bc40c015f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732362391 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1732362391
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3244670083
Short name T222
Test name
Test status
Simulation time 26329969892 ps
CPU time 593.33 seconds
Started Jun 30 05:22:57 PM PDT 24
Finished Jun 30 05:32:51 PM PDT 24
Peak memory 219212 kb
Host smart-e31294bf-c9ea-4f9e-bb1a-e4f4b5ae8b2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244670083 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3244670083
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1613995603
Short name T459
Test name
Test status
Simulation time 58620052 ps
CPU time 1.43 seconds
Started Jun 30 05:25:46 PM PDT 24
Finished Jun 30 05:25:49 PM PDT 24
Peak memory 220072 kb
Host smart-f40e1b58-376e-454e-96a4-bd8e7ad34aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613995603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1613995603
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.10283001
Short name T433
Test name
Test status
Simulation time 83959790 ps
CPU time 1.09 seconds
Started Jun 30 05:25:46 PM PDT 24
Finished Jun 30 05:25:48 PM PDT 24
Peak memory 217648 kb
Host smart-ad3d95df-8510-4a13-aa9a-6f89dd2d0cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10283001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.10283001
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3623250685
Short name T431
Test name
Test status
Simulation time 52769025 ps
CPU time 1.52 seconds
Started Jun 30 05:25:46 PM PDT 24
Finished Jun 30 05:25:49 PM PDT 24
Peak memory 217712 kb
Host smart-5942623e-7439-44ab-8337-160446c9c158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623250685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3623250685
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2110170456
Short name T353
Test name
Test status
Simulation time 71745268 ps
CPU time 2.79 seconds
Started Jun 30 05:25:45 PM PDT 24
Finished Jun 30 05:25:48 PM PDT 24
Peak memory 219784 kb
Host smart-e3ee875b-d816-45d9-9c8f-bacb95e39f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110170456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2110170456
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3239242866
Short name T81
Test name
Test status
Simulation time 119057342 ps
CPU time 1.41 seconds
Started Jun 30 05:25:47 PM PDT 24
Finished Jun 30 05:25:49 PM PDT 24
Peak memory 219396 kb
Host smart-a519cc46-59f0-4cf0-9e78-336b1f218fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239242866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3239242866
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.71866861
Short name T700
Test name
Test status
Simulation time 152587185 ps
CPU time 1.39 seconds
Started Jun 30 05:25:53 PM PDT 24
Finished Jun 30 05:25:56 PM PDT 24
Peak memory 217704 kb
Host smart-af833ed7-b015-43ad-acd2-c5370cad6a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71866861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.71866861
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2812404791
Short name T44
Test name
Test status
Simulation time 182441994 ps
CPU time 1.14 seconds
Started Jun 30 05:25:53 PM PDT 24
Finished Jun 30 05:25:56 PM PDT 24
Peak memory 217616 kb
Host smart-90903c79-dfd5-4bc7-ba87-23bb7ec10570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812404791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2812404791
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1478016647
Short name T942
Test name
Test status
Simulation time 34182327 ps
CPU time 1.43 seconds
Started Jun 30 05:25:54 PM PDT 24
Finished Jun 30 05:25:57 PM PDT 24
Peak memory 218700 kb
Host smart-51a0b600-e31a-44c0-b678-ca51f32b5436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478016647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1478016647
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2870655371
Short name T795
Test name
Test status
Simulation time 171454114 ps
CPU time 2.38 seconds
Started Jun 30 05:25:53 PM PDT 24
Finished Jun 30 05:25:57 PM PDT 24
Peak memory 220088 kb
Host smart-2332f27f-4a44-47b3-a113-74202f234d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870655371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2870655371
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2367312077
Short name T9
Test name
Test status
Simulation time 76740298 ps
CPU time 2.15 seconds
Started Jun 30 05:25:53 PM PDT 24
Finished Jun 30 05:25:57 PM PDT 24
Peak memory 220216 kb
Host smart-c6d5108b-e653-493f-9f3e-98623f58a392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367312077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2367312077
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3476650770
Short name T741
Test name
Test status
Simulation time 78235547 ps
CPU time 1.22 seconds
Started Jun 30 05:23:04 PM PDT 24
Finished Jun 30 05:23:06 PM PDT 24
Peak memory 219088 kb
Host smart-a7fcb4f0-34e8-47aa-a9b1-1ca5b3be704c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476650770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3476650770
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.505845978
Short name T783
Test name
Test status
Simulation time 14459425 ps
CPU time 0.91 seconds
Started Jun 30 05:23:03 PM PDT 24
Finished Jun 30 05:23:04 PM PDT 24
Peak memory 215304 kb
Host smart-9abb3cab-8646-4512-a430-153bbc570212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505845978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.505845978
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.500039597
Short name T419
Test name
Test status
Simulation time 12707436 ps
CPU time 0.91 seconds
Started Jun 30 05:23:03 PM PDT 24
Finished Jun 30 05:23:05 PM PDT 24
Peak memory 216732 kb
Host smart-374d814a-d3c9-4a7b-ade9-c8c8adf5897b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500039597 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.500039597
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.296115302
Short name T745
Test name
Test status
Simulation time 62141697 ps
CPU time 1.27 seconds
Started Jun 30 05:23:06 PM PDT 24
Finished Jun 30 05:23:09 PM PDT 24
Peak memory 217416 kb
Host smart-8d79cd6a-b64b-4fc3-9c2d-8d66cfb17ff2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296115302 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.296115302
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.1007866478
Short name T707
Test name
Test status
Simulation time 18278144 ps
CPU time 1.1 seconds
Started Jun 30 05:23:06 PM PDT 24
Finished Jun 30 05:23:08 PM PDT 24
Peak memory 218812 kb
Host smart-aa3bc3e8-6b11-4210-aba0-5986d09e7b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007866478 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1007866478
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.500041508
Short name T552
Test name
Test status
Simulation time 49996784 ps
CPU time 2.13 seconds
Started Jun 30 05:23:05 PM PDT 24
Finished Jun 30 05:23:08 PM PDT 24
Peak memory 220680 kb
Host smart-cd2598a7-b9e5-4000-aadd-b019ca7bfc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500041508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.500041508
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3859601680
Short name T75
Test name
Test status
Simulation time 37984849 ps
CPU time 0.91 seconds
Started Jun 30 05:23:07 PM PDT 24
Finished Jun 30 05:23:08 PM PDT 24
Peak memory 215832 kb
Host smart-d0714ea6-0c10-4691-8026-4141b97013f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859601680 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3859601680
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3480210454
Short name T426
Test name
Test status
Simulation time 93147210 ps
CPU time 0.92 seconds
Started Jun 30 05:22:59 PM PDT 24
Finished Jun 30 05:23:00 PM PDT 24
Peak memory 215588 kb
Host smart-8fb870f7-1d71-4dd7-9eed-16836e7587ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480210454 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3480210454
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.843343384
Short name T964
Test name
Test status
Simulation time 166231300 ps
CPU time 2.85 seconds
Started Jun 30 05:23:06 PM PDT 24
Finished Jun 30 05:23:10 PM PDT 24
Peak memory 215588 kb
Host smart-c2c7ae2f-0919-4da1-bba8-a5f05de015a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843343384 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.843343384
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.382246724
Short name T845
Test name
Test status
Simulation time 82130450249 ps
CPU time 453.07 seconds
Started Jun 30 05:23:08 PM PDT 24
Finished Jun 30 05:30:42 PM PDT 24
Peak memory 224056 kb
Host smart-edf4d6ca-40af-467b-8bdc-2a27e7aa6bff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382246724 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.382246724
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1925392364
Short name T22
Test name
Test status
Simulation time 367349727 ps
CPU time 4.87 seconds
Started Jun 30 05:25:53 PM PDT 24
Finished Jun 30 05:26:00 PM PDT 24
Peak memory 218020 kb
Host smart-b69f9fb7-1329-40e8-bb70-332e4cce1de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925392364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1925392364
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1774590133
Short name T537
Test name
Test status
Simulation time 42922679 ps
CPU time 1.72 seconds
Started Jun 30 05:25:54 PM PDT 24
Finished Jun 30 05:25:58 PM PDT 24
Peak memory 218936 kb
Host smart-988e49b4-c820-4cf5-b071-bc4d06367d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774590133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1774590133
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.456154482
Short name T19
Test name
Test status
Simulation time 63412750 ps
CPU time 1.35 seconds
Started Jun 30 05:25:54 PM PDT 24
Finished Jun 30 05:25:58 PM PDT 24
Peak memory 220172 kb
Host smart-efa32bc7-fa54-4697-953c-4eaa2471641f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456154482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.456154482
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2335039997
Short name T592
Test name
Test status
Simulation time 139132650 ps
CPU time 3.07 seconds
Started Jun 30 05:25:53 PM PDT 24
Finished Jun 30 05:25:58 PM PDT 24
Peak memory 219196 kb
Host smart-9a9629a5-62a4-49fd-8b71-ef4e3fc4a959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335039997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2335039997
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.4084315147
Short name T708
Test name
Test status
Simulation time 25360325 ps
CPU time 1.13 seconds
Started Jun 30 05:25:53 PM PDT 24
Finished Jun 30 05:25:56 PM PDT 24
Peak memory 219076 kb
Host smart-5727b2c6-bf4c-4f29-81fa-69cb03aba2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084315147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.4084315147
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3597965338
Short name T778
Test name
Test status
Simulation time 48552905 ps
CPU time 1.24 seconds
Started Jun 30 05:25:52 PM PDT 24
Finished Jun 30 05:25:54 PM PDT 24
Peak memory 218948 kb
Host smart-78a274c3-40b8-4c36-b121-2a43b1bb5cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597965338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3597965338
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2253270078
Short name T920
Test name
Test status
Simulation time 44935359 ps
CPU time 1.76 seconds
Started Jun 30 05:25:57 PM PDT 24
Finished Jun 30 05:26:00 PM PDT 24
Peak memory 220392 kb
Host smart-968d82e1-eb56-4c4a-a4ce-12db897a86e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253270078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2253270078
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.781429994
Short name T457
Test name
Test status
Simulation time 27012069 ps
CPU time 1.2 seconds
Started Jun 30 05:25:57 PM PDT 24
Finished Jun 30 05:26:00 PM PDT 24
Peak memory 218852 kb
Host smart-cf984f7e-c042-4d98-903b-42e9529337e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781429994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.781429994
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.287098907
Short name T336
Test name
Test status
Simulation time 31206318 ps
CPU time 1.21 seconds
Started Jun 30 05:25:52 PM PDT 24
Finished Jun 30 05:25:54 PM PDT 24
Peak memory 217508 kb
Host smart-59392814-c983-464a-b44d-952e13ab23a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287098907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.287098907
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1998736852
Short name T960
Test name
Test status
Simulation time 89009608 ps
CPU time 1.11 seconds
Started Jun 30 05:25:54 PM PDT 24
Finished Jun 30 05:25:56 PM PDT 24
Peak memory 218604 kb
Host smart-6c8a92e1-4d9b-4e56-8123-6812865b0e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998736852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1998736852
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1637032524
Short name T280
Test name
Test status
Simulation time 45885124 ps
CPU time 1.15 seconds
Started Jun 30 05:23:05 PM PDT 24
Finished Jun 30 05:23:07 PM PDT 24
Peak memory 220000 kb
Host smart-d65f7a49-faf4-480b-b281-295ced345b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637032524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1637032524
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1833345123
Short name T658
Test name
Test status
Simulation time 26094768 ps
CPU time 0.91 seconds
Started Jun 30 05:23:05 PM PDT 24
Finished Jun 30 05:23:07 PM PDT 24
Peak memory 215148 kb
Host smart-5c66decb-1dc0-4764-ba37-4eb767410da7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833345123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1833345123
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2681212828
Short name T146
Test name
Test status
Simulation time 15282883 ps
CPU time 0.94 seconds
Started Jun 30 05:23:07 PM PDT 24
Finished Jun 30 05:23:09 PM PDT 24
Peak memory 215844 kb
Host smart-94f2dfde-46c8-4f60-96a9-e69e5f5c8e9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681212828 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2681212828
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2334744162
Short name T373
Test name
Test status
Simulation time 22670463 ps
CPU time 1.01 seconds
Started Jun 30 05:23:08 PM PDT 24
Finished Jun 30 05:23:10 PM PDT 24
Peak memory 218616 kb
Host smart-acdc39de-0cc2-4b48-ae36-b552e0f1636a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334744162 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2334744162
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_genbits.2352471862
Short name T388
Test name
Test status
Simulation time 57477730 ps
CPU time 1.03 seconds
Started Jun 30 05:23:08 PM PDT 24
Finished Jun 30 05:23:10 PM PDT 24
Peak memory 219988 kb
Host smart-a8dfd11e-7be6-4eed-ad8f-e65724c20a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352471862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2352471862
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2004839827
Short name T581
Test name
Test status
Simulation time 20641043 ps
CPU time 1.28 seconds
Started Jun 30 05:23:03 PM PDT 24
Finished Jun 30 05:23:05 PM PDT 24
Peak memory 224340 kb
Host smart-8f6d5053-8144-4eeb-a2b4-404de2a4024d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004839827 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2004839827
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3781858460
Short name T790
Test name
Test status
Simulation time 42238452 ps
CPU time 0.95 seconds
Started Jun 30 05:23:06 PM PDT 24
Finished Jun 30 05:23:08 PM PDT 24
Peak memory 215604 kb
Host smart-d411bada-e3af-4ff8-9ae6-d5cb651af230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781858460 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3781858460
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1092588943
Short name T780
Test name
Test status
Simulation time 435545032 ps
CPU time 3 seconds
Started Jun 30 05:23:05 PM PDT 24
Finished Jun 30 05:23:09 PM PDT 24
Peak memory 215576 kb
Host smart-c70a4359-be49-4e04-9ff4-e8bbf47ac31d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092588943 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1092588943
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1276680417
Short name T674
Test name
Test status
Simulation time 180515373059 ps
CPU time 458.54 seconds
Started Jun 30 05:23:05 PM PDT 24
Finished Jun 30 05:30:44 PM PDT 24
Peak memory 228268 kb
Host smart-c0155c48-6472-4d31-8d0c-e24df958decf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276680417 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1276680417
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.125635185
Short name T361
Test name
Test status
Simulation time 546294573 ps
CPU time 4.46 seconds
Started Jun 30 05:25:54 PM PDT 24
Finished Jun 30 05:26:00 PM PDT 24
Peak memory 220708 kb
Host smart-92d35673-a2a1-4553-a17b-bbaf53a5e57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125635185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.125635185
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3387717695
Short name T699
Test name
Test status
Simulation time 43263312 ps
CPU time 1.56 seconds
Started Jun 30 05:25:52 PM PDT 24
Finished Jun 30 05:25:55 PM PDT 24
Peak memory 218912 kb
Host smart-bf63a3d7-b1e0-42d1-a916-f8975a2eb19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387717695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3387717695
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1335080255
Short name T1
Test name
Test status
Simulation time 88867905 ps
CPU time 1.36 seconds
Started Jun 30 05:25:52 PM PDT 24
Finished Jun 30 05:25:55 PM PDT 24
Peak memory 218604 kb
Host smart-d530502e-3f62-410f-b96a-4ec92f4b90ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335080255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1335080255
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2951970702
Short name T301
Test name
Test status
Simulation time 43134969 ps
CPU time 1.84 seconds
Started Jun 30 05:25:53 PM PDT 24
Finished Jun 30 05:25:57 PM PDT 24
Peak memory 218760 kb
Host smart-3edbe8ff-c4f6-4402-96e5-6a8862acf011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951970702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2951970702
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3661581191
Short name T408
Test name
Test status
Simulation time 39699698 ps
CPU time 1.6 seconds
Started Jun 30 05:25:52 PM PDT 24
Finished Jun 30 05:25:55 PM PDT 24
Peak memory 218716 kb
Host smart-e62ea1e0-52af-4cca-b7b9-1fd4ae8d903b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661581191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3661581191
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1429810940
Short name T763
Test name
Test status
Simulation time 48087516 ps
CPU time 1.11 seconds
Started Jun 30 05:25:53 PM PDT 24
Finished Jun 30 05:25:56 PM PDT 24
Peak memory 217492 kb
Host smart-f10d9a29-76fb-4fe6-b1af-c80d3d448a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429810940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1429810940
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2227071153
Short name T478
Test name
Test status
Simulation time 277770663 ps
CPU time 2.04 seconds
Started Jun 30 05:25:53 PM PDT 24
Finished Jun 30 05:25:56 PM PDT 24
Peak memory 220524 kb
Host smart-86419be9-a9d4-426c-89c5-f21563413e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227071153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2227071153
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3562080615
Short name T808
Test name
Test status
Simulation time 79236448 ps
CPU time 2.85 seconds
Started Jun 30 05:25:58 PM PDT 24
Finished Jun 30 05:26:03 PM PDT 24
Peak memory 220320 kb
Host smart-44d21130-0501-4cb1-9b66-2f950519dcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562080615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3562080615
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3286925377
Short name T374
Test name
Test status
Simulation time 82355830 ps
CPU time 1.18 seconds
Started Jun 30 05:25:55 PM PDT 24
Finished Jun 30 05:25:58 PM PDT 24
Peak memory 217688 kb
Host smart-cac26fda-6c9c-47a0-9d38-ff32a9ed8495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286925377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3286925377
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1809120863
Short name T380
Test name
Test status
Simulation time 76884547 ps
CPU time 1.15 seconds
Started Jun 30 05:25:54 PM PDT 24
Finished Jun 30 05:25:57 PM PDT 24
Peak memory 217424 kb
Host smart-db1453a9-eb70-461d-bb28-b8f2d0721037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809120863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1809120863
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert_test.2951595173
Short name T355
Test name
Test status
Simulation time 43621233 ps
CPU time 0.87 seconds
Started Jun 30 05:23:07 PM PDT 24
Finished Jun 30 05:23:09 PM PDT 24
Peak memory 207072 kb
Host smart-968b73fe-431f-410a-b426-4e3e6d25b103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951595173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2951595173
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_err.1835641461
Short name T407
Test name
Test status
Simulation time 18325767 ps
CPU time 1.04 seconds
Started Jun 30 05:23:04 PM PDT 24
Finished Jun 30 05:23:05 PM PDT 24
Peak memory 218896 kb
Host smart-4801e90b-51ed-457d-97f0-b90ddf3bcf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835641461 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1835641461
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2017375350
Short name T649
Test name
Test status
Simulation time 163707994 ps
CPU time 1.25 seconds
Started Jun 30 05:23:06 PM PDT 24
Finished Jun 30 05:23:09 PM PDT 24
Peak memory 219964 kb
Host smart-69f184b5-97e6-4dca-a8df-73edd85bee00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017375350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2017375350
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2695473130
Short name T692
Test name
Test status
Simulation time 22530929 ps
CPU time 1.12 seconds
Started Jun 30 05:23:03 PM PDT 24
Finished Jun 30 05:23:05 PM PDT 24
Peak memory 215792 kb
Host smart-f1978ee8-e535-4e61-b765-ab4b2ed7fdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695473130 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2695473130
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3778234311
Short name T318
Test name
Test status
Simulation time 52893437 ps
CPU time 0.93 seconds
Started Jun 30 05:23:04 PM PDT 24
Finished Jun 30 05:23:05 PM PDT 24
Peak memory 215612 kb
Host smart-d46d62e7-840f-4963-a3b9-059de7c50985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778234311 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3778234311
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1391002629
Short name T343
Test name
Test status
Simulation time 114993331 ps
CPU time 2.74 seconds
Started Jun 30 05:23:03 PM PDT 24
Finished Jun 30 05:23:07 PM PDT 24
Peak memory 218964 kb
Host smart-e3e70631-78f1-41b8-abcc-e6d7b11e0ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391002629 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1391002629
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.4045102015
Short name T349
Test name
Test status
Simulation time 81506500136 ps
CPU time 1006.6 seconds
Started Jun 30 05:23:07 PM PDT 24
Finished Jun 30 05:39:55 PM PDT 24
Peak memory 224064 kb
Host smart-6898b2df-6a1c-4173-ab76-2dbaa00091f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045102015 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.4045102015
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/231.edn_genbits.2804750309
Short name T360
Test name
Test status
Simulation time 47588795 ps
CPU time 1.67 seconds
Started Jun 30 05:25:56 PM PDT 24
Finished Jun 30 05:26:00 PM PDT 24
Peak memory 217736 kb
Host smart-11d77c81-76ab-4efc-a9d1-89a6305d3bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804750309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2804750309
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1961709418
Short name T383
Test name
Test status
Simulation time 107553593 ps
CPU time 1.15 seconds
Started Jun 30 05:25:54 PM PDT 24
Finished Jun 30 05:25:57 PM PDT 24
Peak memory 217688 kb
Host smart-f054c5ec-f07d-4937-beff-8b868f3b6903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961709418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1961709418
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3243737651
Short name T822
Test name
Test status
Simulation time 155298540 ps
CPU time 1.35 seconds
Started Jun 30 05:25:55 PM PDT 24
Finished Jun 30 05:25:58 PM PDT 24
Peak memory 219156 kb
Host smart-789bace0-63b1-4e74-9700-61734d29d69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243737651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3243737651
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1848802184
Short name T600
Test name
Test status
Simulation time 53123997 ps
CPU time 1.27 seconds
Started Jun 30 05:25:56 PM PDT 24
Finished Jun 30 05:25:59 PM PDT 24
Peak memory 217664 kb
Host smart-6c13dd41-31f7-41dd-a2df-9bba4bc056cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848802184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1848802184
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.291291206
Short name T487
Test name
Test status
Simulation time 93721742 ps
CPU time 1.18 seconds
Started Jun 30 05:25:58 PM PDT 24
Finished Jun 30 05:26:02 PM PDT 24
Peak memory 220456 kb
Host smart-0e91b935-f6cd-4a60-881d-748ba9a0ddf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291291206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.291291206
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2140981172
Short name T915
Test name
Test status
Simulation time 59725861 ps
CPU time 1.27 seconds
Started Jun 30 05:25:55 PM PDT 24
Finished Jun 30 05:25:58 PM PDT 24
Peak memory 217568 kb
Host smart-8aa063eb-f238-4bd2-96c4-efcc3037750a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140981172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2140981172
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1059072525
Short name T346
Test name
Test status
Simulation time 66804751 ps
CPU time 1.05 seconds
Started Jun 30 05:25:53 PM PDT 24
Finished Jun 30 05:25:56 PM PDT 24
Peak memory 217616 kb
Host smart-3d7d1ef3-c0c7-48c5-a9cd-57416dc883c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059072525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1059072525
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.620356281
Short name T328
Test name
Test status
Simulation time 47752337 ps
CPU time 1.61 seconds
Started Jun 30 05:25:57 PM PDT 24
Finished Jun 30 05:26:01 PM PDT 24
Peak memory 215616 kb
Host smart-264cd5df-e8bd-453a-af28-95777de26b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620356281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.620356281
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert_test.2519185747
Short name T989
Test name
Test status
Simulation time 17156941 ps
CPU time 0.94 seconds
Started Jun 30 05:23:12 PM PDT 24
Finished Jun 30 05:23:14 PM PDT 24
Peak memory 206992 kb
Host smart-38bce06d-53b0-4f35-ba67-bfec3a32e759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519185747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2519185747
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.455056153
Short name T157
Test name
Test status
Simulation time 39204883 ps
CPU time 0.88 seconds
Started Jun 30 05:23:10 PM PDT 24
Finished Jun 30 05:23:11 PM PDT 24
Peak memory 216544 kb
Host smart-ecbc04f8-8469-4cf6-bad7-f0e9f0986979
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455056153 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.455056153
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.511569609
Short name T665
Test name
Test status
Simulation time 28266464 ps
CPU time 1.02 seconds
Started Jun 30 05:23:11 PM PDT 24
Finished Jun 30 05:23:13 PM PDT 24
Peak memory 224020 kb
Host smart-96f5f5ed-9dac-41ab-b421-2553a4f2c7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511569609 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.511569609
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.4226941013
Short name T226
Test name
Test status
Simulation time 73154991 ps
CPU time 1.48 seconds
Started Jun 30 05:23:14 PM PDT 24
Finished Jun 30 05:23:16 PM PDT 24
Peak memory 218936 kb
Host smart-1585b1e6-3c6d-421b-b332-dd427d3912ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226941013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.4226941013
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2271198915
Short name T663
Test name
Test status
Simulation time 25254503 ps
CPU time 1.17 seconds
Started Jun 30 05:23:12 PM PDT 24
Finished Jun 30 05:23:14 PM PDT 24
Peak memory 215708 kb
Host smart-6381cd1a-d4fa-4c57-a94b-686ba80e7983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271198915 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2271198915
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3428377997
Short name T571
Test name
Test status
Simulation time 32909743 ps
CPU time 0.94 seconds
Started Jun 30 05:23:02 PM PDT 24
Finished Jun 30 05:23:03 PM PDT 24
Peak memory 215560 kb
Host smart-accaff32-b164-4cde-8bb2-084bdfaae8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428377997 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3428377997
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2490371304
Short name T304
Test name
Test status
Simulation time 63237868 ps
CPU time 1.86 seconds
Started Jun 30 05:23:13 PM PDT 24
Finished Jun 30 05:23:16 PM PDT 24
Peak memory 215572 kb
Host smart-99f105ed-5629-4350-967f-1f7db0a08224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490371304 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2490371304
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1294493900
Short name T220
Test name
Test status
Simulation time 19491914208 ps
CPU time 418.25 seconds
Started Jun 30 05:23:13 PM PDT 24
Finished Jun 30 05:30:12 PM PDT 24
Peak memory 218072 kb
Host smart-8f5ce7c9-f5f1-40e7-89da-000c3d5cfb3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294493900 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1294493900
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1205926077
Short name T518
Test name
Test status
Simulation time 54950305 ps
CPU time 1.33 seconds
Started Jun 30 05:25:55 PM PDT 24
Finished Jun 30 05:25:58 PM PDT 24
Peak memory 218692 kb
Host smart-41ccda08-3b5f-42d8-9ac6-d73fdff09159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205926077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1205926077
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3267513514
Short name T883
Test name
Test status
Simulation time 44439274 ps
CPU time 1.51 seconds
Started Jun 30 05:25:58 PM PDT 24
Finished Jun 30 05:26:01 PM PDT 24
Peak memory 218776 kb
Host smart-777caac3-e42e-4389-9c11-54f08be7d6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267513514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3267513514
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1615451616
Short name T858
Test name
Test status
Simulation time 42048171 ps
CPU time 1.17 seconds
Started Jun 30 05:25:59 PM PDT 24
Finished Jun 30 05:26:03 PM PDT 24
Peak memory 217648 kb
Host smart-f84db431-6cdc-4f25-bb99-cbc2507c402e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615451616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1615451616
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.991269968
Short name T672
Test name
Test status
Simulation time 45985067 ps
CPU time 1.58 seconds
Started Jun 30 05:25:58 PM PDT 24
Finished Jun 30 05:26:02 PM PDT 24
Peak memory 218896 kb
Host smart-6a007d13-e432-4873-9be7-19068baae835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991269968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.991269968
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.489409517
Short name T316
Test name
Test status
Simulation time 219258700 ps
CPU time 3.01 seconds
Started Jun 30 05:25:55 PM PDT 24
Finished Jun 30 05:26:00 PM PDT 24
Peak memory 218812 kb
Host smart-5e20607b-3999-4194-a90e-448dc83440f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489409517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.489409517
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.598711822
Short name T486
Test name
Test status
Simulation time 70029259 ps
CPU time 1.4 seconds
Started Jun 30 05:25:57 PM PDT 24
Finished Jun 30 05:26:00 PM PDT 24
Peak memory 218852 kb
Host smart-0c9be0e9-50fe-473a-91e1-761534d859b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598711822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.598711822
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1820863411
Short name T578
Test name
Test status
Simulation time 36448984 ps
CPU time 1.51 seconds
Started Jun 30 05:25:58 PM PDT 24
Finished Jun 30 05:26:02 PM PDT 24
Peak memory 220408 kb
Host smart-4cee79f6-441a-450e-b5ab-d74361fa80cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820863411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1820863411
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2927581857
Short name T589
Test name
Test status
Simulation time 27947497 ps
CPU time 1.29 seconds
Started Jun 30 05:25:57 PM PDT 24
Finished Jun 30 05:26:00 PM PDT 24
Peak memory 215596 kb
Host smart-cfed1fa0-1ebf-4498-9ee6-a04ce8b100db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927581857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2927581857
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1996901856
Short name T460
Test name
Test status
Simulation time 53937167 ps
CPU time 1.14 seconds
Started Jun 30 05:25:57 PM PDT 24
Finished Jun 30 05:26:00 PM PDT 24
Peak memory 217488 kb
Host smart-16ea36f9-1768-4cef-a723-f1aca07d5ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996901856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1996901856
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1885304365
Short name T46
Test name
Test status
Simulation time 146933474 ps
CPU time 1.24 seconds
Started Jun 30 05:25:56 PM PDT 24
Finished Jun 30 05:25:59 PM PDT 24
Peak memory 217532 kb
Host smart-9c4effdb-ee28-48ae-aa95-92022dd3a96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885304365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1885304365
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1157899939
Short name T98
Test name
Test status
Simulation time 48463865 ps
CPU time 1.19 seconds
Started Jun 30 05:23:13 PM PDT 24
Finished Jun 30 05:23:15 PM PDT 24
Peak memory 221236 kb
Host smart-a64c460c-4c9b-4bab-a92c-e9a9145072ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157899939 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1157899939
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.280869654
Short name T803
Test name
Test status
Simulation time 103963390 ps
CPU time 0.94 seconds
Started Jun 30 05:23:11 PM PDT 24
Finished Jun 30 05:23:13 PM PDT 24
Peak memory 207068 kb
Host smart-def605b8-fe64-4001-b339-538ad8487397
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280869654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.280869654
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1258986174
Short name T976
Test name
Test status
Simulation time 240999242 ps
CPU time 1.35 seconds
Started Jun 30 05:23:12 PM PDT 24
Finished Jun 30 05:23:14 PM PDT 24
Peak memory 217092 kb
Host smart-3ecd3517-d42d-46df-85bb-e421695e1278
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258986174 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1258986174
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1952518950
Short name T690
Test name
Test status
Simulation time 21594722 ps
CPU time 1.09 seconds
Started Jun 30 05:23:10 PM PDT 24
Finished Jun 30 05:23:12 PM PDT 24
Peak memory 224216 kb
Host smart-1dbface9-a1a7-49dd-8d3a-af4ee5ef49cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952518950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1952518950
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1700048765
Short name T498
Test name
Test status
Simulation time 225739128 ps
CPU time 1.54 seconds
Started Jun 30 05:23:10 PM PDT 24
Finished Jun 30 05:23:13 PM PDT 24
Peak memory 218832 kb
Host smart-abb470db-f92e-4b5c-84b4-c75d834ab182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700048765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1700048765
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_smoke.3315682783
Short name T406
Test name
Test status
Simulation time 16902894 ps
CPU time 0.94 seconds
Started Jun 30 05:23:13 PM PDT 24
Finished Jun 30 05:23:15 PM PDT 24
Peak memory 215604 kb
Host smart-3ea09d94-ed2e-492b-a381-f0ab803f8b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315682783 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3315682783
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1709489027
Short name T619
Test name
Test status
Simulation time 23039192 ps
CPU time 0.98 seconds
Started Jun 30 05:23:11 PM PDT 24
Finished Jun 30 05:23:13 PM PDT 24
Peak memory 206720 kb
Host smart-87a01cb7-a74f-4ae9-a615-7ecbff63f9e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709489027 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1709489027
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1018648713
Short name T957
Test name
Test status
Simulation time 171006738114 ps
CPU time 2032.72 seconds
Started Jun 30 05:23:11 PM PDT 24
Finished Jun 30 05:57:06 PM PDT 24
Peak memory 230124 kb
Host smart-501aca66-e570-49bf-982d-b42af4436c23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018648713 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1018648713
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.319792949
Short name T21
Test name
Test status
Simulation time 229974952 ps
CPU time 1.18 seconds
Started Jun 30 05:25:55 PM PDT 24
Finished Jun 30 05:25:59 PM PDT 24
Peak memory 220268 kb
Host smart-b9848306-c95c-44d7-ba9b-ad78fbcfe882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319792949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.319792949
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2985767276
Short name T993
Test name
Test status
Simulation time 193577862 ps
CPU time 1.33 seconds
Started Jun 30 05:25:58 PM PDT 24
Finished Jun 30 05:26:01 PM PDT 24
Peak memory 218708 kb
Host smart-776305f6-9f03-4b58-a094-5783c8aca95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985767276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2985767276
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2447862233
Short name T429
Test name
Test status
Simulation time 92189384 ps
CPU time 1.1 seconds
Started Jun 30 05:25:58 PM PDT 24
Finished Jun 30 05:26:01 PM PDT 24
Peak memory 217632 kb
Host smart-a4bf177e-1755-4d47-8820-877e79799d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447862233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2447862233
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3407724409
Short name T826
Test name
Test status
Simulation time 85754166 ps
CPU time 1.16 seconds
Started Jun 30 05:25:56 PM PDT 24
Finished Jun 30 05:25:59 PM PDT 24
Peak memory 217612 kb
Host smart-b74e820b-d96b-4fce-96cc-1435d386dc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407724409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3407724409
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3715608505
Short name T37
Test name
Test status
Simulation time 47320679 ps
CPU time 1.56 seconds
Started Jun 30 05:25:59 PM PDT 24
Finished Jun 30 05:26:03 PM PDT 24
Peak memory 217836 kb
Host smart-b7b63fc8-0fe2-403e-80d6-036534b93d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715608505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3715608505
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.677875181
Short name T50
Test name
Test status
Simulation time 31346782 ps
CPU time 1.24 seconds
Started Jun 30 05:25:56 PM PDT 24
Finished Jun 30 05:26:00 PM PDT 24
Peak memory 217632 kb
Host smart-0e499ebc-131a-40f7-a56d-a0c91b17cf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677875181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.677875181
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.453504690
Short name T532
Test name
Test status
Simulation time 51124081 ps
CPU time 1.19 seconds
Started Jun 30 05:25:59 PM PDT 24
Finished Jun 30 05:26:03 PM PDT 24
Peak memory 217496 kb
Host smart-4df48542-7bf5-4969-8abb-e2ca7b62a4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453504690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.453504690
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2943887991
Short name T546
Test name
Test status
Simulation time 109987303 ps
CPU time 1.35 seconds
Started Jun 30 05:26:00 PM PDT 24
Finished Jun 30 05:26:04 PM PDT 24
Peak memory 217660 kb
Host smart-6543b27a-2435-411c-8a8e-fad2f1ae91cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943887991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2943887991
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.4146306922
Short name T601
Test name
Test status
Simulation time 36098419 ps
CPU time 1.67 seconds
Started Jun 30 05:26:00 PM PDT 24
Finished Jun 30 05:26:04 PM PDT 24
Peak memory 218968 kb
Host smart-1c868c49-2bcf-49ef-8c47-79cd6347c237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146306922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.4146306922
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1189792388
Short name T392
Test name
Test status
Simulation time 90472978 ps
CPU time 1.25 seconds
Started Jun 30 05:26:05 PM PDT 24
Finished Jun 30 05:26:06 PM PDT 24
Peak memory 217608 kb
Host smart-40042e98-53d7-4f14-9ab8-a9e4886f8793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189792388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1189792388
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert_test.115332829
Short name T743
Test name
Test status
Simulation time 40317514 ps
CPU time 0.84 seconds
Started Jun 30 05:23:08 PM PDT 24
Finished Jun 30 05:23:10 PM PDT 24
Peak memory 214988 kb
Host smart-1c82d212-e417-4b2f-91b2-abbc630e1040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115332829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.115332829
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2239397673
Short name T163
Test name
Test status
Simulation time 21399806 ps
CPU time 0.89 seconds
Started Jun 30 05:23:10 PM PDT 24
Finished Jun 30 05:23:11 PM PDT 24
Peak memory 216564 kb
Host smart-c4fb26a4-53f4-4d79-86e3-2e27f30d8a11
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239397673 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2239397673
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2773696907
Short name T436
Test name
Test status
Simulation time 50772376 ps
CPU time 1.53 seconds
Started Jun 30 05:23:10 PM PDT 24
Finished Jun 30 05:23:12 PM PDT 24
Peak memory 217316 kb
Host smart-27d49f63-caa8-4ccd-b1e1-4d2ac17e1be2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773696907 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2773696907
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.464245581
Short name T980
Test name
Test status
Simulation time 23150161 ps
CPU time 1.06 seconds
Started Jun 30 05:23:11 PM PDT 24
Finished Jun 30 05:23:13 PM PDT 24
Peak memory 224460 kb
Host smart-29163011-aec5-45b3-a840-a32846a29c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464245581 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.464245581
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.235642171
Short name T270
Test name
Test status
Simulation time 57361875 ps
CPU time 2.25 seconds
Started Jun 30 05:23:11 PM PDT 24
Finished Jun 30 05:23:14 PM PDT 24
Peak memory 220284 kb
Host smart-373e2912-5b9e-483c-b68c-2b1e7dd900a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235642171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.235642171
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.196219818
Short name T384
Test name
Test status
Simulation time 24523609 ps
CPU time 0.97 seconds
Started Jun 30 05:23:11 PM PDT 24
Finished Jun 30 05:23:13 PM PDT 24
Peak memory 216020 kb
Host smart-9c4fcf0c-6701-471c-8797-19690b1ff27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196219818 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.196219818
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.1464705946
Short name T868
Test name
Test status
Simulation time 16700796 ps
CPU time 1.01 seconds
Started Jun 30 05:23:11 PM PDT 24
Finished Jun 30 05:23:13 PM PDT 24
Peak memory 215568 kb
Host smart-e3b7610c-862a-458e-b732-589b57131562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464705946 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1464705946
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.340503564
Short name T895
Test name
Test status
Simulation time 96991318 ps
CPU time 1.18 seconds
Started Jun 30 05:23:10 PM PDT 24
Finished Jun 30 05:23:12 PM PDT 24
Peak memory 215604 kb
Host smart-88d4f5fa-d843-4e8c-9318-e4b918619bc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340503564 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.340503564
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1543442116
Short name T295
Test name
Test status
Simulation time 33191114074 ps
CPU time 415.85 seconds
Started Jun 30 05:23:12 PM PDT 24
Finished Jun 30 05:30:09 PM PDT 24
Peak memory 219128 kb
Host smart-d2b2c5d2-cef7-409b-84f6-65a735efd5c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543442116 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1543442116
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3462262914
Short name T387
Test name
Test status
Simulation time 52081296 ps
CPU time 1.2 seconds
Started Jun 30 05:26:34 PM PDT 24
Finished Jun 30 05:26:36 PM PDT 24
Peak memory 220120 kb
Host smart-6993c7d7-88ae-486b-b524-a5f56974814b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462262914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3462262914
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2595094888
Short name T42
Test name
Test status
Simulation time 71443153 ps
CPU time 1.1 seconds
Started Jun 30 05:26:04 PM PDT 24
Finished Jun 30 05:26:06 PM PDT 24
Peak memory 217600 kb
Host smart-b65def7f-08d3-4f1a-a2e1-9fe1a8a5d54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595094888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2595094888
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1695163035
Short name T294
Test name
Test status
Simulation time 73791375 ps
CPU time 1.75 seconds
Started Jun 30 05:25:58 PM PDT 24
Finished Jun 30 05:26:02 PM PDT 24
Peak memory 218864 kb
Host smart-fdd5d70e-a38c-4c1d-a327-d10bcc656539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695163035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1695163035
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3627294655
Short name T467
Test name
Test status
Simulation time 49381555 ps
CPU time 1.18 seconds
Started Jun 30 05:25:59 PM PDT 24
Finished Jun 30 05:26:02 PM PDT 24
Peak memory 218740 kb
Host smart-f121eff9-75d3-43d1-85fd-38fd7a35cf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627294655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3627294655
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.786931062
Short name T729
Test name
Test status
Simulation time 88046901 ps
CPU time 1.96 seconds
Started Jun 30 05:26:03 PM PDT 24
Finished Jun 30 05:26:06 PM PDT 24
Peak memory 218852 kb
Host smart-153bf8d0-3850-4b3c-b328-bfe7b3e5f2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786931062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.786931062
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2695482659
Short name T726
Test name
Test status
Simulation time 41450366 ps
CPU time 2.06 seconds
Started Jun 30 05:26:00 PM PDT 24
Finished Jun 30 05:26:05 PM PDT 24
Peak memory 218812 kb
Host smart-447e0804-cdf5-45df-b024-52f5b5a8ef75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695482659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2695482659
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3970976748
Short name T583
Test name
Test status
Simulation time 54371397 ps
CPU time 1.3 seconds
Started Jun 30 05:26:41 PM PDT 24
Finished Jun 30 05:26:44 PM PDT 24
Peak memory 218684 kb
Host smart-1d94a98a-1f48-4449-b771-acf2eb497bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970976748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3970976748
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1920336131
Short name T717
Test name
Test status
Simulation time 111913379 ps
CPU time 1.29 seconds
Started Jun 30 05:26:03 PM PDT 24
Finished Jun 30 05:26:05 PM PDT 24
Peak memory 219044 kb
Host smart-37e787a4-d5bd-4c47-8d38-387740d1d0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920336131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1920336131
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.540368373
Short name T494
Test name
Test status
Simulation time 200127500 ps
CPU time 2.5 seconds
Started Jun 30 05:26:00 PM PDT 24
Finished Jun 30 05:26:04 PM PDT 24
Peak memory 217712 kb
Host smart-d5d9c254-8bbc-4b68-892e-bb0c84e32094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540368373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.540368373
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2354650792
Short name T416
Test name
Test status
Simulation time 38608139 ps
CPU time 1.37 seconds
Started Jun 30 05:26:02 PM PDT 24
Finished Jun 30 05:26:05 PM PDT 24
Peak memory 220212 kb
Host smart-eec3f2dd-6878-4794-b494-9c8ded3d8820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354650792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2354650792
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.823381801
Short name T90
Test name
Test status
Simulation time 89411052 ps
CPU time 1.28 seconds
Started Jun 30 05:23:22 PM PDT 24
Finished Jun 30 05:23:24 PM PDT 24
Peak memory 220208 kb
Host smart-fab0ad0c-eb5e-4f24-b51e-1f0c02fce2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823381801 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.823381801
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1446230037
Short name T64
Test name
Test status
Simulation time 54602588 ps
CPU time 0.85 seconds
Started Jun 30 05:23:23 PM PDT 24
Finished Jun 30 05:23:24 PM PDT 24
Peak memory 207012 kb
Host smart-4ad602cd-f3c0-4638-9131-a52bbc37796c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446230037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1446230037
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3784750757
Short name T48
Test name
Test status
Simulation time 23535858 ps
CPU time 0.9 seconds
Started Jun 30 05:23:21 PM PDT 24
Finished Jun 30 05:23:22 PM PDT 24
Peak memory 216504 kb
Host smart-e17c414a-579f-4b9a-9c54-9b62f5d79bcd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784750757 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3784750757
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1396024671
Short name T879
Test name
Test status
Simulation time 40252635 ps
CPU time 1.1 seconds
Started Jun 30 05:23:20 PM PDT 24
Finished Jun 30 05:23:22 PM PDT 24
Peak memory 217280 kb
Host smart-c3a77ae5-7619-46b2-8e95-08f2bd115d26
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396024671 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1396024671
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2222202896
Short name T550
Test name
Test status
Simulation time 53688801 ps
CPU time 0.91 seconds
Started Jun 30 05:23:21 PM PDT 24
Finished Jun 30 05:23:23 PM PDT 24
Peak memory 218836 kb
Host smart-bb592004-5b7f-4616-b7ea-ad624219fa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222202896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2222202896
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.403701773
Short name T869
Test name
Test status
Simulation time 27611762 ps
CPU time 1.27 seconds
Started Jun 30 05:23:12 PM PDT 24
Finished Jun 30 05:23:14 PM PDT 24
Peak memory 218860 kb
Host smart-20a17e7a-e216-4090-88ce-a520e838203c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403701773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.403701773
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_smoke.1065878373
Short name T580
Test name
Test status
Simulation time 82492438 ps
CPU time 0.88 seconds
Started Jun 30 05:23:13 PM PDT 24
Finished Jun 30 05:23:15 PM PDT 24
Peak memory 215628 kb
Host smart-9bf70815-a9ba-4ab7-9348-1dcbe42d07ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065878373 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1065878373
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3031732293
Short name T3
Test name
Test status
Simulation time 56315292 ps
CPU time 1.17 seconds
Started Jun 30 05:23:13 PM PDT 24
Finished Jun 30 05:23:15 PM PDT 24
Peak memory 215572 kb
Host smart-fe5c2393-e6d5-409f-89d7-4ab9187b6a03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031732293 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3031732293
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.77919363
Short name T224
Test name
Test status
Simulation time 17183261855 ps
CPU time 387.42 seconds
Started Jun 30 05:23:20 PM PDT 24
Finished Jun 30 05:29:48 PM PDT 24
Peak memory 218140 kb
Host smart-7dd0c913-abd7-4d03-acc9-b22f8a86c05a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77919363 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.77919363
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2525701441
Short name T924
Test name
Test status
Simulation time 48196575 ps
CPU time 1.73 seconds
Started Jun 30 05:26:41 PM PDT 24
Finished Jun 30 05:26:44 PM PDT 24
Peak memory 218500 kb
Host smart-2dd51eb4-22a1-4854-ae33-464a46472409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525701441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2525701441
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3313460457
Short name T949
Test name
Test status
Simulation time 45583789 ps
CPU time 1.37 seconds
Started Jun 30 05:26:03 PM PDT 24
Finished Jun 30 05:26:06 PM PDT 24
Peak memory 217476 kb
Host smart-cd371a19-7b1b-4234-830a-10925a246df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313460457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3313460457
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2806843916
Short name T278
Test name
Test status
Simulation time 61962303 ps
CPU time 2.13 seconds
Started Jun 30 05:26:01 PM PDT 24
Finished Jun 30 05:26:05 PM PDT 24
Peak memory 217964 kb
Host smart-fa9639b7-6cbf-42bf-9fa9-9feffe2a1631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806843916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2806843916
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1684935283
Short name T319
Test name
Test status
Simulation time 38550594 ps
CPU time 1 seconds
Started Jun 30 05:26:03 PM PDT 24
Finished Jun 30 05:26:05 PM PDT 24
Peak memory 216632 kb
Host smart-e85fdd14-6b92-46e5-b547-a8bbbde3adad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684935283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1684935283
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3781234670
Short name T598
Test name
Test status
Simulation time 56269965 ps
CPU time 1.25 seconds
Started Jun 30 05:26:41 PM PDT 24
Finished Jun 30 05:26:44 PM PDT 24
Peak memory 218672 kb
Host smart-5fc89e30-26c2-425a-ab23-b3a9ce47900b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781234670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3781234670
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2882131833
Short name T875
Test name
Test status
Simulation time 93042995 ps
CPU time 1.16 seconds
Started Jun 30 05:25:59 PM PDT 24
Finished Jun 30 05:26:02 PM PDT 24
Peak memory 215644 kb
Host smart-9725bfa9-6b47-47c8-b6b4-884bfef58660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882131833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2882131833
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1388175450
Short name T531
Test name
Test status
Simulation time 150631538 ps
CPU time 2.89 seconds
Started Jun 30 05:26:07 PM PDT 24
Finished Jun 30 05:26:12 PM PDT 24
Peak memory 220244 kb
Host smart-ab0c6efb-102c-46ae-b126-e914883f99c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388175450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1388175450
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2717814900
Short name T604
Test name
Test status
Simulation time 20868888 ps
CPU time 1.03 seconds
Started Jun 30 05:26:07 PM PDT 24
Finished Jun 30 05:26:11 PM PDT 24
Peak memory 217448 kb
Host smart-78e53301-4032-41dd-b74a-cafbd67d7e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717814900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2717814900
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1455079219
Short name T990
Test name
Test status
Simulation time 241088737 ps
CPU time 4.01 seconds
Started Jun 30 05:26:06 PM PDT 24
Finished Jun 30 05:26:11 PM PDT 24
Peak memory 219972 kb
Host smart-6b6b4c29-f1d2-4ce3-ab72-a1353e637845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455079219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1455079219
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3239152883
Short name T906
Test name
Test status
Simulation time 159432731 ps
CPU time 2.64 seconds
Started Jun 30 05:26:11 PM PDT 24
Finished Jun 30 05:26:15 PM PDT 24
Peak memory 220520 kb
Host smart-25554d28-d855-440c-a0be-f24afc0f43f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239152883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3239152883
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.922458010
Short name T386
Test name
Test status
Simulation time 45026047 ps
CPU time 1.22 seconds
Started Jun 30 05:23:19 PM PDT 24
Finished Jun 30 05:23:20 PM PDT 24
Peak memory 220604 kb
Host smart-f3559da0-f659-47f7-85b1-6e6aa9cb190c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922458010 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.922458010
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3292701403
Short name T339
Test name
Test status
Simulation time 11381344 ps
CPU time 0.83 seconds
Started Jun 30 05:23:18 PM PDT 24
Finished Jun 30 05:23:20 PM PDT 24
Peak memory 206796 kb
Host smart-b4ce44c0-0236-436d-b8e2-602ea7beeeb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292701403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3292701403
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2264889207
Short name T52
Test name
Test status
Simulation time 29821187 ps
CPU time 0.83 seconds
Started Jun 30 05:23:21 PM PDT 24
Finished Jun 30 05:23:23 PM PDT 24
Peak memory 215716 kb
Host smart-501d92ef-2702-4c4f-98e5-b233f9a214e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264889207 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2264889207
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.566611874
Short name T141
Test name
Test status
Simulation time 49233573 ps
CPU time 1.46 seconds
Started Jun 30 05:23:20 PM PDT 24
Finished Jun 30 05:23:22 PM PDT 24
Peak memory 217336 kb
Host smart-909b2d69-67b6-4037-afbb-dbcea5ad0bdc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566611874 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.566611874
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.169698622
Short name T56
Test name
Test status
Simulation time 99367520 ps
CPU time 1.16 seconds
Started Jun 30 05:23:19 PM PDT 24
Finished Jun 30 05:23:20 PM PDT 24
Peak memory 226016 kb
Host smart-2756cffd-a536-4cba-b36e-f169db9fd843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169698622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.169698622
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.4162335270
Short name T305
Test name
Test status
Simulation time 52276700 ps
CPU time 1.05 seconds
Started Jun 30 05:23:20 PM PDT 24
Finished Jun 30 05:23:21 PM PDT 24
Peak memory 217640 kb
Host smart-5da67dfc-7d3e-4051-b860-0fe2b6a73eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162335270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.4162335270
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2765401685
Short name T555
Test name
Test status
Simulation time 23832816 ps
CPU time 1.12 seconds
Started Jun 30 05:23:20 PM PDT 24
Finished Jun 30 05:23:21 PM PDT 24
Peak memory 215940 kb
Host smart-6a52faf3-90e4-4061-bc69-4600a8102d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765401685 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2765401685
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2563476024
Short name T725
Test name
Test status
Simulation time 221853020 ps
CPU time 0.97 seconds
Started Jun 30 05:23:21 PM PDT 24
Finished Jun 30 05:23:22 PM PDT 24
Peak memory 215604 kb
Host smart-be7378a4-c57b-43cb-9729-7bc897c0d24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563476024 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2563476024
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2865920678
Short name T917
Test name
Test status
Simulation time 712540502 ps
CPU time 4.32 seconds
Started Jun 30 05:23:20 PM PDT 24
Finished Jun 30 05:23:25 PM PDT 24
Peak memory 218756 kb
Host smart-fc87fb99-8f85-4eae-a3d1-72cef818944e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865920678 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2865920678
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2299300690
Short name T217
Test name
Test status
Simulation time 103081806153 ps
CPU time 1615.82 seconds
Started Jun 30 05:23:19 PM PDT 24
Finished Jun 30 05:50:15 PM PDT 24
Peak memory 225336 kb
Host smart-07a50ed7-aced-40f4-b8d3-5efd6e3dc589
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299300690 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2299300690
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3601743776
Short name T679
Test name
Test status
Simulation time 107908412 ps
CPU time 1.3 seconds
Started Jun 30 05:26:07 PM PDT 24
Finished Jun 30 05:26:10 PM PDT 24
Peak memory 217620 kb
Host smart-b9644f67-7ca6-475b-a922-770f684446af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601743776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3601743776
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.709547050
Short name T683
Test name
Test status
Simulation time 53598515 ps
CPU time 1.28 seconds
Started Jun 30 05:26:10 PM PDT 24
Finished Jun 30 05:26:13 PM PDT 24
Peak memory 217688 kb
Host smart-035a9d5e-f535-40ea-9fbe-ac1539d17888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709547050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.709547050
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2883326753
Short name T74
Test name
Test status
Simulation time 303742818 ps
CPU time 3.04 seconds
Started Jun 30 05:26:06 PM PDT 24
Finished Jun 30 05:26:10 PM PDT 24
Peak memory 218868 kb
Host smart-6becf399-ec34-4353-a9bb-fa314e49949a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883326753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2883326753
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2735402003
Short name T422
Test name
Test status
Simulation time 37362966 ps
CPU time 1.42 seconds
Started Jun 30 05:26:09 PM PDT 24
Finished Jun 30 05:26:12 PM PDT 24
Peak memory 218784 kb
Host smart-5b1c01b7-45c8-4c7f-bf87-f1314e50ed37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735402003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2735402003
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.784401568
Short name T313
Test name
Test status
Simulation time 53729950 ps
CPU time 1.68 seconds
Started Jun 30 05:26:08 PM PDT 24
Finished Jun 30 05:26:12 PM PDT 24
Peak memory 220236 kb
Host smart-76bbf846-e011-47b8-b4b5-2a13e77f0860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784401568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.784401568
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.934324715
Short name T424
Test name
Test status
Simulation time 51237678 ps
CPU time 1.72 seconds
Started Jun 30 05:26:09 PM PDT 24
Finished Jun 30 05:26:13 PM PDT 24
Peak memory 218788 kb
Host smart-abb8dff7-3daa-4e4b-813d-ec6a3c74290f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934324715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.934324715
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2014197791
Short name T934
Test name
Test status
Simulation time 51355141 ps
CPU time 1.18 seconds
Started Jun 30 05:26:08 PM PDT 24
Finished Jun 30 05:26:12 PM PDT 24
Peak memory 218872 kb
Host smart-c28660bc-8a76-4d00-bdec-c448c0957c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014197791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2014197791
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1333288768
Short name T828
Test name
Test status
Simulation time 70208598 ps
CPU time 1.35 seconds
Started Jun 30 05:26:09 PM PDT 24
Finished Jun 30 05:26:13 PM PDT 24
Peak memory 217588 kb
Host smart-17d25543-a963-44ce-bb1e-267e0d7ad150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333288768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1333288768
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.1861471851
Short name T730
Test name
Test status
Simulation time 353360405 ps
CPU time 4.05 seconds
Started Jun 30 05:26:08 PM PDT 24
Finished Jun 30 05:26:14 PM PDT 24
Peak memory 220336 kb
Host smart-3bb53be7-e571-4a1c-b154-20b7c8468951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861471851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1861471851
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1166046131
Short name T410
Test name
Test status
Simulation time 43789383 ps
CPU time 1.23 seconds
Started Jun 30 05:26:08 PM PDT 24
Finished Jun 30 05:26:11 PM PDT 24
Peak memory 217688 kb
Host smart-a9e17416-2b59-4ddf-8256-db97c30bfc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166046131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1166046131
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.3265309242
Short name T670
Test name
Test status
Simulation time 25342595 ps
CPU time 1.2 seconds
Started Jun 30 05:23:21 PM PDT 24
Finished Jun 30 05:23:23 PM PDT 24
Peak memory 220960 kb
Host smart-36a3e716-b073-48ac-8075-41ad77dd84b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265309242 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3265309242
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.62363672
Short name T644
Test name
Test status
Simulation time 20753571 ps
CPU time 0.87 seconds
Started Jun 30 05:23:21 PM PDT 24
Finished Jun 30 05:23:22 PM PDT 24
Peak memory 207096 kb
Host smart-82766b85-ad58-4b55-b05f-30e1a46ec5ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62363672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.62363672
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3821816953
Short name T198
Test name
Test status
Simulation time 34795387 ps
CPU time 0.88 seconds
Started Jun 30 05:23:21 PM PDT 24
Finished Jun 30 05:23:23 PM PDT 24
Peak memory 216564 kb
Host smart-799d25b9-a205-40b2-85d7-c1ab2cbe7523
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821816953 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3821816953
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.2052619620
Short name T627
Test name
Test status
Simulation time 24648623 ps
CPU time 0.94 seconds
Started Jun 30 05:23:19 PM PDT 24
Finished Jun 30 05:23:20 PM PDT 24
Peak memory 218852 kb
Host smart-82936c78-acac-4475-b53c-9de2133a34f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052619620 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2052619620
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3771944726
Short name T358
Test name
Test status
Simulation time 45027316 ps
CPU time 1.13 seconds
Started Jun 30 05:23:20 PM PDT 24
Finished Jun 30 05:23:22 PM PDT 24
Peak memory 220244 kb
Host smart-b9b7eb0e-8346-4732-a2f0-f0a7aa0e785a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771944726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3771944726
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3533485663
Short name T769
Test name
Test status
Simulation time 24117978 ps
CPU time 0.91 seconds
Started Jun 30 05:23:21 PM PDT 24
Finished Jun 30 05:23:23 PM PDT 24
Peak memory 216036 kb
Host smart-d6196d44-7e11-468b-ae15-06293947a57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533485663 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3533485663
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.4040715198
Short name T625
Test name
Test status
Simulation time 68180471 ps
CPU time 0.95 seconds
Started Jun 30 05:23:20 PM PDT 24
Finished Jun 30 05:23:21 PM PDT 24
Peak memory 215624 kb
Host smart-f38db2b2-6c58-4b80-a99c-a26cd26597a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040715198 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.4040715198
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1932356680
Short name T545
Test name
Test status
Simulation time 1186695571 ps
CPU time 4.63 seconds
Started Jun 30 05:23:20 PM PDT 24
Finished Jun 30 05:23:25 PM PDT 24
Peak memory 220076 kb
Host smart-5ed7c1cf-19d7-4e47-90f4-7ac537b08891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932356680 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1932356680
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2435898678
Short name T395
Test name
Test status
Simulation time 205470501812 ps
CPU time 2381.37 seconds
Started Jun 30 05:23:21 PM PDT 24
Finished Jun 30 06:03:04 PM PDT 24
Peak memory 229448 kb
Host smart-ea7d7c7e-07d6-4ea0-b6fc-51bf3774c7ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435898678 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2435898678
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.3278106237
Short name T314
Test name
Test status
Simulation time 79948751 ps
CPU time 1.01 seconds
Started Jun 30 05:26:07 PM PDT 24
Finished Jun 30 05:26:10 PM PDT 24
Peak memory 217784 kb
Host smart-0e136e1c-89b1-4a2c-8976-f5c70f402622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278106237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3278106237
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.558989574
Short name T379
Test name
Test status
Simulation time 42980360 ps
CPU time 1.42 seconds
Started Jun 30 05:26:08 PM PDT 24
Finished Jun 30 05:26:11 PM PDT 24
Peak memory 218912 kb
Host smart-a18449ae-c9ab-4d97-88f4-b85a22d54000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558989574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.558989574
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.755756292
Short name T838
Test name
Test status
Simulation time 54939809 ps
CPU time 1.22 seconds
Started Jun 30 05:26:07 PM PDT 24
Finished Jun 30 05:26:10 PM PDT 24
Peak memory 217664 kb
Host smart-4c49dd90-45fa-4eef-9d79-de124ead074b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755756292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.755756292
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2997086623
Short name T940
Test name
Test status
Simulation time 88324722 ps
CPU time 1.35 seconds
Started Jun 30 05:26:07 PM PDT 24
Finished Jun 30 05:26:10 PM PDT 24
Peak memory 217820 kb
Host smart-82b178a3-00e7-4e1b-a3e0-5d258fce0d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997086623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2997086623
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3970363882
Short name T894
Test name
Test status
Simulation time 44437675 ps
CPU time 1.15 seconds
Started Jun 30 05:26:07 PM PDT 24
Finished Jun 30 05:26:10 PM PDT 24
Peak memory 217792 kb
Host smart-b971f745-d6bf-4e90-90f3-caafcf564d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970363882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3970363882
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.216108825
Short name T51
Test name
Test status
Simulation time 249305608 ps
CPU time 3.42 seconds
Started Jun 30 05:26:06 PM PDT 24
Finished Jun 30 05:26:10 PM PDT 24
Peak memory 218196 kb
Host smart-3e93f9ee-78d6-4e4f-9da6-8403c5e91ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216108825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.216108825
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3595802874
Short name T639
Test name
Test status
Simulation time 121936975 ps
CPU time 1.72 seconds
Started Jun 30 05:26:07 PM PDT 24
Finished Jun 30 05:26:11 PM PDT 24
Peak memory 219044 kb
Host smart-4299d9d8-f7b5-4705-9cf4-842458536d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595802874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3595802874
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.986681650
Short name T904
Test name
Test status
Simulation time 162686577 ps
CPU time 1.27 seconds
Started Jun 30 05:26:11 PM PDT 24
Finished Jun 30 05:26:13 PM PDT 24
Peak memory 220120 kb
Host smart-9bffad57-3db8-4c9c-bd6b-63733ef61a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986681650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.986681650
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1512106008
Short name T323
Test name
Test status
Simulation time 90161537 ps
CPU time 1.16 seconds
Started Jun 30 05:26:08 PM PDT 24
Finished Jun 30 05:26:12 PM PDT 24
Peak memory 217712 kb
Host smart-b065de07-6a2e-44c5-b824-74741bcb131d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512106008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1512106008
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.56168635
Short name T740
Test name
Test status
Simulation time 61355385 ps
CPU time 1.24 seconds
Started Jun 30 05:26:07 PM PDT 24
Finished Jun 30 05:26:09 PM PDT 24
Peak memory 218632 kb
Host smart-ad9c3831-d9c5-4fc6-857b-953fef3e7604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56168635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.56168635
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2247277639
Short name T698
Test name
Test status
Simulation time 24273878 ps
CPU time 1.22 seconds
Started Jun 30 05:21:55 PM PDT 24
Finished Jun 30 05:21:57 PM PDT 24
Peak memory 219896 kb
Host smart-4013b1ad-70b6-4444-82fe-735aac4c5793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247277639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2247277639
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1018693126
Short name T820
Test name
Test status
Simulation time 22111028 ps
CPU time 0.89 seconds
Started Jun 30 05:21:52 PM PDT 24
Finished Jun 30 05:21:54 PM PDT 24
Peak memory 215068 kb
Host smart-43380da0-6ca8-4d96-80ff-219dc5f85cdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018693126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1018693126
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.800062737
Short name T737
Test name
Test status
Simulation time 43398981 ps
CPU time 0.87 seconds
Started Jun 30 05:21:54 PM PDT 24
Finished Jun 30 05:21:55 PM PDT 24
Peak memory 215632 kb
Host smart-1ab3c4a2-f6f9-4569-aa35-86c4480e604b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800062737 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.800062737
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2241624826
Short name T490
Test name
Test status
Simulation time 46991638 ps
CPU time 1.17 seconds
Started Jun 30 05:21:53 PM PDT 24
Finished Jun 30 05:21:54 PM PDT 24
Peak memory 217300 kb
Host smart-fb9d7b6e-aa5b-41f5-a1cf-0970efd403a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241624826 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2241624826
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2186883925
Short name T642
Test name
Test status
Simulation time 40152893 ps
CPU time 0.87 seconds
Started Jun 30 05:21:53 PM PDT 24
Finished Jun 30 05:21:54 PM PDT 24
Peak memory 218460 kb
Host smart-2aa3956a-90df-4676-b016-ca3dc29c4c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186883925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2186883925
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.4202399758
Short name T82
Test name
Test status
Simulation time 104639681 ps
CPU time 1.44 seconds
Started Jun 30 05:21:55 PM PDT 24
Finished Jun 30 05:21:56 PM PDT 24
Peak memory 217264 kb
Host smart-772f5aad-f224-460e-8d5b-8b131f9aa206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202399758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.4202399758
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3244577945
Short name T32
Test name
Test status
Simulation time 20923783 ps
CPU time 1.09 seconds
Started Jun 30 05:21:53 PM PDT 24
Finished Jun 30 05:21:54 PM PDT 24
Peak memory 216160 kb
Host smart-742d454f-5a19-481d-919a-513459190a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244577945 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3244577945
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.900116352
Short name T522
Test name
Test status
Simulation time 50036392 ps
CPU time 0.97 seconds
Started Jun 30 05:21:55 PM PDT 24
Finished Jun 30 05:21:56 PM PDT 24
Peak memory 207352 kb
Host smart-51322d5c-074b-4584-9611-76ca48ebbf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900116352 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.900116352
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1765738713
Short name T18
Test name
Test status
Simulation time 488713822 ps
CPU time 8.17 seconds
Started Jun 30 05:21:51 PM PDT 24
Finished Jun 30 05:22:00 PM PDT 24
Peak memory 237368 kb
Host smart-cf25046a-8959-42ed-9278-06edd92fe512
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765738713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1765738713
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3652343229
Short name T662
Test name
Test status
Simulation time 29341799 ps
CPU time 0.98 seconds
Started Jun 30 05:21:52 PM PDT 24
Finished Jun 30 05:21:54 PM PDT 24
Peak memory 215612 kb
Host smart-d5a2c010-34fe-4f7e-b663-5f4838f80371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652343229 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3652343229
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1811108616
Short name T764
Test name
Test status
Simulation time 548666179 ps
CPU time 5.56 seconds
Started Jun 30 05:21:54 PM PDT 24
Finished Jun 30 05:22:00 PM PDT 24
Peak memory 217368 kb
Host smart-a726d3a0-21fd-45a8-ba91-59afb314dce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811108616 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1811108616
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.4099588397
Short name T671
Test name
Test status
Simulation time 304058761974 ps
CPU time 1513.49 seconds
Started Jun 30 05:21:53 PM PDT 24
Finished Jun 30 05:47:07 PM PDT 24
Peak memory 225020 kb
Host smart-eb6f09ba-57c8-4bbd-8255-43a31e814f18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099588397 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.4099588397
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1465493334
Short name T843
Test name
Test status
Simulation time 94643445 ps
CPU time 1.19 seconds
Started Jun 30 05:23:30 PM PDT 24
Finished Jun 30 05:23:31 PM PDT 24
Peak memory 215992 kb
Host smart-3e4cedf2-6cba-4ab5-b727-fc8d23de6e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465493334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1465493334
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.138920649
Short name T821
Test name
Test status
Simulation time 51796669 ps
CPU time 1.11 seconds
Started Jun 30 05:23:26 PM PDT 24
Finished Jun 30 05:23:28 PM PDT 24
Peak memory 207128 kb
Host smart-2d62a9c8-38f3-433a-8175-5ca96d80771f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138920649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.138920649
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3770388974
Short name T710
Test name
Test status
Simulation time 27981892 ps
CPU time 0.86 seconds
Started Jun 30 05:23:29 PM PDT 24
Finished Jun 30 05:23:31 PM PDT 24
Peak memory 216160 kb
Host smart-43c67827-c283-4dd3-96b5-9f33f4d1eb77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770388974 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3770388974
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.701737944
Short name T736
Test name
Test status
Simulation time 30064396 ps
CPU time 1.14 seconds
Started Jun 30 05:23:26 PM PDT 24
Finished Jun 30 05:23:27 PM PDT 24
Peak memory 215792 kb
Host smart-deb12d55-b790-4012-b4f8-1285ed446aaa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701737944 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.701737944
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.2776223643
Short name T739
Test name
Test status
Simulation time 35519911 ps
CPU time 0.9 seconds
Started Jun 30 05:23:30 PM PDT 24
Finished Jun 30 05:23:31 PM PDT 24
Peak memory 219872 kb
Host smart-0e4fc54a-03ee-45e5-99e7-c305b1b26646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776223643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2776223643
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3271679763
Short name T291
Test name
Test status
Simulation time 45753099 ps
CPU time 1.4 seconds
Started Jun 30 05:23:29 PM PDT 24
Finished Jun 30 05:23:31 PM PDT 24
Peak memory 218600 kb
Host smart-918af057-c3b2-4109-9424-46dc4c23c1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271679763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3271679763
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1109228013
Short name T651
Test name
Test status
Simulation time 26214002 ps
CPU time 0.92 seconds
Started Jun 30 05:23:29 PM PDT 24
Finished Jun 30 05:23:31 PM PDT 24
Peak memory 216224 kb
Host smart-e7d948d3-9cbb-4e93-a277-1f13ab706eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109228013 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1109228013
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2934626926
Short name T322
Test name
Test status
Simulation time 54172161 ps
CPU time 0.91 seconds
Started Jun 30 05:23:28 PM PDT 24
Finished Jun 30 05:23:29 PM PDT 24
Peak memory 215616 kb
Host smart-61de973e-3d0d-45cb-83a4-d7912fdcd4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934626926 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2934626926
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3674587029
Short name T476
Test name
Test status
Simulation time 443135839 ps
CPU time 4.86 seconds
Started Jun 30 05:23:26 PM PDT 24
Finished Jun 30 05:23:31 PM PDT 24
Peak memory 215680 kb
Host smart-a3e1d62c-f5ad-494d-8d00-ba7ad12c15c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674587029 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3674587029
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.4046754934
Short name T341
Test name
Test status
Simulation time 37375271213 ps
CPU time 526.35 seconds
Started Jun 30 05:23:26 PM PDT 24
Finished Jun 30 05:32:12 PM PDT 24
Peak memory 218668 kb
Host smart-0534cb51-87dd-4e0d-a968-8e5d47636693
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046754934 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.4046754934
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1468664636
Short name T697
Test name
Test status
Simulation time 36189033 ps
CPU time 1.28 seconds
Started Jun 30 05:23:25 PM PDT 24
Finished Jun 30 05:23:27 PM PDT 24
Peak memory 219776 kb
Host smart-cb89f6ca-61e1-4206-85f4-97d615e68e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468664636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1468664636
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3588636019
Short name T390
Test name
Test status
Simulation time 125543115 ps
CPU time 0.92 seconds
Started Jun 30 05:23:29 PM PDT 24
Finished Jun 30 05:23:31 PM PDT 24
Peak memory 215100 kb
Host smart-f78e4328-523e-4cfa-abfa-bb245d555dca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588636019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3588636019
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2646456318
Short name T187
Test name
Test status
Simulation time 15640051 ps
CPU time 0.83 seconds
Started Jun 30 05:23:27 PM PDT 24
Finished Jun 30 05:23:28 PM PDT 24
Peak memory 216520 kb
Host smart-f35f0576-3d09-4837-aeb0-2a196190835a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646456318 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2646456318
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1079205572
Short name T620
Test name
Test status
Simulation time 24595922 ps
CPU time 1.09 seconds
Started Jun 30 05:23:25 PM PDT 24
Finished Jun 30 05:23:27 PM PDT 24
Peak memory 218608 kb
Host smart-cc6b8547-33ca-4349-b3bc-e654c896fd6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079205572 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1079205572
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2146998920
Short name T107
Test name
Test status
Simulation time 21030901 ps
CPU time 1.22 seconds
Started Jun 30 05:23:29 PM PDT 24
Finished Jun 30 05:23:30 PM PDT 24
Peak memory 229808 kb
Host smart-45ecf80c-72dd-4c28-9672-c0031f4ed4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146998920 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2146998920
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3912188837
Short name T893
Test name
Test status
Simulation time 35498632 ps
CPU time 1.36 seconds
Started Jun 30 05:23:29 PM PDT 24
Finished Jun 30 05:23:31 PM PDT 24
Peak memory 218764 kb
Host smart-6f22e7dd-9b8a-4ee3-b27b-20e0b61100c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912188837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3912188837
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1227555319
Short name T33
Test name
Test status
Simulation time 31943068 ps
CPU time 0.89 seconds
Started Jun 30 05:23:26 PM PDT 24
Finished Jun 30 05:23:27 PM PDT 24
Peak memory 216148 kb
Host smart-d3741515-7313-4ddf-8da0-099bcec18de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227555319 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1227555319
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3827096305
Short name T864
Test name
Test status
Simulation time 15476325 ps
CPU time 0.96 seconds
Started Jun 30 05:23:25 PM PDT 24
Finished Jun 30 05:23:26 PM PDT 24
Peak memory 215612 kb
Host smart-9397e1e3-9664-4b67-a8df-1aee08f09e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827096305 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3827096305
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1182172369
Short name T765
Test name
Test status
Simulation time 496029891 ps
CPU time 5.37 seconds
Started Jun 30 05:23:30 PM PDT 24
Finished Jun 30 05:23:36 PM PDT 24
Peak memory 215644 kb
Host smart-81e495d4-869a-4051-8815-a5aa364e6957
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182172369 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1182172369
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3093234406
Short name T35
Test name
Test status
Simulation time 112819573019 ps
CPU time 777.38 seconds
Started Jun 30 05:23:27 PM PDT 24
Finished Jun 30 05:36:25 PM PDT 24
Peak memory 224016 kb
Host smart-8178c50c-df64-4ccd-b306-843e8d0d0c9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093234406 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3093234406
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3785063506
Short name T500
Test name
Test status
Simulation time 44800404 ps
CPU time 1.12 seconds
Started Jun 30 05:23:30 PM PDT 24
Finished Jun 30 05:23:32 PM PDT 24
Peak memory 220996 kb
Host smart-02f4cec0-73d1-4919-8d3b-40106502205a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785063506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3785063506
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2597880014
Short name T676
Test name
Test status
Simulation time 12284713 ps
CPU time 0.89 seconds
Started Jun 30 05:23:35 PM PDT 24
Finished Jun 30 05:23:36 PM PDT 24
Peak memory 207220 kb
Host smart-77266388-832e-4403-b65b-5b0d710a98f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597880014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2597880014
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3622359682
Short name T963
Test name
Test status
Simulation time 25810601 ps
CPU time 0.89 seconds
Started Jun 30 05:23:36 PM PDT 24
Finished Jun 30 05:23:38 PM PDT 24
Peak memory 216428 kb
Host smart-337a2fb1-2d43-4611-a39e-d45db6d08b47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622359682 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3622359682
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3133657792
Short name T573
Test name
Test status
Simulation time 38711840 ps
CPU time 1.35 seconds
Started Jun 30 05:23:34 PM PDT 24
Finished Jun 30 05:23:36 PM PDT 24
Peak memory 218828 kb
Host smart-3d69aeaa-f0cf-431b-b636-c728af2aa502
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133657792 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3133657792
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.1054217145
Short name T112
Test name
Test status
Simulation time 40817060 ps
CPU time 1.07 seconds
Started Jun 30 05:23:36 PM PDT 24
Finished Jun 30 05:23:38 PM PDT 24
Peak memory 229592 kb
Host smart-f4ba8982-9e97-4a5d-9b4b-af96d7b17761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054217145 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1054217145
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3257157855
Short name T664
Test name
Test status
Simulation time 54873283 ps
CPU time 1.32 seconds
Started Jun 30 05:23:30 PM PDT 24
Finished Jun 30 05:23:32 PM PDT 24
Peak memory 218720 kb
Host smart-a8312fcd-5ce7-4f84-bdd8-5315fd2d1d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257157855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3257157855
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.28365460
Short name T491
Test name
Test status
Simulation time 34469963 ps
CPU time 1.04 seconds
Started Jun 30 05:23:27 PM PDT 24
Finished Jun 30 05:23:28 PM PDT 24
Peak memory 224356 kb
Host smart-6aaf4559-94a8-4244-afea-6e674bec7f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28365460 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.28365460
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.722264383
Short name T788
Test name
Test status
Simulation time 48598539 ps
CPU time 0.95 seconds
Started Jun 30 05:23:27 PM PDT 24
Finished Jun 30 05:23:28 PM PDT 24
Peak memory 215580 kb
Host smart-45852c72-6249-41ff-a80d-12c75370c4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722264383 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.722264383
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.485245465
Short name T776
Test name
Test status
Simulation time 914698912 ps
CPU time 4.17 seconds
Started Jun 30 05:23:25 PM PDT 24
Finished Jun 30 05:23:30 PM PDT 24
Peak memory 215608 kb
Host smart-ca261855-69b3-4c40-9b80-547683336d66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485245465 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.485245465
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.627757865
Short name T36
Test name
Test status
Simulation time 190291787846 ps
CPU time 1272.36 seconds
Started Jun 30 05:23:29 PM PDT 24
Finished Jun 30 05:44:42 PM PDT 24
Peak memory 224204 kb
Host smart-e5546e54-cacd-4dd5-a9bf-cb2421400f58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627757865 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.627757865
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.4284332500
Short name T484
Test name
Test status
Simulation time 37894159 ps
CPU time 1.26 seconds
Started Jun 30 05:23:34 PM PDT 24
Finished Jun 30 05:23:35 PM PDT 24
Peak memory 219988 kb
Host smart-4305e890-54dc-4b96-a3d5-8ed16c2c8c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284332500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.4284332500
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3181493524
Short name T813
Test name
Test status
Simulation time 102224204 ps
CPU time 0.91 seconds
Started Jun 30 05:23:35 PM PDT 24
Finished Jun 30 05:23:37 PM PDT 24
Peak memory 214888 kb
Host smart-c5e44d30-88de-4cc3-b7f3-a8dd0adb6fda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181493524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3181493524
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.565011294
Short name T203
Test name
Test status
Simulation time 30859528 ps
CPU time 0.86 seconds
Started Jun 30 05:23:33 PM PDT 24
Finished Jun 30 05:23:35 PM PDT 24
Peak memory 216560 kb
Host smart-9bbfdb92-0f30-4104-a7fd-2c808b161c33
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565011294 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.565011294
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1687486101
Short name T142
Test name
Test status
Simulation time 113580593 ps
CPU time 1.25 seconds
Started Jun 30 05:23:34 PM PDT 24
Finished Jun 30 05:23:36 PM PDT 24
Peak memory 217232 kb
Host smart-253ff00a-528d-45cb-8236-bf31375b4a0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687486101 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1687486101
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1176374575
Short name T507
Test name
Test status
Simulation time 34720000 ps
CPU time 0.9 seconds
Started Jun 30 05:23:34 PM PDT 24
Finished Jun 30 05:23:36 PM PDT 24
Peak memory 218612 kb
Host smart-961a87b9-6296-4db2-bcf6-cc717b0a6cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176374575 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1176374575
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_intr.2874729810
Short name T100
Test name
Test status
Simulation time 20521478 ps
CPU time 1.07 seconds
Started Jun 30 05:23:33 PM PDT 24
Finished Jun 30 05:23:34 PM PDT 24
Peak memory 216056 kb
Host smart-c720eeef-124f-40cc-a166-abd9c6bf8843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874729810 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2874729810
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2769479317
Short name T394
Test name
Test status
Simulation time 56230441 ps
CPU time 0.93 seconds
Started Jun 30 05:23:34 PM PDT 24
Finished Jun 30 05:23:36 PM PDT 24
Peak memory 215420 kb
Host smart-56c98e1a-1791-4d45-b9e0-ca30920b335c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769479317 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2769479317
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1080897712
Short name T661
Test name
Test status
Simulation time 80745036 ps
CPU time 2.2 seconds
Started Jun 30 05:23:35 PM PDT 24
Finished Jun 30 05:23:37 PM PDT 24
Peak memory 217616 kb
Host smart-6c44b55d-8569-4cf8-be11-444eba6a255a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080897712 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1080897712
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3088485972
Short name T213
Test name
Test status
Simulation time 56186166099 ps
CPU time 538.43 seconds
Started Jun 30 05:23:34 PM PDT 24
Finished Jun 30 05:32:33 PM PDT 24
Peak memory 218564 kb
Host smart-9a80b88d-4086-43ef-9262-eec13af4c4b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088485972 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3088485972
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2710206480
Short name T176
Test name
Test status
Simulation time 33754477 ps
CPU time 1.28 seconds
Started Jun 30 05:23:36 PM PDT 24
Finished Jun 30 05:23:38 PM PDT 24
Peak memory 220068 kb
Host smart-6b724f96-e3f2-43fa-a572-be9426f438ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710206480 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2710206480
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.928903335
Short name T577
Test name
Test status
Simulation time 43800279 ps
CPU time 0.85 seconds
Started Jun 30 05:23:39 PM PDT 24
Finished Jun 30 05:23:40 PM PDT 24
Peak memory 207044 kb
Host smart-9e99adac-9e34-4ac8-baac-dfed4e50aa43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928903335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.928903335
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.466283531
Short name T979
Test name
Test status
Simulation time 17715207 ps
CPU time 0.85 seconds
Started Jun 30 05:23:39 PM PDT 24
Finished Jun 30 05:23:40 PM PDT 24
Peak memory 215692 kb
Host smart-b5cf82e7-75ee-420a-bf70-c7b0defd169e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466283531 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.466283531
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1697388217
Short name T40
Test name
Test status
Simulation time 54630857 ps
CPU time 1.16 seconds
Started Jun 30 05:23:43 PM PDT 24
Finished Jun 30 05:23:45 PM PDT 24
Peak memory 217380 kb
Host smart-83e8286e-6feb-46bb-9a34-9c22dfa0b0a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697388217 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1697388217
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2693147586
Short name T916
Test name
Test status
Simulation time 23502205 ps
CPU time 0.98 seconds
Started Jun 30 05:23:32 PM PDT 24
Finished Jun 30 05:23:34 PM PDT 24
Peak memory 218776 kb
Host smart-b17e5d04-04f6-4523-a8c1-15d2e476dfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693147586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2693147586
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2450704405
Short name T292
Test name
Test status
Simulation time 59114819 ps
CPU time 2.03 seconds
Started Jun 30 05:23:33 PM PDT 24
Finished Jun 30 05:23:35 PM PDT 24
Peak memory 218652 kb
Host smart-ce6dadc2-b58a-4fe6-9220-a9eb69b4077c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450704405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2450704405
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.456538271
Short name T504
Test name
Test status
Simulation time 28638044 ps
CPU time 0.98 seconds
Started Jun 30 05:23:33 PM PDT 24
Finished Jun 30 05:23:35 PM PDT 24
Peak memory 215800 kb
Host smart-42cdc834-c4a8-4bfb-a57e-a1950f1fb749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456538271 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.456538271
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2810001690
Short name T974
Test name
Test status
Simulation time 50630280 ps
CPU time 0.92 seconds
Started Jun 30 05:23:35 PM PDT 24
Finished Jun 30 05:23:36 PM PDT 24
Peak memory 215596 kb
Host smart-7cff4ed3-05c6-411c-ae62-7312a6d16f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810001690 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2810001690
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3999006822
Short name T425
Test name
Test status
Simulation time 214549960 ps
CPU time 4.54 seconds
Started Jun 30 05:23:34 PM PDT 24
Finished Jun 30 05:23:38 PM PDT 24
Peak memory 220284 kb
Host smart-8f0ff153-0fdb-4efa-a077-051c933422be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999006822 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3999006822
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_alert.4123648329
Short name T856
Test name
Test status
Simulation time 33273579 ps
CPU time 1.18 seconds
Started Jun 30 05:23:41 PM PDT 24
Finished Jun 30 05:23:42 PM PDT 24
Peak memory 219828 kb
Host smart-86e9b150-ebdc-4b7a-abfd-a027261eefb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123648329 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.4123648329
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1505900849
Short name T817
Test name
Test status
Simulation time 23710277 ps
CPU time 0.87 seconds
Started Jun 30 05:23:41 PM PDT 24
Finished Jun 30 05:23:42 PM PDT 24
Peak memory 206964 kb
Host smart-49c863b2-a620-408b-8e1c-e11c1f42cf43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505900849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1505900849
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3318118034
Short name T970
Test name
Test status
Simulation time 96514544 ps
CPU time 1.18 seconds
Started Jun 30 05:23:42 PM PDT 24
Finished Jun 30 05:23:43 PM PDT 24
Peak memory 217308 kb
Host smart-c46cab6e-36aa-43ee-87e9-e42e814e30e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318118034 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3318118034
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2482585791
Short name T168
Test name
Test status
Simulation time 19827086 ps
CPU time 1.09 seconds
Started Jun 30 05:23:42 PM PDT 24
Finished Jun 30 05:23:44 PM PDT 24
Peak memory 218740 kb
Host smart-dcf871eb-2aee-4030-9255-e4a33d052e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482585791 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2482585791
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3875515889
Short name T423
Test name
Test status
Simulation time 45666088 ps
CPU time 1.06 seconds
Started Jun 30 05:23:52 PM PDT 24
Finished Jun 30 05:23:54 PM PDT 24
Peak memory 217424 kb
Host smart-3f8e5578-4589-4b18-a625-1b9a3c1541c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875515889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3875515889
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1043841769
Short name T667
Test name
Test status
Simulation time 22273878 ps
CPU time 1.18 seconds
Started Jun 30 05:23:52 PM PDT 24
Finished Jun 30 05:23:53 PM PDT 24
Peak memory 215704 kb
Host smart-fa1a02e1-676f-47af-b814-93089f284b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043841769 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1043841769
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.335195379
Short name T913
Test name
Test status
Simulation time 22673190 ps
CPU time 0.95 seconds
Started Jun 30 05:23:42 PM PDT 24
Finished Jun 30 05:23:44 PM PDT 24
Peak memory 215620 kb
Host smart-5964dae5-e360-4abb-b2f0-4d94d4ae48ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335195379 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.335195379
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.3491251696
Short name T950
Test name
Test status
Simulation time 569820111 ps
CPU time 2.25 seconds
Started Jun 30 05:23:42 PM PDT 24
Finished Jun 30 05:23:44 PM PDT 24
Peak memory 217452 kb
Host smart-3b682519-d1cc-4491-a3ca-f75e2502d2f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491251696 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3491251696
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.4094253891
Short name T218
Test name
Test status
Simulation time 278500680719 ps
CPU time 2511.87 seconds
Started Jun 30 05:23:52 PM PDT 24
Finished Jun 30 06:05:44 PM PDT 24
Peak memory 228560 kb
Host smart-7a831a06-ede2-429b-990d-ae54f130a082
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094253891 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.4094253891
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2828978984
Short name T873
Test name
Test status
Simulation time 31243904 ps
CPU time 1.27 seconds
Started Jun 30 05:23:40 PM PDT 24
Finished Jun 30 05:23:42 PM PDT 24
Peak memory 219680 kb
Host smart-18009e8f-0b24-45f0-b59d-a600708ec260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828978984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2828978984
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.240429164
Short name T936
Test name
Test status
Simulation time 41497288 ps
CPU time 1.29 seconds
Started Jun 30 05:23:49 PM PDT 24
Finished Jun 30 05:23:51 PM PDT 24
Peak memory 207168 kb
Host smart-34335d76-2223-48b6-ba45-db25419c7787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240429164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.240429164
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2348181500
Short name T174
Test name
Test status
Simulation time 24327833 ps
CPU time 0.83 seconds
Started Jun 30 05:23:40 PM PDT 24
Finished Jun 30 05:23:41 PM PDT 24
Peak memory 216560 kb
Host smart-4b6d3c0f-be14-47b8-b1b6-6711dc3e0df3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348181500 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2348181500
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1838239964
Short name T356
Test name
Test status
Simulation time 19922006 ps
CPU time 1.01 seconds
Started Jun 30 05:23:49 PM PDT 24
Finished Jun 30 05:23:51 PM PDT 24
Peak memory 218460 kb
Host smart-2c8a193e-b0da-4242-b71e-8e4a01c080a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838239964 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1838239964
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1977956180
Short name T640
Test name
Test status
Simulation time 51068798 ps
CPU time 0.92 seconds
Started Jun 30 05:23:40 PM PDT 24
Finished Jun 30 05:23:41 PM PDT 24
Peak memory 218952 kb
Host smart-aff450ba-88d8-4fa7-9074-6e078abfdf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977956180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1977956180
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3428069830
Short name T660
Test name
Test status
Simulation time 31772258 ps
CPU time 1.46 seconds
Started Jun 30 05:23:40 PM PDT 24
Finished Jun 30 05:23:42 PM PDT 24
Peak memory 217852 kb
Host smart-7c26e92f-c402-4d7a-bdb4-a7fd8e87f4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428069830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3428069830
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3569649980
Short name T31
Test name
Test status
Simulation time 25265909 ps
CPU time 0.95 seconds
Started Jun 30 05:23:41 PM PDT 24
Finished Jun 30 05:23:42 PM PDT 24
Peak memory 216140 kb
Host smart-70a72b19-9b9f-4216-8a99-7ea4c3e59503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569649980 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3569649980
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.610035844
Short name T680
Test name
Test status
Simulation time 26631440 ps
CPU time 0.94 seconds
Started Jun 30 05:23:52 PM PDT 24
Finished Jun 30 05:23:53 PM PDT 24
Peak memory 215464 kb
Host smart-dcbced6c-d473-455e-863e-d949dbe606e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610035844 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.610035844
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2630798547
Short name T926
Test name
Test status
Simulation time 373492553 ps
CPU time 2.6 seconds
Started Jun 30 05:23:42 PM PDT 24
Finished Jun 30 05:23:45 PM PDT 24
Peak memory 215700 kb
Host smart-67f8ced9-e756-4ca0-b49c-bcc69ac40802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630798547 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2630798547
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2038905068
Short name T733
Test name
Test status
Simulation time 20199570801 ps
CPU time 427.9 seconds
Started Jun 30 05:23:52 PM PDT 24
Finished Jun 30 05:31:00 PM PDT 24
Peak memory 217212 kb
Host smart-89d3b52a-2dff-41d6-b2d7-dda69aa313fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038905068 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2038905068
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1089525552
Short name T502
Test name
Test status
Simulation time 201363837 ps
CPU time 1.28 seconds
Started Jun 30 05:23:47 PM PDT 24
Finished Jun 30 05:23:49 PM PDT 24
Peak memory 218872 kb
Host smart-54b43938-a3b5-4cc4-b0e6-b90974711f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089525552 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1089525552
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2098941878
Short name T819
Test name
Test status
Simulation time 16936286 ps
CPU time 0.92 seconds
Started Jun 30 05:23:48 PM PDT 24
Finished Jun 30 05:23:50 PM PDT 24
Peak memory 207064 kb
Host smart-afa1101f-bb2c-4fa4-83e2-d7bf31e5f570
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098941878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2098941878
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2069428605
Short name T854
Test name
Test status
Simulation time 19578537 ps
CPU time 0.92 seconds
Started Jun 30 05:23:48 PM PDT 24
Finished Jun 30 05:23:49 PM PDT 24
Peak memory 216820 kb
Host smart-fcd91e78-7e08-49a3-8da3-5e29753730fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069428605 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2069428605
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1293995223
Short name T905
Test name
Test status
Simulation time 39249447 ps
CPU time 1.06 seconds
Started Jun 30 05:23:49 PM PDT 24
Finished Jun 30 05:23:51 PM PDT 24
Peak memory 217232 kb
Host smart-06abc330-3b89-4921-9485-f428e6a80ea7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293995223 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1293995223
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.280682312
Short name T159
Test name
Test status
Simulation time 23896844 ps
CPU time 0.93 seconds
Started Jun 30 05:23:49 PM PDT 24
Finished Jun 30 05:23:50 PM PDT 24
Peak memory 218620 kb
Host smart-b40e66d4-303a-4c69-875b-6b3636423794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280682312 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.280682312
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.227059954
Short name T628
Test name
Test status
Simulation time 214356791 ps
CPU time 0.99 seconds
Started Jun 30 05:23:47 PM PDT 24
Finished Jun 30 05:23:49 PM PDT 24
Peak memory 217676 kb
Host smart-97adec9a-9a0d-430f-8bd1-d09c489dda55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227059954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.227059954
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3335352848
Short name T99
Test name
Test status
Simulation time 56724793 ps
CPU time 1 seconds
Started Jun 30 05:23:48 PM PDT 24
Finished Jun 30 05:23:50 PM PDT 24
Peak memory 216112 kb
Host smart-b3c821bf-f461-4d04-9331-ddb86be40f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335352848 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3335352848
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.617464309
Short name T884
Test name
Test status
Simulation time 16119720 ps
CPU time 0.95 seconds
Started Jun 30 05:23:49 PM PDT 24
Finished Jun 30 05:23:50 PM PDT 24
Peak memory 215596 kb
Host smart-ab9877d2-fc30-4258-bf02-b248937363ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617464309 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.617464309
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1194934047
Short name T839
Test name
Test status
Simulation time 181029114 ps
CPU time 1.61 seconds
Started Jun 30 05:23:48 PM PDT 24
Finished Jun 30 05:23:50 PM PDT 24
Peak memory 217756 kb
Host smart-1e603ee4-7d36-4ccd-8438-5e0adc630931
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194934047 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1194934047
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1183148336
Short name T594
Test name
Test status
Simulation time 53477262653 ps
CPU time 1356.14 seconds
Started Jun 30 05:23:48 PM PDT 24
Finished Jun 30 05:46:25 PM PDT 24
Peak memory 223716 kb
Host smart-8fa9b24c-086b-47f3-a182-9cbd5db40ec3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183148336 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1183148336
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert_test.3853403641
Short name T647
Test name
Test status
Simulation time 15497292 ps
CPU time 0.92 seconds
Started Jun 30 05:23:48 PM PDT 24
Finished Jun 30 05:23:49 PM PDT 24
Peak memory 215196 kb
Host smart-ebadbd87-dcad-484c-9024-f6d504dd976a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853403641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3853403641
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3723194977
Short name T882
Test name
Test status
Simulation time 34580500 ps
CPU time 0.88 seconds
Started Jun 30 05:23:48 PM PDT 24
Finished Jun 30 05:23:50 PM PDT 24
Peak memory 216536 kb
Host smart-b00534f4-752e-44a8-addf-9a76877eeebf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723194977 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3723194977
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.633429791
Short name T114
Test name
Test status
Simulation time 24476511 ps
CPU time 1.01 seconds
Started Jun 30 05:23:46 PM PDT 24
Finished Jun 30 05:23:48 PM PDT 24
Peak memory 217176 kb
Host smart-8638f2c8-959c-460c-a3a5-d91f3669e736
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633429791 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.633429791
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1278197007
Short name T144
Test name
Test status
Simulation time 31752589 ps
CPU time 0.88 seconds
Started Jun 30 05:23:46 PM PDT 24
Finished Jun 30 05:23:48 PM PDT 24
Peak memory 218460 kb
Host smart-9d682b65-0513-4019-ba99-de8b51274378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278197007 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1278197007
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.35741742
Short name T495
Test name
Test status
Simulation time 71436716 ps
CPU time 1.41 seconds
Started Jun 30 05:23:50 PM PDT 24
Finished Jun 30 05:23:52 PM PDT 24
Peak memory 218780 kb
Host smart-dfc20bca-6d8d-4788-925c-379f59eb6f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35741742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.35741742
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2050833229
Short name T528
Test name
Test status
Simulation time 22285170 ps
CPU time 1.09 seconds
Started Jun 30 05:23:49 PM PDT 24
Finished Jun 30 05:23:51 PM PDT 24
Peak memory 215792 kb
Host smart-168aa627-8089-494f-96f0-9abb397a2105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050833229 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2050833229
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.225608747
Short name T317
Test name
Test status
Simulation time 130861640 ps
CPU time 0.95 seconds
Started Jun 30 05:23:45 PM PDT 24
Finished Jun 30 05:23:46 PM PDT 24
Peak memory 215572 kb
Host smart-1481c097-27c3-43cd-b8a5-ea432420cfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225608747 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.225608747
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.279389652
Short name T831
Test name
Test status
Simulation time 99300624 ps
CPU time 2.4 seconds
Started Jun 30 05:23:47 PM PDT 24
Finished Jun 30 05:23:50 PM PDT 24
Peak memory 215664 kb
Host smart-4af66f21-020f-49a1-922a-0b9edfc52a81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279389652 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.279389652
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2791209353
Short name T214
Test name
Test status
Simulation time 27223490493 ps
CPU time 637.42 seconds
Started Jun 30 05:23:47 PM PDT 24
Finished Jun 30 05:34:25 PM PDT 24
Peak memory 217888 kb
Host smart-15b09d9a-15b8-4778-8356-3aa5a7741a51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791209353 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2791209353
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert_test.2486672141
Short name T575
Test name
Test status
Simulation time 15710641 ps
CPU time 0.95 seconds
Started Jun 30 05:23:55 PM PDT 24
Finished Jun 30 05:23:56 PM PDT 24
Peak memory 207048 kb
Host smart-4433d3f7-52b0-43f8-a224-27f09a69c8b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486672141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2486672141
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.968055438
Short name T465
Test name
Test status
Simulation time 33109290 ps
CPU time 0.85 seconds
Started Jun 30 05:23:48 PM PDT 24
Finished Jun 30 05:23:49 PM PDT 24
Peak memory 216272 kb
Host smart-05b8a747-612a-48ba-816d-052187bbfeaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968055438 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.968055438
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.958664115
Short name T126
Test name
Test status
Simulation time 297014477 ps
CPU time 1.24 seconds
Started Jun 30 05:23:48 PM PDT 24
Finished Jun 30 05:23:50 PM PDT 24
Peak memory 217264 kb
Host smart-826047df-dd8c-4912-969c-f0270a03362c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958664115 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.958664115
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2883161378
Short name T195
Test name
Test status
Simulation time 20348211 ps
CPU time 1.11 seconds
Started Jun 30 05:23:47 PM PDT 24
Finished Jun 30 05:23:49 PM PDT 24
Peak memory 218992 kb
Host smart-f9a0a85d-2cf7-470c-bc84-62f7ab9de86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883161378 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2883161378
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.307280393
Short name T428
Test name
Test status
Simulation time 52858683 ps
CPU time 1.52 seconds
Started Jun 30 05:23:48 PM PDT 24
Finished Jun 30 05:23:50 PM PDT 24
Peak memory 218624 kb
Host smart-85f61646-89b6-4f52-a555-8228d81391bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307280393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.307280393
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.4205436743
Short name T866
Test name
Test status
Simulation time 19393877 ps
CPU time 1.04 seconds
Started Jun 30 05:23:48 PM PDT 24
Finished Jun 30 05:23:49 PM PDT 24
Peak memory 216084 kb
Host smart-7f2d6671-e7c2-4fd2-a21a-99af55a6caf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205436743 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.4205436743
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.3949689738
Short name T334
Test name
Test status
Simulation time 26915440 ps
CPU time 0.93 seconds
Started Jun 30 05:23:47 PM PDT 24
Finished Jun 30 05:23:48 PM PDT 24
Peak memory 215624 kb
Host smart-a9757334-9822-419b-ad80-f7c1ceef998c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949689738 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3949689738
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1880399616
Short name T629
Test name
Test status
Simulation time 195202528 ps
CPU time 4.22 seconds
Started Jun 30 05:23:49 PM PDT 24
Finished Jun 30 05:23:54 PM PDT 24
Peak memory 215608 kb
Host smart-65cd83ab-b7ba-4648-94d1-d88bc73c0d38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880399616 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1880399616
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2628470550
Short name T219
Test name
Test status
Simulation time 82623782677 ps
CPU time 863.67 seconds
Started Jun 30 05:23:48 PM PDT 24
Finished Jun 30 05:38:12 PM PDT 24
Peak memory 224064 kb
Host smart-9df25ea8-fe01-424b-b6de-271587cee5f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628470550 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2628470550
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1987492679
Short name T859
Test name
Test status
Simulation time 87641261 ps
CPU time 1.19 seconds
Started Jun 30 05:21:59 PM PDT 24
Finished Jun 30 05:22:01 PM PDT 24
Peak memory 218716 kb
Host smart-6681403e-6de4-4195-9d33-952336f09ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987492679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1987492679
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2200804706
Short name T398
Test name
Test status
Simulation time 20655400 ps
CPU time 0.83 seconds
Started Jun 30 05:22:00 PM PDT 24
Finished Jun 30 05:22:01 PM PDT 24
Peak memory 207024 kb
Host smart-d1366620-9b58-4253-96a0-da00e72129da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200804706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2200804706
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.293910400
Short name T161
Test name
Test status
Simulation time 46725670 ps
CPU time 0.86 seconds
Started Jun 30 05:22:00 PM PDT 24
Finished Jun 30 05:22:01 PM PDT 24
Peak memory 216608 kb
Host smart-b23b768d-5c54-4d7e-b73f-1619d206cfd2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293910400 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.293910400
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.970157188
Short name T774
Test name
Test status
Simulation time 56427376 ps
CPU time 1.24 seconds
Started Jun 30 05:22:00 PM PDT 24
Finished Jun 30 05:22:01 PM PDT 24
Peak memory 219860 kb
Host smart-d3a9a4cf-839f-49ee-b940-bbea1dcc0e87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970157188 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.970157188
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1367204092
Short name T167
Test name
Test status
Simulation time 22347691 ps
CPU time 1.07 seconds
Started Jun 30 05:21:58 PM PDT 24
Finished Jun 30 05:22:00 PM PDT 24
Peak memory 215656 kb
Host smart-0a629551-f6ce-4b36-a319-e8b9376b8228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367204092 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1367204092
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.901481706
Short name T381
Test name
Test status
Simulation time 43168777 ps
CPU time 1.24 seconds
Started Jun 30 05:21:55 PM PDT 24
Finished Jun 30 05:21:56 PM PDT 24
Peak memory 217296 kb
Host smart-4d8b5531-0501-4891-a1fe-77ff392fab61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901481706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.901481706
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2534136805
Short name T85
Test name
Test status
Simulation time 19885773 ps
CPU time 1.09 seconds
Started Jun 30 05:21:59 PM PDT 24
Finished Jun 30 05:22:01 PM PDT 24
Peak memory 216052 kb
Host smart-3c8450ec-b5d4-46bd-a20d-f79db5a9e552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534136805 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2534136805
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2015962158
Short name T971
Test name
Test status
Simulation time 42967943 ps
CPU time 0.98 seconds
Started Jun 30 05:21:54 PM PDT 24
Finished Jun 30 05:21:55 PM PDT 24
Peak memory 207380 kb
Host smart-3399ae47-1d2a-4261-a129-07158f0ea4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015962158 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2015962158
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2421090259
Short name T16
Test name
Test status
Simulation time 1029660697 ps
CPU time 4.73 seconds
Started Jun 30 05:22:00 PM PDT 24
Finished Jun 30 05:22:06 PM PDT 24
Peak memory 242308 kb
Host smart-f67569ee-3350-45d3-a85d-fb074f0fc552
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421090259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2421090259
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2029039454
Short name T437
Test name
Test status
Simulation time 24664027 ps
CPU time 0.96 seconds
Started Jun 30 05:21:55 PM PDT 24
Finished Jun 30 05:21:56 PM PDT 24
Peak memory 215548 kb
Host smart-07e8e9f1-028f-4cca-8c94-e2333e93dd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029039454 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2029039454
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.130020183
Short name T931
Test name
Test status
Simulation time 299300353 ps
CPU time 6.24 seconds
Started Jun 30 05:21:59 PM PDT 24
Finished Jun 30 05:22:05 PM PDT 24
Peak memory 217704 kb
Host smart-e6c6cf58-1ebf-4c2c-8dbd-ee8f8489b417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130020183 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.130020183
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_alert.1088787044
Short name T284
Test name
Test status
Simulation time 42948861 ps
CPU time 1.2 seconds
Started Jun 30 05:23:57 PM PDT 24
Finished Jun 30 05:23:59 PM PDT 24
Peak memory 220140 kb
Host smart-b9bc2161-c5df-4066-9083-f7a8841db097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088787044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1088787044
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1610669008
Short name T455
Test name
Test status
Simulation time 28191885 ps
CPU time 1.16 seconds
Started Jun 30 05:23:55 PM PDT 24
Finished Jun 30 05:23:57 PM PDT 24
Peak memory 207024 kb
Host smart-8219977e-4951-4628-ae17-af7dcc402068
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610669008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1610669008
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3745032463
Short name T682
Test name
Test status
Simulation time 11993097 ps
CPU time 0.91 seconds
Started Jun 30 05:23:56 PM PDT 24
Finished Jun 30 05:23:58 PM PDT 24
Peak memory 216728 kb
Host smart-933e2662-12c8-46f3-bb8f-03bc0c91c941
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745032463 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3745032463
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3684117455
Short name T113
Test name
Test status
Simulation time 45195126 ps
CPU time 1.15 seconds
Started Jun 30 05:23:56 PM PDT 24
Finished Jun 30 05:23:57 PM PDT 24
Peak memory 217024 kb
Host smart-73c35346-9a07-4c84-8aa6-c9a02310e008
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684117455 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3684117455
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2277603440
Short name T132
Test name
Test status
Simulation time 26309005 ps
CPU time 0.99 seconds
Started Jun 30 05:23:57 PM PDT 24
Finished Jun 30 05:23:59 PM PDT 24
Peak memory 220096 kb
Host smart-968bf901-b5c7-4365-87ed-bb2371ea37e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277603440 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2277603440
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.4284704495
Short name T287
Test name
Test status
Simulation time 40128603 ps
CPU time 1.39 seconds
Started Jun 30 05:23:56 PM PDT 24
Finished Jun 30 05:23:59 PM PDT 24
Peak memory 217468 kb
Host smart-34b833d9-9698-42fc-897b-1f844783bc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284704495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.4284704495
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3920538617
Short name T823
Test name
Test status
Simulation time 39148126 ps
CPU time 0.89 seconds
Started Jun 30 05:23:58 PM PDT 24
Finished Jun 30 05:23:59 PM PDT 24
Peak memory 215492 kb
Host smart-42febbd9-bdcc-4271-b18b-4c8835209fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920538617 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3920538617
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3158657217
Short name T810
Test name
Test status
Simulation time 14804042 ps
CPU time 0.98 seconds
Started Jun 30 05:23:55 PM PDT 24
Finished Jun 30 05:23:56 PM PDT 24
Peak memory 215628 kb
Host smart-bc2d5eac-9050-41ab-a78d-2f80e32a9bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158657217 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3158657217
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3985456876
Short name T986
Test name
Test status
Simulation time 270938529 ps
CPU time 2.55 seconds
Started Jun 30 05:23:56 PM PDT 24
Finished Jun 30 05:24:00 PM PDT 24
Peak memory 215516 kb
Host smart-201531ab-6cef-4744-9ead-419fd5c7da2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985456876 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3985456876
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2704713995
Short name T752
Test name
Test status
Simulation time 232999175270 ps
CPU time 1105.85 seconds
Started Jun 30 05:23:56 PM PDT 24
Finished Jun 30 05:42:22 PM PDT 24
Peak memory 224020 kb
Host smart-8e177c80-2ee6-48c2-8148-a0fc361a4503
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704713995 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2704713995
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1116988891
Short name T413
Test name
Test status
Simulation time 176496223 ps
CPU time 1.13 seconds
Started Jun 30 05:23:56 PM PDT 24
Finished Jun 30 05:23:58 PM PDT 24
Peak memory 220284 kb
Host smart-16ae0089-0aae-444f-af81-6266e056493c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116988891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1116988891
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1651369583
Short name T404
Test name
Test status
Simulation time 43984910 ps
CPU time 0.99 seconds
Started Jun 30 05:23:57 PM PDT 24
Finished Jun 30 05:23:59 PM PDT 24
Peak memory 207036 kb
Host smart-40449582-f373-41fe-b514-307ab1e2f5c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651369583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1651369583
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2121110787
Short name T211
Test name
Test status
Simulation time 20021083 ps
CPU time 0.89 seconds
Started Jun 30 05:23:58 PM PDT 24
Finished Jun 30 05:23:59 PM PDT 24
Peak memory 215688 kb
Host smart-c34a96d6-cc09-4a79-b2c2-68f9723b034f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121110787 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2121110787
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2870971430
Short name T452
Test name
Test status
Simulation time 35183378 ps
CPU time 1.21 seconds
Started Jun 30 05:24:01 PM PDT 24
Finished Jun 30 05:24:02 PM PDT 24
Peak memory 217100 kb
Host smart-b342a115-88ae-4aec-b584-edcf4abc4109
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870971430 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2870971430
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2228734625
Short name T958
Test name
Test status
Simulation time 43362908 ps
CPU time 1.13 seconds
Started Jun 30 05:23:56 PM PDT 24
Finished Jun 30 05:23:57 PM PDT 24
Peak memory 219780 kb
Host smart-8f577f6f-7a16-4e74-a22d-07a72a35c106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228734625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2228734625
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3191819304
Short name T508
Test name
Test status
Simulation time 50020329 ps
CPU time 1.43 seconds
Started Jun 30 05:23:56 PM PDT 24
Finished Jun 30 05:23:58 PM PDT 24
Peak memory 218968 kb
Host smart-6d3df894-4749-4a11-90d1-025cba94c612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191819304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3191819304
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.302247906
Short name T668
Test name
Test status
Simulation time 24774544 ps
CPU time 1.04 seconds
Started Jun 30 05:23:56 PM PDT 24
Finished Jun 30 05:23:58 PM PDT 24
Peak memory 224384 kb
Host smart-ad929e72-4615-4389-90d9-ec071ad6f621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302247906 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.302247906
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1834075963
Short name T731
Test name
Test status
Simulation time 47682599 ps
CPU time 0.9 seconds
Started Jun 30 05:23:56 PM PDT 24
Finished Jun 30 05:23:57 PM PDT 24
Peak memory 215588 kb
Host smart-ce984605-fa82-42b1-921f-eed4f34c3371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834075963 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1834075963
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.506275556
Short name T89
Test name
Test status
Simulation time 122218897 ps
CPU time 3.01 seconds
Started Jun 30 05:23:57 PM PDT 24
Finished Jun 30 05:24:00 PM PDT 24
Peak memory 218768 kb
Host smart-cad769db-6662-4f4d-84d3-2d3f55d14d2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506275556 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.506275556
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3393479301
Short name T851
Test name
Test status
Simulation time 162587074785 ps
CPU time 1821.39 seconds
Started Jun 30 05:23:56 PM PDT 24
Finished Jun 30 05:54:18 PM PDT 24
Peak memory 225696 kb
Host smart-23bfa5d4-5be5-4753-872b-32b93e18eb7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393479301 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3393479301
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1890101925
Short name T833
Test name
Test status
Simulation time 24506090 ps
CPU time 1.19 seconds
Started Jun 30 05:23:57 PM PDT 24
Finished Jun 30 05:23:59 PM PDT 24
Peak memory 220008 kb
Host smart-73196299-ac50-4c82-8320-f36eb6918ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890101925 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1890101925
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2073070312
Short name T925
Test name
Test status
Simulation time 40468034 ps
CPU time 0.83 seconds
Started Jun 30 05:24:03 PM PDT 24
Finished Jun 30 05:24:04 PM PDT 24
Peak memory 206840 kb
Host smart-3025dde9-9b31-42e7-9605-0a0e38ca3630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073070312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2073070312
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2503772033
Short name T331
Test name
Test status
Simulation time 28618788 ps
CPU time 0.86 seconds
Started Jun 30 05:23:54 PM PDT 24
Finished Jun 30 05:23:56 PM PDT 24
Peak memory 216220 kb
Host smart-d2bdb25e-8124-4fad-8de8-5bc1679547eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503772033 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2503772033
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.968249638
Short name T846
Test name
Test status
Simulation time 30251432 ps
CPU time 1.12 seconds
Started Jun 30 05:23:58 PM PDT 24
Finished Jun 30 05:23:59 PM PDT 24
Peak memory 218632 kb
Host smart-6a7bf28e-6e6d-443e-9ea2-a7e5637c8c3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968249638 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.968249638
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2128104036
Short name T229
Test name
Test status
Simulation time 21466071 ps
CPU time 1.09 seconds
Started Jun 30 05:23:59 PM PDT 24
Finished Jun 30 05:24:01 PM PDT 24
Peak memory 215620 kb
Host smart-58dfc71b-99c3-4460-9d3e-c7b61b290429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128104036 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2128104036
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.4144661276
Short name T367
Test name
Test status
Simulation time 131595611 ps
CPU time 1.19 seconds
Started Jun 30 05:23:56 PM PDT 24
Finished Jun 30 05:23:58 PM PDT 24
Peak memory 217736 kb
Host smart-f653a353-d864-4415-8b9e-92083793ddc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144661276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.4144661276
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2261617634
Short name T461
Test name
Test status
Simulation time 27082408 ps
CPU time 0.97 seconds
Started Jun 30 05:23:55 PM PDT 24
Finished Jun 30 05:23:56 PM PDT 24
Peak memory 215824 kb
Host smart-a7b6a5a8-2893-47ee-bb41-67a5651aca32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261617634 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2261617634
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2143675143
Short name T579
Test name
Test status
Simulation time 24777819 ps
CPU time 1 seconds
Started Jun 30 05:23:56 PM PDT 24
Finished Jun 30 05:23:58 PM PDT 24
Peak memory 215560 kb
Host smart-927d3e88-2101-4f7e-9c49-59b4ac376f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143675143 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2143675143
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.106790354
Short name T695
Test name
Test status
Simulation time 312910519 ps
CPU time 5.94 seconds
Started Jun 30 05:23:56 PM PDT 24
Finished Jun 30 05:24:03 PM PDT 24
Peak memory 215576 kb
Host smart-960cf887-e1ea-44c5-aa37-f73065dd0f20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106790354 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.106790354
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1974135259
Short name T585
Test name
Test status
Simulation time 213620467974 ps
CPU time 1484.38 seconds
Started Jun 30 05:24:01 PM PDT 24
Finished Jun 30 05:48:46 PM PDT 24
Peak memory 226248 kb
Host smart-a48490df-9d4f-4040-8129-29aa5ea37fcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974135259 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1974135259
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.767057091
Short name T889
Test name
Test status
Simulation time 86755212 ps
CPU time 1.09 seconds
Started Jun 30 05:24:02 PM PDT 24
Finished Jun 30 05:24:04 PM PDT 24
Peak memory 219972 kb
Host smart-76626b77-0d00-4e36-a742-070e7662788a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767057091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.767057091
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1040458519
Short name T908
Test name
Test status
Simulation time 184639900 ps
CPU time 0.87 seconds
Started Jun 30 05:24:03 PM PDT 24
Finished Jun 30 05:24:05 PM PDT 24
Peak memory 207236 kb
Host smart-c1722d59-df47-42d3-b5a3-22986d885688
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040458519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1040458519
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2532306055
Short name T720
Test name
Test status
Simulation time 14631105 ps
CPU time 0.95 seconds
Started Jun 30 05:24:06 PM PDT 24
Finished Jun 30 05:24:07 PM PDT 24
Peak memory 216768 kb
Host smart-32b7be3b-8fe2-4d36-a4e2-903d828291e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532306055 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2532306055
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1082627033
Short name T953
Test name
Test status
Simulation time 177684816 ps
CPU time 1.05 seconds
Started Jun 30 05:24:03 PM PDT 24
Finished Jun 30 05:24:05 PM PDT 24
Peak memory 219508 kb
Host smart-0a67d500-477a-48ef-8c58-6d84970386a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082627033 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1082627033
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2177180296
Short name T123
Test name
Test status
Simulation time 29256857 ps
CPU time 1.05 seconds
Started Jun 30 05:24:02 PM PDT 24
Finished Jun 30 05:24:03 PM PDT 24
Peak memory 219780 kb
Host smart-ca576cce-0f4d-4e85-a65a-39f9111e65f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177180296 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2177180296
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2097478250
Short name T612
Test name
Test status
Simulation time 33318937 ps
CPU time 1.47 seconds
Started Jun 30 05:24:03 PM PDT 24
Finished Jun 30 05:24:05 PM PDT 24
Peak memory 217652 kb
Host smart-9c214cf6-db73-4cb9-a61a-68a649c3d9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097478250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2097478250
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3688965624
Short name T702
Test name
Test status
Simulation time 24436070 ps
CPU time 1.07 seconds
Started Jun 30 05:24:03 PM PDT 24
Finished Jun 30 05:24:05 PM PDT 24
Peak memory 223772 kb
Host smart-f44ef930-a233-41a7-97f7-d8b1e5270488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688965624 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3688965624
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3365638491
Short name T438
Test name
Test status
Simulation time 25078692 ps
CPU time 0.95 seconds
Started Jun 30 05:24:03 PM PDT 24
Finished Jun 30 05:24:04 PM PDT 24
Peak memory 215620 kb
Host smart-109c9124-1290-4f4f-9390-071f0a7e953a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365638491 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3365638491
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2728022609
Short name T853
Test name
Test status
Simulation time 41699465 ps
CPU time 1.38 seconds
Started Jun 30 05:24:02 PM PDT 24
Finished Jun 30 05:24:04 PM PDT 24
Peak memory 215616 kb
Host smart-be3bdb89-70c9-4b7a-8b85-7b6e8770de0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728022609 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2728022609
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3493304255
Short name T397
Test name
Test status
Simulation time 40142877661 ps
CPU time 949.89 seconds
Started Jun 30 05:24:04 PM PDT 24
Finished Jun 30 05:39:55 PM PDT 24
Peak memory 219452 kb
Host smart-957c4b5c-4ad4-476c-82e3-2fc86b93a6ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493304255 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3493304255
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2147494747
Short name T369
Test name
Test status
Simulation time 28679851 ps
CPU time 1.19 seconds
Started Jun 30 05:24:07 PM PDT 24
Finished Jun 30 05:24:08 PM PDT 24
Peak memory 218872 kb
Host smart-1474e9a0-fbe7-4dd7-b7e2-f7a616278478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147494747 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2147494747
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.867580423
Short name T568
Test name
Test status
Simulation time 29062434 ps
CPU time 0.95 seconds
Started Jun 30 05:24:02 PM PDT 24
Finished Jun 30 05:24:03 PM PDT 24
Peak memory 215200 kb
Host smart-2549102c-79d0-469a-91b2-b78b92946872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867580423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.867580423
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2570341197
Short name T946
Test name
Test status
Simulation time 25724715 ps
CPU time 0.92 seconds
Started Jun 30 05:24:03 PM PDT 24
Finished Jun 30 05:24:04 PM PDT 24
Peak memory 216524 kb
Host smart-27fef252-9581-4190-a586-5ae7d1f35ce3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570341197 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2570341197
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.4079736763
Short name T134
Test name
Test status
Simulation time 43886527 ps
CPU time 1.52 seconds
Started Jun 30 05:24:01 PM PDT 24
Finished Jun 30 05:24:03 PM PDT 24
Peak memory 217220 kb
Host smart-f764e5cf-f91a-4793-b42e-f2a8b9a2b96c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079736763 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.4079736763
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.219474136
Short name T103
Test name
Test status
Simulation time 32127872 ps
CPU time 1.17 seconds
Started Jun 30 05:24:01 PM PDT 24
Finished Jun 30 05:24:03 PM PDT 24
Peak memory 229964 kb
Host smart-9087b93d-1acc-4ccd-8882-adb379eb617d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219474136 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.219474136
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3018101754
Short name T530
Test name
Test status
Simulation time 67574321 ps
CPU time 1.41 seconds
Started Jun 30 05:24:04 PM PDT 24
Finished Jun 30 05:24:06 PM PDT 24
Peak memory 219056 kb
Host smart-562775fb-317c-41cc-b134-19da43acce00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018101754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3018101754
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3051458600
Short name T703
Test name
Test status
Simulation time 40998666 ps
CPU time 0.95 seconds
Started Jun 30 05:24:00 PM PDT 24
Finished Jun 30 05:24:01 PM PDT 24
Peak memory 224304 kb
Host smart-a0db21b2-7234-4c47-8811-234554b1b9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051458600 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3051458600
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1542910326
Short name T634
Test name
Test status
Simulation time 26008739 ps
CPU time 0.92 seconds
Started Jun 30 05:24:03 PM PDT 24
Finished Jun 30 05:24:05 PM PDT 24
Peak memory 215576 kb
Host smart-c3c13540-ef22-49c6-9ff2-99e5bac63122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542910326 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1542910326
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2683950332
Short name T375
Test name
Test status
Simulation time 437674315 ps
CPU time 5.12 seconds
Started Jun 30 05:24:04 PM PDT 24
Finished Jun 30 05:24:10 PM PDT 24
Peak memory 215884 kb
Host smart-e3d3b6c4-f6fe-4b2b-a1e0-98d17cf76704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683950332 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2683950332
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2478723834
Short name T842
Test name
Test status
Simulation time 15054101039 ps
CPU time 165.83 seconds
Started Jun 30 05:24:01 PM PDT 24
Finished Jun 30 05:26:47 PM PDT 24
Peak memory 223912 kb
Host smart-bcd6b4b1-59cb-463e-a7cc-aefed7626483
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478723834 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2478723834
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.502377321
Short name T759
Test name
Test status
Simulation time 45507889 ps
CPU time 1.21 seconds
Started Jun 30 05:24:04 PM PDT 24
Finished Jun 30 05:24:06 PM PDT 24
Peak memory 220484 kb
Host smart-b1aef1f6-589d-42d3-aead-b7d795a2d066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502377321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.502377321
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3129833592
Short name T590
Test name
Test status
Simulation time 12284541 ps
CPU time 0.91 seconds
Started Jun 30 05:24:12 PM PDT 24
Finished Jun 30 05:24:13 PM PDT 24
Peak memory 207532 kb
Host smart-ee6ca746-7950-4655-b56b-cc906dd7474d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129833592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3129833592
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3173294768
Short name T158
Test name
Test status
Simulation time 15110280 ps
CPU time 0.85 seconds
Started Jun 30 05:24:03 PM PDT 24
Finished Jun 30 05:24:05 PM PDT 24
Peak memory 216160 kb
Host smart-d6011552-3539-46fe-85de-45524317750e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173294768 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3173294768
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.928793695
Short name T140
Test name
Test status
Simulation time 53495287 ps
CPU time 0.96 seconds
Started Jun 30 05:24:01 PM PDT 24
Finished Jun 30 05:24:02 PM PDT 24
Peak memory 217220 kb
Host smart-a77cb14a-e16b-464f-94ac-5575b0a12b2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928793695 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.928793695
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1605461602
Short name T192
Test name
Test status
Simulation time 36298968 ps
CPU time 0.85 seconds
Started Jun 30 05:24:07 PM PDT 24
Finished Jun 30 05:24:08 PM PDT 24
Peak memory 219720 kb
Host smart-cc6ab350-cd82-4b5b-aba2-47afd07ccb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605461602 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1605461602
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.667130686
Short name T512
Test name
Test status
Simulation time 577032759 ps
CPU time 4.38 seconds
Started Jun 30 05:24:04 PM PDT 24
Finished Jun 30 05:24:09 PM PDT 24
Peak memory 220508 kb
Host smart-dcda8588-1648-44db-89cb-2679974c18b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667130686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.667130686
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.498029945
Short name T711
Test name
Test status
Simulation time 20457158 ps
CPU time 1.22 seconds
Started Jun 30 05:24:04 PM PDT 24
Finished Jun 30 05:24:06 PM PDT 24
Peak memory 224488 kb
Host smart-a9905c8f-866b-49ae-9f81-caf89d692e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498029945 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.498029945
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1615020646
Short name T623
Test name
Test status
Simulation time 32544914 ps
CPU time 1 seconds
Started Jun 30 05:24:03 PM PDT 24
Finished Jun 30 05:24:05 PM PDT 24
Peak memory 215088 kb
Host smart-509d2730-56cc-438c-b6b2-e604b100f8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615020646 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1615020646
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.227787824
Short name T186
Test name
Test status
Simulation time 294196647 ps
CPU time 5.54 seconds
Started Jun 30 05:24:06 PM PDT 24
Finished Jun 30 05:24:12 PM PDT 24
Peak memory 217392 kb
Host smart-3a907d63-b75a-4f7f-b9ef-c6972176199f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227787824 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.227787824
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1132252911
Short name T462
Test name
Test status
Simulation time 489872264223 ps
CPU time 2250.26 seconds
Started Jun 30 05:24:04 PM PDT 24
Finished Jun 30 06:01:35 PM PDT 24
Peak memory 231768 kb
Host smart-8a44a96a-5956-4b05-9087-87acc1affacf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132252911 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1132252911
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1912104081
Short name T983
Test name
Test status
Simulation time 85829999 ps
CPU time 1.16 seconds
Started Jun 30 05:24:08 PM PDT 24
Finished Jun 30 05:24:09 PM PDT 24
Peak memory 218708 kb
Host smart-8d5f539d-d56e-4d6e-a5d0-c548e5ff867b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912104081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1912104081
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2605999527
Short name T228
Test name
Test status
Simulation time 19003421 ps
CPU time 0.83 seconds
Started Jun 30 05:24:08 PM PDT 24
Finished Jun 30 05:24:09 PM PDT 24
Peak memory 215396 kb
Host smart-a0e48992-092c-41ef-a836-612086840761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605999527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2605999527
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.723040520
Short name T189
Test name
Test status
Simulation time 16715340 ps
CPU time 0.85 seconds
Started Jun 30 05:24:11 PM PDT 24
Finished Jun 30 05:24:12 PM PDT 24
Peak memory 216536 kb
Host smart-f9fd4689-bd51-45ad-9f43-e89cd2e61675
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723040520 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.723040520
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.998319106
Short name T840
Test name
Test status
Simulation time 29665224 ps
CPU time 0.97 seconds
Started Jun 30 05:24:11 PM PDT 24
Finished Jun 30 05:24:13 PM PDT 24
Peak memory 218428 kb
Host smart-8cdf02f6-33ea-4070-a5ef-852415faed54
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998319106 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.998319106
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.121958082
Short name T108
Test name
Test status
Simulation time 35734567 ps
CPU time 1.07 seconds
Started Jun 30 05:24:09 PM PDT 24
Finished Jun 30 05:24:11 PM PDT 24
Peak memory 219896 kb
Host smart-fe575e2a-ff3f-49ad-9837-55f6dc82c27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121958082 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.121958082
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.3405628456
Short name T344
Test name
Test status
Simulation time 61637273 ps
CPU time 1.21 seconds
Started Jun 30 05:24:11 PM PDT 24
Finished Jun 30 05:24:13 PM PDT 24
Peak memory 217472 kb
Host smart-4ca35114-2c74-423e-91b6-49201446ceb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405628456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3405628456
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.2360170166
Short name T686
Test name
Test status
Simulation time 20106683 ps
CPU time 1.09 seconds
Started Jun 30 05:24:11 PM PDT 24
Finished Jun 30 05:24:12 PM PDT 24
Peak memory 216192 kb
Host smart-22b056fc-165d-42bf-83c2-676256608ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360170166 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2360170166
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1279930721
Short name T632
Test name
Test status
Simulation time 18507722 ps
CPU time 1 seconds
Started Jun 30 05:24:10 PM PDT 24
Finished Jun 30 05:24:11 PM PDT 24
Peak memory 215604 kb
Host smart-5cb5cd2b-4920-453e-8d40-57efcedf70f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279930721 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1279930721
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1411696940
Short name T493
Test name
Test status
Simulation time 62943438 ps
CPU time 1.24 seconds
Started Jun 30 05:24:10 PM PDT 24
Finished Jun 30 05:24:12 PM PDT 24
Peak memory 217468 kb
Host smart-ee202cda-0232-4351-83b7-531ae962d1af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411696940 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1411696940
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.534759313
Short name T215
Test name
Test status
Simulation time 26683734486 ps
CPU time 644.2 seconds
Started Jun 30 05:24:09 PM PDT 24
Finished Jun 30 05:34:54 PM PDT 24
Peak memory 224020 kb
Host smart-605ddfe7-2bc7-4ccc-8927-1a7506e194ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534759313 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.534759313
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1719671874
Short name T921
Test name
Test status
Simulation time 57183396 ps
CPU time 1.15 seconds
Started Jun 30 05:24:09 PM PDT 24
Finished Jun 30 05:24:10 PM PDT 24
Peak memory 219232 kb
Host smart-a27642bb-3b6c-4f48-80a1-76814a75dc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719671874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1719671874
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.994442412
Short name T345
Test name
Test status
Simulation time 30437483 ps
CPU time 0.95 seconds
Started Jun 30 05:24:12 PM PDT 24
Finished Jun 30 05:24:13 PM PDT 24
Peak memory 207012 kb
Host smart-fcf637b2-1da7-4c21-a900-ae3495d032c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994442412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.994442412
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.216163042
Short name T207
Test name
Test status
Simulation time 15776807 ps
CPU time 0.88 seconds
Started Jun 30 05:24:09 PM PDT 24
Finished Jun 30 05:24:11 PM PDT 24
Peak memory 216756 kb
Host smart-e7587b2f-5f9b-46c7-8c6e-1c088277c0af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216163042 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.216163042
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3066526037
Short name T434
Test name
Test status
Simulation time 104044982 ps
CPU time 1.21 seconds
Started Jun 30 05:24:11 PM PDT 24
Finished Jun 30 05:24:13 PM PDT 24
Peak memory 217100 kb
Host smart-ce543f27-d9a1-48f0-99a6-3edc3e24e3f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066526037 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3066526037
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2166292640
Short name T456
Test name
Test status
Simulation time 21923783 ps
CPU time 0.91 seconds
Started Jun 30 05:24:09 PM PDT 24
Finished Jun 30 05:24:10 PM PDT 24
Peak memory 218684 kb
Host smart-db6e3879-8474-44e8-93cb-df06cc2095ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166292640 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2166292640
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1732982500
Short name T443
Test name
Test status
Simulation time 66966458 ps
CPU time 1.07 seconds
Started Jun 30 05:24:09 PM PDT 24
Finished Jun 30 05:24:11 PM PDT 24
Peak memory 217608 kb
Host smart-a9d6df36-ee5e-4832-88dc-6ffe87de5361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732982500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1732982500
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1726476276
Short name T377
Test name
Test status
Simulation time 30568167 ps
CPU time 0.94 seconds
Started Jun 30 05:24:11 PM PDT 24
Finished Jun 30 05:24:12 PM PDT 24
Peak memory 215784 kb
Host smart-30a07db1-2433-480b-9c18-1edd16d3de5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726476276 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1726476276
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3890105980
Short name T621
Test name
Test status
Simulation time 18643395 ps
CPU time 0.99 seconds
Started Jun 30 05:24:12 PM PDT 24
Finished Jun 30 05:24:13 PM PDT 24
Peak memory 215560 kb
Host smart-1e5278fe-98e3-41cb-bb50-d1ef5ffb7d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890105980 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3890105980
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2578028800
Short name T962
Test name
Test status
Simulation time 155415191 ps
CPU time 3.41 seconds
Started Jun 30 05:24:11 PM PDT 24
Finished Jun 30 05:24:15 PM PDT 24
Peak memory 217504 kb
Host smart-e2ee5549-49fb-48aa-8e0b-31e506ed93ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578028800 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2578028800
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.984415022
Short name T972
Test name
Test status
Simulation time 31836410231 ps
CPU time 702.75 seconds
Started Jun 30 05:24:10 PM PDT 24
Finished Jun 30 05:35:53 PM PDT 24
Peak memory 218692 kb
Host smart-56548ab2-c8bb-4b1d-812a-d4ff08bad181
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984415022 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.984415022
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3979361321
Short name T824
Test name
Test status
Simulation time 40299300 ps
CPU time 1.15 seconds
Started Jun 30 05:24:18 PM PDT 24
Finished Jun 30 05:24:20 PM PDT 24
Peak memory 219856 kb
Host smart-6c982834-7342-4120-87d8-a6803ceb0864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979361321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3979361321
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1082642041
Short name T350
Test name
Test status
Simulation time 15136311 ps
CPU time 0.94 seconds
Started Jun 30 05:24:18 PM PDT 24
Finished Jun 30 05:24:20 PM PDT 24
Peak memory 207028 kb
Host smart-dbd3e7a7-7953-4484-966b-d2dbb1925983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082642041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1082642041
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1687825488
Short name T688
Test name
Test status
Simulation time 12131251 ps
CPU time 0.92 seconds
Started Jun 30 05:24:16 PM PDT 24
Finished Jun 30 05:24:17 PM PDT 24
Peak memory 216616 kb
Host smart-f8ebec7e-de04-4772-8337-8a9be4e11013
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687825488 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1687825488
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3044015745
Short name T947
Test name
Test status
Simulation time 35932781 ps
CPU time 1.15 seconds
Started Jun 30 05:24:17 PM PDT 24
Finished Jun 30 05:24:19 PM PDT 24
Peak memory 217216 kb
Host smart-272d108c-a4ab-4139-bb4e-00f0216a327b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044015745 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3044015745
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_genbits.1318148722
Short name T378
Test name
Test status
Simulation time 66993511 ps
CPU time 1.52 seconds
Started Jun 30 05:24:09 PM PDT 24
Finished Jun 30 05:24:10 PM PDT 24
Peak memory 219256 kb
Host smart-b076f607-37b4-4ca2-896c-0cec0206edff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318148722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1318148722
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.4246821475
Short name T742
Test name
Test status
Simulation time 21634910 ps
CPU time 1.09 seconds
Started Jun 30 05:24:22 PM PDT 24
Finished Jun 30 05:24:24 PM PDT 24
Peak memory 215744 kb
Host smart-ccb1387f-d8a5-40a5-851e-4198bc866615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246821475 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.4246821475
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.471397556
Short name T666
Test name
Test status
Simulation time 36226082 ps
CPU time 1.02 seconds
Started Jun 30 05:24:13 PM PDT 24
Finished Jun 30 05:24:14 PM PDT 24
Peak memory 215880 kb
Host smart-f7355cee-d079-4adf-b2e4-91a946c61e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471397556 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.471397556
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.688358823
Short name T689
Test name
Test status
Simulation time 327502271 ps
CPU time 2.26 seconds
Started Jun 30 05:24:18 PM PDT 24
Finished Jun 30 05:24:21 PM PDT 24
Peak memory 217456 kb
Host smart-dbbb974b-cfd3-4acb-afa5-ac83d776aad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688358823 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.688358823
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2169699004
Short name T977
Test name
Test status
Simulation time 39139872037 ps
CPU time 841.78 seconds
Started Jun 30 05:24:17 PM PDT 24
Finished Jun 30 05:38:19 PM PDT 24
Peak memory 219092 kb
Host smart-ac927bf5-bdeb-4c7f-9831-61b45c5e9530
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169699004 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2169699004
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1864493682
Short name T282
Test name
Test status
Simulation time 60247228 ps
CPU time 1.05 seconds
Started Jun 30 05:24:18 PM PDT 24
Finished Jun 30 05:24:20 PM PDT 24
Peak memory 218944 kb
Host smart-b8cde1b4-93cf-4e79-9c23-77e2f72ea863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864493682 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1864493682
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.239584067
Short name T548
Test name
Test status
Simulation time 18579046 ps
CPU time 1.04 seconds
Started Jun 30 05:24:21 PM PDT 24
Finished Jun 30 05:24:22 PM PDT 24
Peak memory 206932 kb
Host smart-1c7c7785-159a-424f-b12e-8f3a237c7c60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239584067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.239584067
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2599190551
Short name T635
Test name
Test status
Simulation time 24998646 ps
CPU time 0.8 seconds
Started Jun 30 05:24:17 PM PDT 24
Finished Jun 30 05:24:19 PM PDT 24
Peak memory 216504 kb
Host smart-5f74c2b4-022d-4700-8764-1ecd1b205e0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599190551 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2599190551
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3209624285
Short name T966
Test name
Test status
Simulation time 31677868 ps
CPU time 1.17 seconds
Started Jun 30 05:24:18 PM PDT 24
Finished Jun 30 05:24:20 PM PDT 24
Peak memory 216952 kb
Host smart-e11a88b8-dba6-4cf3-8668-c6108b6d423d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209624285 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3209624285
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2148518012
Short name T844
Test name
Test status
Simulation time 21110510 ps
CPU time 1.08 seconds
Started Jun 30 05:24:20 PM PDT 24
Finished Jun 30 05:24:21 PM PDT 24
Peak memory 220036 kb
Host smart-38f5713b-395b-4c19-9604-3a84dbefb40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148518012 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2148518012
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1098551922
Short name T23
Test name
Test status
Simulation time 99995052 ps
CPU time 1.54 seconds
Started Jun 30 05:24:21 PM PDT 24
Finished Jun 30 05:24:23 PM PDT 24
Peak memory 218932 kb
Host smart-8a4f5107-8fc6-49c0-a637-be6ec2877376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098551922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1098551922
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2145089758
Short name T382
Test name
Test status
Simulation time 25368876 ps
CPU time 0.9 seconds
Started Jun 30 05:24:16 PM PDT 24
Finished Jun 30 05:24:17 PM PDT 24
Peak memory 215800 kb
Host smart-a217b7eb-1e09-462b-b21d-36abdc69e13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145089758 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2145089758
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.88908995
Short name T400
Test name
Test status
Simulation time 15978227 ps
CPU time 0.98 seconds
Started Jun 30 05:24:17 PM PDT 24
Finished Jun 30 05:24:18 PM PDT 24
Peak memory 215560 kb
Host smart-136ee98f-3545-4817-8e96-4442a96d7724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88908995 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.88908995
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1334785244
Short name T289
Test name
Test status
Simulation time 1008882053 ps
CPU time 5.22 seconds
Started Jun 30 05:24:21 PM PDT 24
Finished Jun 30 05:24:27 PM PDT 24
Peak memory 215508 kb
Host smart-ef5c4794-f318-4824-9320-a8523f5bd6c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334785244 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1334785244
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1386061977
Short name T608
Test name
Test status
Simulation time 60453950370 ps
CPU time 1507.7 seconds
Started Jun 30 05:24:18 PM PDT 24
Finished Jun 30 05:49:27 PM PDT 24
Peak memory 225852 kb
Host smart-338d548c-dca6-4c41-95ff-6889a2e4e899
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386061977 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1386061977
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1941203276
Short name T749
Test name
Test status
Simulation time 48567656 ps
CPU time 1.23 seconds
Started Jun 30 05:22:05 PM PDT 24
Finished Jun 30 05:22:07 PM PDT 24
Peak memory 219708 kb
Host smart-fadd0590-a237-428b-bad9-100743b770d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941203276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1941203276
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2486700331
Short name T324
Test name
Test status
Simulation time 25221189 ps
CPU time 0.96 seconds
Started Jun 30 05:22:07 PM PDT 24
Finished Jun 30 05:22:08 PM PDT 24
Peak memory 215176 kb
Host smart-4710dbea-0a45-4d25-a87d-96194c1bb087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486700331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2486700331
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1714921488
Short name T191
Test name
Test status
Simulation time 31978754 ps
CPU time 0.91 seconds
Started Jun 30 05:22:10 PM PDT 24
Finished Jun 30 05:22:11 PM PDT 24
Peak memory 216512 kb
Host smart-c8a3f287-b5a5-4f67-83a1-90d6708cd3b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714921488 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1714921488
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2126887148
Short name T646
Test name
Test status
Simulation time 117839223 ps
CPU time 1.12 seconds
Started Jun 30 05:22:08 PM PDT 24
Finished Jun 30 05:22:10 PM PDT 24
Peak memory 217184 kb
Host smart-2e349015-b5d0-41e3-8453-1ba8ffe6dd38
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126887148 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2126887148
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1325537244
Short name T155
Test name
Test status
Simulation time 18934296 ps
CPU time 1.08 seconds
Started Jun 30 05:22:07 PM PDT 24
Finished Jun 30 05:22:09 PM PDT 24
Peak memory 218752 kb
Host smart-a4246c0c-8df0-4dcc-9570-4c8a40ccd19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325537244 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1325537244
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3291941146
Short name T411
Test name
Test status
Simulation time 276200866 ps
CPU time 3.97 seconds
Started Jun 30 05:22:07 PM PDT 24
Finished Jun 30 05:22:11 PM PDT 24
Peak memory 219168 kb
Host smart-5031d401-a375-4110-80ad-6110edafee89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291941146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3291941146
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.4112441254
Short name T716
Test name
Test status
Simulation time 28869879 ps
CPU time 1.2 seconds
Started Jun 30 05:22:06 PM PDT 24
Finished Jun 30 05:22:07 PM PDT 24
Peak memory 215724 kb
Host smart-9e90ebda-37dd-45c9-a267-d43f224cf4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112441254 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.4112441254
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_smoke.2766983347
Short name T445
Test name
Test status
Simulation time 16520558 ps
CPU time 1.06 seconds
Started Jun 30 05:22:07 PM PDT 24
Finished Jun 30 05:22:08 PM PDT 24
Peak memory 215600 kb
Host smart-a616e368-0588-475a-a375-6e4934034d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766983347 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2766983347
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3524514102
Short name T899
Test name
Test status
Simulation time 198238931 ps
CPU time 3.14 seconds
Started Jun 30 05:22:08 PM PDT 24
Finished Jun 30 05:22:11 PM PDT 24
Peak memory 217528 kb
Host smart-d6247f18-7194-42b8-b474-93a84d569200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524514102 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3524514102
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1015437388
Short name T535
Test name
Test status
Simulation time 47988000936 ps
CPU time 1234.78 seconds
Started Jun 30 05:22:06 PM PDT 24
Finished Jun 30 05:42:41 PM PDT 24
Peak memory 221584 kb
Host smart-376db455-0764-4aa6-93ee-907d9f5eb0ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015437388 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1015437388
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.2392935004
Short name T987
Test name
Test status
Simulation time 24373327 ps
CPU time 1.26 seconds
Started Jun 30 05:24:22 PM PDT 24
Finished Jun 30 05:24:24 PM PDT 24
Peak memory 219684 kb
Host smart-f20a5884-3abd-43f6-b6b0-489199f2fe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392935004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2392935004
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.4209701860
Short name T200
Test name
Test status
Simulation time 45079266 ps
CPU time 1.19 seconds
Started Jun 30 05:24:18 PM PDT 24
Finished Jun 30 05:24:20 PM PDT 24
Peak memory 219768 kb
Host smart-94367bf0-4b5e-4cae-ad1c-01156137740a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209701860 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.4209701860
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1436111993
Short name T439
Test name
Test status
Simulation time 85586460 ps
CPU time 1.98 seconds
Started Jun 30 05:24:19 PM PDT 24
Finished Jun 30 05:24:21 PM PDT 24
Peak memory 220456 kb
Host smart-23a94204-d65b-4c8c-80de-7450f41fe343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436111993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1436111993
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.3960605184
Short name T650
Test name
Test status
Simulation time 30209016 ps
CPU time 1.39 seconds
Started Jun 30 05:24:18 PM PDT 24
Finished Jun 30 05:24:20 PM PDT 24
Peak memory 216000 kb
Host smart-a8020a02-13e7-454d-bb2b-a47c9b700f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960605184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.3960605184
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.2830315448
Short name T370
Test name
Test status
Simulation time 18699576 ps
CPU time 1.11 seconds
Started Jun 30 05:24:17 PM PDT 24
Finished Jun 30 05:24:19 PM PDT 24
Peak memory 218704 kb
Host smart-93e84a41-8d3c-4d2e-a80b-8c5992223644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830315448 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2830315448
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1081450638
Short name T938
Test name
Test status
Simulation time 110281916 ps
CPU time 0.96 seconds
Started Jun 30 05:24:18 PM PDT 24
Finished Jun 30 05:24:19 PM PDT 24
Peak memory 217624 kb
Host smart-509fcc3e-5bc0-4aa5-86db-c5efc6c24065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081450638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1081450638
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.1919723013
Short name T143
Test name
Test status
Simulation time 24429698 ps
CPU time 1.22 seconds
Started Jun 30 05:24:19 PM PDT 24
Finished Jun 30 05:24:21 PM PDT 24
Peak memory 219040 kb
Host smart-45bd0695-0b24-41fa-9d35-32d557cd5316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919723013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.1919723013
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.622916158
Short name T111
Test name
Test status
Simulation time 50370570 ps
CPU time 1.1 seconds
Started Jun 30 05:24:22 PM PDT 24
Finished Jun 30 05:24:24 PM PDT 24
Peak memory 229956 kb
Host smart-613b8e68-5e67-430f-ace0-93549eb31620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622916158 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.622916158
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3389920053
Short name T446
Test name
Test status
Simulation time 327480816 ps
CPU time 2.01 seconds
Started Jun 30 05:24:18 PM PDT 24
Finished Jun 30 05:24:21 PM PDT 24
Peak memory 219284 kb
Host smart-5ad4e98b-597c-485c-a0e8-d661e9454bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389920053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3389920053
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.1036788167
Short name T564
Test name
Test status
Simulation time 50837918 ps
CPU time 1.23 seconds
Started Jun 30 05:24:24 PM PDT 24
Finished Jun 30 05:24:25 PM PDT 24
Peak memory 220104 kb
Host smart-c0bcf1f0-f414-48b6-bc50-8459da00c732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036788167 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.1036788167
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.575516863
Short name T624
Test name
Test status
Simulation time 26242751 ps
CPU time 0.87 seconds
Started Jun 30 05:24:28 PM PDT 24
Finished Jun 30 05:24:29 PM PDT 24
Peak memory 218528 kb
Host smart-362256a8-c718-486a-b676-20520bf175fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575516863 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.575516863
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.66109152
Short name T503
Test name
Test status
Simulation time 39207869 ps
CPU time 1.43 seconds
Started Jun 30 05:24:23 PM PDT 24
Finished Jun 30 05:24:25 PM PDT 24
Peak memory 219872 kb
Host smart-b691a4fd-b91e-487d-bf9f-15f8e16af776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66109152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.66109152
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.132156922
Short name T279
Test name
Test status
Simulation time 79067651 ps
CPU time 1.12 seconds
Started Jun 30 05:24:22 PM PDT 24
Finished Jun 30 05:24:24 PM PDT 24
Peak memory 218940 kb
Host smart-ac954ebb-a5fd-4ab0-b0a3-1deb8927552b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132156922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.132156922
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.4241569512
Short name T748
Test name
Test status
Simulation time 29291481 ps
CPU time 1.41 seconds
Started Jun 30 05:24:23 PM PDT 24
Finished Jun 30 05:24:25 PM PDT 24
Peak memory 225876 kb
Host smart-706b33ba-303f-482a-9cc7-d68ac70e1f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241569512 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.4241569512
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3073576404
Short name T430
Test name
Test status
Simulation time 886782826 ps
CPU time 5.78 seconds
Started Jun 30 05:24:25 PM PDT 24
Finished Jun 30 05:24:31 PM PDT 24
Peak memory 220244 kb
Host smart-4b2ae385-b6d2-4be3-ac94-ed4aa6b0c7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073576404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3073576404
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.2793188624
Short name T91
Test name
Test status
Simulation time 40077381 ps
CPU time 1.14 seconds
Started Jun 30 05:24:28 PM PDT 24
Finished Jun 30 05:24:29 PM PDT 24
Peak memory 220640 kb
Host smart-a6e70a9a-dcec-45c9-b863-67c36b3ac4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793188624 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.2793188624
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.4071455802
Short name T326
Test name
Test status
Simulation time 37306476 ps
CPU time 0.9 seconds
Started Jun 30 05:24:28 PM PDT 24
Finished Jun 30 05:24:29 PM PDT 24
Peak memory 218376 kb
Host smart-444c0471-17bf-4c03-9756-4a96a6690ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071455802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.4071455802
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2177647949
Short name T829
Test name
Test status
Simulation time 138191879 ps
CPU time 1.63 seconds
Started Jun 30 05:24:25 PM PDT 24
Finished Jun 30 05:24:27 PM PDT 24
Peak memory 219156 kb
Host smart-98158f49-dc7c-4b88-9708-e2c86327fe66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177647949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2177647949
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.1910579396
Short name T735
Test name
Test status
Simulation time 39168717 ps
CPU time 1.24 seconds
Started Jun 30 05:24:24 PM PDT 24
Finished Jun 30 05:24:26 PM PDT 24
Peak memory 219852 kb
Host smart-2b76b931-6cbc-4789-9a91-e16f3d04484e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910579396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.1910579396
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.1178038841
Short name T8
Test name
Test status
Simulation time 20210967 ps
CPU time 1.27 seconds
Started Jun 30 05:24:25 PM PDT 24
Finished Jun 30 05:24:26 PM PDT 24
Peak memory 229864 kb
Host smart-55fcc3f1-86b0-487a-bbc8-f9f774901ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178038841 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1178038841
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.4244605124
Short name T520
Test name
Test status
Simulation time 53562561 ps
CPU time 1.98 seconds
Started Jun 30 05:24:27 PM PDT 24
Finished Jun 30 05:24:29 PM PDT 24
Peak memory 218976 kb
Host smart-0444014b-3bad-4b06-a258-5032fd97c795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244605124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.4244605124
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.2078427146
Short name T137
Test name
Test status
Simulation time 87118795 ps
CPU time 1.27 seconds
Started Jun 30 05:24:28 PM PDT 24
Finished Jun 30 05:24:29 PM PDT 24
Peak memory 218652 kb
Host smart-95f4af71-2f52-44c6-aa93-829faf373d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078427146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.2078427146
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.661479752
Short name T547
Test name
Test status
Simulation time 84613499 ps
CPU time 1.04 seconds
Started Jun 30 05:24:28 PM PDT 24
Finished Jun 30 05:24:30 PM PDT 24
Peak memory 220768 kb
Host smart-634ce97e-53c4-4c9c-a3c0-32d7f2b4e71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661479752 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.661479752
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2964769835
Short name T945
Test name
Test status
Simulation time 363161713 ps
CPU time 1.19 seconds
Started Jun 30 05:24:25 PM PDT 24
Finished Jun 30 05:24:26 PM PDT 24
Peak memory 217676 kb
Host smart-978633cd-1e29-4522-bfc1-4a829d0fda7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964769835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2964769835
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.1203772354
Short name T722
Test name
Test status
Simulation time 29397687 ps
CPU time 1.29 seconds
Started Jun 30 05:24:28 PM PDT 24
Finished Jun 30 05:24:30 PM PDT 24
Peak memory 219028 kb
Host smart-2e22c369-4998-4963-b5c3-402d43ebef25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203772354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.1203772354
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.2324273872
Short name T637
Test name
Test status
Simulation time 18035396 ps
CPU time 1.19 seconds
Started Jun 30 05:24:25 PM PDT 24
Finished Jun 30 05:24:27 PM PDT 24
Peak memory 224252 kb
Host smart-12a751e5-7ef4-4429-a8d4-97d359b11981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324273872 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2324273872
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3514439142
Short name T909
Test name
Test status
Simulation time 546005642 ps
CPU time 5.26 seconds
Started Jun 30 05:24:26 PM PDT 24
Finished Jun 30 05:24:31 PM PDT 24
Peak memory 217984 kb
Host smart-3580005b-3abe-4d2c-8e11-b0ad858ca572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514439142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3514439142
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.3505430564
Short name T513
Test name
Test status
Simulation time 254833211 ps
CPU time 1.13 seconds
Started Jun 30 05:24:27 PM PDT 24
Finished Jun 30 05:24:29 PM PDT 24
Peak memory 219876 kb
Host smart-9972f4fb-420c-4d7a-a777-2aff496abb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505430564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.3505430564
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.3492726447
Short name T988
Test name
Test status
Simulation time 33351193 ps
CPU time 1.2 seconds
Started Jun 30 05:24:24 PM PDT 24
Finished Jun 30 05:24:26 PM PDT 24
Peak memory 229800 kb
Host smart-b5705511-25a0-4a72-9b0c-5b2d0b420f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492726447 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3492726447
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2158546882
Short name T863
Test name
Test status
Simulation time 33783872 ps
CPU time 1.37 seconds
Started Jun 30 05:24:27 PM PDT 24
Finished Jun 30 05:24:28 PM PDT 24
Peak memory 217588 kb
Host smart-45066a2d-ce99-432c-b6e0-4e9d4e2620df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158546882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2158546882
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.140713273
Short name T454
Test name
Test status
Simulation time 23930111 ps
CPU time 1.23 seconds
Started Jun 30 05:22:15 PM PDT 24
Finished Jun 30 05:22:16 PM PDT 24
Peak memory 218900 kb
Host smart-5673ad60-7dcb-416e-8809-da6d1f606a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140713273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.140713273
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3349372253
Short name T393
Test name
Test status
Simulation time 91693975 ps
CPU time 0.77 seconds
Started Jun 30 05:22:13 PM PDT 24
Finished Jun 30 05:22:15 PM PDT 24
Peak memory 206588 kb
Host smart-c58beeef-ffbc-48ce-bfda-1a85ba5a978a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349372253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3349372253
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1599994767
Short name T321
Test name
Test status
Simulation time 15364110 ps
CPU time 0.87 seconds
Started Jun 30 05:22:13 PM PDT 24
Finished Jun 30 05:22:15 PM PDT 24
Peak memory 216184 kb
Host smart-2dcc9e42-a4c2-4914-b9f2-5651672d08b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599994767 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1599994767
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2615952229
Short name T923
Test name
Test status
Simulation time 38306535 ps
CPU time 1.06 seconds
Started Jun 30 05:22:13 PM PDT 24
Finished Jun 30 05:22:15 PM PDT 24
Peak memory 217160 kb
Host smart-d09e4aa5-976d-4b48-a597-6665233f2c7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615952229 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2615952229
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.3539727962
Short name T860
Test name
Test status
Simulation time 29681491 ps
CPU time 1 seconds
Started Jun 30 05:22:14 PM PDT 24
Finished Jun 30 05:22:16 PM PDT 24
Peak memory 224060 kb
Host smart-10256996-3861-45e4-9e23-9fccb0b8d229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539727962 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3539727962
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2261965632
Short name T534
Test name
Test status
Simulation time 45103272 ps
CPU time 1.37 seconds
Started Jun 30 05:22:15 PM PDT 24
Finished Jun 30 05:22:16 PM PDT 24
Peak memory 218884 kb
Host smart-f3863a84-9ad6-460b-bc74-9e433e969d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261965632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2261965632
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2781800646
Short name T939
Test name
Test status
Simulation time 24300003 ps
CPU time 0.92 seconds
Started Jun 30 05:22:14 PM PDT 24
Finished Jun 30 05:22:16 PM PDT 24
Peak memory 215768 kb
Host smart-0be7ab89-fbdb-4476-a640-6eafd7be86b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781800646 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2781800646
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1325765773
Short name T277
Test name
Test status
Simulation time 57131184 ps
CPU time 0.96 seconds
Started Jun 30 05:22:08 PM PDT 24
Finished Jun 30 05:22:09 PM PDT 24
Peak memory 207452 kb
Host smart-8e61a934-733e-4109-b91b-7f7d50887431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325765773 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1325765773
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1144963701
Short name T497
Test name
Test status
Simulation time 17303941 ps
CPU time 0.96 seconds
Started Jun 30 05:22:07 PM PDT 24
Finished Jun 30 05:22:08 PM PDT 24
Peak memory 215592 kb
Host smart-f0980a57-e5fd-438b-855f-6349cb188035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144963701 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1144963701
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.407708734
Short name T338
Test name
Test status
Simulation time 698372773 ps
CPU time 3.7 seconds
Started Jun 30 05:22:13 PM PDT 24
Finished Jun 30 05:22:18 PM PDT 24
Peak memory 217368 kb
Host smart-71c0321b-df39-47d9-a6b1-b61638e30ade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407708734 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.407708734
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1221911187
Short name T216
Test name
Test status
Simulation time 57135802497 ps
CPU time 667.62 seconds
Started Jun 30 05:22:13 PM PDT 24
Finished Jun 30 05:33:21 PM PDT 24
Peak memory 223964 kb
Host smart-32abed1c-b6bd-42dc-a7bb-634cdb0a2ff5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221911187 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1221911187
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.1030425892
Short name T544
Test name
Test status
Simulation time 261243736 ps
CPU time 1.27 seconds
Started Jun 30 05:24:23 PM PDT 24
Finished Jun 30 05:24:24 PM PDT 24
Peak memory 215876 kb
Host smart-a7c7cfc2-8a04-4511-b3f5-4c51f17846bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030425892 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1030425892
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1519383586
Short name T595
Test name
Test status
Simulation time 51839123 ps
CPU time 1.15 seconds
Started Jun 30 05:24:28 PM PDT 24
Finished Jun 30 05:24:29 PM PDT 24
Peak memory 220012 kb
Host smart-92c78a5b-a249-43aa-8d39-d2a37929e092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519383586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1519383586
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1061777369
Short name T816
Test name
Test status
Simulation time 49936268 ps
CPU time 1.13 seconds
Started Jun 30 05:24:25 PM PDT 24
Finished Jun 30 05:24:27 PM PDT 24
Peak memory 217716 kb
Host smart-2796c881-b7b9-40bc-9d91-668bd6905301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061777369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1061777369
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.23758616
Short name T888
Test name
Test status
Simulation time 24175002 ps
CPU time 1.3 seconds
Started Jun 30 05:24:33 PM PDT 24
Finished Jun 30 05:24:35 PM PDT 24
Peak memory 220060 kb
Host smart-7e0c7f02-8463-45c6-8d14-6eec84dccaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23758616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.23758616
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.3907626321
Short name T199
Test name
Test status
Simulation time 19523128 ps
CPU time 1.02 seconds
Started Jun 30 05:24:31 PM PDT 24
Finished Jun 30 05:24:33 PM PDT 24
Peak memory 219820 kb
Host smart-8d97728c-903f-4a45-a8b8-1a19813c2c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907626321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3907626321
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.210104234
Short name T991
Test name
Test status
Simulation time 93066971 ps
CPU time 1.32 seconds
Started Jun 30 05:24:24 PM PDT 24
Finished Jun 30 05:24:25 PM PDT 24
Peak memory 219696 kb
Host smart-691d5fc3-e24f-4f93-8278-8f1949d0cea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210104234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.210104234
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.2408068162
Short name T566
Test name
Test status
Simulation time 85153869 ps
CPU time 1.22 seconds
Started Jun 30 05:24:32 PM PDT 24
Finished Jun 30 05:24:33 PM PDT 24
Peak memory 220156 kb
Host smart-ddf1e7bc-0cb1-4a79-86ed-869121b4d23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408068162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.2408068162
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.2244570566
Short name T94
Test name
Test status
Simulation time 21932869 ps
CPU time 1.15 seconds
Started Jun 30 05:24:32 PM PDT 24
Finished Jun 30 05:24:34 PM PDT 24
Peak memory 220256 kb
Host smart-d8ecefd3-a02e-4520-8720-1505a0797ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244570566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2244570566
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2763795490
Short name T466
Test name
Test status
Simulation time 27503795 ps
CPU time 1.29 seconds
Started Jun 30 05:24:30 PM PDT 24
Finished Jun 30 05:24:31 PM PDT 24
Peak memory 220572 kb
Host smart-09e02baa-aee4-4fda-9db9-c80c774750f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763795490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2763795490
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.564962577
Short name T874
Test name
Test status
Simulation time 24603908 ps
CPU time 1.32 seconds
Started Jun 30 05:24:34 PM PDT 24
Finished Jun 30 05:24:36 PM PDT 24
Peak memory 220428 kb
Host smart-67b333aa-6d24-4383-bc2b-a3d845d05e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564962577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.564962577
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.3979160844
Short name T935
Test name
Test status
Simulation time 49177989 ps
CPU time 1.08 seconds
Started Jun 30 05:24:32 PM PDT 24
Finished Jun 30 05:24:33 PM PDT 24
Peak memory 218920 kb
Host smart-1126ebf9-04fb-4baa-8ae3-f59c4f5b0430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979160844 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3979160844
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/64.edn_alert.2423869701
Short name T652
Test name
Test status
Simulation time 65467072 ps
CPU time 1.36 seconds
Started Jun 30 05:24:32 PM PDT 24
Finished Jun 30 05:24:33 PM PDT 24
Peak memory 215992 kb
Host smart-c44be79a-1c54-41dc-a39c-0a1f3d7205ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423869701 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.2423869701
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.3253426095
Short name T599
Test name
Test status
Simulation time 27919253 ps
CPU time 1.09 seconds
Started Jun 30 05:24:33 PM PDT 24
Finished Jun 30 05:24:35 PM PDT 24
Peak memory 218748 kb
Host smart-6d7d8637-d81e-43b4-b8d0-a2a3e5ce66e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253426095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3253426095
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1783507103
Short name T43
Test name
Test status
Simulation time 90884495 ps
CPU time 1.38 seconds
Started Jun 30 05:24:31 PM PDT 24
Finished Jun 30 05:24:33 PM PDT 24
Peak memory 219488 kb
Host smart-b1fbc398-fcb9-4e68-b0ec-f50917f0863c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783507103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1783507103
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.2786821244
Short name T181
Test name
Test status
Simulation time 29286043 ps
CPU time 1.28 seconds
Started Jun 30 05:24:33 PM PDT 24
Finished Jun 30 05:24:35 PM PDT 24
Peak memory 220312 kb
Host smart-1e81e296-1301-4615-849b-3e0518c59912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786821244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.2786821244
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_genbits.3689854613
Short name T474
Test name
Test status
Simulation time 247174358 ps
CPU time 1.84 seconds
Started Jun 30 05:24:34 PM PDT 24
Finished Jun 30 05:24:36 PM PDT 24
Peak memory 218864 kb
Host smart-5dfb4928-6b53-4e09-b01c-726c6c2931ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689854613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3689854613
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.702392899
Short name T852
Test name
Test status
Simulation time 41932599 ps
CPU time 1.28 seconds
Started Jun 30 05:24:31 PM PDT 24
Finished Jun 30 05:24:33 PM PDT 24
Peak memory 220560 kb
Host smart-6c09fa3f-91e6-409f-be71-e349d34aa872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702392899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.702392899
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.2949160966
Short name T978
Test name
Test status
Simulation time 70457764 ps
CPU time 0.99 seconds
Started Jun 30 05:24:33 PM PDT 24
Finished Jun 30 05:24:34 PM PDT 24
Peak memory 229536 kb
Host smart-bf2bdc53-9b54-4254-a5b8-8f2d16e46a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949160966 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2949160966
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3354047317
Short name T928
Test name
Test status
Simulation time 297823133 ps
CPU time 1.19 seconds
Started Jun 30 05:24:34 PM PDT 24
Finished Jun 30 05:24:36 PM PDT 24
Peak memory 217896 kb
Host smart-e499b89b-6a0e-40f0-a7ac-53d6b7afd92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354047317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3354047317
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.3814747241
Short name T653
Test name
Test status
Simulation time 86858865 ps
CPU time 1.19 seconds
Started Jun 30 05:24:31 PM PDT 24
Finished Jun 30 05:24:33 PM PDT 24
Peak memory 220492 kb
Host smart-a5afc8ae-5f99-49a8-84b3-e7a7857ba4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814747241 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.3814747241
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.799528818
Short name T352
Test name
Test status
Simulation time 78268581 ps
CPU time 0.89 seconds
Started Jun 30 05:24:31 PM PDT 24
Finished Jun 30 05:24:32 PM PDT 24
Peak memory 218724 kb
Host smart-09991623-be65-4ada-aa78-ba3caf9963e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799528818 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.799528818
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3101264494
Short name T463
Test name
Test status
Simulation time 66533582 ps
CPU time 1.08 seconds
Started Jun 30 05:24:35 PM PDT 24
Finished Jun 30 05:24:37 PM PDT 24
Peak memory 217684 kb
Host smart-a13e3db8-eab9-477c-8612-241c6adb186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101264494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3101264494
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.1905202976
Short name T210
Test name
Test status
Simulation time 29809743 ps
CPU time 1.27 seconds
Started Jun 30 05:24:31 PM PDT 24
Finished Jun 30 05:24:32 PM PDT 24
Peak memory 219016 kb
Host smart-557db23d-d089-4a36-84d9-f07166d0c491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905202976 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.1905202976
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.2294436706
Short name T204
Test name
Test status
Simulation time 29399544 ps
CPU time 1.45 seconds
Started Jun 30 05:24:33 PM PDT 24
Finished Jun 30 05:24:35 PM PDT 24
Peak memory 226028 kb
Host smart-df6242f4-6424-49be-9560-05d11aabd8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294436706 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2294436706
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3495798250
Short name T442
Test name
Test status
Simulation time 82733335 ps
CPU time 1.21 seconds
Started Jun 30 05:24:31 PM PDT 24
Finished Jun 30 05:24:32 PM PDT 24
Peak memory 220284 kb
Host smart-13cde36d-44ca-4839-9732-fd7c51a3929f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495798250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3495798250
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.4016392653
Short name T985
Test name
Test status
Simulation time 75673381 ps
CPU time 1.29 seconds
Started Jun 30 05:24:32 PM PDT 24
Finished Jun 30 05:24:34 PM PDT 24
Peak memory 219536 kb
Host smart-aa2b5852-c337-45aa-b03c-bc604e53df01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016392653 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.4016392653
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.50841425
Short name T120
Test name
Test status
Simulation time 28156556 ps
CPU time 1.35 seconds
Started Jun 30 05:24:38 PM PDT 24
Finished Jun 30 05:24:41 PM PDT 24
Peak memory 229876 kb
Host smart-15d5f05a-bc21-4763-8b3b-1784a7c3a45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50841425 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.50841425
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.3901220410
Short name T834
Test name
Test status
Simulation time 34569248 ps
CPU time 1.45 seconds
Started Jun 30 05:24:33 PM PDT 24
Finished Jun 30 05:24:35 PM PDT 24
Peak memory 218924 kb
Host smart-04505b50-7230-4c82-b177-ebdc74be1b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901220410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3901220410
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.798472511
Short name T596
Test name
Test status
Simulation time 167150897 ps
CPU time 1.21 seconds
Started Jun 30 05:22:15 PM PDT 24
Finished Jun 30 05:22:16 PM PDT 24
Peak memory 220036 kb
Host smart-818720ab-0ab1-4882-8ade-854d67dda195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798472511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.798472511
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1167420927
Short name T902
Test name
Test status
Simulation time 54194737 ps
CPU time 0.95 seconds
Started Jun 30 05:22:22 PM PDT 24
Finished Jun 30 05:22:24 PM PDT 24
Peak memory 215436 kb
Host smart-408dd554-76d6-4d08-afa2-7d934db07542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167420927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1167420927
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2247342096
Short name T847
Test name
Test status
Simulation time 24211981 ps
CPU time 0.84 seconds
Started Jun 30 05:22:15 PM PDT 24
Finished Jun 30 05:22:16 PM PDT 24
Peak memory 215720 kb
Host smart-593a3ab5-a3da-4298-990c-c85162efc39e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247342096 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2247342096
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1035568587
Short name T449
Test name
Test status
Simulation time 65975863 ps
CPU time 1.3 seconds
Started Jun 30 05:22:20 PM PDT 24
Finished Jun 30 05:22:22 PM PDT 24
Peak memory 217388 kb
Host smart-4a87c46d-7d1c-4931-9daf-b76e0822528f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035568587 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1035568587
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2141433275
Short name T150
Test name
Test status
Simulation time 19411369 ps
CPU time 1.01 seconds
Started Jun 30 05:22:13 PM PDT 24
Finished Jun 30 05:22:14 PM PDT 24
Peak memory 218636 kb
Host smart-4792d6b0-66ef-4044-b318-c6eecaf1af81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141433275 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2141433275
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1727827907
Short name T728
Test name
Test status
Simulation time 69734955 ps
CPU time 1.2 seconds
Started Jun 30 05:22:14 PM PDT 24
Finished Jun 30 05:22:16 PM PDT 24
Peak memory 219028 kb
Host smart-34f17f97-0b42-450c-84d6-2959296860b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727827907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1727827907
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.4041322502
Short name T781
Test name
Test status
Simulation time 24396211 ps
CPU time 1.14 seconds
Started Jun 30 05:22:14 PM PDT 24
Finished Jun 30 05:22:15 PM PDT 24
Peak memory 224268 kb
Host smart-dd7d63d7-818b-408e-b2db-d8186a1dd11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041322502 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.4041322502
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2119368483
Short name T24
Test name
Test status
Simulation time 16643970 ps
CPU time 1.04 seconds
Started Jun 30 05:22:17 PM PDT 24
Finished Jun 30 05:22:18 PM PDT 24
Peak memory 207360 kb
Host smart-34d5d269-6724-4856-81d7-aea3deaf6cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119368483 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2119368483
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1322806033
Short name T885
Test name
Test status
Simulation time 42372281 ps
CPU time 0.92 seconds
Started Jun 30 05:22:14 PM PDT 24
Finished Jun 30 05:22:15 PM PDT 24
Peak memory 215624 kb
Host smart-2544c316-c659-4ee8-96b8-276664da91a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322806033 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1322806033
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3249507640
Short name T584
Test name
Test status
Simulation time 44236408 ps
CPU time 1.5 seconds
Started Jun 30 05:22:13 PM PDT 24
Finished Jun 30 05:22:14 PM PDT 24
Peak memory 215632 kb
Host smart-e0695460-fb81-450e-88c2-5ded99ebb699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249507640 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3249507640
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2510548975
Short name T409
Test name
Test status
Simulation time 120385448796 ps
CPU time 817.39 seconds
Started Jun 30 05:22:13 PM PDT 24
Finished Jun 30 05:35:52 PM PDT 24
Peak memory 221552 kb
Host smart-f5b54c85-804b-4bf8-9d73-a29403899b25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510548975 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2510548975
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.1217996233
Short name T479
Test name
Test status
Simulation time 103099137 ps
CPU time 1.13 seconds
Started Jun 30 05:24:39 PM PDT 24
Finished Jun 30 05:24:42 PM PDT 24
Peak memory 220072 kb
Host smart-786f53ec-43fd-4c9a-b869-9f69e95af32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217996233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.1217996233
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.222201065
Short name T501
Test name
Test status
Simulation time 29974556 ps
CPU time 1.4 seconds
Started Jun 30 05:24:39 PM PDT 24
Finished Jun 30 05:24:42 PM PDT 24
Peak memory 225832 kb
Host smart-4b840989-bec0-407c-b72c-0db906fef3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222201065 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.222201065
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3266191592
Short name T473
Test name
Test status
Simulation time 53587504 ps
CPU time 1.22 seconds
Started Jun 30 05:24:40 PM PDT 24
Finished Jun 30 05:24:43 PM PDT 24
Peak memory 220196 kb
Host smart-82594423-867e-4933-a38b-80cb60096d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266191592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3266191592
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2919931979
Short name T704
Test name
Test status
Simulation time 73111957 ps
CPU time 1.17 seconds
Started Jun 30 05:24:40 PM PDT 24
Finished Jun 30 05:24:42 PM PDT 24
Peak memory 219956 kb
Host smart-f760f666-67d6-4732-9177-2fe0a017a608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919931979 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2919931979
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.4138954238
Short name T713
Test name
Test status
Simulation time 20228400 ps
CPU time 1.12 seconds
Started Jun 30 05:24:41 PM PDT 24
Finished Jun 30 05:24:44 PM PDT 24
Peak memory 219780 kb
Host smart-fa61858b-6d08-4fad-a830-2c65b678b6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138954238 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.4138954238
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2596913822
Short name T606
Test name
Test status
Simulation time 52260629 ps
CPU time 1.34 seconds
Started Jun 30 05:24:41 PM PDT 24
Finished Jun 30 05:24:44 PM PDT 24
Peak memory 217732 kb
Host smart-fb426bf2-f090-426a-a2b0-457a3057619f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596913822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2596913822
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.2437951962
Short name T811
Test name
Test status
Simulation time 101633222 ps
CPU time 1.06 seconds
Started Jun 30 05:24:41 PM PDT 24
Finished Jun 30 05:24:44 PM PDT 24
Peak memory 215944 kb
Host smart-bd1a3659-2ddf-4455-b347-3463c429b5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437951962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.2437951962
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_genbits.3120343802
Short name T757
Test name
Test status
Simulation time 65811210 ps
CPU time 1.12 seconds
Started Jun 30 05:24:40 PM PDT 24
Finished Jun 30 05:24:42 PM PDT 24
Peak memory 217856 kb
Host smart-0dd64fe2-5d33-4dcc-af54-ccf08074a8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120343802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3120343802
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.406442054
Short name T615
Test name
Test status
Simulation time 155392095 ps
CPU time 1.16 seconds
Started Jun 30 05:24:38 PM PDT 24
Finished Jun 30 05:24:40 PM PDT 24
Peak memory 220488 kb
Host smart-fc91361f-1fff-4f6c-9a08-525156b1ccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406442054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.406442054
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.901256090
Short name T402
Test name
Test status
Simulation time 27014091 ps
CPU time 0.97 seconds
Started Jun 30 05:24:38 PM PDT 24
Finished Jun 30 05:24:41 PM PDT 24
Peak memory 224056 kb
Host smart-56f1596c-9cfc-47eb-b486-56418aa61194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901256090 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.901256090
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3640249595
Short name T342
Test name
Test status
Simulation time 46154926 ps
CPU time 1.26 seconds
Started Jun 30 05:24:40 PM PDT 24
Finished Jun 30 05:24:42 PM PDT 24
Peak memory 217572 kb
Host smart-49a88c3c-14ae-4cf2-a05b-737939cb2f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640249595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3640249595
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.3423029739
Short name T169
Test name
Test status
Simulation time 23169400 ps
CPU time 1.18 seconds
Started Jun 30 05:24:37 PM PDT 24
Finished Jun 30 05:24:39 PM PDT 24
Peak memory 218884 kb
Host smart-88d965b7-8253-4f54-8938-bf1e6cae572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423029739 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.3423029739
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.3049512460
Short name T201
Test name
Test status
Simulation time 58735655 ps
CPU time 0.93 seconds
Started Jun 30 05:24:39 PM PDT 24
Finished Jun 30 05:24:42 PM PDT 24
Peak memory 229560 kb
Host smart-38713bbb-fc34-460f-8f99-71b6d6aab19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049512460 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3049512460
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2282099685
Short name T13
Test name
Test status
Simulation time 80603677 ps
CPU time 1.31 seconds
Started Jun 30 05:24:38 PM PDT 24
Finished Jun 30 05:24:39 PM PDT 24
Peak memory 219708 kb
Host smart-dab84238-998f-4b7d-b2d2-1d991d1ed5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282099685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2282099685
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.1276999666
Short name T855
Test name
Test status
Simulation time 71818686 ps
CPU time 1.15 seconds
Started Jun 30 05:24:41 PM PDT 24
Finished Jun 30 05:24:44 PM PDT 24
Peak memory 219884 kb
Host smart-a39c7434-4a5f-40fd-9620-8217138d31d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276999666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.1276999666
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.1536326439
Short name T15
Test name
Test status
Simulation time 33212652 ps
CPU time 1 seconds
Started Jun 30 05:24:39 PM PDT 24
Finished Jun 30 05:24:42 PM PDT 24
Peak memory 224040 kb
Host smart-a99273a8-1e27-4f66-89ae-23143eed8ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536326439 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1536326439
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3729806915
Short name T645
Test name
Test status
Simulation time 190588007 ps
CPU time 1.23 seconds
Started Jun 30 05:24:40 PM PDT 24
Finished Jun 30 05:24:42 PM PDT 24
Peak memory 217528 kb
Host smart-b37d4d78-8b58-4ea0-97e0-e13fef73b46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729806915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3729806915
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.754958042
Short name T669
Test name
Test status
Simulation time 48544392 ps
CPU time 1.29 seconds
Started Jun 30 05:24:41 PM PDT 24
Finished Jun 30 05:24:44 PM PDT 24
Peak memory 220884 kb
Host smart-af152e83-1d75-422f-b881-d70ef81cef3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754958042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.754958042
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.1954072302
Short name T179
Test name
Test status
Simulation time 18324367 ps
CPU time 1.07 seconds
Started Jun 30 05:24:39 PM PDT 24
Finished Jun 30 05:24:41 PM PDT 24
Peak memory 218772 kb
Host smart-6012d6a9-0428-4989-9351-c559e6fa4e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954072302 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1954072302
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2575305651
Short name T303
Test name
Test status
Simulation time 44728951 ps
CPU time 1.47 seconds
Started Jun 30 05:24:39 PM PDT 24
Finished Jun 30 05:24:42 PM PDT 24
Peak memory 220356 kb
Host smart-7504eab3-f858-465c-b942-e48f482569c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575305651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2575305651
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.2195065071
Short name T754
Test name
Test status
Simulation time 28331679 ps
CPU time 1.23 seconds
Started Jun 30 05:24:40 PM PDT 24
Finished Jun 30 05:24:42 PM PDT 24
Peak memory 219956 kb
Host smart-1670ba58-c432-478d-ba33-5af5d25d1f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195065071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.2195065071
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.2122751445
Short name T967
Test name
Test status
Simulation time 23791235 ps
CPU time 1.18 seconds
Started Jun 30 05:24:38 PM PDT 24
Finished Jun 30 05:24:40 PM PDT 24
Peak memory 220028 kb
Host smart-cc9085f8-92f5-4525-aa23-db0ef615cc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122751445 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2122751445
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.293278433
Short name T961
Test name
Test status
Simulation time 42271055 ps
CPU time 1.57 seconds
Started Jun 30 05:24:40 PM PDT 24
Finished Jun 30 05:24:43 PM PDT 24
Peak memory 217696 kb
Host smart-efc1f7f1-62f4-4807-9e27-dc9588918933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293278433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.293278433
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.3316875233
Short name T160
Test name
Test status
Simulation time 29428641 ps
CPU time 0.85 seconds
Started Jun 30 05:24:38 PM PDT 24
Finished Jun 30 05:24:41 PM PDT 24
Peak memory 218592 kb
Host smart-b0b417bb-092f-448e-b095-5c6abf4be3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316875233 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3316875233
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1854051839
Short name T79
Test name
Test status
Simulation time 23541759 ps
CPU time 1.22 seconds
Started Jun 30 05:24:40 PM PDT 24
Finished Jun 30 05:24:42 PM PDT 24
Peak memory 217500 kb
Host smart-fc19c394-fdbb-4895-84e4-8af6aa600ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854051839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1854051839
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.3299635966
Short name T539
Test name
Test status
Simulation time 45232223 ps
CPU time 1.12 seconds
Started Jun 30 05:24:40 PM PDT 24
Finished Jun 30 05:24:43 PM PDT 24
Peak memory 219008 kb
Host smart-9b430492-2760-42ba-906b-1c706d7907ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299635966 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.3299635966
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.1687377033
Short name T448
Test name
Test status
Simulation time 18257784 ps
CPU time 1.05 seconds
Started Jun 30 05:24:37 PM PDT 24
Finished Jun 30 05:24:38 PM PDT 24
Peak memory 218684 kb
Host smart-bfdfb5e5-18fe-4bda-a94c-bdd0135f8dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687377033 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1687377033
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3202289287
Short name T900
Test name
Test status
Simulation time 198014839 ps
CPU time 1.41 seconds
Started Jun 30 05:24:39 PM PDT 24
Finished Jun 30 05:24:42 PM PDT 24
Peak memory 217948 kb
Host smart-e45d10f1-6b8d-4fb3-920b-2fc4b47a117d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202289287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3202289287
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2114725919
Short name T118
Test name
Test status
Simulation time 32662482 ps
CPU time 1.37 seconds
Started Jun 30 05:22:20 PM PDT 24
Finished Jun 30 05:22:21 PM PDT 24
Peak memory 216012 kb
Host smart-ebc93de7-f15c-449b-a225-f2b9196f1f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114725919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2114725919
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3582669797
Short name T514
Test name
Test status
Simulation time 44454305 ps
CPU time 0.85 seconds
Started Jun 30 05:22:21 PM PDT 24
Finished Jun 30 05:22:23 PM PDT 24
Peak memory 215424 kb
Host smart-cd11fa5a-583d-47b5-b9e8-7b0450a32f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582669797 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3582669797
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2315531193
Short name T197
Test name
Test status
Simulation time 11584241 ps
CPU time 0.9 seconds
Started Jun 30 05:22:21 PM PDT 24
Finished Jun 30 05:22:23 PM PDT 24
Peak memory 216504 kb
Host smart-5854bc8f-8225-47a0-ab48-011a6291ac0c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315531193 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2315531193
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3430243848
Short name T933
Test name
Test status
Simulation time 57521270 ps
CPU time 1.12 seconds
Started Jun 30 05:22:20 PM PDT 24
Finished Jun 30 05:22:22 PM PDT 24
Peak memory 217244 kb
Host smart-29fe4756-6795-4e9e-af5c-ccf0d1a7ba6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430243848 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3430243848
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2317891021
Short name T184
Test name
Test status
Simulation time 20138421 ps
CPU time 1.2 seconds
Started Jun 30 05:22:26 PM PDT 24
Finished Jun 30 05:22:28 PM PDT 24
Peak memory 229784 kb
Host smart-6609bdc5-5691-4255-88da-e82dc122daee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317891021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2317891021
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1512448586
Short name T225
Test name
Test status
Simulation time 38390573 ps
CPU time 1.44 seconds
Started Jun 30 05:22:20 PM PDT 24
Finished Jun 30 05:22:22 PM PDT 24
Peak memory 219936 kb
Host smart-261f2b57-06d2-4039-b7ef-ce6dccd5121c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512448586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1512448586
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3671742214
Short name T891
Test name
Test status
Simulation time 22581762 ps
CPU time 1.16 seconds
Started Jun 30 05:22:20 PM PDT 24
Finished Jun 30 05:22:22 PM PDT 24
Peak memory 215856 kb
Host smart-7732f893-9322-4efc-9a29-b3359d3610fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671742214 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3671742214
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.70284941
Short name T929
Test name
Test status
Simulation time 16455999 ps
CPU time 1 seconds
Started Jun 30 05:22:25 PM PDT 24
Finished Jun 30 05:22:26 PM PDT 24
Peak memory 207360 kb
Host smart-b5eca1bb-5197-4d01-bb2d-79e64c136858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70284941 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.70284941
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.608211283
Short name T973
Test name
Test status
Simulation time 38697851 ps
CPU time 0.94 seconds
Started Jun 30 05:22:20 PM PDT 24
Finished Jun 30 05:22:21 PM PDT 24
Peak memory 215608 kb
Host smart-8e8f5b12-f3e0-4dd4-ad43-de95bff275dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608211283 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.608211283
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2571170723
Short name T337
Test name
Test status
Simulation time 929075764 ps
CPU time 4.2 seconds
Started Jun 30 05:22:23 PM PDT 24
Finished Jun 30 05:22:28 PM PDT 24
Peak memory 215612 kb
Host smart-30bdae3e-2bba-49f4-b0d8-8dd8b6718aed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571170723 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2571170723
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.108253034
Short name T368
Test name
Test status
Simulation time 143847086651 ps
CPU time 932.38 seconds
Started Jun 30 05:22:23 PM PDT 24
Finished Jun 30 05:37:55 PM PDT 24
Peak memory 223920 kb
Host smart-457bc31d-10db-4f1f-a916-dc526afa7b7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108253034 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.108253034
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.1245903777
Short name T832
Test name
Test status
Simulation time 76543768 ps
CPU time 1.18 seconds
Started Jun 30 05:24:39 PM PDT 24
Finished Jun 30 05:24:42 PM PDT 24
Peak memory 220352 kb
Host smart-e69a23a4-22a3-4660-b23e-27861c128eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245903777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.1245903777
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.4248589702
Short name T38
Test name
Test status
Simulation time 28581165 ps
CPU time 0.86 seconds
Started Jun 30 05:24:46 PM PDT 24
Finished Jun 30 05:24:48 PM PDT 24
Peak memory 218344 kb
Host smart-4b13d4cc-4dd0-4a9e-8320-083e539caab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248589702 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.4248589702
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1276273536
Short name T705
Test name
Test status
Simulation time 42430846 ps
CPU time 1.5 seconds
Started Jun 30 05:24:41 PM PDT 24
Finished Jun 30 05:24:44 PM PDT 24
Peak memory 218744 kb
Host smart-edddcac7-1c65-4c6d-80c7-aa7cdda11cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276273536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1276273536
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1938798329
Short name T835
Test name
Test status
Simulation time 21830081 ps
CPU time 1.15 seconds
Started Jun 30 05:24:45 PM PDT 24
Finished Jun 30 05:24:46 PM PDT 24
Peak memory 220088 kb
Host smart-602aaa05-c9cc-46e8-b3cd-5730b25080e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938798329 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1938798329
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.2931287048
Short name T582
Test name
Test status
Simulation time 18046857 ps
CPU time 1.17 seconds
Started Jun 30 05:24:47 PM PDT 24
Finished Jun 30 05:24:49 PM PDT 24
Peak memory 224200 kb
Host smart-f94d51ef-26de-4646-ba67-dddb7f26a1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931287048 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2931287048
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1727797434
Short name T675
Test name
Test status
Simulation time 176536349 ps
CPU time 2.49 seconds
Started Jun 30 05:24:50 PM PDT 24
Finished Jun 30 05:24:53 PM PDT 24
Peak memory 220356 kb
Host smart-38dbb6fd-854e-4081-bb4b-6dccad296b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727797434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1727797434
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.283647402
Short name T131
Test name
Test status
Simulation time 34459250 ps
CPU time 1.06 seconds
Started Jun 30 05:24:46 PM PDT 24
Finished Jun 30 05:24:48 PM PDT 24
Peak memory 218968 kb
Host smart-77cb06c7-8704-4907-91c0-2ca5dd71bebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283647402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.283647402
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.1717870107
Short name T183
Test name
Test status
Simulation time 27591972 ps
CPU time 0.87 seconds
Started Jun 30 05:24:47 PM PDT 24
Finished Jun 30 05:24:48 PM PDT 24
Peak memory 219416 kb
Host smart-b4c0d7a9-d3ab-410d-a201-a6b780c87475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717870107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1717870107
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1330961974
Short name T591
Test name
Test status
Simulation time 53366754 ps
CPU time 1.19 seconds
Started Jun 30 05:24:46 PM PDT 24
Finished Jun 30 05:24:48 PM PDT 24
Peak memory 219024 kb
Host smart-81be7cca-88f5-40cc-86c2-6e9c7878a878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330961974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1330961974
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.2800130583
Short name T166
Test name
Test status
Simulation time 58274385 ps
CPU time 1.27 seconds
Started Jun 30 05:24:50 PM PDT 24
Finished Jun 30 05:24:52 PM PDT 24
Peak memory 220096 kb
Host smart-73de0369-b397-4a13-ae14-f7e400fc15c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800130583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.2800130583
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_genbits.899496424
Short name T308
Test name
Test status
Simulation time 81030337 ps
CPU time 1.16 seconds
Started Jun 30 05:24:45 PM PDT 24
Finished Jun 30 05:24:46 PM PDT 24
Peak memory 220164 kb
Host smart-ddcb725f-4d99-4f0c-8783-40777b755ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899496424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.899496424
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.2445666902
Short name T165
Test name
Test status
Simulation time 70702758 ps
CPU time 1.03 seconds
Started Jun 30 05:24:45 PM PDT 24
Finished Jun 30 05:24:47 PM PDT 24
Peak memory 220164 kb
Host smart-57272593-396c-4203-ab22-4404f46845a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445666902 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2445666902
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.799755324
Short name T919
Test name
Test status
Simulation time 25539505 ps
CPU time 1.23 seconds
Started Jun 30 05:24:50 PM PDT 24
Finished Jun 30 05:24:52 PM PDT 24
Peak memory 221288 kb
Host smart-4c4d8629-20a6-48a2-8f5f-6a1068887934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799755324 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.799755324
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.365797376
Short name T685
Test name
Test status
Simulation time 25009273 ps
CPU time 1.18 seconds
Started Jun 30 05:24:45 PM PDT 24
Finished Jun 30 05:24:47 PM PDT 24
Peak memory 217912 kb
Host smart-2676076d-2423-4f6a-b4e3-5a3ae6b2efae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365797376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.365797376
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.3521304585
Short name T607
Test name
Test status
Simulation time 25768309 ps
CPU time 1.21 seconds
Started Jun 30 05:24:50 PM PDT 24
Finished Jun 30 05:24:52 PM PDT 24
Peak memory 219096 kb
Host smart-e4dbef9a-88fc-4232-ba63-ed3a978da40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521304585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.3521304585
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.611649489
Short name T83
Test name
Test status
Simulation time 30555453 ps
CPU time 1.29 seconds
Started Jun 30 05:24:46 PM PDT 24
Finished Jun 30 05:24:48 PM PDT 24
Peak memory 219944 kb
Host smart-eded6868-6589-45bf-987b-4e146612d3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611649489 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.611649489
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.128386600
Short name T648
Test name
Test status
Simulation time 35554031 ps
CPU time 1.44 seconds
Started Jun 30 05:24:46 PM PDT 24
Finished Jun 30 05:24:49 PM PDT 24
Peak memory 217784 kb
Host smart-58410cd1-f3e5-48fe-93e2-05b0bd2f1d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128386600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.128386600
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.1444958544
Short name T641
Test name
Test status
Simulation time 206969885 ps
CPU time 1.12 seconds
Started Jun 30 05:24:45 PM PDT 24
Finished Jun 30 05:24:47 PM PDT 24
Peak memory 219696 kb
Host smart-b0aee9b6-1657-4df7-bb2b-eb07a00b9a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444958544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1444958544
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2968489778
Short name T565
Test name
Test status
Simulation time 17814918 ps
CPU time 1.06 seconds
Started Jun 30 05:24:49 PM PDT 24
Finished Jun 30 05:24:50 PM PDT 24
Peak memory 218648 kb
Host smart-ad0df702-70a4-4e77-8c5a-6c7f97818133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968489778 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2968489778
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3285374714
Short name T696
Test name
Test status
Simulation time 362817875 ps
CPU time 2.22 seconds
Started Jun 30 05:24:50 PM PDT 24
Finished Jun 30 05:24:53 PM PDT 24
Peak memory 219912 kb
Host smart-9763efdc-a302-4e8c-825f-6e5ddf9bfca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285374714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3285374714
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.3147384725
Short name T147
Test name
Test status
Simulation time 22106463 ps
CPU time 1.15 seconds
Started Jun 30 05:24:47 PM PDT 24
Finished Jun 30 05:24:49 PM PDT 24
Peak memory 218964 kb
Host smart-90a85579-a687-4234-9e52-dab2580093fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147384725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.3147384725
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.666488442
Short name T897
Test name
Test status
Simulation time 53140127 ps
CPU time 1.2 seconds
Started Jun 30 05:24:46 PM PDT 24
Finished Jun 30 05:24:48 PM PDT 24
Peak memory 229580 kb
Host smart-49a2d9cc-d1cb-4a68-b65f-1e21530b7adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666488442 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.666488442
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2703979511
Short name T799
Test name
Test status
Simulation time 59869054 ps
CPU time 1.03 seconds
Started Jun 30 05:24:48 PM PDT 24
Finished Jun 30 05:24:50 PM PDT 24
Peak memory 217512 kb
Host smart-8cdc56e7-236e-47e4-82ce-30c246912928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703979511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2703979511
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.706132923
Short name T440
Test name
Test status
Simulation time 25303086 ps
CPU time 1.22 seconds
Started Jun 30 05:24:47 PM PDT 24
Finished Jun 30 05:24:49 PM PDT 24
Peak memory 221148 kb
Host smart-bfc6b6d5-77a7-46fb-9d35-d63c42395e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706132923 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.706132923
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.1807291394
Short name T488
Test name
Test status
Simulation time 19413266 ps
CPU time 1.19 seconds
Started Jun 30 05:24:49 PM PDT 24
Finished Jun 30 05:24:50 PM PDT 24
Peak memory 224180 kb
Host smart-1c615404-f318-4e94-8724-05b5c50781b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807291394 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1807291394
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.39299747
Short name T751
Test name
Test status
Simulation time 90888882 ps
CPU time 1.28 seconds
Started Jun 30 05:24:45 PM PDT 24
Finished Jun 30 05:24:47 PM PDT 24
Peak memory 217540 kb
Host smart-1f515907-1124-46e6-bfa7-eaf90b5bba2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39299747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.39299747
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.4002449931
Short name T121
Test name
Test status
Simulation time 103636947 ps
CPU time 1.27 seconds
Started Jun 30 05:24:45 PM PDT 24
Finished Jun 30 05:24:47 PM PDT 24
Peak memory 218844 kb
Host smart-049f8b2b-a691-488d-9be8-c19e0e4da1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002449931 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.4002449931
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.3451849047
Short name T59
Test name
Test status
Simulation time 21077732 ps
CPU time 1.26 seconds
Started Jun 30 05:24:46 PM PDT 24
Finished Jun 30 05:24:49 PM PDT 24
Peak memory 229932 kb
Host smart-870a5dab-e7e4-42f9-9ac8-c3141e8ac2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451849047 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3451849047
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1122052268
Short name T815
Test name
Test status
Simulation time 84557826 ps
CPU time 1.3 seconds
Started Jun 30 05:24:46 PM PDT 24
Finished Jun 30 05:24:49 PM PDT 24
Peak memory 219260 kb
Host smart-fcfcc15c-3846-424a-b0cf-6a44781b35d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122052268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1122052268
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1810573366
Short name T952
Test name
Test status
Simulation time 35201494 ps
CPU time 1.17 seconds
Started Jun 30 05:22:21 PM PDT 24
Finished Jun 30 05:22:22 PM PDT 24
Peak memory 220060 kb
Host smart-6fca905e-f925-4b6d-b502-5501ad5ca37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810573366 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1810573366
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1599833094
Short name T787
Test name
Test status
Simulation time 65879305 ps
CPU time 0.91 seconds
Started Jun 30 05:22:24 PM PDT 24
Finished Jun 30 05:22:25 PM PDT 24
Peak memory 207008 kb
Host smart-281bda93-c670-43a6-b028-b474c36328a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599833094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1599833094
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2013493691
Short name T510
Test name
Test status
Simulation time 13409623 ps
CPU time 0.94 seconds
Started Jun 30 05:22:23 PM PDT 24
Finished Jun 30 05:22:25 PM PDT 24
Peak memory 216420 kb
Host smart-400ec4e8-9a61-4cbc-aa90-f27f5c7d30df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013493691 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2013493691
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1495119794
Short name T124
Test name
Test status
Simulation time 25769419 ps
CPU time 1.11 seconds
Started Jun 30 05:22:20 PM PDT 24
Finished Jun 30 05:22:22 PM PDT 24
Peak memory 218816 kb
Host smart-a7e1460c-9a5b-4f9e-a15b-831e1cd9ce58
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495119794 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1495119794
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1954657836
Short name T173
Test name
Test status
Simulation time 19259077 ps
CPU time 1.08 seconds
Started Jun 30 05:22:23 PM PDT 24
Finished Jun 30 05:22:25 PM PDT 24
Peak memory 218672 kb
Host smart-d4a15bf8-a342-4197-9ecd-35488183e29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954657836 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1954657836
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1469112087
Short name T458
Test name
Test status
Simulation time 104745579 ps
CPU time 1.76 seconds
Started Jun 30 05:22:21 PM PDT 24
Finished Jun 30 05:22:23 PM PDT 24
Peak memory 219088 kb
Host smart-641dbbaf-3407-4cd8-93f8-776dec3448aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469112087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1469112087
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1405670244
Short name T53
Test name
Test status
Simulation time 29430505 ps
CPU time 0.89 seconds
Started Jun 30 05:22:20 PM PDT 24
Finished Jun 30 05:22:21 PM PDT 24
Peak memory 215848 kb
Host smart-34fceca0-b4f5-4136-bc3d-8572a53b3aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405670244 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1405670244
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3005984896
Short name T25
Test name
Test status
Simulation time 117085503 ps
CPU time 0.97 seconds
Started Jun 30 05:22:21 PM PDT 24
Finished Jun 30 05:22:23 PM PDT 24
Peak memory 207400 kb
Host smart-6c4084ab-02dc-47d2-96c7-718e37517daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005984896 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3005984896
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1918531974
Short name T330
Test name
Test status
Simulation time 19418367 ps
CPU time 1.06 seconds
Started Jun 30 05:22:21 PM PDT 24
Finished Jun 30 05:22:23 PM PDT 24
Peak memory 215600 kb
Host smart-ced41f8f-83a2-4a9f-9fff-9d1ff8b1704a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918531974 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1918531974
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2432562474
Short name T887
Test name
Test status
Simulation time 167468722 ps
CPU time 3.75 seconds
Started Jun 30 05:22:21 PM PDT 24
Finished Jun 30 05:22:26 PM PDT 24
Peak memory 220484 kb
Host smart-ef7af86b-04b9-4070-b8ae-99308dc007cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432562474 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2432562474
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2655782026
Short name T221
Test name
Test status
Simulation time 180368434143 ps
CPU time 533.66 seconds
Started Jun 30 05:22:22 PM PDT 24
Finished Jun 30 05:31:16 PM PDT 24
Peak memory 223884 kb
Host smart-5fa04850-41f0-4af1-8e3d-96e3b81d1b61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655782026 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2655782026
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.2341483924
Short name T857
Test name
Test status
Simulation time 35586155 ps
CPU time 1.16 seconds
Started Jun 30 05:24:48 PM PDT 24
Finished Jun 30 05:24:49 PM PDT 24
Peak memory 220144 kb
Host smart-eddd4c47-7841-4d17-bee9-4c703858e9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341483924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.2341483924
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.2543162392
Short name T57
Test name
Test status
Simulation time 61701332 ps
CPU time 1.02 seconds
Started Jun 30 05:24:50 PM PDT 24
Finished Jun 30 05:24:52 PM PDT 24
Peak memory 223960 kb
Host smart-951ac507-8d3b-4fe7-8590-a19d9c604c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543162392 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2543162392
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.4092384502
Short name T719
Test name
Test status
Simulation time 35251532 ps
CPU time 1.02 seconds
Started Jun 30 05:24:49 PM PDT 24
Finished Jun 30 05:24:50 PM PDT 24
Peak memory 217584 kb
Host smart-7f444e72-3aaf-4c84-9a9b-59e74a5131bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092384502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.4092384502
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.1005888217
Short name T472
Test name
Test status
Simulation time 89304711 ps
CPU time 1.12 seconds
Started Jun 30 05:24:53 PM PDT 24
Finished Jun 30 05:24:54 PM PDT 24
Peak memory 218660 kb
Host smart-4c38c5c6-6b87-4344-95a0-4783fcecbeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005888217 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.1005888217
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.321989324
Short name T185
Test name
Test status
Simulation time 107522979 ps
CPU time 0.87 seconds
Started Jun 30 05:24:53 PM PDT 24
Finished Jun 30 05:24:54 PM PDT 24
Peak memory 219376 kb
Host smart-89a47fa5-f2a8-4d42-b430-5a96ae69852c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321989324 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.321989324
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3491712583
Short name T309
Test name
Test status
Simulation time 57243331 ps
CPU time 1.1 seconds
Started Jun 30 05:24:54 PM PDT 24
Finished Jun 30 05:24:56 PM PDT 24
Peak memory 217596 kb
Host smart-84714fb4-da32-4494-8c12-fbc0fbe6421c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491712583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3491712583
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.809454169
Short name T747
Test name
Test status
Simulation time 89527826 ps
CPU time 1.21 seconds
Started Jun 30 05:24:54 PM PDT 24
Finished Jun 30 05:24:56 PM PDT 24
Peak memory 219332 kb
Host smart-ce8d5317-a9b0-40e7-b477-c8f9a695189a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809454169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.809454169
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.735232100
Short name T7
Test name
Test status
Simulation time 42175059 ps
CPU time 0.97 seconds
Started Jun 30 05:24:54 PM PDT 24
Finished Jun 30 05:24:56 PM PDT 24
Peak memory 224172 kb
Host smart-a938d539-6ddf-456f-84d1-ace9463f0233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735232100 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.735232100
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.927367903
Short name T450
Test name
Test status
Simulation time 90202917 ps
CPU time 1.27 seconds
Started Jun 30 05:24:52 PM PDT 24
Finished Jun 30 05:24:53 PM PDT 24
Peak memory 220292 kb
Host smart-1dfab8b2-5872-4713-8a41-2ed6cd3bd9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927367903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.927367903
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.4103416038
Short name T633
Test name
Test status
Simulation time 78464299 ps
CPU time 1.16 seconds
Started Jun 30 05:24:52 PM PDT 24
Finished Jun 30 05:24:54 PM PDT 24
Peak memory 219900 kb
Host smart-2c557e74-ee80-453f-9461-4f4b801be195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103416038 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.4103416038
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.289531701
Short name T738
Test name
Test status
Simulation time 29823510 ps
CPU time 1.04 seconds
Started Jun 30 05:24:54 PM PDT 24
Finished Jun 30 05:24:56 PM PDT 24
Peak memory 229916 kb
Host smart-8675623e-ec46-4c81-ae23-78ee394ffcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289531701 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.289531701
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1031682802
Short name T932
Test name
Test status
Simulation time 40321782 ps
CPU time 1.76 seconds
Started Jun 30 05:24:51 PM PDT 24
Finished Jun 30 05:24:54 PM PDT 24
Peak memory 220244 kb
Host smart-f2e73fdb-7611-48eb-a5a0-e418eb655957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031682802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1031682802
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1658634170
Short name T76
Test name
Test status
Simulation time 46756884 ps
CPU time 1.27 seconds
Started Jun 30 05:24:53 PM PDT 24
Finished Jun 30 05:24:55 PM PDT 24
Peak memory 219468 kb
Host smart-bd279f5d-14c4-451a-864f-17d60b7db0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658634170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1658634170
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1522294048
Short name T119
Test name
Test status
Simulation time 83658524 ps
CPU time 1.22 seconds
Started Jun 30 05:24:54 PM PDT 24
Finished Jun 30 05:24:56 PM PDT 24
Peak memory 229560 kb
Host smart-bf2e7498-fa7e-4324-9260-70ed76db2f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522294048 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1522294048
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1357642729
Short name T227
Test name
Test status
Simulation time 44129524 ps
CPU time 1.19 seconds
Started Jun 30 05:24:52 PM PDT 24
Finished Jun 30 05:24:54 PM PDT 24
Peak memory 215592 kb
Host smart-991f3edc-0163-4626-9dcc-e61ce2b33334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357642729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1357642729
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.2323012805
Short name T714
Test name
Test status
Simulation time 43408363 ps
CPU time 1.16 seconds
Started Jun 30 05:24:55 PM PDT 24
Finished Jun 30 05:24:57 PM PDT 24
Peak memory 219628 kb
Host smart-e1f63aa7-943c-4171-976b-aad02e51b7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323012805 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.2323012805
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.856601107
Short name T154
Test name
Test status
Simulation time 29534000 ps
CPU time 1.25 seconds
Started Jun 30 05:24:53 PM PDT 24
Finished Jun 30 05:24:55 PM PDT 24
Peak memory 219940 kb
Host smart-0d4e4076-6400-424e-bbe0-e8c2bd6a5830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856601107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.856601107
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3725277278
Short name T954
Test name
Test status
Simulation time 40905288 ps
CPU time 1.07 seconds
Started Jun 30 05:24:52 PM PDT 24
Finished Jun 30 05:24:54 PM PDT 24
Peak memory 217432 kb
Host smart-3ecd4068-dbc0-4e8e-9465-8687082df7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725277278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3725277278
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.2821129598
Short name T796
Test name
Test status
Simulation time 24304470 ps
CPU time 1.17 seconds
Started Jun 30 05:24:54 PM PDT 24
Finished Jun 30 05:24:56 PM PDT 24
Peak memory 218724 kb
Host smart-1587af2a-9907-450c-a437-5f826020972b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821129598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.2821129598
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.1091753674
Short name T151
Test name
Test status
Simulation time 20273250 ps
CPU time 1.12 seconds
Started Jun 30 05:24:54 PM PDT 24
Finished Jun 30 05:24:56 PM PDT 24
Peak memory 218868 kb
Host smart-495e46e1-54a2-4e3e-91ca-576cfc753b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091753674 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1091753674
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.897375007
Short name T482
Test name
Test status
Simulation time 51191098 ps
CPU time 1.18 seconds
Started Jun 30 05:24:53 PM PDT 24
Finished Jun 30 05:24:55 PM PDT 24
Peak memory 217764 kb
Host smart-9ab6c04c-0134-44b4-82c2-53dea921abd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897375007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.897375007
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.220762418
Short name T536
Test name
Test status
Simulation time 88027434 ps
CPU time 1.21 seconds
Started Jun 30 05:25:00 PM PDT 24
Finished Jun 30 05:25:02 PM PDT 24
Peak memory 215972 kb
Host smart-b40fbe7b-197b-4300-981f-7e133f7c5ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220762418 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.220762418
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.3753475824
Short name T178
Test name
Test status
Simulation time 21147928 ps
CPU time 1.11 seconds
Started Jun 30 05:25:01 PM PDT 24
Finished Jun 30 05:25:03 PM PDT 24
Peak memory 218744 kb
Host smart-e99c1055-f53d-4145-ad1e-16279a6e2be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753475824 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3753475824
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1534123427
Short name T441
Test name
Test status
Simulation time 64003719 ps
CPU time 1.64 seconds
Started Jun 30 05:24:54 PM PDT 24
Finished Jun 30 05:24:56 PM PDT 24
Peak memory 218868 kb
Host smart-4fc9bc79-44eb-49c6-9734-b14e3c3e27f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534123427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1534123427
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.673879645
Short name T464
Test name
Test status
Simulation time 107404108 ps
CPU time 1.24 seconds
Started Jun 30 05:24:59 PM PDT 24
Finished Jun 30 05:25:01 PM PDT 24
Peak memory 218840 kb
Host smart-5385755e-4970-4ee5-8ba7-ae2a5e5990d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673879645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.673879645
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.2650213661
Short name T129
Test name
Test status
Simulation time 161937772 ps
CPU time 0.96 seconds
Started Jun 30 05:24:59 PM PDT 24
Finished Jun 30 05:25:01 PM PDT 24
Peak memory 218648 kb
Host smart-063df1c8-0ed2-4459-97a2-a760dbcdfdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650213661 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2650213661
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1827356749
Short name T471
Test name
Test status
Simulation time 36389086 ps
CPU time 1.57 seconds
Started Jun 30 05:25:01 PM PDT 24
Finished Jun 30 05:25:03 PM PDT 24
Peak memory 218864 kb
Host smart-ca344405-d5ba-49ba-8e65-eece8a5f56bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827356749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1827356749
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.1974577393
Short name T559
Test name
Test status
Simulation time 45002149 ps
CPU time 1.3 seconds
Started Jun 30 05:25:01 PM PDT 24
Finished Jun 30 05:25:03 PM PDT 24
Peak memory 219412 kb
Host smart-bebb6c4d-ce19-4a57-af61-0b0074c8089a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974577393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.1974577393
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.2925445642
Short name T104
Test name
Test status
Simulation time 59822213 ps
CPU time 1.22 seconds
Started Jun 30 05:24:59 PM PDT 24
Finished Jun 30 05:25:01 PM PDT 24
Peak memory 229968 kb
Host smart-0e1b4ae4-2dc2-427e-bfaa-cf2913d67e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925445642 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2925445642
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.491465101
Short name T327
Test name
Test status
Simulation time 36526253 ps
CPU time 1.38 seconds
Started Jun 30 05:25:08 PM PDT 24
Finished Jun 30 05:25:10 PM PDT 24
Peak memory 217640 kb
Host smart-5b5fe781-6260-4d3c-8feb-c871935a9358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491465101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.491465101
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%